ELECTRONIC DEVICE, ARRANGEMENT AND PROCEDURE FOR MANUFACTURING AN ELECTRONIC DEVICE

Micro device transfer head

A micro device transfer head and head array are disclosed. In an embodiment, the micro device transfer head includes a base substrate, a mesa structure with sidewalls, an electrode formed over the mesa structure, and a dielectric layer covering the electrode. A voltage can be applied to the micro device transfer head and head array to pick up a micro device from a carrier substrate and release the micro device onto a receiving substrate.

Micro device transfer head

A micro device transfer head and head array are disclosed. In an embodiment, the micro device transfer head includes a base substrate, a mesa structure with sidewalls, an electrode formed over the mesa structure, and a dielectric layer covering the electrode. A voltage can be applied to the micro device transfer head and head array to pick up a micro device from a carrier substrate and release the micro device onto a receiving substrate.

SEMICONDUCTOR DEVICE

A semiconductor device (100) is provided with a BGA substrate (110), a semiconductor chip (101), bumps (106) and an underfill (108) applied around the bumps (106). An interlayer insulating film (104) of the semiconductor chip (101) is composed of a low dielectric constant film. The bumps (106) are composed of a lead-free solder. The underfill (108) is composed of a resin material having an elastic modulus of 150MPa or more but not more than 800MPa, and a linear expansion coefficient of the BGA substrate (110) in a substrate planar direction is less than 14ppm/~C.

Wafer level system packaging method and packaging structure

Semiconductor structure and methods of forming semiconductor constructions

ELECTRONIC POWER MODULE

L'invention concerne un module électronique de puissance, en particulier pour des systèmes de commande de vol électromécaniques. Il présente un premier substrat ayant des pistes conductrices appliquées sur celui-ci, ainsi qu'un composant à semi-conducteur de puissance et au moins un capteur de courant, de même qu'un second substrat, une première carte de circuit imprimé qui est fixée sur le second substrat et une seconde carte de-circuit imprimé qui est agencée au-dessus de la première carte de circuit imprimé, sur la première carte de circuit imprimé, dans lequel au moins un contact à ressort est connecté électriquement de manière ponctuelle à la première carte de circuit imprimé.

반도체 디바이스 및 제조 방법

... 반도체 디바이스 및 제조 방법이 제공된다. 리플로우 가능 물질이 관통 비아와 전기 접속하고, 관통 비아는 봉지재를 통해 연장된다. 보호층이 리플로우 가능 물질 위에 형성된다. 실시예에서, 개구부는 리플로우 가능 물질을 노출하기 위해 보호층 내에 형성된다. 다른 실시예에서, 보호층은 리플로우 가능 물질이 보호층으로부터 멀리 연장되도록 형성된다.

Integrated circuit device having through-silicon via structure and method of manufacturing the same

반도체 장치 및 그 형성방법

... 관통 전극을 갖는 반도체 장치가 제공된다. 상기 반도체 장치의 기판을 관통하는 TSV를 둘러싸는 에어 갭에 의하여 상기 TSV가 형성된 반도체 소자에 인가하는 스트레스가 완화되어, 상기 반도체 소자의 전기적 특성 및 신뢰성이 향상될 수 있다.

핫 스팟 열 관리 특징부를 갖춘 3ＤＩＣ 패키징

... 패키지는 전도성 층을 갖는 기판을 포함하며, 전도성 층은 노출된 부분을 포함한다. 다이 스택은 기판 위에 배치되며, 전도성 층에 전기적으로 접속된다. 고 열전도성 재료가 기판 위에 배치되며 전도성 층의 노출된 부분과 접촉한다. 패키지는 또한, 고 열전도성 재료 위에 있고 고 열전도성 재료와 접촉하는 콘투어 링을 포함한다.

마이크로 소자를 이송하는 방법

... 마이크로 소자 이송 헤드 및 헤드 어레이가 개시된다. 일 실시예에서, 마이크로 소자 이송 헤드는, 베이스 기판, 측벽들을 갖는 메사 구조체, 메사 구조체 위에 형성된 전극, 및 전극을 덮는 유전체 층을 포함한다. 캐리어 기판으로부터 마이크로 소자를 픽업하고 수용 기판 상에 마이크로 소자를 릴리즈하기 위해 마이크로 소자 이송 헤드 및 헤드 어레이에 전압이 인가될 수 있다.

이중 랜드를 갖는 반도체패키지 및 관련된 장치

... 이중 랜드(dual land)를 갖는 반도체패키지를 제공한다. 상기 반도체패키지는 다수의 내부 패드들을 갖는 기판을 구비한다. 반도체 칩이 상기 기판에 부착된다. 상기 반도체 칩은 상기 내부 패드들에 전기적으로 접속된다. 상기 기판에 형성되고 상기 내부 패드들에 전기적으로 접속된 다수의 랜드들을 제공한다. 상기 기판에 형성된 적어도 하나의 우회배선을 제공한다. 상기 우회배선은 제 1 랜드 및 제 2 랜드에 접속된다. 상기 제 1 랜드는 상기 랜드들 중 선택된 하나이고, 상기 제 2 랜드는 상기 랜드들 중 선택된 다른 하나이다. 상기 제 1 랜드 및 상기 제 2 랜드는 상기 랜드들 사이의 평균거리보다 3배 이상 떨어진다.

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

Disclosed is a semiconductor package where a semiconductor chip and a mounting device are packaged together. The semiconductor package according to the embodiment of the present invention includes a semiconductor chip, a mounting block where a first mounting device is mounted on a substrate having a circuit, and a wiring part which electrically connects the semiconductor chip and the mounting block. So, the semiconductor chip can be separated from the substrate having the mounting device. COPYRIGHT KIPO 2016 ...

Method and device for integrated semiconductor wafers

METHOD OF FORMING A PROTECTIVE LAYER ON A MOLD AND THE MOLD HAVING A PROTECTIVE LAYER, CAPABLE OF PREVENTING DAMAGE TO A SUBSTRATE

PURPOSE: A method of forming a protective layer on a mold and the mold having a protective layer is provided to improve the operation life of the molds by prevent the failure or crack of a solder ball which is formed in a cavity. CONSTITUTION: In a method of forming a protective layer on a mold and the mold having a protective layer, a mold substrate(2) having at least one substantially planar surface is formed. The mold substrate has a main body. A mold protective layer is formed on at least one substantially planar surface. A lithographic film is coated on the mold protective layer. A plurality of cavities are etched in the at least substantially planar surface through the mold protective layer. COPYRIGHT KIPO 2011 ...

MULTI-CHIP SEMICONDUCTOR PACKAGE AND A METHOD FOR FORMING THE SAME CAPABLE OF IMPROVING PRODUCTION EFFICIENCY

PURPOSE: A multi-chip semiconductor package and a method for forming the same are provided to reduce a chip crack by using an insulating layer, a protrusion electrode, and an interconnection. CONSTITUTION: A first semiconductor chip(11) having a first protrusion electrode(17) is formed on the upper surface. A second semiconductor chip(21) having a second protrusion electrode(27) is formed on the first semiconductor chip. An insulating layer(8) is formed between the first protrusion electrode and the second protrusion electrode. A groove is formed on the insulating layer. The first protrusion electrode is interconnected with the second protrusion electrode by filling the groove. COPYRIGHT KIPO 2013 ...

Semiconductor packages

Semiconductor packages are provided. One of the semiconductor packages includes a first chip, a second chip and a molding compound. The first chip has at least one first via and a protection layer thereon, and the at least one first via is formed in the protection layer. The second chip has at least one second via thereon. The molding layer encapsulates the first and second chips. The at least one second via is disposed in and contact with the molding layer, and top surfaces of the protection layer, the at least one first via and the at least one second via are substantially coplanar with a top surface of the molding layer.

Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate

A microelectronic package 100 includes a microelectronic element 101 having a memory storage array. Terminals 104 on a surface 110 of a substrate 102 are configured for connection to an external component. Substrate contacts 121 exposed at an opposite surface 108 of the substrate 102 face and are joined to element contacts 111 of the microelectronic element 101. The terminals can include first terminals 104 arranged at positions within first and second sets 114, 124 thereof disposed on respective opposite sides of a theoretical axis 132. Each set of first terminals 104 can be configured to carry address information usable by circuitry within the microelectronic package 100 to determine an addressable memory location in the memory storage array. The signal assignments of the first terminals 104 in the first set 114 can be a mirror image of the signal assignments of the first terminals in the second set 124.

A semiconductor package structure and the method for forming the same

The present invention provides a semiconductor package structure and the method for forming the same. Wherein the semiconductor package structure including a first semiconductor package. The first semiconductor package includes a first redistribution layer (RDL) structure having a first surface and a second surface opposite thereto. A first semiconductor die is disposed on and electrically coupled to the first surface of the first RDL structure. A first molding compound is disposed on the first surface of the first RDL structure and surrounds the first semiconductor die. A plurality of solder balls or conductive pillar structures is disposed in the first molding compound and electrically coupled to the first semiconductor die through the first RDL structure.

Two material high k thermal encapsulant system

Some embodiments relate to an electronic package. The electronic package includes a first die and a second die stacked onto the first die. A first encapsulant is positioned between the first die and the second die. The first encapsulant includes a first material that covers a first volume between the first die and the second die. A second encapsulant is positioned between the first die and the second die. The second encapsulant includes a second material that covers a second volume between the first die and the second die. The first material has a higher thermal conductivity than the second material, and the second material more effectively promotes electrical connections between the first die and the second die as compared to the first material.

A semiconductor package structure

The present invention provides a semiconductor package structure. The structure includes a molding compound having a dicing lane region. A semiconductor die is disposed in the molding compound and surrounded by the dicing lane region. The semiconductor die has a first surface and a second surface opposite thereto. The structure further includes a redistribution layer (RDL) structure disposed on the first surface of the semiconductor die and covering the molding compound. The RDL structure has an opening aligned with the dicing lane region.

Manufacturing method of package-on-package structure

Semiconductor package with in-package compartmental shielding and fabrication method thereof

Stub minimization for multi-die wirebond assemblies with parallel windows

MULTI-CHIP PACKAGE AND INTERPOSER WITH SIGNAL LINE COMPRESSION

A multi-chip package with signal line compression for testing of the multi-chip package. The multi-chip package includes an interposer and two or more integrated circuits attached to the interposer. The interposer includes multiple data signal lines for data communications between the two integrated circuits. The data signal lines are also coupled to one or more test contacts through an interface circuit. The number of test contacts is smaller than the number of signal lines, which allows a large number of signal lines to be tested with a smaller number of test contacts.

CARRIER ULTRA THIN SUBSTRATE

Method of forming ultra thin coreless substrates are described. In an embodiment, the method utilizes a debond layer including high and low adhesion surface areas to the carrier substrate, and cutting through the low adhesion surface areas to remove a build-up structure from the carrier substrate. An electrical short layer may be formed as a part of or on the debond layer to facilitate electrical testing of the build-up structure prior to debonding, and aid in the formation a “known good” substrate on a support substrate.

Semiconductor package and method of manufacturing the same

A semiconductor package including an internal package including at least one semiconductor chip sealed with an internal seal, an external substrate on which the internal package is mounted, and an external seal sealing the internal package is provided. Also provided is a method of manufacturing the semiconductor package including forming an internal package including at least one semiconductor chip sealed with an internal seal, mounting the internal package on an external substrate, and sealing the internal package with an external seal. The internal seal and the external seal have different Young's moduli, for example, a Young's modulus of the internal seal is smaller than a Young's modulus of the external seal. Accordingly, the semiconductor package is less susceptible to warpage and can be handled with relative ease in subsequent semiconductor package processes.

SEMICONDUCTOR MEMORY DEVICE

According to one embodiment, a semiconductor memory device includes a via provided above a substrate, a conductive layer provided on the via, and a via provided on the conductive layer. The via, the conductive layer, and the via are one continuous structure.

NONVOLATILE MEMORY DEVICE, STORAGE DEVICE, AND OPERATING METHOD OF NONVOLATILE MEMORY DEVICE

Each of memory blocks of a nonvolatile memory device includes a memory cell region including first metal pads, first memory cells of a first portion of pillar, and second memory cells of a second portion of the pillar, and a peripheral circuit region including second metal pads, a row decoder, and a page buffer. When performing program operations based on consecutive addresses at a memory block selected from the memory blocks, the nonvolatile memory device sequentially completes first program operations of non-adjacent memory cells not adjacent to a boundary of the first portion and the second portion from among the first and second memory cells and then completes a second program operation of an adjacent memory cell adjacent to the boundary. The peripheral circuit region is vertically connected to the memory cell region by the first metal pads and the second metal pads directly. 1. A nonvolatile memory device comprising:a memory cell array disposed on a substrate, wherein the memory cell array comprises a plurality of memory blocks;a row decoder connected to the memory cell array through word lines; anda page buffer connected to the memory cell array through bit lines,wherein each of the memory blocks comprises a pillar including a first portion disposed on the substrate and a second portion stacked on the first portion,wherein at least a portion of a width of the first portion increases as a distance from the substrate increases, and first conductive materials and first insulating layers surround the first portion and are stacked in turn on the substrate,wherein at least a portion of a width of the second portion increases as a distance from the substrate increases, and second conductive materials and second insulating layers surround the second portion and are stacked in turn on the substrate,wherein a first boundary is located between the first portion and the second portion,wherein the first conductive materials form first memory cells together with the first ...

NONVOLATILE MEMORY DEVICE INCLUDING ERASE TRANSISTORS

A nonvolatile memory device includes bitlines, a source line, cell channel structures, a gate electrode structure, erase channel structures and an erase selection line. The bitlines are disposed at a first end portion of a cell region, arranged in a first horizontal direction and extend in a second horizontal direction. The source line is disposed at a second end portion of the cell region and extend in the second horizontal direction. The cell channel structures are disposed in a cell string area of the cell region and are respectively connected between the bitlines and the source line. The erase channel structures are disposed in a contact area of the cell region and respectively connected between the bitlines and the source line. The erase channel structures include erase transistors. The erase selection line is disposed in the contact area to form a gate electrode of the erase transistors. 1. A nonvolatile memory device bitlines disposed at a first end portion of a cell region , arranged in a first horizontal direction and extending in a second horizontal direction;a source line disposed at a second end portion of the cell region and extending in the second horizontal direction;cell channel structures disposed in a cell string area of the cell region, wherein each one of the cell channel structures is connected between the bitlines and the source line and includes a string selection transistor, a ground selection transistor and memory cells;a gate electrode structure vertically stacked in the cell string area, wherein the gate electrode structure includes a string selection line, a ground selection transistor and wordlines;erase channel structures disposed in a contact area of the cell region, wherein each one of the erase channel structures is connected between the bitlines and the source line and includes erase transistors; andan erase selection line disposed in the contact area to form a gate electrode of the erase transistors.2. The nonvolatile memory device ...

3D packaging with low-force thermocompression bonding of oxidizable materials

Methods and systems for low-force, low-temperature thermocompression bonding. The present application teaches new methods and structures for three-dimensional integrated circuits, in which cold thermocompression bonding is used to provide reliable bonding. To achieve this, reduction and passivation steps are preferably both used to reduce native oxide on the contact metals and to prevent reformation of native oxide, preferably using atmospheric plasma treatments. Preferably the physical compression height of the elements is set to be only enough to reliably achieve at least some compression of each bonding element pair, compensating for any lack of flatness. Preferably the thermocompression bonding is performed well below the melting point. This not only avoids the deformation of lower levels which is induced by reflow techniques, but also provides a steep relation of force versus z-axis travel, so that a drastically-increasing resistance to compression helps to regulate the degree of thermocompression ...

Grinding wheel design with elongated teeth arrangement

A grinding wheel includes a base disk, and a plurality of teeth protruding beyond a surface of the base disk. The plurality of teeth is aligned to an elongated ring encircling a center of the grinding wheel.

SEMICONDUCTOR DEVICES

A semiconductor device includes a first conductive pattern at an upper portion of a first insulating interlayer on a first substrate, a first plurality of conductive nanotubes (CNTs) extending vertically, a second conductive pattern at a lower portion of a second insulating interlayer beneath a second substrate, and a second plurality of CNTs extending vertically. A lower surface of the second insulating interlayer contacts an upper surface of the first insulating interlayer. At least a portion of a sidewall of each of the first plurality of CNTs is covered by the first conductive pattern, and at least a portion of a sidewall of each of the second plurality of CNTs is covered by the second conductive pattern. The first and second conductive patterns vertically face each other, and at least one of the first plurality of CNTs and at least one of the second plurality of CNTs contact each other.

FAN-OUT POP STACKING PROCESS

Package on package structures and manners of formation are described. In an embodiment, an array of trenches is formed partially through a fan-out substrate. In an embodiment, a plurality of laterally separate locations thermal interface material is dispensed onto an array of embedded bottom die. In an embodiment a thermal compression tool including an array of cavities corresponding to an array of top packages is brought into contact with the array of top packages and underlying fan-out substrate during PoP joint formation. The fan-out substrate may be secured to a vacuum chuck during several processing operations.

SEMICONDUCTOR PACKAGE ASSEMBLY AND METHOD FOR FORMING THE SAME

A semiconductor package assembly and method for forming the same are provided. The semiconductor package assembly includes a first semiconductor die and a second semiconductor die disposed on a first surface of a substrate. The first semiconductor die includes a peripheral region having a second edge facing the first edge of the second semiconductor die and a third edge opposite to the second edge, a circuit region surrounded by the peripheral region, wherein the circuit region has a fourth edge adjacent to the second edge and a fifth edge adjacent to the third edge. A minimum distance between the second edge and the fourth edge is a first distance, a minimum distance between the third edge and the fifth edge is a second distance, and the first distance is different from the second distance.

Methods of making semiconductor device modules with increased yield

Methods of making semiconductor device modules may involve forming holes in a sacrificial material and placing an electrically conductive material in the holes. The sacrificial material may be removed to expose posts of the electrically conductive material. A stack of semiconductor dice may be placed between at least two of the posts after removing the sacrificial material, one of the semiconductor dice of the stack including an active surface facing in a direction opposite a direction in which another active surface of another of the semiconductor dice of the stack. The posts and the stack of semiconductor dice may be at least laterally encapsulated in an encapsulant. Bond pads of the one of the semiconductor dice may be electrically connected to corresponding posts after at least laterally encapsulating the posts and the stack of semiconductor dice.

LAND GRID ARRAY PATTERNS FOR MODULAR ELECTRONICS PLATFORMS AND METHODS OF PERFORMING THE SAME

Provided are methods, systems, and apparatuses related to modular electronics platforms for mobile computing devices. One such apparatus may include a system on module (SOM) having a first surface that is configured to be coupled electrically to one or more chipsets. The apparatus may include a land grid array (LGA) disposed on a second surface of the SOM. The LGA may include one or more center anchor pads, one or more corner anchor pads, a digital signal array, one or more communications pads, and one or more ground pads. The various pads of the LGA may be configured to be coupled to one or more pads or pins disposed on a surface of a main logic board (MLB).

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure includes a first substrate; a second substrate, disposed over the first substrate; a die, disposed over the second substrate; a via, extending through the second substrate and electrically connecting to the die; a redistribution layer (RDL) disposed between the first substrate and the second substrate, including a dielectric layer, a first conductive structure electrically connecting to the via, and a second conductive structure surrounding the first conductive structure, wherein the second conductive structure extends along an edge of the dielectric layer and penetrates through the dielectric layer; and a first underfill material, disposed between the first substrate and the RDL, wherein one end of the second conductive structure exposed through the dielectric layer is entirely in contact with the first underfill material.

OFFSET-ALIGNED THREE-DIMENSIONAL INTEGRATED CIRCUIT

A method for manufacturing a three-dimensional integrated circuit includes attaching a first side of a first die to a first carrier wafer. The method includes preparing a second side of the first die to generate a prepared second side of the first die. The method includes attaching the prepared second side of the first die to a second carrier wafer. The method includes removing the first carrier wafer from the first side of the first die to form a transitional three-dimensional integrated circuit. The method includes attaching a third carrier wafer to a first side of the transitional three-dimensional integrated circuit. The method includes attaching a first side of the second die to a second side of the transitional three-dimensional integrated circuit.

SEMICONDUCTOR DEVICES WITH BALL STRENGTH IMPROVEMENT

A semiconductor device includes a contact region over a substrate. The semiconductor device further includes a metal pad over the contact region. Additionally, the semiconductor device includes a post passivation interconnect (PPI) line over the metal pad, where the PPI line is in contact with the metal pad. Furthermore, the semiconductor device includes an under-bump-metallurgy (UBM) layer over the PPI line. Moreover, the semiconductor device includes a plurality of solder balls over the UBM layer, the plurality of solder balls being arranged at some, but not all, intersections of a number of columns and rows of a ball pattern.

Package substrate

A package substrate includes an inner interlayer, a first conductor layer on the inner interlayer, a second conductor layer on which the inner interlayer is formed, an outermost interlayer on the first conductor layer, an outermost conductor layer on the outermost interlayer and including first and second pads positioned to mount first and second electronic components on the outermost interlayer, outermost vias connecting the first and outermost conductor layers through the outermost interlayer, and skip vias connecting the outermost and second conductor layers through the outermost and inner interlayers. The first conductor layer includes a first circuit connecting two outermost vias, and the outermost conductor layer includes an outermost circuit connecting one of the two outermost vias and one skip via such that the first conductor circuit, two outermost vias, outermost circuit and one skip via form a connection path connecting one second pad and the second conductor layer.

Non-Vertical Through-via in Package

A package includes a device die, a through-via having a sand timer profile, and a molding material molding the device die and the through-via therein, wherein a top surface of the molding material is substantially level with a top surface of the device die. A dielectric layer overlaps the molding material and the device die. A plurality of redistribution lines (RDLs) extends into the dielectric layer to electrically couple to the device die and the through-via.

THREE-DIMENSIONAL MEMORY DEVICE WITH LOGIC SIGNAL ROUTING THROUGH A MEMORY DIE AND METHODS OF MAKING THE SAME

A memory device includes a memory die containing memory elements, a support die containing peripheral devices and bonded to the memory die, and an electrically conductive path between two of the peripheral devices which extends at least partially through the memory die. The electrically conductive path is electrically isolated from the memory elements.

High density interconnection using fanout interposer chiplet

Multiple component package structures are described in which an interposer chiplet is integrated to provide fine routing between components. In an embodiment, the interposer chiplet and a plurality of conductive vias are encapsulated in an encapsulation layer. A first plurality of terminals of the first and second components may be in electrical connection with the plurality of conductive pillars and a second plurality of terminals of first and second components may be in electrical connection with the interposer chiplet.

Interconnect structure with redundant electrical connectors and associated systems and methods

Semiconductor die assemblies having interconnect structures with redundant electrical connectors are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die, a second semiconductor die, and an interconnect structure between the first and the second semiconductor dies. The interconnect structure includes a first conductive film coupled to the first semiconductor die and a second conductive film coupled to the second semiconductor die. The interconnect structure further includes a plurality of redundant electrical connectors extending between the first and second conductive films and electrically coupled to one another via the first conductive film.

Semiconductor device having a plurality of chips being stacked

A semiconductor device, includes: a first semiconductor chip including: a first substrate; a first via; a first rear surface-side pad connected to the first via; a first wiring layer; a first front surface-side pad formed on the first wiring layer; and an input circuit formed in the first substrate, an input signal wire connecting the first via, the first front surface-side pad, and an input terminal of the input circuit; and a second semiconductor chip including: a second substrate; a second wiring layer; a second front surface-side pad; and an output circuit formed in the second substrate, an output signal wire connecting the second front surface-side pad to an output terminal of the output circuit. The second semiconductor chip is stacked on a rear surface side of the first semiconductor chip, and the first rear surface-side pad and the second front surface-side pad are connected.

SHIELDED PACKAGE ASSEMBLIES WITH INTEGRATED CAPACITOR

Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.

NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

Provided is a nonvolatile memory device. The nonvolatile memory device includes a conductive plate, a barrier conductive film extending along a surface of the conductive plate, a mold structure including a plurality of gate electrodes sequentially stacked on the barrier conductive film, a channel hole penetrating the mold structure to expose the barrier conductive film, an impurity pattern being in contact with the barrier conductive film, and formed in the channel hole, and a semiconductor pattern formed in the channel hole, extending from the impurity pattern along a side surface of the channel hole, and intersecting the plurality of gate electrodes.

Package and Method for Making the Same

A package structure includes a substrate having a first bond pad layer. A silicon bridge layer having one or more redistribution layers therein. The silicon bridge layer has a second bond pad, and the silicon bridge layer is attached to the substrate by an adhesive layer. A first die is coupled to the substrate and the silicon bridge layer. A second die is coupled to the silicon bridge layer, wherein the first die and the second die communicate with one another by way of the one or more redistribution layers. Power and/or ground connectors are coupled to the first bond pad and the second bond pad for enabling grounding and/or transferring power from the semiconductor substrate to the second die.

BONDED DIE ASSEMBLY CONTAINING PARTIALLY FILLED THROUGH-SUBSTRATE VIA STRUCTURES AND METHODS FOR MAKING THE SAME

A bonded assembly includes a first semiconductor die including a first substrate, first semiconductor devices located on the first substrate, first dielectric material layers located on the first semiconductor devices and embedding first metal interconnect structures, and first through-substrate via structures extending through the first substrate and contacting a respective first metal interconnect structure. Each of the first through-substrate via structures laterally surrounds a respective core cavity that contains a void or a dielectric fill material portion. The bonded assembly includes a second semiconductor die attached to the first semiconductor die, and including a second substrate, second semiconductor devices located on the second substrate, second dielectric material layers located on the second semiconductor devices and embedding second metal interconnect structures, and bonding pad structures electrically connected to a respective one of the second metal interconnect structures and bonded to a respective first through-substrate via structure. 1. A bonded assembly comprising:a first semiconductor die comprising a first substrate, first semiconductor devices located on the first substrate, first dielectric material layers located on the first semiconductor devices and embedding first metal interconnect structures, and first through-substrate via structures extending through the first substrate and the first semiconductor devices and contacting a respective one of the first metal interconnect structures, wherein each of the first through-substrate via structures laterally surrounds a respective core cavity that contains a void or a dielectric fill material portion; anda second semiconductor die attached to the first semiconductor die, and comprising a second substrate, second semiconductor devices located on the second substrate, second dielectric material layers located on the second semiconductor devices and embedding second metal interconnect ...

CHIP PACKAGE STRUCTURE

A chip package structure is provided. The chip package structure includes a first redistribution structure including a dielectric structure and wiring layers in the dielectric structure. The chip package structure includes a first chip over the first surface. The chip package structure includes a first conductive pillar over the first surface and electrically connected to the wiring layers. The chip package structure includes a second chip over the second surface. The second chip includes a second substrate and a second conductive pad over the second substrate, and the second conductive pad is between the second substrate and the first redistribution structure. The chip package structure includes a second conductive pillar over the second surface and electrically connected to the wiring layers.

Device and Method for UBM/RDL Routing

An under bump metallurgy (UBM) and redistribution layer (RDL) routing structure includes an RDL formed over a die. The RDL comprises a first conductive portion and a second conductive portion. The first conductive portion and the second conductive portion are at a same level in the RDL. The first conductive portion of the RDL is separated from the second conductive portion of the RDL by insulating material of the RDL. A UBM layer is formed over the RDL. The UBM layer includes a conductive UBM trace and a conductive UBM pad. The UBM trace electrically couples the first conductive portion of the RDL to the second conductive portion of the RDL. The UBM pad is electrically coupled to the second conductive portion of the RDL. A conductive connector is formed over and electrically coupled to the UBM pad.

Semiconductor packaging structure and manufacturing method thereof

A semiconductor structure includes a die, a molding interfacing with the die along a first direction, wherein a coefficient of thermal expansion (CTE) mismatch is between the molding and the die, a via extending within and through the molding, an elongated member extending within the molding and at least partially along the first direction, a conductive trace over the elongated member and the die, and a dielectric between the elongated member and the conductive trace, wherein the elongated member is proximal to the die than the via.

Wiring substrate

A wiring substrate includes a substrate body, a first wiring, and a second wiring. The first wiring and the second wiring are located on an upper surface of the substrate body. The wiring substrate further includes a solder resist layer that covers the first wiring and the second wiring. The solder resist layer includes a first opening that partially exposes the second wiring and a missing portion that partially exposes the first wiring. The wiring substrate further includes an insulation coating that covers an inner wall of the missing portion, the first wiring exposed by the missing portion, and at least a portion of an upper surface of the solder resist layer. The insulation coating includes a second opening that is in communication with the first opening and partially exposes the second wiring.

Method of forming a dummy die of an integrated circuit having an embedded annular structure

An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.

POWER ROUTING FOR 2.5D OR 3D INTEGRATED CIRCUITS

Embodiments relate to an electronic circuit implemented using a first integrated circuit die, a second integrated circuit die, and an interposer connecting the first integrated circuit die to the second integrated circuit die. The first integrated circuit die implements a first electronic circuit. The first integrated circuit die includes a first set of contacts on a bottom surface, a buried power rail (BPR), and a plurality of through-silicon vias (TSV) for connecting the BPR to the first set of contacts. The interposer includes a second set of contacts and a power delivery network (PDN). Each contact of the second set of contact corresponds to a contact of the first set of contacts of the first integrated circuit die. The PDN is configured to route a power supply voltage to the second set of contacts.

THREE-DIMENSIONAL MEMORY DEVICES AND METHODS FOR FORMING THE SAME

In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, a first bonding interface between the first semiconductor structure and the second semiconductor structure, and a second bonding interface between the second semiconductor structure and the third semiconductor structure. The first semiconductor structure includes an array of NAND memory strings and a first semiconductor layer in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a first peripheral circuit of the array of NAND memory strings including a first transistor, and a second semiconductor layer in contact with the first transistor. A third semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a third semiconductor layer in contact with the second transistor. The first peripheral circuit ...

Three-dimensional memory devices

In certain aspects, a three-dimensional (3D) memory device includes a memory stack including interleaved conductive layers and dielectric layers, a plurality of channel structures each extending vertically through the memory stack, a conductive layer in contact with source ends of the plurality of channel structures, a first source contact electrically connected to the channel structures, and a second source contact electrically connected to the channel structures.

SEMICONDUCTOR PACKAGE

A semiconductor package is provided. The semiconductor package includes a package substrate, an interposer including a lower protective layer, conductive connectors connecting the package substrate to the interposer, a semiconductor chip arranged between the package substrate and the interposer, and cooling patches arranged between the semiconductor chip and the interposer and having cylindrical shapes, wherein each of the cooling patches includes the same material as each of the conductive connectors, a height of each of the cooling patches is less than or equal to a diameter of each of the cooling patches, and thermal conductivity of each of the cooling patches is greater than thermal conductivity of the lower protective layer.

SEMICONDUCTOR PACKAGE

A semiconductor package includes a first lower redistribution layer, a first upper redistribution layer over the first lower redistribution layer, a first semiconductor chip between the first lower redistribution layer and the first upper redistribution layer, a first connection post spaced apart from the first semiconductor chip and connecting the first lower redistribution layer to the first upper redistribution layer, a first interposition layer on the first upper redistribution layer, a second interposition layer on the first interposition layer, a second lower redistribution layer on the second interposition layer, a second upper redistribution layer over the second lower redistribution layer, a second semiconductor chip between the second lower redistribution layer and the second upper redistribution layer, and a second connection post spaced apart from each other and connecting the second lower redistribution layer to the second upper redistribution layer.

Semiconductor device having package on package structure and method of manufacturing the semiconductor device

A semiconductor device having a package on package (PoP) structure, in which a fine pitch between package substrates is implemented, a total height of a package is reduced, and reliability is enhanced. The semiconductor package includes a first package substrate including a first body layer and a first passivation layer, a first semiconductor chip on the first package substrate, a second package substrate on the first package substrate, the second package substrate including a second body layer and a second passivation layer, a first connection member on the first package substrate outside the first semiconductor chip, and a gap filler filled between the first package substrate and the second package substrate, wherein the first package substrate includes a first trench, the second package substrate includes a second trench, and the first semiconductor chip is disposed between the first trench and the second trench.

Semiconductor memory device

A semiconductor memory device includes a first chip having a peripheral transistor and a first insulating layer, and includes a second chip having a stacked structure and a second insulating layer. The stacked structure includes conductive patterns and insulating patterns alternately stacked with each other, the first insulating layer includes a first bonding surface, the second insulating layer includes a second bonding surface contacting the first bonding surface, and the second chip further includes a protrusion protruding from the second bonding surface of the second insulating layer toward the first insulating layer.

MEMORY CIRCUITS

A circuit is provided. The circuit includes a first die that includes a memory array, and the memory array includes a plurality of memory cells, a sensing element coupled to the plurality of memory cells, and a first plurality of conductive pads coupled to the sensing element. The circuit also includes a second die that includes an address decoder associated with the memory array of the first die and a second plurality of conductive pads coupled to the address decoder. The first die is coupled to the second die by an interposer. The address decoder of the second die is coupled to the sensing element of the first die. A first voltage swing of the first die is larger than a second voltage swing of the second die.

CRUCIFORM BONDING STRUCTURE FOR 3D-IC

A bonding structure that may be used to form 3D-IC devices is formed using first oblong bonding pads on a first substrate and second oblong bonding pads one a second substrate. The first and second oblong bonding pads are laid crosswise, and the bond is formed. Viewed in a first cross-section, the first bonding pad is wider than the second bonding pad. Viewed in a second cross-section at a right angle to the first, the second bonding pad is wider than the first bonding pad. Making the bonding pads oblong and angling them relative to one another reduces variations in bonding area due to shifts in alignment between the first substrate and the second substrate. The oblong shape in a suitable orientation may also be used to reduce capacitive coupling between one of the bonding pads and nearby wires.

SEMICONDUCTOR DEVICE INCLUDING RESISTOR ELEMENT

A semiconductor device includes a first pad defined on one surface of a first chip; a second pad defined on one surface of a second chip which is stacked on the first chip, and bonded to the first pad; a first resistor element defined in the first chip, and coupled to the first pad; and a second resistor element defined in the second chip, and coupled to the second pad.

ELECTRONIC ASSEMBLY AND METHOD FOR THE PRODUCTION THEREOF

HALBLEITERVORRICHTUNG UND VERFAHREN ZUM HERSTELLEN EINER HALBLEITERVORRICHTUNG

Eine Halbleitervorrichtung umfasst einen Träger, der ein Chippad und einen Kontakt umfasst, einen Halbleiterchip, der eine erste Hauptseite und eine gegenüberliegende zweite Hauptseite umfasst, wobei der Halbleiterchip durch eine erste Lötstelle derart an dem Chippad befestigt ist, dass die zweite Hauptseite dem Chippad zugewandt ist, und einen Kontaktclip mit einem ersten Kontaktbereich und einem zweiten Kontaktbereich, wobei der erste Kontaktbereich durch eine zweite Lötstelle an der ersten Hauptseite des Halbleiterchips befestigt ist und der zweite Kontaktbereich durch eine dritte Lötstelle am Kontakt befestigt ist, wobei der erste Kontaktbereich eine konvexe Form aufweist, die der ersten Hauptseite des Halbleiterchips derart zugewandt ist, dass ein Abstand zwischen der ersten Hauptseite und dem ersten Kontaktbereich von einer Basis des konvexen Bereichs aus zu einem Rand des ersten Kontaktbereichs hin zunimmt, und wobei die Basis entlang einer Linie verläuft, die im Wesentlichen senkrecht ...

Halbleiterbauelemente und Verfahren zur Herstellung von Halbleiterbauelementen

Bauelement, umfassend:ein Halbleitermaterial (1), das eine erste Hauptoberfläche (2), eine gegenüberliegende Oberfläche (3), die der ersten Hauptoberfläche gegenüberliegt, und eine seitliche Oberfläche (4), die sich von der ersten Hauptoberfläche zur gegenüberliegenden Oberfläche erstreckt, umfasst, wobei das Halbleitermaterial eine Funktionsfläche umfasst, die in einem Hochfrequenzbereich betrieben wird;ein erstes elektrisches Kontaktelement (5), das auf der ersten Hauptoberfläche (2) des Halbleitermaterials angeordnet ist;ein Glasmaterial (6), das eine zweite Hauptoberfläche (7) umfasst, wobei das Glasmaterial die seitliche Oberfläche (4) des Halbleitermaterials kontaktiert und wobei die erste Hauptoberfläche (2) des Halbleitermaterials und die zweite Hauptoberfläche des Glasmaterials in einer gemeinsamen Ebene angeordnet sind; undeine Metallschicht (11), die über der ersten Hauptoberfläche (2) des Halbleitermaterials und über dem Glasmaterial angeordnet ist, wobei eine passive elektronische ...

Multi-Stack-Package-on-Package-Strukturen

Ein Package enthält einen ersten Bauelement-Die und ein erstes Verkapselungsmaterial, das den ersten Bauelement-Dies verkapselt. Eine Unterseite des ersten Bauelement-Dies ist mit einer Unterseite des ersten Verkapselungsmaterials koplanar. Erste dielektrische Schichten liegen unter dem ersten Bauelement-Die. Erste Umverteilungsleitungen befinden sich in den ersten dielektrischen Schichten und sind elektrisch mit dem ersten Bauelement-Die gekoppelt. Zweite dielektrischen Schichten liegen über dem ersten Bauelement-Die. Zweite Umverteilungsleitungen befinden sich in den zweiten dielektrischen Schichten und sind elektrisch mit den ersten Umverteilungsleitungen gekoppelt. Ein zweiter Bauelement-Die liegt über den zweiten Umverteilungsleitungen und ist elektrisch mit ihnen gekoppelt. Keine Lötregion verbindet den zweiten Bauelement-Die mit den zweiten Umverteilungsleitungen. Ein zweites Verkapselungsmaterial verkapselt den zweiten Bauelement-Die. Ein dritter Bauelement-Die ist elektrisch mit ...

Port spreading

Supercomputer using wafer scale integration

THROUGH SILICON VIA BRIDGE INTERCONNECT

In integrated circuit bridge interconnect system includes a first die and a second die provided in a side by side configuration and electrically interconnected to each other by a bridge die. The bridge die includes through silicon vias (TSVs) to connect conductive interconnect lines on the bridge die to the first die and the second die. Active circuitry, other than interconnect lines, may be provided on the bridge die. At least one or more additional die may be stacked on the bridge die and interconnected to the bridge die.

Semiconductor package

Fan out system in package and method for forming the same

Method of forming a semiconductor die

In one embodiment, semiconductor die having non-rectangular shapes and die having various different shapes are formed and singulated from a semiconductor wafer.

Adhesion Enhancing Structures for a Package

Integrated circuit packaging technology and small form factor or wearable device configuration

반도체 장치, 반도체 장치의 제조 방법, 고체 촬상 장치 및 전자 기기

... 본 발명의 반도체 장치의 제조 방법은 제1 기판과 상기 제1 기판의 일면과 접하도록 형성된 제1 절연층을 갖는 제1의 반도체 웨이퍼와, 제2 기판과 상기 제2 기판의 일면과 접하도록 형성된 제2 절연층을 갖는 제2의 반도체 웨이퍼를 적층하여 접합하는 공정과, 상기 제1 기판의 일면과 반대측의 타면에 제3 절연층을 형성하는 공정과, 상기 제3 절연층, 상기 제1 기판, 및 상기 제1 절연층을 관통하고, 상기 제2 절연층 내에 형성된 제2 배선층상에 상기 제2 절연층이 남도록 에칭을 행하여, 제1 접속구멍을 형성하는 공정과, 상기 제1 접속구멍에 절연막을 형성하는 공정과, 상기 제2 배선층상의 상기 제2 절연층 및 상기 절연막의 에칭을 행하여, 제2 접속구멍을 형성하고, 상기 제2 배선층을 노출시키는 공정과, 상기 제1 및 제2 접속구멍의 내부에 형성되고, 상기 제2 배선층과 접속하는 제1의 비어를 형성하는 공정을 구비하고, 상기 제1 기판의 상기 타면에 형성된 상기 제1 접속구멍의 지름은, 상기 제3 절연층에 형성된 상기 제1 접속구멍의 지름보다 큰 것을 특징으로 한다.

소형 폼 팩터 또는 웨어러블 디바이스를 위한 집적 회로 패키징 기술, 구성, 장치, 조립체 및 방법

... 본 발명의 실시예들은 소형 폼 팩터 또는 웨어러블 디바이스들을 위한 집적 회로(IC) 패키징 기술들 및 구성들에 관한 것이다. 일 실시예에서, 장치는 제 1 면 및 제 1 면에 대향 배치된 제 2 면, 및 제 1 면과 제 2 면 사이에 배치된 측벽을 갖는 기판과 - 측벽은 기판의 둘레를 정의함 -, 기판의 제 1 면과 제 2 면 사이에 배치된 복수의 기판 관통 비아(TSV)와, 제 1 면 상에 배치된 제 1 유전층 - 제 1 유전층은 제 1 유전층의 평면에서 하나 이상의 다이의 전기 신호들을 라우팅하기 위한 전기 라우팅 피처들을 포함함 -을 포함할 수 있다. 다른 실시예들이 설명되고/되거나 청구될 수 있다.

Semiconductor Package with POP(Package On Package) structure

SEMICONDUCTOR PACKAGE HAVING EXPANDED BANDWIDTH

Disclosed is a semiconductor package having an expanded bandwidth. The disclosed semiconductor package includes: mutually stacked first and second semiconductor chips having, on a lower surface of each of the first and second semiconductor chips, a first normal pad to which a first input-output circuit is connected and a first dummy pad to which the first input-output pad is not connected; a first through electrode electrically connecting the first dummy pad of the first semiconductor chip and the first normal pad of the second semiconductor chip by penetrating the first semiconductor chip; and a substrate supporting the lower surface of the first semiconductor chip and having first connection pads electrically connected to the first normal pad and the first dummy pad of the first semiconductor chip individually. COPYRIGHT KIPO 2016 ...

스택되는 다이들의 위치들을 제어하는 기술

... 조립 부품(100) 및 조립 부품을 이용하여 칩 패키지를 조립하는 기술이 설명된다. 이 칩 패키지는 수직 방향으로 스택 내에 배열되는 반도체 다이들(310-1 내지 310-N)의 세트를 포함하는데, 반도체 다이들은 수직 스택의 일 측에 계단형 테라스(112-1)를 정의하도록 수평 방향에서 서로 오프셋된다. 또한, 칩 패키지는 조립 부품(100)을 이용하여 조립될 수 있다. 특히, 조립 부품은 대략 칩 패키지의 계단형 테라스를 대략 미러링하는 계단형 테라스들(112-1, 112-2)의 쌍을 포함할 수 있고, 이 경사형 테라스들의 쌍은 칩 패키지의 조립 동안 수직 스택으로 반도체 다이들의 세트를 배치하는 조립 도구에 대해 수직 위치 레퍼런스를 제공한다.

적층형 반도체 패키지

... 적층형 반도체 패키지는 제1 패키지 기판 및 상기 제1 패키지 기판 상에 실장되며 일측부를 따라 배열된 제1 칩 패드들을 갖는 제1 반도체 칩을 포함하는 제1 반도체 패키지, 및 상기 제1 반도체 패키지 상에 배치되며, 제2 패키지 기판 및 상기 제2 패키지 기판 상에 실장되고 상기 제2 패키지 기판의 제1 측부의 연장 방향을 따라 나란히 배열되며 일측부를 따라 배열된 제2 칩 패드들을 각각 갖는 제1 서브 반도체 칩과 제2 서브 반도체 칩을 포함하는 제2 반도체 패키지를 포함하고, 상기 제2 패키지 기판은 상기 제2 칩 패드들과 전기적으로 연결되며 상기 제2 칩 패드들과 인접하도록 상기 제1 측부를 따라 배열된 제2 접속 패드들을 가지고, 상기 제1 패키지 기판은 상기 제1 칩 패드들과 전기적으로 연결되며 상기 제2 접속 패드와 대응하도록 상기 제1 패키지 기판의 제1 측부를 따라 배열된 제1 접속 패드들을 갖는다.

Board for electronic component package, electronic component package, and method of manufacturing board for electronic component package

Integrated circuit packaging techniques and configurations for small form-factor or wearable devices

Embodiments of the present disclosure are directed toward integrated circuit (IC) packaging techniques and configurations for small form-factor or wearable devices. In one embodiment, an apparatus may include a substrate having a first side and a second side disposed opposite to the first side and a sidewall disposed between the first side and the second side, the sidewall defining a perimeter of the substrate, and a plurality of through-substrate vias (TSVs) disposed between the first side and the second side of the substrate, and a first dielectric layer disposed on the first side and including electrical routing features to route electrical signals of one or more dies in a plane of the first dielectric layer. Other embodiments may be described and/or claimed.

Dynamic random access memory (DRAM) mounts

Donut-shaped Dynamic Random Access Memory (DRAM) includes a hole that fits around a processor, such that the DRAM and the processor are adjacent to one another on an Integrated Circuit (IC) package. In an embodiment, a heat spreader is mounted on top of the processor and covers a top of the DRAM without touching the DRAM.

System on integrated chips and methods of forming same

An embodiment method for forming a semiconductor package includes attaching a first die to a first carrier, depositing a first isolation material around the first die, and after depositing the first isolation material, bonding a second die to the first die. Bonding the second die to the first die includes forming a dielectric-to-dielectric bond. The method further includes removing the first carrier and forming fan-out redistribution layers (RDLs) on an opposing side of the first die as the second die. The fan-out RDLs are electrically connected to the first die and the second die.

Memory module in a package

A microelectronic package can include a substrate having first and second opposed surfaces, first, second, third, and fourth microelectronic elements, and a plurality of terminals exposed at the second surface. Each microelectronic element can have a front surface facing the first surface of the substrate and a plurality of contacts at the front surface. The front surfaces of the microelectronic elements can be arranged in a single plane parallel to the first surface. Each microelectronic element can have a column of contacts exposed at the front surface and arranged along respective first, second, third, and fourth axes. The first and third axes can be parallel to one another. The second and fourth axes can be transverse to the first and third axes. The microelectronic package can also include electrical connections extending from at least some of the contacts of each microelectronic element to at least some of the terminals.

Package and method

A package includes a die, which includes a semiconductor substrate, a plurality of through-vias penetrating through the semiconductor substrate, a seal ring overlapping and connected to the plurality of through-vias, and a plurality of electrical connectors underlying the semiconductor substrate and connected to the seal ring. An interposer is underlying and bonded to the die. The interposer includes a substrate, and a plurality of metal lines over the substrate. The plurality of metal lines is electrically coupled to the plurality of electrical connectors. Each of the plurality metal lines has a first portion overlapped by the first die, and a second portion misaligned with the die. A thermal conductive block encircles the die, and is mounted on the plurality of metal lines of the interposer.

APPARATUSES COMPRISING SEMICONDUCTOR DIES IN FACE-TO-FACE ARRANGEMENTS

Electronic component package and electronic device including the same

Semiconductor device, manufacturing method thereof, solid-state imaging device, and electronic apparatus

Method for manufacturing semiconductor device

BBUL MATERIAL INTEGRATION IN-PLANE WITH EMBEDDED DIE FOR WARPAGE CONTROL

An apparatus including a die including a first side and an opposite second side including a device side with contact points and lateral sidewalls defining a thickness of the die; a primary core adjacent at least a pair of the lateral sidewalls of the die; and a build-up carrier coupled to the second side of the die, the build-up carrier including a plurality of alternating layers of conductive material and insulating material, wherein at least one of the layers of conductive material is coupled to one of the contact points of the die. A method of forming a package and an apparatus including a computing device including a package are also disclosed.

Methods of packaging semiconductor devices and packaged semiconductor devices

Methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes coupling through-vias to an insulating material, each of the through-vias having a first width. Dies are also coupled to the insulating material. A portion of the insulating material is removed proximate each of the through-vias. The portion of the insulating material proximate each of the through-vias removed has a second width, the second width being less than the first width.

Semiconductor module

The present invention provides a semiconductor module capable of improving a bandwidth between a logic chip and a RAM. According to the present invention, a semiconductor module 1 is provided with: a logic chip; a pair of RAM units 30 each composed of a lamination-type RAM module; a first interposer 10 electrically connected to the logic chip and to each of the pair of RAM units 30; and a connection unit 40 that communicatively connects the logic chip and each of the pair of RAM units 30, wherein one RAM unit 30a is placed on the first interposer 10, and has one end portion disposed so as to overlap, in the lamination direction C, one end portion of the logic chip with the connection unit 40 therebetween, and the other RAM unit 30b is disposed so as to overlap the one RAM unit 30a with the connection unit 40 therebetween, and is also disposed along the outer periphery of the logic chip.

Semiconductor device and manufacturing method thereof

A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a stackable semiconductor device with small size and fine pitch and a method of manufacturing thereof.

Stack packages including diffusion barriers over sidewalls of through via electrodes and methods of manufacturing the same

Embodiments of a stack package may include an upper chip on a lower chip, a backside passivation layer covering the backside surface of the lower chip and having a thickness which is substantially equal to a height of the protrusion portion of a lower through via electrode, a backside bump substantially contacting the protrusion portion, and a front side bump electrically connected to a chip contact portion of the upper chip and physically and electrically connected to the backside bump. The backside passivation layer may include a first insulation layer provided over a sidewall of the protrusion portion and the backside surface of the lower chip. Embodiments of fabrication methods are also disclosed.

Hybrid carbon-metal interconnect structures

Embodiments of the present disclosure are directed towards techniques and configurations for hybrid carbon-metal interconnect structures in integrated circuit assemblies. In one embodiment, an apparatus includes a substrate, a metal interconnect layer disposed on the substrate and configured to serve as a growth initiation layer for a graphene layer and the graphene layer, wherein the graphene layer is formed directly on the metal interconnect layer, the metal interconnect layer and the graphene layer being configured to route electrical signals. Other embodiments may be described and/or claimed.

Semiconductor device and method of manufacturing the same

According to one embodiment, a semiconductor device includes a stacked chip includes semiconductor chips which are stacked, the semiconductor chips comprises semiconductor substrates and through electrodes formed in the semiconductor substrates, respectively, the through electrodes being electrically connected, and deactivating circuits provided in the semiconductor chips, respectively, and configured to deactivate a failed semiconductor chip.

Semiconductor structure and manufacturing method thereof

In a manufacturing method of a semiconductor structure, a substrate having a front surface and a back surface is provided. The front surface has a device layer thereon and conductive plugs electrically connected to the device layer. A thinning process is performed on the back surface of the substrate, such that the back surface of the substrate and surfaces of the conductive plugs have a distance therebetween. Holes are formed in the substrate from the back surface to the conductive plugs, so as to form a porous film. An oxidization process is performed, such that the porous film correspondingly is reacted to form an oxide material layer. A polishing process is performed on the oxide material layer to expose the surfaces of the conductive plugs.

Alignment marks to enable 3d integration

Disclosed are a structure including alignment marks and a method of forming alignment marks in three dimensional (3D) structures. The method includes forming apertures in a first surface of a first semiconductor substrate; joining the first surface of the first semiconductor substrate to a first surface of a second semiconductor substrate; thinning the first semiconductor on a second surface of the first semiconductor substrate to provide optical contrast between the apertures and the first semiconductor substrate; and aligning a feature on the second surface of the first semiconductor substrate using the apertures as at least one alignment mark.

Method of transferring and electrically joining a high density multilevel thin film to a circuitized and flexible organic substrate and associated devices

A method is for making an electronic device and includes forming an interconnect layer stack on a sacrificial substrate and having a plurality of patterned electrical conductor layers, and a dielectric layer between adjacent patterned electrical conductor layers. The method also includes laminating and electrically joining through an intermetallic bond a liquid crystal polymer (LCP) substrate to the interconnect layer stack on a side thereof opposite the sacrificial substrate. The method further includes removing the sacrificial substrate to expose a lowermost patterned electrical conductor layer, and electrically coupling at least one first device to the lowermost patterned electrical conductor layer.

Unpackaged and packaged IC stacked in a system-in-package module

There is provided a system and method for unpackaged and packaged IC stacked in a system-in-package module. There is provided a system-in-package module comprising a substrate including a first contact pad and a second contact pad disposed thereon, a packaged device disposed on the substrate, and an unpackaged device stacked atop the packaged device, wherein a first electrode of the packaged device is electrically and mechanically coupled to the first contact pad, and wherein a second electrode of the unpackaged device is electrically coupled to the second contact pad. The structure of the disclosed system-in-package module provides several advantages over conventional designs including increased yields, facilitated die substitution, enhanced thermal and grounding performance through direct connect vias, stacking of wider devices without a spacer, and a simplified single package structure for reduced fabrication time and cost.

Memory module in a package

A microelectronic package can include a substrate having first and second opposed surfaces, at least two pairs of microelectronic elements, and a plurality of terminals exposed at the second surface. Each pair of microelectronic elements can include an upper microelectronic element and a lower microelectronic element. The pairs of microelectronic elements can be fully spaced apart from one another in a horizontal direction parallel to the first surface of the substrate. Each lower microelectronic element can have a front surface facing the first surface of the substrate and a plurality of contacts at the front surface. A surface of each of the upper microelectronic elements can at least partially overlie a rear surface of the lower microelectronic element in its pair. The microelectronic package can also include electrical connections extending from at least some of the contacts of each lower microelectronic element to at least some of the terminals.

Dram repair architecture for wide i/o dram based 2.5d/3d system chips

A 2.5D or 3D repair architecture includes a logic die, and a memory die. In the 2.5D architecture, the logic die and memory die are mounted on an interposer. In the 3D architecture, the memory die is mounted on the logic die. The logic has a control logic wrapped with a processor wrapper. The processor wrapper enables testing components of the control logic. The control logic further comprises a wide input/output controller, a built-in-repair analyzer (BIRA), and a repair controller. A method utilizing the repair architecture provides for repairing failed columns and rows of a memory device.

Multi-chip semiconductor package and method of fabricating the same

A first semiconductor chip having a first projection electrode formed on an upper surface thereof is prepared. A second semiconductor chip having a second projection electrode is mounted on the first semiconductor chip to expose the first projection electrode. An insulating film is formed between the first projection electrode and the second projection electrode. A groove is formed in the insulating film. An interconnection configured to fill an inside of the groove and connected to the first projection electrode and the second projection electrode is formed.

Novel semiconductor device and structure

A semiconductor device, including: a first semiconductor layer including first transistors, wherein the first transistors are interconnected by at least one metal layer including aluminum or copper; and a second mono-crystallized semiconductor layer including second transistors and overlaying the at least one metal layer, wherein the at least one metal layer is in-between the first semiconductor layer and the second mono-crystallized semiconductor layer, wherein the second mono-crystallized semiconductor layer is less than 100 nm in thickness, and wherein the second transistors include horizontally oriented transistors.

Large panel leadframe

A method of manufacturing an integrated circuit package includes mounting a large panel leadframe having a substantially square shape to a ring. The large panel leadframe includes a plurality of die pads and a corresponding plurality of leads arranged in a matrix pattern. An integrated circuit chip is attached to each of the die pads. An encapsulant material is applied over the integrated circuit chips and at least a part of the large panel leadframe. Each of the die pads and its corresponding leads are separated from the large panel leadframe to form individual integrated circuit packages. The steps of attaching the integrated circuit chips and applying the encapsulant material are performed while the large panel leadframe is mounted to a taped ring.

Method of fabricating a micro device transfer head

A micro device transfer head and head array are disclosed. In an embodiment, the micro device transfer head includes a base substrate, a mesa structure with sidewalls, an electrode formed over the mesa structure, and a dielectric layer covering the electrode. A voltage can be applied to the micro device transfer head and head array to pick up a micro device from a carrier substrate and release the micro device onto a receiving substrate.

Multichip Module with Reroutable Inter-Die Communication

A multichip module (MCM) has redundant I/O connections between its dice. That is, the number of inter-die I/O connections used is larger than the number of connections ordinarily used to provide connectivity between the dice. Defective connections are discovered through testing after MCM assembly and avoided, with signals being rerouted through good (e.g., not defective) redundant connections. The testing can be done at assembly time and the results stored in nonvolatile memory. Alternatively, the MCM can perform the testing itself dynamically, e.g., at power up, and use the test results to configure the inter-die I/O connections.

Power line filter for multidimensional integrated circuits

An interposer element in a multidimensional integrated circuit with stacked elements has one or more conductors, especially power supply lines, coupled through decoupling networks defining low impedance shunts for high frequency signals to ground. The interposer has successive tiers including silicon, metal and dielectric deposition layers. The decoupling network for a conductor has at least one and preferably two reactive transmission lines. A transmission line has an inductor in series with the conductor and parallel capacitances at the inductor terminals. The inductors are formed by traces in spaced metal deposition layers forming coil windings and through vias connecting between layers to permit conductor crossovers. The capacitances are formed by MOScaps in the interposer layers. An embodiment has serially coupled coils with capacitances at the input, output and junction between the coils, wherein the coils are magnetically coupled to form a transformer.

Semiconductor Die Connection System and Method

A system and method for connecting semiconductor dies is provided. An embodiment comprises connecting a first semiconductor die with a first width to a second semiconductor die with a larger second width and that is still connected to a semiconductor wafer. The first semiconductor die is encapsulated after it is connected, and the encapsulant and first semiconductor die are thinned to expose a through substrate via within the first semiconductor die. The second semiconductor die is singulated from the semiconductor wafer, and the combined first semiconductor die and second semiconductor die are then connected to another substrate.

Package-on-package assembly with wire bond vias

A structure includes a substrate having a first region and a second region, the substrate also having a first surface and a second surface. Electrically conductive elements are exposed at the first surface within the second region. Wire bonds have bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. At least one of the wire bonds has a shape such that the wire bond defines an axis between the free end and the base thereof and such that the wire bond defines a plane. A bent portion of the at least one wire bond extends away from the axis within the plane. A dielectric encapsulation layer covers portions of the wire bonds such that unencapsulated portions, including the ends, of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer.

Method of fabricating wafer level package

A method of fabricating a wafer level package includes preparing a wafer including a plurality of first semiconductor chips, mounting a plurality of second semiconductor chips on the wafer, disposing the wafer on a lower mold and disposing an upper mold so as to surround edges of a top surface of the wafer, dispensing a molding member on the wafer, and pressurizing the molding member by using a plunger so as to fabricate a wafer level package in which a top surface of each of the plurality of second semiconductor chips is exposed.

Noise attenuation wall

An embodiment of an apparatus is disclosed. For this embodiment of the apparatus, an interposer has first vias. First interconnects and second interconnects respectively are coupled on opposite surfaces of the interposer. A first portion of the first interconnects and a second portion of the first interconnects are spaced apart from one another defining an isolation region between them. A substrate has second vias. Third interconnects and the second interconnects are respectively coupled on opposite surfaces of the package substrate. A first portion of the first vias and a first portion of the second vias are both in the isolation region and are coupled to one another with a first portion of the second interconnects.

Integrated circuit package

An integrated circuit package and a manufacturing method thereof are provided. The integrated circuit package can include a substrate provided with a circuit pattern, a first set of bonding fingers and a second set of bonding fingers, a first chip stack mounted on the substrate and having a plurality of first semiconductor chips stacked in a first direction in a stepped manner, each of the first semiconductor chips being provided with a first bonding pad at an end thereof on one side, a second chip stack mounted on the first chip stack and having a plurality of second semiconductor chips stacked in a second direction opposite to the first direction in a stepped manner.

Interconnect Structure and Method of Forming Same

A semiconductor device comprises a first chip bonded on a second chip. The first chip comprises a first substrate and first interconnection components formed in first IMD layers. The second chip comprises a second substrate and second interconnection components formed in second IMD layers. The device further comprises a first conductive plug formed within the first substrate and the first IMD layers, wherein the first conductive plug is coupled to a first interconnection component and a second conductive plug formed through the first substrate and the first IMD layers and formed partially through the second IMD layers, wherein the second conductive plug is coupled to a second interconnection component. 1. A method comprising: the first semiconductor wafer comprises a first substrate, first inter-metal dielectric layers and first interconnect structures formed in the first inter-metal dielectric layers and over the first substrate; and', 'the second semiconductor wafer comprises a second substrate, second inter-metal dielectric layers and second interconnect structures formed in the second inter-metal dielectric layers and over the second substrate;, 'bonding a first semiconductor wafer on a second semiconductor wafer, whereinpatterning the first substrate to form a first opening and a second opening in the first substrate;depositing a liner to extend from within the first opening to within the second opening; the third opening is an extension of the first opening and formed partially through the first inter-metal dielectric layers; and', 'the fourth opening is an extension of the second opening and formed through the first inter-metal dielectric layers and partially through the second inter-metal dielectric layers; and, 'forming a third opening and a fourth opening using an etching process and using a first interconnect structure as a hard mask layer, whereinplating a conductive material in the first opening, the second opening, the third opening and the fourth ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a wiring board; a first semiconductor chip including a first surface, a second surface, and a connection bump on the first surface, the first semiconductor chip coupled to the wiring board through the connection bump; a resin layer covering the connection bump between the first semiconductor chip and the wiring board, an upper surface of the resin layer parallel to the second surface of the first semiconductor chip; and a second semiconductor chip including a third surface, a fourth surface, and an adhesive layer on the third surface, the second semiconductor chip adhering to the second surface of the first semiconductor chip and the upper surface of the resin layer through the adhesive layer. The upper surface of the resin layer projects outside a portion of at least an outer edge of the second semiconductor chip when viewed from the top. 1. A semiconductor device comprising:a wiring board;a first semiconductor chip including a first surface, a second surface opposite to the first surface, and a connection bump on the first surface, the first semiconductor chip coupled to the wiring board through the connection bump;a resin layer covering the connection bump between the first semiconductor chip and the wiring board, an upper surface of the resin layer substantially parallel to the second surface of the first semiconductor chip; anda second semiconductor chip including a third surface, a fourth surface opposite to the third surface, and an adhesive layer on the third surface, the second semiconductor chip adhering to the second surface of the first semiconductor chip and the upper surface of the resin layer through the adhesive layer,wherein the upper surface of the resin layer projects outside a portion of at least an outer edge of the second semiconductor chip when viewed from the top.2. The semiconductor device according to claim 1 ,wherein a spacer is not provided between the second semiconductor chip and the wiring board.3. The ...

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

To improve the assemblability of a semiconductor device. 120-. (canceled)21. A method for manufacturing a semiconductor device , comprising the steps of:(a) preparing a first semiconductor chip that has a first main surface and a second main surface on a side opposite to the first main surface, and a second semiconductor chip that has a first main surface, and a second main surface on a side opposite to the first main surface; and(b) mounting the second semiconductor chip over the first semiconductor chip so that the second main surface of the first semiconductor chip and the first main surface of the second semiconductor chip face each other,wherein a plurality of electrode pads arranged in a matrix form and a recognition mark are arranged over the second main surface of the first semiconductor chip,wherein a plurality of projection electrodes corresponding to the electrode pads of the first semiconductor chip is arranged over the first main surface of the second semiconductor chip. The disclosure of Japanese Patent Application No. 2013-061088 filed on Mar. 22, 2013 including the specification, drawings and abstract is incorporated herein by reference in its entirety.The present invention relates to a manufacturing technology of a semiconductor device, and for example, to a technology effective in applying to assembly of a semiconductor device having a semiconductor chip in which through electrodes have been formed.For example, in Japanese Patent Laid-Open No. 2009-260373 (Patent Document 1), there is disclosed a structure in which an alignment mark is formed on a surface where a pad of a semiconductor chip has been formed, and in which the alignment mark is used as a test-dedicated pad which a probe and the like touch.In addition, for example, in Japanese Patent Laid-Open No. 2005-175263 (Patent Document 2), there is disclosed a technology in which alignment marks that are formed in the same step as a step of forming through electrodes and that have the same ...

NONVOLATILE MEMORY DEVICES

Nonvolatile memory device includes memory cell region including a first metal pad and a second metal pad, peripheral circuit region including a third metal pad and a fourth metal pad, vertically connected to the memory cell region. The nonvolatile memory device includes a page buffer circuit including page buffers to sense data from selected memory cells, each including two sequential sensing operations to determine one data state, and each of the page buffers including a latch to sequentially store results of the two sequential sensing operations. The nonvolatile memory device includes control circuit in the peripheral circuit region, to control the page buffers to store result of the first read operation, reset the latches after completion of the first read operation, and control the page buffers to perform the second read operation based on a valley determined based on the result of the first read operation. 1. A nonvolatile memory device comprising:a memory cell region including a first metal pad and a second metal pad;a peripheral circuit region including a third metal pad and a fourth metal pad, the peripheral circuit region being connected to the memory cell region by the first metal pad, the second metal pad, the third metal pad and the fourth metal pad;a memory cell array in the memory cell region, the memory cell array including a plurality of pages, each of the plurality of pages including a plurality of memory cells, each of the plurality of memory cells storing a plurality of data bits, each of the plurality of data bits being selectable by a different threshold voltage; sense data from selected memory cells among the plurality of memory cells through the plurality of bit-lines, the second metal pad and the fourth metal pad, and', 'perform a first read operation and a second read operation, each including two sequential sensing operations to determine one data state, and each of the plurality of page buffers including a latch, among a plurality of ...

Semiconductor assemblies including vertically integrated circuits and methods of manufacturing the same

Semiconductor assemblies including thermal management configurations for reducing heat transfer between vertically stacked devices and associated systems and methods are disclosed herein. In some embodiments, the semiconductor assemblies comprise at least one memory device mounted over a logic device with a thermally conductive layer, a thermal-insulator interposer, or a combination thereof disposed between the memory device and the logic device. The thermally conductive layer includes a structure configured to transfer the thermal energy across a horizontal plane. The thermal-insulator interposer includes a structure configured to reduce heat transfer between the logic device and the memory device.

MEMORY DEVICES WITH THREE-DIMENSIONAL STRUCTURE

A memory device includes a peripheral circuit layer, a first memory layer provided on the peripheral circuit layer, an inter-metal layer provided on the first memory layer, and a second memory layer provided on the inter-metal layer. The peripheral circuit layer includes a first substrate and a peripheral circuit provided on the first substrate. The first memory layer includes a first memory structure electrically connected to the peripheral circuit through metal bonding pads. The inter-metal layer includes intermediate pads electrically connected to the peripheral circuit through metal bonding pads. The second memory layer includes a second memory structure electrically connected with the intermediate pads and a second substrate provided on the second memory structure. The peripheral circuit, the first memory structure, and the second structure are provided between the first substrate and the second substrate. 1. A memory device comprising: a first substrate;', 'a peripheral circuit provided on the first substrate;', 'first metal bonding pads; and', 'second metal bonding pads, 'a peripheral circuit layer including third metal bonding pads;', 'fourth metal bonding pads; and', 'a first memory structure electrically connected to the peripheral circuit through the first metal bonding pads and the third metal bonding pads;, 'a first memory layer provided on the peripheral circuit layer, the first memory layer includingan inter-metal layer provided on the first memory layer, the inter-metal layer including intermediate pads electrically connected to the peripheral circuit through the second metal bonding pads; and a second memory structure electrically connected with the intermediate pads; and', 'a second substrate provided on the second memory structure,, 'a second memory layer provided on the inter-metal layer, the second memory layer includingwherein the peripheral circuit, the first memory structure, and the second structure are provided between the first substrate ...

PACKAGING PROCESS AND MANUFACTURING METHOD

A manufacturing method and a packaging process are provided. A package having a first die and a second die is provided. A circuit substrate having a first warpage level is provided. The package is mounted onto the circuit substrate and then heated under an elevated temperature to bond the package to the circuit substrate. The package heated under the elevated temperature is warped with a second warpage level, and the first warpage level is substantially in conformity with the second warpage level. 1. A bonding process , comprising:providing a circuit substrate on a fixture, wherein the circuit substrate has a mounting surface and mounting portions formed on the mounting surface;performing a substrate padding process;mounting a package onto the mounting surface of the circuit substrate, wherein the package has a bottom surface and connectors formed on the bottom surface of the package; andperforming a reflow process and bonding the connectors of the package to the mounting portions of the circuit substrate.2. The process according to claim 1 , wherein performing a substrate padding process includes placing a spacer underneath the circuit substrate and between the circuit substrate and the fixture to bend the circuit substrate and turn the mounting surface into a first warped surface.3. The process according to claim 2 , wherein the package includes at least one first die and a plurality of second dies claim 2 , and placing a spacer includes placing at least one spacer beneath the circuit substrate at a position corresponding to a position of the at least one first die of the package.4. The process according to claim 3 , wherein a vertical projection of the at least one spacer is partially overlapped with a vertical projection of the at least one first die.5. The process according to claim 3 , wherein a vertical projection of the at least one spacer is fully overlapped with a vertical projection of the at least one first die.6. The process according to claim 3 , ...

Fan-Out Stacked System in Package (SIP) and the Methods of Making the Same

An embodiment package includes a first fan-out tier having a first device die, a molding compound extending along sidewalls of the first device die, and a through intervia (TIV) extending through the molding compound. One or more first fan-out redistribution layers (RDLs) are disposed over the first fan-out tier and bonded to the first device die. A second fan-out tier having a second device die is disposed over the one or more first fan-out RDLs. The one or more first fan-out RDLs electrically connects the first and second device dies. The TIV electrically connects the one or more first fan-out RDLs to one or more second fan-out RDLs. The package further includes a plurality of external connectors at least partially disposed in the one or more second fan-out RDLs. The plurality of external connectors are further disposed on conductive features in the one or more second fan-out RDLs. 1. A package comprising: a first device die;', 'a first molding compound extending along sidewalls of the first device die; and', 'a first through intervia (TIV) extending through the first molding compound;, 'a first fan-out tier comprisingone or more first fan-out redistribution layers (RDLs) over the first fan-out tier and bonded to the first device die;a second fan-out tier over the one or more first fan-out RDLs, wherein the second fan-out tier comprises a second device die bonded to the one or more first fan-out RDLs, wherein the one or more first fan-out RDLs electrically connects the first device die to the second device die;one or more second fan-out RDLs on an opposing side of the first fan-out tier from the one or more first fan-out RDLs, wherein the first TIV electrically connects the one or more first fan-out RDLs to the one or more second fan-out RDLs; anda plurality of external connectors at least partially disposed in the one or more second fan-out RDLs, wherein the plurality of external connectors are further disposed on conductive features in the one or more second fan ...

THREE-DIMENSIONAL INTEGRATED FAN-OUT WAFER LEVEL PACKAGE

An integrated fan-out wafer level package houses a semiconductor package having a first semiconductor die encapsulated by a dielectric compound. A plurality of redistribution layers are formed on a first side of the semiconductor package which are in electrical contact with contact pads of the first semiconductor die. A plurality of solder balls located on the first side of the semiconductor package is electrically connected to the contact pads of the semiconductor die via the redistribution layers. A second semiconductor die is further attached to the first side of the semiconductor package and is electrically connected to the contact pads of the first semiconductor die via the redistribution layers. 1. An integrated fan-out wafer level package comprising:a semiconductor package comprising a first semiconductor die encapsulated by a dielectric compound;a plurality of redistribution layers formed on a first side of the semiconductor package in electrical contact with contact pads of the first semiconductor die;a plurality of solder balls located on the first side of the semiconductor package and electrically connected to the contact pads of the semiconductor die via the redistribution layers; anda second semiconductor die attached to the first side of the semiconductor package and electrically connected to the contact pads of the first semiconductor die via the redistribution layers; anda plurality of wire bond pads formed on the redistribution layers on the first side of the semiconductor package and wire bonds directly connecting the second semiconductor die to the wire bond pads.2. The integrated fan-out wafer level package as claimed in claim 1 , wherein the plurality of solder balls is arranged for electrically mounting the integrated fan-out wafer level package onto a printed circuit board.3. The integrated fan-out wafer level package as claimed in claim 1 , wherein the first semiconductor die comprises an application processor chip.4. The integrated fan-out ...

Single-Shot Encapsulation

A semiconductor device includes a semiconductor wafer. A plurality of pillar bumps is formed over the semiconductor wafer. A solder is deposited over the pillar bumps. The semiconductor wafer is singulated into a plurality of semiconductor die after forming the pillar bumps while the semiconductor wafer is on a carrier. An encapsulant is deposited around the semiconductor die and pillar bumps while the semiconductor die remains on the carrier. The encapsulant covers an active surface of the semiconductor die between the pillar bumps. 1. A method of making a semiconductor device , comprising:providing a semiconductor wafer;forming a plurality of pillar bumps over the wafer;singulating the semiconductor wafer into a plurality of semiconductor die; anddepositing an encapsulant over the semiconductor die with the pillar bumps exposed from the encapsulant.2. The method of claim 1 , wherein the pillar bumps include solder caps.3. The method of claim 2 , wherein the solder caps include lead-free solder.4. The method of claim 1 , further including transfer-mounting the semiconductor die prior to depositing the encapsulant.5. The method of claim 1 , further including singulating the semiconductor die through the encapsulant.6. The method of claim 5 , further including singulating the semiconductor die with a plurality of semiconductor die packaged together.7. A method of making a semiconductor device claim 5 , comprising:providing a semiconductor die;forming a pillar bump over the semiconductor die;forming a solder cap over the pillar bump; anddepositing an encapsulant over the semiconductor die, pillar bump, and solder cap.8. The method of claim 7 , wherein a surface of the encapsulant is coplanar with a surface of the solder cap.9. The method of claim 7 , further including disposing the semiconductor die over a substrate after depositing the encapsulant claim 7 , wherein the encapsulant contacts the substrate.10. The method of claim 9 , further including reflowing the ...

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING THE SAME

A manufacturing method of a semiconductor device according to an embodiment comprises, bonding a first semiconductor substrate and a second semiconductor substrate to form a stack, filling a first fill material having a first viscosity in a gap located between an outer peripheral portion of the first semiconductor substrate and an outer peripheral portion of the second semiconductor substrate, filling a second fill material having a second viscosity higher than the first viscosity in the gap so as to be adjacent to the first fill material after filling the first fill material in the gap and thinning the second semiconductor. 1. A semiconductor device manufacturing method , comprising:bonding a first semiconductor substrate and a second semiconductor substrate, to form a stack;filling a first fill material having a first viscosity in a gap located between an outer peripheral portion of the first semiconductor substrate and an outer peripheral portion of the second semiconductor substrate;filling a second fill material having a second viscosity higher than the first viscosity in the gap so as to be adjacent to the first fill material after filling the first fill material in the gap; andthinning the second semiconductor substrate.2. The semiconductor device manufacturing method according to claim 1 , wherein the first fill material includes an organic compound claim 1 , and the second fill material includes a glass material or an inorganic polymer.3. The semiconductor device manufacturing method according to claim 2 , wherein claim 2 , in the cross-sectional view of the stack claim 2 ,the gap is provided along a surface of the first semiconductor substrate and a surface of the second semiconductor substrate, and includes a first gap portion and a second gap portion,the first gap portion locates closer a center of the first semiconductor substrate and a center of the second semiconductor substrate than an end of the first semiconductor substrate and an end of the second ...

LOGIC DRIVE USING STANDARD COMMODITY PROGRAMMABLE LOGIC IC CHIPS COMPRISING NON-VOLATILE RANDOM ACCESS MEMORY CELLS

A multi-chip package includes a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a truth table, wherein the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprises multiple non-volatile memory cells therein configured to store multiple resulting values of the truth table, and a programmable logic block therein configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output; and a memory chip coupling to the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip, wherein a data bit width between the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and the memory chip is greater than or equal to 64. 1. A chip package comprising:a non-volatile memory cell configured to store resulting data of a look-up table (LUT) therein;a sense amplifier configured to sense input data thereof associated with the resulting data of the look-up table (LUT) stored in the non-volatile memory cell to generate output data of the sense amplifier;a logic circuit comprising a static-random-access-memory (SRAM) cell configured to store first data therein associated with the output data of the sense amplifier, and a selection circuit comprising a first set of input points for a first input data set for input data of a logic operation and a second set of input points for a second input data set having second data associated with the first data stored in the static-random-access-memory (SRAM) cell, wherein the selection circuit is configured to select, in accordance with the first input data set, input data from the second input data set as output data of the logic operation; anda plurality of metal bumps at a bottom of the chip package, wherein the plurality of metal bumps comprise five metal bumps arranged in a line.2. The chip package of claim 1 , wherein the sense amplifier and logic circuit are provided by a ...

Thermal transfer structures for semiconductor die assemblies

Several embodiments of the present technology are described with reference to a semiconductor die assembly and processes for manufacturing the assembly. In some embodiments of the present technology, a semiconductor die assembly includes a stack of semiconductor dies attached to a thermal transfer structure (also known as a “heat spreader,” “lid,” or “thermal lid”). The thermal transfer structure conducts heat away from the stack of semiconductor dies. Additionally, the assembly can include molded walls fabricated with molding material to support the thermal transfer structure.

Thermally enhanced package to reduce thermal interaction between dies

A method of reducing heat flow between IC chips and the resulting device are provided. Embodiments include attaching plural IC chips to an upper surface of a substrate; forming a lid over the IC chips; and forming a slit through the lid at a boundary between adjacent IC chips.

Embedded structures for package-on-package architecture

Electronic assemblies including substrates and their manufacture are described. One assembly includes a die embedded in a dielectric layer in a multilayer substrate, and a dielectric region embedded in the dielectric layer in the multilayer substrate. The multilayer substrate includes a die side and a land side, with the first dielectric region and the dielectric layer extending to the die side. A plurality of vias are positioned within the first dielectric region, the vias extending to pads on the die side. Other embodiments are described and claimed.

Interconnect structures with intermetallic palladium joints and associated systems and methods

Interconnect structures with intermetallic palladium joints are disclosed herein. In one embodiment, a method of forming an interconnect structure includes depositing a first conductive material comprising nickel on a first conductive surface of a first die, and depositing a second conductive material comprising nickel on a second conductive surface of a second die spaced apart from the first surface. The method further includes depositing a third conductive material on the second conductive material, and thermally compressing tin/solder between the first and third conductive materials to form an intermetallic palladium joint that extends between the first conductive material and the second conductive material such that one end of the intermetallic palladium joint is bonded directly to the first conductive material and an opposite end of the intermetallic palladium joint is bonded directly to the second conductive material.

METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE

A method for manufacturing a semiconductor package includes following operations. A die having a first surface and a second surface opposite to the first surface is provided. A polymeric film is disposed over the second surface of the die. An adhesive film is provided. The die and the polymeric film are attached to a carrier substrate through the adhesive film. The die, the polymeric film and the adhesive film are molded with a molding compound. The polymeric film is sandwiched between the die and the adhesive film upon attaching to the carrier substrate. 1. A method for manufacturing a semiconductor package , comprising:providing a die comprising a first surface and a second surface opposite to the first surface;disposing a polymeric film over the second surface of the die;providing an adhesive film;attaching the die and the polymeric film to a carrier substrate through the adhesive film; andmolding the die, the polymeric film and the adhesive film with a molding compound,wherein the polymeric film is sandwiched between the die and the adhesive film upon attaching to the carrier substrate.2. The method of claim 1 , further comprising removing a portion of the die from the second surface before disposing the polymeric film.3. The method of claim 2 , wherein a thickness of the portion of the die being removed is substantially equal to a thickness of the polymeric film.4. The method of claim 1 , wherein the die comprises a first coefficient of thermal expansion (CTE) claim 1 , the polymeric film comprises a second CTE claim 1 , the adhesive film comprises a third CTE claim 1 , and the second CTE of the polymeric film is between the first CTE of the die and the third CTE of the adhesive film.5. The method of claim 4 , wherein the molding compound comprises a fourth CTE claim 4 , and the second CTE of the polymeric film is closer to the fourth CTE of the molding compound than to the first CTE of the die and to the third CTE of the adhesive film.6. The method of claim 1 ...

METAL-FREE FRAME DESIGN FOR SILICON BRIDGES FOR SEMICONDUCTOR PACKAGES

Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate. 1. A semiconductor structure , comprising:a substrate having an insulating layer thereon, the substrate having a perimeter, and the substrate comprising silicon;a metallization structure on the insulating layer, the metallization structure comprising conductive routing in a dielectric material stack;a first metal guard ring in the dielectric material stack and continuous around the conductive routing;a second metal guard ring in the dielectric material stack and continuous around the first metal guard ring;a plurality of staggered mini guard rings between the first metal guard ring and the second metal guard ring; anda metal-free region of the dielectric material stack surrounding the second metal guard ring, the metal-free region adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.2. The semiconductor structure of claim 1 , wherein at least one of the first metal guard ring or the second metal guard ring provides a hermetic seal for the metallization structure.3. The semiconductor structure of claim 1 , further comprising:a metal feature between the first metal ...

SEMICONDUCTOR PACKAGE

A semiconductor package includes a substrate, a first chip on the substrate, a second chip on the substrate and arranged side-by-side with the first chip, and a support structure on the second chip. A width of the support structure is equal to or greater than a width of the second chip. 1. A semiconductor package , comprising:a substrate;at least one first chip on an upper surface of the substrate;a second chip on the upper surface of the substrate and located beside the at least one first chip as viewed in a plan view; anda support structure on the second chip,wherein a width of the support structure, in a direction parallel to the upper surface of the substrate, is equal to or greater than a width of the second chip in said direction.2. The semiconductor package of claim 1 , wherein a distance from the upper surface of the substrate to a top surface of the support structure is substantially the same as a distance from the upper surface of the substrate to a top surface of an uppermost one the at least one first chip.3. The semiconductor package of claim 1 , wherein the support structure comprises a block of insulating material claim 1 , a dummy chip claim 1 , or a memory chip.4. The semiconductor package of claim 1 , wherein the support structure comprises silicon (Si).5. The semiconductor package of claim 1 , wherein each said at least one first chip is a memory chip claim 1 , andthe second chip is a logic chip.6. The semiconductor package of claim 1 , wherein the at least one first chip is wire-bonded to the substrate claim 1 , andthe second chip is flip-chip bonded to the substrate.7. The semiconductor package of claim 5 , wherein the at least one first chip comprises a stack of first chips.8. The semiconductor package of claim 1 , further comprising at least one third chip on the at least one first chip and the second chip.9. The semiconductor package of claim 1 , further comprising at least one third chip on the at least one first chip and the support ...

Systems and Methods for Self Test Circuit Security

The present inventions are related to systems and methods for circuit implementation, and more particularly to systems and methods for securing data in a circuit. 1. A semiconductor device , the device comprising:a wafer upon which an overall circuit is implemented, wherein the overall circuit includes: a first cell, a second cell, an internal only pad, an external pad, a gate circuit, and a test circuit;wherein the test circuit is coupled to an output of the second cell and an output of the gate circuit;wherein the overall circuit is selectably operable in a test mode or a functional mode based upon data received via the external pad; the output of the gate circuit follows the output of the first cell when the internal only pad is asserted at a first level and the test mode of the overall circuit is selected; and', 'the output of the gate circuit is fixed regardless of the output of the first cell when the internal only pad is asserted at a second level and the test mode of the overall circuit is selected., 'wherein a first input of the gate circuit is coupled to the internal only pad and a second input of the gate circuit is coupled to an output of the first cell, and wherein the gate circuit is configured such that2. The device of claim 1 , wherein the output of the gate circuit is configured to follow the output of the first cell when the functional mode of the overall circuit is selected.3. The device of claim 1 , the device further comprising:a test system electrically coupled to the wafer, wherein the test system is operable to assert the internal only pad at the first level.4. The device of claim 3 , wherein the test system is further operable to assert the external pad such that the test mode of the overall circuit is selected.5. The device of claim 1 , the device further comprising:a chip package encapsulating the wafer and including a plurality of pins, wherein the external pad is bonded to one of the plurality of pins, and wherein the internal only pad ...

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE

A semiconductor device includes a semiconductor substrate having a first surface and a second surface, which are opposite to each other, an active pattern protruding from the first surface of the semiconductor substrate, the active pattern including a source/drain region, a power rail electrically connected to the source/drain region, a power delivery network disposed on the second surface of the semiconductor substrate, and a penetration via structure penetrating the semiconductor substrate and electrically connected to the power rail and the power delivery network. The penetration via structure includes a first conductive pattern electrically connected to the power rail and a second conductive pattern electrically connected to the power delivery network. The first conductive pattern includes a material different from the second conductive pattern. 1. A semiconductor device , comprising:a semiconductor substrate having a first surface and a second surface, which are opposite to each other;an active pattern protruding from the first surface of the semiconductor substrate, the active pattern including a source/drain region;a power rail electrically connected to the source/drain region;a power delivery network disposed on the second surface of the semiconductor substrate; anda penetration via structure penetrating the semiconductor substrate and electrically connected to the power rail and the power delivery network,wherein the penetration via structure comprises:a first conductive pattern electrically connected to the power rail; anda second conductive pattern electrically connected to the power delivery network,wherein the first conductive pattern comprises a material different from the second conductive pattern.2. The semiconductor device of claim 1 , wherein the penetration via structure further comprises:a barrier pattern interposed between the semiconductor substrate and the first conductive pattern and between the semiconductor substrate and the second ...

METHODS FOR FORMING THREE-DIMENSIONAL MEMORY DEVICES WITH SUPPORTING STRUCTURE FOR STAIRCASE REGION

Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A peripheral circuit is formed on a first substrate. A first semiconductor layer is formed on a second substrate. A supporting structure and a second semiconductor layer coplanar with the supporting structure are formed on the first semiconductor layer. A memory stack is formed above the supporting structure and the second semiconductor layer. The memory stack has a staircase region overlapping the supporting structure. A channel structure extending vertically through the memory stack and the second semiconductor layer into the first semiconductor layer is formed. The first substrate and the second substrate are bonded in a face-to-face manner. 1. A method for forming a three-dimensional (3D) memory device , comprising:sequentially forming a first semiconductor layer, a first block layer, and a sacrificial layer on a substrate;forming a block plug extending vertically through the sacrificial layer and the first block layer to divide the sacrificial layer into a supporting portion and a sacrificial portion;forming a dielectric stack above the sacrificial layer and having a staircase region, such that the supporting portion of the sacrificial layer is below and overlaps the staircase region of the dielectric stack;forming a channel structure extending vertically through the dielectric stack, the sacrificial portion of the sacrificial layer, and the first block layer, into the first semiconductor layer;forming an opening extending vertically through the dielectric stack to expose part of the sacrificial portion of the sacrificial layer; andreplacing, through the opening, the sacrificial portion of the sacrificial layer with a second semiconductor layer coplanar with the supporting portion of the sacrificial layer.2. The method of claim 1 , wherein replacing the sacrificial portion of the sacrificial layer with the second ...

SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE

A semiconductor device includes: a substrate extending in a first direction and a second direction intersecting with the first direction; a plurality of input/output pads disposed at one side of the substrate; a first circuit adjacent to the input/output pads in the first direction; a second circuit disposed to be spaced farther apart from the input/output pads in the first direction than the first circuit; a first memory cell array overlapping the first circuit; a second memory cell array overlapping the second circuit; first metal source patters overlapping the first memory cell array and being spaced apart from each other in the second direction; and a second metal source pattern overlapping the second memory cell array and formed to have a width wider than a width of each of the first metal source patterns in the second direction. 1. A semiconductor memory device comprising:a substrate extending in a first direction and a second direction intersecting with the first direction;a plurality of input/output pads disposed at one side of the substrate;a first circuit adjacent to the input/output pads in the first direction;a second circuit disposed to be spaced farther apart from the input/output pads in the first direction than the first circuit;a first memory cell array overlapping the first circuit;a second memory cell array overlapping the second circuit;first metal source patters overlapping the first memory cell array, wherein the first metal source patterns are spaced apart from each other in the second direction; anda second metal source pattern overlapping the second memory cell array, wherein the second metal source pattern has a width wider than a width of each of the first metal source patterns in the second direction.2. The semiconductor memory device of claim 1 , further comprising a transmission line overlapping the first memory cell array between the first metal source patterns claim 1 ,wherein the transmission line is configured to transmit an ...

STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH HIGH EFFICIENCY THERMAL PATHS AND MOLDED UNDERFILL

Semiconductor die assemblies having high efficiency thermal paths and molded underfill material. In one embodiment, a semiconductor die assembly comprises a first die and a plurality of second dies. The first die has a first functionality, a lateral region, and a stacking site. The second dies have a different functionality than the first die, and the second dies are in a die stack including a bottom second die mounted to the stacking site of the first die and a top second die defining a top surface of the die stack. A thermal transfer structure is attached to at least the lateral region of the first die and has a cavity in which the second dies are positioned. An underfill material is in the cavity between the second dies and the thermal transfer structure, and the underfill material covers the top surface of the die stack. 116-. (canceled)17. A method of manufacturing a semiconductor device , comprising:forming a semiconductor die having a stacking area and an outer region laterally extending in a first direction;attaching a die stack to the stacking area;attaching a thermal transfer structure to the outer region, the thermal transfer structure having a cavity laterally extending in a second direction generally perpendicular to the first direction; andfilling the cavity with an underfill material.18. The method of claim 17 , further comprising filling the cavity such that the underfill material extends to a top surface of the die stack.19. The method of claim 17 , further comprising disposing the thermal transfer structure at least partially surrounding the die stack.20. The method of claim 17 , wherein the semiconductor die is a first semiconductor die claim 17 , and wherein the die stack includes two or more second semiconductor dies.21. The method of claim 20 , wherein the first semiconductor die is a logic die claim 20 , and wherein the second semiconductor dies are memory dies.22. The method of claim 17 , wherein the thermal transfer structure includes an ...

Package-on-Package Structure Including a Thermal Isolation Material and Method of Forming the Same

A semiconductor device includes a first package component and a second package component. The first package component has a first die formed on a first substrate. A second package component has a second die formed on a second substrate. A thermal isolation material is attached on the first die, wherein the thermal isolation material thermally insulates the second die from the first die, and the thermal isolation material has a thermal conductivity of from about 0.024 W/mK to about 0.2 W/mK. A first set of conductive elements couples the first package component to the second package component.

Chip Structure, Wafer Structure And Method For Manufacturing The Same

A chip structure, a wafer structure and a method for manufacturing the same are provided in the present disclosure. A first chip and a second chip are bonded by bonding layers of a dielectric material. Top wiring layers are led out through bonding via holes from a back surface of a bonded chip. The bonding via holes are used for bonding and are surrounded by the bonding layers. A top wiring layer of a third chip is led out through bonding pads formed in a bonding layer. The bonding via holes are aligned with and bonded to the bonding pads to achieve bonding of the three chips. The top wiring layer of the third chip is led out from the back surface of the third chip through a lead-out pad. 1. A chip structure , comprising:a first chip and a second chip, wherein a front surface of the first chip is covered with a first bonding layer of a first dielectric material, a front surface of the second chip is covered with a second bonding layer of a second dielectric material, and the first bonding layer is bonded to the second bonding layer;a third bonding layer of a third dielectric material covering a back surface of the second chip;bonding via holes, comprising a first bonding via hole extending from the third bonding layer to a first top wiring layer of the first chip and a second bonding via hole extending from the third bonding layer to a second top wiring layer of the second chip;a third chip, comprising a third top wiring layer, a fourth boding layer and bonding pads, wherein the fourth boding layer is made of a fourth dielectric material and is arranged on the third top wiring layer and convers a front surface of the third chip, each of the bonding pads extends through the fourth bonding layer and is connected to the third top wiring layer, the third bonding layer is bonded to the fourth bonding layer, and the bonding via holes are bonded to the bonding pads; anda lead-out pad extending from a back surface of the third chip to the third top wiring layer.2. The chip ...

SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor memory device includes a stack disposed over a substrate defined with cell and connection areas; channel structures passing through the stack in the cell area; and slits defined in the stack. The stack includes first dielectric layers separately staked in the cell and connection areas; electrode layers disposed alternately with the first dielectric layers in the cell area and a periphery of the connection area adjacent to the slits; and second dielectric layers disposed alternately with the first dielectric layers in a central part of the connection area distant from the slits. A distance between the slits in the connection area is larger than a distance between the slits in the cell area, and, at a boundary between the periphery and the central part of the connection area, the electrode layers and the second dielectric layers disposed at the same layers are in contact with each other. 1. A semiconductor memory device comprising:a stack with a cell area and a connection area disposed over a substrate;a plurality of channel structures passing through the stack in the cell area; anda plurality of slits,the stack comprising:a plurality of first dielectric layers;a plurality of electrode layers alternately stacked with the plurality of first dielectric layers in the cell area and in a periphery of the connection area; anda plurality of second dielectric layers alternately stacked with the plurality of first dielectric layers in a center of the connection area,wherein a distance between the slits in the connection area is greater than a distance between the slits in the cell area, andwherein, at an intersection of the periphery and the center of the connection area, one of the plurality of the electrode layers and one of the plurality of the second dielectric layers are in contact with each other.2. The semiconductor memory device according to claim 1 , further comprising:a plurality of contact plugs passing through the first and second dielectric layers ...

Pre-package and methods of manufacturing semiconductor package and electronic device using the same

Methods of fabricating semiconductor packages are provided. One of the methods includes forming a protection layer including metal on a first surface of a substrate to cover a semiconductor device disposed on the first surface of the substrate, attaching a support substrate to the protection layer by using an adhesive member, processing a second surface of the substrate opposite to the protection layer to remove a part of the substrate, and detaching the support substrate from the substrate.

Semiconductor Die Connection System and Method

A system and method for connecting semiconductor dies is provided. An embodiment comprises connecting a first semiconductor die with a first width to a second semiconductor die with a larger second width and that is still connected to a semiconductor wafer. The first semiconductor die is encapsulated after it is connected, and the encapsulant and first semiconductor die are thinned to expose a through substrate via within the first semiconductor die. The second semiconductor die is singulated from the semiconductor wafer, and the combined first semiconductor die and second semiconductor die are then connected to another substrate. 1. A semiconductor device comprising:a first die with a first width having a first side and a second side opposite to the first side;a through substrate via formed in the first die, wherein an edge of the through substrate via is exposed at the second side of the first die;a second die with a second width having a first side and a second side, wherein the first side of the second die is bonded to the first side of the first die, and the second width is larger than the first width; andan encapsulant extending between a sidewall of first die and a surface of the first side of second die.2. The semiconductor device of claim 1 , further comprising a redistribution layer in connection with the through substrate via.3. The semiconductor device of claim 1 , further comprising a printed circuit board bonded to the first die.4. The semiconductor device of claim 3 , further comprising solder balls located between the first die and the printed circuit board.5. The semiconductor device of claim 1 , wherein the first die is a logic die.6. The semiconductor device of claim 5 , wherein the second die is a memory die.7. The semiconductor device of claim 1 , wherein the first die and the second die are in a chip on memory architecture.8. A semiconductor device comprising:a first die with a first width over a second die with a second width, wherein the ...

4D DEVICE, PROCESS AND STRUCTURE

A 4D device comprises a 2D multi-core logic and a 3D memory stack connected through the memory stack sidewall using a fine pitch T&J connection. The 3D memory in the stack is thinned from the original wafer thickness to no remaining Si. A tongue and groove device at the memory wafer top and bottom surfaces allows an accurate stack alignment. The memory stack also has micro-channels on the backside to allow fluid cooling. The memory stack is further diced at the fixed clock-cycle distance and is flipped on its side and re-assembled on to a template into a pseudo-wafer format. The top side wall of the assembly is polished and built with BEOL to fan-out and use the T&J fine pitch connection to join to the 2D logic wafer. The other side of the memory stack is polished, fanned-out, and bumped with C4 solder. The invention also comprises a process for manufacturing the device. In another aspect, the invention comprises a 4D process and device for over 50× greater than 2D memory density per die and an ultra high density memory. 161-. (canceled)62. An article of manufacture comprising a 4D device.63. The device of which includes a vertically stacked 3D component comprising at least one of a 2D-in-4D format claim 62 , 3D-in-4D format claim 62 , and 2D/3D-in-4D format claim 62 , connected to a horizontally stacked component comprising at least one of a 2D format and a 3D format.64. The device of wherein said horizontally stacked component comprises a 2D planar multicore logic device (2D).65. The device of wherein said horizontally stacked component comprises a 3D multi-stacked device with through-Si-vias (TSV) comprising at least one of TSV and 3D-TSV.66. The device of wherein said horizontally stacked component comprises at least one of a voltage regulating module (VRM) claim 63 , memory claim 63 , logic claim 63 , optoelectronics (O-E) claim 63 , III-V device claim 63 , micro-electro-mechanical (MEMS) stacks with TSV in the 3D stacks which comprises a 3D-TSV-combination.67. ...

Embedded chip packages and methods for manufacturing an embedded chip package

A method for manufacturing an embedded chip package is provided. The method may include: forming electrically conductive lines over a substrate; placing the substrate next to a chip arrangement comprising a chip, the chip comprising one or more contact pads, wherein one or more of the electrically conductive lines are arranged proximate to a side wall of the chip; and forming one or more electrical interconnects over the chip arrangement to electrically connect at least one electrically conductive line to at least one contact pad.

Flip-chip, face-up and face-down centerbond memory wirebond assemblies

A microelectronic assembly can include a substrate having first and second surfaces and an aperture extending therebetween, the substrate having terminals. The assembly can also include a first microelectronic element having a front surface facing the first surface of the substrate, a second microelectronic element having a front surface facing the first microelectronic element and projecting beyond an edge of the first microelectronic element, first and second leads electrically connecting contacts of the respective first and second microelectronic elements to the terminals, and third leads electrically interconnecting the contacts of the first and second microelectronic elements. The contacts of the first microelectronic element can be exposed at the front surface thereof adjacent the edge thereof. The contacts of the second microelectronic element can be disposed in a central region of the front surface thereof. The first, second, and third leads can have portions aligned with the aperture.

PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS

A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer. 1. A structure comprising:a substrate having a first region and a second region, the substrate also having a first surface and a second surface remote from the first surface, wherein the first surface extends in first and second lateral directions to define a first plane;electrically conductive elements exposed at the first surface of the substrate within the second region;wire bonds having bases bonded to respective ones of the conductive elements and free ends remote from the substrate and remote from the bases, at least one of the wire bonds having a shape such that the at least one wire bond defines an axis between the free end and the base thereof coincident with a side surface of the at least one wire bond and such that the at least one wire bond defines a second plane, a bent portion of the at least one wire bond extending away from the axis within the second plane, wherein the entire at least one wire bond is positioned on one side of the axis and a substantially straight portion of the at least one wire bond extends between the free end ...

3D Semiconductor Package Interposer with Die Cavity

Disclosed herein is a method of forming a device, comprising mounting a plurality of first interconnects on one or more first integrated circuit dies. One or more second integrated circuit dies are mounted on a first side of an interposer. The interposer is mounted at a second side to the first integrated circuit dies, the plurality of first interconnects disposed outside of the interposer. The interposer is mounted to a first side of a substrate by attaching the first interconnects to the substrate, the substrate in signal communication with one or more of the first integrated circuit dies through the first interconnects. 1. A device , comprising:a substrate having a top surface;an interposer over the top surface of the substrate, the interposer being connected to the substrate by first interconnects;a first integrated circuit die connected to a first side of the interposer by first connectors;a second integrated circuit die connected to a second side of the interposer opposite the first side by second connectors, the second integrated circuit die having a smaller footprint than the interposer; anda fan-out structure disposed over a top surface of the interposer and extending beyond outermost edges of the interposer, wherein the fan-out structure is electrically connected to second interconnects, the second interconnects in contact with the top surface of the substrate.2. The device of claim 1 , further comprising third connectors connecting the fan-out structure to the second integrated circuit die.3. The device of claim 1 , further comprising a cavity in the top surface of the substrate claim 1 , wherein the first integrated circuit die extends into the cavity.4. The device of claim 1 , further comprising:a first molding compound on sidewalls of the interposer, the first interconnects, and the second interconnects; anda second molding compound on the first molding compound, the fan-out structure, and the second integrated circuit die.5. The device of claim 1 , ...

INTERCONNECT STRUCTURE WITH REDUNDANT ELECTRICAL CONNECTORS AND ASSOCIATED SYSTEMS AND METHODS

Semiconductor die assemblies having interconnect structures with redundant electrical connectors are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die, a second semiconductor die, and an interconnect structure between the first and the second semiconductor dies. The interconnect structure includes a first conductive film coupled to the first semiconductor die and a second conductive film coupled to the second semiconductor die. The interconnect structure further includes a plurality of redundant electrical connectors extending between the first and second conductive films and electrically coupled to one another via the first conductive film. 1. A semiconductor device , comprising:a semiconductor substrate;a dielectric material over the substrate;a conductive trace extending at least partially through the dielectric material; and a conductive member coupled to the conductive trace, and', 'a conductive bond material bonded to the conductive member,, 'a plurality of redundant electrical connectors extending from the conductive trace and through at least a portion of the dielectric material, wherein each of the redundant electrical connectors includes—'}wherein all of the redundant electrical connectors are coupled to the conductive trace.2. The semiconductor device of wherein the dielectric includes a plurality of openings exposing portions of the conductive trace claim 1 , wherein the redundant electrical connectors are formed in the openings.3. The semiconductor device of wherein the conductive member comprises copper and the bond material comprises a solder material.4. The semiconductor device of wherein the conductive member includes an end portion claim 1 , and wherein the conductive bond material and conductive member form a conductive joint at the end portion.5. The semiconductor device of claim 1 , further comprising a through-substrate via (TSV) extending at least partially through the substrate claim 1 , ...

NON-VOLATILE MEMORY DEVICE AND PROGRAMMING METHOD THEREOF

A non-volatile memory device includes a memory cell array including memory cells respectively connected to bit lines; and a control logic unit configured to control a program operation with respect to the memory cells. The control logic unit is configured to perform a normal program verify operation with respect to the memory cells by using a normal program verify condition, during the program operation, and, based on a suspend command that is received during the program operation, perform an initial program verify operation with respect to the memory cells by using an initial program verify condition that is different from the normal program verify condition. 1. A non-volatile memory device comprising:a memory cell array including memory cells respectively connected to bit lines; anda control logic unit configured to control a program operation with respect to the memory cells, wherein the control logic unit is further configured to:perform a normal program verify operation with respect to the memory cells by using a normal program verify condition, during the program operation, andbased on a suspend command that is received during the program operation, perform an initial program verify operation with respect to the memory cells by using an initial program verify condition that is different from the normal program verify condition,wherein the normal program verify condition comprises a normal program verify voltage, andthe initial program verify condition comprises an initial program verify voltage that is different from the normal program verify voltage.2. The non-volatile memory device of claim 1 , further comprising:a row decoder configured to drive a selected word line connected to the memory cells,wherein the row decoder is further configured to apply the normal program verify voltage to the selected word line during the normal program verify operation and to apply the initial program verify voltage to the selected word line during the initial program verify ...

MEMORY SYSTEM INCLUDING A NONVOLATILE MEMORY DEVICE, AND AN ERASING METHOD THEREOF

A fail detecting method of a memory system including a nonvolatile memory device and a memory controller, the fail detecting method including: counting, by the memory controller, the number of erases of a word line connected to a pass transistor; issuing a first erase command, by the memory controller, when the number of erases reaches a reference value; applying a first voltage, by the nonvolatile memory device, in response to the first erase command, that causes a gate-source potential difference of the pass transistor to have a first value; detecting, by the memory controller, a leakage current in a word line, after the applying of the first voltage; and determining, by the memory controller, the word line as a fail when a leakage voltage caused by the leakage current is greater than a first threshold value. 1. A fail detecting method of a memory system comprising a nonvolatile memory device and a memory controller , the fail detecting method comprising:counting, by the memory controller, the number of erases of a word line connected to a pass transistor;issuing a first erase command, by the memory controller, when the number of erases reaches a reference value;applying a first voltage, by the nonvolatile memory device, in response to the first erase command, that causes a gate-source potential difference of the pass transistor to have a first value;detecting, by the memory controller, a leakage current in a word line, after the applying of the first voltage; anddetermining, by the memory controller, the word line as a fail when a leakage voltage caused by the leakage current is greater than a first threshold value.2. The fail detecting method of claim 1 , wherein the applying of the first voltage comprises increasing a source terminal voltage of the pass transistor.3. The fail detecting method of claim 1 , wherein the applying of the first voltage comprises decreasing a gate terminal voltage of the pass transistor.4. The fail detecting method of claim 1 , ...

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, SOLID-STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS

A method of manufacturing a semiconductor device includes bonding a first semiconductor wafer including a first substrate and a first insulating layer formed to contact one surface of the first substrate, and a second semiconductor wafer including a second substrate and a second insulating layer, forming a third insulating layer, performing etching so that the second insulating layer remains on a second wiring layer, forming a first connection hole, forming an insulating film on the first connection hole, performing etching of the second insulating layer and the insulating film, forming a second connection hole, and forming a first via formed in inner portions of the connection holes and connected to the second wiring layer, wherein a diameter of the first connection hole formed on the other surface of the first substrate is greater than a diameter of the first connection hole formed on the third insulating layer. 1. A method of manufacturing a semiconductor device comprising:laminating a first semiconductor wafer including a first substrate and a first insulating layer which is formed so as to come into contact with one surface of the first substrate, and a second semiconductor wafer including a second substrate and a second insulating layer which is formed so as to come into contact with one surface of the second substrate and bonding the first semiconductor wafer and the second semiconductor wafer to each other;forming a third insulating layer on the other surface of a side opposite to the one surface of the first substrate;penetrating the third insulating layer, the first substrate, and the first insulating layer, performing etching so as that the second insulating layer remains on a second wiring layer which is formed in the second insulating layer, and forming a first connection hole;forming an insulating film on the first connection hole;performing etching of the second insulating layer on the second wiring layer and the insulating film, forming a second ...

THREE-DIMENSIONAL MEMORY DEVICE INCLUDING BUMP-CONTAINING BIT LINES AND METHODS FOR MANUFACTURING THE SAME

A semiconductor die can include an alternating stack of insulating layers and electrically conductive layers located on a substrate, memory stack structures extending through the alternating stack, drain regions located at a first end of a respective one of the vertical semiconductor channels of a memory stack structure, and bit lines extending over the drain regions and electrically connected to a respective subset of the drain regions. At least of a subset of the bit lines includes bump-containing bit lines. Each of the bump-containing bit lines includes a line portion and a bump portion that protrudes upward from a top surface of the line portion by a bump height. Bit line contact via structures overlie the bit lines and contact a bump portion of a respective one of the bump-containing bit lines. 1. A semiconductor structure comprising a first semiconductor die , wherein the first semiconductor die comprises:an alternating stack of insulating layers and electrically conductive layers located on a first substrate;memory stack structures extending through the alternating stack, wherein each of the memory stack structures comprises a respective vertical semiconductor channel and a respective memory film;drain regions located at a first end of a respective one of the vertical semiconductor channels;bit lines extending over the drain regions and electrically connected to a respective subset of the drain regions by at least one conductive via structure, wherein at least a subset of the bit lines comprises bump-containing bit lines, and each of the bump-containing bit lines comprises a line portion and a bump portion that protrudes upward from a top surface of the line portion by a bump height; andbit line contact via structures overlying the bit lines and contacting a bump portion of a respective one of the bump-containing bit lines.2. The semiconductor structure of claim 1 , wherein:the bit lines have a periodic pitch along a first horizontal direction and laterally ...

DEVICES, SYSTEMS, AND METHODS FOR STACKED DIE PACKAGES

A package includes a first chip stack. The first chip stack includes a first chip including first bonding structures, a second chip including second bonding structures facing the first bonding structures and bonded to the first bonding structures, and a first electrical contact on the second chip. At least a portion of the first electrical contact does not overlap with the first chip in a plan view. 1. A package , comprising: a first chip including first bonding structures;', 'a second chip including second bonding structures facing the first bonding structures and bonded to the first bonding structures; and', 'a first electrical contact on the second chip, wherein at least a portion of the first electrical contact does not overlap with the first chip in a plan view., 'a first chip stack including2. The package of claim 1 , wherein the first electrical contact is located at a first side of the second chip.3. The package of claim 2 , further comprising:a second electrical contact on the second chip and located at a second side of the second chip opposite the first side of the second chip.4. The package of claim 3 , wherein at least a portion of the second electrical contact does not overlap with the first chip in the plan view.5. The package of claim 1 , wherein claim 1 , in a cross sectional view claim 1 , a width of the first chip is less than a width of the second chip.6. The package of claim 1 , further comprising: a third chip including third bonding structures;', 'a fourth chip including fourth bonding structures facing the third bonding structures and bonded to the third bonding structures; and', 'a second electrical contact on the fourth chip, wherein at least a portion of the second electrical contact does not overlap with the third chip in the plan view; and, 'a second chip stack adhered to the first chip stack and includinga support substrate that supports the first chip stack and the second chip stack.7. The package of claim 6 , wherein claim 6 , in a ...

SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE

There are provided a semiconductor memory device and a manufacturing method of a semiconductor memory device. The semiconductor memory device includes: a peripheral circuit layer; a bonding structure disposed on the peripheral circuit layer; a channel structure disposed on the bonding structure; a first gate contact structure including a first vertical part penetrating the bonding structure and a first horizontal part intersecting with the first vertical part and extending from the first vertical part; and a first gate conductive pattern in contact with a side all of the first horizontal part, the first gate conductive pattern being spaced apart from the first vertical part, the first gate conductive pattern extending to surround the channel structure. 1. A semiconductor memory device comprising:a peripheral circuit layer;a bonding structure disposed on the peripheral circuit layer;a channel structure disposed on the bonding structure;a first gate contact structure including a first vertical part penetrating the bonding structure and a first horizontal part intersecting with the first vertical part and extending from the first vertical part; anda first gate conductive pattern in contact with a sidewall of the first horizontal part and spaced apart from the first vertical part, wherein the first gate conductive pattern extends to surround the channel structure.2. The semiconductor memory device of claim 1 , wherein the bonding structure includes a structure in which dielectric layers are bonded together.3. The semiconductor memory device of claim 1 , further comprising:a second gate conductive pattern surrounding the channel structure, the second gate conductive pattern disposed between the first gate conductive pattern and the bonding structure; anda second gate contact structure disposed between the second gate conductive pattern and the first gate contact structure,wherein the second gate contact structure includes a second vertical part penetrating the bonding ...

VERTICAL INTERCONNECTS FOR SELF SHIELDED SYSTEM IN PACKAGE (SiP) MODULES

A system in package (SiP) is disclosed that uses an EMI shield to inhibit EMI or other electrical interference on the components within the SiP. A metal shield may be formed on an upper surface of an encapsulant encapsulating the SiP. The metal shield may be electrically coupled to a ground layer in a printed circuit board (PCB) to form the EMI shield around the SiP. The metal shield may be electrically coupled to the ground layer using one or more conductive structures located in the encapsulant. The conductive structures may be located on a perimeter of the components in the SiP. The conductive structures may provide a substantially vertical connection between the substrate and the shield on the upper surface of the encapsulant. 1. A semiconductor device package , comprising:at least one device;an encapsulant at least partially encapsulating the at least one device;one or more terminals coupled to a lower surface of the at least one device;a plurality of conductive structures at least partially encapsulated in the encapsulant, wherein the plurality of conductive structures comprise discrete structures at least partially surrounding the at least one device in the encapsulant;one or more ground terminals coupled to lower surfaces of the conductive structures; anda shield positioned above the at least one device and the conductive structures, wherein the shield is electrically coupled to at least two of the conductive structures.2. The package of claim 1 , wherein the package comprises a substrate-less package.3. The package of claim 1 , wherein the at least two conductive structures electrically coupled to the shield are separately attached to the shield.4. The package of claim 1 , wherein the at least two conductive structures electrically coupled to the shield are attached to the shield using conductive material.5. The package of claim 1 , wherein the shield is positioned over the encapsulant.6. The package of claim 1 , wherein the at least one device comprises a ...

System on Integrated Chips and Methods of Forming Same

An embodiment method for forming a semiconductor package includes attaching a first die to a first carrier, depositing a first isolation material around the first die, and after depositing the first isolation material, bonding a second die to the first die. Bonding the second die to the first die includes forming a dielectric-to-dielectric bond. The method further includes removing the first carrier and forming fan-out redistribution layers (RDLs) on an opposing side of the first die as the second die. The fan-out RDLs are electrically connected to the first die and the second die. 1. A package comprising:a first semiconductor die;a second semiconductor die bonded to the first semiconductor die, wherein a first dielectric layer of the first semiconductor die is directly bonded to a second dielectric layer of the second semiconductor die;a third semiconductor die bonded to the first semiconductor die, wherein the first dielectric layer of the first semiconductor die is directly bonded to a third dielectrics layer of the third semiconductor die;a first isolation material disposed around the second semiconductor die and the third semiconductor die, wherein the second semiconductor die is physically separated from the third semiconductor die by the first isolation material; anda redistribution structure electrically connected to the first semiconductor die, the second semiconductor die, and the third semiconductor die.2. The package of claim 1 , wherein the redistribution structure is disposed on an opposing side of the first semiconductor die as the second semiconductor die and the third semiconductor die.3. The package of claim 1 , wherein the redistribution structure is electrically connected to the second semiconductor die by a conductive via extending through a second isolation material claim 1 , and wherein the first semiconductor die is physically separated from the conductive via by the second isolation material.4. The package of claim 3 , wherein the second ...

NON-VOLATILE MEMORY DEVICE

A non-volatile memory device comprises a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, a memory cell array in the memory cell region including a plurality of memory cells, each of the memory cells being connected to a plurality of word lines in the memory cell region and a plurality of bit lines in the memory cell region, and a control logic circuit in the peripheral circuit region configured to control voltages to be applied to the plurality of word lines and the plurality of bit lines. 1. A non-volatile memory device comprising:a memory cell region including a first metal pad;a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad;a memory cell array in the memory cell region including a plurality of memory cells, each of the memory cells being connected to a plurality of word lines in the memory cell region and a plurality of bit lines in the memory cell region; anda control logic circuit in the peripheral circuit region configured to control voltages to be applied to the plurality of word lines and the plurality of bit lines,wherein the control logic circuit is configured to:apply a program word line voltage with a voltage level changed stepwise to a selected word line connected to the plurality of memory cells, the program word line voltage including a first voltage level during a first time interval and a second voltage level different from the first voltage level during a subsequent second time interval;apply a program bit line voltage to a first bit line of the plurality of bit lines connected to a plurality of first memory cells, while the program word line voltage is applied to the selected word line;when the program bit line voltage has a program inhibit voltage level, inhibit the plurality of first ...

SEMICONDUCTOR PACKAGE INCLUDING AN IMAGE SENSOR CHIP AND A METHOD OF FABRICATING THE SAME

Disclosed are a semiconductor package and a method of fabricating the same. The semiconductor package may include a semiconductor chip structure, a transparent substrate disposed on the semiconductor chip structure, a dam placed on an edge of the semiconductor chip structure and between the semiconductor chip structure and the transparent substrate, and an adhesive layer interposed between the dam and the semiconductor chip structure. The semiconductor chip structure may include an image sensor chip and a logic chip, which are in contact with each other, and the image sensor chip may be closer to the transparent substrate than the logic chip. 1. A semiconductor package , comprising:a semiconductor chip structure;a transparent substrate disposed on the semiconductor chip structure;a dam placed on an edge of the semiconductor chip structure and between the semiconductor chip structure and the transparent substrate; andan adhesive layer interposed between the dam and the semiconductor chip structure,wherein the semiconductor chip structure includes an image sensor chip and a logic chip, which are in contact with each other, wherein the image sensor chip is closer to the transparent substrate than the logic chip, andwherein widths of the image sensor chip and the logic chip are less than a width of the transparent substrate.2. The semiconductor package of claim 1 ,wherein the image sensor chip comprises a micro lens array, which is provided in a center region of the image sensor chip,wherein the logic chip comprises a through electrode, andwherein the through electrode overlaps the micro lens array.3. The semiconductor package of claim 1 , wherein a sidewall of the image sensor chip is aligned with a sidewall of the logic chip.4. The semiconductor package of claim 1 , wherein the adhesive layer is extended to be in contact with a sidewall of the dam and a surface of the transparent substrate.5. The semiconductor package of claim 1 ,wherein the image sensor chip ...

IMAGE SENSOR USING A BOOSTING CAPACITOR AND A NEGATIVE BIAS VOLTAGE

An image sensor includes a photodiode generating a charge in response to light, a transfer transistor connecting the photodiode and a floating diffusion, a reset transistor connected between the floating diffusion and a power node, a boosting capacitor connected to the floating diffusion, and adjusting a capacity of the floating diffusion in response to a boosting control signal, and a bias circuit having first and second current circuits for supplying different bias currents to an output node to which a voltage signal corresponding to a charge accumulated in the floating diffusion is output. The boosting control signal decreases from a high level to a low level after the transfer transistor is turned off, and the reset transistor is switched from a turned on state to a turned off state when the bias currents of the first and second current circuits are simultaneously provided to the output node. 1. An image sensor , comprising:a photodiode configured to generate a charge in response to light;a transfer transistor connecting the photodiode and a floating diffusion in response to a transmission control signal;a reset transistor connected between the floating diffusion and a power node;a boosting capacitor connected to the floating diffusion, and configured to adjust a capacity of the floating diffusion in response to a boosting control signal; anda bias circuit having a first current circuit and a second current circuit configured to supply different bias currents to an output node to which a voltage signal corresponding to a charge accumulated in the floating diffusion is output,wherein the boosting control signal decreases from a high level to a low level after the transfer transistor is turned off, andthe reset transistor is switched from a turned on state to a turned off state during a first time at which a first bias current of the first current circuit and a second bias current of the second current circuit are simultaneously provided to the output node.2. The ...

SEMICONDUCTOR DEVICE

Provided is a semiconductor device which can be prevented from increasing in size. The semiconductor device includes a semiconductor chip having a first main surface and a second main surface opposite to the first main surface and a wiring substrate over which the semiconductor chip is mounted such that the second main surface of the semiconductor chip faces a first main surface of the wiring substrate. Over the second main surface of the semiconductor chip, a plurality of first terminals connected with a first circuit and a plurality of second terminals connected with a second circuit are arranged. An arrangement pattern of the plurality of first terminals and an arrangement pattern of the plurality of second terminals include the same arrangement pattern. In a region of the wiring substrate where the first circuit is close to the second circuit when viewed from the first main surface of the semiconductor chip, a voltage line which supplies a power supply voltage to the first circuit is formed. In a region of the wiring substrate where the second circuit is close to the first circuit, a voltage line which supplies the power supply voltage to the second circuit is formed. 1. A semiconductor device , comprising:a semiconductor chip having a quadrangular shape in plan view, and including a first circuit, a second circuit, a first main surface, a second main surface opposite and facing the first main surface, a plurality of first terminals formed two-dimensionally over the second main surface and connected with the first circuit, and a plurality of second terminals formed two-dimensionally over the second main surface and connected with the second circuit;a wiring substrate including a first main surface over which a plurality of first external terminals are arranged, a wiring layer, and a second main surface over which a plurality of second external terminals are arranged, the second main surface being opposite to the first main surface via the wiring layer; anda ...

SEMICONDUCTOR DEVICE

A semiconductor device, includes: a first semiconductor chip including: a first substrate; a first via; a first rear surface-side pad connected to the first via; a first wiring layer; a first front surface-side pad formed on the first wiring layer; and an input circuit formed in the first substrate, an input signal wire connecting the first via, the first front surface-side pad, and an input terminal of the input circuit; and a second semiconductor chip including: a second substrate; a second wiring layer; a second front surface-side pad; and an output circuit formed in the second substrate, an output signal wire connecting the second front surface-side pad to an output terminal of the output circuit. The second semiconductor chip is stacked on a rear surface side of the first semiconductor chip, and the first rear surface-side pad and the second front surface-side pad are connected. 1. A semiconductor device comprising:a first semiconductor chip including: a first substrate; a first via penetrating through the first substrate; a first rear surface-side pad formed on a rear surface side of the first substrate and connected to the first via; a first wiring layer formed on a front surface side of the first substrate; a first front surface-side pad formed on a front surface side of the first wiring layer; and an input circuit formed in the first substrate, the first wiring layer being provided with an input signal wire which connects the first via, the first front surface-side pad, and an input terminal of the input circuit; anda second semiconductor chip including: a second substrate, a second wiring layer formed on a front surface side of the second substrate; a second front surface-side pad formed on a front surface side of the second wiring layer; and an output circuit formed in the second substrate, the second wiring layer being provided with an output signal wire which connects the second front surface-side pad to an output terminal of the output circuit,wherein ...

Stack package

A stack package includes a substrate, a stack of semiconductor chips mounted to the substrate, a side semiconductor chip disposed on one side of the stack, and adhesive interposed between the lower surface of the side semiconductor chip and the stack of semiconductor chips and which attaches the side semiconductor chip to the stack.

SEMICONDUCTOR PACKAGE ASSEMBLY WITH PASSIVE DEVICE

A semiconductor package assembly includes a first substrate. A first semiconductor die is disposed on the first substrate. A passive device is located directly on the first semiconductor die. The passive device is disposed within a boundary of the first semiconductor die in a plan view. 1. A semiconductor package assembly , comprising:a first substrate;a first semiconductor die disposed on the first substrate; anda passive device located directly above the first semiconductor die, wherein the passive device is disposed within a boundary of the first semiconductor die in a plan view.2. The semiconductor package assembly as claimed in claim 1 , wherein pads of the passive device connect directly to pads of the first semiconductor die.3. The semiconductor package assembly as claimed in claim 1 , further comprising a second substrate between the first semiconductor die and the passive device claim 1 , wherein pads of the first semiconductor die are exposed form the second substrate.4. The semiconductor package assembly as claimed in claim 3 , wherein the pads of the passive device directly attach onto pads of the second substrate.5. The semiconductor package assembly as claimed in claim 3 , wherein an area of the second substrate is less than that of the first semiconductor die and that of the first substrate.6. The semiconductor package assembly as claimed in claim 3 , wherein the second substrate is coupled to the pads of the first semiconductor die only through conductive wires.7. The semiconductor package assembly as claimed in claim 3 , further comprising a second semiconductor die disposed directly on the second substrate.8. The semiconductor package assembly as claimed in claim 3 , wherein the passive device is disposed beside the second semiconductor die.9. A semiconductor package assembly claim 3 , comprising:a first substrate;a first semiconductor die disposed on the first substrate; anda discrete passive device located directly above the first semiconductor ...

Semiconductor devices comprising protected side surfaces and related methods

Methods of protecting semiconductor devices may involve cutting partially through a thickness of a semiconductor wafer to form trenches between stacks of semiconductor dice on regions of integrated circuitry of the semiconductor wafer. A protective material may be dispensed into the trenches and to a level at least substantially the same as a height of the stacks of semiconductor dice. Material of the semiconductor wafer may be removed from a back side thereof at least to a depth sufficient to expose the protective material in the trenches. A remaining thickness of the protective material between the stacks of semiconductor dice may be cut through.

METHODS OF MANUFACTURING MULTI-DIE SEMICONDUCTOR DEVICE PACKAGES AND RELATED ASSEMBLIES

Methods of making semiconductor device packages may involve attaching a first semiconductor die to a carrier wafer, an inactive surface of the first semiconductor die facing the carrier wafer. One or more additional semiconductor die may be stacked on the first semiconductor die on a side of the first semiconductor die opposite the carrier wafer to form a stack of semiconductor dice. A protective material may be positioned over the stack of semiconductor dice, a portion of the protective material extending along side surfaces of the first semiconductor die to a location proximate the inactive surface of the first semiconductor die. The carrier wafer may be detached from the first semiconductor die. 1. A method of making a semiconductor device package , comprising:attaching a first semiconductor die to a carrier wafer with an attachment material;stacking at least one additional semiconductor die on and in direct electrical contact with the first semiconductor die on a side of the first semiconductor die opposite the carrier wafer and positioned such that at least one shelf portion of the first semiconductor die extends laterally past at least one side surface of the at least one semiconductor die;positioning a protective material over at least sides of the stack of semiconductor dice, a portion of the protective material extending contiguously along all side surfaces of the at least one additional semiconductor die and along all side surfaces of the first semiconductor die to a location in contact with the attachment material; anddetaching the carrier wafer from the first semiconductor die by removing a first portion of a material of the carrier wafer from a side of the carrier wafer opposite the first semiconductor die at a first rate and subsequently removing a second portion of the material of the carrier wafer from the side of the carrier wafer opposite the first semiconductor die at a second, different rate.2. The method of claim 1 , wherein attaching the first ...

PAGE BUFFER CIRCUITS AND NONVOLATILE MEMORY DEVICES INCLUDING THE SAME

A nonvolatile memory device includes a memory cell array including memory cells and a page buffer circuit. The page buffer circuit includes page buffer units and cache latches. The cache latches are spaced apart from the page buffer units in a first horizontal direction, and correspond to respective ones of the plurality of page buffer units. Each of the page buffer units includes a pass transistor connected to each sensing node and driven in response to a pass control signal. The page buffer circuit being configured to perform a data transfer operation, based on performing a first data output operation to output data, provided from a first portion of page buffer units, from a first portion of cache latches to a data input/output (I/O) line, the data transfer operation configured to dump sensed data from a second portion of page buffer units to a second portion of cache latches. 1. A nonvolatile memory device comprising:a memory cell array including a plurality of memory cells; anda page buffer circuit including a plurality of page buffer units and a plurality of cache latches, the plurality of page buffer units in a first horizontal direction and connected to each of the memory cells through a plurality of bit-lines, the plurality of cache latches being spaced apart from the plurality of page buffer units in the first horizontal direction, the plurality of cache latches corresponding to respective ones of the plurality of page buffer units,each of the plurality of page buffer units including a pass transistor connected to each sensing node and driven in response to a pass control signal, andthe page buffer circuit being configured to perform a data transfer operation, based on performing a first data output operation to output data, provided from a first portion of page buffer units among the plurality of page buffer units, from a first portion of cache latches among the plurality of cache latches to a data input/output (I/O) line, the data transfer operation ...

FACE-UP FAN-OUT ELECTRONIC PACKAGE WITH PASSIVE COMPONENTS USING A SUPPORT

A face-up fan-out electronic package including at least one passive component located on a support. The electronic package can include a die. The die can include a plurality of conductive pillars having a proximal end communicatively coupled to the first side of the die and a distal end opposite the proximal end. A mold can at least partially surround the die. The mold can include a first surface that is coplanar with the distal end of the conductive pillars and a second surface opposing the first surface. In an example, the passive component can include a body and a lead. The passive component can be located within the mold. The lead can be coplanar with the first surface, and the body can be located at a distance from the second surface. The support can be located between the body and the second surface. 1. A device comprising:a die having a first side and a second side;a conductive pillar including a first end communicatively coupled to the first side of the die and a second end opposite the first end;a mold at least partially surrounding the die, the mold including a first surface about the second end of the conductive pillar and a second surface opposing the first surface;a passive component including a body and a lead within the mold, the lead coplanar with the first surface; anda support located between the passive component and the second surface.2. The electronic package of claim 1 , further comprising a routing layer electrically coupled to the second end of the conductive pillar.3. The electronic package of claim 1 , wherein the passive component is a first passive component claim 1 , and the device further comprises a second passive component claim 1 , the first passive component is located on the support claim 1 , wherein the support is a first support claim 1 , and the second passive component located on a second support claim 1 , the first support including a different offset from the first surface than the second support.4. The electronic package of ...

MICROELECTRONIC DEVICES, RELATED ELECTRONIC SYSTEMS, AND METHODS OF FORMING MICROELECTRONIC DEVICES

A microelectronic device comprises a first die and a second die attached to the first die. The first die comprises a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, vertically extending strings of memory cells within the stack structure, and first bond pad structures vertically neighboring the vertically extending strings of memory cells. The second die comprises a control logic region comprising control logic devices configured to effectuate at least a portion of control operations for the vertically extending string of memory cells, second bond pad structures in electrical communication with the first bond pad structures, and signal routing structures located at an interface between the first die and the second die. Related microelectronic devices, electronic systems, and methods are also described. 1. A microelectronic device , comprising:{'claim-text': {'claim-text': ['a stack structure comprising vertically alternating conductive structures and insulative structures;', 'vertically extending strings of memory cells within the stack structure; and', 'first bond pad structures vertically neighboring the vertically extending strings of memory cells; and'], '#text': 'a memory array region comprising:'}, '#text': 'a first die comprising:'}{'claim-text': ['a control logic region comprising control logic devices configured to effectuate at least a portion of control operations for the vertically extending string of memory cells;', 'second bond pad structures in electrical communication with the first bond pad structures; and', 'signal routing structures located at an interface between the first die and the second die.'], '#text': 'a second die attached to the first die, the second die comprising:'}2. The microelectronic device of claim 1 , wherein the signal routing structures contact a dielectric material of the first die.3. The microelectronic device of claim 2 , wherein a pitch of ...

SEMICONDUCTOR DEVICE

According to one embodiment, a semiconductor device includes a support and a stacked body on the support. The stacked body is formed of a plurality of semiconductor chips that are stacked on each other. The stacked body has a lower surface facing the support and an upper surface facing away from the support. A first wire is connected to one of the semiconductor chips in the stack and extends upward from the semiconductor chip to at least the height of the upper surface of the stacked body. A second wire is connected to the support and extends upward from the support to at least the height of the upper surface of the stacked body. 1. A semiconductor device , comprising:a support;a stacked body on the support and including a plurality of semiconductor chips stacked on each other, the stacked body having a lower surface facing the support and an upper surface facing away from the support;a first wire that is connected to one of the semiconductor chips and extends upward from the semiconductor chip to at least the height of the upper surface of the stacked body; anda second wire that is connected to the support and extends upward from the support to at least the height of the upper surface of the stacked body.2. The semiconductor device according to claim 1 , further comprising:a third wire that connects two of the semiconductor chips to each other; anda fourth wire that connects the support to one of the semiconductor chips.3. The semiconductor device according to claim 2 , further comprising:a wiring substrate above the stacked body, whereinthe first wire connects the wiring substrate to the one of the semiconductor chips, andthe second wire connects the wiring substrate to the support.4. The semiconductor device according to claim 3 , further comprising:a plurality of second wires that are each connected to the support and extend upward from the support to at least the height of the upper surface of the stacked body, whereinthe support includes a first electrode ...

SEMICONDUCTOR ASSEMBLIES WITH REDISTRIBUTION STRUCTURES FOR DIE STACK SIGNAL ROUTING

Semiconductor devices having redistribution structures, and associated systems and methods, are disclosed herein. In some embodiments, a semiconductor assembly comprises a die stack including a plurality of semiconductor dies, and a routing substrate mounted on the die stack. The routing substrate includes an upper surface having a redistribution structure. The semiconductor assembly also includes a plurality of electrical connectors coupling the redistribution structure to at least some of the semiconductor dies. The semiconductor assembly further includes a controller die mounted on the routing substrate. The controller die includes an active surface that faces the upper surface of the routing substrate and is electrically coupled to the redistribution structure, such that the routing substrate and the semiconductor dies are electrically coupled to the controller die via the redistribution structure. 1. A semiconductor assembly , comprising:a die stack including a plurality of semiconductor dies;a routing substrate mounted on the die stack, the routing substrate including an upper surface having a redistribution structure;a plurality of electrical connectors coupling the redistribution structure to at least some of the semiconductor dies of the die stack; anda controller die mounted on the routing substrate, wherein the controller die includes an active surface that faces the upper surface of the routing substrate and is electrically coupled to the redistribution structure, such that the routing substrate and the semiconductor dies are electrically coupled to the controller die via the redistribution structure.2. The semiconductor assembly of wherein the routing substrate is a semiconductor die.3. The semiconductor assembly of wherein the routing substrate is a memory die.4. The semiconductor assembly of wherein the routing substrate is an organic or inorganic interposer.5. The semiconductor assembly of wherein the redistribution structure includes a plurality of ...

SEMICONDUCTOR DEVICE PRODUCTION METHOD

A semiconductor device production method includes forming a first recess portion in a first insulating film formed on a first substrate and a first conductive layer on the front surface of the first insulating film located inside and outside the first recess portion. In the first recess portion, a first pad is formed having a width of 3 μm or less and including the first conductive layer by performing a first polishing the first conductive layer at a first polishing rate and, after the first polishing, a second polishing the first conductive layer at a second polishing rate lower than the first polishing rate. The first pad of the first substrate and a second pad of a second substrate are joined together by annealing the first substrate and the second substrate. The selection ratio of the first conductive layer to the first insulating film is 0.3 to 0.4. 1. A semiconductor device production method comprising:forming a first recess portion in a first insulating film formed on a first substrate;forming a first conductive layer on a front surface of the first insulating film located both inside and outside the first recess portion;forming, in the first recess portion, a first pad having a width of 3 μm or less and including the first conductive layer by performing a first process of polishing the first conductive layer at a first polishing rate and, after the first process, a second process of polishing the first conductive layer at a second polishing rate which is lower than the first polishing rate, wherein the second process is performed such that a selection ratio of the first conductive layer to the first insulating film is 0.3 to 0.4; andjoining the first pad of the first substrate and a second pad of a second substrate together by annealing the first substrate and the second substrate.2. The semiconductor device production method according to claim 1 , wherein the first conductive layer contains copper.3. The semiconductor device production method according to ...

SEMICONDUCTOR DEVICE

The semiconductor device comprises a first semiconductor element provided on a face on one side of a flat plate shaped interconnect component , an insulating resin covering a face of a side where the first semiconductor element of the interconnect component is provided and a side face of the first semiconductor element , and a second semiconductor element provided on a face on the other side of the interconnect component . The interconnect component has a constitution where an interconnect layer , a silicon layer and an insulating film are sequentially formed. The interconnect layer has a constitution where the interconnect layer has a flat plate shaped insulating component and a conductive component extending through the insulating component. The first semiconductor element is electrically connected with the second semiconductor element through the conductive component. 1. A semiconductor device comprising:a wiring member having a first surface and a second surface opposite the first surface, a plurality of wirings being formed in the wiring member, a plurality of external terminals being arranged on the second surface;a memory chip having a first main surface on which a plurality of first electrodes are formed; anda logic chip for controlling the memory chip having a second main surface on which a plurality of second electrodes and a plurality of third electrodes are formed,wherein the memory chip is mounted over the first surface of the wiring member such that the first main surface of the memory chip faces the first surface of the wiring member, such that the memory chip is located over the logic chip, and such that the first main surface of the memory chip faces the second main surface of the logic chip,wherein the first electrodes of the memory chip are electrically connected with the second electrodes of the logic chip, respectively, and not mechanically connected with the external terminals of the wiring member via the wirings of the wiring member, ...

Package-on-package Assembly With Wire Bond Vias

A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.

BONDED THREE-DIMENSIONAL MEMORY DEVICES AND METHODS OF MAKING THE SAME BY REPLACING CARRIER SUBSTRATE WITH SOURCE LAYER

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a carrier substrate. Memory stack structures vertically extend through the alternating stack. Each memory stack structure includes a respective vertical semiconductor channel and a respective memory film. The memory die can be bonded to a logic die containing peripheral circuitry for supporting operations of memory cells within the memory die. A distal end of each of the vertical semiconductor channels is physically exposed by removing the carrier substrate. A source layer is formed directly on the distal end each of the vertical semiconductor channels. A source power supply network can be formed on the backside of the source layer. 1. A semiconductor structure comprising a memory die bonded to a logic die , the memory die comprising:an alternating stack of insulating layers and electrically conductive layers;memory openings extending through the alternating stack;memory opening fill structures located in the memory openings and comprising a respective vertical semiconductor channel and a respective memory film;a source layer having a front side electrically connected to first end portions of the vertical semiconductor channels that are distal from an interface between the logic die and the memory die;an electrically conductive layer connected to a back side of the source layer; andbackside bonding pads electrically connected to the electrically conductive layer.2. The semiconductor structure of claim 1 , wherein electrically conductive layer comprises a source power supply network.3. The semiconductor structure of claim 2 , wherein the source power supply network comprises backside metal interconnect structures embedded in a backside isolation dielectric layer and contacting the source layer at multiple locations.4. The semiconductor structure of claim 3 , wherein the source power supply network comprises:a network of metal lines; ...

SEMICONDUCTOR MEMORY DEVICE HAVING THREE-DIMENSIONAL STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor memory device includes an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers which are alternately stacked on a substrate defined with a plurality of cell areas and a plurality of coupling areas in a first direction; a hard mask pattern disposed on the electrode structure, and having a plurality of opening holes in the coupling areas; and a plurality of contact holes defined in the electrode structure under the plurality of opening holes, and exposing pad areas of the electrode layers, respectively. The plurality of opening holes are disposed by being distributed in a plurality of rows arranged in a second direction intersecting with the first direction. 1. A semiconductor memory device comprising:an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers which are alternately stacked on a substrate defined with a plurality of cell areas and a plurality of coupling areas in a first direction;a hard mask pattern disposed on the electrode structure, and having a plurality of opening holes in the coupling areas; anda plurality of contact holes defined in the electrode structure under the plurality of opening holes, and exposing pad areas of the electrode layers, respectively,wherein the plurality of opening holes are distributed in a plurality of rows arranged in a second direction.2. The semiconductor memory device according to claim 1 ,wherein opening holes disposed in the same coupling area and in the same row comprise a hole group, andwherein the opening holes in the hole group are disposed in the first direction.3. The semiconductor memory device according to claim 2 ,wherein the plurality of contact holes disposed under the plurality of opening holes of the same hole group are sequentially deepened by a first depth, andwherein the first depth is the same as a vertical pitch of the plurality of electrode layers.4. The semiconductor ...

Semiconductor Structure and Method of Forming

A device package and methods of forming are provided. The device package includes a logic die and a first passivation layer over the logic die. The device package also includes a memory die and a molding compound extending along sidewalls of the logic die and the memory die. The device package also includes a conductive via extending through the molding compound, and a first redistribution layer (RDL) structure over the molding compound. The molding compound extends between a top surface of the memory die and a bottom surface of the first RDL structure. A top surface of the first passivation layer contacts the bottom surface of the first RDL structure. 1. A device package comprising:a logic die, a first passivation layer over the logic die;a memory die,a molding compound extending along sidewalls of the logic die and the memory die;a conductive via extending through the molding compound; anda first redistribution layer (RDL) structure over the molding compound, wherein the molding compound extends between a top surface of the memory die and a bottom surface of the first RDL structure along a line that intersects the memory die and that is parallel to a sidewall of the memory die, and wherein a top surface of the first passivation layer contacts the bottom surface of the first RDL structure.2. The device package of claim 1 , wherein the memory die is a dynamic random access memory (DRAM) die.3. The device package of claim 1 , wherein the first passivation layer comprises polybenzoxazole (PBO).4. The device package of claim 1 , wherein a second passivation layer is disposed along a surface of the memory die claim 1 , the surface of the second passivation layer contacting the molding compound.5. The device package of claim 4 , wherein the first passivation layer comprises a first material claim 4 , the second passivation layer comprises a second material claim 4 , and wherein the first material and the second material are different.6. The device package of claim 1 , ...

Vertical Memory Module Enabled by Fan-Out Redistribution Layer

Vertical memory modules enabled by fan-out redistribution layer(s) (RDLs) are provided. Memory dies may be stacked with each die having a signal pad directed to a sidewall of the die. A redistribution layer (RDL) is built on sidewalls of the stacked dies and coupled with the signal pads. The RDL may fan-out to UBM and solder balls, for example. An alternative process reconstitutes dies on a carrier with a first RDL on a front side of the dies. The dies and first RDL are encapsulated, and the modules vertically disposed for a second reconstitution on a second carrier. A second RDL is applied to exposed contacts of the vertically disposed modules and first RDLs. The vertical modules and second RDL are encapsulated in turn with a second mold material. The assembly may be singulated into individual memory modules, each with a fan-out RDL on the sidewalls of the vertically disposed dies. 1. A method , comprising:disposing multiple memory dies to make a vertical stack, each memory die having a respective signal pad directed to an edge of the memory die in a common direction with the signal pads of the multiple memory dies; andbuilding a redistribution layer (RDL) on a sidewall of the stack of memory dies, the redistribution layer (RDL) perpendicular to the vertical stack and communicatively coupled with the signal pads.2. The method of claim 1 , wherein building the RDL on the sidewall includes communicatively coupling the RDL to the signal pads with solderless connections claim 1 , or includes applying a solderless process to communicatively couple the RDL to the signal pads.3. The method of claim 1 , further comprising building the RDL as a fan-out of conductive lines from the signal pads.4. The method of claim 1 , further comprising building the RDL to fan-out conductive lines from the signal pads to under ball metallization or to solder balls.5. The method of claim 1 , further comprising building multiple redistribution layers (RDLs) on the sidewall.6. The method of ...

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

To improve the assemblability of a semiconductor device. 120-. (canceled)21. A method for manufacturing a semiconductor device , comprising the steps of:(a) mounting a first semiconductor chip over a second semiconductor chip such that a first surface of the first semiconductor chip faces to a second surface of the second semiconductor chip,wherein the second semiconductor chip includes a plurality of electrode pads and a recognition mark arranged on the second surface, and a plurality of through electrodes electrically coupled with the electrode pads respectively, andwherein the first semiconductor chip includes a plurality of projection electrodes arranged on the first surface, (a1) recognizing the recognition mark;', '(a2) performing alignment of the first semiconductor chip and the second semiconductor chip based on a result of having recognized the recognition mark; and', '(a3) mounting the first semiconductor chip over the second semiconductor chip, and electrically coupling the electrode pads of the second semiconductor chip and the projection electrodes of the first semiconductor chip respectively,, 'the (a) step including the steps of(b) before the (a) step, forming the through electrodes such that the through electrodes are formed penetrating a silicon base portion of the first semiconductor chip, and(c) after the (b) step, forming the recognition mark on the second surface such that the recognition mark is electrically separated from the through electrodes and not overlapped with the through electrodes in plan view.22. The method for manufacturing the semiconductor device according to claim 21 , further comprising the steps of:(d) after the (b) step and before the (c) step, forming the electrode pads on the through electrodes such that the electrode pads are electrically coupled with the through electrodes respectively; andwherein, in the (c) step, the recognition mark is formed by plating.23. The method for manufacturing the semiconductor device ...

SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE

A method for manufacturing a semiconductor device includes providing an adhesive film over a first surface of a semiconductor wafer on which a semiconductor device layer and a bump electrically connected to the semiconductor device layer are formed, forming a slit in the adhesive film, fragmenting the semiconductor wafer into semiconductor chips along the slit, and connecting the bump to a wiring of a circuit board within the adhesive film. 1. A method for manufacturing a semiconductor device , comprising:providing an adhesive film over a first surface of a semiconductor wafer on which a semiconductor device layer and a bump electrically connected to the semiconductor device layer are formed;forming a slit in the adhesive film;fragmenting the semiconductor wafer into semiconductor chips along the slit; andconnecting the bump to a wiring of a circuit board within the adhesive film.2. The method according to claim 1 , wherein the slit does not reach the semiconductor wafer.3. The method according to claim 2 , wherein the slit has a depth that is at least one-third of a thickness of the adhesive film.4. The method according to claim 1 , further comprising:before providing the adhesive film, emitting laser light towards a region in a second surface of the semiconductor wafer corresponding to a region of the adhesive film where the slit is to be formed.5. The method according to claim 4 , whereina crystal property of an internal portion of the semiconductor wafer is modified by the laser light, andthe fragmenting includes cleaving the semiconductor wafer at a modified region including the internal portion of the semiconductor wafer where the crystal property was modified.6. The method according to claim 5 , further comprising:after emitting the laser light but before providing the adhesive film, inspecting a condition of a crack that extends from the modified region towards the first or the second surface.7. The method according to claim 1 , wherein the forming of the ...

Memory device including pass transistors

A memory device includes an active region with a drain; a plurality of memory blocks arranged in a first direction; and a plurality of pass transistors formed in the active region and sharing the drain, each one of the plurality of pass transistors configured to transfer an operating voltage from the drain to a corresponding one of the plurality of memory blocks in response to a block select signal. The plurality of pass transistors is divided into first pass transistors and second pass transistors. A channel length direction of the first pass transistors and a channel length direction of the second pass transistors are different from each other.

SEMICONDUCTOR STORAGE DEVICE

A semiconductor storage device includes a first chip and a second chip. The first chip includes a semiconductor substrate, transistors, a first interconnect, and first bonding electrodes. The second chip includes a memory cell array and second bonding electrodes. The second bonding electrodes are bonded to the first bonding electrodes. The first chip or the second chip has bonding pad electrodes. The second bonding electrodes include third bonding electrodes and fourth bonding electrodes. The third and fourth bonding electrodes overlap the memory cell array. The third bonding electrodes are in a current pathway between the memory cell array and the transistors whereas the fourth bonding electrodes are not in such a current pathway. The first interconnect is electrically connected to a bonding pad electrode and a fourth bonding electrode directly, without a current path via any one of transistors. 1. A semiconductor storage device , comprising:a first chip including a semiconductor substrate, a plurality of transistors, a first interconnect, and a plurality of first bonding electrodes;a second chip including a memory cell array and a plurality of second bonding electrodes, the second bonding electrodes being bonded to the first bonding electrodes; anda plurality of bonding pad electrodes on the first chip or the second chip, the bonding pad electrodes being connectable to bonding wires, wherein{'claim-text': ['third bonding electrodes that overlap the memory cell array and are in a current pathway between the memory cell array and the transistors; and', 'fourth bonding electrodes that overlap the memory cell array but are not in a current pathway between the memory cell array and the transistors,'], '#text': 'the plurality of second bonding electrodes includes:'}the first interconnect is electrically connected to a bonding pad electrode in the plurality of bonding pad electrodes without via any of the transistors being in the electrical connection between the bonding ...

SEMICONDUCTOR PACKAGE

A semiconductor package according to the inventive concept includes a first semiconductor chip configured to include a first semiconductor device, a first semiconductor substrate, a plurality of through electrodes penetrating the first semiconductor substrate, and a plurality of first chip connection pads arranged on an upper surface of the first semiconductor substrate; a plurality of second semiconductor chips sequentially stacked on an upper surface of the first semiconductor chip and configured to each include a second semiconductor substrate, a second semiconductor device controlled by the first semiconductor chip, and a plurality of second chip connection pads arranged on an upper surface of the second semiconductor substrate; a plurality of bonding wires configured to connect the plurality of first chip connection pads to the plurality of second chip connection pads; and a plurality of external connection terminals arranged on a lower surface of the first semiconductor chip. 1. A semiconductor package comprising:a first semiconductor chip configured to include a first semiconductor device, a first semiconductor substrate, a plurality of through electrodes penetrating the first semiconductor substrate, and a plurality of first chip connection pads arranged on an upper surface of the first semiconductor substrate;a plurality of second semiconductor chips sequentially stacked on an upper surface of the first semiconductor chip and configured to each include a second semiconductor substrate, a second semiconductor device controlled by the first semiconductor chip, and a plurality of second chip connection pads arranged on an upper surface of the second semiconductor substrate;a plurality of bonding wires configured to connect the plurality of first chip connection pads to the plurality of second chip connection pads;a molding layer configured to surround the plurality of second semiconductor chips and the plurality of bonding wires; anda plurality of external ...

SEMICONDUCTOR PACKAGE ASSEMBLY AND METHOD FOR FORMING THE SAME

A semiconductor package assembly is provided. The semiconductor package assembly includes a semiconductor die and a first memory die disposed on a first surface of a substrate, wherein the first memory die comprises a first edge facing the semiconductor die. The semiconductor die includes a peripheral region having a second edge facing the first edge of the first memory die and a third edge opposite to the second edge. The semiconductor die also includes a circuit region surrounded by the peripheral region, wherein the circuit region has a fourth edge adjacent to the second edge and a fifth edge adjacent to the third edge. A minimum distance between the second edge and the fourth edge is a first distance, a minimum distance between the third edge and the fifth edge is a second distance, and the first distance is different from the second distance. 1. A semiconductor package assembly , comprising: a peripheral region having a second edge facing the first edge of the first memory die and a third edge opposite to the second edge; and', 'a circuit region surrounded by the peripheral region, wherein the circuit region has a fourth edge adjacent to the second edge and a fifth edge adjacent to the third edge, and, 'a semiconductor die and a first memory die disposed on a first surface of a substrate, wherein the first memory die comprises a first edge facing the semiconductor die, and the semiconductor die compriseswherein a minimum distance between the second edge and the fourth edge is a first distance, a minimum distance between the third edge and the fifth edge is a second distance, and the first distance is different from the second distance.2. The semiconductor package assembly as claimed in claim 1 , further comprising:a second memory die disposed on the first surface of the substrate, wherein a width of the first memory die is the same as a width of the second memory die, and the second edge is between the fourth edge and a sixth edge of the second memory die.3. ...

Integrated Circuit Device with Separate Die for Programmable Fabric and Programmable Fabric Support Circuitry

An integrated circuit device having separate dies for programmable logic fabric and circuitry to operate the programmable logic fabric are provided. A first integrated circuit die may include field programmable gate array fabric. A second integrated circuit die may be coupled to the first integrated circuit die. The second integrated circuit die may include fabric support circuitry that operates the field programmable gate array fabric of the first integrated circuit die. 1. An integrated circuit device comprising:a first integrated circuit die comprising field programmable gate array fabric; anda second integrated circuit die coupled to the first integrated circuit die, wherein the second integrated circuit die comprises fabric support circuitry configured to operate the field programmable gate array fabric of the first integrated circuit die.2. The integrated circuit device of claim 1 , wherein the fabric support circuitry of the second integrated circuit die comprises a device controller configured to control circuitry of the first integrated circuit die and the second integrated circuit die claim 1 , a sector controller configured to control a sector of circuitry of the first integrated circuit die and the second integrated circuit die claim 1 , a network-on-chip claim 1 , a configuration network on chip claim 1 , data routing circuitry claim 1 , sector-aligned memory claim 1 , a memory controller configured to program the programmable logic fabric claim 1 , an input/output (I/O) interface for the programmable logic fabric claim 1 , an external memory interface claim 1 , a first processor embedded in the second integrated circuit die claim 1 , an interface to connect the programmable logic fabric to a second processor external to the first integrated circuit die and the second integrated circuit die claim 1 , voltage control circuitry configured to control a voltage supplied to the programmable logic fabric claim 1 , thermal monitoring circuitry configured to ...

LOGIC DRIVE BASED ON MULTICHIP PACKAGE COMPRISING STANDARD COMMODITY FPGA IC CHIP WITH COOPERATING OR SUPPORTING CIRCUITS

A multichip package includes: a chip package comprising a first IC chip, a polymer layer in a space beyond and extending from a sidewall of the first IC chip, a through package via in the polymer layer, an interconnection scheme under the first IC chip, polymer layer and through package via, and a metal bump under the interconnection scheme and at a bottom of the chip package, wherein the first IC chip comprises memory cells for storing data therein associated with resulting values for a look-up table (LUT) and a selection circuit comprising a first input data set for a logic operation and a second input data set associated with the data stored in the memory cells, wherein the selection circuit selects, in accordance with the first input data set, data from the second input data set as an output data for the logic operation; and a second IC chip over the chip package, wherein the second IC chip couples to the first IC chip through, in sequence, the through package via and interconnection scheme, wherein the second IC chip comprises a hard macro having an input data associated with the output data for the logic operation. 1. A multichip package comprising:a first chip package comprising a first semiconductor integrated-circuit (IC) chip, a first polymer layer in a space beyond and extending from a sidewall of the first semiconductor integrated-circuit (IC) chip, a through-polymer via in the first polymer layer, a first interconnection scheme under the first semiconductor integrated-circuit (IC) chip, first polymer layer and through-polymer via, and a first metal bump under the first interconnection scheme and at a bottom of the first chip package, wherein a top surface of the first polymer layer and a top surface of the through-polymer via are coplanar, wherein the first interconnection scheme comprises a first interconnection metal layer under the first semiconductor integrated-circuit (IC) chip, first polymer layer and through-polymer via, a second interconnection ...

SEMICONDUCTOR PACKAGE AND A METHOD FOR MANUFACTURING THE SAME

A semiconductor package may include a package substrate, a support structure on the package substrate and having a cavity therein, and at least one first semiconductor chip on the package substrate in the cavity. The support structure may have a first inner sidewall facing the cavity, a first top surface, and a first inclined surface connecting the first inner sidewall and the first top surface. The first inclined surface may be inclined with respect to a top surface of the at least one first semiconductor chip. 1. A semiconductor package comprising:a package substrate;a support structure on the package substrate and having a cavity therein; andat least one first semiconductor chip on the package substrate in the cavity,wherein the support structure has: a first inner sidewall facing the cavity; a first top surface; and a first inclined surface connecting the first inner sidewall and the first top surface, andwherein the first inclined surface is inclined with respect to a top surface of the at least one first semiconductor chip.2. The semiconductor package of claim 1 , wherein a contact point of the first inner sidewall and the first inclined surface of the support structure is at a lower level than the top surface of the at least one first semiconductor chip.3. The semiconductor package of claim 1 , wherein the first top surface of the support structure is at substantially the same level as the top surface of the at least one first semiconductor chip.4. The semiconductor package of claim 1 , wherein a distance between the first inner sidewall of the support structure and the at least one first semiconductor chip ranges from 1 μm to 10 μm.5. The semiconductor package of claim 1 , wherein the first inner sidewall of the support structure is substantially perpendicular to a top surface of the package substrate.6. The semiconductor package of claim 1 , wherein the at least one first semiconductor chip is connected to the package substrate by a bonding wire claim 1 , ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

In a semiconductor device according to an embodiment, a second semiconductor chip is mounted on a first rear surface of a first semiconductor chip. Also, the first rear surface of the first semiconductor chip includes a first region in which a plurality of first rear electrodes electrically connected to the second semiconductor chip via a protrusion electrode are formed and a second region which is located on a peripheral side relative to the first region and in which a first metal pattern is formed. In addition, a protrusion height of the first metal pattern with respect to the first rear surface is smaller than a protrusion height of each of the plurality of first rear electrodes with respect to the first rear surface. 1. A semiconductor device comprising:a wiring substrate including a first surface, a plurality of first terminals formed on the first surface, and a second surface opposite to the first surface;a first semiconductor chip which includes a first front surface, a plurality of first front electrodes formed on the first front surface, a first rear surface opposite to the first front surface, a plurality of first rear electrodes formed on the first rear surface, and a plurality of through electrodes electrically connecting the plurality of first front electrodes to the plurality of first rear electrodes, and is mounted on the wiring substrate so that the first front surface faces the first surface of the wiring substrate; anda second semiconductor chip which includes a second front surface, a plurality of second front electrodes formed on the second front surface, and a second rear surface opposite to the second front surface, and is mounted on the first semiconductor chip so that the second front surface faces the first rear surface of the first semiconductor chip,wherein the plurality of first terminals of the wiring substrate and the plurality of first front electrodes of the first semiconductor chip are electrically connected to each other via a ...

Single-Shot Encapsulation

A semiconductor device includes a semiconductor wafer. A plurality of pillar bumps is formed over the semiconductor wafer. A solder is deposited over the pillar bumps. The semiconductor wafer is singulated into a plurality of semiconductor die after forming the pillar bumps while the semiconductor wafer is on a carrier. An encapsulant is deposited around the semiconductor die and pillar bumps while the semiconductor die remains on the carrier. The encapsulant covers an active surface of the semiconductor die between the pillar bumps.

Interconnect Structure and Method of Forming Same

A semiconductor device comprises a first chip bonded on a second chip. The first chip comprises a first substrate and first interconnection components formed in first IMD layers. The second chip comprises a second substrate and second interconnection components formed in second IMD layers. The device further comprises a first conductive plug formed within the first substrate and the first IMD layers, wherein the first conductive plug is coupled to a first interconnection component and a second conductive plug formed through the first substrate and the first IMD layers and formed partially through the second IMD layers, wherein the second conductive plug is coupled to a second interconnection component. 1. A semiconductor device comprising:a first conductive plug, the first conductive plug having a first width adjacent to a semiconductor substrate and having a second width adjacent to a first metallization layer within a first die, the second width being smaller than the first width;a second conductive plug, the second conductive plug having a third width adjacent to the semiconductor substrate, a fourth width adjacent to the first metallization layer, and a fifth width adjacent to a second metallization layer of a second die; anda dielectric liner continuously extending to be in contact with both the first conductive plug and the second conductive plug, the dielectric liner remaining outside of the first metallization layer.2. The semiconductor device of claim 1 , wherein the first conductive plug is in physical contact with a conductive portion of the first metallization layer.3. The semiconductor device of claim 2 , wherein the first conductive plug extends into the conductive portion of the first metallization layer.4. The semiconductor device of claim 2 , wherein the conductive portion of the first metallization layer is adjacent to an interface between the semiconductor substrate and the first metallization layer.5. The semiconductor device of claim 2 , wherein ...

Methods to fabricate integrated circuits by assembling components

The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. The present process can fabricate multiple components separately before assembling them into a complete integrated circuit. In an aspect, the ready-for-assembling components are taken directly from processed wafers without any additional assembling processes, and/or having lateral dimensions less than 1 mm.

Carrier Wafers, Methods of Manufacture Thereof, and Packaging Methods

Carrier wafers, methods of manufacture thereof, and packaging methods are disclosed. In one embodiment, a carrier wafer includes a first glass layer. The carrier wafer includes a second glass layer coupled to the first glass layer. The first glass layer has a first coefficient of thermal expansion (CTE), and the second glass layer has a second CTE.

Memory device with improved program performance and method of operating the same

A memory device includes a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first and second metal pads, a memory cell array in the memory cell region including cell strings including memory cells, word lines respectively connected to the memory cells, bit lines connected to one side of the cell strings, and a ground selection line connected to the cell strings, a control logic in the peripheral circuit region including a precharge control circuit for controlling precharge on partial cell strings among the cell strings and controlling a plurality of data program steps on the memory cells, and a row decoder in the peripheral circuit region for activating at least some of the word lines in response to a control of the control logic.