СПОСОБ ИЗГОТОВЛЕНИЯ ПРОВОДЯЩЕЙ СХЕМЫ НА ПОДЛОЖКЕ, ПРОВОДЯЩАЯ СХЕМА НА ПОДЛОЖКЕ И УСТРОЙСТВО ДЛЯ ИЗГОТОВЛЕНИЯ ГИБКОЙ ПРОВОДЯЩЕЙ СХЕМЫ

Из проводящей схемы можно изготовить плотно упакованные блоки контактов для использования в качестве электрических соединителей или схем. Способ и устройство для изготовления проводящей схемы включает в себя формование листа проводящего материала 22 для образования выступов 24 и желобков 26, из которых один образует проводящую схему, а другой - отходы материала, которые затем механически удаляются. Таким образом проводящая схема поддерживается слоем 12 диэлектрика.

Herstellungsverfahren für eine gedruckte Schaltung

PRINTED CIRCUIT CARD

... 1,221,968. Printed circuit assemblies. INTERNATIONAL BUSINESS MACHINES CORP. 17 April, 1968 [8 May, 1967], No. 18052/68. Heading H1R. [Also in Division H2] Electrical connection between two electrically conductive coatings 46, 48, Fig. 3, on a dielectric base 47 is produced by providing in one coating conical members 53 which project through holes in the base 47 and corresponding conical members in the second coating which fit over the first said members. Such connections are produced by depositing a conducting layer (72), Fig. 2b (not shown), of e.g. copper, on a steel former (70) having raised conical projections (71), and then assembling a prepunched dielectric layer (73), e.g. of epoxy or silicone glass, a further conducting layer (74), e.g. of copper, provided with conical members (76), on the deposited conducting layer. The various layers are then laminated together by heat and pressure and thereafter removed from the former. To ensure good electrical connections, solder may be provided ...

Multilayer Printed Circuit Board and Method for Manufacturing Same.

... 1,187,916. Printed circuits. CONTROL DATA CORP. 18 March, 1968 [26 June, 1967], No. 13110/68. Heading H1R. A multilayer printed circuit board is made by repeating the following steps; forming a conductive layer on an insulating substrate; covering the conductive layer with a suitable masking material; developing the mask according to the desired pattern of interlayer connectors; electroforming these connectors; removing the mask; and insulating the conductive layer and connectors. In a first embodiment the first of the multilayers of printed circuit is formed by photo-etching a layer of copper on an insulating substrate, Figs. 1, 2 (not shown), after which the exposed photoresist is removed and the printed circuit and exposed surfaces of substrate are coated with copper by an electroless or vacuum deposition process, Fig. 3 (not shown). The assembly is then coated with a mask which is photodeveloped in the pattern of interlayer connectors and conforms to the contours of the printed circuit ...

PRODUCTION OF CIRCUIT BOARDS

... 1,262,245. Printed circuits. INTERNATIONAL BUSINESS MACHINES CORP. 20 March, 1970 [2 April, 1969], No. 13673/70. Heading H1R. A substrate; 10, is coated with a conducting layer, 11, on which areas 13 of spacing material are formed, the intervening spaces 14 then being built up with conducting material to form conductors, the areas 13 and the conducting layer beneath being then removed and replaced by an insulator in liquid or powder form, which is then hardened in. position at 16, any excess covering the conductors being subsequently removed. The substrate may be of epoxy resin ceramic or steel of high impedance, the areas 13 being provided by applying and. exposing a photo-resist. The conductors may be built up electrolytically, the areas 13 being removed with a solvent, and the portions of the layer 11 beneath by etching. The insulator applied between the conductors may be of resin or powdered glass which is sintered. The finished board may be used as the substrate for a subsequent layer ...

Electrochemically fabricated hermetically sealed microstructures

MULTI-LAYERED GLASS-CERAMIC SUBSTRATE FOR MOUNTING OF SEMICONDUCTOR DEVICE

Multilayered Glass-Ceramic Substrate For Mounting Of Semiconductor Device A method for fabricating an interconnection package for a plurality of semiconductor chips which include the fabrication of a multilayered glass-ceramic superstructure with a multilayered distribution of-conductors on a preformed multilayered glass-ceramic base, by the repeatable steps of depositing a conductor pattern on the base and forming thereon a crystallizable glass dielectric layer which is then crystallized to a glass-ceramic prior to further additions of conductor patterns and crystallizable glass layers to form a monolithic compatible substrate all through. Semiconductor chips can be electrically connected to exposed conductor patterns at the top surface of the resultant glass-ceramic package. FI9-78-039 ...

MULTILAYER SUBSTRATE

A multilayer substrate device formed from a base substrate (12) and alternating metalization layers (14) and dielectric layers (16). Each layer is formed without firing. Vias (44) may extend through one of the dielectric layers (16) such that two metalization layers (14) surrounding the dielectric layers (16) make contact with each other. The vias (44) may be formed by placing pillars (40) on top of a metalization layer (14), forming a dielectric layer (16) on top of the metalization layer (14) and surrounding the pillars (40), and removing the pillars (40). Dielectric layers (16) may be followed by other dielectric layers (16) and metalization layers (14) may be followed by other metalization layers (14).

Verfahren zur Herstellung mehrschichtiger Moduln integrierter Schaltungen aus Glas und Metall

CONTACT UNIT

配线基板的制造方法

... 本发明的目的在于简单制造可靠性高的配线基板。通过热固化性树脂前驱体形成受理层。在受理层的上面，通过含有导电性微粒的分散液来形成配线层。使热固化性树脂前驱体进行固化反应，向受理层和配线层供给使导电性微粒相互结合的热。 ...

METHOD OF MANUFACTURING A WAFER HOLDING CONDUCTOR PATTERNS UPON TWO OPPOSITE FACES ELECTROCHEMICAL PRODUCTION OF SUBSTITUTED PYRIDINES

CIRCUIT SEVERAL LAYERS FOR INTEGRATION HAS LARGE SCALES AND MANUFACTORING PROCESS OF THIS CIRCUIT

Procede de fabrication d'un substrat conducteur multicouche

Le procede de fabrication d'un substrat conducteur multicouche se caracterise en ce qu'un film mince 3 de palladium est forme sur toute une surface d'un substrat 2 renfermant une couche de lignes conductrices 1. Une zone a l'exception d'une zone de formation de contact predeterminee sur le film mince de palladium est masquee par un premier agent photoresistant. Une resine conductrice a base de polyimide est inseree dans la zone de formation de contact a travers le premier agent photoresistant. Le premier agent photoresistant est elimine. La couche de lignes conductrices et la zone de formation de contact sont masquees par un deuxieme agent photoresistant. Le film mince de palladium expose est grave. Le deuxieme agent photoresistant est elimine. La resine conductrice 8 est cuite. Une resine polyimide 9 photosensible est appliquee sur toute une surface du substrat, un trou de contact 10 est forme dans la zone de formation de contact et la resine polyimide photosensible est cuite.

METHOD AND APPARATUS FOR MEASURING SHAPE OF BUMPS

MULTILAYERED PRINTED WIRING BOARD AND METHOD FOR MANUFACTURING THE SAME, CAPABLE OF MAKING A SUBSTRATE SMALLER WITHOUT REDUCING THE NUMBER OF MOUNTED ELECTRICAL/ELECTRONIC COMPONENTS

PURPOSE: A multilayered printed wiring board and a method for manufacturing the same are provided to realize a small module by applying the multilayered printed wiring board to a module substrate. CONSTITUTION: A multilayered printed wiring board includes a flexible wiring substrate(2), rigid wiring substrates(1,3), and electric/electronic components. The flexible wiring substrate has a wiring layer on both circumferential surfaces. The rigid wiring substrates have a wiring layer on both circumferential surfaces and are arranged to face one circumferential surface of the flexible wiring substrate in a body. The area of the rigid wiring substrates is narrower than the area of the flexible wiring substrate. The electric/electronic components are paced at a region closer to the rigid wiring substrate than the flexible wiring substrate. © KIPO 2008 ...

CONDUCTIVE PASTE INCLUDING CONDUCTIVE PARTICLES, POLYMER AND FOAMING POLYMER, A PRINTED CIRCUIT BOARD USING THE SAME AND A MANUFACTURING METHOD THEREOF

PURPOSE: A conductive paste, a printed circuit board using the same and a manufacturing method thereof are provided to realize the simplification of a process, reduction of process time and reliability by reducing the printing counter for forming bump. CONSTITUTION: A conductive paste comprises 80~90 parts by weight of conductive particles; and 10~20 parts by weight of a mixture of a polymer and a foaming polymer. The conductive particles comprise any one selected from a group consisting of silver, copper, tin, indium and nickel. The polymer comprises at least one selected from a group consisting of epoxy-based or phenol-melamine-base resin. © KIPO 2009 ...

PRINTED CIRCUIT BOARD WITH HIGH HEAT RADIATION PERFORMANCE AND A MANUFACTURING METHOD THEREOF

PURPOSE: A printed circuit board and a manufacturing method thereof are provided to improve heat radiation by directly bonding a CNT(Carbon Nanotube) heat sink to a first circuit pattern or insulation layer. CONSTITUTION: A groove is formed in an insulation layer(10) with an imprint process. A metal material(20) is formed in one side of the insulation layer and the groove. The metal material is CNT. A first circuit pattern(14) is formed in at least one of the metal material formed in the groove and the other side of the insulation layer. A conductive bump(30) is formed in one side of the first circuit pattern. An insulator(40) buries the first circuit pattern. A second circuit pattern(44) is formed on the insulator. COPYRIGHT KIPO 2010 ...

Package substrate and fabrication method thereof

Provided is a package substrate and fabrication method thereof, and the package substrate comprises a first dielectric layer, a first circuit layer, a first metal bump and a buildup structure. The first metal bump and the first circuit layer are, respectively, embedded in and exposed from two surfaces of the first dielectric layer, wherein one end of the first metal bump is embedded into the first circuit layer, and a electrically conductive layer is disposed between the first circuit layer and the first dielectric layer and between the first circuit layer and the first metal bump. The buildup structure is disposed above the first circuit layer and the first dielectric layer, and the outmost layer of the buildup structure is provided with a plurality of electrical contact pads. Compared to prior arts, this application can effectively improve the problem of a conventional a package substrate being excessively wrapped.

Multilayer printed circuit board and method of manufacturing multilayer printed circuit board

A multilayer printed circuit board which can surely establish interlayer connection with low resistance. The multilayer printed circuit board comprises: a first substrate having a conductive pattern on one face and a non-penetration connection hole on the other face, for exposing the conductive pattern to outside; a second substrate having a conductive pattern formed on a face opposed to the other face of first substrate and a conductive bump on the conductive pattern integrally. The first substrate and the second substrate are integrated by engaging the bump of the second substrate with the connection hole of the first substrate and by intervening a conductive cement between the bumps and the conductive pattern exposed to outside from the connection holes.

Manufacturing method of electronic component and electronic component

The present invention is related to the manufacturing method of electronic component where plural wiring patterns, the insulation layer between the wiring patterns, and the inter-layer connection portion penetrating through the insulation layer are used to perform electrical connection between the wiring patterns. In the invention, the followings are performed repeatedly: the first engineering for forming the wiring pattern and the pillar conductor; and the second engineering, in which, by bonding the insulation sheet from the upper side and using the pillar conductor as the stop lump, the insulation sheet is pressed till the thickness of insulation sheet is the same as the height of the pillar conductor, so as to form an insulation layer with a constant thickness.

CONTACT NODE

Cette invention se rapporte à la fabrication de connexions à demeure lors de la production d'appareils à base de composants micro-électroniques et de dispositifs à semiconducteurs. Cette invention concerne plus précisément des noeuds de contact qui permettent d'assembler, entre autres, des structures de commutation multicouches pour des modules polycristallins, et de monter des cristaux de circuits intégrés à grande échelle sur une structure de commutation lors de la fabrication desdits modules polycristallins. Ce noeud de contact comprend au moins deux contacts métallisés qui sont connectés à des pistes électroconductrices (2, 6) disposées sur les surfaces de couches de commutation (3, 7). Ces couches sont à base d'un matériau diélectrique, sont superposées et sont connectées entre elles électriquement et mécaniquement par un matériau liant électroconducteur (8). Le noeud de contact consiste en une épissure qui relie, d'une part, le contact consistant en une plage métallisée (1) connectée ...

METHOD FOR PRODUCING CIRCUIT BOARD AND CIRCUIT BOARD

A method for producing a circuit board in which protrusion electrodes formed on a multilayer build-up substrate can be insulated and the upper part of protrusion electrodes for forming bumps can be exposed by coating the entire surface of the multilayer build-up substrate with photosensitive resin, and then exposing and developing the surface of the photosensitive resin with a light exposure only enough to remove the photosensitive resin formed on theprotrusion electrodes thereby arranging the photosensitive resin between the protrusion electrodes.

METHOD OF MANUFACTURING MULTILAYER WIRING BOARD

L'invention concerne un procédé de fabrication d'un panneau de câblage multicouche. Ce procédé comprend une étape consistant à former une couche de câblage supérieure (27), dont une partie est connectée électriquement à un corps métallique en forme de colonne (24a), une fois que ce dernier est formé sur une couche de câblage inférieure (22). Ce procédé est caractérisé en ce que l'étape consistant à former corps métallique comprend une sous-étape consistant à former une couche d'électrodéposition (24) constituant le corps métallique, une sous-étape consistant à former une couche de masquage (25) de la couche d'électrodéposition sur la surface où le corps métallique est formé et une sous-étape consistant à graver la couche d'électrodéposition. La fabrication peut être effectuée au moyen d'une simple combinaison d'équipements avec des étapes conventionnelles et la couche de câblage peut être affinée. Par ailleurs, il est possible de fabriquer un panneau de câblage multicouche à fiabilité élevée ...

MULTILAYER WIRING BOARD, METHOD FOR PRODUCING MULTILAYER WIRING BOARD, POLISHER FOR MULTILAYER WIRING BOARD, AND METAL SHEET FOR PRODUCING WIRING BOARD

A plurality of multilayer metal sheets (1) each comprising a bump-forming metal layer (2), etching-stop layer (3), and a wiring film-forming metal layer (4) are processed so as to each have a wiring film (4a) formed out of the wiring film-forming metal layer and bumps (2a) formed out of the bump-forming metal layer. The multilayer metal sheets are so stacked by repeating a stacking step in such a way that the bump-forming surface of one multilayer metal sheet faces to the wiring film of another multilayer metal sheet. A multilayer wiring board is polished by a polisher (11a) for a multilayer wiring board comprising a metal sheet holding means (13) for holding a metal sheet (1a), a blade holding means (25) for holding a blade (26) above the metal sheet, a height adjusting mechanism (20) for adjusting the height of the blade holding means, and a blade translating mechanism (15) for moving the blade holding means parallel to the surface of the metal sheet.

Circuit device and manufacturing method thereof

A circuit device including a multilayer wiring structure having an improved heat radiation performance, and a manufacturing method thereof is provided. A circuit device of the invention includes a first wiring layer and a second wiring layer laminated while interposing a first insulating layer. The first wiring layer is connected to the second wiring layer in a desired position through a connecting portion formed so as to penetrate the first insulating layer. The connecting portion includes a first connecting portion protruding in a thickness direction from the first wiring layer, and a second connecting portion protruding in the thickness direction from the second wiring layer. The first connecting portion and the second connecting portion contact each other at an intermediate portion in the thickness direction of the insulating layer.

Process for making a multilayer interconnect system

A process for making an interconnect system for a multilayer circuit pattern. The interconnect system is formed having minimized through-hole space consumption so as to be suitable for high density, closely meshed circuit patterns.

METHOD FOR INTERCONNECTING CONTACT LAYERS OF A CIRCUIT BOARD

PRINTED CIRCUIT BOARD AND METHOD OF MANUFACTURING THE SAME

A printed circuit board includes: a first insulating layer; a first circuit layer disposed on one surface of the first insulating layer; a second insulating layer disposed on the first insulating layer and covering at least a portion of the first circuit layer; a via conductor passing through the second insulating layer and connected to the first circuit layer; a via land connected to the via conductor in an upper portion of the via conductor; and a second circuit layer disposed on the second insulating layer and connected to the via land. The via conductor and the via land have a first interface where the via conductor and the via land are in contact with each other. 1. A printed circuit board comprising:a first insulating layer;a first circuit layer disposed on one surface of the first insulating layer;a second insulating layer disposed on the first insulating layer and covering at least a portion of the first circuit layer;a via conductor passing through the second insulating layer and connected to the first circuit layer;a via land connected to the via conductor in an upper portion of the via conductor; anda second circuit layer disposed on the second insulating layer and connected to the via land,wherein the via conductor and the via land have a first interface where the via conductor and the via land are in contact with each other.2. The printed circuit board of claim 1 , further comprising a third circuit layer disposed on the other surface of the first insulating layer.3. The printed circuit board of claim 1 , wherein the via land is disposed in a position in which at least a portion of the via conductor overlaps with the via land.4. The printed circuit board of claim 1 , wherein the via conductor has substantially the same cross-sectional area in a stacking direction of the first insulating layer and the first circuit layer.5. The printed circuit board of claim 4 , wherein the via land has a tapered shape.6. The printed circuit board of claim 4 , wherein ...

Lamination process and structure of high layout density substrate

A lamination process and structure of a high layout density substrate is disclosed. The lamination process comprises the following steps. First of all, a plurality of laminating layers are individually formed, wherein each laminating layer has a first dielectric layer, a plurality of first vias and a patterned conducting layer. Next, a bottom layer having a second dielectric layer and a plurality of second vias is formed. Then, the laminating layers and the bottom layer are stacked. Finally, the laminating layers and the bottom layer are laminated simultaneously to form a multiplayer substrate at one time.

Method for manufacturing a polyimide multilayer wiring substrate

A polyimide multilayer wiring substrate that comprises a plurality of wiring layer blocks, each of which including a plurality of polyimide wiring layers, which are electrically connected and formed into a single body by means of an anisotropic conductive film that is inserted between adjacent blocks, the multiple wiring substrate being manufactured by inserting said anisotropic conductive film between adjacent blocks and compressing and heating the blocks and layer of film so as to form them into a single body. This process of inserting, compressing and heating is repeated N times to provide a layered structure comprising N pieces of wiring layer blocks.

Printed circuit boards and method for manufacturing printed circuit boards

A printed circuit board is described in which an electrically insulating laminate material has first and second sides. An electrically conducting first circuit pattern is embedded in the first side of the laminate material, and an electrically conducting second circuit pattern is embedded in the second side of the laminate material electrically insulated from the first circuit pattern by the laminate material. A solid interconnection member extends through the laminate material and electrically contacts both the first and second circuit patterns at selected locations thereof. The method for fabricating the board includes as a first step the fabrication of a first board panel having a raised electrically conducting first circuit pattern extending from a base layer of conductive material. A second board panel is also fabricated, having a raised electrically conducting second circuit pattern extending from a its base layer of conductive material and a raised electrically conducting third circuit ...

Circuit board and method for manufacturing the same

A circuit board with a heat-recovery function includes a substrate, a heat-storing device, and a thermoelectric device. The heat-storing device is embedded in the substrate and connected to a processor for performing heat exchange with the processor. The thermoelectric device embedded in the substrate includes a first metal-junction surface and a second metal-junction surface. The first metal-junction surface is connected to the heat-storing device for performing heat exchange with the heat-storing device. The second metal-junction surface is joined with the first metal-junction surface, in which the thermoelectric device generates an electric potential by a temperature difference between the first metal-junction surface and the second metal-junction surface.

Electronic part manufacturing method and electronic part

Provided is a method of manufacturing an electronic part having a plurality of wiring patterns and an insulating layer interposed between the wiring patterns and serving to establish electrical connection between the wiring patterns through an interlayer connecting portion penetrating the insulating layer. In the method, a first step of forming a wiring pattern and a columnar conductor and a second step of forming a layer having a uniform thickness by bonding an insulating sheet from above and pressing the insulating sheet to the height of the columnar conductor with the columnar conductor as a stopper so as to conform the thickness of the insulating sheet to the height of the columnar conductor are repeated.

Multi-layer printed circuit structure

A multi-layer PC board structure is created by successively building PC board layers of metal and insulator on a carrier (708). Each layer is built sucessively by building a layer of circuitry, a layer of inter-layer connectors ("vias"), and a layer of protective "caps" to allow the formation of voids and throughholes. Each layer of circuitry, vias, and caps is generally built by successive deposition of a photoresist layer (714), exposure of the photoresist layer under a mask (723), and plating of metal (722, 724, 710). Photoresist material (714) is stripped away at appropriate process steps and replaced with a flowable polyimide insulator (712) which may be locally tailored for a desired thermal coefficient of expansion ("TCE") and a desired rigidity. The method is adapted to create PC boards with a center-oriented thermal plane ("COTP") (731) with connectors which extend completely through, without any hard tooling. The method is also adapted to create extended three-dimensional voids ...

Metal foil having bumps, circuit substrate having the metal foil, and semiconductor device having the circuit substrate

A semiconductor device wherein a circuit substrate of a single or multiple layer is composed in such a manner that bumps (22), which are electrically connected to connection electrodes (12) provided on one face of a surface mount device (10), are arranged in the same planar arrangement as that of the connection electrodes (12). The bumps (22) protrude from one side of a sheet of metal foil (20) on which wiring patterns (16) electrically connected to the bumps (22) are formed. An insulating adhesive agent layer (18) is adhered to the side of the sheet of metal foil (20) having the bumps (22) and is also adhered to one face of the surface mount device (10) while the tips of the bumps (22) come into contact with respective connection electrodes (12).

CdTe CRYSTAL OR CdZnTe CRYSTAL AND METHOD FOR PREPARING THE SAME

A process for manufacturing a chip carrier substrate, the process including the steps of providing a first layer of copper conductor on a substrate, forming a first layer of barrier metal on the first layer of copper conductor, forming a layer of aluminum on the first layer of barrier metal, forming a second barrier metal on the aluminum layer, patterning the top barrier metal in the form of studs, anodizing the aluminum unprotected by the top barrier metal, removing the aluminum oxide and patterning the first copper layer, removing all the exposed barrier metal; surrounding the studs and the copper conductor with a polymeric dielectric; polishing the polymeric dielectric to expose the studs; and forming a second layer of copper conductor on the planar polymeric dielectric.

METHOD FOR MANUFACTURING PRINTED CIRCUIT BOARDS

FLEXIBLE PRINTED CIRCUIT BOARD AND ELECTRONIC APPARATUS

PROBLEM TO BE SOLVED: To provide a flexible printed wiring board in which the mounting density of a wiring pattern is improved, by reducing the opening area of a conductive joining portion. SOLUTION: A plurality of bumps 31 are formed to be upright by repeatedly applying conductive paste at a predetermined interval on a ground line 21 so as to be laminated, a plurality of bump-penetrating portions (CHs) are formed in a cover layer 1c corresponding to the position of the plurality of bumps 31, the heads of the bumps 31 protruding from the bump-penetrating portions (CHs) are crushed to be flat, and the ground layer (electromagnetic layer ) 1d is conductively connected to the plurality of crushed portions. COPYRIGHT: (C)2010,JPO&INPIT ...

PRODUCTION OR PRINTED CIRCUIT

PURPOSE: To eliminate the need of continuous etching and plating by isolating a basic body and circuit elements from a mandrel in order to obtain a dielectric basic body mounting a circuit element pattern having projecting conductive structure. CONSTITUTION: A mandrel and a Teflon pattern are coated with an appropriate resist 18 which is then masked, exposed and developed to leave holes 20 in the resist 18. The mandrel coated with the resist is then immersed into an etching bath such that a recess 24 is made in the working surface 14 of a stainless steel mandrel basic body. The recess 24 has tapered structure obtained by removing metal from the side face or in the lateral direction inherent to etching process. Consequently, the resist 18 is removed from the recess 24 and the Teflon pattern 16 is left thus obtaining a mandrel having a single three dimensional structure, i.e., the recess 24. COPYRIGHT: (C)1992,JPO ...

PRINTED CIRCUIT BOARD AND METHOD OF MANUFACTURING THE SAME

PROBLEM TO BE SOLVED: To provide a printed circuit board capable of reducing lead time, being formed in the shape that an outer circuit pattern is embedded in an insulating layer unlike a substrate formed by the existing method, and manufacturing a thinner printed circuit board; and to provide a method of manufacturing the same. SOLUTION: The method of manufacturing a printed circuit board includes steps of: providing a first resin layer having a first pattern on one surface thereof; forming a conductive bump, which is electrically connected to the first pattern, on one surface of the first resin layer; compressing an insulating layer and the first resin layer such that the conductive bump passes through the insulating layer; laminating a second resin layer, which has a second pattern on a surface thereof facing the insulating layer, on the insulating layer; and forming an opening by etching a portion of at least one of the first resin layer and the second resin layer. COPYRIGHT: (C)2010 ...

МНОГОФАЗНАЯ ШИНА ЭЛЕКТРОПИТАНИЯ ДЛЯ ПЕРЕДАЧИ ЭЛЕКТРОЭНЕРГИИ, СПОСОБ ЕЕ ИЗГОТОВЛЕНИЯ И КОММУТАЦИОННЫЙ ШКАФ, ВКЛЮЧАЮЩИЙ В СЕБЯ ТАКУЮ ШИНУ ЭЛЕКТРОПИТАНИЯ

Изобретение относится к многофазной шине электропитания для передачи электроэнергии, способу ее изготовления и коммутационному шкафу, включающему такую шину. Технический результат - обеспечение многофазной шины электропитания, которая легка в изготовлении и обладает сниженной тенденцией к расслаиванию слоев в случае электрического короткого замыкания, обеспечение способа изготовления такой шины, а также коммутационного шкафа, включающего в себя такую шину, которую можно изготавливать при сниженных затратах. Достигается тем, что многофазная шина (1) электропитания содержит необязательный базовый (2) слой изолирующего материала, первый (4a) проводящий слой тонколистового металла, первый (6a) слой изолирующего материала на первом (4a) проводящем слое, второй (4b) проводящий слой тонколистового металла на изолирующем слое (6a) и второй (6b) слой электроизолирующего материала, установленный на втором (4b) проводящем слое. Первый и второй проводящие слои (4a, 4b) могут содержать покрытие (14) ...

KASCHIERTE PLATTE FÜR EINE LEITERPLATTE, MEHRSCHICHTIGE LEITERPLATTE UND VERFAHREN ZU DEREN HERSTELLUNG

Elektronische Verdrahtungsstruktur

Connections for semiconductor devices

A lower conductive layer 2 is formed on a substrate and then a screen plate, with openings corresponding to desired positions on the lower conductive layer, is used for screen printing a metal paste which is dried and calcined by heat treatment to form a metal pillar 11. An insulating film 3 covering the lower conductive layer 2 and the metal pillar 11 is formed so that only the tip of the metal pillar 11 is exposed. An upper conductive layer 4 is formed on the insulating film 3 so that this layer contacts the exposed tip of the metal pillar. ...

SEMICONDUCTOR DEVICE MANUFACTURING METHOD

METHODS OF AND APPARATUS FOR ELECTROCHEMICALLY FABRICATING STRUCTURES VIA INTERLACED LAYERS OR VIA SELECTIVE ETCHING AND FILLING OF VOIDS

Methods to produce robust multilayer circuitry for electronic packaging

FIRING PROCESS FOR FORMING A MULTILAYER GLASS-METAL MODULE

MULTILAYER PRINTED WIRING BOARD AND PROCESS FOR MANUFACTURING THE SAME

КОНТАКТНЫЙ УЗЕЛ

Изобретение относится к изготовлению неразъемных соединений в процессе производства аппаратуры на основе изделий микроэлектроники и полупроводниковых приборов, а конкретно к контактным узлам, посредством которых осуществляется сборка, в том числе многослойных коммутационных структур для многокристальных модулей (МКМ), а также монтаж кристаллов БИС на коммутационной структуре в процессе изготовления МКМ. Контактный узел содержит, по крайней мере, два металлизированных контакта, связанных с токоведущими дорожками (2, 6), размещенными на поверхностях коммутационных слоев (3, 7), выполненных на основе из диэлектрического материала, совмещенных друг с другом и соединенных между собой электрически и механически электропроводящим связующим материалом (8). Контактный узел представляет собой стык между контактом, изготовленным в виде металлизированной контактной площадки (1), связанной с токоведущими дорожками (2) на поверхности нижележащего коммутационного слоя (3), и ответным контактом, выполненным ...

Multilayered structure forming method

Circuit device

High-density fine-line printed circuits prodn. - by forming circuit on a substrate, laminating a flowable insulating film and removing film and circuit pattern from substrate

MANUFACTORING PROCESS Of a MULTI-LAYER CONDUCTING SUBSTRATE

PROCESS OF FORMATION OF PILLARS OF the MULTI-LAYER NETWORK Of a CONNECTION CARD Of AT LEAST an INTEGRATED CIRCUIT OF HIGH DENSITY

A printed circuit board and a fabricating method the same

CIRCUIT DEVICES AND FABRICATION METHOD OF THE SAME

METHOD FOR FABRICATING MULTILAYER CIRCUIT BOARD, CIRCUIT PLATE, AND METHOD FOR FABRICATING THE CIRCUIT PLATE

A method for fabricating a circuit board comprises steps of: preparing a film (1) with interlayer adhesive, in which a first protective film (102) and a first interlayer adhesive (104) are stacked; preparing a first circuit board (2) having a first substrate (202) and a conductive post (204) protruding from the first substrate (202); stacking the surface of the first interlayer adhesive and the surface having the conductive post; peeling off the first protective film (102); preparing a second circuit board (3) having a conductive pad (302) receiving the conductive post (204); and stacking and bonding the first circuit board (2) and the second circuit board (3) through the first interlayer adhesive (104) so that the conductive post (204) and the conductive pad (302) are opposed to each other. In the peeling off step, in addition to peeling off the first protective film (102), the first interlayer adhesive (104) at the top portion (206) of the conductive post is selectively removed. © KIPO ...

Multilayer circuit board, manufacturing method therefor, electronic device, and electronic apparatus

WIRING BOARD AND METHOD FOR MANUFACTURING SAME

Reliability on electrical connection between a conductive layer and a bump is adequately secured, while achieving sufficient mechanical strength between an insulating layer and the conductive layer. A conductive layer is formed on an insulating layer (5) wherein a bump (4) for interlayer connection is buried, and the conductive layer and the bump (4) are electrically connected with each other. The conductive layer is composed of a second metal foil (6) which is provided with an opening (7) in a position corresponding to the bump (4), and a connection layer (9) which is formed in contact with the front end face (4a) of the bump (4) facing the opening (7) of the second metal foil (6). When manufacturing a wiring board, the second metal foil (6) which is provided with the opening (7) in advance is bonded to the insulating layer (5) wherein the bump (4) is buried, and then a plating layer is formed. Alternatively, the opening (7) is formed after bonding the second metal foil (6) to the insulating ...

TRANSMISSION CABLE AND PROCESS FOR PRODUCING SAME

Câble de transmission comportant une pluralité de lignes de signaux (2) formées sur un côté d’une couche isolante (1) et une ligne de surface (3) formée entre les lignes de signaux (2). La ligne de surface (3) est connectée électriquement à une couche de protection (4) formée sur la surface arrière de la couche isolante (1) grâce à une bosse de métal (5) incorporée dans la couche isolante (1). En variante, les couches isolantes (1, 6) et les couches de protection (4, 7) peuvent être formées sur les côtés opposés des lignes de signaux (2) et de la ligne de surface (3). Dans ce cas, la ligne de surface (3) est connectée électriquement aux couches de protection (4, 7) respectivement grâce aux bosses de métal (5, 8) situées sur les côtés opposés. En conséquence, il est possible d’obtenir un câble de transmission très fiable susceptible de réaliser un transfert à débit élevé et un transfert de grande capacité.

STRUCTURE AND METHOD OF MAKING INTERCONNECT ELEMENT, AND MULTILAYER WIRING BOARD INCLUDING THE INTERCONNECT ELEMENT

An interconnect element (2) is provided which includes a dielectric element (4) having a first major surface, a second major surface remote from the first major surface, and a plurality of recesses extending inwardly from the first major surface. A plurality of metal traces (6), (6a) are embedded in the plurality of recesses, the metal traces having outer surfaces substantially co-planar with the first major surface and inner surfaces remote from the outer surfaces. A plurality of posts (8) extend from the inner surfaces of the plurality of metal traces (6), (6a) through the dielectric element (4), the plurality of posts having tops exposed at the second major surface. A multilayer wiring board (12) including a plurality of such interconnect elements (2) is also provided, as, well as various methods for making such interconnect elements and multilayer wiring boards.

PRINTED CIRCUIT BOARD AND METHOD FOR MANUFACTURING THE SAME

Disclosed are a printed circuit board and a method for manufacturing the same. The printed circuit board includes a core insulating layer, at least one via formed through the core insulating layer, an inner circuit layer buried in the core insulating layer, and an outer circuit layer on a top surface or a bottom surface of the core insulating layer, wherein the via includes a center part having a first width and a contact part having a second width, the contact part makes contact with a surface of the core insulating layer, and the first width is larger than the second width. The inner circuit layer and the via are simultaneously formed so that the process steps are reduced. Since odd circuit layers are provided, the printed circuit board has a light and slim structure.

MULTILAYER PRINTED WIRING BOARD AND PROCESS FOR PRODUCING THE SAME

A process for producing a multilayer printed wiring board comprising a step for forming a conductor pattern (3a) on a multilayer of a first metal layer (1) becoming a first interlayer connector and a first protective metal layer (2) of a different metal, a step for forming a second protective metal layer (11) coating it, a step for farther forming a second metal layer (14) of a different metal, a step for forming a second mask layer (15) on the surface part thereof, a step for etching it selectively to form a second interlayer connector (14a), a step for forming a second insulating layer on the surface thereof, a step for forming a first mask layer on the surface part of the first metal layer, a step for etching it selectively to form a first interlayer connector, and a step for etching and removing the first protective metal layer (2) and the second protective metal layer (11) selectively.

Forming interconnections for multilevel interconnection metallurgy systems

A method for forming feedthrough connections, or via studs, between levels of metallization which are typically formed atop semiconductor substrates. A conductive pattern is formed which includes the first level metallurgy, an etch barrier and the feedthrough metallurgy in the desired first level metallurgical configuration. The via stud metallurgy alone is then patterned, preferably by reactive ion etching, using the etch barrier to prevent etching of the first level metallurgy. An insulator is then deposited around the via studs to form a planar layer of studs and insulator, after which a second level of metallization may be deposited.

Circuit devices and fabrication Method of the same

A supporting member or first synthetic resin sheet with conductive bumps disposed at predetermined positions are superposed on a second synthetic resin sheet under the condition that the resin component of the second synthetic resin sheet is plastic deformed or the temperature thereof exceeds a glass transition temperature so that the conductive bumps are pierced into the second synthetic resin sheet. In other words, the conductive bumps are pierced vertically into the second synthetic resin sheet so as to form through-type conducive lead portions exposed to the first (supporting substrate) and second synthetic resin sheets. The through-type conductive lead portions are used to electrically connect electric devices and circuit and to connect wiring pattern layers. The conductive bumps can be precisely and densely formed and disposed by printing method or plating method. The conductive bumps can be pushed and pierced into the second synthetic resin sheet. Moreover, the conductive bumps can ...

Methods of and Apparatus for Forming Three-Dimensional Structures Integral with Semiconductor Based Circuitry

Enhanced Electrochemical fabrication processes are provided that can form three-dimensional multi-layer structures using semiconductor based circuitry as a substrate. Electrically functional portions of the structure are formed from structural material (e.g. nickel) that adheres to contact pads of the circuit. Aluminum contact pads and silicon structures are protected from copper diffusion damage by application of appropriate barrier layers. In some embodiments, nickel is applied to the aluminum contact pads via solder bump formation techniques using electroless nickel plating. In other embodiments, selective electroless copper plating or direct metallization is used to plate sacrificial material directly onto dielectric passivation layers. In still other embodiments, structural material deposition locations are shielded, then sacrificial material is deposited, the shielding is removed, and then structural material is deposited. In still other embodiments structural material is made to ...

Firing process for forming a multilayer glass-metal module

A process for forming a glass interconnection package for semiconductor chips including the steps of depositing a first layer of glass material on a supporting substrate and then heating the layer in a first gaseous ambient which is soluble in the glass material. Immediately thereafter, the first gaseous ambient is replaced by a second gaseous ambient which is insoluble in the glass material and the glass layer is heated and then cooled down to ambient atmosphere.

Method For Manufacturing Multilayer Wiring Board

A process for manufacturing a multilayer wiring board including the steps of forming an insulating layer on a base provided with a bump for interlayer connection, bonding a copper foil onto the insulating layer by a thermocompression bonding by sandwiching the copper foil between stainless steel plates, and patterning the copper foil, in which a metal foil is interposed at least between each of the stainless plates and the copper foil at the time of the thermocompression bonding. At this time, a mold release layer is formed on a surface of the metal foil to be imposed. Thus, such a multilayer wiring board can be manufactured that prevents sticking of a product after molding (cementing of the copper foil) and excels in dimensional stability without occurrence of wrinkling and ruggedness.

CONNECTION BOARD, AND MULTI-LAYER WIRING BOARD, SUBSTRATE FOR SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE USING CONNECTION BOARD, AND MANUFACTURING METHOD THEREOF

The present invention provides a connection board that is formed by an insulating resin composition layer made of one layer or two or more layers and a connection conductor that is formed so as to pass through the insulating resin composition layer in its thickness direction at a position where a conductor circuit is connected, and a multi-layer wiring board, a substrate for semiconductor package and a semiconductor package using the connection board, and methods for manufacturing them.

CONNECTION BOARD, AND MULTI-LAYER WIRING BOARD, SUBSTRATE FOR SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE USING CONNECTION BOARD, AND MANUFACTURING METHOD THEREOF

The present invention provides a connection board that is formed by an insulating resin composition layer made of one layer or two or more layers and a connection conductor that is formed so as to pass through the insulating resin composition layer in its thickness direction at a position where a conductor circuit is connected, and a multi-layer wiring board, a substrate for semiconductor package and a semiconductor package using the connection board, and methods for manufacturing them.

Method of making an electronic component

A method for making an electronic component, for example, a motor coil. The method comprises the steps of forming a plurality of conductive layers and interconnecting the layers to provide an electrically conductive path between the layers. In order to form interconnections between the layers which have a low electrical resistance and which can be formed in a high-speed automated process, a conductive paste is applied to one of the conductive layers and the layers are superposed to form the interconnections.

Polyimide multilayer wiring board and method of producing same

A polyimide multilayer wiring board is constructed by using a plurality of laminated blocks each of which has a plurality of wiring layers and interlaminar insulating layers of polyimide. On a base block having a substrate, the other blocks are laid on top of another, bonded to each other with a polyimide used in each block or another adhesive and electrically connected to each other by using, for example, metal bumps formed on each block. Each of the blocks except the base block is formed on a temporary substrate, and the temporary substrate is removed after bonding each block to the base block or precedingly bonded blocks. This multilayer wiring board can be produced in a shortened time with increased yield.

Printed circuit assembly and method of manufacture therefor

A printed circuit assembly and method of making the same utilize in one embodiment an adhesive layer including a plurality of non-conductive "gauge particles" disposed within a non-conductive adhesive. When the adhesive layer is disposed between opposing printed circuit layers (be they insulating substrates, conductive layers, or other layers), individual gauge particles are interposed or sandwiched at various points between the layers such that the diameters of the particles control the layer separation throughout overlapping areas of thereof, thereby permitting careful control over layer separation. A printed circuit assembly and method of making the same utilize in another embodiment an interlayer interconnecting technology incorporating conductive posts that are deposited on one of a pair of contact pads formed on opposing printed circuit boards and thereafter bonded to the other in the pair of contact pads during lamination. Fusible material may be utilized in the conductive posts ...

Process for fabricating an interconnected multilayer board

A process for the fabrication of an interconnected multilayer board involves the steps of forming a metallic under-conductive layer on a base substrate, forming a windowed resist layer on the metallic under-conductive layer, filling windows of the resist layer with a conductor by plating thereby forming a conductor layer, forming another windowed resist layer on the conductor layer and filling windows of this resist layer with a conductor by plating, thereby forming a via-hole layer and to provide a two-level structure of the conductor layer and the via-hole layer. Thereafter, the resist layers and portions of the metallic under-conductor layer other than those in contact with a lower face of the conductor constituting the conductor layer are dissolved to form a two-level skeleton structure of conductor lines and spaces within the skeleton structure are filled with a varnish in a solventless form and the varnish is cured.

METHODS OF FORMING CIRCUIT INTERCONNECTIONS

A method of forming circuit interconnections between adjacent circuits of a multilayer circuit structure is described in which corresponding sets of solder protrusions carried on conductive tracks of adjacent circuits are separated by a layer of uncured, heat-curable insulating material having a transient state, in which the material becomes deformable, between the uncured and the cured states. The layer is heated and the circuits are urged towards one another during the transient, deformable state of the material so that the protrusions pierce the layer, corresponding protrusions contacting one another and the heat subsequently causing the material to become cured. Finally, the contacting protrusions are fused together.

Manufacturing method of double layer circuit board

A manufacturing method of a double layer circuit board comprises forming a connecting pillar on a first circuit, wherein the connecting pillar comprises a first end, connected to the first circuit, and a second end, opposite to the first end; forming a substrate on the first circuit and the connecting pillar; drilling the substrate to expose a portion of the second end of the connecting pillar, wherein the other portion of the second end of the connecting pillar is covered by the substrate; and forming a second circuit on the substrate and the portion of the second end of the connecting pillar, wherein an area of the first end connected to the first circuit layer is greater than an area of the portion of the second end connected to the second circuit layer.

Integrated circuit packaging system with coreless substrate and method of manufacture thereof

An integrated circuit packaging system and method of manufacture thereof includes: discrete components coupled to a top trace; vias attached to the top trace separated from the discrete components; a dielectric layer on the top trace, the discrete components, and the vias, includes a component surface formed above the discrete components, with the top trace coplanar with the dielectric layer; and system interconnects coupled to the vias for electrically connecting the top trace, the discrete components, or a combination thereof to the system interconnects.

STACKED MULTILAYER STRUCTURE

Disclosed is a stacked multilayer structure, including a first circuit layer having bumps, a plastic film stacked on the first circuit layer to fill up the space among the bumps so as to form a co-plane, and a second circuit layer formed on the co-plane and connected to the first circuit layer. The plastic film includes a glass fiber layer which is embedded and not exposed. The adhesion between plastic film and the second circuit layer is greatly improved because the glass fiber layer of the plastic film filling up the space among the bumps is not deformed and exposed outwards. Therefore, the yield and reliability of the stacked multilayer structure is increased.

Wiring board and multilayer wiring board

A wiring board formed by an electrophotographic system of transferring a visible image to a substrate, the wiring board including: a substrate to which a visible image is transferred; a nonconductive metal-containing resin layer selectively formed on the substrate and containing metal particulates dispersed therein; a conductive conductor metal layer formed on the metal-containing resin layer; and a resin layer formed contiguously to the metal-containing resin layer on the substrate.

Method for making a build-up package of a semiconductor

A method for making a build-up package of a semiconductor die and a structure formed from the same. A copper foil with conductive columns is bonded to an encapsulated die by thermal compression, between thereof there is a pre-curing dielectric film sandwiched. The dielectric film is cured to form a dielectric layer of a die build-up package and the copper foil on the dielectric layer is etched to form the conductive traces. At least one conductive column in one of the dielectric layers is vertically corresponding to one of conductive column in the adjacent dielectric layer.

Electronic interconnect structure and method for manufacturing it

Multi-layer printed circuit structure

SUBSTRATE AND METHOD OF MANUFACTURING THE SAME

PROBLEM TO BE SOLVED: To provide a substrate in which a fine metal column is formed by injecting and depositing metal particles dispersion onto the substrate using a fine ink-jet printing method capable of fine drawing, a manufacturing method thereof, a substrate structured to have a high aspect ratio, and a manufacturing method simply producing the substrate at high speed. SOLUTION: In the substrate manufacturing method, metal particles are deposited on a certain position of a substrate in a column state by using a fine ink-jet method and then sintered, thus a metal column is formed. COPYRIGHT: (C)2005,JPO&NCIPI ...

MANUFACTURING METHOD FOR MULTILAYER WIRING BOARD, MULTILAYER WIRING BOARD, ELECTRONIC DEVICE, AND ELECTRONIC INSTRUMENT

PROBLEM TO BE SOLVED: To provide a multilayer wiring board, its manufacturing method, an electronic device, and an electronic instrument. SOLUTION: The manufacturing method for the multilevel interconnection substrate, which has at least two wiring layers 17, an interlayer insulating film 24 provided between the wiring layers 17, and a conducting post 18 that the wiring layers 17, changes the film thickness according to the shape of an uneven part of the insulating film formation area where the interlayer insulating film 24 is formed so that the upper surface of the interlayer insulating film 24 may be flat, thus forming the interlayer insulating film 24. COPYRIGHT: (C)2004,JPO&NCIPI ...

METHOD OF MANUFACTURING OPTICAL WAVEGUIDE LAMINATED WIRING BOARD

PROBLEM TO BE SOLVED: To miniaturize the pitch of conduction vias to be formed on an optical waveguide board to be integrated, and to prevent degradation of a yield due to insufficient filling of a conductive material. SOLUTION: Vias are opened on a first clad layer 21 laminated on a wiring board 10, the opened vias are filled with a conductive material to form first conductor parts 24 (partial parts of the conduction vias) each having a shape projecting in a mushroom-like form from the surface of the first clad layer 21. Vias are opened on a second clad layer 23 formed by covering a core layer 22 and the first clad layer 21 along with the first conductor parts 24, the opened vias are filled with a conductive material to form second conductor parts 25 (residual parts of the conduction vias) connected to the first conductor parts 24. COPYRIGHT: (C)2011,JPO&INPIT ...

Method of manufacturing printed circuitry

A polished substrate 14 carries thin layers of nickel and copper over which a photo-resist layer 10 is applied. A film of lubricating wax 16 is optionally applied to the layer 10 before a photomask 18 is placed in position and pressed into intimate contact by passing the assembly through pressure rollers 20 and 22. Subsequently the resist layer is exposed through the mask and developed to form spaces into which the required conductive circuit pattern is deposited. The remaining photo-resist is removed, an insulating layer is laminated to the pattern and the assembly is stripped from the substrate, after which the copper and nickel layers are etched away. ...

FORMING A GLASS LAYER ON A SUBSTRATE

... 1366602 Coating with glass INTERNATIONAL BUSINESS MACHINES CORP 28 July 1972 [27 Aug 1971] 35353/72 Heading C1M [Also in Division H1] A method of producing a glass layer on a ceramic substrate comprises depositing a glass slurry on the substrate and firing the structure in a first gaseous atmosphere which is soluble in the glass, and a second atmosphere which is less soluble in the glass. The first atmosphere may be hydrogen, the second, nitrogen or argon. The firing preferably takes place at the glass sintering temperature and results in a bubble free layer. The glass may be used as insulation layers between interconnection levels in a printed circuit. The substrate used is alumina with a metallizing layer and the glass is chosen to have a lower coefficient of thermal expansion than the ceramic. Specification 1,366,601 is referred to.

METHODS OF FORMING CIRCUIT INTERCONNECTIONS

... 1353671 Direct connections INTERNATIONAL COMPUTERS Ltd 12 May 1972 [10 June 1971] 27362/71 Heading H2E [Also in Division H1] Connections between layers in a multilayer printed circuit are formed without drilling holes. Fibreglass epoxy substrates 11, 15, carrying printed wiring 17 and lumps 13, 14 of solder or copper covered with solder, are placed in a press on opposite sides of a sheet 12 of uncured phenolic-butynol dry adhesive and the structure is heated to 160‹ C. When the sheet 12 is heated it first softens and then is cured. While it is soft the lumps 13 force their way through it until they touch. When the sheet 12 has been cured the structure is heated to 250‹ C. and the solder lumps 13 melt and form connections between the two sets of wiring 17. The substrates 11, 15 may carry copper earth planes 10, 16. The sheet 12 may be of any insulating material having uncured, plastic and cured states.

IN AN ENVIRONMENTALLY FRIENDLY MANNER MANUFACTURED PRINTED CIRCUIT BOARD AND ASSOCIATED DEVICE

MULTILEVEL SUBSTRATE

SUBSTRATE, WIRING BOARD, SEMICONDUCTOR PACKAGE-USE SUBSTRATE, SEMICONDUCTOR PACKAGE AND PRODUCTION METHODS FOR THEM

METHOD OF AND APPARATUS FOR FORMING THREE-DIMENSIONAL STRUCTURES INTEGRAL WITH SEMICONDUCTOR BASED CIRCUITRY

Monolithic structures including alignment and/or retention fixtures for accepting components

Printed circuit board and method of manufacturing the same

Disclosed herein are a printed circuit board and a method of manufacturing the same. The printed circuit board includes: an insulating layer; a first circuit layer including a first metal layer and a first plating layer provided on an outer side of the first metal layer and embedded in one surface of the insulating layer; a second circuit layer including a second metal layer and a second plating layer provided on an outer side of the second metal layer and embedded in the other surface of the insulating layer; and a bump interconnecting the first circuit layer and the second circuit layer while penetrating through the insulating layer. The bump is used, such that there is no need to perform hole plating. Therefore, an increase in the surface plating thickness due to the hole plating is previously prevented.

Printed circuit board

A printed circuit board having an insulating layer; circuit patterns formed on both surfaces of the insulating layer in order to be embedded in the insulating layer; and a bump formed to pass through the insulating layer in order to electrically connect the circuit patterns formed on both surfaces of the insulating layer.

Wiring board and method of manufacturing the same

A wiring board includes a first substrate portion including a first feed-through conductor portion in a vertical direction, a second substrate portion provided on the first substrate portion and including a second feed-through conductor portion in a vertical direction of a corresponding part to the first feed-through conductor portion, and a feed-through electrode including the first feed-through conductor portion and the second feed-through conductor portion.

Package substrate and die spacer layers having a ceramic backbone

A layer or layers for use in package substrates and die spacers are described. The layer or layers include a plurality of ceramic wells lying within a plane and separated by metallic vias. Recesses within the ceramic wells are occupied by a dielectric filler material.

Alignment between layers of multilayer electronic support structures

A process for alignment a subsequent layer over a previous layer comprising metal features or vias encapsulated in dielectric material comprising the steps of: thinning and planarizing the dielectric material to create a smooth surface of dielectric material and coplanar exposed ends of the via posts; imaging the smooth surface; discerning the position of the end of at least one feature, and using the position of the end of at least one via feature as a registration mark for aligning the subsequent layer.

Printed circuit board and method for manufacturing the same

Disclosed are a printed circuit board and a method for manufacturing the same. The printed circuit board includes a core insulating layer, at least one via formed through the core insulating layer, an inner circuit layer buried in the core insulating layer, and an outer circuit layer on a top surface or a bottom surface of the core insulating layer, wherein the via includes a center part having a first width and a contact part having a second width, the contact part makes contact with a surface of the core insulating layer, and the first width is larger than the second width. The inner circuit layer and the via are simultaneously formed so that the process steps are reduced. Since odd circuit layers are provided, the printed circuit board has a light and slim structure.

Printed wiring board and method for manufacturing printed wiring board

A method for manufacturing a printed wiring board includes forming metal posts on a conductor circuit formed on a resin insulating layer, forming the outermost resin layer on the resin insulating layer such that the metal posts is embedded in the outermost resin layer, forming a mask at a dam formation site for a dam structure of the outermost resin layer to surround at least part of a pad group including the metal posts on the outermost resin layer, and reducing a thickness of the outermost resin layer exposed from the mask such that end portions of the metal posts are exposed from the outermost resin layer, that the metal posts form the pad group, and that the outermost resin layer has the dam structure forming part of the outermost resin layer and formed to surround at least part of the pad group including the metal posts.

Semiconductor device and manufacturing method thereof

A semiconductor structure includes a molding compound, a conductive plug, and a cover. The conductive plug is in the molding compound. The cover is over a top meeting joint between the conductive plug and the molding compound. The semiconductor structure further has a dielectric. The dielectric is on the cover and the molding compound.

METHOD OF MANUFACTURING MULTILAYER WIRING BOARD, PROBE CARD INCLUDING MULTILAYER WIRING BOARD MANUFACTURED BY THE METHOD, AND MULTILAYER WIRING BOARD

A method of manufacturing a multilayer wiring board includes a stacking process in which insulating layers, each of which includes a ceramic layer and a shrinkage suppression layer being stacked on top of the ceramic layer, are stacked on top of one another, a press-bonding process in which the insulating layers are press-bonded, so that a multilayer body is formed, and a firing process in which the multilayer body is fired. In the stacking process, in each of the insulating layers, a wiring electrode is formed on a surface of the shrinkage suppression layer on the opposite side to the surface of the layer facing the ceramic layer, and the thickness of a peripheral area of the shrinkage suppression layer located around the area of the shrinkage suppression layer that is in contact with the electrode is larger than those of portions of the layer except for the peripheral area.

Circuit board and method for manufacturing the same

A circuit board element includes a glass substrate, a first dielectric layer, and a first patterned metal layer. The glass substrate has an edge. The first dielectric layer is disposed on the glass substrate and has a central region and an edge region. The edge region is in contact with the edge of the glass substrate, and the thickness of the central region is greater than the thickness of the edge region. The first patterned metal layer is disposed on the glass substrate and in the central region of the first dielectric layer.

CIRCUIT BOARD AND METHOD FOR MANUFACTURING THE SAME

A circuit board with a heat-recovery function includes a substrate, a heat-storing device, and a thermoelectric device. The heat-storing device is embedded in the substrate and connected to a processor for performing heat exchange with the processor. The thermoelectric device embedded in the substrate includes a first metal-junction surface and a second metal-junction surface. The first metal-junction surface is connected to the heat-storing device for performing heat exchange with the heat-storing device. The second metal-junction surface is joined with the first metal-junction surface, in which the thermoelectric device generates an electric potential by a temperature difference between the first metal-junction surface and the second metal-junction surface. 1. A method for a circuit board with a heat-recovery function , comprising:forming a first opening in a first buildup-dielectric layer and disposing a heat-storing device into the first opening for embedding the heat-storing device in the first buildup-dielectric layer;disposing a first pattern-metal layer on the first buildup-dielectric layer and the heat-storing device;disposing a second buildup-dielectric layer on the first buildup-dielectric layer and the first pattern-metal layer, wherein the second buildup-dielectric layer comprises a second opening communicating to the first opening;disposing an interposer board on the heat-storing device and in the second opening, and disposing a second pattern-metal layer on the second buildup-dielectric layer and the interposer board; andforming a third opening at the first buildup-dielectric layer or the second buildup-dielectric layer, and disposing a thermoelectric device into the third opening for embedding the thermoelectric device in the first buildup-dielectric layer or the second buildup-dielectric layer, wherein the thermoelectric device is connected to the heat-storing device through the first pattern-metal layer.2. A method for a circuit board with a heat- ...

INSULATING FILM, PRINTED CIRCUIT BOARD USING THE SAME, AND METHOD OF MANUFACTURING THE PRINTED CIRCUIT BOARD

There are provided an insulating film, a printed circuit board including the insulating film, and a method of manufacturing the printed circuit board. The insulating film includes a first insulating material; a second insulating material; and a metal thin film disposed between the first insulating material and the second insulating material. 1. An insulating film comprising:a first insulating material;a second insulating material; anda metal thin film disposed between the first insulating material and the second insulating material.2. A printed circuit board comprising:a board on which an inner layer buildup layer is formed;a first insulating layer formed on the inner layer buildup layer;a metal layer formed on the first insulating layer;a second insulating layer formed on the metal layer;a via formed to pass through the first insulating layer, the metal layer, and the second insulating layer and be in contact with an inner layer circuit layer of the inner layer buildup layer; andan insulating coating layer formed between the first insulating layer, the metal layer, and the second insulating layer and the via.3. The printed circuit board of claim 2 , wherein the metal layer is formed to be in contact with an entire one surface of the first insulating layer.4. The printed circuit board of claim 2 , wherein the metal layer is a ground layer.5. The printed circuit board of claim 2 , wherein the inner layer buildup layer includes one or more layers of the inner layer circuit layer.6. The printed circuit board of claim 2 , further comprising: a solder resist layer formed on the second insulating layer.7. The printed circuit board of claim 2 , further comprising: an outer layer buildup layer formed on the second insulating layer and including one or more layers of outer layer circuit layer.8. The printed circuit board of claim 7 , further comprising: a solder resist layer formed on the outer layer buildup layer.9. A method of manufacturing a printed circuit board claim 7 ...

Semicondcutor package and manufacturing method thereof

A method includes the following steps. A seed layer is formed over a structure having at least one semiconductor die. A first patterned photoresist layer is formed over the seed layer, wherein the first patterned photoresist layer includes a first opening exposing a portion of the seed layer. A metallic wiring is formed in the first opening and on the exposed portion of the seed layer. A second patterned photoresist layer is formed on the first patterned photoresist layer and covers the metallic wiring, wherein the second patterned photoresist layer includes a second opening exposing a portion of the metallic wiring. A conductive via is formed in the second opening and on the exposed portion of the metallic wiring. The first patterned photoresist layer and the second patterned photoresist layer are removed. The metallic wiring and the conductive via are laterally wrapped around with an encapsulant.

INTERPOSER SUBSTRATE AND METHOD OF MANUFACTURING THE SAME

A method of manufacturing an interposer substrate, including providing a carrier having a first circuit layer formed thereon, forming a plurality of conductive pillars on the first circuit layer, forming a first insulating layer on the carrier, with the conductive pillars being exposed from the first insulating layer, forming, on the conductive pillars a second circuit layer that is electrically connected to the conductive pillars, forming a second insulating layer on the second surface of the first insulating layer and the second circuit layer, exposing a portion of a surface of the second circuit layer from the second insulating layer, and removing the carrier. The invention further provides the interposer substrate as described above. 19.-. (canceled)10. A method of manufacturing an interposer substrate , comprising:providing a carrier having a first wiring layer and a plurality of conductive pillars disposed on the first wiring layer;forming on the carrier a first insulating layer that has a first surface and a second surface opposing the first surface and is coupled to the carrier via the first surface thereof, with the conductive pillars being exposed from the second surface of the first insulating layer;forming on the second surface of the first insulating layer and the conductive pillars a second wiring layer that is electrically connected with the conductive pillars;forming on the second surface of the first insulating layer and the second wiring layer a second insulating layer, from which a portion of a surface of the second wiring is exposed; andremoving the carrier to allow the first wiring layer to be exposed from the first surface of the first insulating layer.11. The method of claim 10 , wherein the first insulating layer is formed on the carrier by a molding claim 10 , coating claim 10 , or lamination process.12. The method of claim 10 , wherein the first wiring layer has a surface lower than the first surface of the first insulating layer.13. The ...

PRINTED WIRING BOARD AND METHOD FOR MANUFACTURING PRINTED WIRING BOARD

A printed wiring board includes a first circuit substrate having first and second surfaces, and a second circuit substrate having third and fourth surfaces such that the first substrate is laminated on the third surface and that the first and third surfaces are opposing each other. The second substrate includes a conductor layer, a first insulating layer including reinforcing material and formed on the conductor layer, and mounting via conductors formed in the first insulating layer and connected to the conductor layer such that the second substrate has a mounting area on the third surface and that the mounting via conductors have via bottoms forming pads positioned to mount an electronic component in the mounting area, and the first substrate includes an insulating layer which does not contain reinforcing material and has an opening through the insulating layer and exposing the via bottoms forming the pads in the mounting area. 1. A printed wiring board , comprising:a first circuit substrate having a first surface and a second surface on an opposite side with respect to the first surface; anda second circuit substrate having a third surface and a fourth surface on an opposite side with respect to the third surface such that the first circuit substrate is laminated on the third surface and that the first surface and the third surface are opposing each other,wherein the second circuit substrate comprises a first conductor layer, a first resin insulating layer including a reinforcing material and formed on the first conductor layer, and a plurality of mounting via conductors formed in the first resin insulating layer and connected to the first conductor layer such that the second circuit substrate has a mounting area on the third surface and that the plurality of mounting via conductors has a plurality of via bottoms forming a plurality of pads and positioned to mount an electronic component in the mounting area, respectively, and the first circuit substrate comprises ...

TOUCH SCREEN, METHOD FOR PRODUCING TOUCH SCREEN, TOUCH DISPLAY DEVICE

The embodiments of the invention disclose a touch screen, a method for producing a touch screen, and a touch display device, which relate to a field of display. The touch screen does not need bridging, have high transmittance, and are simple in process, which can not only reduce the production cost but also achieve a high yield of mass production. The touch screen as provided in the embodiments of the invention comprises: a transparent substrate; a first patterned transparent eclectically conductive layer; a patterned insulating layer and a second patterned transparent eclectically conductive layer, which are formed above said transparent substrate successively, wherein among said first patterned transparent electrically conductive layer and said second patterned transparent electrically conductive layer, one is formed with a plurality of drive lines, and the other is formed with a plurality of induction lines; the pattern of said insulating layer is identical with that of said first patterned transparent electrically conductive layer, or identical with that of said second patterned transparent electrically conductive layer. 1. A touch screen , comprising:a transparent substrate;a first patterned transparent electrically conductive layer;a patterned insulating layer; anda second patterned transparent electrically conductive layer;wherein said first patterned transparent electrically conductive layer, said patterned insulating layer, and said second patterned transparent electrically conductive layer are formed successively above said transparent substrate;wherein one of the first and second patterned transparent electrically conductive layers comprises a plurality of drive lines;wherein the other of the first and second patterned transparent electrically conductive layers comprises a plurality of induction lines;wherein an insulating pattern of said patterned insulating layer is selected from the group consisting of a first pattern of the first patterned transparent ...

PACKAGE BOARD, METHOD FOR MANUFACTURING THE SAME AND PACKAGE ON PACKAGE HAVING THE SAME

There are provided a package board, a method for manufacturing the same, and a package on package having the same. The package board according to an exemplary embodiment of the present disclosure includes a first insulating layer formed with a cavity having a penetrating shape; and a first connection pad formed to penetrate through the first insulating layer and formed at one side of the cavity. 1. A package board , comprising:a first insulating layer formed with a cavity having a penetrating shape; anda first connection pad formed to penetrate through the first insulating layer and formed at one side of the cavity.2. The package board of claim 1 , further comprising:a second connection pad formed on the first connection pad and the first insulating layer and formed to be exposed to the outside.3. The package board of claim 2 , wherein the second connection pad is formed to have a diameter larger than that of the first connection pad.4. The package board of claim 1 , wherein the first connection pad includes:a metal post; anda barrier layer formed to be bonded to a lower surface of the metal post.5. The package board of claim 1 , further comprising:a second insulating layer formed beneath the first insulating layer; anda first circuit pattern formed inside the second insulating layer.6. The package board of claim 5 , wherein an upper surface of the first circuit pattern is exposed to the outside by the cavity.7. The package board of claim 1 , further comprising:a build up layer formed under the first insulating layer.8. A method for manufacturing a package board claim 1 , comprising:forming a first connection pad and a cavity pattern on a carrier substrate;forming a first insulating layer which is formed on the carrier substrate and has the first connection pad and the cavity pattern embedded therein to expose upper surfaces of the first connection pad and the cavity pattern;removing the carrier substrate; andremoving the cavity pattern to form a cavity.9. The ...

Multilayer electronic structure with integral faraday shielding

A multilayer electronic support structure including at least one metallic component encapsulated in a dielectric material, and comprising at least one faraday barrier to shield the at least one metallic component from interference from external electromagnetic fields and to prevent electromagnetic emission from the metallic component.

INTERPOSER BOARD AND METHOD OF MANUFACTURING THE SAME

Disclosed herein are an interposer board and a method of manufacturing the same. According to a preferred embodiment of the present invention, the interposer substrate may include: a base substrate; a circuit pattern formed on the base substrate; and a through via formed to penetrate through the base substrate and have a height lower than that of the circuit pattern. 1. An interposer board , comprising:a base substrate;a circuit pattern formed on the base substrate; anda through via formed to penetrate through the base substrate and have a height lower than that of the circuit pattern.2. The interposer board as set forth in claim 1 , wherein an inside of the through via is filled with a filler and is formed to have a height lower than that of a side wall thereof.3. The interposer board as set forth in claim 1 , wherein an edge of an inside of the through via is formed to have a height lower than that of a center thereof.4. The interposer board as set forth in claim 1 , wherein an inside of the through via is made of a conductive material or a non-conductive material.5. The interposer board as set forth in claim 1 , wherein an inside of the through via is made of a photosensitive insulating material.6. The interposer board as set forth in claim 1 , wherein the base substrate and the circuit pattern are further provided with a build-up layer which includes a build-up insulating layer and a build-up circuit layer.7. The interposer board as set forth in claim 6 , wherein the build-up insulating layer and an inside of the through via are made of the same material.8. The interposer board as set forth in claim 6 , wherein the build-up insulating layer is made of a photosensitive insulating material.9. The interposer board as set forth in claim 1 , wherein a circuit layer formed in an inside of the through via and a circuit layer formed on a side wall thereof are formed to have the same height.10. A method for manufacturing an interposer board claim 1 , comprising:preparing ...

ELECTRONIC COMPONENT EMBEDDED SUBSTRATE AND METHOD OF MANUFACTURING ELECTRONIC COMPONENT EMBEDDED SUBSTRATE

An electronic component embedded substrate and a method of manufacturing an electronic component embedded substrate, The substrate includes a first via passing through a part of an insulating portion of the substrate to an electrode of the electronic component, and a second via passing through a part of the insulating portion to the conductor pattern. The second via has a contact portion with a smaller cross-sectional area than the cross-sectional area of a contact portion of the first via. 1. An electronic component embedded substrate comprising:an insulating layer having a cavity;an electronic component in the cavity and comprising an external electrode;a conductor pattern provided on a surface of the insulating layer;a build-up insulating layer provided on the insulating layer and covering the conductor pattern and the electronic component;a first via passing through the build-up insulating layer and having a first contact portion in contact with the external electrode; anda second via passing through the build-up insulating layer and having a second contact portion which is in contact with the conductor pattern and has a smaller cross-sectional area than that of the first contact portion.2. The electronic component embedded substrate according to claim 1 , wherein the electronic component is a multilayer ceramic capacitor (MLCC).3. The electronic component embedded substrate according to claim 1 , wherein a plurality of vias are in contact with the conductor pattern claim 1 , and the second via is a via formed in the position closet to the first via among the vias formed in the conductor pattern.4. The electronic component embedded substrate according to claim 1 , wherein a contact surface of the electronic component and the first via and a contact surface of the conductor pattern and the second via are positioned on the same horizontal plane.5. The electronic component embedded substrate according to claim 4 , wherein the first via and the second via have the ...

Wiring board and planar transformer

Disclosed is a wiring board having at least one insulating layer and at least one wiring layer arranged to overlap the insulating layer. The insulating layer includes: an arrangement portion at which the wiring layer is arranged; and a side wall portion which surrounds at least a part of the wiring layer arranged at the arrangement portion in a plane direction. The side wall portion has a planar shape that restricts movement and rotation of the wiring layer in the plane direction.

CIRCUIT BOARD AND METHOD FOR MANUFACTURING THE SAME

A circuit board element includes a glass substrate, a first dielectric layer, and a first patterned metal layer. The glass substrate has an edge. The first dielectric layer is disposed on the glass substrate and has a central region and an edge region. The edge region is in contact with the edge of the glass substrate, and the thickness of the central region is greater than the thickness of the edge region. The first patterned metal layer is disposed on the glass substrate and in the central region of the first dielectric layer. 1. A method for manufacturing a circuit board , comprising:forming a first sacrificial metal layer on a carrier, wherein the first sacrificial metal layer has a plurality of first openings;forming a first etching stop layer on the carrier, wherein the first etching stop layer covers the first sacrificial metal layer;forming a patterned resist on the first etching stop layer, wherein the patterned resist has a plurality of second openings and a intaglioed pattern, the second openings respectively correspond to the first openings to expose a part of the first sacrificial metal layer, and the intaglioed pattern exposes a part of the first etching stop layer;forming a plurality of metal bump in the first openings and the second openings and forming a first circuit layer in the intaglioed pattern;removing the patterned resist;forming a build-up structure on the first etching stop layer, wherein the build-up structure includes a dielectric layer, a plurality of conductive vias, and at least one second circuit layer, the dielectric layer covers the metal bumps and the first circuit layer, the conductive vias is formed in the dielectric layer, the second circuit layer is formed on the dielectric layer, the conductive vias connects the first circuit layer and the second circuit layer;a second etching stop layer is formed on the dielectric layer, wherein the second etching stop layer covers the second circuit layer;separating the carrier and the first ...

METHOD FOR PRODUCING RESIN MULTILAYER BOARD

A method for producing a resin multilayer board includes preparing a first resin layer including one or more conductor patterns that are disposed thereon and a conductor pattern including a first region that is to be connected to a conductor via; forming a paint layer by applying a paste including a LCP powder to a second region entirely covering the one or more conductor patterns; forming a cavity in the paint layer such that at least the first region is exposed, by performing laser processing; stacking a second resin layer including the conductor via on the first resin layer; and obtaining a resin multilayer board including a layer obtained by curing the paint layer, by applying pressure and heat to the multilayer body to perform thermal pressure-bonding. 1. A method for producing a resin multilayer board , comprising:preparing a first resin layer that includes a liquid crystal polymer as a main material, a main surface, and one or more conductor patterns disposed on the main surface, the one or more conductor patterns including a conductor pattern including a first region that is to be connected to a conductor via;forming a paint layer by applying a paste including a liquid crystal polymer powder to a second region entirely or substantially entirely covering the one or more conductor patterns on the main surface;forming a cavity in the paint layer such that at least the first region of the one or more conductor patterns is exposed, by performing laser processing on the paint layer;stacking a second resin layer including the conductor via, on the first resin layer after the cavity is formed, such that the conductor via overlaps the first region; andconnecting the conductor via and the conductor pattern in the first region and obtaining a resin multilayer board including a layer obtained by curing the paint layer, by applying pressure and heat to a multilayer body including a stack of the second resin layer stacked on the first resin layer to perform thermal ...

CIRCUIT BOARD AND METHOD FOR MANUFACTURING THE SAME

A circuit board element includes a glass substrate, a first dielectric layer, and a first patterned metal layer. The glass substrate has an edge. The first dielectric layer is disposed on the glass substrate and has a central region and an edge region. The edge region is in contact with the edge of the glass substrate, and the thickness of the central region is greater than the thickness of the edge region. The first patterned metal layer is disposed on the glass substrate and in the central region of the first dielectric layer. 1. A method for manufacturing a circuit board , comprising:forming a first sacrificial metal layer on a carrier, wherein the first sacrificial metal layer has a plurality of first openings;forming a first etching stop layer on the carrier, wherein the first etching stop layer covers the first sacrificial metal layer;forming a patterned resist on the first etching stop layer, wherein the patterned resist has a plurality of second openings and an intaglioed pattern, the second openings respectively correspond to the first openings to expose a part of the first sacrificial metal layer, and the intaglioed pattern exposes a part of the first etching stop layer;forming a plurality of metal bump in the first openings and the second openings and forming a first circuit layer in the intaglioed pattern;removing the patterned resist;forming a build-up structure on the first etching stop layer, wherein the build-up structure includes a dielectric layer, a plurality of conductive vias, and at least one second circuit layer, the dielectric layer covers the metal bumps and the first circuit layer, the conductive vias is formed in the dielectric layer, the second circuit layer is formed on the dielectric layer, the conductive vias connects the first circuit layer and the second circuit layer;a second etching stop layer is formed on the dielectric layer, wherein the second etching stop layer covers the second circuit layer;separating the carrier and the ...

LAMINATED SUBSTRATE AND METHOD OF MANUFACTURING LAMINATED SUBSTRATE

A laminated substrate includes: a first substrate; a second substrate having a through-hole; a third substrate; a first adhesive layer bonding a rear surface of the first substrate and a front surface of the second substrate; a second adhesive layer bonding a rear surface of the second substrate and a front surface of the third substrate; a first post penetrating through the first adhesive layer, electrically connecting the first substrate to the second substrate, and made of an alloy of a high melting point metal and a low melting point metal; a second post penetrating through the second adhesive layer, electrically connecting the second substrate to the third substrate, and made of an alloy of the high melting point metal and the low melting point metal; and an electronic component fixed to the front surface of the third substrate and disposed in the through-hole of the second substrate. 1. (canceled)2. A method of manufacturing a laminated substrate , the method comprising:preparing a first adhesive sheet having a first through-hole;preparing a second adhesive sheet having a second through-hole and a third through-hole;preparing a second substrate having a fourth through-hole;forming a first post by applying a conductive paste, in which a high melting point metal and a low melting point metal are mixed, to a rear surface of a first substrate or a front surface of the second substrate and heating the applied conductive paste to enter a semi-sintered state;forming a second post by applying the conductive paste, in which the high melting point metal and the low melting point metal are mixed, to a rear surface of the second substrate or a front surface of a third substrate and heating the applied conductive paste to enter a semi-sintered state;fixing an electronic component to the front surface of the third substrate; andafter the forming of the first post, the forming of the second post, and the fixing of the electronic component to the front surface of the third ...

Component-embedded substrate, method of manufacturing the same, and high-frequency module

A method of manufacturing a component-embedded substrate includes a resist forming step in which a patterning resist is formed on a support, a patterning step in which a through hole extending through the resist is formed by performing patterning on the resist, a first-electrode forming step in which a through-via electrode is formed by filling the through hole with an electrode material, a resist removing step in which the resist is removed, a component placement step in which an electronic component is placed, a substrate forming step in which a resin substrate is formed by sealing the electronic component with a resin that includes a filler having a diameter larger than the surface roughness of a side surface of the through-via electrode, and a removing step in which the support is removed from the resin substrate. The first-electrode forming step is performed before the substrate forming step is performed.

Component Carrier Having a Three Dimensionally Printed Wiring Structure

A component carrier and a method for manufacturing a component carrier is described wherein the component carrier includes a carrier body with a plurality of electrically conductive layer structures and/or electrically insulating layer structures and a wiring structure on and/or in the layer structures where the wiring structure is at least partially formed as a three-dimensionally printed structure. 1. A component carrier , wherein the component carrier comprises:a carrier body comprising at least one of a plurality of electrically conductive layer structures and electrically insulating layer structures; anda wiring structure on and/or in the layer structures and being at least partially formed as a three-dimensionally printed structure.2. The component carrier according to claim 1 , further comprising:a component mounted on and/or embedded in the carrier body.3. The component carrier according to claim 2 , wherein the wiring structure is configured to form an electronic and/or thermal connection with the electronic component.4. The component carrier according to claim 1 , wherein the wiring structure comprises at least one protrusion for forming an electrical and/or thermal contact claim 1 , wherein the wiring structure is at least partially surrounded by an encapsulation claim 1 , wherein the protrusion extends through the encapsulation for forming an electrical contact.5. The component carrier according to claim 1 , comprising at least one of the following features:wherein a cross section of the wiring structure perpendicular to a current propagation direction has a shape of at least one of the group comprising a rectangular shape, a fractal shape, a circular shape, an oval shape and an trapezoid shape,wherein the wiring structure formed extends along a stacking direction of the plurality of layer structures,wherein the wiring structure extends perpendicular with respect to a stacking direction of the plurality of layer structures.6. The component carrier ...

Circuit board and method for manufacturing the same

A circuit board with a heat-recovery function includes a substrate, a heat-storing device, and a thermoelectric device. The heat-storing device is embedded in the substrate and connected to a processor for performing heat exchange with the processor. The thermoelectric device embedded in the substrate includes a first metal-junction surface and a second metal-junction surface. The first metal-junction surface is connected to the heat-storing device for performing heat exchange with the heat-storing device. The second metal-junction surface is joined with the first metal-junction surface, in which the thermoelectric device generates an electric potential by a temperature difference between the first metal-junction surface and the second metal-junction surface.

FLEXIBLE PRINTED CIRCUIT BOARD

A flexible printed circuit board includes a base layer and a pattern line. At least one communication hole penetrating opposite surfaces of the base layer. The pattern line includes two conductive circuit layers formed on the opposite surfaces of the base layer. At least one conductive pole are formed in the at least one communication hole and electrically connects the two conductive circuit layers. A gap being is formed between the conductive pole and the base layer. 1. A flexible printed circuit board comprising:a base layer defining at least one communication hole penetrating opposite surfaces of the base layer;a pattern line comprising two conductive circuit layers formed on the opposite surfaces of the base layer; andat least one conductive pole formed in the at least one communication hole and electrically connecting the two conductive circuit layers, a gap being formed between the conductive pole and the base layer.2. The flexible printed circuit board of claim 1 , further comprising:an outer pattern line;a adhesive layer covering a side of the pattern line and the base layer on the same side that is not covered by the pattern line, the adhesive layer defining at least one through hole penetrating the adhesive layer to expose the pattern line;wherein the outer pattern line comprises an outer conductive layer formed on a surface of the adhesive layer away from the base layer, and the conductive post formed in the through hole and electrically connected to the outer conductive layer to the pattern line, a diameter of the conductive post is less than a diameter of the through hole.3. The flexible printed circuit board of claim 1 , further comprising:an outer pattern line;two adhesive layers, each adhesive layer covering one side of the pattern line and the base layer on the same side that is not covered by the pattern line, at least one adhesive layers defining at least one through hole penetrating the adhesive layer to expose the pattern line;wherein the outer ...

PRINTED WIRING BOARD

A printed wiring board includes a core substrate and first and second build-up layers. The substrate includes a core layer, through-hole conductors formed in through holes such that each through hole has first opening tapering from first toward second surface of the core layer, and second opening tapering from second toward first surface of the core layer, and first and second through-hole lands directly connected to the through-hole conductors. Each build-up layer includes an insulating layer, via conductors, via lands, an outermost insulating layer, an outermost conductor layer, and outermost via conductors. Each of the through-hole lands, via lands and outermost conductor layers includes a metal foil, a seed layer and an electrolytic plating film. The foils have mat surfaces such that the mat surfaces of the via lands has ten-point average roughness smaller than ten-point average roughness of the mat surfaces of the through-hole lands and outermost conductor layers. 1. A printed wiring board , comprising:a core substrate;a first build-up layer formed on a first surface side of the core substrate; anda second build-up layer formed on a second surface side of the core substrate on an opposite side with respect to the first surface side,{'b': 1', '1', '2', '1', '2', '2', '1', '2', '1', '2, 'wherein the core substrate includes a core layer having a plurality of through holes, a plurality of through-hole conductors formed in the plurality of through holes respectively such that each of the through holes has a first opening tapering from a first surface of the core layer toward a second surface of the core layer on an opposite side with respect to the first surface, and a second opening tapering from the second surface of the core layer toward the first surface of the core layer, a plurality of first through-hole lands formed on the first surface of the core layer such that the first through-hole lands are directly connected to the through-hole conductors respectively, ...

CERAMIC WIRING BOARD AND METHOD FOR PRODUCING THE SAME

A ceramic wiring board that includes a ceramic insulator and a via-conductor. The ceramic insulator includes a crystalline constituent and an amorphous constituent. The via-conductor includes a metal and an oxide. The crystalline constituent and the oxide include at least one metal element in common. A tubular region having a thickness of 5 μm adjoins and surrounds the via-conductor and has a higher concentration of the metal element than the ceramic insulator. 1. A ceramic wiring board comprising:a ceramic insulator including a crystalline constituent and an amorphous constituent;a via-conductor formed in the ceramic insulator, the via-conductor including a metal and an oxide the crystalline constituent and the oxide including a metal element in common; anda tubular region adjoining and surrounding the via-conductor, the tubular region having a concentration of the metal element higher than that of the ceramic insulator.2. The ceramic wiring board according to claim 1 , wherein the tubular region has a thickness of 5 μm.4. The ceramic wiring board according to claim 1 , wherein the tubular region includes a crystalline constituent including the metal element.5. The ceramic wiring board according to claim 4 , wherein the metal element is Ti.6. The ceramic wiring board according to claim 5 , wherein the crystalline constituent including the metal element includes a fresnoite compound including Ba claim 5 , Ti claim 5 , and Si.7. The ceramic wiring board according to claim 4 , wherein the metal element is Al.8. The ceramic wiring board according to claim 7 , wherein the crystalline constituent including the metal element includes a celsian compound including Ba claim 7 , Al claim 7 , and Si.9. The ceramic wiring board according to claim 1 , wherein the via-conductor has a diameter of 100 μm or less.10. The ceramic wiring board according to claim 1 , wherein the via-conductor is exposed at a surface of the ceramic wiring board.11. A method for producing a ceramic ...

METHODS OF MAKING STACKABLE WIRING BOARD HAVING ELECTRONIC COMPONENT IN DIELECTRIC RECESS

A method of making a stackable wiring board is characterized by positioning an electronic component in a dielectric recess to realize the thickness reduction of the wiring board and sidewalls of the recess can confine the dislocation of the electronic component to avoid misalignment between buildup circuitry and the electronic component. A plurality of plated through holes are formed to provide vertical electrical connections between dual buildup circuitries, thereby providing the wiring board with stacking capability. 1. A method of making a stackable wiring board , comprising:providing a metal carrier having substantially parallel first and second surfaces in opposite first and second directions, respectively;forming a protruded metal platform from the first surface of the metal carrier;forming a dielectric base covering the protruded metal platform and the remaining first surface of the metal carrier, wherein the dielectric base has a first surface apart from the metal carrier and substantially parallel to the first and second surfaces of the metal carrier and an opposite second surface adjacent to the metal carrier;forming a recess in the dielectric base by removing the protruded metal platform and a corresponding portion of the metal carrier, wherein the recess has a floor that is substantially parallel to the first surface of the dielectric base and a periphery defining interior sidewalls that extend from the floor to the second surface of the dielectric base;attaching an electronic component in the recess of the dielectric base by an adhesive, wherein the electronic component protrudes out from the recess and the sidewalls of the recess confine the dislocation of the electronic component laterally;forming a first buildup circuitry over the first surface of the dielectric base from the first direction and a second buildup circuitry over the electronic component from the second direction, wherein one of the first and second buildup circuitries is electrically ...

ZERO-MISALIGNMENT VIA-PAD STRUCTURES

A photoresist is deposited on a seed layer on a substrate. A first region of the photoresist is removed to expose a first portion of the seed layer to form a via-pad structure. A first conductive layer is deposited onto the first portion of the seed layer. A second region of the photoresist adjacent to the first region is removed to expose a second portion of the seed layer to form a line. A second conductive layer is deposited onto the first conductive layer and the second portion of the seed layer. 1. An apparatus , comprisinga via-pad structure over a substrate; anda conductive line adjacent to the via-pad structure over a second portion of a substrate, wherein the via-pad structure comprises: a lower portion of a first conductive layer that represents a pad portion, and a first portion of a second conductive layer on an upper portion of the first conductive layer that represents a via portion, wherein a size of the pad portion and the size of the via portion are substantially similar.2. The apparatus of claim 1 , wherein the via portion comprises a sidewall extending in a direction of the conductive line.3. The apparatus of claim 1 , wherein the conductive line comprises a second portion of the second conductive layer over the second portion of the substrate.4. The apparatus of claim 1 , wherein the via-pad structure is over a first portion of a seed layer on the substrate claim 1 , wherein the seed layer is deposited between at least one of the first conductive layer and the second conductive layer and the substrate.5. The apparatus of claim 1 , wherein at least one of the first conductive layer and the second conductive layer comprises copper.6. An apparatus claim 1 , comprising:a via-pad structure comprising: a first conductive layer on substrate, wherein a lower portion of the first conductive layer represents a pad portion; and a first portion of a second conductive layer on an upper portion of the first conductive layer represents a via portion; anda ...

HERMETICALLY SEALED THROUGH VIAS (TVS)

Hermetically sealed through vias (TVs) are disclosed. In one aspect, an hourglass TV is first created in a substrate. The hourglass TV has a waist opening. A conductive conformal coating covers at least a portion of an interior wall of the hourglass TV. The conductive conformal coating also completely fills the waist opening to provide a hermetic seal between an upper opening and a lower opening of the hourglass TV, thus creating the hermetically sealed TV. The combination of the hourglass shape, which provides a narrowing waist, and using the conformal coating process, facilitates the natural accumulation of the conductive conformal coating material in and about the waist opening. Creating hermetically sealed TVs in this manner leads to lower costs, shortened process and plating times, and increased production throughput compared to conventional processes for creating the hermetically sealed TVs in substrates. 1. An apparatus comprising a substrate having at least one hourglass through via (TV) comprising:an hourglass-shaped cross section that extends between an upper opening on a top surface of the substrate and a lower opening on a bottom surface of the substrate;an upper cavity that extends between the upper opening and a waist opening, which is inside the at least one hourglass TV and between the upper opening and the lower opening;a lower cavity that extends between the lower opening and the waist opening, wherein the waist opening has a width that is less than a width of the upper opening and a width of the lower opening; anda conductive conformal coating that covers at least a portion of an interior wall of the at least one hourglass TV and fills the waist opening to provide a hermetic seal between the upper opening and the lower opening.2. The apparatus of wherein the upper cavity and the lower cavity are conical-shaped cavities.3. The apparatus of wherein the width of the upper opening is greater than the width of the lower opening.4. The apparatus of ...

PRINTED WIRING BOARD AND METHOD FOR MANUFACTURING PRINTED WIRING BOARD

A printed wiring board includes a conductor layer including a conductor circuit, a resin insulating layer formed on the conductor layer and having a via opening reaching to the conductor circuit of the conductor layer, and a via conductor formed in the via opening of the resin insulating layer such that the via conductor is connecting to the conductor circuit of the conductor layer. The conductor circuit of the conductor layer has a first conductor portion and a second conductor portion integrally formed such that the first conductor portion is connected to the via opening of the resin insulating layer, that the second conductor portion is surrounding the first conductor portion and that the first conductor portion has a thickness which is greater than a thickness of the second conductor portion. 1. A printed wiring board , comprising:a conductor layer including a conductor circuit;a resin insulating layer formed on the conductor layer and having a via opening reaching to the conductor circuit of the conductor layer; anda via conductor formed in the via opening of the resin insulating layer such that the via conductor is connecting to the conductor circuit of the conductor layer,wherein the conductor circuit of the conductor layer comprises a first conductor portion and a second conductor portion integrally formed such that the first conductor portion is connected to the via opening of the resin insulating layer, that the second conductor portion is surrounding the first conductor portion and that the first conductor portion has a thickness which is greater than a thickness of the second conductor portion.2. A printed wiring board according to claim 1 , further comprising:a first conductor layer;a first resin insulating layer formed on the first conductor layer such that the conductor layer is a second conductor layer formed on the first resin insulating layer and that the resin insulating layer is a second resin insulating layer; anda first via conductor formed ...

ELECTRICAL INTERCONNECT FORMED THROUGH BUILDUP PROCESS

This disclosure relates generally to an electronic chip package that can include a die and a buildup layer substantially enveloping the die. Electrical interconnects can be electrically coupled to the die and passing, at least in part, through the buildup layer. An optical emitter can be electrically coupled to the die with a first one of the electrical interconnects and configured to emit light from a first major surface of the electronic chip package. A solder bump can be electrically coupled to the die with a second one of the electrical interconnects and positioned on a second major surface of the electronic chip package different from the first major surface. 1. An electronic package , comprising:a die at least partially embedded in an insulator;a first electrically conductive layer embedded in the first insulator layer of the insulator;a second electrically conductive layer embedded in a second insulator layer of the insulator; anda metal layer embedded in a third insulator layer of the insulator and having a side substantially orthogonal to the first electrically conductive layer and the second electrically conductive layer, the metal layer electrically coupling the first electrically conductive layer to the second electrically conducive layer.2. The electronic package of claim 1 , wherein the first electrically conductive layer claim 1 , the second electrically conductive layer claim 1 , and the metal layer form a via claim 1 , wherein the via has a substantially non-circular profile.3. The electronic package of claim 2 , wherein the via has a substantially regular profile.4. The electronic package of claim wherein the via has a substantially irregular regular profile.5. An electronic package assembly claim 2 , comprising:an electrically conductive layer embedded in a first insulator layer;a masking layer formed with respect to a first electrically conductive layer, the masking layer forming a cavity;a metal layer formed within the cavity, at least a portion ...

REFLECTED SIGNAL ABSORPTION IN INTERCONNECT

Embodiments of the present disclosure are directed toward techniques and configurations for electrical signal absorption in an interconnect stub. In one instance, a printed circuit board (PCB) assembly may comprise a substrate and an interconnect (such as a via) formed in the substrate to route an electrical signal within the PCB. The interconnect may include a stub formed on the interconnect. At least a portion of the stub may be covered with an absorbing material to at least partially absorb a portion of the electric signal that is reflected by the stub. The absorbing material may be selected such that its dielectric loss tangent is greater than one, for a frequency range of a frequency of the reflected portion of the electric signal. A dielectric constant of the absorbing material may be inversely proportionate to the frequency of the reflected electric signal. Other embodiments may be described and/or claimed. 1. A printed circuit board (PCB) assembly comprising:a substrate; andat least one interconnect formed in the substrate to form an electrically conductive line to route an electrical signal within the PCB, wherein the interconnect includes a stub formed on the interconnect, wherein the stub forms an electric path that extends away from the electrically conductive line, wherein the electric signal includes a desired transmission signal portion to travel via the electrically conductive line and a stub signal portion to travel through the stub, to form a reflected noise signal in response to a reflection by an end of the stub,wherein at least a portion of the end of the stub is covered with an absorbing material to at least partially absorb the portion of the electric signal that is reflected by the end of the stub, wherein the absorbing material has a dielectric loss tangent that is greater than a determined value, and remains substantially constant, for a frequency range of a frequency of the reflected portion of the electric signal that is to be at least ...

Manufacturing method of package substrate with metal on conductive portions

A manufacturing method of a package substrate includes forming a patterned first dielectric layer on a carrier; forming a first wiring layer on a first surface of the first dielectric layer facing away from the carrier, a wall surface facing one of the openings of the first dielectric layer, and the carrier in one of the openings; forming a first conductive pillar layer on the first wiring layer on the first surface; forming a second dielectric layer on the first surface, the first wiring layer, and the openings, wherein the first conductive pillar layer is exposed from the second dielectric layer; forming a second wiring layer on the exposed first conductive pillar layer and the second dielectric layer; forming an electrical pad layer on the second wiring layer; and forming a third dielectric layer on the second dielectric layer and the second wiring layer.

Zero-misalignment via-pad structures

A photoresist is deposited on a seed layer on a substrate. A first region of the photoresist is removed to expose a first portion of the seed layer to form a via-pad structure. A first conductive layer is deposited onto the first portion of the seed layer. A second region of the photoresist adjacent to the first region is removed to expose a second portion of the seed layer to form a line. A second conductive layer is deposited onto the first conductive layer and the second portion of the seed layer.

CIRCUIT BOARD AND METHOD FOR MANUFACTURING THE SAME

A circuit board with a heat-recovery function includes a substrate, a heat-storing device, and a thermoelectric device. The heat-storing device is embedded in the substrate and connected to a processor for performing heat exchange with the processor. The thermoelectric device embedded in the substrate includes a first metal-junction surface and a second metal-junction surface. The first metal-junction surface is connected to the heat-storing device for performing heat exchange with the heat-storing device. The second metal-junction surface is joined with the first metal-junction surface, in which the thermoelectric device generates an electric potential by a temperature difference between the first metal-junction surface and the second metal-junction surface. 14-. (canceled)5. A circuit board with a heat-recovery function , comprising:a substrate having a top surface and a bottom surface which are opposite to each other;a heat-storing device embedded in the substrate and connected to a processor for performing heat exchange with the processor; and a first metal-junction surface connected to the heat-storing device for performing heat exchange with the heat-storing device; and', 'a second metal-junction surface joined with the first metal-junction surface, wherein the thermoelectric device generates an electric potential by a temperature difference between the first metal-junction surface and the second metal-junction surface, wherein the substrate further comprises:', 'a first recess disposed at the top surface of the substrate, wherein the thermoelectric device is located in the first recess;', 'a second recess disposed at the bottom surface of the substrate, wherein the heat-storing device is located in the second recess, the first recess and the second recess are opposite to each other, and at least one portion of the substrate is located between the heat-storing device and the thermoelectric device;', 'at least one first via disposed at the portion of the ...

MULTILAYER WIRING SUBSTRATE AND PRODUCTION METHOD THEREFOR

To improve the degree of freedom of design of a multilayer wiring substrate incorporating therein an electronic component. A multilayer wiring substrate includes a first layered structure including conductor layers and insulation layers including therein via conductors each having a diameter which decreases from the upper surface of the insulation layer toward the lower surface thereof; an electronic component embedded in the first layered structure; and a second layered structure stacked on the first layered structure, and including conductor layers, and an insulation layer including therein a via conductor having a diameter which decreases from the upper surface of the insulation layer toward the lower surface thereof. 1. A multilayer wiring substrate comprising a plurality of insulation layers and a plurality of conductor layers , the insulation layers and the conductor layers being alternately stacked , and a via conductor formed in each insulation layer for electrically connecting conductor layers formed on upper and lower surfaces of the insulation layer , the multilayer wiring substrate being characterized by comprising:a first layered structure including a plurality of conductor layers, and a plurality of insulation layers each including therein a via conductor having a diameter which decreases from the upper surface of the insulation layer toward the lower surface thereof;an electronic component embedded in the first layered structure; anda second layered structure stacked on the first layered structure, and including at least one conductor layer, and at least one insulation layer including therein a via conductor having a diameter which decreases from the upper surface of the insulation layer toward the lower surface thereof.2. A multilayer wiring substrate according to claim 1 , wherein the first layered structure includes a metal layer which is formed below the electronic component so as to be in contact with a lower portion of the electronic component.3 ...

FLEXIBLE SUBSTRATE AND METHOD FOR FABRICATING THE SAME

A flexible substrate is provided, including a coreless substrate body having a flexible section, and an additional element formed on the substrate body and having a through hole exposing the flexible section, thereby reducing the overall thickness of the flexible substrate and meeting the thinning requirement 1. A flexible substrate , comprising:a coreless substrate body having at least a dielectric layer as a soft portion, wherein a flexible section is defined by the dielectric layer, and the dielectric layer is made of a molding compound or a primer; andan additional element as a rigid portion formed on the coreless substrate body with a through hole exposing the flexible section, wherein the through hole and the flexible section form a cavity.2. The flexible substrate of claim 1 , wherein the coreless substrate body further has a circuit structure bonded to the dielectric layer.3. The flexible substrate of claim 1 , wherein the additional element further has a conductive post embedded in an insulating layer.4. The flexible substrate of claim 3 , wherein the insulating layer is made of a dielectric material.5. The flexible substrate of claim 4 , wherein the dielectric material is a molding compound or a primer.6. The flexible substrate of claim 1 , wherein the additional element is a metal sheet.7. A method for fabricating a flexible substrate claim 1 , comprising:providing a coreless substrate body having a flexible section and at least a dielectric layer;forming an additional element on the coreless substrate body, wherein the additional element has an insulating layer, a conductive post embedded in the insulating layer, and a block penetrating the additional element; andremoving the block to form in the additional element a through hole exposing the flexible section, wherein the through hole and the flexible section form a cavity.8. The method of claim 7 , wherein the dielectric layer is made of a molding compound or a primer.9. The method of claim 7 , wherein ...

LANDLESS MULTILAYER CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF

A landless multilayer circuit board includes a first substrate, a first circuit, at least one connecting pillar, a second substrate, and a second circuit. The second substrate is on the surface of the first substrate, covering the first circuit, and exposing at least one top of the at least one connecting pillar exposed out of a surface of the second substrate, wherein an area of a portion of the at least one connecting pillar that is exposed out of the surface of the second substrate is greater than an area of a portion of the at least one connecting pillar that is connected to the first circuit. The second circuit is on the surface of the second substrate and the at least one connecting pillar, and connected to the portion of the at least one connecting pillar that is exposed out of the surface of the second substrate. 1. A landless multilayer circuit board , comprising:a first substrate;a first circuit mounted on a surface of the first substrate;at least one connecting pillar mounted on a top surface of the first circuit and connected to the first circuit;a second substrate mounted on the surface of the first substrate, covering the first circuit, and exposing at least one top of the at least one connecting pillar exposed out of a surface of the second substrate; wherein an area of a portion of the at least one connecting pillar that is exposed out of the surface of the second substrate is greater than an area of a portion of the at least one connecting pillar that is connected to the first circuit;a second circuit mounted on the surface of the second substrate and the at least one connecting pillar, and connected to the portion of the at least one connecting pillar that is exposed out of the surface of the second substrate.2. The landless multilayer circuit board as claimed in claim 1 , wherein an area of the first circuit connected to the first substrate is greater than an area of at least one bottom surface of the at least one connecting pillar connected to ...

CONDUCTOR COMPOSITION INK, LAMINATED WIRING MEMBER, SEMICONDUCTOR ELEMENT AND ELECTRONIC DEVICE, AND METHOD FOR PRODUCING LAMINATED WIRING MEMBER

A conductor of the invention is in a form of a conductive convex portion in a laminated wiring member and includes a conductive material and a liquid repellent, in which the conductive material is in a form of metal particles, the liquid repellent is a fluorine-containing compound adapted to form a self-assembled monomolecular film. The conductor has a surface energy in a range from more than 30 mN/m to 80 mN/m. The conductor of the invention is exemplified by the conductive convex portion in the laminated wiring member and functions as a VIA post in the laminated wiring member. 1. A laminated wiring member comprising:a wiring member comprising a base material and a first electrode formed on the base material;a conductor in a form of a conductive convex portion comprising a conductive material and a liquid repellent, the conductive convex portion being in electrical continuity with the first electrode, functioning as a VIA post, and having a surface energy from more than 30 mN/m to 80 mN/m, wherein the conductive material is in a form of metal particles, and the liquid repellent is a fluorine-containing compound adapted to form a self-assembled monomolecular film;an insulation layer formed of a resin composition and in which the conductive convex portion is present; anda second electrode in electrical continuity with the conductive convex portion and formed on the insulation layer, whereina height of the conductive convex portion is larger than a thickness of the insulation layer, andat least a part of the conductive convex portion projecting from the insulation layer is in electrical continuity with the second electrode.2. The laminated wiring member according to claim 1 , whereinthe fluorine-containing compound is a fluorine-containing thiol compound.3. The laminated wiring member according to claim 1 , whereinthe conductive material and the liquid repellent are exposed on a surface of the conductor.4. The laminated wiring member according to claim 1 , whereinthe ...

Substrates with Ultra Fine Pitch Flip Chip Bumps

A method of attaching a chip to the substrate with an outer layer comprising via pillars embedded in a dielectric such as solder mask, with ends of the via pillars flush with said dielectric, the method comprising the steps of: (o) optionally removing organic varnish, (p) positioning a chip having legs terminated with solder bumps in contact with exposed ends of the via pillars, and (q) applying heat to melt the solder bumps and to wet the ends of the vias with solder. 1. A method of terminating a side of a multilayer composite structure having an outer layer of via posts embedded in a dielectric , comprising the steps of:(i) thinning away the outer layer to expose the copper vias;(ii) sputtering a layer of copper over the thinned surface;(iii) applying, exposing and developing a penultimate pattern of photoresist;(iv) electroplating an external feature layer into the pattern;(v) stripping away the penultimate pattern of photoresist;(vi) applying, exposing and developing an ultimate pattern of photoresist corresponding to the desired pattern of micro bumps;(vii) pattern plating copper via posts into the ultimate pattern of photoresist;(viii) pattern plating solderable metal over the copper via posts;(ix) stripping away the ultimate pattern of photoresist;(x) etching away the seed layer;(xi) laminating a dielectric outer layer;(xiv) plasma etching the dielectric outer layer to expose the solderable cap of the via post, and(xv) applying a finishing treatment of the solderable cap.2. The method of wherein the dielectric outer layer is selected from the group consisting of a film dielectric and a dry film solder mask.3. The method of where step (xv) comprises applying pressure to the solder cap along axis of the via post resulting in a flat coined solderable cap.4. The method of where step (xv) comprises applying pressure along axis of the via post together with heat to cause reflow under pressure claim 1 , resulting in a flat coined solderable cap.5. The method of ...

FLAT-WIRE COPPER VERTICAL LAUNCH MICROWAVE INTERCONNECTION METHOD

A circuit structure includes a signal substrate having a signal trace formed thereon and a microstrip substrate disposed above the signal substrate that includes a microstrip trace formed thereon and a hole passing through it. The circuit structure also includes a conductor passing through and substantially filling the hole passing through the microstrip substrate and electrically contacting the signal trace on the signal substrate and a flat wire connector electrically connecting the microstrip trace to a first end of the conductor, the flat wire connector being arranged such that a gap is formed between the flat wire connector and a top surface of the microstrip substrate. 1. A circuit structure , comprising:a signal substrate having a signal trace formed thereon;a microstrip substrate disposed above the signal substrate that includes a microstrip trace formed thereon and a hole passing through it;a conductor passing through and substantially filling the hole passing through the microstrip substrate and electrically contacting the signal trace on the signal substrate; anda flat wire connector electrically connecting the microstrip trace to a first end of the conductor, the flat wire connector being arranged such that a gap is formed between the flat wire connector and a top surface of the microstrip substrate.2. The circuit board of claim 1 , wherein the flat wire connector is soldered to the microstrip trace and a top of the conductor.3. The circuit structure of claim 1 , wherein the conductor is a solid wire.4. The circuit structure of claim 1 , wherein a second end of the conductor is soldered to signal trace.5. The circuit of claim 1 , wherein a top of the conductor extend above the top surface of the microstrip substrate.6. The circuit structure of claim 1 , further including an intermediate substrate located between the signal substrate and the microstrip substrate that includes a hole formed therein and that aligns with the hole passing through the ...

MANUFACTURING METHOD OF DOUBLE LAYER CIRCUIT BOARD

A manufacturing method of a double layer circuit board comprises forming a connecting pillar on a first circuit, wherein the connecting pillar comprises a first end, connected to the first circuit, and a second end, opposite to the first end; forming a substrate on the first circuit and the connecting pillar; drilling the substrate to expose a portion of the second end of the connecting pillar, wherein the other portion of the second end of the connecting pillar is covered by the substrate; and forming a second circuit on the substrate and the portion of the second end of the connecting pillar, wherein an area of the first end connected to the first circuit layer is greater than an area of the portion of the second end connected to the second circuit layer. 1. A manufacturing method of a double layer circuit board comprising:forming a connecting pillar on a first circuit layer, wherein the connecting pillar comprises a first end, connected to the first circuit layer, and a second end, opposite to the first end;forming a substrate on the first circuit layer and the connecting pillar;drilling the substrate to expose a portion of the second end of the connecting pillar, wherein the other portion of the second end of the connecting pillar is covered by the substrate; andforming a second circuit layer on the substrate and the portion of the second end of the connecting pillar, wherein an terminal area of the first end connected to the first circuit layer is greater than an terminal area of the portion of the second end connected to the second circuit layer.2. The manufacturing method of a double layer circuit board as claimed in claim 1 , wherein the first circuit layer includes a first circuit claim 1 , and the second circuit layer includes a second circuit;wherein the substrate comprises a first surface and a second surface, the first surface is opposite to the second surface, and the first circuit is on the first surface of the substrate.3. The manufacturing method of ...

Printed circuit board for memory module, method of manufacturing the same and memory module/socket assembly

Example embodiments of the present invention may include a printed circuit board, a method of manufacturing the printed circuit board, and a memory module/socket assembly. Example embodiments of the present invention may increase the number of contact taps on a memory module, in addition, a force required to insert the memory module into a module socket may be decreased.

Large area multi-electrode radiation detector substrate

A process for making an electrical interconnect comprising the steps of adhering a flexible electrical circuit to the surface of a substrate, building conductive posts on said flexible electrical circuit, putting a curable dielectric composition around said posts, and curing said composition.

Methods of planarizing structures on wafers and substrates by polishing

Methods of planarizing structures formed on the surfaces of substrates and wafers are disclosed. The methods form a planarizing layer over the surface and the structures, or the locations where the structures are to be formed, such that the top surface of the layer has low areas between the locations of the structures, and such that the low areas lie substantially within a plane which is below the tops of the structures. A polish-stop layer is then formed over the low areas of the planarizing layer, the polish-stop layer being more resistant to polishing than the planarizing layer and, preferably, the structures. The resulting surface is then polished. The polishing may be accomplished by, for example, standard mechanical polishing, and chemical-mechanical polishing.

Methods of planarizing structures on wafers and substrates by polishing

Methods of planarizing structures formed on the surfaces of substrates and wafers are disclosed. The methods form a planarizing layer over the surface and the structures, or the locations where the structures are to be formed, such that the top surface of the layer has low areas between the locations of the structures, and such that the low areas lie substantially within a plane which is below the tops of the structures. A polish-stop layer is thee formed over the low areas of the planarizing layer, the polish-stop layer being more resistant to polishing than the planarizing layer and, preferably, the structures. The resulting surface is then polished. The polishing may be accomplished by, for example, standard mechanical polishing, and chemical-mechanical polishing.

Multi-layer fabrication in integrated circuit systems

A method for fabricating layers permits the accurate removal of surface material in a multi-layer multi-chip carrier. An intermediate layer of solid vias is deposited over a circuit layer attached to a substrate. The layer can be filled with a dielectric material. The substrate is attached to a substrate holder such that the intermediate layer is exposed, and the substrate holder is placed onto a rotating platen polisher with the intermediate layer facing the platen surface. Tooling presses the intermediate layer against the rotating polishing platen, allowing the substrate holder and substrate to rotate with three degrees of angular freedom, letting the substrate and intermediate layer self-align to the polishing platen in order to uniformly remove material from the intermediate layer surface. A second circuit layer can be formed on the resulting structure. The foregoing steps can be iterated to build a multi-layer structure of circuit layers separated by uniformly thick dielectric and via layers. As an alternative method, substrate attached to a substrate holder is placed against the platen surface of a shaking polisher, allowing the substrate and substrate holder to self-align to the polishing platen. In a third embodiment, where metal irregularities exist along the intermediate layer surface, wiping the surface evenly with cloth soaked in an appropriate etchant can uniformly remove the unwanted metal irregularities.

Methods of planarizing structures on wafers and substrates by polishing

Methods of planarizing structures formed on the surfaces of substrates and wafers are disclosed. The methods form a planarizing layer over the surface and the structures, or the locations where the structures are to be formed, such that the top surface of the layer has low areas between the locations of the structures, and such that the low areas lie substantially within a plane which is below the tops of the structures. A polish-stop layer is thee formed over the low areas of the planarizing layer, the polish-stop layer being more resistant to polishing than the planarizing layer and, preferably, the structures. The resulting surface is then polished. The polishing may be accomplished by, for example, standard mechanical polishing, and chemical-mechanical polishing.

A printed circuit board and a fabricating method the same

본 발명은 인쇄회로기판 및 그 제조방법에 관한 것으로, 절연층, 상기 절연층과 동일한 표면 높이를 가진 상태로 상기 절연층에 함침된 접속패드를 가지며, 상기 절연층에 함침된 회로층, 및 상기 접속패드를 노출시키는 오픈부를 가지며, 상기 회로층을 외부로부터 보호하도록 상기 절연층에 함침된 절연재를 포함하는 것을 특징으로 하며, 박판화가 가능하고, 기판의 신뢰성 및 설계자유도를 증대시킬 수 있는 인쇄회로기판 및 그 제조방법을 제공한다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board and a method of manufacturing the same. A printed circuit having an open portion for exposing a connection pad and including an insulating material impregnated in the insulating layer to protect the circuit layer from the outside, which can be thinned and can increase the reliability and design freedom of the substrate. Provided are a substrate and a method of manufacturing the same. 함침, 절연재, 감광성, 기판, 반경화, 가압 Impregnation, insulation, photosensitive, substrate, semi-hardened, pressurized

Making method of Printed circuit board

본 발명은 인쇄회로기판의 제조방법에 관한 것이다. 본 발명은 상대적으로 내부에 구비되고 양측 표면에 제1회로패턴(12)이 형성된 제1절연층(10) 상에 상기 제1회로패턴(12)을 덮도록 상기 제1절연층(10)의 표면에 제2절연층(20)과 금속층(22')을 차례로 적층하는 단계와, 상기 금속층(22')과 제2절연층(20)을 선택적으로 제거하여 상기 제1회로패턴(12)이 선택적으로 노출되게 블라인드홀(25)을 형성하는 단계와, 상기 금속층(22')의 표면에 도금마스크(40)를 설치하여 블라인드홀(25)의 내부에만 도금이 수행되도록 하여 상기 제1회로패턴(12)과 상기 금속층(22')을 전기적으로 연결하는 접속돌기(50)를 형성하는 단계와, 상기 금속층(22')을 선택적으로 제거하여 제2회로패턴(22)을 형성하는 단계를 포함하여 구성된다. 본 발명에서는 보다 미세한 회로패턴을 형성함과 동시에 서로 다른 층에 있는 회로패턴의 전기적 연결을 위한 구성이 차지하는 공간이 줄어들어 인쇄회로기판을 소형화할 수 있고, 특히 기존의 설비와 재료를 이용하면서도 회로패턴을 미세하게 형성할 수 있어 상대적으로 인쇄회로기판의 제조원가가 낮아지며, 도금을 이용하여 층 사이의 회로패턴을 연결하므로 인쇄회로기판의 품질이 좋아진다. The present invention relates to a method of manufacturing a printed circuit board. According to an exemplary embodiment of the present invention, the first insulating layer 10 may be disposed to cover the first circuit pattern 12 on the first insulating layer 10 provided therein and having the first circuit pattern 12 formed on both surfaces thereof. Sequentially stacking the second insulating layer 20 and the metal layer 22 'on the surface, and selectively removing the metal layer 22' and the second insulating layer 20 to form the first circuit pattern 12. Forming a blind hole 25 to be selectively exposed, and installing a plating mask 40 on the surface of the metal layer 22 'so that plating is performed only inside the blind hole 25 so as to perform the first circuit pattern. And forming a connection protrusion 50 electrically connecting the metal layer 22 'and the metal layer 22' to form the second circuit pattern 22 by selectively removing the metal layer 22 '. It is configured by. In the present invention, a smaller circuit pattern can be formed and the space occupied by the configuration for the electrical connection of the circuit patterns on different layers can be reduced, thereby miniaturizing the printed circuit board, and in particular, using the existing equipment and materials. Since it is ...

Making method of printed circuit board

본 발명은 인쇄회로기판의 제조방법에 관한 것이다. 본 발명은 코어층(20)의 양측 표면에 패턴(22)을 형성하고 이들 사이를 통공(24)을 통해 전기적으로 연결하는 단계와, 상기 패턴(22)을 포함하는 코어층(20) 표면 전체를 덮도록 감광성 재질로 된 표면보호층(26)을 도포하는 단계와, 상기 코어층(20)의 양면에서 동시에 상기 표면보호층(26)의 표면에 압력을 가해 표면보호층(26)을 평탄하게 만드는 단계와, 상기 표면보호층(26)에 광을 선택적으로 조사하고 표면보호층(26)을 선택적으로 제거하여 외부와의 연결을 위한 패드(34)를 형성하는 단계를 포함하여 구성된다. 이와 같은 구성을 가지는 본 발명에 의한 인쇄회로기판의 제조방법에 의하면 상대적으로 간단한 방법으로 인쇄회로기판의 표면 편평도를 높일 수 있고, 특히 두께가 얇은 인쇄회로기판의 표면 편평도를 높일 수 있어 경박단소화된 제품의 외관을 보다 깔끔하게 할 수 있는 이점이 있다. The present invention relates to a method of manufacturing a printed circuit board. The present invention is to form a pattern 22 on both surfaces of the core layer 20 and to electrically connect them through the through-holes 24, the entire surface of the core layer 20 including the pattern 22 Applying a surface protective layer 26 of photosensitive material to cover the surface of the core layer; and applying pressure to the surface of the surface protective layer 26 simultaneously on both surfaces of the core layer 20 to flatten the surface protective layer 26. And selectively irradiating the surface protection layer 26 with light and selectively removing the surface protection layer 26 to form a pad 34 for connection with the outside. According to the method of manufacturing a printed circuit board according to the present invention having such a configuration, the surface flatness of the printed circuit board can be increased by a relatively simple method, and in particular, the surface flatness of the thin printed circuit board can be increased, thereby reducing the thickness There is an advantage that can make the appearance of the finished product more neat. 인쇄회로기판, 표면평탄도, 박형 인쇄회로기판 Printed Circuit Board, Surface Flatness, Thin Printed Circuit Board

Method For Forming Printed Wiring Board and Printed Wiring Board Thus Obtained

절연층의 반경화와 완전경화의 2단계 프로세스에 의해 절연층과 도전패턴의 접착력을 개선할 수 있는 배선기판의 제조방법이 제공된다. 본 발명의 배선기판 제조방법은, 절연기재상에 배선패턴을 따라 도전패턴과 절연패턴을 적어도 1층 이상 형성하는 방법으로, There is provided a method of manufacturing a wiring board capable of improving the adhesion between an insulating layer and a conductive pattern by a two-step process of semi-curing and completely curing the insulating layer. A wiring board manufacturing method of the present invention is a method of forming at least one conductive pattern and an insulating pattern on an insulating substrate along a wiring pattern, 상기 절연기재와 절연패턴의 적어도 하나는 반경화 상태에서 그 상부에 상기 도전패턴을 형성하여 적층체를 얻고, 이 적층체를 열처리하여 상기 반경화상태의 절연기재 또는/및 절연패턴의 적어도 하나는 완전경화하면서 도전패턴은 소성하는 것을 포함하여 이루어진다. Wherein at least one of the insulating substrate and the insulating pattern is formed in a semi-cured state to form the conductive pattern thereon, thereby obtaining a laminate, and the laminate is subjected to heat treatment so that at least one of the insulating substrate and / And the conductive pattern is baked while fully curing. 본 발명은 반경화상태의 절연층에 도전패턴이 인쇄되면 친숙성이 더 좋아지고, 또한, 반경화 절연층과 그 상부에 인쇄된 도전패턴을 동시에 열처리하면 반경화 절연층이 완전 경화되는 과정에서 도전패턴은 소성되기 때문에 밀착성이 개선되는 것이다. 본 발명에서 반경화는 자외선(UV)조사에 의해 행하는 것이 바람직하다. When the conductive pattern is printed on the semi-cured insulating layer, the familiarity is improved. When the semi-cured insulating layer and the conductive pattern printed on the semi-cured insulating layer are heat-treated at the same time, Since the pattern is baked, the adhesion is improved. In the present invention, the semi-curing is preferably carried out by ultraviolet (UV) irradiation. 반경화, 다층기판, 잉크젯 방식, 절연층, 도전층 Semi-curing, multi-layer substrate, inkjet method, insulating layer, conductive layer

Via formation for multilayer inductive devices and other devices

A method of creating a multilayer ceramic component of the present invention is used to spontaneously create vias between adjacent conductor layers in a multilayer inductive component. After a first conductive layer is printed, a via dot is printed on the first conductive layer. Next, a controlled thickness of ceramic slurry is cast over the previous ceramic layer, first conductive pattern, and the via dot. The physical/chemical forces between the via dot and the ceramic slurry expel the slurry in the proximity of the top surface of the via dot. When the ceramic slurry dries, the ceramic cast leaves vias filled with conductors from the preprinted via dots. This process is repeated until a desired number of conductive layers are formed.

Method of manufacturing multilayer wiring boards

하층의 배선층 위에 주형 금속체을 형성하는 단계를 가지며, 또한 주형 금속체에 전기적으로 연결된 일부 상층의 배선층을 형성한 후, 하층의 배선층에 도금 단계의 일부 주형체와 일부 주형 금속체로 구성된 금속이 에칭 되는 경우 도전층 주형 금속체로 구성되는 금속 도금층의 형성, 도전층을 포함하는 표면의 개구, 주형 금속체로부터 도금층의 외면의 개구 상에 마스크 층, 및 도금층의 에칭을 하는 특징이 있는 다층 배선기판의 제조방법이고, 이 방법은 간이하고 저렴하며, 또한 짧은 시간에 일정하게 높은 주형 금속체을 형성하는 능력이 있다. Forming a mold metal body on the lower wiring layer, and forming a part of the upper wiring layer electrically connected to the mold metal body, and then etching the metal composed of some of the mold body and some mold metal body of the plating step on the lower wiring layer. Manufacture of a multilayer wiring board characterized by forming a metal plating layer composed of a conductive layer mold metal body, an opening on a surface including the conductive layer, a mask layer on the opening of the outer surface of the plating layer from the mold metal body, and etching of the plating layer. It is a method, which is simple and inexpensive, and also has the ability to form a constantly high mold metal body in a short time.

Bump forming method and manufacturing method for printed circuit board using the same

본 발명은 범프에 의해 층간을 도통시키고 이를 이용한 전층연결 일괄적층하여 다층인쇄회로기판을 제조하는 방법에 관한 것이다. 보다 구체적으로, 본 발명은 회로층에 도금에 의해 범프를 형성하고 프레스 공정에 의해 가압하여 범프에 의해 인쇄회로기판의 층간을 도통시킴으로써 공정수를 줄이고, 생산성 및 시간을 단축할 수 있는 다층 인쇄회로기판 제조 방법에 관한 것이다. The present invention relates to a method of manufacturing a multi-layer printed circuit board by conducting the layers by bumps and stacking all layers using the same. More specifically, in the present invention, a multilayer printed circuit capable of reducing the number of processes, productivity and time by forming bumps on a circuit layer by plating and pressurizing by a press process to conduct interlayers of a printed circuit board by bumps. It relates to a substrate manufacturing method. 도금, 범프, 인쇄회로기판, 도금 레지스트, 일괄적층 Plating, Bump, Printed Circuit Board, Plating Resist, Batch Lamination

Multilayer wiring board and method of producing the same

본 발명은 코어 기판과 코어 기판의 양면에 형성된 배선 패턴을 갖고, 코어 기판은 코어 기판을 관통하는 도전성 부재를 갖고, 코어 기판의 양면의 배선 패턴 부재는 코어 기판을 관통하는 도전성 부재를 통해 서로 접속되는 다층 배선판에 있어서, 코어 기판은 비어 칼럼과, 도금으로 형성된 도전성 구조 부재 및 비어 칼럼과 도전 구조 부재를 전기적으로 서로 절연시키는 절연 구조 부재를 갖고, 비어 칼럼은 코어 기판을 관통하여 코어 기판의 양면의 배선 패턴 부재를 서로 접속하는 도전성 부재로서 기능하는 다층 배선판에 관한 것이다. 이와 같은 다층 배선판을 제조하는 방법도 개시된다. The present invention has a wiring pattern formed on both sides of the core substrate and the core substrate, the core substrate has a conductive member penetrating the core substrate, the wiring pattern members on both sides of the core substrate are connected to each other through the conductive member penetrating the core substrate In the multilayer wiring board, the core substrate has a via column, a conductive structural member formed by plating, and an insulating structural member that electrically insulates the via column and the conductive structural member from each other. The multilayer wiring board which functions as an electroconductive member which connects wiring pattern members of each other is related. Also disclosed is a method of manufacturing such a multilayer wiring board. 다층 배선판, 비어 칼럼 Multilayer Wiring Board, Beer Column

印刷电路板及其制造方法

提供一种印刷电路板结构及其制造方法。该制造方法包括在第一电路图案上形成连接凸点并且形成第一绝缘层，从而形成内层电路板的第一步骤；使用模具对其上形成有金属籽晶层的第二绝缘层进行处理以形成第二电路图案，从而构造外层电路板的第二步骤；以及将内层电路板和外层电路板彼此对准，并层压内层电路板和外层电路板的第三步骤。因此，可以提供具有嵌入于绝缘层中的电路的高密度高可靠度的印刷电路板结构。通过使用与籽晶层结合的绝缘层，可以去除用于形成最外层电路的籽晶层形成过程。此外，形成连接凸点形式的导电结构，从而不需要形成过孔以及利用导电材料填充过孔的复杂过程。此外，去除研磨所填充的导电材料的表面的过程，从而显著地降低电路出错率。

Inspecting method, inspection treating system, treating device, inspecting device, manufacturing/inspecting device, and manufacturing/inspecting method

반송(搬送) 라인 상을 흐르는 복수개의 시트에 대하여 소정의 처리를 소정 횟수(N회) 행하는 경우에 있어서, 많은 시간 연장되는 일 없이, N회의 처리가 모두 종료되기 전에, 도중의 처리(n회째의 처리)에 대한 검사 결과를 파악할 수 있는 검사 방법 등을 제공하는 것을 목적으로 한다. In the case where predetermined processing is performed a predetermined number of times (N times) for a plurality of sheets flowing on a conveying line, before the N times of processing are all terminated, And a test method capable of grasping the test result of the test result of the test result. 소정의 처리가 행해진 대상물을 검사하는 검사 방법으로서, 복수개의 상기 대상물을 반송 라인 상에 반송하면서 각 상기 대상물에 대하여 차례로 상기 소정의 처리를 N회(N은 2이상의 자연수) 반복하여 행하는 처리 공정과, 상기 복수개의 대상물 중, n회째(n은 N 이하의 1이상의 자연수)의 처리가 종료된 선두의 상기 대상물에 대하여 검사를 행하고, 검사 후의 상기 대상물을 상기 복수개의 대상물 중 상기 n회째의 처리가 종료된 대상물의 뒤로 되돌리는 검사 공정을 포함하는 것을 특징으로 한다. There is provided an inspection method for inspecting an object on which a predetermined process has been performed, comprising the steps of: a) carrying out a plurality of the objects on a transfer line while repeating the predetermined process N times (N is a natural number of 2 or more) (N is a natural number equal to or smaller than N) among the plurality of objects, and the n-th processing among the plurality of objects And returning to the back of the finished object. 반송 라인, 대상물, 검사 공정, 검사 방법, 검사 처리 시스템, 처리 장치, 검사 장치, 제조/검사 장치 및 제조/검사 방법 Transfer line, object, inspection process, inspection method, inspection processing system, processing apparatus, inspection apparatus, manufacturing / inspection apparatus, and manufacturing / inspection method

Printed circuit board and method of mamufacturing the same

본 발명은 인쇄회로기판 및 인쇄회로기판에 관한 것이다. 본 발명의 실시 예에 따르면 베이스 기판, 베이스 기판에 형성되며, 제1 내층 회로층, 제2 내층 회로층, 내층 절연층 및 테이퍼(Taper) 형태의 단면을 갖는 내층 비아를 포함하는 내층 빌드업층, 및 내층 빌드업층에 형성되며, 외층 회로층, 외층 절연층 및 직사각형 형태의 단면을 갖는 외층 비아를 포함하는 외층 빌드업층을 포함하는 인쇄회로기판이 제공된다. The present invention relates to a printed circuit board and a printed circuit board. According to an embodiment of the present invention, an inner layer buildup layer formed on a base substrate and a base substrate and including inner layer vias having a first inner layer circuit layer, a second inner layer circuit layer, an inner layer insulating layer, and a taper- And an outer layer build-up layer formed on the inner-layer build-up layer and including outer-layer circuit layers, outer-layer insulating layers, and outer-layer vias having rectangular cross sections.

Inspecting method, inspection treating system, treating device, inspecting device, manufacturing/inspecting device, and manufacturing/inspecting method

반송(搬送) 라인 상을 흐르는 복수개의 시트에 대하여 소정의 처리를 소정 횟수(N회) 행하는 경우에 있어서, 많은 시간 연장되는 일 없이, N회의 처리가 모두 종료되기 전에, 도중의 처리(n회째의 처리)에 대한 검사 결과를 파악할 수 있는 검사 방법 등을 제공하는 것을 목적으로 한다. 소정의 처리가 행해진 대상물을 검사하는 검사 방법으로서, 복수개의 상기 대상물을 반송 라인 상에 반송하면서 각 상기 대상물에 대하여 차례로 상기 소정의 처리를 N회(N은 2이상의 자연수) 반복하여 행하는 처리 공정과, 상기 복수개의 대상물 중, n회째(n은 N 이하의 1이상의 자연수)의 처리가 종료된 선두의 상기 대상물에 대하여 검사를 행하고, 검사 후의 상기 대상물을 상기 복수개의 대상물 중 상기 n회째의 처리가 종료된 대상물의 뒤로 되돌리는 검사 공정을 포함하는 것을 특징으로 한다. In the case where predetermined processing is performed a predetermined number of times (N times) for a plurality of sheets flowing on a conveying line, before the N times of processing are all terminated, And a test method capable of grasping the test result of the test result of the test result. There is provided an inspection method for inspecting an object on which a predetermined process has been performed, comprising the steps of: a) carrying out a plurality of the objects on a transfer line while repeating the predetermined process N times (N is a natural number of 2 or more) (N is a natural number equal to or smaller than N) among the plurality of objects, and the n-th processing among the plurality of objects And returning to the back of the finished object.

Circuit device and manufacturing method thereof

방열성이 향상된 구조의 다층 배선을 구비하는 회로 장치 및 그 제조 방법을 제공한다. 본 발명의 회로 장치(10)는, 제1 절연층(17A)을 개재하여 적층된 제1 배선층(18A) 및 제2 배선층(18B)을 갖는다. 제1 배선층(18A)과 제2 배선층(18B)은, 제1 절연층(17A)을 관통하여 형성된 접속부(25)에 의해 원하는 개소에서 접속되어 있다. 접속부(25)는, 제1 배선층(18A)으로부터 두께 방향으로 돌출되는 제1 접속부(25A)와, 제2 배선층(18B)으로부터 두께 방향으로 돌출되는 제2 접속부(25B)로 이루어진다. 그리고, 제1 접속부(25A)와 제2 접속부(25B)는, 제1 절연층(17A)의 두께 방향에서, 그 중간부에서 컨택트하고 있다. Provided are a circuit device having a multilayer wiring structure having improved heat dissipation and a method of manufacturing the same. The circuit device 10 of the present invention has the first wiring layer 18A and the second wiring layer 18B stacked through the first insulating layer 17A. The first wiring layer 18A and the second wiring layer 18B are connected at desired locations by the connecting portion 25 formed through the first insulating layer 17A. The connection part 25 consists of the 1st connection part 25A which protrudes in the thickness direction from the 1st wiring layer 18A, and the 2nd connection part 25B which protrudes in the thickness direction from the 2nd wiring layer 18B. And the 1st connection part 25A and the 2nd connection part 25B are contacting in the intermediate part in the thickness direction of the 1st insulating layer 17A. 회로 장치, 접속부, 배선층, 절연층 Circuit device, connection part, wiring layer, insulation layer

Contact assembly

FIELD: non-split joints for microelectronic and semiconductor devices. SUBSTANCE: contact assembly has at least two metal-coated contacts coupled with current-carrying tracks placed on switching-layer surfaces on insulating substrate, joined together, and interconnected electrically and mechanically by means of electricity conducting binder. Contact assembly is, essentially, joint between metal-coated contact pad coupled with current-carrying tracks on surface of lower switching layer and mating contact made in the form of metal-coated hole in insulating layer. EFFECT: enlarged functional capabilities of contact assembly. 23 cl, 6 dwg зб с ПЧ ГЭ РОССИЙСКОЕ АГЕНТСТВО ПО ПАТЕНТАМ И ТОВАРНЫМ ЗНАКАМ (19) (51) МПК ВИ” 2134 498 13) СЛ Н 05 К 1/41, 3/36, 3/42, 13/04, Н 01 В 4/00, 9/09 12) ОПИСАНИЕ ИЗОБРЕТЕНИЯ К ПАТЕНТУ РОССИЙСКОЙ ФЕДЕРАЦИИ (21), (22) Заявка: 98121773109, 08.12.1998 (24) Дата начала действия патента: 08.12.1998 (46) Дата публикации: 10.08.1999 (56) Ссылки: Моряков О.С. Технология полупроводниковых приборов и изделий микроэлектроники. - М.: Высшая школа, 1990, с.38-40. ОЕ 4040226 05, 17.06.92. ЕР 0493103 А2, 01.07.92. ЗЦ 1739529 АЛ, 07.06.92. $ 1757138 АЛ, 23.08.92. (98) Адрес для переписки: 117333, Москва, Ленинский пр-т, 60/2-160, Таран А.И. (71) Заявитель: Таран Александр Иванович (72) Изобретатель: Таран А.И. (73) Патентообладатель: Таран Александр Иванович (54) КОНТАКТНЫЙ УЗЕЛ (57) Реферат: Изобретение относится к изготовлению неразъемных соединений в процессе производства аппаратуры на основе изделий микроэлектроники и — полупроводниковых приборов, а конкретно - к контактным узлам, посредством которых осуществляется сборка, в том числе многослойных коммутационных структур для многокристальных модулей (МКМ)а также монтаж кристаллов БИС на коммутационной структуре в процессе изготовления МКМ. Контактный узел содержит по крайней мере два металлизированных контакта, связанных с токоведущими дорожками, размещенными на поверхностях коммутационных слоев, ...

Wiring Board, Wiring Board Manufacturing Apparatus, and Wiring Board Manufacturing Method

가시상을 기판에 전사하는 전자 사진 방식에 의해 형성된 배선 기판이며, 배선 기판이 가시상이 전사되는 기판과, 상기 기판 상에 선택적으로 형성되어 금속 미립자를 분산하여 함유한 비도전성의 금속 함유 수지층과, 상기 금속 함유 수지층 상에 형성된 도전성의 도전 금속층과, 상기 기판 상의 금속 함유 수지층 사이에 형성된 수지층을 구비한다. A wiring board formed by an electrophotographic method of transferring a visible image to a substrate, the wiring board being a substrate on which the visible image is transferred, a non-conductive metal-containing resin layer selectively formed on the substrate to disperse and contain metal fine particles; And a conductive conductive metal layer formed on the metal-containing resin layer and a resin layer formed between the metal-containing resin layer on the substrate. 배선 기판, 베이스, 금속 함유 수지층, 도체 금속층, 수지층 Wiring board, base, metal-containing resin layer, conductor metal layer, resin layer

电路板的制作方法

一种电路板的制作方法，包括步骤：提供第一基板和第二基板，所述第一基板具有第一导电线路层，所述第一导电线路层具有暴露区及环绕暴露区的贴合区，所述第二基板具有与所述暴露区相对应的去除区及环绕所述去除区的保留区；在所述第一基板形成环绕所述暴露区的第一环形凸起，在所述第二基板上形成环绕去除区的第二环形凸起，所述第二环形凸起与第一环形凸起相对应；提供一个粘合片，所述粘合片具有开口；将所述粘合片压合于第一导电线路层的贴合区和第二基板的保留区之间，使第一导电线路层的暴露区和第二基板的去除区均暴露于所述开口，并使第一环形凸起与第二环形凸起相抵靠；以及去除所述第二基板的去除区，暴露出所述第一基板的暴露区。

접촉노드

본 발명은 마이크로전자공학 부품 및 반도체 디바이스에 기초한 장비의 제조시 영구적인 연결부를 제조하는 것에 관한 것으로, 특히 마이크로칩 모듈(MCM)의 제조시 LSIC 칩의 장착공정이 수행될 뿐만 아니라 MCM을 위한 다층 연결플레이트의 조립공정을 위한 접촉 노드에 관한 것이다. 상기 접촉노드는 유전체 재질의 베이스위에 형성되고 상호 정렬되며 도전성 바인딩재에 의해 전기적 및 기계적으로 상호연결된 연결층 표면상에 배치된 도전성 경로에 연결된 적어도 두개의 메탈라이즈 접촉부를 포함한다. 상기 접촉노드는 연결층 표면상의 도전성 경로에 연결된 메탈라이즈 접촉패드 형태로 형성된 접촉부와, 상기 패드와 접합되고 상부 연결층의 메탈라이즈 홀 형태로 형성된 각각의 접촉부 사이의 접합부 형태로 형성되며, 상기 메탈라이즈 홀의 하측 엣지부는 하부 연결층 표면상의 메탈라이즈 접촉패드를 향해 있고, 상기 메탈라이즈 홀의 상측 엣지부는 상부 연결층의 상측면위 도전층 경로에 연결된다.

Core substrate and multiplayer printed circuit board using paste bump and method of manufacturing thereof

페이스트 범프를 이용한 코어기판 및 그 제조방법이 개시된다. (a) 표면에 복수의 페이스트 범프가 결합된 한 쌍의 페이스트 범프기판을 페이스트 범프가 서로 대향하도록 정렬하는 단계, (b) 한 쌍의 페이스트 범프기판을 서로 압착하는 단계를 포함하되, 한 쌍의 페이스트 범프기판 사이에는 절연재가 개재되는 페이스트 범프를 이용한 코어기판 제조방법은, 회로패턴의 층간 전기적 연결(interconnection)이 용이하고, 절연층의 두께를 조절함으로써 코어기판의 두께를 용이하게 조절할 수 있으며, 한 쌍의 페이스트 범프 기판을 상하에서 압착하므로 강성(stiffness)이 향상되고, 한 쌍의 페이스트 범프를 연결하기 때문에 페이스트 범프 기판에 형성되는 페이스트 범프의 직경을 축소할 수 있어 고밀도 회로패턴을 용이하게 형성할 수 있다. Disclosed are a core substrate using a paste bump and a method of manufacturing the same. (a) arranging a pair of paste bump substrates having a plurality of paste bumps bonded to a surface thereof so that the paste bumps face each other, and (b) pressing the pair of paste bump substrates against each other, In the core substrate manufacturing method using the paste bumps in which the insulating material is interposed between the paste bump substrates, the electrical interconnection of the circuit patterns is easy, and the thickness of the core substrate can be easily adjusted by adjusting the thickness of the insulating layer. By squeezing a pair of paste bump substrates up and down, the stiffness is improved, and the pair of paste bumps are connected to reduce the diameter of the paste bumps formed on the paste bump substrate, thereby easily forming a high density circuit pattern. can do. 페이스트 범프, 코어기판 Paste Bump, Core Board

Method for forming wiring pattern, wiring pattern, and electronic apparatus

본 발명은 도통 포스트의 형성에 적합한 배선 패턴의 형성 방법을 제공하는 것을 과제로 한다. An object of this invention is to provide the formation method of the wiring pattern suitable for formation of a conductive post. 복수의 노즐(91)을 갖는 토출 헤드(20)와 기판(31)을 소정 방향(Y방향)으로 상대 이동시키면서, 복수의 노즐(91) 중 소정 노즐로부터 액적을 토출하여 복수의 도통 포스트(34)를 형성한다. 소정 방향(Y방향)과 직교하는 방향(X방향)에 관하여, 복수 노즐(91)의 간격을 a, 복수의 도통 포스트(34)의 간격을 b라고 할 때, b=m×a(m은 양의 정수)를 만족시키는 조건을 설정한다. While relatively moving the discharge head 20 and the board | substrate 31 which have the some nozzle 91 in the predetermined direction (Y direction), droplets are discharged from the predetermined nozzle among the some nozzle 91, and the some conductive post 34 is carried out. ). When a distance between the plurality of nozzles 91 is a and a distance between the plurality of conductive posts 34 is b with respect to a direction (X direction) orthogonal to a predetermined direction (Y direction), b = m × a (m is Positive integer). 배선 패턴, 도통 포스트, 액적 토출, 전자 기기 Wiring pattern, conductive post, droplet ejection, electronic equipment

다중 층 구조 형성 방법

본 발명은 기판에 전기에칭 또는 전기도금을 행함에 의해서 다중 층을 형성하는 방법을 제공한다. 시드 층은 기판에 배열되고 마스터 전극이 도포된다. 마스터 전극은 기판과 다중 전기화학적 셀을 형성하는 패턴 층을 갖는다. 전압은 시드 층을 에칭하거나 시드 층에 도금 재료를 도포하기 위해 인가된다. 유전체 재료(9)는 형성된 구조(8) 사이에 배열된다. 유전체 층은 구조의 아래를 노출하기 위해 평탄화되고 다른 구조 층은 제 1부 상부에 형성된다. 대안적으로, 유전체 층은 2개의 층의 두께로 도포되고 아래의 구조는 아래 구조의 상부 표면을 선택적으로 노출시키기 위해서 유전체 층의 선택적 에칭에 의해 접근된다. 다중 구조 층은 하나의 단계에서 또한 형성될 수 있다. 전기에칭, 시드 층, 에칭, 도금, 마스터 전극, 스퍼터링, 증착

具有超细间距倒装芯片凸点的基板

一种将芯片连接至具有外层的基板上的方法，所述外层包括嵌入在如焊料掩膜的电介质中的通孔柱，其中通孔柱的端部与所述电介质齐平，该方法包括以下步骤：(o)任选地移除有机涂层；(p)将具有端接焊料凸点的引脚的芯片定位为与通孔柱暴露端接触；和(q)加热并熔融焊料凸点并使焊料润湿通孔端部。

Wiring board, semiconductor device and manufacturing method thereof

Electrochemically molded and hermetically sealed microstructure and method and apparatus for producing the microstructure

In some embodiments, multilayer structures are electrochemically fabricated from at least one structural material (e.g. nickel), at least one sacrificial material (e.g. copper), and at least one sealing material (e.g. solder). In some embodiments, the layered structure is made to have a desired configuration which is at least partially and immediately surrounded by sacrificial material which is in turn surrounded almost entirely by structural material. The surrounding structural material includes openings in the surface through which etchant can attack and remove trapped sacrificial material found within. Sealing material is located near the openings. After removal of the sacrificial material, the box is evacuated or filled with a desired gas or liquid. Thereafter, the sealing material is made to flow, seal the openings, and resolidify. In other embodiments, a post-layer formation lid or other enclosure completing structure is added.

用于制造绝缘层和多层印刷电路板的方法

本发明涉及用于制造绝缘层的方法，其可以以更快且更简单的方式制造，可以改善工艺效率，可以防止对绝缘层的物理损坏，并且可以容易地调节层厚度；以及使用由所述制造绝缘层的方法获得的绝缘层来制造多层印刷电路板的方法。

Manufacturing method of wiring board or wiring board material

High density printed circuit board and method of manufacturing the same

본 발명은 고밀도 인쇄회로기판 제조 방법에 관한 것이다. 보다 구체적으로, 본 발명은 인쇄회로기판 제조 공정 중에는 물리적 강도를 유지하기 위해 필요하지만 최종 제품에서는 배선의 길이 증가로 고주파 적용 패캐지 제품에서의 전기적 특성 저하를 가져온다. 이에 코어 절연층을 제거함으로써 보다 배선 길이가 짧고,기판두께가 얇은 인쇄회로기판을 제조할 수 있는 방법에 관한 것이다. The present invention relates to a method for manufacturing a high density printed circuit board. More specifically, the present invention is required to maintain physical strength during the manufacturing process of the printed circuit board, but in the final product, the increase in the length of the wiring leads to a decrease in electrical characteristics in the high frequency packaged product. Accordingly, the present invention relates to a method for manufacturing a printed circuit board having a shorter wiring length and a thinner substrate thickness by removing the core insulating layer. 코어 절연층, 패터닝 가능한 폴리머, 인쇄회로기판 Core Insulation, Patterned Polymer, Printed Circuit Board

Method of forming wiring pattern, wiring pattern and electronic equipment

본 발명은 도통(導通) 포스트를 상당 높이에 형성하면서, 다층화 및 미세화를 실현시키는 것이 가능한 배선 패턴의 형성 방법을 제공한다. The present invention provides a method of forming a wiring pattern which can realize multilayering and miniaturization while forming a conductive post at a considerable height. 적층 배치된 복수의 전기 배선(32, 36)이 도통 포스트(34)에 의해 서로 도통 접속되어 이루어지는 배선 패턴의 형성 방법으로서, 전기 배선(32)의 형성 재료를 포함하는 제 1 액적을 토출하여 전기 배선(32)을 형성하는 공정과, 도통 포스트(34)의 형성 재료를 포함하는 제 2 액적을 토출하여 도통 포스트(34)를 형성하는 공정을 갖고, 제 2 액적의 체적이 상기 제 1 액적의 체적보다 큰 것을 특징으로 한다. A method of forming a wiring pattern in which a plurality of stacked electrical wires 32 and 36 are electrically connected to each other by a conductive post 34, wherein a first droplet containing a forming material of the electrical wire 32 is discharged to generate electricity. A process of forming the wiring 32 and a process of ejecting the second droplet containing the material for forming the conductive post 34 to form the conductive post 34, wherein the volume of the second droplet It is characterized by being larger than the volume. 전기 배선, 도통 포스트, 배선 패턴, 액적 토출 장치 Electrical wiring, conductive posts, wiring patterns, droplet ejection devices

Insulating layer for multilayered printed circuit board

본 발명은 미세패턴을 용이하게 형성할 수 있고 기계적 물성이 우수한 다층인쇄회로기판용 절연층을 제공한다.

Multilayer wiring board, method for producing multilayer wiring board, polisher for multilayer wiring board, and metal sheet for producing wiring board

범프형성용 금속층(2)/에칭스톱층(3)/배선형성용 금속층(4)으로 이루어지는 다층금속판(1)의 배선막형성용 금속층으로 배선막(4a)을 형성하여, 범프형성용 금속층으로 범프(2a)를 형성한 것을 복수 준비하여, 1개의 다층금속판의 범프의 형성면에 별도의 다층금속판의 배선막을 포갠다고 하는 형태로 반복하는 적층공정을 순차 반복하여 다층화를 한다. 또한, 금속판(1a)을 유지하는 금속판유지수단(13)과, 금속판의 위쪽에 칼날(26)을 유지하는 칼날유지수단(25)과, 해당 칼날유지수단의 높이를 조정하는 높이조정기구(20)와, 해당 칼날유지수단을 금속판의 표면에 대하여 상대적으로 평행하게 이동시키는 칼날평행이동기구(15)를 갖는 다층배선기판용 연마기(11a)로 연마한다. The wiring film 4a is formed of the wiring film forming metal layer of the multilayer metal plate 1, which is formed of the bump forming metal layer 2, the etching stop layer 3, and the wiring forming metal layer 4, thereby forming the bump forming metal layer. A plurality of bumps 2a are prepared, and a lamination process is repeated in a manner of laminating a wiring film of another multi-layer metal plate on the forming surface of the bump of one multi-layer metal plate to sequentially multilayer. In addition, the metal plate holding means 13 for holding the metal plate 1a, the blade holding means 25 for holding the blade 26 above the metal plate, and the height adjusting mechanism 20 for adjusting the height of the blade holding means. ), And the blade holding means is polished with a multi-layer wiring board polishing machine 11a having a blade parallel moving mechanism 15 for moving the blade holding means relatively parallel to the surface of the metal plate.

Multi-layer type coreless substrate and Method of manufacturing the same

본 발명에 따른 적층형 코어리스 인쇄회로기판의 제조 방법은 (A) 절연판의 일면 또는 양면에 적어도 하나의 동박을 구비한 캐리어 기판을 준비하는 단계, (B) 상기 캐리어 기판의 일면 또는 양면에 코어리스 인쇄회로기판 전구체를 형성하는 단계, (C) 상기 캐리어 기판을 분리하는 단계, (D) 상기 코어리스 인쇄회로기판 전구체에 대해 평탄화 공정을 수행하는 단계, 및 (E) 상기 코어리스 인쇄회로기판 전구체의 평탄한 외부면에 대해 다른 회로층과 다른 필라를 순차적으로 포함한 다른 절연층을 다수 적층하는 단계를 포함한다.

Manufacturing method for printed circuit board

A method for manufacturing a printed circuit board is provided to form a minute pattern with high reliability and to improve productivity. A first circuit pattern(306) is formed on a metal layer of a conductive carrier(300) in which the metal layer(302) is laminated on one side. The conductive carrier and a first insulation layer(310) are compressed so that the first circuit pattern faces the first insulation layer. A via(312) is formed by selectively removing the conductive carrier. The conductive carrier is etched by coating an etching solution corresponding to the conductive carrier on the conductive carrier and forming an etching resist corresponding to the position of the via. The metal layer is removed.

Clad board for printed-circuit board, multilayered printed-circuit board, and method for mfg. same

提供一种制造多层印刷电路板和低成本包层板的方法。将用于形成导体层(10、17、18)的铜箔层(19、24、33)和用于形成蚀刻停止层(11、12)的镍镀层(20、21)交替层叠并压紧，形成用于印刷电路板的包层板(34)。有选择性地蚀刻用于印刷电路板的包层板(34)以制造基板。在该基板表面上形成外导体层(15、16)并制作图形。导体层(10、15、16)通过由蚀刻铜箔层(19、24、33)和镍镀层(20、21)而形成的柱状导体(17、18)实现电连接，制成多层印刷电路板。

How to embed conductive elements in a dielectric layer

인쇄회로기판을 구성하는 층들의 제조 과정 중 일부로서 형성되는 내장형 도전성 엘리먼트를 포함하는 다층 인쇄회로기판을 제조하는 방법이 제공된다. 그리고 나서, 절연층 및 도전층은 상기 도전성 엘리먼트 위로 프레싱되어, 상기 도전성 엘리먼트들은 상기 도전층의 표면으로부터 돌출된다. 상기 돌출부들을 제거하여 상기 내장된 도전성 엘리먼트들을 노출하기 위해 기계적인 공정이 추가된다. 도전성 언더코트가 상기 도전층의 표면에 부가되고, 상기 도전성 언더코트 위에 제2 회로 패턴이 형성된다. A method of manufacturing a multilayer printed circuit board including an embedded conductive element formed as part of the manufacturing process of the layers constituting the printed circuit board is provided. Then, the insulating layer and the conductive layer are pressed onto the conductive element so that the conductive elements protrude from the surface of the conductive layer. A mechanical process is added to remove the protrusions to expose the embedded conductive elements. A conductive undercoat is added to the surface of the conductive layer, and a second circuit pattern is formed on the conductive undercoat. 인쇄회로기판, 프레싱, 도전성 엘리먼트, 언더코트, 절연층 Printed Circuit Board, Pressing, Conductive Element, Undercoat, Insulation Layer

Method for manufacturing electronic device, method for manufacturing electronic device

Chip embedded printed circuit board and manufacturing method thereof

본 발명은 칩 내장 인쇄회로기판 및 그 제조방법에 관한 것으로서, 복수의 제1 패드가 상면에 구비된 제1 칩이 내장되고, 양면에 제1 회로패턴이 구비된 제1 코어기판; 상기 제1 코어기판의 하부에 이격 배치되며, 복수의 제2 패드가 하면에 구비된 제2 칩이 내장되고, 양면에 제2 회로패턴이 구비된 제2 코어기판; 상기 제1 코어기판의 상부에 적층되고, 상기 제1 회로패턴 및 상기 제1 패드와 접속되는 복수의 제1 도전성 범프가 관통 형성된 제1 절연층; 상기 제1 코어기판 및 상기 제2 코어기판의 사이에 적층되어, 상기 제1 회로패턴과 상기 제2 회로패턴을 서로 접속시키는 복수의 제2 도전성 범프가 관통 형성된 제2 절연층; 및 상기 제2 코어기판의 하부에 적층되고, 상기 제2 회로패턴 및 상기 제2 패드에 접속되는 복수의 제3 도전성 범프가 관통 형성된 제3 절연층;을 포함하는 칩 내장 인쇄회로기판을 제공하고, 또한 본 발명은 상기 칩 내장 인쇄회로기판의 제조방법을 제공한다. The present invention relates to a chip-embedded printed circuit board and a method of manufacturing the same, comprising: a first core substrate having a plurality of first pads provided thereon and having a first chip pattern on both surfaces thereof; A second core substrate spaced apart from the first core substrate, a second chip having a plurality of second pads disposed on a lower surface thereof, and having a second circuit pattern on both surfaces thereof; A first insulating layer stacked on the first core substrate and having a plurality of first conductive bumps penetrating through the first circuit pattern and the first pad; A second insulating layer stacked between the first core substrate and the second core substrate and having a plurality of second conductive bumps penetrating the first circuit pattern and the second circuit pattern therebetween; And a third insulating layer laminated under the second core substrate and having a plurality of third conductive bumps penetrated through the second circuit pattern and the second pad. In addition, the present invention provides a method for manufacturing the chip embedded printed circuit board. 내장(embedded), 인쇄회로기판, 도전성 범프, 적층 Embedded, Printed Circuit Board, Conductive Bump, Laminated

Circuit device and manufacturing method thereof

방열성이 향상된 구조의 다층 배선을 구비하는 회로 장치 및 그 제조 방법을 제공한다. 본 발명의 회로 장치(10)는, 제1 절연층(17A)을 개재하여 적층된 제1 배선층(18A) 및 제2 배선층(18B)을 갖는다. 제1 배선층(18A)과 제2 배선층(18B)은, 제1 절연층(17A)을 관통하여 형성된 접속부(25)에 의해 원하는 개소에서 접속되어 있다. 접속부(25)는, 제1 배선층(18A)으로부터 두께 방향으로 돌출되는 제1 접속부(25A)와, 제2 배선층(18B)으로부터 두께 방향으로 돌출되는 제2 접속부(25B)로 이루어진다. 그리고, 제1 접속부(25A)와 제2 접속부(25B)는, 제1 절연층(17A)의 두께 방향에서, 그 중간부에서 컨택트하고 있다. 회로 장치, 접속부, 배선층, 절연층

Printed circuit board And Method for fabricating the same

본 발명은 인쇄회로기판의 제조방법에 관련되며, 포스트 비아가 형성된 제1 절연층의 외면에 보강기재가 포함된 제2 절연층을 적층하는 단계, 상기 포스트 비아의 상측이 노출되도록 상기 제2 절연층의 상면을 연마하는 단계, 상기 포스트 비아를 커버하며 상기 제2 절연층이 압착되도록 상기 제2 절연층 상에 필름부재를 적층하는 단계, 상기 포스트 비아의 상측이 노출되도록 상기 필름부재의 상면을 연마하는 단계, 및 상기 필름부재의 상면에 상기 포스트 비아와 연결된 회로층을 형성하는 단계를 포함한다. The present invention relates to a method for manufacturing a printed circuit board, comprising: laminating a second insulating layer including a reinforcing base material on an outer surface of a first insulating layer on which post vias are formed; Polishing the upper surface of the layer, laminating a film member on the second insulating layer to cover the post via and compress the second insulating layer, and to expose the upper surface of the post via to expose the upper surface of the post via. Polishing, and forming a circuit layer connected to the post via on the upper surface of the film member.

METHOD FOR INTEGRATING ELECTRIC CONDUCTING ELEMENTS IN A LAYER DIELECTRIC

ÐÎÑÑÈÉÑÊÀß ÔÅÄÅÐÀÖÈß (19) RU (11) 2007 105 901 (13) A (51) ÌÏÊ H01L 21/48 (2006.01) ÔÅÄÅÐÀËÜÍÀß ÑËÓÆÁÀ ÏÎ ÈÍÒÅËËÅÊÒÓÀËÜÍÎÉ ÑÎÁÑÒÂÅÍÍÎÑÒÈ, ÏÀÒÅÍÒÀÌ È ÒÎÂÀÐÍÛÌ ÇÍÀÊÀÌ (12) ÇÀßÂÊÀ ÍÀ ÈÇÎÁÐÅÒÅÍÈÅ (21), (22) Çà âêà: 2007105901/28, 12.02.2007 (71) Çà âèòåëü(è): Ñàíìèíà-ÝñÑèÀé Êîðïîðåéøí (US) (30) Êîíâåíöèîííûé ïðèîðèòåò: 13.02.2006 US 11/353,725 (43) Äàòà ïóáëèêàöèè çà âêè: 20.08.2008 Áþë. ¹ 23 A 2 0 0 7 1 0 5 9 0 1 R U Ñòðàíèöà: 1 RU A (57) Ôîðìóëà èçîáðåòåíè 1. Ñïîñîá ñîçäàíè ýëåêòðîïðîâîä ùåãî ýëåìåíòà â ìíîãîñëîéíîé ïå÷àòíîé ïëàòå, âêëþ÷àþùèé: ñîçäàíèå ïåðâîé ïîäëîæêè, èìåþùåé ïåðâóþ ïîâåðõíîñòü, ôîðìèðîâàíèå ïåðâîãî ïðîâîä ùåãî ðèñóíêà ñõåìû íà ïåðâîé ïîâåðõíîñòè ïåðâîé ïîäëîæêè, ôîðìèðîâàíèå ïåðâîãî ýëåêòðîïðîâîä ùåãî ýëåìåíòà íà ïåðâîé ïîâåðõíîñòè, ôîðìèðîâàíèå ïåðâîãî èçîëèðóþùåãî ñëî è ïåðâîãî ïðîâîä ùåãî ñëî ïîâåðõ ïåðâîé ïîâåðõíîñòè ïåðâîé ïîäëîæêè, ïåðâîãî ïðîâîä ùåãî ðèñóíêà ñõåìû è ïåðâîãî ýëåêòðîïðîâîä ùåãî ýëåìåíòà, ïðè ýòîì ïåðâûé èçîëèðóþùèé ñëîé ðàñïîëîæåí ñìåæíî ñ ïåðâîé ïîâåðõíîñòüþ, óäàëåíèå ó÷àñòêà ïåðâîãî èçîëèðóþùåãî ñëî è ó÷àñòêà ïåðâîãî ïðîâîä ùåãî ñëî äë îáíàæåíè ïî ìåíüøåé ìåðå îäíîé ïîâåðõíîñòè ïåðâîãî ýëåêòðîïðîâîä ùåãî ýëåìåíòà, ïðè÷åì ïåðâûé ïðîâîä ùèé ñëîé è îáíàæåííûé ïåðâûé ýëåêòðîïðîâîä ùèé ýëåìåíò çàäàþò âòîðóþ ïîâåðõíîñòü, è ôîðìèðîâàíèå ïåðâîãî ýëåêòðîïðîâîä ùåãî ïðîìåæóòî÷íîãî ñëî ïîâåðõ âòîðîé ïîâåðõíîñòè. 2. Ñïîñîá ïî ï.1, â êîòîðîì ìåæäó ïåðâûì ïðîâîä ùèì ñëîåì è ïåðâûì ýëåêòðîïðîâîä ùèì ýëåìåíòîì îáåñïå÷èâàþò íåïðåðûâíîñòü ýëåêòðè÷åñêîé öåïè. 3. Ñïîñîá ïî ï.1, â êîòîðîì äîïîëíèòåëüíî ïðîñâåðëèâàþò îòâåðñòèå ÷åðåç ïåðâûé ýëåêòðîïðîâîä ùèé ýëåìåíò. 4. Ñïîñîá ïî ï.1, â êîòîðîì äîïîëíèòåëüíî ôîðìèðóþò âòîðîé ïðîâîä ùèé ðèñóíîê ñõåìû ïîâåðõ ïåðâîãî ýëåêòðîïðîâîä ùåãî ïðîìåæóòî÷íîãî ñëî è ýëåêòðè÷åñêè ïðèñîåäèí þò ïåðâûé ýëåêòðîïðîâîä ùèé ýëåìåíò ïî ìåíüøåé ìåðå ê îäíîìó ïðîâîä ùåìó ðèñóíêó ñõåìû, ïåðâîìó èëè âòîðîìó. 5. Ñïîñîá ïî ï.1, â êîòîðîì äîïîëíèòåëüíî íàíîñ ò ñëîé ôîòîðåçèñòà ïîâåðõ ïåðâîé ïîâåðõíîñòè, êîòîðûé çàäàåò ãðàíèöû ...

Method for manufacturing insulating film and multilayered printed circuit board

본 발명은, 보다 빠르면서도 간단한 방법으로 제조가 가능하여 공정의 효율성이 향상될 수 있으며, 절연층의 물리적 손상을 방지할 수 있고, 두께 조절이 용이한 절연층 제조방법 및 상기 절연층 제조방법으로부터 얻어지는 절연층을 이용한 다층인쇄회로기판 제조방법에 관한 것이다. The present invention can be manufactured in a faster and simpler method to improve the efficiency of the process, to prevent physical damage of the insulating layer, and to control the thickness of the insulating layer manufacturing method and the insulating layer manufacturing method A method for manufacturing a multilayer printed circuit board using an insulating layer obtained.

Printed circuit board and making method the same

본 발명은 인쇄회로기판 및 그 제조방법에 관한 것이다. 본 발명은 표면에 회로패턴(24)이 구비되는 적어도 하나 이상의 절연층(22)과 상기 절연층(22)을 관통하여 회로패턴(24)을 연결하는 연결범프(26)부가 구비되는 내층부(21)와; 상기 내층부(21)의 표면에 부착되는 것으로, 상기 내층부(21) 표면의 회로패턴(24)을 보호하는 표피절연층(36)을 구비하고, 상기 표피절연층(36)의 표면에는 실장되는 부품과의 전기적 연결을 위한 연결패드(32)가 구비되며, 상기 연결패드(32)는 상기 표피절연층(36)을 관통하는 외층연결범프(34)를 통해 상기 내층부(21)의 회로패턴(24)과 전기적으로 연결되는 외층부(30)를; 포함하여 구성된다. 이와 같은 구성을 가지는 본 발명에 의한 인쇄회로기판의 제조방법을 사용하면 인쇄회로기판의 크기를 소형화할 수 있고, 인쇄회로기판의 표면을 다양한 자재로 형성할 수 있어 인쇄회로기판의 품질 및 원가를 낮출 수 있는 이점이 있다. The present invention relates to a printed circuit board and a method of manufacturing the same. According to an embodiment of the present invention, an inner layer part including at least one insulating layer 22 having a circuit pattern 24 on a surface thereof and a connection bump 26 part connecting the circuit pattern 24 through the insulating layer 22 may be provided. 21); It is attached to the surface of the inner layer portion 21, and provided with a skin insulation layer 36 to protect the circuit pattern 24 on the surface of the inner layer portion 21, the surface of the skin insulation layer 36 is mounted A connection pad 32 is provided for electrical connection with a component to be formed, and the connection pad 32 is a circuit of the inner layer part 21 through an outer layer connection bump 34 passing through the skin insulation layer 36. An outer layer portion 30 electrically connected to the pattern 24; . By using the method of manufacturing a printed circuit board according to the present invention having such a configuration, the size of the printed circuit board can be miniaturized, and the surface of the printed circuit board can be formed of various materials, thereby improving the quality and cost of the printed circuit board. There is an advantage that can be lowered. 인쇄회로기판, 연결패드, 솔더레지스트, 면적 Printed circuit board, connection pad, solder resist, area

Interlayer member used for producing multi-layer wiring board and method of producing the same

本发明是关于一种多层布线基板制造用层间构件及其制造方法，可提高插入于二个布线层间并完成该布线层的层间绝缘和层间电性连接的多层布线基板制造用层间构件的尺寸精度，且谋求配置密度的提高。该制造方法藉由在片状的载体层(2)的主表面上形成掩蔽膜(4)，并在载体层(2)的该主表面上，将掩蔽膜(4)作为掩膜并电镀铜，而形成层间连接用金属柱(8)，并除去掩蔽膜(4)。接着，在载体层(2)的主表面上，将层间绝缘层(10)及保护片(12)以被层间连接用金属柱(8)贯通的形态进行叠层，且使层间绝缘层(10)及保护片(12)露出该层间连接用金属柱(8)的上面，然后除去载体层(2)，另外还除去保护片(12)。

conductive layer adhesive anisotropic concuctive sheet and wiring board using such a sheet

상하의 배선패턴 사이의 전기적 접속이 용이하고, 용이하게 제조할 수 있고, 또 두께도 얇게 할 수 있는 배선기판을 제공한다. 해결수단은 한쪽 면에 배선패턴(62)이 형성된 이방성도전시트(52)를 복수매적층하여 고착되고, 또 최하층의 이방성도전시트(52)의 다른쪽 면에서, 표면에 배선패턴(60)이 형성된 프린트배선기판(58)면에 고착되고, 상기 배선패턴(60, 62)사이가 상기 이방성도전시트(52)를 거쳐서 전기적으로 접속되어 있고, 최상층의 이방성도전시트(52)의 배선패턴(62)의 외부접속부(62a)를 노출하여 전기적 절연피막(64)이 형성되어 있는 것을 특징으로 한다. Provided is a wiring board which can be easily connected to the upper and lower wiring patterns, can be easily manufactured, and can be made thin. The solution means is obtained by laminating a plurality of anisotropic conductive sheets 52 in which wiring patterns 62 are formed on one side, and fixing them, and on the other side of the anisotropic conductive sheet 52 of the lowest layer, wiring patterns 60 are formed on the surface thereof. It is adhered to the formed printed wiring board 58 surface, and the wiring patterns 60 and 62 are electrically connected through the anisotropic conductive sheet 52, and the wiring pattern 62 of the anisotropic conductive sheet 52 of the uppermost layer is connected. It is characterized in that the electrical insulating film 64 is formed by exposing the external connection portion (62a).

Conductor composition ink, laminated wiring member, semiconductor element and electronic device, and method for producing laminated wiring member

Core substrate and multiplayer printed circuit board using paste bump and method of manufacturing thereof

本发明公开了一种使用焊膏凸块的基板和多层印刷电路板，及其制造方法。使用焊膏凸块的基板的制造方法包括：(a)对准一对焊膏凸块板，每个都具有多个连接至其表面的焊膏凸块，使得焊膏凸块彼此相对；以及(b)将该一对焊膏凸块板压合到一起，其中绝缘元件放置在该对焊膏凸块板之间，很容易在电路图案之间实现夹层电性互连，通过调整绝缘层的厚度，能够轻易地调整基板的厚度，由于一对焊膏凸块板被从顶部和底部压合，硬度也有所提高，并且由于焊膏凸块成对连接，能够更轻易地形成高密度布线，从而能够减小形成在焊膏凸块板上的焊膏凸块的直径。

Bump forming method and manufacturing method for printed circuit board using the same

본 발명은 범프에 의해 층간을 도통시키고 이를 이용한 전층연결 일괄적층하여 다층인쇄회로기판을 제조하는 방법에 관한 것이다. 보다 구체적으로, 본 발명은 회로층에 도금에 의해 범프를 형성하고 프레스 공정에 의해 가압하여 범프에 의해 인쇄회로기판의 층간을 도통시킴으로써 공정수를 줄이고, 생산성 및 시간을 단축할 수 있는 다층 인쇄회로기판 제조 방법에 관한 것이다. 도금, 범프, 인쇄회로기판, 도금 레지스트, 일괄적층

Method of producing circuit board by additive method, and circuit board and multilayer circuit board obtained by the method

다층 회로 기판 제조 방법은, 절연 기재의 표면에 팽윤성 수지 필름을 형성하는 필름-형성 단계, 상기 팽윤성 수지 필름의 외표면에 상기 팽윤성 수지 필름의 두께 이상의 깊이를 갖는 회로 홈을 형성하는 회로 홈-형성 단계, 상기 회로 홈의 표면과 상기 팽윤성 수지 필름의 표면 위에 도금 촉매 또는 그 전구체를 피착하는 촉매-피착 단계, 상기 팽윤성 수지 필름을 특정 액체로 팽윤시켜, 팽윤된 수지 필름을 상기 절연 기재 표면으로부터 박리하는 필름-박리 단계, 및 상기 팽윤성 수지 필름의 박리 후 도금 촉매 또는 그 도금 촉매의 전구체로부터 형성된 도금 촉매가 박리되지 않고 잔류하는 영역에만 무전해 도금막을 형성하는 도금 처리 단계를 포함한다. The multi-layer circuit board manufacturing method includes a film-forming step of forming a swellable resin film on a surface of an insulating substrate, and a circuit groove-forming step of forming a circuit groove having a depth greater than or equal to the thickness of the swellable resin film on an outer surface of the swellable resin film. Step, a catalyst-deposition step of depositing a plating catalyst or a precursor thereof on the surface of the circuit groove and the surface of the swellable resin film, swelling the swellable resin film with a specific liquid, peeling the swollen resin film from the surface of the insulating substrate A film-peeling step, and a plating treatment step of forming an electroless plated film only in a region in which the plating catalyst formed from the plating catalyst or the precursor of the plating catalyst remains after the peeling of the swellable resin film is not peeled off.