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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ

Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 10597. Отображено 100.
12-01-2012 дата публикации

Apparatus and method for determining dynamic voltage scaling mode, and apparatus and method for detecting pumping voltage using the same

Номер: US20120007661A1
Автор: Young Do Hur
Принадлежит: Hynix Semiconductor Inc

A mode determination apparatus in a semiconductor apparatus includes a first condition detection block configured to generate a first condition signal in response to a clock enable signal activated when the semiconductor apparatus enters a dynamic voltage scaling mode, a second condition detection block configured to generate a second condition signal in response to an external high voltage in the dynamic voltage scaling mode, the external high voltage having a voltage level in the dynamic voltage scaling mode different from a voltage level in a normal mode, and a signal processing block configured to generate a dynamic voltage scaling mode signal in response to the first condition signal and the second condition signal.

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Номер записи: 1
12-01-2012 дата публикации

Rfid access method using an indirect memory pointer

Номер: US20120007722A1
Автор: Danny Lee Secrest, Mark R. Whitaker
Принадлежит: Ramtron International Corp

A method of operating a memory in an RFID application includes locating a memory pointer at a fixed read/writeable memory location in the memory, determining a range of a pedigree buffer, initializing the memory pointer to a lowest value in the range, providing a second memory location that serves as a trigger address for an indirect write, and writing to a next location in the pedigree buffer by directing write data to the trigger address, which is then automatically written at a location pointed to by the memory pointer.

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Номер записи: 2
12-01-2012 дата публикации

Memory devices and methods having multiple address accesses in same cycle

Номер: US20120008378A1
Автор: Dinesh Maheshwari
Принадлежит: Cypress Semiconductor Corp

A memory device can include a plurality of banks, each bank including memory locations accessible by different access circuits; at least a first address port configured to receive addresses on falling and rising edges of a timing clock, each address corresponding to locations in different banks; and at least two read/write data ports configured to receive write data for storage in one of the banks, and output read data from one of the banks.

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Номер записи: 3
12-01-2012 дата публикации

Method for writing in a mram-based memory device with reduced power consumption

Номер: US20120008380A1
Автор: Mourad El Baraji, Neal Berger
Принадлежит: CROCUS TECHNOLOGY SA

A method of writing in a memory device comprising a plurality of MRAM cells, each cell including a magnetic tunnel junction having a resistance that can be varied during a write operation when heated at a high threshold temperature; a plurality of word lines connecting cells along a row; and a plurality of bit lines connecting cells along a column; the method comprising supplying a bit line voltage to one of the bit lines and a word line voltage to one of the word lines for passing a heating current through the magnetic tunnel junction of a selected cell; said word line voltage is a word line overdrive voltage being higher than the core operating voltage of the cells such that the heating current has a magnitude that is high enough for heating the magnetic tunnel junction at the predetermined high threshold temperature. The memory device can be written with low power consumption.

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Номер записи: 4
26-01-2012 дата публикации

Method and apparatus for word line decoder layout

Номер: US20120020179A1
Автор: Cheng Hung Lee, Chung-Ji Lu, Hong-Chen Cheng, Jung-Hsuan Chen, Li-Chun Tien, You-Cheng Xiao
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A word line decoder comprises a plurality of driver circuits, a plurality of word lines provided at respective outputs of the driver circuits, and a plurality of primary input lines coupled to the driver circuits and oriented in a first direction. The word line decoder also comprises a plurality of secondary input lines coupled to the driver circuits and oriented in the first direction. The word line decoder also comprises a local decode line coupled to each of the primary input lines. The word line decoder also comprises a decode line coupled to the local decode line and oriented in the first direction. A cluster decode line is coupled to the decode line. The word line decoder is configured to select at least one of the word lines based on signals provided by the cluster decode line and the secondary input lines.

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Номер записи: 5
09-02-2012 дата публикации

Semiconductor integrated device

Номер: US20120032730A1
Автор: Jun Koyama
Принадлежит: Semiconductor Energy Laboratory Co Ltd

To reduce power consumption of a semiconductor integrated circuit and to reduce delay of the operation in the semiconductor integrated circuit, a plurality of sequential circuits included in a storage circuit each include a transistor whose channel formation region is formed with an oxide semiconductor, and a capacitor whose one electrode is electrically connected to a node that is brought into a floating state when the transistor is turned off. By using an oxide semiconductor for the channel formation region of the transistor, the transistor with an extremely low off-state current (leakage current) can be realized. Thus, by turning off the transistor in a period during which power supply voltage is not supplied to the storage circuit, the potential in that period of the node to which one electrode of the capacitor is electrically connected can be kept constant or almost constant. Consequently, the above objects can be achieved.

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Номер записи: 6
09-02-2012 дата публикации

Word line driving circuit, semiconductor memory device including the same, and method for testing the semiconductor memory device

Номер: US20120033516A1
Автор: Chang-Ho Do
Принадлежит: Individual

A semiconductor memory device in accordance with the present invention is able to facilitate detecting whether a word line fails or not by floating the word line. The semiconductor memory device includes a word line driver, and a floating controller. The word line driver is configured to control a word line to be enabled/disabled. The floating controller is configured to control the word line driver to float the word line in response to a word line floating signal.

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Номер записи: 7
16-02-2012 дата публикации

Method and apparatus for word line driver with decreased gate resistance

Номер: US20120037997A1
Автор: Jung-Hsuan Chen, Shao-Yu Chou, Yen-Huei Chen, You-Cheng Xiao
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor device comprises first, second, and third. The first conductor is a gate conductor formed above an oxide region over a substrate and having a contact. The second conductor is coupled to the contact and extends across a width of the oxide region. The second conductor has a lower resistance than the gate conductor. The third conductor is a word line conductor. The second conductor is routed to not intersect the word line conductor.

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Номер записи: 8
23-02-2012 дата публикации

Sub word line driver and apparatuses having the same

Номер: US20120043616A1
Автор: Hyang Ja Yang, Jae Young Lee
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A sub word line driver is provided. The sub word line driver includes a first layer including a plurality of first pads disposed in a first line of a first direction, a plurality of second pads arranged in a second line of the first direction, and two first word lines arranged twisted twice in the first direction between the plurality of first pads and the plurality of second pads, each of the two first word lines being connected to a corresponding pad among the plurality of second pads; and a second layer, which is formed at a lower part of the first layer, and includes the second layer including a plurality of third pads, each the plurality of third pads each being embodied disposed at each corresponding a position corresponding to a pad from among one of the plurality of first pads and the plurality of second pads.

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Номер записи: 9
23-02-2012 дата публикации

Nonvolatile semiconductor memory device and driving method thereof

Номер: US20120044760A1
Автор: Keita Takahashi
Принадлежит: Panasonic Corp

A nonvolatile semiconductor memory device has a first select transistor having a gate electrode connected to a first select word line, a source connected to a first sub bit line, and a drain connected to a first main bit line, and a second select transistor having a gate electrode connected to a second select word line, a source connected to a second sub bit line, and a drain connected to a second main bit line. The first sub bit lines are controlled by the first select transistor so as to be electrically isolated from each other between memory cell groups each formed by the memory cells to be erased simultaneously. On the other hand, the second sub bit lines are connected in common to the memory cells of memory cell groups to be erased separately, by the second select transistor.

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Номер записи: 10
08-03-2012 дата публикации

Devices and system providing reduced quantity of interconnections

Номер: US20120057421A1
Автор: Robert M. Walker
Принадлежит: Micron Technology Inc

Methods, devices and systems for reducing the quantity of external interconnections of a memory device are disclosed. Implementation of one such method, device and system includes inputting over an address bus a first portion of an address of a next row of memory cells to be activated. The first portion of the address of the next row of memory cells to be activated is embedded in a command related to the previously activated row of memory cells. The next row of memory cells is subsequently activated according to a concurrently received second portion of the address of the next row of memory cells also received over the address bus. The portioning of the address signals can reduce the width of the address bus and, therefore, the number of required respective external interconnections.

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Номер записи: 11
31-05-2012 дата публикации

Charge pump control scheme using frequency modulation for memory word line

Номер: US20120134218A1
Автор: Hung-Chang Yu, Yue-Der Chih
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A memory includes a word line having a word line voltage, a charge pump coupled to the word line, and a dynamic feedback control circuit coupled to the charge pump. The dynamic feedback control circuit is capable of changing a clock frequency of a clock signal supplied the charge pump from a first non-zero value to a second non-zero value depending on the difference between the word line voltage and a target threshold voltage.

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Номер записи: 12
31-05-2012 дата публикации

Allocation method and apparatus of moderate memory

Номер: US20120137104A1
Автор: Guoping Li, HE Huang, Qinghua FAN
Принадлежит: Artek Microelectronics Co Ltd

An allocation method comprises: partitioning moderate memory into a plurality of physical memory pages having predetermined page size according to the predetermined page size; scanning the moderate memory using the predetermined page size and recording the physical address and damage degree of each physical memory page; obtaining the allocation information of the physical memory pages when a memory request is received and allocating physical memory to the request based on the recorded physical address and damage degree of each physical memory page and the obtained allocation information. A moderate memory is scanned and the physical address and damage degree of each physical memory page are recorded, then the physical memory is allocated based on the recorded physical address and damage degree of each physical memory page and the obtained allocation information.

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Номер записи: 13
14-06-2012 дата публикации

Continuous mesh three dimensional non-volatile storage with vertical select devices

Номер: US20120147644A1
Автор: Roy E. Scheuerlein
Принадлежит: SanDisk 3D LLC

A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

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Номер записи: 14
14-06-2012 дата публикации

Three dimensional non-volatile storage with multi block row selection

Номер: US20120147689A1
Автор: Roy E. Scheuerlein, Tianhong Yan
Принадлежит: SanDisk 3D LLC

A three-dimensional array adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

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Номер записи: 15
28-06-2012 дата публикации

NAND logic word line selection

Номер: US20120163114A1
Автор: Balaji Srinivasan, Dinesh Somasekhar, Fatih Hamzaoglu, Swaroop Ghosh
Принадлежит: Individual

A NAND architecture for selecting a word line driver in a DRAM is disclosed. Separately decoded addresses in the low, mid and high ranges are used to select a final word line driver. The output of the word line driver is at a potential negative with respect to ground for a deselected word line and a positive potential more positive than the power supply potential for a selected word line.

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Номер записи: 16
05-07-2012 дата публикации

Semiconductor device and method of generating voltages using the same

Номер: US20120170367A1
Автор: Bon Kwang Koo
Принадлежит: Hynix Semiconductor Inc

A semiconductor device includes a register unit for storing additional bits associated with a command signal and outputting a selected additional bit corresponding to a received address; a combination circuit for combining received control bits and the selected additional bit, and outputting enable signals based on the combined bits, where the received control bits are generated in response to the command signal and a control signal; and a voltage generation circuit for outputting voltages distributed in response to the enable signals.

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Номер записи: 17
05-07-2012 дата публикации

Column address counter circuit of semiconductor memory device

Номер: US20120170398A1
Автор: Jee Yul KIM
Принадлежит: Hynix Semiconductor Inc

The column address counter circuit of a semiconductor memory device includes at least one lower bit counter unit configured to generate a first bit of a column address by counting an internal clock, where the first bit is not a most significant bit of the column address, and a most significant counter unit configured to generate the most significant bit of the column address in response to a mask clock, where the mask clock is toggled when the internal clock is toggled by a set number of times.

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Номер записи: 18
16-08-2012 дата публикации

Semiconductor memory devices with a power supply

Номер: US20120206989A1
Автор: Tae-Joong Song
Принадлежит: SAMSUNG ELECTRONICS CO LTD

A semiconductor device includes a virtual power supplier, a driving signal generator and a load driver. The virtual power supplier boosts a driving voltage to generate a virtual voltage. The driving signal generator generates a driving signal based on the virtual voltage, such that the driving signal has a voltage level that is reinforced as compared with a voltage level of the driving voltage. The load driver drives a load based on the driving voltage and the driving signal.

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Номер записи: 19
30-08-2012 дата публикации

Non-volatile memory device and memory system including the same

Номер: US20120218850A1
Автор: Tae Un Youn
Принадлежит: Hynix Semiconductor Inc

A non-volatile memory device and a read method thereof are disclosed. The read method includes providing a memory block having memory cells connected to word lines and connected in serial to a bit line, sensing potential of the bit line by applying a first read voltage to a selected word line of the word lines and providing a first pass voltage to an unselected word line adjacent to the selected word line, sensing potential of the bit line by applying a second read voltage higher than the first read voltage to the selected word line and providing a second pass voltage lower than the first pass voltage to the unselected word line adjacent to the selected word line, and sensing potential of the bit line by applying a third read voltage higher than the second read voltage to the selected word line and providing a third pass voltage lower than the second pass voltage to the unselected word line adjacent to the selected word line.

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Номер записи: 20
06-09-2012 дата публикации

System and method of decoding data from memory based on sensing information and decoded data of neighboring storage elements

Номер: US20120224421A1
Автор: Eran Sharon, Idan Alrod, Simon Litsyn
Принадлежит: SanDisk Technologies LLC

Systems and methods to decode data stored in a data storage device are disclosed. Data bits stored in a first group of storage elements are decoded using data in a second group of storage elements together with physical characteristics of the second group of storage elements to aid in the decoding of the first group of storage elements.

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Номер записи: 21
27-09-2012 дата публикации

Semiconductor memory device and method of setting operation environment therein

Номер: US20120243365A1
Автор: Kazushige Kanda, Toshihiro Suzuki
Принадлежит: Toshiba Corp

A semiconductor memory device comprises: a memory cell array including a plurality of memory cells; an internal circuit having a function required in a storage operation of the memory cell array; a parameter storage unit configured to store a certain parameter and to have a storage place specified by a parameter address, the certain parameter designating an operation of the internal circuit; a command register configured to store a command instructing an operation of the internal circuit; and a converting circuit configured to adjust at least one of the parameter address and the command that differ between products or between standards to the internal circuit.

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Номер записи: 22
01-11-2012 дата публикации

Variable Resistance Switch Suitable for Supplying High Voltage to Drive Load

Номер: US20120275225A1
Автор: Feng Pan, Jonathan Hoang Huynh, Khin Htoo
Принадлежит: SanDisk Technologies LLC

A circuit for supplying a high voltage to load is described. An example of such a circuit could be used in the peripheral circuitry of a non-volatile memory device for supplying a program voltage from a charge pump to a selected word line. The circuit includes a charge pump that generates the high voltage and decoding circuitry that is connected to receive this high voltage and selectively apply it to a load. The decoding circuitry receives the high voltage through a switch, where the switch is of a variable resistance that progressively passes the high voltage in response to a control signal. In a particular example, the switch includes a transistor connected between the charge pump and the decoding circuitry, where the control gate of the transistor is connected to the output of a second charge pump that is connected to receive the high voltage and a settable clock signal as its inputs.

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Номер записи: 23
01-11-2012 дата публикации

Internal wordline current leakage self-detection method, detection system and computer-readable storage medium for nor-type flash memory device

Номер: US20120275228A1
Автор: Hsiao-Hua Lu
Принадлежит: Eon Silicon Solutions Inc

A wordline internal current leakage self-detection method, system and a computer-readable storage medium thereof employ the originally existed high voltage supply unit and the voltage detector connected to the wordline in the flash memory device, in which the high voltage supply unit applies the test signal to the selected wordline, and the voltage detector detects the voltage signal of the wordline. By comparing the test signal with the voltage signal, the wordline will be indicated as current leakage when the voltage signal is lower than the test signal.

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Номер записи: 24
08-11-2012 дата публикации

Raising Programming Currents of Magnetic Tunnel Junctions Using Word Line Overdrive and High-k Metal Gate

Номер: US20120281464A1
Автор: Chun-Jung Lin, Hung-Sen Wang, Shine Chung, Tao-Wen Chung, Yu-Jen Wang
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A method of operating magneto-resistive random access memory (MRAM) cells includes providing an MRAM cell, which includes a magnetic tunneling junction (MTJ) device; and a selector comprising a source-drain path serially coupled to the MTJ device. The method further includes applying an overdrive voltage to a gate of the selector to turn on the selector.

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Номер записи: 25
10-01-2013 дата публикации

Memory circuit and word line control circuit

Номер: US20130010531A1
Автор: Shih-Huang Huang
Принадлежит: MediaTek Inc

The invention provides a memory circuit. In one embodiment, the memory circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second PMOS transistor, and a memory cell array. The first PMOS transistor is coupled between a first voltage terminal and a first node. The second PMOS transistor is coupled between the first voltage terminal and a second node. The first NMOS transistor is coupled between a third node and a second voltage terminal. The second NMOS transistor is coupled between a fourth node and the second voltage terminal. The memory cell array comprises a plurality of memory cells, at least one comprising a first inverter and a second inverter. A positive power terminal of the first inverter is coupled to the first node, a negative power terminal of the first inverter is coupled to the third node, a positive power terminal of the second inverter is coupled to the second node, and a negative power terminal of the second inverter is coupled to the fourth node.

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Номер записи: 26
14-02-2013 дата публикации

Line driver circuits, methods, and apparatuses

Номер: US20130039132A1
Автор: Howard C. Kirsch, Mingshiang Wang, Tae H. Kim, Todd A. Merritt, Yu-Wen Huang
Принадлежит: Individual

Described embodiments are directed to line drivers, such as those for providing reduced gate induced drain leakage in a memory array. Corresponding methods of operation of line drivers are also disclosed.

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Номер записи: 27
14-02-2013 дата публикации

Input buffer circuit, semiconductor memory device and memory system

Номер: US20130039142A1
Автор: Hyoung-Seok Kim, Kwan-Yong Jin
Принадлежит: Individual

An input buffer circuit includes a logic unit, a clock enable buffer, and a clock buffer. The logic unit is configured to receive a clock signal and a clock enable signal, and to output a decision signal indicative of whether the clock signal is normally input, where the decision signal is activated when the clock signal is normally input. The clock enable buffer is configured to buffer the clock enable signal and to activate an internal clock enable signal, in response to an activation of the decision signal. The clock buffer is configured to buffer the clock signal and to output an internal clock signal, in response to an activation of the internal clock enable signal.

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Номер записи: 28
28-02-2013 дата публикации

Floating addressing of an eeprom memory page

Номер: US20130051153A1
Автор: Francois Tailliet, Yvon Bahout
Принадлежит: STMICROELECTRONICS ROUSSET SAS

A method for electrically programming a non-volatile memory in which a programming cycle includes prior addressing of memory cells from an initial address corresponding to a first row and a column of a memory plane. The method may include addressing the memory cells in a second consecutive row when the end of the first row i is reached to store data on bits with consecutive and increasing addresses in two consecutive rows.

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Номер записи: 29
28-02-2013 дата публикации

High voltage generation circuit and semiconductor device including the same

Номер: US20130051159A1
Автор: Je Il RYU
Принадлежит: SK hynix Inc

A high voltage generation circuit includes a plurality of pumps configured to generate a final pump voltage, a plurality of switches configured to couple the pumps to various nodes, a voltage division circuit configured to divide the final pump voltage from the pumps interconnected by the switches, and outputting a divided voltage, a section signal generation circuit configured to generate a plurality of section signals by comparing the divided voltage with each of different reference voltages, and a section signal combination circuit configured to generate enable signals for controlling the switches by combining the section signals.

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Номер записи: 30
21-03-2013 дата публикации

Select devices for memory cell applications

Номер: US20130070511A1
Автор: D.V. Nirmal Ramaswamy, David H. Wells
Принадлежит: Micron Technology Inc

Select devices for memory cell applications and methods of forming the same are described herein. As an example, one or more memory cells comprise a a select device structure including a two terminal select device having a current-voltage (I-V) profile associated therewith, and a non-ohmic device in series with the two terminal select device. The combined two terminal select device and non-ohmic device provide a composite I-V profile of the select device structure that includes a modified characteristic as compared to the I-V profile, and the modified characteristic is based on at least one operating voltage associated with the memory cell.

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Номер записи: 31
21-03-2013 дата публикации

IMAGE DECODING APPARATUS, IMAGE ENCODING APPARATUS, AND METHOD AND PROGRAM FOR IMAGE DECODING AND ENCODING

Номер: US20130071038A1
Автор: Kondo Kenji
Принадлежит:

An encoded bit stream is processed by a lossless decoding unit (), an inverse quantization unit (), and an inverse orthogonal transform unit () in this order, to obtain orthogonally transformed coefficient data and encoding parameter information. The inverse orthogonal transform unit () performs an inverse orthogonal transform on the coefficient data by using bases that are set beforehand in accordance with the locations of transform blocks in a macroblock indicated by the encoding parameter information. In this manner, prediction error data is obtained. An intra prediction unit () generates predicted image data. An addition unit () adds the predicted image data to the prediction error data, to decode image data. By using bases that are set in accordance with the locations of transform blocks, an optimum inverse orthogonal transform can be performed, and encoding efficiency can be increased. 1. An image decoding apparatus that performs an orthogonal transform on prediction error data of each transform block , and decodes image data from an encoded bit stream generated by processing coefficient data subjected to the orthogonal transform , the prediction error data being a difference between the image data and predicted image data ,the image decoding apparatus comprising:a data processing unit configured to process the encoded bit stream to obtain the coefficient data subjected to the orthogonal transform and encoding parameter information;an inverse orthogonal transform unit configured to perform an inverse orthogonal transform on the coefficient data by using a base to obtain the prediction error data, the base being set beforehand in accordance with a location of the transform block in a macroblock indicated by the encoding parameter information;a predicted image data generation unit configured to generate the predicted image data; andan addition unit configured to add the predicted image data generated by the predicted image data generation unit to the prediction ...

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Номер записи: 32
28-03-2013 дата публикации

CONTROL OF INPUTS TO A MEMORY DEVICE

Номер: US20130077417A1
Автор: Abe Keiichiro, Ito Yutaka, Nomura Masayoshi
Принадлежит: MICRON TECHNOLOGY, INC.

A memory device includes a command decoder and control interface logic. One or more external inputs, such as row and column address strobes, communicate with the command decoder through the control interface logic. A control signal is also in communication with the control interface logic. During operation of a drowsy mode in the memory device, a self-refresh signal causes the control signal to disable the external inputs. With the external inputs disabled, command hazards are reduced when exiting drowsy mode. 1. A semiconductor integrated circuit device comprising:a command decoder configured to control a memory system by decoding a memory system input signal;interface logic electrically coupled to the command decoder and configured to receive the memory system input signal and a control signal, the interface logic further configured to disable the memory system input signal based at least in part on the control signal;self-refresh logic configured to provide a self-refresh signal based at least in part on an external clock enable signal, the control signal based at least in part on the self-refresh signal; anda path-gate electrically coupled to the self-refresh logic and configured to receive the external clock enable signal and provide the external clock enable signal to the self-refresh logic, the path-gate receiving power from a main voltage generator and a secondary voltage generator in the event that the main voltage generator powers off.2. The semiconductor integrated circuit device of wherein the main voltage generator is configured to provide a generator state signal indicating a voltage level of the main voltage generator.3. The semiconductor integrated circuit device of wherein the control signal is based at least in part on the self refresh signal and the generator state signal.4. The semiconductor integrated circuit device of wherein the control signal causes the interface logic to disable the memory system input signal when the main voltage generator ...

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Номер записи: 33
04-04-2013 дата публикации

Voltage supply circuit, semiconductor memory device, and operating method thereof

Номер: US20130083614A1
Автор: Duck Ju Kim, Je Il RYU, Pil Seon YOO
Принадлежит: SK hynix Inc

A voltage supply circuit includes a high voltage generator configured to generate an operating voltage, a global word line switch configured to transfer the operating voltage to global word lines, a plurality of local line switches coupled to the global word lines and configured to transfer the operating voltage to corresponding local word lines, a precharge unit configured to supply a precharge voltage to an unselect local line switch adjacent to a select local line switch to which the operating voltage will be supplied, from among the plurality of local line switches, in a preparation section before an operation is started, and a coupling unit configured to couple the unselect local line switch and the global word line switch when the operation is started.

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Номер записи: 34
11-04-2013 дата публикации

IMAGE SIGNAL ENCODING APPARATUS AND IMAGE SIGNAL ENCODING METHOD

Номер: US20130089267A1
Автор: Hattori Shinobu, Suzuki Teruhiko
Принадлежит: SONY CORPORATION

An encoding method encodes a first image signal of a first view and a second image signal of a second view. The method includes encoding the first image signal to generate a base stream. The method also includes encoding the second image signal to generate a dependent stream, and inserting a dependent delimiter indicating a picture boundary between pictures in the dependent stream at the beginning of a picture in the dependent stream. 1. An encoding method for encoding a first image signal of a first view and a second image signal of a second view , the method comprising:encoding the first image signal to generate a base stream; andencoding the second image signal to generate a dependent stream, and inserting a dependent delimiter indicating a picture boundary between pictures in the dependent stream at the beginning of a picture in the dependent stream.2. An encoding apparatus for encoding a first image signal of a first view and a second image signal of a second view , the apparatus comprising:means for encoding the first image signal to generate a base stream; andmeans for encoding the second image signal to generate a dependent stream and for inserting a dependent delimiter indicating a picture boundary between pictures in the dependent stream at the beginning of a picture in the dependent stream.3. An encoding apparatus for encoding a first image signal of a first view and a second image signal of a second view , the apparatus comprising:a processing unit configured to encode the first image signal to generate a base stream, to encode the second image signal to generate a dependent stream, and to insert a dependent delimiter indicating a picture boundary between pictures in the dependent stream at the beginning of a picture in the dependent stream. This application is a continuation of and claims the benefit of priority under 35 U.S.C. §120 from U.S. Ser. No. 12/993,400, filed Nov. 18, 2010, the entire content of which is incorporated herein by reference. U.S. ...

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Номер записи: 35
18-04-2013 дата публикации

Apparatus, System, and Method for Writing Multiple Magnetic Random Access Memory Cells with a Single Field Line

Номер: US20130094283A1
Автор: Jean-Pierre Nozieres, Neal Berger, Virgile Javerliac
Принадлежит: Crocus Technology Inc

A memory device includes a plurality of magnetic random access memory (MRAM) cells, a field line, and a field line controller configured to generate a write sequence that traverses the field line. The write sequence is for writing a multi-bit word to the plurality of MRAM cells. The multi-bit word includes a first subset of bits having a first polarity and a second subset of bits having a second polarity. The write sequence writes concurrently to at least a subset of the plurality of MRAM cells corresponding to the first subset of bits having the first polarity, then subsequently writes concurrently to a remaining subset of the plurality of MRAM cells corresponding to the second subset of bits having the second polarity.

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Номер записи: 36
18-04-2013 дата публикации

Method and Apparatus of Addressing A Memory Integrated Circuit

Номер: US20130094319A1
Автор: Chang Kuen-Long, Chih Hsieh Ming, Hung Chun-Hsiung
Принадлежит:

A memory integrated circuit has control circuitry that accesses memory cells of the memory integrated circuit. The control circuitry is responsive to commands including a first command and a second command. The first command specifies a high order set of address bits. The second command specifies a low order set of address bits. The high order set of address bits and the low order set of address bits constitute a complete access address of the memory integrated circuit. The first command and the second command have different in command codes. 1. An integrated circuit , comprising:an input receiving a memory command for the memory array, the memory command including an encoded memory address; and 'an address decoder receiving the encoded memory address and generating a decoded memory address from the encoded memory address, wherein the decoded memory address is longer than the encoded memory address; and', 'control circuitry accessing the memory array on the integrated circuit, comprisingthe memory array.2. The circuit of claim 1 , wherein the memory command is sent from a location off of the integrated circuit.3. The circuit of claim 1 , wherein the encoded memory address is encoded at a location off of the integrated circuit.4. The circuit of claim 1 , wherein the memory command includes an operation code and the encoded memory address.5. The circuit of claim 1 , wherein the memory array is addressable by the decoded memory address and not addressable by the encoded memory address.6. The circuit of claim 1 , wherein the decoded memory address is associated with a communication duration of fewer address load cycles than the encoded memory address.7. The circuit of claim 1 , wherein the decoded memory address is associated with a serial communication duration of fewer address load cycles than the encoded memory address.8. A method claim 1 , comprising:receiving a memory command for a memory array in an integrated circuit, the memory command including an encoded ...

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Номер записи: 37
18-04-2013 дата публикации

SEMICONDUCTOR DEVICE HAVING LATENCY COUNTER TO CONTROL OUTPUT TIMING OF DATA AND DATA PROCESSING SYSTEM INCLUDING THE SAME

Номер: US20130094321A1
Автор: Dono Chiaki, SHIDO Taihei
Принадлежит: ELPIDA MEMORY, INC.

Disclosed herein is a device that includes a command decoder and a latency counter. The command decoder generates a first internal command in response to a first internal clock signal. The latency counter includes: a gate control signal generation unit generating output gate signals in response to a second internal clock signal; delay circuits each receiving an associated one of the output gate signals and generating an associated one of input gate signals; and a command signal latch unit fetching the first internal command in response to one of the input gate signals and outputting the first internal command in response to one of the output gate signals. Each of the delay circuit includes a first delay element that operates on a first power supply voltage and a second delay element that operates on a second power supply voltage different from the first power supply voltage. 1. A semiconductor device comprising:a command decoder generating a first internal command in response to a first internal clock signal; and a gate control signal generation unit generating a plurality of output gate signals in response to a second internal clock signal that is different from the first internal clock signal;', 'a plurality of delay circuits each receiving an associated one of the output gate signals and generating an associated one of a plurality of input gate signals, each of the delay circuits including a first delay element that operates on a first power supply voltage and a second delay element that operates on a second power supply voltage, the first power supply voltage being different from the second power supply voltage; and', 'a command signal latch unit fetching the first internal command in response to one of the input gate signals and outputting the first internal command as a second internal command in response to one of the output gate signals., 'a latency counter that includes;'}2. The semiconductor device as claimed in claim 1 , wherein each of the first and ...

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Номер записи: 38
25-04-2013 дата публикации

Method and apparatus for word line suppression

Номер: US20130100730A1
Автор: Chien-Kuo SU, Chiting Cheng, Chung-Cheng Chou, Jack Liu, Jonathan Tsung-Yung Chang
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A memory access operation on a bit cell of a digital memory, e.g., a static random access memory (SRAM), is assisted by reducing the word line control voltage for reading and boosting it for writing, thus improving data integrity. The bit cell has cross coupled inverters for storing and retrieving a logic state via bit line connections through a passing gate transistor controlled by the word line. A level of a word line signal controlling the passing gate transistor is shifted from a first voltage value to a higher second voltage value to begin a memory access cycle. The level of the word line signal is shifted from the second voltage value to a third voltage value less than the second voltage value during the access cycle. The word line signal is maintained at the third voltage value for a time interval during the access cycle.

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Номер записи: 39
25-04-2013 дата публикации

SEMICONDUCTOR DEVICE

Номер: US20130100750A1
Автор: Hironaka Tetsuo, INAGI Masato, ISHIGURO Takashi, Sato Masayuki, Shimazaki Hitoshi
Принадлежит: TAIYO YUDEN CO., LTD.

Disclosed is a semiconductor device which is intended to reduce the total number of storage element blocks that constitute a desired logic circuit. The semiconductor device includes N address lines (N is an integer equal to two or more), N data lines, and a plurality of storage sections. Each of the storage sections includes an address decoder for decoding an address supplied via the N address lines to output a word select signal to word lines; and a plurality of storage elements which are connected to the word lines and the data lines, each store data that constitute a truth table, and input or output the data via the data lines in accordance with the word select signal supplied via the word lines. The semiconductor device is adapted such that the N address lines for the storage sections are connected to the respective data lines of other N ones of the storage sections, while the N data lines for the storage sections are connected to the respective address lines of other N ones of the storage sections. 115-. (canceled)16. A semiconductor device , comprising:a first logic section and a second logic section each including a plurality of storage sections, each storage section including (i) an address decoder which decodes a memory operation address inputted from a first address line or a logic operation address inputted from a second address line and outputs a word selection signal to a word line, and (ii) a plurality of storage elements being connected to the word line and a data line, which store data configuring a truth table defining a logic operation or connection relation, and are connected to the data line inputting and outputting the data by the word selection signal inputted from the word line; andan arithmetic processing section which includes (i) a first input/output section connecting the first address line of the storage sections included in the first logic section and the data line, (ii) a second input/output section connecting the second address line of ...

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Номер записи: 40
25-04-2013 дата публикации

LOCAL WORD LINE DRIVER

Номер: US20130100758A1
Автор: Chen Chung-Kuang, Chen Han-Sung, Hung Chun-Hsiung
Принадлежит:

A memory circuit with a word line driver and control circuitry is disclosed. The word line driver receives a first voltage reference signal, a second voltage reference signal, and an input signal. The word line driver has an output coupled to a word line. The control circuitry is configured to deselect the word line by applying the input signal to the input of the word line driver. For example, in a program operation the word line is deselected to indicate that the word line is not programmed, and another word line is selected to be programmed. During an operation in which the word line is deselected and another word line is selected, the word line discharges through both of a first p-type transistor and a first n-type transistor of the word line driver. 1. A memory circuit , comprising:a word line driver receiving a first voltage reference signal, a second voltage reference signal, and an input signal, the word line driver having an output coupled to a word line; andcontrol circuitry configured to deselect the word line by applying the input signal to the input of the word line driver, wherein during an operation in which the word line is deselected and another word line is selected, the word line discharges through both of a first p-type transistor and a first n-type transistor of the word line driver.2. The memory circuit of claim 1 , wherein claim 1 , during the program operation in which the word line is deselected and another word line is selected claim 1 , the control circuitry prevents discharge of the word line via only a p-type transistor of the word line driver.3. The memory circuit of claim 1 , wherein the input signal having one of at least a select value and a deselect value claim 1 , the select value and the deselect value having a same voltage polarity during an operation.4. The memory circuit of claim 1 , wherein the first voltage reference signal is received from a global word line claim 1 , the global word line selecting or deselecting a plurality ...

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Номер записи: 41
02-05-2013 дата публикации

Selector circuit and processor system

Номер: US20130106492A1
Автор: Tomohiro Tanaka
Принадлежит: Fujitsu Ltd

A selector circuit includes a plurality of first selection circuits each configured to select one of plural input signals on the basis of a first selection control signal and to output a first output signal and a second selection circuit configured to select one of the first output signals on the basis of a second selection control signal. Each of the first selection circuits includes a charging circuit configured to charge a first node by electrically connecting the first node to a first voltage in a first period, and a discharge control circuit configured to control, on the basis of the first selection control signal, the input signals and the second selection control signal, whether to discharge the charged first node by electrically connecting the first node to a second voltage source having a potential lower than the first voltage source in a second period following the first period.

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Номер записи: 42
02-05-2013 дата публикации

STORAGE DEVICE, CONTROL METHOD OF STORAGE DEVICE, AND CONTROL METHOD OF STORAGE CONTROL DEVICE

Номер: US20130107644A1
Автор: NIIMI Masahiro
Принадлежит: SPANSION LLC

Memory cell regions as units of erasing operation are sectors S, and units of reading operation and/or writing operation are blocks B to B in a sector, in which a block address BA for selecting one of blocks B to B is held in block address buffer (BAB) . Holding operation is executed prior to reading or writing operation, and hence in subsequent reading operation or writing operation, re-input is not needed. Depending on the held block address BA, any one of selection signals YDn (n=0 to 3) is selected, and any one block is selected depending on the selection signal YDn. This state is maintained until the block address BA held in the block address buffer (BAB) is rewritten, and therefore it is not required to enter or decode the block address BA on every occasion of reading and/or writing operation, so that the access operation can be executed promptly and at low current consumption. 124.-. (canceled)25. A control method of a storage device which comprises a memory cell array comprised of a plurality of sectors each of which is a memory cell region that is associated as a unit with an erase operation , the control method comprising:inputting a first address signal which selects a partial region when a readout operation and a write operation starts, the partial region being defined as one unit of access;holding the inputted first address signal during the readout operation and the write operation of the partial region, wherein the partial region comprises a plurality of data readout lines which are placed in the sector and partitioned; andretaining the plurality of the data readout lines in a selected state during the readout operation and/or the write operation depending on the held first address signal.26. The control method of the storage device of claim 25 , further comprising commonly selecting a memory cell selection line which intersects with the data readout lines in the sector regardless of the first address signal.27. The control method of the storage ...

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Номер записи: 43
02-05-2013 дата публикации

IMAGE PROCESSING DEVICE, IMAGE PROCESSING METHOD, AND PROGRAM

Номер: US20130108185A1
Автор: Kenji Kondo
Принадлежит: SONY CORPORATION

The present technology relates to an image processing device, an image processing method, and a program capable of reducing the amount of processing required for ROT and DCT or inverse DCT and inverse ROT. Image information obtained by decoding an encoded image is dequantized to obtain a low frequency component of the image information, which is obtained by a first orthogonal transform unit, and to obtain a frequency component higher than the low frequency component of the image information, which is obtained by a second orthogonal transform unit. The low frequency component and the high frequency component are subjected to an inverse orthogonal transform according to the same method. The present technology can be applied when encoding and decoding images, for example. 1. An image processing device comprising:a dequantization unit that dequantizes a quantized image to obtain a low frequency component having a predetermined size of the image, which is obtained by performing a second orthogonal transform after a first orthogonal transform, and to obtain a high frequency component, which is a component other than the low frequency component of the image and is obtained by the first orthogonal transform; andan inverse orthogonal transform unit that, when a size of the image is the predetermined size, performs a third inverse orthogonal transform, which is a combined transform of a first inverse orthogonal transform corresponding to the first orthogonal transform and a second inverse orthogonal transform corresponding to the second orthogonal transform, on the image which is the low frequency component, and that, when the size of the image is larger than the predetermined size, performs the second inverse orthogonal transform on the low frequency component and performs the first inverse orthogonal transform on the low frequency component having been subjected to the second inverse orthogonal transform and the high frequency component obtained by the dequantization unit.2 ...

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Номер записи: 44
02-05-2013 дата публикации

Semiconductor memory device and operating method thereof

Номер: US20130111101A1
Автор: Seok-Cheol Yoon
Принадлежит: Hynix Semiconductor Inc

A semiconductor memory device includes a path control unit configured to activate an address transmission path corresponding to a bank address, an address providing unit configured to provide a memory address to the path control unit in response to an active signal, and a plurality of memory banks each configured to receive the memory address provided through the corresponding address transmission path of the path control unit, wherein the bank address corresponds to a memory bank of the plurality of memory banks.

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Номер записи: 45
09-05-2013 дата публикации

VIDEO CAMERA

Номер: US20130113951A1
Автор: Jannard James, Nattress Thomas Graeme
Принадлежит: RED.COM, INC.

Embodiments provide a video camera that can be configured to highly compress video data in a visually lossless manner. The camera can be configured to transform blue and red image data in a manner that enhances the compressibility of the data. The data can then be compressed and stored in this form. This allows a user to reconstruct the red and blue data to obtain the original raw data for a modified version of the original raw data that is visually lossless when demosacied. Additionally, the data can be processed in a manner in which the green image elements are demosaiced first and then the red and blue elements are reconstructed based on values of the demosaiced green image elements. 1. (canceled)2. A method of compressing mosaiced digital image data , comprising: first pixel data corresponding to first pixels of the plurality of sensor pixels and that represents light corresponding to a first color; and', 'second pixel data corresponding to second pixels of the plurality of sensor pixels and that represents light corresponding to a second color; and, 'with a plurality of digital image sensor pixels, generating mosaiced image data, the mosaiced image data comprising at leastfor each second pixel of a plurality of the second pixels, and based on values of the first pixel data corresponding to two or more of the first pixels, transforming the second pixel data corresponding to the second pixel, said two or more of the first pixels located on opposite sides of and in the vicinity of the second pixel;compressing the transformed second pixel data; andstoring the compressed, transformed second pixel data on a memory device.3. The method of claim 2 , wherein said transforming comprises:calculating an average of the values of the first pixel data corresponding to said two or more of the first pixels; andsubtracting the calculated average from a value of the second pixel data corresponding to the second pixel.4. The method of claim 2 , wherein said two or more of the ...

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Номер записи: 46
16-05-2013 дата публикации

MEMORY ACCESS CONTROL DEVICE AND MANUFACTURING METHOD

Номер: US20130121093A1
Автор: Hashimoto Takashi, Morimoto Takashi
Принадлежит:

A memory access control device including: a bit position information storage unit storing bit position information indicating one or more bit positions in a bit sequence of a predetermined length; a reading unit configured to attempt to read a bit sequence from the range specified by the logical address received by the logical address receiving unit, thereby receiving a first bit sequence from the external memory in units of the predetermined length, the first bit sequence being composed of bits that are larger in number than bits stored in the range specified by the logical address; a bit sequence extracting unit configured to extract one or more bit sequences from the first bit sequence at the one or more bit positions indicated by the bit position information in units of the predetermined length. 1. A memory access control device comprising:a logical address receiving unit configured to receive a logical address specifying a range in a storage area of an external memory;a bit position information storage unit storing bit position information indicating one or more bit positions in a bit sequence of a predetermined length;a reading unit configured to attempt to read a bit sequence from the range specified by the logical address received by the logical address receiving unit, thereby receiving a first bit sequence from the external memory in units of the predetermined length, the first bit sequence being composed of bits that are larger in number than bits stored in the range specified by the logical address;a bit sequence extracting unit configured to extract one or more bit sequences from the first bit sequence at the one or more bit positions indicated by the bit position information in units of the predetermined length; andan output unit configured to generate a second bit sequence composed of bits that are equal in number to the bits stored in the range specified by the logical address, by using the one or more bit sequences extracted by the bit sequence ...

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Номер записи: 47
16-05-2013 дата публикации

INTEGRATED CIRCUIT COMPRISING A DELAY-LOCKED LOOP

Номер: US20130121094A1
Автор: Chau Pak S., Hossain Masum, Zerbe Jared L.
Принадлежит: RAMBUS INC.

Embodiments of an integrated circuit (IC) comprising a delay-locked loop (DLL) are described. Some embodiments include first circuitry to generate a first clock signal by delaying an input clock signal by a first delay, second circuitry to determine a code based on the input clock signal and the first clock signal, and third circuitry to produce an output clock signal based on the input clock signal and the code. In some embodiments, the power consumption of the DLL circuitry is reduced by powering down at least some parts of the DLL circuitry for most of the time. In some embodiments, the clock signal that is used to clock the command-and-address circuitry of a memory device is used to clock the on-die-termination latency counter circuitry. 1. An integrated circuit (IC) , comprising:first circuitry to generate a first clock signal by delaying an input clock signal by a first delay;second circuitry to determine a code based on the input clock signal and the first clock signal, wherein the code represents a second delay which, when applied to the first clock signal, produces a second clock signal that has a desired phase delay with respect to the input clock signal; andthird circuitry to produce an output clock signal based on the input clock signal and the code, wherein the third circuitry is capable of delaying the input clock signal by the second delay.2. The IC of claim 1 , wherein the first delay is substantially equal to a buffer delay of a clock buffer.3. The IC of claim 2 , wherein the IC further comprises fourth circuitry to provide the output clock signal as an input to the clock buffer.4. The IC of claim 2 , further comprising:a duty-cycle corrector (DCC) to adjust a duty cycle of the output clock signal; andfourth circuitry to provide an output signal of the DCC as an input to the clock buffer.5. The IC of claim 1 , wherein the desired phase delay is zero.6. The IC of claim 1 , wherein the second circuitry comprises:fourth circuitry to generate a set of ...

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Номер записи: 48
16-05-2013 дата публикации

IMAGE PROCESSING DEVICE AND IMAGE PROCESSING METHOD

Номер: US20130121604A1
Автор: Matsuhira Masatoshi
Принадлежит: SEIKO EPSON CORPORATION

In the printer, the correction content setting portion sets equal to or more than one correction contents, the decimation rate setting portion sets decimation rates for respective planes of Y, Cb, and Cr of JPEG data (compressed data) based on the set correction contents. Pixels are decimated at the set decimation rates and the decompression processing unit decompresses the JPEG data so as to generate image data. In this manner, decimation processing is performed in accordance with the plurality of correction contents. Therefore, for example, inverse quantization processing, inverse DCT operation processing, and the like, can be omitted in accordance with the correction contents. The decompression processing may be executed on a sampling image to be used for sampling when the contents of correction to be performed on the image data are determined and on a print image to be used for printing. 1. An image processing device that decompresses compressed data which has a plurality of planes and has been compressed with a compression method with DCT operation so as to generate image data , the image processing device comprising:a correction content setting unit that sets equal to or more than one correction contents relating to the image data;a decimation rate setting unit that sets a decimation rate for each of the plurality of planes based on the set correction contents,and a decompression processing unit that decimates pixels at the decimation rate set for each of the plurality of planes and decompresses the compressed data so as to generate the image data.2. The image processing device according to claim 1 ,wherein the correction content setting unit sets the correction contents including equal to or more than one of face information, exposure degree, intensity, contrast, blurring degree and noise degree, andthe decimation rate setting unit sets the decimation rates for the planes in accordance with the correction contents including equal to or more than one of the ...

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Номер записи: 49
23-05-2013 дата публикации

NON-VOLATILE MEMORY DEVICE HAVING CONFIGURABLE PAGE SIZE

Номер: US20130128668A1
Автор: KIM Jin-Ki
Принадлежит: MOSAID TECHNOLOGIES INCORPORATED

A flash memory device having at least one bank, where the each bank has an independently configurable page size. Each bank includes at least two memory planes having corresponding page buffers, where any number and combination of the memory planes are selectively accessed at the same time in response to configuration data and address data. The configuration data can be loaded into the memory device upon power up for a static page configuration of the bank, or the configuration data can be received with each command to allow for dynamic page configuration of the bank. By selectively adjusting a page size the memory bank, the block size is correspondingly adjusted. 1. A flash memory device comprising:a memory bank having a plurality of planes, including a first plane and a second plane, each of the plurality of planes having a page buffer for storing write data for programming to a corresponding plane and for storing read data from the corresponding plane; and,the first plane and the second plane both being configured to be selectively enabled at the same time when required based on configuration data and address data in relation to a memory operation within the flash memory device.2. The flash memory device of claim 1 , wherein each of the plurality of planes includes a dedicated row decoder for driving wordlines.3. The flash memory device of claim 1 , wherein the plurality of planes are organized as tiles claim 1 , where each of the tiles includes two planes coupled to a shared row decoder for driving wordlines in the two planes.4. The flash memory device of claim 3 , wherein the shared row decoder of each of the tiles selectively drives wordlines of at least one of the two planes in response to row decoder enabling signals.5. The flash memory device of claim 4 , wherein the shared row decoder includesa row driver for selectively passing row drive signals to the wordlines of the one of the two planes in response to a first output voltage, and to the wordlines of the ...

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Номер записи: 50
23-05-2013 дата публикации

Semiconductor Devices and Methods for Changing Operating Characteristics and Semiconductor Systems Including the Same

Номер: US20130128683A1
Автор: Ahn Seung Eon, Choi Hyun Ho, Kang Sang Beom, Kim Ho Jung, LEE Jung Min, Park Chul Woo
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A method of changing a parameter in a semiconductor device is provided. The method includes receiving and storing data in a storage region; and changing at least one between a DC characteristic and an AC timing characteristic of a parameter, used to access a non-volatile memory cell included in a memory core of the semiconductor device, according to the data stored in the storage. 1. A method of controlling a memory system that includes a memory device and a memory controller , the method comprising:generating and transmitting a data set including a command and data to the memory device, using the memory controller;decoding the command from the data set, and storing the data in a storage region of the memory device based on the decoding result;generating a parameter control signal based on the data stored in the storage region; andchanging an AC timing characteristic of a parameter used to access a memory cell of the memory device according to the parameter control signal.2. The method of claim 1 , wherein the generating the parameter control signal includes:generating a plurality of DC voltages according to a first portion of the data stored in the storage region;generating a plurality of AC timing signals according to a second portion of the data stored in the storage region; andgenerating the parameter control signal by mixing one of the DC voltages and one of the AC timing signals in response to selection signals.3. The method of claim 1 , wherein the parameter is a program time claim 1 , an erase time claim 1 , a read time claim 1 , a program voltage claim 1 , an erase voltage claim 1 , a read voltage claim 1 , a reference cell voltage claim 1 , a program current claim 1 , an erase current claim 1 , a read current claim 1 , and/or a reference cell current claim 1 ,4. The method of claim 1 , wherein the AC timing characteristic is a parameter control signal time value.5. The method of claim 1 , wherein the command included in the data set instructs the memory ...

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Номер записи: 51
23-05-2013 дата публикации

REDUCED LEAKAGE BANKED WORDLINE HEADER

Номер: US20130128684A1
Автор: Buettner Stefan, Froehnel Thomas, Juchmes Werner, Sautter Rolf, Zyuban Victor
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A memory array can be arranged with header devices to reduce leakage. The header devices are coupled with a decoder to receive at least a first portion of a memory address indication and are coupled to receive current from a power supply. Each of header devices is adapted to provide power from the power supply to a set of the wordline drivers corresponding to a bank indicated with the first portion of the memory address indication. Each of the logic devices is coupled to receive at least a second portion of the memory address indication from a decoder. Each of the logic devices is coupled to activate the wordline drivers coupled with those of the wordlines indicated with the second portion of the memory address indication. 1. An electronic device , comprisinga memory bank comprising a plurality of wordlines adapted to activate memory cells; an input to activate the wordline driver,', 'the output to activate the respective one of the plurality of wordlines, and a power input that receives current to power the wordline driver;, 'a plurality of wordline drivers, each of the plurality of wordline drivers coupled via an output to a respective one of the plurality of wordlines and comprising'}a decoder adapted to decode a memory access request and to generate a memory address indication from a decoded memory access request, the decoder coupled to control delivery of power from an array supply to the power inputs of the plurality of wordline drivers based on a first part of the memory address indication and coupled to control selective activation of the plurality of word line drivers via the inputs thereof based on a second part of the memory address indication.2. The electronic device according to further comprising a header control device coupled to receive the first part of the memory address indication from the decoder and coupled to provide power to the power inputs of the plurality of wordline drivers in accordance with the first part of memory address indication.3. ...

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Номер записи: 52
23-05-2013 дата публикации

TAMPER-RESISTANT MEMORY INTEGRATED CIRCUIT AND ENCRYPTION CIRCUIT USING SAME

Номер: US20130129083A1
Автор: Fujino Takeshi
Принадлежит: The Ritsumeikan Trust

The present invention provides an integrated memory circuit applicable to an S-box of a cryptographic circuit, the integrated memory circuit having a row decoder, a column decoder, and a sense amplifier composed of a domino-RSL circuit, wherein data reading and data writing from/to memory cells of a memory cell array are performed via two complementary bit lines, and the transition probability of a signal line is equalized by input of random-number data supplied from a random-number generating circuit using an arbiter circuit. 1. An integrated memory circuit comprising a memory cell array , a row decoder , a column decoder , a sense amplifier , and an input/output driver , wherein data reading and data writing from/to memory cells of the memory cell array is performed via two complementary bit lines , and each of the row decoder , the column decoder , and the sense amplifier comprises a circuit in which transition probabilities of signal lines are equalized by random-number data that is externally supplied.2. The integrated memory circuit according to claim 1 , wherein each of the row decoder claim 1 , the column decoder claim 1 , and the sense amplifier comprises a domino-RSL circuit.3. The integrated memory circuit according to claim 2 , wherein:the row decoder comprises a first predecoder and a word line driver for driving word lines of the memory cells;the first predecoder comprises a plurality of first inverters for inverting a part of multiple-bit data that constitutes address data, and a plurality of first domino-RSL gates;the first domino-RSL gates comprise first to eighth transistors and a second inverter;the first and fifth transistors are PMOS transistors;the second to fourth and sixth to eighth transistors are NMOS transistors;the first to fourth transistors are sequentially connected in series by connecting their sources or drains;a power-supply voltage is applied to a source of the first transistor disposed at one end of the first to fourth transistors ...

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Номер записи: 53
30-05-2013 дата публикации

SEMICONDUCTOR DEVICE HAVING PLURAL SELECTION LINES

Номер: US20130135947A1
Автор: Noguchi Hidekazu
Принадлежит: ELPIDA MEMORY, INC.

The semiconductor device includes a plurality of word lines classified into a plurality of groups and a selection circuit for selecting a word line according to an address. The selection circuit has a level shifter arranged for each of the groups. The address includes a first address for selecting any of the groups and a second address for selecting a word line in the selected group. The selection circuit selects a word line by allowing supply of active potential for word line by the level shifter of a group selected by the first address and further allowing supply of the active potential to the word line selected by the second address out of a plurality of word lines belonging to the selected group. 1. A semiconductor device comprising:a plurality of circuit sets each including a plurality of drive circuits;a plurality of selection circuits each assigned to an associated one of the circuit sets such that each of the selection circuits are coupled in common to the driver circuits included in the associated one of the circuit sets; anda plurality of selection lines, whereinone of the selection circuits selected by a first signal supplies an active potential to a first output node thereof, andeach of the drive circuits includes a first transistor coupled between an associated one of the selection lines and the first output node of the associated one of the selection circuits, the first transistor having a control electrode supplied with a second signal that id different from the first signal.2. The semiconductor device as claimed in claim 1 , whereinthe first signal includes a plurality of address bits each taking one of first and second potentials,the other of the selection circuits that are not selected by the first signal supplies an inactive potential to the first output node thereof, anda first voltage between the first and second potentials is different from a second voltage between the active potential and the inactive potential.3. The semiconductor device as ...

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Номер записи: 54
06-06-2013 дата публикации

HIGH DENSITY SEMICONDUCTOR MEMORY DEVICES

Номер: US20130141965A1
Автор: KANG Youngmin, Lee Hyunju, Lee Jaekyu
Принадлежит:

High density semiconductor memory devices are provided. The device may include a cell array region including a lower structure, an upper structure, and a selection structure, the selection structure being interposed between the lower and upper structures and including word lines, and a decoding circuit controlling voltages applied to the word lines. The decoding circuit may be configured to apply a first voltage to a pair of the word lines adjacent to each other and to apply a second voltage different from the first voltage to the remaining ones of the word lines, in response to word line address information input thereto. 1. A semiconductor memory device , comprising:a cell array region comprising a lower structure, an upper structure, and a selection structure, the selection structure being interposed between the lower and upper structures and comprising a plurality of word lines; anda decoding circuit controlling voltages applied to the word lines,wherein the decoding circuit is configured to apply a first voltage to a pair of the word lines adjacent to each other and to apply a second voltage different from the first voltage to remaining ones of the word lines, in response to word line address information input thereto.2. The device of claim 1 , wherein the decoding circuit comprises a plurality of decoders claim 1 , each of which is configured to apply the first voltage to a corresponding one of the word lines claim 1 , if the word line address information input thereto is greater by one than or equal to address information of the each decoder claim 1 , and to apply the second voltage to the corresponding one of the word lines if the word line address information input thereto is less than the address information of the each decoder.3. The device of claim 1 , wherein the lower structure comprises a semiconductor substrate and a lower doped region provided above the semiconductor substrate claim 1 , and the selection structure further comprises a plurality of ...

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Номер записи: 55
06-06-2013 дата публикации

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR CONTROLLING THE SAME

Номер: US20130141975A1
Автор: JEONG Ji Kyung, KIM Jee Yul
Принадлежит: SK HYNIX INC.

A semiconductor memory device capable of reducing the size of a NAND flash memory device includes a latch unit configured to store a bad block address, a comparator configured to compare the bad block address with an access address so as to output a bad-block detection signal, and a bad block controller configured to sequentially output a plurality of bad block pulses corresponding to the bad-block detection signal during a predetermined period in response to a plurality of bad-block flag signals that are sequentially activated. 1. A semiconductor memory device comprising:a memory cell array including a plurality of planes, each plane including a plurality of blocks;a bad block detector configured to determine whether each of input addresses for accessing corresponding blocks of the plurality of planes corresponds to any of bad block addresses and sequentially output a plurality of bad-block pulses showing the determination results according to an input sequence of the input addresses, a bad block address being an address for accessing a block determined as a bad block; anda block selector configured to receive the plurality of bad-block pulses and select the corresponding blocks of the plurality of planes in response to the plurality of bad-block pulses, respectively.2. The semiconductor memory device of claim 1 , wherein the bad block detector comprises:a latch unit configured to store the bad block addresses;a comparator configured to compare the bad block addresses with each of the input addresses to output a bad-block detection signal; anda bad block controller configured to sequentially output the plurality of bad-block pulses corresponding to the bad-block detection signal in response to a plurality of bad-block flag signals that are sequentially activated according to the input sequence of the input addresses,wherein the plurality of bad-block flag signals corresponds to the plurality of planes, respectively.3. The semiconductor memory device according to ...

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Номер записи: 56
06-06-2013 дата публикации

SEMICONDUCTOR INTEGRATED CIRCUIT

Номер: US20130141999A1
Автор: NATSUME Hidetaka, Takahashi Hiroyuki
Принадлежит: RENESAS ELECTRONICS CORPORATION

A semiconductor integrated circuit according to one aspect of the present invention may includes a plurality of driving circuits to drive a respective plurality of word lines with either a first voltage supplied from a first power supply or a second voltage supplied from a second power supply in accordance with a control signal, and a plurality of gate transistors in each of which a gate is connected to one of the plurality of word lines, and a connection state between a storage node and a bit line is changed based on the voltage provided to the word line connected to the gate. In the semiconductor integrated circuit, a gate oxide film of each of the plurality of gate transistors is thinner than a gate oxide film of each of transistors constituting the plurality of driving circuits. 1. A semiconductor integrated circuit , comprising:a memory cell that includes a gate transistor;a word line that is connected to a gate of the gate transistor;a bit line that is connected to the memory cell; anda driving circuit that drives the word line, and includes a transistor that has a gate oxide film thicker than a gate oxide film of the gate transistor,wherein a range of voltage between the gate and back-gate of the gate transistor is larger than a voltage range of the bit line.2. The semiconductor integrated circuit according to claim 1 , wherein a voltage difference between the gate and back-gate of the gate transistor in read mode is larger than the voltage range of the bit line.3. The semiconductor integrated circuit according to claim 1 , further comprises:a control circuit that controls writing data to the memory cell or reading data from the memory cell,wherein the range of voltage between the gate and back-gate of the gate transistor is larger than a range of voltage between a power supply voltage and a ground voltage supplied to the control circuit.4. The semiconductor integrated circuit according to claim 3 , wherein a gate oxide film of a transistor constituting the ...

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Номер записи: 57
06-06-2013 дата публикации

Semiconductor Memory Apparatus

Номер: US20130142002A1
Автор: Kim Jong Woo, Lee Sang Don, Shim Sung Bo
Принадлежит: HYNIX SEMICONDUCTOR INC.

A semiconductor memory apparatus comprises first and second memory blocks each comprising semiconductor elements coupled to first and second local line groups, a first switching circuit configured to couple a first global line group to the first local line group of the first memory block in response to a block selection signal, a second switching circuit configured to couple a second global line group to the second local line groups of the first and second memory blocks in response to the block selection signal, and a third switching circuit configured to couple the first global line group to the first local line group of the second memory block in response to the block selection signal. 1. A semiconductor memory apparatus , comprising:a memory cell array comprising a plurality of memory blocks classified into a plurality of block groups;a first subdecoder configured to output a first selection signal for outputting one of the block groups in response to an enable signal and first row address signals; anda second subdecoder configured to output a second selection signal or a third selection signal for selecting one of a pair of even and odd memory blocks from a block group, selected by the first subdecoder, in response to the first selection signal and a second row address signal.2. The semiconductor memory apparatus of claim 1 , wherein the first row address signals comprise:first signals generated by decoding a first block address signal used to classify the memory blocks into a plurality of first subblock groups;second signals generated by decoding a second block address signal used to classify the first subblock group into a plurality of second subblock groups; andthree signals selected one by one from among third signals generated by decoding a third block address signal used to classify the second subblock group into a plurality of third subblock groups,wherein the second row address signal comprises two fourth signals for selecting a pair of even and odd ...

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Номер записи: 58
06-06-2013 дата публикации

DEVICES AND SYSTEM PROVIDING REDUCED QUANTITY OF INTERCONNECTIONS

Номер: US20130142004A1
Автор: Walker Robert M.
Принадлежит: MICRON TECHNOLOGY, INC.

Methods, devices and systems for reducing the quantity of external interconnections of a memory device are disclosed. Implementation of one such method, device and system includes inputting over an address bus a first portion of an address of a next row of memory cells to be activated. The first portion of the address of the next row of memory cells to be activated is embedded in a command related to the previously activated row of memory cells. The next row of memory cells is subsequently activated according to a concurrently received second portion of the address of the next row of memory cells also received over the address bus. The portioning of the address signals can reduce the width of the address bus and, therefore, the number of required respective external interconnections. 1. A memory device , comprising:at least two pages of memory cells; and receive a first portion of an address of a new page of memory cells in combination with a first command; and', 'receive a second portion of the address of the new page of memory cells in combination with a second command to activate the new page of memory cells with an address including the first portion and the second portion., 'a controller, an address bus, and a command bus configured to cooperatively2. The memory device of claim 1 , wherein the at least two pages of memory cells are addressable by a first number of address signals claim 1 , and wherein the address bus includes a second number of address signals claim 1 , which is less than the first number of address signals.3. The memory device of claim 1 , wherein the first command comprises a precharge command claim 1 , in response to which an open page of memory cells is at least partially closed.4. The memory device of claim 1 , wherein the first command comprises a refresh command to refresh at least one other page of memory cells.5. The memory device of claim 1 , further comprising a register to buffer the first portion of the address of the new page of ...

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Номер записи: 59
13-06-2013 дата публикации

Control scheme for 3d memory ic

Номер: US20130148402A1
Автор: Chien-yuan Chen, Meng-Fan Chang, Tsung-Hsien Huang, Wei-Cheng Wu
Принадлежит: National Tsing Hua University NTHU

The present invention discloses a control scheme for 3D memory IC that includes a master chip and at least one slave chip. The master chip includes a main memory core, a first local timer, an I/O buffer, a first pad and a second pad. The at least one slave chip is stacked with the master chip. Each of the slave chip includes a slave memory core, a second local timer and a third pad. A first TSV is coupled to the first pad and the third pad. A logic control circuit layer includes a logic control circuit and a fourth pad, and the logic control circuit is coupled to the fourth pad. A second TSV is coupled to the second pad and the fourth pad.

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Номер записи: 60
13-06-2013 дата публикации

MEMORY DEVICE

Номер: US20130148411A1
Автор: Atsumi Tomoaki, Okuda Takashi
Принадлежит: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

A memory device including first to fourth memory cell arrays and a driver circuit including a pair of bit line driver circuits and a pair of word line driver circuits is provided. The first to fourth memory cell arrays are overlap with the driver circuit. Each of the pair of bit line driver circuits and a plurality of bit lines are connected through connection points on an edge along the boundary between the first and second memory cell arrays or on an edge along the boundary between the third and fourth memory cell arrays. Each of the pair of word line driver circuits and a plurality of word lines are connected through second connection points on an edge along the boundary between the first and fourth memory cell arrays or on an edge along the boundary between the second and third memory cell arrays. 1. A memory device comprising:a driver circuit including a first bit line driver circuit, a second bit line driver circuit, a first word line driver circuit, and a second word line driver circuit;a first memory cell array including a first bit line and a first word line;a second memory cell array including a second bit line and a second word line;a third memory cell array including a third bit line and the second word line; anda fourth memory cell array including a fourth bit line and the first word line with the first memory cell array,wherein:each of the first to fourth memory cell arrays overlaps with the driver circuit,the first bit line driver circuit and the second bit line driver circuit are diagonally opposite to each other in the driver circuit,the first word line driver circuit and the second word line driver circuit are diagonally opposite to each other in driver circuit,the first and second bit line driver circuits and the first and second word line driver circuits are arranged so that in data writing, a signal is transmitted across the first bit line driver circuit toward a boundary between the first word line driver circuit and the first bit line driver ...

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Номер записи: 61
13-06-2013 дата публикации

LOCAL WORD LINE DRIVER

Номер: US20130148445A1
Автор: Chen Chung-Kuang, Chen Han-Sung, Hung Chun-Hsiung
Принадлежит:

A memory circuit with a word line driver and control circuitry is disclosed. The plurality of word line drivers are coupled to a plurality of word lines. Word line drivers include a CMOS inverter, which can have an input and an output, and a p-type transistor and an n-type transistor. The output of the CMOS inverter is coupled to one of the plurality of word lines. The control circuitry has multiple modes, including at least a first mode to discharge a particular word line of the plurality of word lines via a first discharge path such as at least a first transistor type of the CMOS inverter; and a second mode to discharge the particular word line of the plurality of word lines via a second discharge path such as at least the a second transistor type of the CMOS inverter. 1. A memory circuit , comprising:a plurality of word line drivers coupled to a plurality of word lines, word line drivers in the plurality including a CMOS inverter, the CMOS inverter having an input and an output coupled to a word line of the plurality of word lines; andcontrol circuitry having at least a first mode to discharge a particular word line of the plurality of word lines via at least a first transistor type of the CMOS inverter;the control circuitry having at least a second mode to discharge the particular word line of the plurality of word lines via at least a second transistor type of the CMOS inverter, the second transistor type different from the first transistor type,wherein, during a memory operation on a selected word line of the plurality of word lines, the control circuitry is configured to deselect the particular word line adjacent to the selected word line, via the second mode and not the first mode.2. The memory circuit of claim 1 , wherein the CMOS inverter includes a p-type transistor and an n-type transistor claim 1 , the first transistor type is a p-type transistor claim 1 , and the second transistor type is an n-type transistor.3. The memory circuit of claim 2 , wherein ...

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Номер записи: 62
13-06-2013 дата публикации

MEMORY SYSTEM AND DATA TRANSMISSION METHOD

Номер: US20130148448A1
Автор: MATSUI Yoshinori
Принадлежит: ELPIDA MEMORY, INC.

A memory system of a high-speed operation can be realized by reducing an influence of reflection signals etc. caused by branching and impedance mismatching in various wirings between a memory controller and a memory module, and an influence due to transmission delays of data, command/address, and clocks in the memory module. To this end, a memory system comprises a memory controller and a memory module mounted with DRAMs. A buffer is mounted on the memory module. The buffer and the memory controller are connected to each other via data wiring, command/address wiring, and clock wiring. The DRAMs and the buffer on the memory module are connected to each other via internal data wiring, internal command/address wiring, and internal cock wiring. The data wiring, the command/address wiring, and the clock wiring may be connected to buffers of other memory modules in cascade. Between the DRAMs and the buffer on the memory module, high-speed data transmission is implemented using data phase signals synchronous with clocks. 1. A memory system comprising:a substrate;a plurality of memory chips mounted over the substrate, the plurality of memory chips receiving a first signal and a second signal;a memory buffer mounted over the substrate, the memory buffer including a detection circuit which detects a skew between the first signal and the second signal, and the memory buffer including an adjustment circuit which adjusts a relationship between the first signal and the second signal based on the skew.a first wiring configured to commonly couple each of the plurality of memory chips for transferring the first signal to the each of the plurality of memory chips in common; anda plurality of second wirings corresponding with the plurality of memory chips, each first end of the plurality of second wirings configured to couple to an associated one of the plurality of memory chips independently for transferring the second signal to an associated one of the plurality of memory chips.2. ...

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Номер записи: 63
13-06-2013 дата публикации

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME

Номер: US20130148449A1
Автор: KIM Kwi-Dong, Kim Sung-Ho, PARK Mun-Phil
Принадлежит: SK HYNIX INC.

A semiconductor memory device includes first and second write driving blocks to perform a data write operation on first and second memory banks in response to first and second bank strobe signals, respectively, and a common input driving block to transmit data to the first and second write driving blocks through a common data line in response to access information of the first and second memory banks. 14-. (canceled)5. A semiconductor memory device , comprising:first and second memory banks each of which includes a plurality of sub-memory banks corresponding to data width option information;a plurality of write driving blocks each of which performs a data write operation on each of the sub-memory banks in response to a first or second bank strobe signal;a control signal generating block to generate a plurality of input control signals dependent on access information of the first and second memory banks the data width option information; anda plurality of common input driving blocks each of which transmits data through a common data line to a write driving block, among the plurality of write driving blocks, for each of the first and second memory banks, wherein the plurality of common input driving blocks are activated in response to the plurality of input control signals.6. The semiconductor memory device of claim 5 , wherein enable periods of the plurality of input control signals are defined by enable periods of the first and second bank strobe signals.7. The semiconductor memory device of claim 5 , wherein the first and second memory banks are stacked with each other.8. The semiconductor memory device of claim 5 , wherein the access information of the first and second memory banks corresponds to the first and second bank strobe signals.9. The semiconductor memory device of claim 5 , wherein the common data lines are disposed to cross one of the first and second memory banks.10. The semiconductor memory device of claim 5 , further comprising an activation signal ...

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Номер записи: 64
20-06-2013 дата публикации

MEMORY MACRO CONFIGURATION AND METHOD

Номер: US20130155785A1
Автор: ROMANOVSKYY Sergiy
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

A memory macro comprises a plurality of memory array segments, each having a predetermined number of data inputs and outputs. A segment decoder circuit is configured to: receive a first value indicating a number of memory partitions among which the memory array segments are to be divided, and output a plurality of signals for selectively activating one or more of the plurality of memory array segments to be accessed based on the first value. A plurality of output drivers are coupled to the segment decoder circuit and to respective ones of the outputs. The plurality of output drivers are configured to selectively output data from the respective outputs of each of the respective activated memory array segments. 1. A memory macro , comprising:a plurality of memory array segments, each having a predetermined number of data outputs; receive a first value, and', 'output a plurality of signals based on the first value; and, 'a segment decoder circuit configured toa plurality of output drivers coupled to the segment decoder circuit and to respective ones of the outputs.2. The memory macro of claim 1 , wherein the plurality of memory array segments are configured so that ones of the memory array segments which are not selected by the plurality of signals are placed in an inactive state.3. The memory macro of claim 1 , wherein each of the output drivers includes a tri-state buffer.4. The memory macro of claim 3 , wherein the output drivers are configured to respond to the plurality of signals claim 3 , so that each output driver coupled to one of the outputs of one of the plurality of memory array segments that is not selected is placed in a high impedance state.5. The memory macro of claim 1 , wherein the memory macro is an embedded dynamic random access memory macro.6. The memory macro of claim 1 , wherein the segment decoder is configured to generate the plurality of signals so that a number of memory array segments activated at a given time is equal to a total number of ...

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Номер записи: 65
20-06-2013 дата публикации

Memory access control system and method

Номер: US20130155793A1
Автор: Russell Schreiber, Vikram Suresh
Принадлежит: ATI TECHNOLOGIES ULC

The present disclosure relates to a method and system for controlling memory access. In particular, a method for controlling memory access includes, in response to receiving a write request operative to write data to at least one memory cell of a plurality of memory cells, increasing a word line voltage above a nominal level after a predetermined delay following the receipt of the write request. A disclosed system includes a word line driver operative to increase a word line voltage above a nominal level during a write access after a predetermined delay in response to a write request.

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Номер записи: 66
27-06-2013 дата публикации

IMAGE PROCESSING DEVICE AND IMAGE PROCESSING METHOD

Номер: US20130163893A1
Автор: Hosaka Kazuhisa
Принадлежит: SONY CORPORATION

An image processing device includes: a significant digit number encoding unit designating a set of a predetermined number of coefficient data items generated from image data. The maximum number of significant digits of coefficient data for each set every cycle is obtained, and information regarding the maximum number is encoded. A zero run encoding unit encodes zero runs formed by sets that include only coefficient data whose value is 0 at a cycle that differs from the cycle of encoding the significant digit number. The absolute value for the maximum number of significant digits other than the zero runs is extracted and encoded. The positive or negative sign of each coefficient data item whose absolute value is not 0 in a set at a cycle that differs from a cycle in relation to coefficient data other than the zero runs is encoded. 1. An image processing device comprising:a significant digit number encoding unit that designates a predetermined number of coefficient data items of a plurality of coefficient data items generated from image data as a set, obtains the maximum number of significant digits which is the number of significant digits of coefficient data having the greatest absolute value in relation to each set every cycle, and encodes information regarding the maximum number of significant digits;a zero run encoding unit that encodes zero runs formed by sets including only coefficient data whose value is 0 at a cycle different from a cycle of encoding of the significant digit number encoding unit;an absolute value encoding unit that extracts an absolute value for the maximum number of significant digits of each coefficient data item in a set which has been encoded by the significant digit number encoding unit in relation to coefficient data other than the zero runs, and encodes the absolute value at a cycle different from a cycle of encoding of the significant digit number encoding unit; anda sign encoding unit that encodes a positive or negative sign of each ...

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Номер записи: 67
27-06-2013 дата публикации

MEMORY CIRCUIT INCORPORATING RADIATION-HARDENED MEMORY SCRUB ENGINE

Номер: US20130166990A1
Автор: Gifford David R., Lowther Rex E., Morris Wesley H.
Принадлежит:

An example integrated circuit includes a first memory array including a first plurality of data groups, each such data group including a respective plurality of data bits. The integrated circuit also includes a first error detection and correction (EDAC) circuit configured to detect and correct an error in a data group read from the first memory array. The integrated circuit also includes a first scrub circuit configured to access in a sequence each of the first plurality of data groups to correct any detected errors therein. Both the first EDAC circuit and the first scrub circuit include spatially redundant circuitry. The first EDAC circuit and the first scrub circuit may include buried guard ring (BGR) structures, and may include parasitic isolation device (PID) structures. The spatially redundant circuitry may include dual interlocked storage cell (DICE) circuits, and may include temporal filtering circuitry. 1. An integrated circuit comprising:a first memory array comprising a first plurality of data groups, each such data group including a respective plurality of data bits;a first error detection and correction (EDAC) circuit configured to detect and correct an error in a data group read from the first memory array, said first EDAC circuit comprising spatially redundant circuitry; anda first scrub circuit configured to access in a sequence each of the first plurality of data groups to correct any detected errors therein, said first scrub circuit comprising spatially redundant circuitry.2. The integrated circuit as recited in wherein:the first EDAC circuit and the first scrub circuit each includes buried guard ring (BGR) structures.3. The integrated circuit as recited in wherein:the first EDAC circuit and the first scrub circuit each includes parasitic isolation device (PID) structures.4. The integrated circuit as recited in wherein:the spatially redundant circuitry comprises dual interlocked storage cell (DICE) circuits.5. The integrated circuit as recited in ...

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Номер записи: 68
04-07-2013 дата публикации

DCT COMPRESSION USING GOLOMB-RICE CODING

Номер: US20130170748A1
Автор: Thyagarajan Kadayam S.
Принадлежит: QUALCOMM INCORPORATED

An apparatus and method for encoding quantized frequency represented data, the data comprising zero and non-zero represented data is claimed. For zero represented data, a zero run length is determined. A Golomb parameter is determined as a function of the zero run length. A quotient is encoded as a function of the zero run length and the Golomb parameter. A remainder is encoded as a function of the zero run length, the Golomb parameter and the quotient. The coded quotient and the coded remainder are concatenated. For non-zero represented data, the nonzero data is encoded as a function of the non-zero data value and the sign of the non-zero data value. 2. The computer readable medium set forth in claim 1 , wherein run-length coding is a function of the cumulative value and the corresponding number of times that a particular value occurs.3. The computer readable medium set forth in claim 1 , wherein scaling further comprises providing a frequency weighted mask to said sub-blocks of pixel data claim 1 , such that the frequency weighting mask provides emphasis to the portions of the image that the human visual system is more sensitive claim 1 , and provides less emphasis to the portions of the image that the human visual system is less sensitive.4. The computer readable medium set forth in claim 1 , wherein transforming further comprises performing a Discrete Cosine Transform.5. The computer readable medium set forth in claim 1 , wherein transforming further comprises performing a Discrete Cosine Transform followed by a Differential Quad-tree Transform.7. The processor set forth in claim 6 , wherein the processor run-length codes as a function of the cumulative value and the corresponding number of times that a particular value occurs.8. The processor set forth in claim 6 , wherein the processor scales by providing a frequency weighted mask to said sub-blocks of pixel data claim 6 , such that the frequency weighting mask provides emphasis to the portions of the image ...

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Номер записи: 69
04-07-2013 дата публикации

DOWNSIZING AN ENCODED IMAGE

Номер: US20130170764A1
Автор: Carmel Sharon, Gill Dror, Shoham Tamar
Принадлежит: I.C.V.T LTD.

There is provided a system, a computer program product, program storage device readable by machine, and a method of downsizing an input disjoint block level encoded image. According to examples of the presently disclosed subject matter, the method can include calculating a DCT downsize ratio for downsizing the input image in a DCT domain according to a target downsize ratio and according to a size of a DCT transform length associated with the input image; adapting an I-DCT according to the DCT domain downsize ratios; performing the adapted I-DCT; providing an intermediate image as output of a DCT domain process; and applying a pixel domain interpolation to the intermediate image according to dimensions of the intermediate image and according to dimensions of the target image. 1. A method of downsizing an input disjoint block level encoded image , comprising:calculating a DCT downsize ratio for downsizing the input image in a DCT domain according to a target downsize ratio and according to a size of a DCT transform length associated with the input image;adapting an I-DCT according to the DCT domain downsize ratios;performing the adapted I-DCT;providing an intermediate image as output of a DCT domain process; andapplying a pixel domain interpolation to the intermediate image according to dimensions of the intermediate image and according to dimensions of the target image.2. The method according to claim 1 , wherein said calculating comprises computing the DCT domain downsize ratio based on a length of the DCT transform and based on the target downsize ratio claim 1 , for each dimension of the input image.3. The method according to claim 1 , wherein said adapting comprises adapting one or both of a horizontal inverse transform length and a vertical inverse transform length claim 1 , according to the calculated DCT domain downsize ratio.4. The method according to claim 1 , wherein said adapting comprises reducing one or both of a horizontal inverse transform length and ...

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Номер записи: 70
11-07-2013 дата публикации

METHOD FOR ACCESSING A FLASH MEMORY, AND ASSOCIATED FLASH MEMORY SYSTEM

Номер: US20130176785A1
Автор: Chen Chun-Yu, KUAN Chi-Chih
Принадлежит: Silicon Motion Inc.

A method for accessing a Flash memory and an associated Flash memory system are provided, where the Flash memory includes a plurality of blocks, each of the blocks includes a plurality of pages, and each of the pages includes a plurality of sectors. The method includes: receiving a page of data from a host; encoding a first portion of the page of data by a randomizer that operated under a first seed to generate a first encoded data; encoding a second portion of the page of data by the randomizer that operated under a second seed to generate a second encoded data, wherein the first seed is different from the second seed; and storing the first encoded data and the second encoded data to the Flash memory. An associated method and an associated Flash memory system are also provided. 1. A method for accessing a Flash memory , wherein the Flash memory comprises a plurality of blocks , each of the blocks comprises a plurality of pages , each of the pages comprises a plurality of sectors , and the method comprises:receiving a page of data from a host;encoding a first portion of the page of data by a randomizer that operated under a first seed to generate a first encoded data;encoding a second portion of the page of data by the randomizer that operated under a second seed to generate a second encoded data, wherein the first seed is different from the second seed; andstoring the first encoded data and the second encoded data to the Flash memory.2. The method of claim 1 , further comprising:storing the first encoded data and the second encoded data into different sectors of a first page of the Flash memory.3. The method of claim 1 , wherein the second seed is generated from the first seed.4. The method of claim 1 , further comprising:storing the first seed into the Flash memory.5. A method for accessing a Flash memory claim 1 , wherein the Flash memory comprises a plurality of blocks claim 1 , each of the blocks comprises a plurality of pages claim 1 , each of the pages ...

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Номер записи: 71
11-07-2013 дата публикации

MEMORY CONTROLLER HAVING A WRITE-TIMING CALIBRATION MODE

Номер: US20130176800A1
Автор: Ware Frederick A.
Принадлежит: RAMBUS INC.

A memory controller outputs address bits and a first timing signal to a DRAM, each address bit being associated with an edge of the first timing signal and the first timing signal requiring a first propagation delay time to propagate to the DRAM. The memory controller further outputs write data bits and a second timing signal to the DRAM in association with the address bits, each of the write data bits being associated with an edge of the second timing signal and the second timing signal requiring a second propagation delay time to propagate to the DRAM. The memory controller includes a plurality of series-coupled delay elements to provide respective, differently-delayed internal delayed timing signals and a multiplexer to select one of the delayed timing signals to be output as the second timing signal based on a difference between the first propagation delay time and the second propagation delay time. 120-. (canceled)21. A memory controller comprising: address information indicating a storage address for first write data; and', 'a first timing signal to time reception of the address information within a first dynamic random access memory (DRAM), the first timing signal requiring a first propagation time to propagate from the memory controller to the first DRAM;, 'first circuitry to output a chain of delay elements to generate a plurality of delayed timing signals, and', 'first select circuitry to select, as a transmission timing source of the second timing signal, a first one of the delayed timing signals, wherein the memory controller is operable in a calibration mode to enable the first select circuitry to select the first one of the delayed timing signals to time transmission of the second timing signal, wherein, during the calibration mode, the second circuitry outputs multiple delayed versions of the timing signals and selects, as the first one of the delayed timing signals, one of the delayed timing signals that compensates for mismatch between the first and ...

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Номер записи: 72
11-07-2013 дата публикации

SELF CLOCKING FOR DATA EXTRACTION

Номер: US20130176809A1
Автор: Swoboda Gary L.
Принадлежит: TEXAS INSTRUMENTS INCORPORATED

A self clocking data extraction method is shown that is tolerant of timing jitter, data skew and the presence of multiple edges per data bit. The data is sampled when the following criterion are met: There is at least one edge across any track (the clock assures this criteria is met), followed by no edges in any track for a defined period of time (T), and all edge activity must occur in a period of time less than T (to keep from detecting false samples). This method enables the handling of trace data signals with poor electrical characteristics that can not be recorded by methods known in the prior art. 1. A method of data extraction of data in a plurality of signal channels , comprising the steps of:for each signal channel taking a group of samples distributed throughout a bit period interval; determining an edge in said signal channel at said sample if said sample differs from said prior sample, and', 'determining no edge in said signal channel at said sample if said sample equals said prior sample;, 'for each signal channel comparing each sample of said group of samples with a prior sample'} (1) a sample during which an edge is determined in at least one signal channel, followed by', '(2) a second predetermined time Y during which no edge is determined for any signal channel., 'extracting data from all signal channels at a sample of said group of samples following detection of'}2. The method of claim 1 , wherein:said first predetermined time X is a first number of sampled of said group of samples.3. The method of claim 1 , wherein:said second predetermined time Y is a second number of sampled of said group of samples.4. The method of claim 1 , wherein:said group of samples is m samples n through n+m−1;sample data [(m/2)−1:00] is used to extract data within a window A; ansample data [m−1;m/2] is used to extract data within a window B.5. The method of claim 4 , wherein: calculating the logical AND of data [n] with a delayed version of sample value [n], and', ' ...

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Номер записи: 73
11-07-2013 дата публикации

IMAGE ENCODER AND IMAGE DECODER

Номер: US20130177240A1
Автор: MOTRA Ajit, Thoma Herbert
Принадлежит: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.

An image encoder includes an extreme value determiner, a floating point-to-integer converter and an encoder. The extreme value determiner determines minimal and maximal values of a floating point image value of each pixel of a part of an image, an image or a group of images. The floating point-to-integer converter maps the floating point image value of each pixel to an integer image value. The minimal floating point image value is mapped to a minimal integer image value of a predefined range of integer image values and the maximal floating point image value is mapped to a maximal integer image value of the predefined range of integer image values. The encoder encodes the integer image value of each pixel to obtain and provide encoded image data of the part of the image, the image or the group of images. 1. Image encoder comprising:an extreme value determiner configured to determine a minimal value and a maximal value of a floating point image value of each pixel of a part of an image, an image or a group of images, wherein the floating point image value of each pixel represents a luminance value of each pixel;a floating point-to-integer converter configured to map the floating point image value of each pixel to an integer image value, wherein each integer image value lies in a predefined range of integer image values, wherein the determined minimal floating point image value is mapped to a minimal integer image value of the predefined range of integer image values and the determined maximal floating point image value is mapped to a maximal integer image value of the predefined range of integer image values,wherein the floating point-to-integer converter is configured to calculate at least one transform parameter for the part of the image, the image or the group of images based on the determined minimal floating point value and the determined maximal floating point value, wherein the floating point value of each pixel of the part of the image, the image or the group ...

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Номер записи: 74
18-07-2013 дата публикации

SEMICONDUCTOR MEMORY DEVICES HAVING INTERNAL CLOCK SIGNALS AND MEMORY SYSTEMS INCLUDING SUCH MEMORY DEVICES

Номер: US20130182524A1
Автор: Cho Young Chul, Eom Yoon Joo, JEON Young Jin
Принадлежит:

A semiconductor memory device has a clock input buffer that is turned ‘on’ or ‘off’ in response to a first control signal. The clock input buffer is configured to buffer an external clock signal in order to output a buffered clock signal. The memory device further includes an internal clock generator that is configured to generate an internal clock signal in response to the buffered clock signal. The generation of the internal clock signal is started in response to a second control signal. 1. A semiconductor memory device comprising:a clock input buffer that is turned ‘on’ or ‘off’ in response to a first control signal, the clock input buffer configured to buffer a clock signal in order to output a buffered clock signal; andan internal clock generator that is configured to generate an internal clock signal in response to the buffered clock signal, wherein the generation of the internal clock signal is started in response to a second control signal.2. The semiconductor memory device of claim 1 , wherein the first control signal is a clock enable signal claim 1 , the second control signal is a chip selection signal claim 1 , and wherein the internal clock generator generates the internal clock signal by starting a division of the buffered clock signal in response to a first pulse of the chip selection signal being input to the internal clock generator.3. The semiconductor memory device of claim 2 , wherein a pulse width of the first pulse of the chip selection signal is greater than one clock cycle of the clock signal.4. The semiconductor memory device of claim 1 , wherein claim 1 , the internal clock generator is configured to start to generate the internal clock signal by dividing the buffered clock signal in response to the first pulse of the second control signal being input to the internal clock generator while the first control signal is activated.5. The semiconductor memory device of claim 1 , wherein the clock input buffer buffers the clock signal in response ...

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Номер записи: 75
01-08-2013 дата публикации

SEMICONDUCTOR DEVICE INCLUDING SEMICONDUCTOR MEMORY CIRCUIT

Номер: US20130194878A1
Автор: NAKAMURA Takashi
Принадлежит: SEIKO INSTRUMENTS INC.

The semiconductor device including a memory circuit is configured to include a mode switching circuit additionally provided with a data comparison circuit which detects that a serial signal supplied to an input terminal for communication and a serial signal supplied to an input terminal used for a purpose other than communication are reversed from each other, a decoder circuit which detects that a serial signal carries predetermined data and which outputs a detection signal, a control signal generating circuit which generates a control signal, and a circuit which outputs a signal for switching to a test mode on the basis of the signals. 1. A semiconductor device including a semiconductor memory circuit , which has a clock input terminal to which a clock signal is supplied and a first input terminal for communication to which a data signal is supplied , and a mode switching circuit comprising:a data comparison circuit which detects that data signals having phases that are reversed from each other have been supplied to the first input terminal and a second input terminal;a first decoder circuit which detects that a first data signal of the data signals has been received and outputs a detection signal in combination with a detection signal of the data comparison circuit;a second decoder circuit which detects that a second data signal of the data signals has been received and outputs a detection signal in combination with the detection signal of the data comparison circuit and the detection signal of the first decoder circuit; anda circuit which outputs a switching signal for shifting to a test mode upon receipt of the detection signals from the first decoder circuit and the second decoder circuit.2. The semiconductor device including a semiconductor memory circuit according to claim 1 , further comprising:a control signal generating circuit which outputs a control signal,wherein the detection signals of the first decoder circuit and the second decoder circuit and the ...

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Номер записи: 76
08-08-2013 дата публикации

ELECTRONIC APPARATUS, DRAM CONTROLLER, AND DRAM

Номер: US20130201779A1
Автор: WEN Chih-Chiang
Принадлежит: MEDIATEK INC.

The invention provides an electronic apparatus. The electronic apparatus includes a Dynamic Random Access Memory (DRAM) and a DRAM controller. The DRAM receives at least one control and address signal and a clock signal, delays the clock signal by a predetermined value to obtain a delayed clock signal, samples the control and address signal according to the clock signal to obtain a first sample signal, samples the control and address signal according to the delayed clock signal to obtain a second sample signal, and compares the first sample signal with the second sample signal to obtain a status signal. The DRAM controller sends the control and address signal and the clock signal to the DRAM, receives the status signal from the DRAM, and adjusts a phase difference between the clock signal and the control and address signal according to the status signal. 1. An electronic apparatus , comprising:a Dynamic Random Access Memory (DRAM), receiving at least one control and address signal and a clock signal, delaying the clock signal by a predetermined value to obtain a delayed clock signal, sampling the control and address signal according to the clock signal to obtain a first sample signal, sampling the control and address signal according to the delayed clock signal to obtain a second sample signal, and comparing the first sample signal with the second sample signal to obtain a status signal; anda DRAM controller, sending the at least one control and address signal and the clock signal to the DRAM, receiving the status signal from the DRAM, and adjusting a phase difference between the clock signal and the at least one control and address signal according to the status signal.2. The electronic apparatus as claimed in claim 1 , wherein the DRAM comprises:a delay unit, delaying the clock signal by the predetermined value to obtain the delayed clock signal;a first latch, sampling the control and address signal according to the clock signal to obtain the first sample signal;a ...

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Номер записи: 77
15-08-2013 дата публикации

LATENCY CONTROL CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE COMPRISING SAME

Номер: US20130208546A1
Автор: BAE Seung-Jun, KIM Hye-Ran, KIM Si-hong, SEOL Ho-Seok
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A latency control circuit is configured to delay a read information signal in response to a CAS latency signal and an internal clock signal to generate a delayed read information signal, and is further configured to generate a latency control signal based on the delayed read information signal in response to a plurality of sampling control signals and a plurality of transfer control signals. 1. A latency control circuit , comprising:a sampling clock signal generating circuit configured to generate a plurality of sampling clock signals having different phases from each other based on an internal clock signal;a multiplexer configured to multiplex the sampling clock signals in response to a column address strobe (CAS) latency signal to generate a plurality of sampling control signals;a transfer control signal generating circuit configured to generate a plurality of transfer control signals having different phases from each other based on an output clock signal; anda latency control signal generating circuit configured to delay a read information signal in response to the CAS latency signal and the internal clock signal to generate a delayed read information signal, and further configured to generate a latency control signal based on the delayed read information signal in response to the sampling control signals and the transfer control signals.2. The latency control circuit of claim 1 , wherein the sampling clock signals are configured to have a phase difference of an integer multiple of a clock cycle of the internal clock signal.3. The latency control circuit of claim 2 , wherein the sampling clock signal generating circuit comprises:a shift register synchronized with the internal clock signal and configured to generate the sampling clock signals that are sequentially enabled with a delay time of the clock cycle.4. The latency control circuit of claim 1 , wherein the latency control signal generating circuit comprises:a delay circuit configured to delay the read ...

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Номер записи: 78
15-08-2013 дата публикации

Phase interpolators and push-pull buffers

Номер: US20130208549A1
Автор: Gregory A. King
Принадлежит: Micron Technology Inc

Interpolator systems are described utilizing one or more push-pull buffers to generate output clock signals that may be provided as inputs to a phase interpolator. The more linear slope on the output of the push-pull buffer may improve the linearity of a phase interpolator using the clock signals output from the push-pull buffers.

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Номер записи: 79
15-08-2013 дата публикации

Power-On-Reset (POR) Circuits for Resetting Memory Devices, and Related Circuits, Systems, and Methods

Номер: US20130208556A1
Автор: Ganesan Balachander, Park Alex Dongkyu, Terzioglu Esin, Yoon Sei Seung
Принадлежит: QUALCOMM INCORPORATED

Power-on-reset (POR) circuits for resetting memory devices, and related circuits, systems, and methods are disclosed. In one embodiment, a POR circuit is provided. The POR circuit is configured to receive as input, a plurality of decoded address outputs from at least one memory decoding device. The POR circuit is further configured to generate a POR reset if any of the plurality of decoded address outputs are active. As a result, memory decoding device latches can be reset to a known, default condition to avoid causing an unintentional word line selection in the memory during power-on state before an external reset is available. Because the POR circuit can generate the POR reset without need of an external reset, the memory decoding devices can be reset quickly to allow for quicker availability of memory after a power-on condition. 1. A power-on-reset (POR) circuit for resetting at least one memory decoding device as a result of a power-on condition , the POR circuit configured to:receive as input, a plurality of decoded address outputs from at least one memory decoding device; andgenerate a POR reset if any of the plurality of decoded address outputs are active.2. The POR circuit of claim 1 , wherein the at least one memory decoding device is comprised of at least one memory decoding latch or at least one memory pre-decoding latch.3. The POR circuit of claim 1 , wherein the at least one memory decoding device is comprised of at least one pulsed latch.4. The POR circuit of claim 1 , further comprising an activity detector configured to:receive as input, the plurality of decoded address outputs from the at least one memory decoding device;determine from the plurality of decoded address outputs if any of the plurality of decoded address outputs are active; andgenerate an activity indication indicating if any of the plurality of decoded address outputs are active.5. The POR circuit of claim 1 , further comprising a delay circuit configured to:receive the activity ...

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Номер записи: 80
15-08-2013 дата публикации

Techniques for Storing Data and Tags in Different Memory Arrays

Номер: US20130212331A1
Автор: Frederick A. Ware
Принадлежит: RAMBUS INC

A memory controller includes logic circuitry to generate a first data address identifying a location in a first external memory array for storing first data, a first tag address identifying a location in a second external memory array for storing a first tag, a second data address identifying a location in the second external memory array for storing second data, and a second tag address identifying a location in the first external memory array for storing a second tag. The memory controller includes an interface that transfers the first data address and the first tag address for a first set of memory operations in the first and the second external memory arrays. The interface transfers the second data address and the second tag address for a second set of memory operations in the first and the second external memory arrays.

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Номер записи: 81
22-08-2013 дата публикации

Circuit for driving word line

Номер: US20130215697A1
Автор: Byeong Chan CHOI, Gyung Tae Kim
Принадлежит: SK hynix Inc

A word line driving circuit includes, inter alia: a word line driving signal generator, a main word line enable signal controller, and a sub word line driver. The word line driving signal generator activates a word line boosting signal, a pre-main word line enable signal, and a word line off signal in response to an active signal and a precharge signal. The main word line enable signal controller receives the pre-main word line enable signal and outputs it as the main word line enable signal in response to a main word line test mode signal. The sub word line driver uses the word line boosting signal as a driving voltage, and drives a sub word line in response to the main word line enable signal and the word line off signal.

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Номер записи: 82
22-08-2013 дата публикации

IMAGE PROCESSING DEVICE AND IMAGE PROCESSING METHOD

Номер: US20130216149A1
Автор: Sato Kazushi
Принадлежит: SONY CORPORATION

An image processing device including a selection section configured to select, from a plurality of transform units with different sizes, a transform unit used for inverse orthogonal transformation of image data to be decoded, a generation section configured to generate, from a first quantization matrix corresponding to a transform unit for a first size, a second quantization matrix corresponding to a transform unit for a second size from a first quantization matrix corresponding to a transform unit for a first size, and an inverse quantization section configured to inversely quantize transform coefficient data for the image data using the second quantization matrix generated by the generation section when the selection section selects the transform unit for the second size. 114-. (canceled)15: An image processing device comprising:a generation section configured to generate, from a first quantization matrix corresponding to a transform unit for a first size, a second quantization matrix corresponding to a transform unit for a second size larger than the first size; andan inverse quantization section configured to inversely quantize transform coefficient data for image data using the second quantization matrix generated by the generation section when a transform unit for the second size is used for inverse orthogonal transformation.16: The image processing device according to claim 15 , wherein the generation section generates the second quantization matrix by duplicating elements of the first quantization matrix.17: The image processing device according to claim 16 , wherein the generation section generates the second quantization matrix by duplicating one of a first element and a second element as an element between the first element and the second element adjacent to each other in the first quantization matrix.18: The image processing device according to claim 15 , wherein the generation section generates the second quantization matrix by linearly interpolating an ...

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Номер записи: 83
29-08-2013 дата публикации

SEMICONDUCTOR MEMORY DEVICE, METHOD OF CONTROLLING READ PREAMBLE SIGNAL THEREOF, AND DATA TRANSMISSION SYSTEM

Номер: US20130223167A1
Автор: KOSHIZUKA Atsuo
Принадлежит: ELPIDA MEMORY, INC.

A system, includes a controller including a plurality of first external terminals configured to supply a command, a clock signal and an address, and communicate a data, and communicate a strobe signal related to the data, and a semiconductor memory device including a plurality of second external terminals corresponding to the plurality of first external terminals, one of the plurality of first external terminals and one of the plurality of second external terminals transferring an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data, 1. A system , comprising:a controller comprising a plurality of first external terminals configured to supply a command and an address, to communicate data, and to communicate a strobe signal related to the data; anda semiconductor memory device comprising a plurality of second external terminals corresponding to the plurality of first external terminals,the semiconductor memory device further comprising a system clock external terminal provided to receive a system clock with a first frequency or a second frequency,one of the plurality of first external terminals and one of the plurality of second external terminals transferring an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data, the length of the preamble including first and second lengths corresponding to the first and second frequencies, respectively.2. The system as claimed in claim 1 , the device further comprising:a data strobe signal output control circuit configured to output the preamble of the strobe signal and then output a toggle transition of the data strobe signal to communicate the data.3. The system as claimed in claim 1 , wherein the more the frequency of the system clock is increased claim 1 , the longer the length of the preamble is.4. The system as claimed in claim 3 , wherein the larger a CAS latency is claim 3 , ...

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Номер записи: 84
05-09-2013 дата публикации

SEMICONDUCTOR MEMORY DEVICE AND ACCESS METHOD THEREOF

Номер: US20130229885A1
Автор: KIM Dae-hyun, KIM Hye-Ran, KIM Hyun-Jin, KIM Kyoung-Ho, Park Kwang-il
Принадлежит:

Example embodiments provide a semiconductor memory device that may include: a cell array arranged in pluralities of rows and columns; and a sense amplifier conducting writing and reading operations to the cell array in response to writing and reading commands in correspondence with an access time, which may be variable in period. The sense amplifier adjusts pulse widths of write-in and read-out data in accordance with a period of the access time. 1. (canceled)2. A method of accessing memory banks in a cell array , the cell array including a plurality of bank groups , wherein each bank group includes at least two banks , the method comprising:receiving a first command to access a first bank of a first bank group;receiving a second command to access a first bank of a second bank group; andreceiving a third command to access a second bank of the first bank group,wherein the third command is received after a first delay time from the received first command,the second command is received after a second delay time from the received first command, andwherein the first and second delay times are different.3. The method of claim 2 , wherein the first delay time is programmed by a mode register setting.4. The method of claim 2 , wherein the first delay time is a first command delay for accesses within a same bank group claim 2 , and the second delay time is a second command delay for accesses within different bank groups.5. The method of claim 2 , wherein the first delay time is greater than the second delay time.6. The method of claim 2 , wherein each of the first claim 2 , second and third commands is a write command or a read command.7. The method of claim 2 , wherein the first claim 2 , second or third command includes a column address strobe signal. This application is a continuation of U.S. application Ser. No. 13/360,093 filed on Jan. 27, 2012, which is a Continuation of U.S. Pat. No. 8,125,847, issued on Feb. 28, 2012, which claims priority to Korean Patent ...

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Номер записи: 85
05-09-2013 дата публикации

METHODS FOR ENCODING AND DECODING AN IMAGE, AND CORRESPONDING DEVICES

Номер: US20130230096A1
Автор: LASSERRE SEBASTIEN, LE LEANNEC Fabrice
Принадлежит: CANON KABUSHIKI KAISHA

A method for encoding at least one frame comprising a plurality of blocks of pixels, each block having a block type, includes the steps of: 1. A method for encoding at least one frame comprising a plurality of blocks of pixels , each block having a block type , comprising the steps of:transforming pixel values for a block among said plurality of blocks into a set of coefficients each having a coefficient type, said block having a given block type;determining a block merit based on a predetermined frame merit and on a number of blocks of the given block type per area unit;determining an initial coefficient encoding merit for each coefficient type;selecting coefficients based, for each coefficient, on the initial encoding merit for said coefficient type and on said block merit;quantizing the selected coefficients into quantized symbols; andencoding the quantized symbols.2. An encoding method according to claim 1 , wherein the step of selecting coefficients includes selecting coefficients for which the initial encoding merit is greater than the block merit.3. An encoding method according to claim 1 , wherein determining the block merit includes multiplying the predetermined frame merit by the number of blocks of the given block type per area unit.4. An encoding method according to claim 1 , wherein determining an initial coefficient encoding merit for a given coefficient type includes estimating a ratio between a distortion variation provided by encoding a coefficient having the given type and a rate increase resulting from encoding said coefficient.5. An encoding method according to claim 1 , comprising the following steps:determining, for each coefficient type and each block type, at least one parameter representative of a probabilistic distribution of coefficients having the concerned coefficient type in the concerned block type; anddetermining the initial coefficient encoding merit for given coefficient type and block type based on the parameter for the given ...

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Номер записи: 86
12-09-2013 дата публикации

Boosting circuit

Номер: US20130234768A1
Автор: Masaya Murata, Tomohiro Oka
Принадлежит: Seiko Instruments Inc

A boosting circuit is provided which performs an appropriate boosting operation in accordance with load capacitance. In the boosting circuit, a slope control circuit is provided between a limiter circuit, which limits a high voltage obtained by a charge pump circuit to a desired boosted voltage VPP, and a discharge circuit, which makes the boosted voltage VPP drop quickly to a power supply voltage VCC after the completion of writing, to enable a boosting operation in an appropriate boosted-voltage reach time, by increasing the time taken to reach the boosted voltage VPP in the case where the load capacitance is low, while keeping the time taken to reach the boosted voltage VPP unchanged, irrespective of the presence/absence of the slope control circuit, in the case where the load capacitance is high as in the case of selecting the memory cells collectively.

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Номер записи: 87
12-09-2013 дата публикации

Random access memory devices having word line drivers therein that support variable-frequency clock signals

Номер: US20130235684A1
Автор: Byung-ho Kang, Yongjin YOON, Youngjae Son
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Integrated circuit memory devices include an array of memory cells electrically coupled to a plurality of word lines and a word line driver circuit. The word line driver circuit includes a variable-width pulse generator having a first delay unit therein. The word line driver circuit is configured to drive a selected one of the plurality of word lines with a first word line signal having a leading edge synchronized with a leading edge of a clock signal and a trailing edge synchronized with a trailing edge of the clock signal when a one-half period of the clock signal is greater than a length of delay provided by the first delay unit.

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Номер записи: 88
12-09-2013 дата публикации

IMAGE PROCESSING DEVICE AND IMAGE PROCESSING METHOD

Номер: US20130236113A1
Автор: Tahara Daisuke, WADA Yuji
Принадлежит: SONY CORPORATION

There is provided an image processing device including an inverse transform unit that transforms transform coefficient data of a frequency component of an image including one or more blocks into an image signal by executing an integer inverse discrete wavelet transform, wherein an integer transform function used in the integer inverse discrete wavelet transform has a function graph that is symmetrical about an origin as a reference. 1. An image processing device comprising an inverse transform unit that transforms transform coefficient data of a frequency component of an image including one or more blocks into an image signal by executing an integer inverse discrete wavelet transform , whereinan integer transform function used in the integer inverse discrete wavelet transform has a function graph that is symmetrical about an origin as a reference.2. The image processing device according to claim 1 , wherein the integer transform function is a function that transforms an absolute value of an argument into an integer independently of a sign of the argument claim 1 , and assigns to the absolute value transformed into the integer the same sign as the sign of the argument.3. The image processing device according to claim 2 , wherein the integer transform function transforms the absolute value into an integer by rounding off the absolute value to a nearest whole number.5. The image processing device according to claim 1 , wherein the transform coefficient data is generated in encoding of the image by expanding a pixel value at an end of each block through symmetric period expansion and executing a discrete wavelet transform on the expanded pixel value.6. The image processing device according to claim 1 , whereinthe image processing device is a device that decodes the image according to a JPEG 2000 scheme, andthe block corresponds to a tile.7. An image processing device comprising a transform unit that transforms an image signal of an image including one or more blocks ...

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Номер записи: 89
19-09-2013 дата публикации

SYSTEM AND METHOD FOR PROCESSING SIGNALS IN HIGH SPEED DRAM

Номер: US20130242685A1
Автор: Ba Ben, Wong Victor
Принадлежит: MICRON TECHNOLOGY, INC.

The embodiments described herein provide memory devices. In one embodiment, a memory device includes bank control logic configured to generate a modified bank address signal and an active driver configured to provide a bank activate signal, receive an activate command signal, execute an activate command of the activate command signal at each one of a group of clock cycles, in which each one of the group of clock cycles is greater than one clock cycle, and receive the modified bank address signal, in which the modified bank address signal is high for at least a portion of each one of the group of clock cycles and the at least a portion of each one of the group of clock cycles is greater than one clock cycle. 1. A memory device , comprising:bank control logic configured to generate a modified bank address signal by passing a bank address and a delayed bank address signal through an OR gate, wherein the delayed bank address signal is a time delayed version of the bank address signal; and provide a bank activate signal;', 'receive an activate command signal and execute an activate command of the activate command signal at each one of a group of clock cycles, wherein each one of the group of clock cycles is greater than one clock cycle; and', 'receive the modified bank address signal, wherein the modified bank address signal is high for at least a portion of each one of the group of clock cycles, and wherein the at least a portion of each one of the group of clock cycles is greater than one clock cycle., 'an active driver configured to2. The memory of claim 1 , wherein the modified bank address signal transitions to a high state at a first time and transitions to a low state at a second time claim 1 , and the activate command transitions to a high state at a third time and transitions to a low state at a fourth time;wherein the third time is after the first time, and wherein the second time is after the fourth time.3. The memory of claim 2 , wherein a difference between ...

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Номер записи: 90
26-09-2013 дата публикации

SEMICONDUCTOR MEMORY DEVICE, INFORMATION PROCESSING SYSTEM AND CONTROL METHOD

Номер: US20130250686A1
Автор: Kinoshita Atsuhiro, Kurita Takahiro, Marukame Takao
Принадлежит: KABUSHIKI KAISHA TOSHIBA

According to an embodiment, a semiconductor memory device includes a first storage unit, a receiving unit, an acquiring unit, and an output control unit. The first storage unit is configured to store a value and address information in which a key address generated on the basis of a key associated with the value and a physical address of the value are associated with each other. The receiving unit is configured to receive a request for acquisition of the value associated with the key. The request contains the key. The acquiring unit is configured to acquire the physical address associated with the key address of the key contained in the request for acquisition on the basis of the address information. The output control unit is configured to acquire the value at the acquired physical address from the first storage unit and output the acquired value in response to the request. 1. A semiconductor memory device comprising:a first storage unit configured to include a block that stores a key, a value associated with the key, a key address generated on the basis of the key and address information in which the key address and a physical address of the value are associated with each other;a receiving unit configured to receive the key via an interface;an acquiring unit configured to acquire the physical address associated with the key address from the address information, when the key is received by the receiving unit; andan output unit configured to refers to the acquired physical address to output the value.2. The device according to claim 1 , further comprising a second storage unit configured to store key-value information in which a key and a value are associated with each other claim 1 , and output the value associated with a specified key if the stored key-value information contains the specified key.3. The device according to claim 2 , wherein the second storage unit outputs information indicating that the specified key is not stored if the stored key-value ...

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Номер записи: 91
26-09-2013 дата публикации

MEMORY MODULE

Номер: US20130250706A1
Автор: Hampel Craig E., Perego Richard E., Tsern Ely K., Ware Frederick A.
Принадлежит: RAMBUS INC.

A memory module having memory components, a termination structure, an address/control signal path, a clock signal path, multiple data signal paths and multiple strobe signal paths. The strobe signal paths and data signal paths are coupled to respective memory components, and the address/control signal path and clock signal path are coupled in common to all the memory components. The address/control signal path extends along the memory components to the termination structure such that control signals propagating toward the termination structure arrive at address/control inputs of respective memory components at progressively later times corresponding to relative positions of the memory components. 1. A memory module comprising:a circuit board;a first plurality of memory components disposed on the circuit board, each of the memory components having an address/control input, a clock input, a data input and a strobe input;a termination structure disposed on the circuit board;an address/control signal path that extends from an edge of the circuit board to the termination structure, the address/control signal path being coupled along its length to the address/control input of each of the memory components such that control signals propagating toward the termination structure on the address/control signal path arrive at the address/control inputs of respective memory components at progressively later times corresponding to relative positions of the memory components;a clock signal path extending from the circuit board edge and coupled along its length to the clock input of each of the memory components such that a clock signal propagating on the clock signal path arrives at the clock inputs of respective memory components at progressively later times corresponding to the times at which the control signals arrive at the address/control inputs of the memory components, the clock signal indicating to the memory components respective times at which to sample the control ...

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Номер записи: 92
26-09-2013 дата публикации

SEMICONDUCTOR MEMORY APPARATUS AND SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING THE SAME

Номер: US20130250712A1
Автор: BYUN Hee Jin
Принадлежит: SK HYNIX INC.

A semiconductor memory apparatus includes: a memory cell area including a plurality of banks each having a plurality of octet banks corresponding to a first group and a plurality of octet banks corresponding to a second group; and a control unit configured to generate a plurality of control signals to input a data signal to any one octet bank of the first group and any one octet bank of the second group with a predetermined margin. 1. A semiconductor memory apparatus comprising:a memory cell area comprising a plurality of banks each having a plurality of octet banks corresponding to a first group and a plurality of octet banks corresponding to a second group; anda control unit configured to generate a plurality of control signals to input a data signal to any one octet bank of the first group and any one octet bank of the second group with a predetermined margin.2. The semiconductor memory apparatus according to claim 1 , wherein the control unit generates the plurality of control signals using a command signal and an address signal which are outputted in synchronization with the same clock claim 1 , andthe plurality of control signals are generated at substantially the same time.3. The semiconductor memory apparatus according to claim 2 , wherein the control unit comprises:a command address signal shifter configured to shift the command signal and the address signal, inputted from outside, such that the shifted signals have a predetermined margin;a data enable signal generator configured to generate a data enable signal having a predetermined margin, using the command signal and the address signal;a first latch signal generator configured to generate a first latch signal to latch a data signal inputted to the octet banks of the first group, using the command signal and the address signal;a second latch signal generator configured to generate a second latch signal for latching a data signal inputted to the octet banks of the second group, using the command signal ...

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Номер записи: 93
10-10-2013 дата публикации

Micro-Threaded Memory

Номер: US20130265842A1
Автор: Bellows Chad A., Hampel Craig E., Lai Lawrence, Richardson Wayne S., Ware Frederick A.
Принадлежит:

A micro-threaded memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval must transpire between successive accesses to a given row of the storage cells. Transfer control circuitry is provided to transfer a first amount of data between the plurality of storage banks and an external signal path in response to a first memory access request, the first amount of data being less than a product of the external signal path bandwidth and the minimum access time interval. 1. (canceled)2. A synchronous memory device , comprising:first and second bank groups, each comprising at least two storage arrays; and the request interface having row control circuitry to service two row activate commands addressed to respective storage arrays in different ones of the bank groups with a shorter intervening interval than the row control circuitry can service two row activate commands addressed to respective storage arrays in a same one of the bank groups,', 'the request interface having column control circuitry to service two column access commands directed to respective, active rows in respective storage arrays in different ones of the bank groups with a shorter intervening interval than the column control circuitry can service two column access commands directed to one or more active rows in a same one of the bank groups., 'a request interface to receive external commands corresponding to memory transactions, including row activate commands and column access commands, each addressed to one of the storage arrays,'}3. The synchronous memory device of claim 2 , further comprising a first data serialization register to receive read data responsive to column access commands addressed to the first bank group claim 2 , and a second data serialization register to receive read data responsive to column access commands addressed to the second bank group.4. The ...

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Номер записи: 94
10-10-2013 дата публикации

MEMORY SYSTEM FOR ACCESS CONCENTRATION DECREASE MANAGEMENT AND ACCESS CONCENTRATION DECREASE METHOD

Номер: US20130268727A1
Автор: Cho Young Jin, Choi Hyung Woo, Lee Dong Su, Sohn Kyo Min
Принадлежит:

A spatial disturbance that occurs when an access is concentrated in a specific memory area in a volatile semiconductor memory like DRAM is properly solved by a memory controller. The memory controller includes a concentration access detection part generating a concentration access detection signal when an address for accessing a specific memory area among memory areas of volatile semiconductor memory is concentrically received. In the case that the concentration access detection signal is generated, the memory controller includes a controller for easing or preventing corruption of data which memory cells of the specific memory area and/or memory cells of memory areas adjacent to the specific memory area hold. 1. A memory controller comprising:a concentration access detector configured to generate a concentration detection signal when concentrically receiving an address for accessing a specific memory area among memory areas of volatile semiconductor memory; anda controller for preventing or mitigating corruption of data of memory cells of the specific memory area or memory cells of memory areas adjacent to the specific memory area when the concentration access detection signal is generated.2. The memory controller of claim 1 , wherein when the concentration access detection signal is generated claim 1 , the controller applies an interrupt signal to a processor connected to the memory controller and the processor changes an address allocation using a software method and thereby an access to the specific memory area is evaded.3. The memory controller of claim 1 , wherein when the concentration access detection signal is generated claim 1 , the controller stores an interrupt signal in an internal register and a processor which checked the internal register changes an address allocation and thereby the specific memory area is not accessed.4. The memory controller of claim 1 , wherein when the concentration access detection signal is generated claim 1 , the controller ...

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Номер записи: 95
17-10-2013 дата публикации

COMMAND LATENCY SYSTEMS AND METHODS

Номер: US20130272079A1
Автор: Morgan Donald M.
Принадлежит:

Examples of command latency systems and methods are described. In some examples, phase information associated with a received command signal is stored, a received command signal is propagated through a reduced clock flip-flop pipeline and the delayed command signal is combined with the stored phase information. The reduced clock flip-flop pipeline may use a clock having a lower frequency than that used to issue the command signal. Accordingly, fewer flip-flops may be required. 1. An apparatus , comprising:a delay circuit configured to receive a first command signal and delay the first command signal based, at least in part, on first and second clock signals to provide a delayed command signal; andan output flip-flop configured to provide a second command signal in accordance with the first clock signal, the second command signal based, at least in part, on the delayed command signal and phase information indicating a cycle of the first clock signal corresponding to receipt of the first command signal by the delay circuit.2. The apparatus of claim 1 , wherein the delay circuit is further configured to lengthen the command signal.3. The apparatus of claim 1 , wherein the second clock signal is based claim 1 , at least in part claim 1 , on the first clock signal.4. The apparatus of claim 1 , further comprising storage circuitry configured to receive the second command signal and provide the phase information responsive claim 1 , at least in part claim 1 , to cycling through a plurality of states.5. The apparatus of claim 4 , wherein the storage circuitry comprises a flip-flop pipeline.6. The apparatus of claim 1 , wherein the apparatus is included in a memory.7. The apparatus of claim 1 , wherein the delay circuit comprises a first number of flip-flops and wherein the delay circuit is configured to delay the first command signal by a second number of cycles of the first clock signal claim 1 , the second number greater than the first number.8. An apparatus claim 1 , ...

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Номер записи: 96
17-10-2013 дата публикации

EFFICIENT CONTENT COMPRESSION AND DECOMPRESSION SYSTEM AND METHOD

Номер: US20130272622A1
Автор: Islam Asad
Принадлежит:

A content compression/compression system and method are disclosed in which a pre-processing step is performed before any compression and a post-processing step is performed once a compressed piece of content is decompressed. 1. A method for compressing a piece of video content , the method comprising:suppressing one or more least significant raw data portions in a piece of video content to generate a pre-processed piece of video content; andcompressing the pre-processed piece of video content using discrete cosine transform based video compression that reduces the amount of data.2. The method of claim 1 , wherein each least significant data portion further comprises a bit-plane.3. The method of claim 2 , wherein suppressing one or more least significant raw data portions further comprises removing the one or more least significant bit-planes.4. The method of claim 1 , wherein suppressing one or more least significant raw data portions further comprises setting a plurality of bits in the one or more least significant bit-planes to a single value that is one of “1” and “0”.5. The method of claim 1 , wherein the discrete cosine transform based video compression is one of motion JPEG claim 1 , motion JPEG 2000 claim 1 , H.263 claim 1 , MPEG-4 and H.264.6. A method for decompressing a compressed piece of video content claim 1 , the method comprising:decompressing a compressed piece of video content using discrete cosine transform based video compression to generate a decompressed piece of content wherein the compressed piece of video content had been pre-processed to suppress one or more least significant unconverted data portions; andregenerating the suppressed one or more least significant data portions.7. The method of claim 6 , wherein the one or more least significant data portions further comprises one or more bit-planes.8. The method of claim 7 , wherein regenerating the suppressed one or more least significant data portions further comprises inserting a number of ...

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Номер записи: 97
24-10-2013 дата публикации

SEMICONDUCTOR MEMORY DEVICE

Номер: US20130279285A1
Автор: Lee Bum Jae, Yoo Han Sik
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A semiconductor memory device includes a memory cell array region and a column decoder. The memory cell array region includes a plurality of memory cell arrays that are arranged in row and column directions. The column decoder includes a first column select line (CSL) driver and a second CSL driver that are disposed adjacent to a first edge of the memory cell array region extending in the row direction and that have different physical layouts. 1. A semiconductor memory device comprising:a memory cell array region comprising a plurality of memory cell arrays each array including memory cells that are arranged in row and column directions, sub-wordline drivers that are disposed between memory cell arrays in the row direction, and conjunction regions that are disposed between sub-wordline drivers in the column direction;protrusion conjunction regions that are disposed adjacent to a first group of the sub-wordline drivers positioned at a first edge of the memory cell array region extending in the row direction and that protrude from the first edge in the column direction; anda column decoder comprising first column select line (CSL) drivers each having a first physical layout and second CSL drivers each having a second physical layout different from the first physical layout, the first and second CSL drivers being disposed adjacent to the first edge of the memory cell array region,wherein the number of the first CSL drivers is greater than the number of the second CSL drivers.2. The semiconductor memory device of claim 1 , wherein the protrusion conjunction regions protrude from the first edge of the memory cell array region by a first distance claim 1 ,wherein each of the first CSL drivers is disposed apart from the first edge by a second distance less than the first distance, andwherein each of the second CSL drivers is disposed apart from the first edge by a third distance greater than the first distance.3. The semiconductor memory device of claim 1 , wherein the ...

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Номер записи: 98
24-10-2013 дата публикации

DUAL TRANSFORM LOSSY AND LOSSLESS COMPRESSION

Номер: US20130279804A1
Автор: CHU Tam-Anh, Kilbank Daniel
Принадлежит:

A system and method for compression of video data uses digital processors to transform the data to a more compressed format. After preprocessing, a KL (Karhunan-Loève) transform is used to treat an array of pixels as a series of vectors transformed to a new set of basis vectors selected so that the data vectors (now represented by coordinates with respect to the transformed axes) lie closest to the transformed axes. A number of the axes lying closest to the data is selected, and the vectors are projected onto the subspace spanned by those axes. Those components extending into the orthogonal subspace are retained as a separate (second) data set, and a second GS (“Gram-Schmidt) compression is applied to those components. By suppressing portions of the data generated in the GS transformation, lossy transformations are efficiently accomplished. The data may also be preprocessed and where different parameter values may be selected for the pre-processing, the system may be tried for different parameter values and the result with the lowest entropy selected. 1. A system for transforming an image for display on a hardware platform by the method for compressing raster graphics images in a rectangular grid of pixels defined in RGB or more color spaces of planes of bytes comprising the steps ofperforming a first KL transform step on each plane of bytes;constructing an additional color plane;sending a subspace of data from the KL transform to the additional color plane;performing in parallel a Gram-Schmidt (herein “GS”) transform on at least a subset of the data in the additional color plane;wherein the subspace of data comprises a raster that is a combination of a zeroed out color plane and elements that are discarded from the KL transform and mapped to the additional color plane.2. The system for transforming an image of claim 1 , further including the pre-processing steps ofreading a data file, and extracting its metadata;dividing data from the data file into subimages and ...

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Номер записи: 99
31-10-2013 дата публикации

Memory Modules and Devices Supporting Configurable Data Widths

Номер: US20130286706A1
Автор: Hampel Craig E., Perego Richard E., Stark Donald C., Tsern Ely K., Ware Frederick A.
Принадлежит:

Described are memory apparatus organized in physical banks and including configurable data control circuit to support multiple data-width configurations. Relatively narrow width configurations load fewer sense amplifiers, resulting in reduced power usage for relatively narrow memory configurations. Also described are memory controllers that convey configuration value to configurable memory apparatus and support point-to-point data buffers for multiple width configurations. 1. (canceled)2. An integrated-circuit memory device comprising:an input to receive memory-width configuration value;data terminals to exchange data with another device;a plurality of physical banks, each physical bank including columns of memory cells coupled to corresponding sense amplifiers; anda data control circuit coupling the physical banks with the data terminals, the data control circuit supporting first and second width configurations responsive to the configuration value; in the first width configuration, the data control circuit conveys data of a first data width between a first integer number of the physical banks per read operation and the data terminals, and the plurality of physical banks collectively provide a first memory depth, and', 'in the second width configuration, the data control circuit conveys data of a second data width between a second integer number of the physical banks per read operation and the data terminals, the second data width wider than the first data width, the second integer number larger than the first integer number, and the plurality of physical banks collectively provide a second memory depth; and', 'wherein the memory device loads a first page of sense amplifiers in the first number of the physical banks for activate operation in the first width configuration and loads a second page of sense amplifiers in the second number of physical banks for activate operations in the second width configuration, the first page smaller than the second page., 'wherein3 ...

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Номер записи: 100