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Небесная энциклопедия

Космические корабли и станции, автоматические КА и методы их проектирования, бортовые комплексы управления, системы и средства жизнеобеспечения, особенности технологии производства ракетно-космических систем

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Мониторинг СМИ и социальных сетей. Сканирование интернета, новостных сайтов, специализированных контентных площадок на базе мессенджеров. Гибкие настройки фильтров и первоначальных источников.

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Применить Всего найдено 11960. Отображено 101.
20-08-2013 дата публикации

Electrical fuses and resistors having sublithographic dimensions

Номер: US0008513769B2
Автор: Charles T. Black, Matthew E. Colburn, Timothy J. Dalton, Daniel C. Edelstein, Wai-Kin Li, Anthony K. Stamper, Haining S. Yang, BLACK CHARLES T, COLBURN MATTHEW E, DALTON TIMOTHY J, EDELSTEIN DANIEL C, LI WAI-KIN, STAMPER ANTHONY K, YANG HAINING S, BLACK CHARLES T., COLBURN MATTHEW E., DALTON TIMOTHY J., EDELSTEIN DANIEL C., STAMPER ANTHONY K., YANG HAINING S.
Принадлежит: International Business Machines Corporation, BLACK CHARLES T, COLBURN MATTHEW E, DALTON TIMOTHY J, EDELSTEIN DANIEL C, LI WAI-KIN, STAMPER ANTHONY K, YANG HAINING S, IBM, BLACK CHARLES T., COLBURN MATTHEW E., DALTON TIMOTHY J., EDELSTEIN DANIEL C., STAMPER ANTHONY K., YANG HAINING S., INTERNATIONAL BUSINESS MACHINES CORPORATION

Electrical fuses and resistors having a sublithographic lateral or vertical dimension are provided. A conductive structure comprising a conductor or a semiconductor is formed on a semiconductor substrate. At least one insulator layer is formed on the conductive structure. A recessed area is formed in the at least one insulator layer. Self-assembling block copolymers are applied into the recessed area and annealed to form a fist set of polymer blocks and a second set of polymer blocks. The first set of polymer blocks are etched selective to the second set and the at least one insulator layer. Features having sublithographic dimensions are formed in the at least one insulator layer and/or the conductive structure. Various semiconductor structures having sublithographic dimensions are formed including electrical fuses and resistors.

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Номер записи: 1
05-01-2012 дата публикации

Copper interconnection structure and method for forming copper interconnections

Номер: US20120003390A1
Автор: Akihiro Shibatomi, Junichi Koike
Принадлежит: Advanced Interconnect Materials LLC

A copper interconnection structure includes an insulating layer, an interconnection body including copper in an opening provided on the insulating layer, and a diffusion barrier layer formed between the insulating layer and the interconnection body. The diffusion barrier layer includes an oxide layer including manganese having a compositional ratio of oxygen to manganese (y/x) less than 2.

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Номер записи: 2
12-01-2012 дата публикации

Semiconductor device structures including damascene trenches with conductive structures and related method

Номер: US20120007209A1
Автор: Howard E. Rhodes
Принадлежит: Micron Technology Inc

A method and apparatus for providing a conductive structure adjacent to a damascene conductive structure in a semiconductor device structure. The semiconductor device structure includes an insulation layer with at least one damascene conductive structure formed therein, wherein the at least one damascene conductive structure includes an insulative, protective layer disposed thereon. The insulative material of the protective layer is able to resist removal by at least some suitable etchants for the insulative material of the insulation layer adjacent to the at least one damascene conductive structure. A self-aligned opening is formed by removing a portion of an insulation layer adjacent the at least one damascene conductive structure. The self-aligned opening is then filled with a conductive material to thereby provide another conductive structure adjacent to the at least one damascene conductive structure.

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Номер записи: 3
12-01-2012 дата публикации

Metal wire for a semiconductor device formed with a metal layer without voids therein and a method for forming the same

Номер: US20120007240A1
Автор: Baek Mann Kim, Dong Ha JUNG, Jeong Tae Kim, Soo Hyun Kim, Sun Woo HWANG, Young Jin Lee
Принадлежит: Hynix Semiconductor Inc

A metal wiring of a semiconductor device includes a semiconductor substrate; an insulating layer provided with a damascene pattern formed over the semiconductor substrate; a diffusion barrier layer which contains a RuO 2 layer formed on a surface of the damascene pattern and an Al deposit-inhibiting layer formed on a portion of the RuO 2 layer in both-side upper portion of the damascene pattern; and a wiring metal layer including Al formed on the diffusion barrier layer by MOCVD method in order to fill the damascene pattern.

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Номер записи: 4
02-02-2012 дата публикации

Semiconductor device and method of manufacturing semiconductor device

Номер: US20120025290A1
Автор: Kazuhiko Takada
Принадлежит: Fujitsu Semiconductor Ltd

A conductive film having a first width in a first direction, an ONO film, and a control gate are formed above a tunnel gate insulating film. With the control gate as a mask, the conductive film is etched to form a floating gate. Then, an inter-layer insulating film is formed. A contact hole whose width in the first direction is larger than the first width is formed in the inter-layer insulating film. Then, sidewall spacer is formed on an inside wall of the contact hole.

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Номер записи: 5
02-02-2012 дата публикации

Semiconductor device and method of manufacturing semiconductor device

Номер: US20120025395A1
Автор: Shinichi Chikaki, Takahiro Nakayama
Принадлежит: Renesas Electronics Corp, Ulvac Inc

A semiconductor device includes: a first porous layer that is formed over a substrate and includes a SiO 2 skeleton; a second porous layer that is formed immediately above the first porous layer and includes a SiO 2 skeleton; a via wiring that is provided in the first porous layer; and a trench wiring that is buried in the second porous layer. The first porous layer has a pore density x 1 of 40% or below and the second porous layer has a pore density x 2 of (x 1 +5) % or above.

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Номер записи: 6
02-02-2012 дата публикации

Semiconductor device and method of fabricating the same

Номер: US20120028460A1
Автор: Kazuyuki Higashi, Makoto Wada
Принадлежит: Toshiba Corp

A semiconductor device according to one embodiment includes: a semiconductor substrate provided with a semiconductor element; a first conductive member formed on the semiconductor substrate; a first insulating film formed on the same layer as the first conductive member; a second conductive member formed so as to contact with a portion of an upper surface of the first conductive member; a second insulating film formed on the first insulating film so as to contact with a portion of the upper surface of the first conductive member, and including at least one type of element among elements contained in the first insulating film except Si; and an etching stopper film formed on the second insulating film so as to contact with a portion of a side surface of the second conductive member, and having an upper edge located below the upper surface of the second conductive member.

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Номер записи: 7
09-02-2012 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20120032323A1
Автор: Akihiro Osaki, Atsushi Ishii, Masahiko Fujisawa, Masahiro Matsumoto
Принадлежит: Renesas Electronics Corp

A preferred aim of the invention is to provide technique for improving reliability of semiconductor devices when using a low-dielectric-constant film having a lower dielectric constant than a silicon oxide film to a part of an interlayer insulating film. More specifically, to achieve the preferred aim, an interlayer insulating film IL 1 forming a first fine layer is formed of a middle-Young's-modulus film, and thus it is possible to separate an integrated high-Young's-modulus layer (a semiconductor substrate 1 S and a contact interlayer insulating film CIL) and an interlayer insulating film (a low-Young's-modulus film; a low-dielectric-constant film) IL 2 forming a second fine layer not to let them directly contact with each other, and stress can be diverged. As a result, film exfoliation of the interlayer insulating film IL 2 formed of a low-Young's-modulus film can be prevented and thus reliability of semiconductor devices can be improved.

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Номер записи: 8
23-02-2012 дата публикации

Semiconductor device and method for forming the same

Номер: US20120043592A1
Автор: Chao Zhao, Huilong Zhu, Wenwu Wang
Принадлежит: Institute of Microelectronics of CAS

The present invention provides a semiconductor device. The semiconductor device comprises contact plugs that comprise a first contact plug formed by a first barrier layer arranged on the source and drain regions and a tungsten layer arranged on the first barrier layer; and second contact plugs comprising a second barrier layer arranged on both of the metal gate and the first contact plug and a conductive layer arranged on the second barrier layer. The conductivity of the conductive layer is higher than that of the tungsten layer. A method for forming the semiconductor device is also provided. The present invention provides the advantage of enhancing the reliability of the device when using the copper contact technique.

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Номер записи: 9
23-02-2012 дата публикации

Interconnects with improved tddb

Номер: US20120043659A1
Автор: Jing Hui Li, Lawrence A. Clevenger, Wu Ping Liu
Принадлежит: GLOBALFOUNDRIES SINGAPORE PTE LTD, International Business Machines Corp

A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided. A first upper etch stop layer is formed on the dielectric layer. The first upper etch stop layer includes a first dielectric material. The dielectric layer and first upper etch stop layer are patterned to form an interconnect opening. The interconnect opening is filled with a conductive material to form an interconnect. The interconnect and first upper etch stop layer have coplanar top surfaces. A second upper etch stop layer is formed over the coplanar top surfaces. The second upper etch stop layer includes a second material having sufficient adhesion with the first material to reduce diffusion of the conductive material.

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Номер записи: 10
23-02-2012 дата публикации

Method of making interconnect structure

Номер: US20120045893A1
Автор: Heinrich Koerner
Принадлежит: Individual

One or more embodiments relate to a method of forming a semiconductor device having a substrate, comprising: providing a Si-containing layer; forming a barrier layer over the Si-containing layer, the barrier layer comprising a compound including a metallic element; forming a metallic nucleation_seed layer over the Si-containing layer, the nucleation_seed layer including the metallic element; and forming a metallic interconnect layer over the nucleation_seed layer, wherein the barrier layer and the nucleation_seed layer are formed without exposing the semiconductor device substrate to the ambient atmosphere.

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Номер записи: 11
22-03-2012 дата публикации

Interconnect structure with a planar interface between a selective conductive cap and a dielectric cap layer

Номер: US20120068344A1
Автор: Elbert E. Huang, Griselda Bonilla, Lawrence A. Clevenger, Satyanarayana V. Nitta, Shom Ponoth
Принадлежит: International Business Machines Corp

A selective conductive cap is deposited on exposed metal surfaces of a metal line by electroless plating selective to exposed underlying dielectric surfaces of a metal interconnect structure. A dielectric material layer is deposited on the selective conductive cap and the exposed underlying dielectric layer without a preclean. The dielectric material layer is planarized to form a horizontal planar surface that is coplanar with a topmost surface of the selective conductive cap. A preclean is performed and a dielectric cap layer is deposited on the selective conductive cap and the planarized surface of the dielectric material layer. Because the interface including a surface damaged by the preclean is vertically offset from the topmost surface of the metal line, electromigration of the metal in the metal line along the interface is reduced or eliminated.

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Номер записи: 12
05-04-2012 дата публикации

Method for manufacturing a semiconductor device having an interconnect structure and a reinforcing insulating film

Номер: US20120083115A1
Автор: Tatsuya Usami
Принадлежит: Renesas Electronics Corp

A semiconductor device includes in an interconnect structure which includes a first interconnect made of a copper-containing metal, a first Cu silicide layer covering the upper portion of the first interconnect, a conductive first plug provided on the upper portion of the Cu silicide layer and connected to the first interconnect, a Cu silicide layer covering the upper portion of the first plug, a first porous MSQ film provided over the side wall from the first interconnect through the first plug and formed to cover the side wall of the first interconnect, the upper portion of the first interconnect, and the side wall of the first plug, and a first SiCN film disposed under the first porous MSQ film to contact with the lower portion of the side wall of the first interconnect and having the greater film density than the first porous MSQ film.

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Номер записи: 13
19-04-2012 дата публикации

Scratch protection for direct contact sensors

Номер: US20120091517A1
Автор: Danielle A. Thomas
Принадлежит: Individual

In capacitive sensor circuits where physical contact is required and excess pressure may be inadvertently applied to the sensor surface, aluminum is not sufficiently hard to provide “scratch” protection and may delaminate, causing circuit failure, even if passivation integrity remains intact. Because hard passivation layers alone provide insufficient scratch resistance, at least the capacitive electrodes and preferably all metallization levels within the sensor circuit in the region of the capacitive electrodes between the surface and the active regions of the substrate are formed of a conductive material having a hardness greater than that of aluminum, and at least as great as the lowest hardness for any interlevel dielectric or passivation material employed.

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Номер записи: 14
26-04-2012 дата публикации

Chip structure and process for forming the same

Номер: US20120098128A1
Автор: Ching-Cheng Huang, Jin-Yuan Lee, Mou-Shiung Lin
Принадлежит: Megica Corp

A chip with a metallization structure and an insulating layer with first and second openings over first and second contact points of the metallization structure, a first circuit layer connecting the first and second contact points and comprising a first trace portion, first and second via portions between the first trace portion and the first and second contact points, the first circuit layer comprising a copper layer and a first conductive layer under the copper layer and at a sidewall of the first trace portion, and a second circuit layer comprising a second trace portion with a third via portion at a bottom thereof, wherein the second circuit layer comprises another copper layer and a second conductive layer under the other copper layer and at a sidewall of the second trace portion, and a second dielectric layer comprising a portion between the first and second circuit layers.

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Номер записи: 15
26-04-2012 дата публикации

Method of manufacturing semiconductor device, apparatus for manufacturing same, and storage medium

Номер: US20120100727A1
Автор: Sumie Nagaseki
Принадлежит: Tokyo Electron Ltd

A method of manufacturing a semiconductor device includes steps of: generating positively or negatively charged fine bubbles having substantially zero buoyancy in a coating solution as an insulating film forming material; coating the coating solution including the bubbles on a substrate to form a coating film; and baking the coating film by heating the substrate before the bubbles are removed to obtain a porous low dielectric constant insulating film.

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Номер записи: 16
17-05-2012 дата публикации

Method For Segregating The Alloying Elements And Reducing The Residue Resistivity Of Copper Alloy Layers

Номер: US20120121799A1
Автор: Jick M. Yu, Xinyu Fu
Принадлежит: Applied Materials Inc

Methods for forming interconnect or interconnections on a substrate for use in a microelectric device are disclosed. In one or more embodiments, the method includes depositing an alloy layer comprising Cu and an alloying element, for, example, Mn, in a dielectric layer and segregating or diffusing the alloying element from the bulk Cu portion of the alloy layer. In one or more embodiments, the method includes annealing the alloy layer in an atomic hydrogen atmosphere. After annealing, the alloy layer exhibits a resistivity that is substantially equivalent to the resistivity of a pure Cu layer.

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Номер записи: 17
24-05-2012 дата публикации

Structures and methods for improving solder bump connections in semiconductor devices

Номер: US20120129336A1
Автор: Anthony K. Stamper, Daniel C. Edelstein, Felix P. Anderson, Thomas L. McDevitt, William Cote
Принадлежит: International Business Machines Corp

Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The structure includes a trench formed in a dielectric layer which has at least a portion thereof devoid of a fluorine boundary layer. The structure further includes a copper wire in the trench having at least a bottom portion thereof in contact with the non-fluoride boundary layer of the trench. A lead free solder bump is in electrical contact with the copper wire.

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Номер записи: 18
14-06-2012 дата публикации

Semiconductor having interconnects with improved mechanical properties by insertion of nanoparticles

Номер: US20120146224A1
Автор: Junjing Bao, Naftali E. Lustig, Tien-Jen J. Cheng
Принадлежит: International Business Machines Corp

In a BEOL process, UV radiation is used in a curing process of ultra low-k (ULK) dielectrics. This radiation penetrates through the ULK material and reaches the cap film underneath it. The interaction between the UV light and the film leads to a change the properties of the cap film. Of particular concern is the change in the stress state of the cap from compressive to tensile stress. This leads to a weaker dielectric-cap interface and mechanical failure of the ULK film. A layer of nanoparticles is inserted between the cap and the ULK film. The nanoparticles absorb the UV light before it can damage the cap film, thus maintaining the mechanical integrity of the ULK dielectric.

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Номер записи: 19
21-06-2012 дата публикации

Creation of vias and trenches with different depths

Номер: US20120153503A1
Автор: Chih-Chao Yang, David V. Horak, Shom Ponoth, Takeshi Nogami
Принадлежит: International Business Machines Corp

Embodiments of the invention provide a method of creating vias and trenches with different length. The method includes depositing a plurality of dielectric layers on top of a semiconductor structure with the plurality of dielectric layers being separated by at least one etch-stop layer; creating multiple openings from a top surface of the plurality of dielectric layers down into the plurality of dielectric layers by a non-selective etching process, wherein at least one of the multiple openings has a depth below the etch-step layer; and continuing etching the multiple openings by a selective etching process until one or more openings of the multiple openings that are above the etch-stop layer reach and expose the etch-stop layer. Semiconductor structures made thereby are also provided.

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Номер записи: 20
05-07-2012 дата публикации

Integrated circuit system with ultra-low k dielectric and method of manufacture thereof

Номер: US20120168203A1
Автор: Ravi Prakash Srivastava
Принадлежит: GLOBALFOUNDRIES SINGAPORE PTE LTD

A method of manufacturing an integrated circuit system includes: providing a etch stop layer; forming a layer stack over the etch stop layer with the layer stack having an anti-reflective coating layer over a low temperature oxide layer; forming a photoresist layer over the anti-reflective coating layer; forming a first resist line and a second resist line from the photoresist layer with the first resist line and the second resist line separated by a through line pitch on the anti-reflective coating layer; etching the anti-reflective coating layer using a low-pressure polymer burst with a non-oxidizing gas mixture to remove a portion of the anti-reflective coating layer; and forming a first polymer layer over the first resist line.

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Номер записи: 21
05-07-2012 дата публикации

Structure with self aligned resist layer on an interconnect surface and method of making same

Номер: US20120168953A1
Автор: Daniel C. Edelstein, Elbert E. Huang, Robert D. Miller
Принадлежит: International Business Machines Corp

A structure is provided with a self-aligned resist layer on a surface of metal interconnects for use in forming air gaps in an insulator material and method of fabricating the same. The non-lithographic method includes applying a resist on a structure comprising at least one metal interconnect formed in an insulator material. The method further includes blanket-exposing the resist to energy and developing the resist to expose surfaces of the insulator material while protecting the metal interconnects. The method further includes forming air gaps in the insulator material by an etching process, while the metal interconnects remain protected by the resist.

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Номер записи: 22
16-08-2012 дата публикации

Method to fabricate copper wiring structures and structures formed tehreby

Номер: US20120205804A1
Автор: Chih-Chao Yang, Fenton Read Mcfeely
Принадлежит: International Business Machines Corp

Techniques formation of high purity copper (Cu)-filled lines and vias are provided. In one aspect, a method of fabricating lines and vias filled with high purity copper with is provided. The method includes the following steps. A via is etched in a dielectric. The via is lined with a diffusion barrier. A thin ruthenium (Ru) layer is conformally deposited onto the diffusion barrier. A Cu layer is deposited on the Ru layer by a sputtering process. A reflow anneal is performed to eliminate voids in the lines and vias.

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Номер записи: 23
20-09-2012 дата публикации

On-chip electronic device and method for manufacturing the same

Номер: US20120235275A1
Автор: Hsin-Fu Hsu, Kuan-Ming Chen, Tzu-Yuan Chao, Yu-Ting Cheng
Принадлежит: National Chiao Tung University NCTU

The present invention relates to an on-chip electronic device and a method for manufacturing the same. The on-chip electronic device according to the present invention comprises a substrate, a porous layer, a plurality of magnetic bodies, and an electronic member layer. The porous layer is disposed on the substrate and has a plurality of voids; each of the plurality of magnetic bodies is disposed in the plurality of voids, respectively; and the electronic member layer is disposed on one side of the porous layer, such as upper side of or lower sider of the porous layer. Because the plurality of magnetic bodies is used as the core of the inductance, the inductance is increased effectively and the area of the on-chip electronic device is reduced. Besides the manufacturing method according to the present invention is simple and compatible with the current CMOS process, the manufacturing cost can be lowered.

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Номер записи: 24
27-09-2012 дата публикации

Nonvolatile semiconductor memory device and method for manufacturing same

Номер: US20120241843A1
Автор: Hiromitsu IINO, Ryota Katsumata
Принадлежит: Toshiba Corp

According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array part, a first contact part, and a peripheral circuit part. The first contact part is juxtaposed with the memory cell array part in a first plane. The peripheral circuit part is juxtaposed with the memory cell array part in the first plane. The memory cell array part includes a first stacked body, a first semiconductor layer, and a memory film. The first contact part includes a first contact part insulating layer, and a plurality of first contact electrodes. The peripheral circuit part includes a peripheral circuit, a structure body, a peripheral circuit part insulating layer, and a peripheral circuit part contact electrode. A width along an axis perpendicular to the first axis of the peripheral circuit part insulating layer is smaller than a diameter of the first particle.

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Номер записи: 25
27-09-2012 дата публикации

Semiconductor device and method of manufacturing the same

Номер: US20120241978A1
Автор: Akira Mino
Принадлежит: Toshiba Corp

A semiconductor device including a first insulating film formed above a semiconductor substrate and having a first relative dielectric constant; a second insulating film formed above the first insulating film and having a second relative dielectric constant greater than the first relative dielectric constant; a plurality of columnar plugs extending longitudinally through the first and the second insulating films having a first sidewall extending through the first insulating film and a second sidewall extending through the second insulating film, wherein the second sidewall is tapered; a third insulating film formed above the second insulating film and having a third relative dielectric constant less than the second relative dielectric constant of the second insulating film; trenches extending through the third insulating film and reaching an upper portion of the plugs; and an interconnect wiring comprising metal formed within the trenches and contacting the upper portion of the plugs.

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Номер записи: 26
18-10-2012 дата публикации

Design structure for interconnect structure containing various capping materials for electrical fuse and other related applications

Номер: US20120261794A1
Автор: Chih-Chao Yang, Louis L. Hsu, William R. Tonti
Принадлежит: International Business Machines Corp

A design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different from the first interfacial structure.

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Номер записи: 27
01-11-2012 дата публикации

Semiconductor device having air gap and method for manufacturing the same

Номер: US20120273962A1
Автор: FAN LI, ZHONGSHAN Hong
Принадлежит: Semiconductor Manufacturing International Shanghai Corp

A method for manufacturing a semiconductor device having an air gap, includes: providing a substrate having a first dielectric layer and a second dielectric layer formed thereon successively; forming a mask layer on the second dielectric layer; patterning the first and the second dielectric layer by using the mask layer as a mask so as to form a plurality of grooves; filling a conducting material into the grooves; removing redundant conducting material on the second dielectric layer utill the second dielectric layer is exposed so as to form a plurality of conductive trenches; forming a molecular sieve on the second dielectric layer and the conductive trenches; and removing the second dielectric layer partly or completely by flowing a reactant gas towards the second dielectric layer through the molecular sieve, so as to form an air gap. It is novel and simple to form an air gap through molecular sieve.

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Номер записи: 28
08-11-2012 дата публикации

Semiconductor device having groove-shaped via-hole

Номер: US20120280396A1
Автор: Kenichi Watanabe
Принадлежит: Fujitsu Semiconductor Ltd

The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66 a having a pattern bent at a right angle; and buried conductors 70, 72 a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66 a. A groove-shaped via-hole 66 a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.

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Номер записи: 29
08-11-2012 дата публикации

Method for air gap interconnect integration using photo-patternable low k material

Номер: US20120280398A1
Автор: Anthony D. Lisi, Lawrence A. Clevenger, Maxime Darnon, Qinghuang Lin, Satyanarayana V. Nitta
Принадлежит: International Business Machines Corp

Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.

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Номер записи: 30
22-11-2012 дата публикации

Interconnect structures and design structures for a radiofrequency integrated circuit

Номер: US20120292741A1
Автор: Anthony K. Stamper, Ebenezer E. Eshun, Sarah L. Grunow, Timothy Dalton, Zhong-Xiang He
Принадлежит: International Business Machines Corp

Interconnect structures that include a passive element, such as a thin film resistor or a metal-insulator-metal (MIM) capacitor, methods for fabricating an interconnect structure that includes a passive element, and design structures embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, such as a radiofrequency integrated circuit. A top surface of a dielectric layer is recessed relative to a top surface of a conductive feature in the dielectric layer. The passive element is formed on the recessed top surface of the dielectric layer and includes a layer of a conductive material that is coplanar with, or below, the top surface of the conductive feature.

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Номер записи: 31
29-11-2012 дата публикации

Wiring structure and method of forming the structure

Номер: US20120299188A1
Автор: Anthony K. Stamper, Fen Chen, Jeffrey P. Gambino, Timothy D. Sullivan
Принадлежит: International Business Machines Corp

Disclosed is a wiring structure and method of forming the structure with a conductive diffusion barrier layer having a thick upper portion and thin lower portion. The thicker upper portion is located at the junction between the wiring structure and the adjacent dielectric materials. The thicker upper portion: (1) minimizes metal ion diffusion and, thereby TDDB; (2) allows a wire width to dielectric space width ratio that is optimal for low TDDB to be achieved at the top of the wiring structure; and (3) provides a greater surface area for via landing. The thinner lower portion: (1) allows a different wire width to dielectric space width ratio to be maintained in the rest of the wiring structure in order to balance other competing factors; (2) allows a larger cross-section of wire to reduce current density and, thereby reduce EM; and (3) avoids an increase in wiring structure resistivity.

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Номер записи: 32
27-12-2012 дата публикации

Interconnect structure including a modified photoresist as a permanent interconnect dielectric and method of fabricating same

Номер: US20120325532A1
Автор: Qinghuang Lin
Принадлежит: International Business Machines Corp

An interconnect structure is provided that may include at least one cured permanent patterned dielectric material located on a surface of a substrate. The at least one cured permanent patterned dielectric material is a cured product of a patterned photoresist that includes a dielectric enabling element therein. The structure further includes at least one conductively filled region embedded within the at least one cured permanent patterned dielectric material.

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Номер записи: 33
27-12-2012 дата публикации

Method of manufacturing a semiconductor device and semiconductor device

Номер: US20120326315A1
Автор: Hirofumi Watatani, Hisaya Sakai, Kazuo Kawamura, Kazuya Okubo, Shinichi Akiyama
Принадлежит: Fujitsu Semiconductor Ltd

A method of manufacturing a semiconductor device has forming, in a dielectric film, a first opening and a second opening located in the first opening, forming a first metal film containing a first metal over a whole surface, etching the first metal film at a bottom of the second opening using a sputtering process and forming a second metal film containing a second metal over the whole surface, and burying a conductive material in the second opening and the first opening.

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Номер записи: 34
27-12-2012 дата публикации

Discontinuous/non-uniform metal cap structure and process for interconnect integration

Номер: US20120329271A1
Автор: Chao-Kun Hu, Chih-Chao Yang, Lynne M. Gignac, Surbhi Mittal
Принадлежит: International Business Machines Corp

A method of fabricating an interconnect structure is provided which includes providing a dielectric material having a dielectric constant of about 3.0 or less and at least one conductive material embedded therein, the at least one conductive material has an upper surface that is coplanar with an upper surface of the dielectric material; and forming a noble metal-containing cap directly on the upper surface of the at least one conductive material, wherein the noble metal cap is discontinuous or non-uniform.

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Номер записи: 35
03-01-2013 дата публикации

Formation of alloy liner by reaction of diffusion barrier and seed layer for interconnect application

Номер: US20130000962A1
Автор: Chih-Chao Yang, Daniel C. Edelstein, Takeshi Nogami
Принадлежит: International Business Machines Corp

An interconnect structure including an alloy liner positioned directly between a diffusion barrier and a Cu alloy seed layer as well as methods for forming such an interconnect structure are provided. The alloy liner of the present invention is formed by thermally reacting a previously deposited diffusion barrier metal alloy layer with an overlying Cu alloy seed layer. During the thermal reaction, the metal alloys from the both the diffusion barrier and the Cu alloys seed layer react forming a metal alloy reaction product between the diffusion barrier and the Cu seed layer.

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Номер записи: 36
03-01-2013 дата публикации

Semiconductor device and method of manufacturing semiconductor device

Номер: US20130001670A1
Автор: Kazuhiko Takada
Принадлежит: Fujitsu Semiconductor Ltd

A conductive film having a first width in a first direction, an ONO film, and a control gate are formed above a tunnel gate insulating film. With the control gate as a mask, the conductive film is etched to form a floating gate. Then, an inter-layer insulating film is formed. A contact hole whose width in the first direction is larger than the first width is formed in the inter-layer insulating film. Then, sidewall spacer is formed on an inside wall of the contact hole.

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Номер записи: 37
03-01-2013 дата публикации

STRUCTURES AND METHODS FOR PHOTO-PATTERNABLE LOW-k (PPLK) INTEGRATION

Номер: US20130001781A1
Автор: Maxime Darnon, Qinghuang Lin
Принадлежит: International Business Machines Corp

An interconnect structure is provided which includes at least one patterned and cured low-k material located directly on a surface of a substrate; and at least one least one conductively filled region embedded within an interconnect pattern located within the at least one patterned and cured low-k material, wherein the at least one conductively filled region has an inflection point at a lower region of the interconnect pattern that is in proximity to an upper surface of the substrate and the interconnect region having an upper region that has substantially straight sidewalls.

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Номер записи: 38
03-01-2013 дата публикации

Semiconductor device and method for manufacturing same

Номер: US20130001785A1
Автор: Tadao Ohta, Yuichi Nakao
Принадлежит: ROHM CO LTD

A semiconductor device includes an interlayer insulating film, a wiring formed on the interlayer insulating film so as to protrude therefrom and made of a material having copper as a main component, and a passivation film formed so as to cover the wiring. The passivation film is made of a laminated film in which a first nitride film, an intermediate film, and a second nitride film are laminated in that order from the wiring side. The intermediate film is made of an insulating material (for example, an oxide) differing from those of the first and second nitride films.

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Номер записи: 39
03-01-2013 дата публикации

Semiconductor Constructions

Номер: US20130001788A1
Автор: Akram Ditali, Tianhong Zhang
Принадлежит: Micron Technology Inc

Some embodiments include semiconductor processing methods in which a copper barrier is formed to be laterally offset from a copper component, and in which nickel is formed to extend across both the barrier and the component. The barrier may extend around an entire lateral periphery of the component, and may be spaced from the component by an intervening ring of electrically insulative material. The copper component may be a bond pad or an interconnect between two levels of metal layers. Some embodiments include semiconductor constructions in which nickel extends across a copper component, a copper barrier is laterally offset from the copper component, and an insulative material is between the copper barrier and the copper component.

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Номер записи: 40
10-01-2013 дата публикации

Semiconductor device having wiring made by damascene method and capacitor and its manufacture method

Номер: US20130011995A1
Автор: Kenichi Watanabe
Принадлежит: Fujitsu Semiconductor Ltd

A wiring trench is formed in an interlayer insulating film partway in the depth direction of the interlayer insulating film. A via hole is formed extending from the bottom of the wiring trench to the bottom of the interlayer insulating film. A capacitor recess is formed reaching the bottom of the interlayer insulating film. A conductive member is embedded in the wiring trench and via hole. A capacitor is embedded in the capacitor recess, including a lower electrode, a capacitor dielectric film and an upper electrode. The lower electrode is made of the same material as that of the conductive member and disposed along the bottom and side surface of the capacitor recess. A concave portion is formed on an upper surface of the lower electrode, and the capacitor dielectric film covers an inner surface of the concave portion. The upper electrode is embedded in the concave portion.

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Номер записи: 41
24-01-2013 дата публикации

Copper Interconnects Separated by Air Gaps and Method of Making Thereof

Номер: US20130020708A1
Автор: George Matamis, James K. Kai, Jarrett Jun Liang, Jayavel Pachamuthu, Vinod R. Purayath
Принадлежит: SanDisk Technologies LLC

A semiconductor device including a plurality of copper interconnects. At least a first portion of the plurality of copper interconnects has a meniscus in a top surface. The semiconductor device also includes a plurality of air gaps, wherein each air gap of the plurality of air gaps is located between an adjacent pair of at least the first portion of the plurality of bit lines.

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Номер записи: 42
28-03-2013 дата публикации

Method for improving the electromigration resistance in the copper interconnection process

Номер: US20130078798A1
Автор: Lin Chen, Pengfei Wang, Qingqing Sun, Wei Zhang, Wen Yang
Принадлежит: FUDAN UNIVERSITY

The present invention belongs to the technical field of integrated semiconductor circuits, and relates to a method used in a process no greater than 32 nm to improve the electromigration resistance of Cu interconnects. Coating layers on Cu interconnects, such as CuSi 3 , CuGe, and CuSiN, can be prepared by autoregistration, and with the use of new impervious layer materials, the electromigration resistance of Cu interconnects can be largely improved and the high conductivity thereof can be kept, which provides an ideal solution for interconnection process for process nodes no greater than 32 nm.

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Номер записи: 43
11-04-2013 дата публикации

Semiconductor device having a multilevel interconnect structure and method for fabricating the same

Номер: US20130089979A1
Автор: Jun Iijima, Junichi Koike, Kazuyoshi Maekawa, Koji Arita, Masaki Yoshimaru, Noriyoshi Shimizu, Ryotaro Yagi, Yoshito Fujii
Принадлежит: Semiconductor Technology Academic Research Center, Tohoku University NUC

A multilevel interconnect structure in a semiconductor device and methods for fabricating the same are described. The multilevel interconnect structure in the semiconductor device includes a first insulating layer formed on a semiconductor wafer, a Cu interconnect layer formed on the first insulating layer, a second insulating layer formed on the Cu interconnect layer, and a metal oxide layer formed at an interface between the Cu interconnect layer and the second insulating layer. The metal oxide layer is formed by immersion-plating a metal, such as Sn or Zn, on the Cu interconnect layer and then heat-treating the plated layer in an oxidizing atmosphere.

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Номер записи: 44
18-04-2013 дата публикации

Semiconductor Device and Manufacturing Method of the Same

Номер: US20130093055A1
Автор: Chang Eun Lee
Принадлежит: Dongbu HitekCo Ltd

Provided is a semiconductor device. The semiconductor device includes a first insulation layer on a semiconductor substrate, the first insulation layer including a lower metal line, a metal head pattern on the first insulation layer, the metal head pattern including an inclined side surface, a thin film resistor pattern on the metal head pattern, a second insulation layer on the metal head pattern and the thin film resistor pattern, an upper metal line on the second insulation layer, a first via connecting the lower metal line to the upper metal line, and a second via connecting the metal head pattern to the upper metal line.

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Номер записи: 45
18-04-2013 дата публикации

Method for fabricating semiconductor device and semiconductor device

Номер: US20130093090A1
Автор: Atsuko Sakata, Hiroshi Toyoda, Kei Watanabe, Makoto Wada, Noriaki Matsunaga, Shinichi Nakao, Yumi Hayashi
Принадлежит: Atsuko Sakata, Hiroshi Toyoda, Kei Watanabe, Makoto Wada, Noriaki Matsunaga, Shinichi Nakao, Yumi Hayashi

A method for fabricating a semiconductor device, includes forming a dielectric film above a substrate; forming an opening in the dielectric film; forming a first film containing a metal whose energy for forming silicide thereof is lower than that of Cu silicide inside the opening; forming a second film that is conductive and contains copper (Cu) in the opening in which the first film containing the metal is formed; and forming a compound film containing Cu and silicon (Si) selectively on the second film in an atmosphere in which a temperature of the substrate is below 300° C.

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Номер записи: 46
25-04-2013 дата публикации

Interconnect Structure for Semiconductor Devices

Номер: US20130102148A1
Автор: Chang Hui-Lin, Jang Syun-Ming, Lu Yung-Cheng, Tsai Hung Chun
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A method of manufacturing a semiconductor device with a cap layer for a copper interconnect structure formed in a dielectric layer is provided. In an embodiment, a conductive material is embedded within a dielectric layer, the conductive material comprising a first material and having either a recess, a convex surface, or is planar. The conductive material is silicided to form an alloy layer. The alloy layer comprises the first material and a second material of germanium, arsenic, tungsten, or gallium. 1. A method of manufacturing a semiconductor device , the method comprising:forming a dielectric layer on a substrate;embedding a conductive material into the dielectric layer, the conductive material comprising a first material and having a recess; andsiliciding the conductive material to form an alloy layer at least partially within the recess, the alloy layer comprising the first material and a second material, the second material comprising germanium, arsenic, tungsten, or gallium.2. The method of claim 1 , wherein the siliciding the conductive material further comprises forming a seed layer of silicon on the conductive material.3. The method of claim 1 , wherein the siliciding the conductive material further comprises:introducing a first precursor material to the conductive material, the first precursor material being a silicon containing precursor material; andintroducing a second precursor material to the conductive material, the second precursor material containing the second material.4. The method of claim 3 , wherein the introducing the first precursor material and the introducing the second precursor material are begun simultaneously.5. The method of claim 3 , wherein the introducing the first precursor material is begun after the introducing the second precursor material.6. The method of claim 1 , wherein the conductive material comprises copper.7. The method of claim 1 , further comprising forming a barrier layer between the conductive material and the ...

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Номер записи: 47
09-05-2013 дата публикации

Semiconductor devices and methods of manufacturing the same

Номер: US20130113111A1
Автор: Young Jin Lee
Принадлежит: SK hynix Inc

A semiconductor device and methods directed toward preventing a leakage current between a contact plug and a line adjacent to the contact plug, and minimizing capacitance between adjacent lines.

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Номер записи: 48
23-05-2013 дата публикации

Redundant Via Structure For Metal Fuse Applications

Номер: US20130127584A1
Автор: Andrew H. Simon, Griselda Bonilla, Kaushik Chanda, Naftali E. Lustig, Ronald G. Filippi, Samuel S. Choi, Stephan Grunow
Принадлежит: International Business Machines Corp

A metal fuse structure using redundant vias. The redundant vias are formed on one metal level in a stacked via metal fuse structure to force failures to occur in the metal level that does not have the redundant vias. The metal fuse structure includes: a first dielectric layer having a metal feature; a second dielectric layer having a first metal connector embedded therein; and a third dielectric layer having a second metal connector embedded therein. The metal connectors include at least one via and one line, and at least one metal connector has at least two vias.

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Номер записи: 49
30-05-2013 дата публикации

Film forming method and processing system

Номер: US20130136859A1
Автор: Hitoshi Itoh, Kenji Matsumoto, Shigetoshi Hosaka
Принадлежит: Tokyo Electron Ltd

A film forming method performs a film forming process on a target object having on a surface thereof an insulating layer. The film forming method includes a first thin film forming step of forming a first thin film containing a first metal, an oxidation step of forming an oxide film by oxidizing the first thin film, and a second thin film forming step of forming a second thin film containing a second metal on the oxide film.

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Номер записи: 50
06-06-2013 дата публикации

Doped Tantalum Nitride for Copper Barrier Applications

Номер: US20130140698A1
Автор: Annamalai Lakshmanan, Jennifer Shan, Mei Chang, Paul F. Ma
Принадлежит: Individual

Described are doped TaN films, as well as methods for providing the doped TaN films. Doping TaN films with Ru, Cu, Co, Mn, Al, Mg, Cr, Nb, Ti and/or V allows for enhanced copper barrier properties of the TaN films. Also described are methods of providing films with a first layer comprising doped TaN and a second layer comprising one or more of Ru and Co, with optional doping of the second layer.

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Номер записи: 51
06-06-2013 дата публикации

Semiconductor device and method for production of semiconductor device

Номер: US20130140699A1
Автор: Atsushi Okuyama
Принадлежит: Sony Corp

A semiconductor device with a connection pad in a substrate, the connection pad having an exposed surface made of a metallic material that diffuses less readily into a dielectric layer than does a metal of a wiring layer connected thereto.

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Номер записи: 52
27-06-2013 дата публикации

HYDROGEN BARRIER FOR FERROELECTRIC CAPACITORS

Номер: US20130164933A1
Автор: Jain Manoj K., Moise Ted S., SUMMERFELT Scott R., Udayakumar Kezhakkedath R.
Принадлежит: TEXAS INSTRUMENTS INCORPORATED

An integrated circuit containing a FeCap array. The FeCap array is at least partially surrounded on the sides by hydrogen barrier walls and on the top by a hydrogen barrier top plate. A method for at least partially enclosing a FeCap array with hydrogen barrier walls and a hydrogen barrier top plate. 1. A process for forming an integrated circuit , comprising:providing a substrate having transistors, a first pre-metal dielectric, and a contact photoresist pattern for a contact wall seal surrounding a FeCap area;forming at least one contact wall seal that is at least partially filled with a first hydrogen barrier material wherein said first hydrogen barrier material covers the walls of said at least one contact wall seal;forming at least one metal wall seal that is at least partially filled with a second hydrogen barrier material wherein said second hydrogen barrier material covers the walls of said at least one metal wall seal;forming at least one via wall seal that is at least partially filled with a third hydrogen barrier material wherein said third hydrogen barrier material covers the walls of said at least one via wall seal;forming a top plate seal over said FeCap array, said top plate seal being over and in contact with one of said at least one via wall seal.2. The process of wherein said first hydrogen barrier is at least one of TiN claim 1 , TiAlN claim 1 , and TiAlON claim 1 , and wherein said contact wall seal is filled with CVD-W.3. The process of wherein said third hydrogen barrier material is at least one of TaN claim 1 , TaON claim 1 , and TiN and wherein said at least one via wall seal is filled with Cu.4. The process of wherein said forming said top plate seal further comprises:forming a photoresist pattern on top of a dielectric layer, said dielectric layer containing a trench for a via wall seal;etching said dielectric layer to form a trench for an interconnect signal lead and a trench for said top plate seal;forming a TaN barrier layer on a bottom ...

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Номер записи: 53
11-07-2013 дата публикации

Interlevel Dielectric Stack for Interconnect Structures

Номер: US20130175697A1
Автор: Alfred Grill, Griselda Bonilla, Satyanarayana V. Nitta, Son Van Nguyen, Thomas J. Haigh, JR.
Принадлежит: International Business Machines Corp

A dielectric stack and method of depositing the stack to a substrate using a single step deposition process. The dielectric stack includes a dense layer and a porous layer of the same elemental compound with different compositional atomic percentage, density, and porosity. The stack enhances mechanical modulus strength and enhances oxidation and copper diffusion barrier properties. The dielectric stack has inorganic or hybrid inorganic-organic random three-dimensional covalent bonding throughout the network, which contain different regions of different chemical compositions such as a cap component adjacent to a low-k component of the same type of material but with higher porosity.

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Номер записи: 54
18-07-2013 дата публикации

WIRING STRUCTURE AND DISPLAY DEVICE

Номер: US20130181218A1
Автор: Kugimiya Toshihiro, Maeda Takeaki
Принадлежит: Kabushiki Kaisha Kobe Seiko Sho (Kobe Steel, Ltd.)

An interconnection structure includes a semiconductor layer of a thin-film transistor and a metal interconnection film above a substrate in this order from a side of the substrate, and includes a barrier layer between the semiconductor layer and the metal interconnection film. The semiconductor layer is composed of an oxide semiconductor. The barrier layer is composed of a Ti oxide film containing TiOx (where x is from 1.0 to 2.0), and the Ti oxide film is directly connected to the semiconductor layer. The oxide semiconductor is composed of an oxide containing at least one element selected from the group consisting of In, Ga, Zn and Sn. 1. An interconnection structure , including a semiconductor layer of a thin-film transistor and a metal interconnection film above a substrate in this order from a side of the substrate , and including a barrier layer between the semiconductor layer and the metal interconnection film , whereinthe semiconductor layer is composed of an oxide semiconductor,the barrier layer is composed of a Ti oxide film containing TiOx (where x is from 1.0 to 2.0), and the Ti oxide film is directly connected to the semiconductor layer, andthe oxide semiconductor is composed of an oxide containing at least one element selected from the group consisting of In, Ga, Zn and Sn.2. The interconnection structure according to claim 1 , whereinthe metal interconnection film has a single-layer structure or a laminated structure,when the metal interconnection film has the single-layer structure, the metal interconnection film is composed of a pure Al film, an Al alloy film containing 90 atomic % or more of Al, a pure Cu film, or a Cu alloy film containing 90 atomic % or more of Cu, andwhen the metal interconnection film has the laminated structure, the metal interconnection film is composed of, in this order from the side of the substrate: a pure Ti film or a Ti alloy film containing 50 atomic % or more of Ti, and a pure Al film or an Al alloy film containing 90 ...

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Номер записи: 55
25-07-2013 дата публикации

Structure for interconnecting copper with low dielectric constant medium and the integration method thereof

Номер: US20130187278A1
Автор: Pengfei Wang, Wei Zhang
Принадлежит: FUDAN UNIVERSITY

The present invention belongs to the technical field of semiconductor devices, and discloses a structure for interconnecting a medium of low dielectric constant with copper and the integration method thereof. It includes: using a combination of copper interconnections and air gaps to reduce capacity, and a special structure to support copper conductors so as to maintain the shape of copper conductors after removing the medium. The advantage of the present invention is that it can realize the complete air gap structure without short circuit or disconnection of copper conductors as well as the complete air gap structure with long conductors, thus reducing RC delay.

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Номер записи: 56
25-07-2013 дата публикации

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

Номер: US20130187283A1
Автор: GU XUN, Ohmi Tadahiro
Принадлежит: NATIONAL UNIVERSITY CORPORATION TOHOKU UNIVERSITY

Provided is a method of manufacturing a semiconductor device of a multilayer wiring structure that comprises a CFfilm as an interlayer insulating film, that can make the most of the advantage of the CFfilm having a low dielectric constant, and that can prevent degradation of the properties of the CFfilm due to CMP. The method of this invention includes (a) forming a CFfilm, (b) forming a recess of a predetermined pattern on the CFfilm, (c) providing a wiring layer so as to bury the recess and to cover the CFfilm, and (d) removing the excess wiring layer on the CFfilm other than in the recess by CMP (Chemical Mechanical Polishing), thereby exposing a surface of the CFfilm, wherein (e) nitriding the surface of the CFfilm is provided before or after (b). 1. A method of manufacturing a semiconductor device , comprising:{'sub': 'x', '(a) forming an interlayer insulating film comprising a CFfilm with no cap film thereon;'}{'sub': 'x', '(b) forming a recess of a predetermined pattern on the CFfilm;'}{'sub': 'x', '(c) providing a wiring layer so as to bury the recess and to cover the CFfilm; and'}{'sub': x', 'x, '(d) removing the excess wiring layer on the CFfilm other than in the recess by CMP (Chemical Mechanical Polishing), thereby exposing a surface of the CFfilm,'}{'sub': 'x', 'wherein (e) nitriding the surface of the CFfilm is provided before or after the (b).'}2. The method of manufacturing a semiconductor device according to claim 1 , wherein (a) comprises forming the CFfilm by CVD using a plasma which is generated using a noble gas.3. The method of manufacturing a semiconductor device according to claim 1 , wherein{'sub': 'x', 'the wiring layer comprises a main wiring layer and a barrier layer which is formed in contact with a back surface of the main wiring layer for preventing diffusion of the main wiring layer into the CFfilm, and'}the main wiring layer is made of a material having a higher conductivity than the barrier layer.4. The method of manufacturing a ...

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Номер записи: 57
01-08-2013 дата публикации

METHOD FOR FORMING A VIA CONTACTING SEVERAL LEVELS OF SEMICONDUCTOR LAYERS

Номер: US20130196500A1
Автор: Batude Perrine, Morand Yves
Принадлежит:

A method for forming a via connecting a first upper level layer to a second lower level layer, both layers being surrounded with an insulating material, the method including the steps of: a) forming an opening to reach an edge of the first layer, the opening laterally continuing beyond said edge; b) forming a layer of a protection material on said edge only; c) deepening said opening by selectively etching the insulating material to reach the second lower level layer; and d) filling the opening with at least one conductive contact material. 1. A method for forming a via connecting a first upper level layer to a second lower level layer , both layers being surrounded with an insulating material , the method comprising the steps of:a) forming an opening to reach an edge of the first layer, the opening laterally continuing beyond said edge;b) forming a layer of a protection material on said edge only;c) deepening said opening by selectively etching the insulating material to reach the second lower level layer; andd) filling the opening with at least one conductive contact material.2. The method of claim 1 , wherein the protection material is a conductive material.3. The method of claim 2 , wherein claim 2 , at step b) claim 2 , the layer of the conductive protection material is formed by electroless deposition.4. The method of claim 1 , wherein the first and second layers are silicon layers covered with a metal silicide.5. The method of claim 4 , wherein the metal silicide is based on a metal selected from the group comprising platinum and nickel.6. The method of claim 1 , wherein:the thickness of the insulating material separating the first layer from the gates of transistors formed on the second layer ranges between 10 and 500 nm;the thickness of the first layer ranges between 5 and 150 nm; andat step b), a layer of the protection material having a thickness ranging between 10 and 50 nm is formed.7. The method of claim 2 , wherein the conductive protection material ...

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Номер записи: 58
01-08-2013 дата публикации

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Номер: US20130196503A1
Автор: OHTSUKA Nobuyuki, Shimizu Noriyoshi
Принадлежит: FUJITSU SEMICONDUCTOR LIMITED

A semiconductor device includes a first conductor formed over a semiconductor device; an insulation film formed over the semiconductor substrate and the first conductor and having an opening arriving at the first conductor; a first film formed in the opening and formed of a compound containing Zr; a second film formed over the first film in the opening and formed of an oxide containing Mn; and a second conductor buried in the opening and containing Cu. 111.-. (canceled)12. A semiconductor device manufacturing method comprising:forming a first conductor over a semiconductor substrate;forming an insulation film over the semiconductor substrate and over the first conductor;forming in the insulation film an opening arrived to the first conductor;forming in the opening a first film formed of a compound containing Zr;forming a second film containing Cu and Mn over the first film in the opening;forming a second conductor containing Cu in the opening; andoxidizing Mn in the second film to change the second film into a third film formed of an oxide containing Mn by thermal processing.13. The semiconductor device manufacturing method according to claim 12 , wherein{'sub': '2', 'the first film is a ZrBfilm, ZrBN film or ZrN film.'}14. A semiconductor device manufacturing method according to claim 12 , whereinin the forming the opening, the opening is formed, including a contact hole arriving at the first conductor and a trench connected to a top of the contact hole.15. A semiconductor device according to claim 14 , whereinin the forming the second film, the second film is formed by forming the second film in the contact hole and the trench while selectively removing the first film on a bottom of the contact hole.16. A semiconductor device manufacturing method according to claim 14 , further comprising claim 14 , after the forming the first film and before the forming the second film claim 14 ,selectively removing the first film on a bottom of the contact hole.17. A ...

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Номер записи: 59
15-08-2013 дата публикации

METHODS FOR MAKING POROUS INSULATING FILMS AND SEMICONDUCTOR DEVICES INCLUDING THE SAME

Номер: US20130207245A1
Автор: INOUE Naoya, TAGAMI Masayoshi
Принадлежит: RENESAS ELECTRONICS CORPORATION

Low-k porous insulating films with a high modulus of elasticity are made by depositing alkylated cyclic siloxane precursors over a semiconductor substrate by CVD. Plasma enhancement of the CVD is performed either during CVD or in situ on the deposited film. A UV cure of the film is effected under controlled temperature and time conditions, which generates a tight bonding structure between adjacent ring moieties without disrupting the Si—O ring bonding. 1. A method of making a porous insulating film , comprising:forming a precursor layer over a semiconductor substrate by depositing at least one cyclic siloxane compound having at least one hydrocarbon side chain by CVD; andconverting the precursor layer to a porous insulating film by exposing the insulating film to UV energy under conditions such that adjacent molecules of the at least one cyclic siloxane compound are bonded via a hydrocarbon group and the porous insulating film has an elastic modulus as measured by a nanoindenter of greater than 5 GPa.2. The method according to claim 1 , wherein the precursor layer is formed by plasma-enhanced CVD.3. The method according to claim 2 , wherein the at least one cyclic siloxane compound is introduced into a plasma during said forming step.4. The method according to claim 2 , wherein the at least one cyclic siloxane compound is treated with plasma in situ after formation of the precursor layer.5. The method according to claim 1 , wherein the porous insulating film has a lower carbon content than the precursor layer.6. The method according to claim 1 , wherein the porous insulating film includes Si—CH2-Si bonds.7. The method according to claim 1 , wherein silicon atoms of adjacent siloxane rings within the porous insulating film are joined by a methylene (—CH—) linkage.8. The method according to claim 1 , wherein the precursor layer is formed by plasma-enhanced CVD at a temperature within the range of 250-400° C.9. The method according to claim 1 , wherein the precursor ...

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Номер записи: 60
15-08-2013 дата публикации

Methods of Forming Device Level Conductive Contacts to Improve Device Performance and Semiconductor Devices Comprising Such Contacts

Номер: US20130207275A1
Автор: Ricardo P. MIKALO, Stefan Flachowsky, Thilo Scheiper
Принадлежит: Globalfoundries Inc

Disclosed herein are various methods of forming device level conductive contacts to improve device performance and various semiconductor devices with such improved deice level contact configurations. In one example, a device disclosed herein includes a first device level conductive contact positioned in a first layer of insulating material, wherein the first device level conductive contact is conductively coupled to a semiconductor device, a second device level conductive contact positioned above and conductively coupled to the first device level contact, wherein the second device level contact is positioned in a second layer of insulating material, and a first wiring layer for the device that is positioned above and conductively coupled to the second device level conductive contact.

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Номер записи: 61
15-08-2013 дата публикации

PHOTO-PATTERNABLE DIELECTRIC MATERIALS CURABLE TO POROUS DIELECTRIC MATERIALS, FORMULATIONS, PRECURSORS AND METHODS OF USE THEREOF

Номер: US20130207278A1
Автор: Brock Phillip J., Lin Qinghuang, Miller Robert D., Nelson Alshakim, Rathore Jitendra S., Sooriyakumaran Ratnam
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

Silsesquioxane polymers that cure to porous silsesquioxane polymers, silsesquioxane polymers that cure to porous silsesquioxane polymers in negative tone photo-patternable dielectric formulations, methods of forming structures using negative tone photo-patternable dielectric formulations containing silsesquioxane polymers that cure to porous silsesquioxane polymers, structures containing porous silsesquioxane polymers and monomers and method of preparing monomers for silsesquioxane polymers that cure to porous silsesquioxane polymers. 1. A structure , comprising:a porous cross-linked layer of a silsesquioxane polymer or a silsesquioxane polymer on a substrate;a trench in said cross-linked layer; andan electrically conductive material filling said trench and contacting said substrate in a bottom of said trench.2. The structure of claim 1 , further including:an additional porous cross-linked layer of an additional silsesquioxane on said cross-linked layer;an additional trench in said additional cross-linked layer, a top of said trench open to a bottom of said additional trench; andsaid electrically conductive material additionally filling said additional trench.4. The structure of claim 1 , wherein said cross-linked layer has a dielectric constant of about 3.0 or less.8. The structure of claim 7 , wherein said porous cross-linked layer consists essentially of a cross-linked polymer of structural formulas (1) claim 7 , (7) claim 7 , (3) and (4) claim 7 , Ris a methyl moiety and m is between about 40 mol % and about 70 mol % claim 7 , Ris an ethyl moiety and o is between about 10 mol % and about 30 mol % claim 7 , and p is between about 5 mol % and about 15 mol %.16. The structure of claim 15 , wherein said additional porous cross-linked layer consists essentially of a cross-linked polymer of structural formulas (1) claim 15 , (7) claim 15 , (3) and (4) claim 15 , Ris a methyl moiety and m is between about 40 mol % and about 70 mol % claim 15 , Ris an ethyl moiety and o ...

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Номер записи: 62
22-08-2013 дата публикации

INTERCONNECT STRUCTURES AND METHODS OF MANUFACTURING OF INTERCONNECT STRUCTURES

Номер: US20130214416A1
Автор: EDELSTEIN Daniel C., Nogami Takeshi
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

Interconnect structures and methods of manufacturing the same are disclosed herein. The method includes forming a barrier layer within a structure and forming an alloy metal on the barrier layer. The method further includes forming a pure metal on the alloy metal, and reflowing the pure metal such that the pure metal migrates to a bottom of the structure, while the alloy metal prevents exposure of the barrier layer. The method further includes completely filling in the structure with additional metal. 1. A structure comprising:a barrier layer on sidewalls of a via and trench structure;a copper alloy seed layer on the barrier layer;a pure copper film layer on the barrier layer and migrated to a bottom of the via and trench structure;an electroplated copper which fills in remaining portions of the via and trench structure, directly on reflowed pure copper of the pure copper film layer; anda dielectric material cap over the filled via and trench structure.2. The structure of claim 1 , further comprising an additional copper alloy layer on the pure copper layer and beneath the electroplated copper.3. The structure of claim 1 , wherein the electroplated copper completely fills the via and trench structure claim 1 , over the pure copper film layer.4. The structure of claim 1 , wherein the copper alloy seed layer is one of CuAl claim 1 , CuMn claim 1 , CuTi and CuSn.5. The structure of claim 1 , wherein the copper alloy wets the barrier layer during reflowing.6. The structure of claim 1 , wherein the via and trench structure are devoid of voids or agglomeration of copper islands.7. The structure of claim 1 , wherein the via and trench structure is formed in an interlevel dielectric material.8. The structure of claim 1 , wherein the barrier layer is a Ta based material using a combination of TaN and Ta claim 1 , Ru claim 1 , Co or alloys thereof.9. The structure of claim 1 , wherein the copper alloy seed layer keeps the barrier metal wet with copper claim 1 , while the pure ...

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Номер записи: 63
29-08-2013 дата публикации

DEVICES AND METHODS RELATED TO A SPUTTERED TITANIUM TUNGSTEN LAYER FORMED OVER A COPPER INTERCONNECT STACK STRUCTURE

Номер: US20130221528A1
Автор: Cheng Kezia
Принадлежит: SKYWORKS SOLUTIONS, INC.

Disclosed are devices and methods related to metallization of semiconductors. A metalized structure can include a stack disposed over a compound semiconductor, with the stack including a barrier, a copper (Cu) layer disposed over the barrier, and a first titanium (Ti) layer disposed over the Cu layer. The metalized structure can further include a sputtered titanium tungsten (TiW) layer disposed over the first Ti layer. The barrier can include an assembly of titanium nitride (TiN) and Ti layers. The metalized structure can further include a second Ti layer disposed over the sputtered TiW layer. 1. A metalized structure for a compound semiconductor device , the structure comprising:a stack disposed over a substrate associated with the compound semiconductor device, the stack including a barrier and a copper (Cu) layer disposed over the barrier; anda sputtered titanium tungsten (TiW) layer disposed over the stack.2. The structure of wherein the barrier includes a titanium nitride (TiN) layer disposed over a Ti layer.3. The structure of wherein the barrier includes a first titanium layer claim 1 , a barrier layer disposed over the first Ti layer claim 1 , and a second Ti layer disposed over the barrier layer.4. The structure of wherein the barrier layer includes platinum (Pt) claim 3 , palladium (Pd) claim 3 , or nickel (Ni).5. The structure of wherein the stack further includes a titanium (Ti) layer disposed between the Cu layer and the sputtered TiW layer.6. The structure of further comprising a gold (Au) layer disposed over the sputtered TiW layer.7. The structure of wherein the sputtered TiW layer has a thickness sufficient to inhibit interaction between the Cu layer and the Au layer.8. The structure of further comprising a Ti layer disposed over the Au layer.9. The structure of wherein each layer of the stack is formed by evaporation.10. The structure of wherein the sputtered TiW is substantially free of wing or stringer features.11. A method for forming a ...

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Номер записи: 64
29-08-2013 дата публикации

Diffusion Barrier Layer, Metal Interconnect Arrangement and Method of Manufacturing the Same

Номер: US20130221535A1
Автор: Huaxiang Yin, Lichuan Zhao, Xiaolong Ma
Принадлежит: Institute of Microelectronics of CAS

A diffusion barrier layer, a metal interconnect arrangement and a method of manufacturing the same are disclosed. In one embodiment, the metal interconnect arrangement may comprise a conductive plug/interconnect wire for electrical connection, and a diffusion barrier layer provided on at least a portion of a surface of the conductive plug/interconnect wire. The diffusion barrier layer may comprise insulating amorphous carbon.

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Номер записи: 65
29-08-2013 дата публикации

PROCESS OF FORMING THROUGH-SILICON VIA STRUCTURE

Номер: US20130224909A1
Автор: Chiou Wen-Chih, LIN Yung-Chi, Wu Weng-Jin
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

In a process, an opening is formed to extend from a front surface of a semiconductor substrate through at least a part of the semiconductor substrate. A metal seed layer is formed on a sidewall of the opening. A metal silicide layer is formed on at least one portion of the metal seed layer. A metal layer is formed on the metal silicide layer and the metal seed layer to fill the opening. 1. A process , comprising:forming an opening extending from a front surface of a semiconductor substrate through at least a part of the semiconductor substrate;forming a metal seed layer on a sidewall of the opening;forming a metal silicide layer on at least one portion of the metal seed layer; andforming a metal layer on the metal silicide layer and the metal seed layer to fill the opening.2. The process of claim 1 , wherein the metal silicide layer comprises copper.3. The process of claim 1 , wherein the metal layer comprises copper claim 1 , and the metal seed layer comprises copper.4. The process of claim 1 , further comprising:forming a barrier layer lining the opening before forming the metal seed layer, wherein barrier layer comprises at least one selected from the group consisting of TaN, Ta, TiN, and Ti.5. The process of claim 4 , further comprising:forming a passivation layer lining the opening before forming the barrier layer.6. The process of claim 5 , wherein the passivation layer comprises silicon oxide.7. The process of claim 1 , further comprising:performing a thinning process on a back surface of the semiconductor substrate to expose an end of the metal layer.8. The process of claim 7 , further comprising:stacking a semiconductor component on the back surface of the semiconductor substrate, the semiconductor component electrically connected to the exposed end of the metal layer.9. A process claim 7 , comprising:forming an opening extending from a front surface of a semiconductor substrate through at least a part of the semiconductor substrate;forming a metal seed ...

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Номер записи: 66
05-09-2013 дата публикации

Methods and layers for metallization

Номер: US20130228923A1
Автор: Artur Kolics, NALLA Praveen
Принадлежит: Individual

One aspect of the present invention is a method of making an electronic device. According to one embodiment, the method comprises depositing a cap layer containing at least one dopant onto a gapfill metal and annealing so that the at least one dopant migrates to grain boundaries and/or interfaces of the gapfill metal. Another aspect of the present invention is an electronic device.

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Номер записи: 67
05-09-2013 дата публикации

COPPER INTERCONNECTS HAVING A TITANIUM-PLATINUM-TITANIUM ASSEMBLY BETWEEN COPPER AND COMPOUND SEMICONDUCTOR

Номер: US20130228924A1
Автор: Cheng Kezia
Принадлежит: SKYWORKS SOLUTIONS, INC.

Disclosed are devices and methods related to metallization of semiconductors. A metalized structure can include a first titanium (Ti) layer disposed over a compound semiconductor, a first barrier layer disposed over the first Ti layer, a second Ti layer disposed over the first barrier layer, and a copper (Cu) layer disposed over the second Ti layer. The second Ti layer can be configured to inhibit or reduce alloying of the Cu layer and the first barrier layer. The first Ti layer, the first barrier layer, and the second Ti layer can be configured to yield a barrier between the Cu layer and an ohmic metal layer formed on the compound semiconductor. The metalized structure can further include a third Ti layer disposed over the Cu layer and a second barrier layer disposed over the third Ti layer. The first and second barrier layers can include platinum (Pt) and/or palladium (Pd). 1. A metalized structure for a compound semiconductor device , the structure comprising:a first titanium (Ti) layer disposed over a substrate associated with the compound semiconductor device;a first barrier layer disposed over the first Ti layer;a second Ti layer disposed over the first barrier layer; anda copper (Cu) layer disposed over the second Ti layer, the second Ti layer configured to inhibit alloying of the Cu layer and the barrier layer.2. The structure of wherein the first Ti layer claim 1 , the first barrier layer claim 1 , and the second Ti layer are configured to yield a barrier between the Cu layer and an ohmic metal layer formed on the substrate.3. The structure of wherein the first barrier layer includes platinum (Pt) claim 1 , palladium (Pd) claim 1 , or nickel (Ni).4. The structure of further comprising a third Ti layer disposed over the Cu layer and a second barrier layer disposed over the third Ti layer.5. The structure of wherein the second barrier layer includes platinum (Pt) claim 4 , palladium (Pd) claim 4 , or nickel (Ni).6. The structure of wherein thicknesses of the ...

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Номер записи: 68
05-09-2013 дата публикации

INTERCONNECTION STRUCTURE

Номер: US20130228926A1
Автор: Kugimiya Toshihiro, Maeda Takeaki
Принадлежит: Kabushiki Kaisha Kobe Seiko Sho (Kobe Steel, Ltd.)

Provided is an interconnection structure that, in a display device such as an organic EL display or a liquid crystal display, has superior workability during wet etching even without providing an etch stop layer. The interconnection structure has, in the given order, a substrate, a semiconductor layer of a thin film transistor, and a metal interconnection film, and has a barrier layer between the semiconductor layer and the metal interconnection film. The semiconductor layer comprises an oxide semiconductor, the barrier layer has a layered structure of a high-melting-point metal thin film and a Si thin film, and the Si thin film is directly connected to the semiconductor layer. 1. An interconnection structure , comprising:a substrate;a semiconductor layer for a thin film transistor on the substrate;a metal interconnection film on the semiconductor layer; anda barrier layer between the semiconductor layer and the metal interconnection film,wherein the semiconductor layer comprises oxide semiconductor, andthe barrier layer has a stacked structure of a high-melting-point-metal thin film and a Si thin film, in which the Si thin film is directly connected to the semiconductor layer.2. The interconnection structure according to claim 1 , wherein the high-melting-point-metal thin film is configured of one selected from the group consisting of a pure Ti thin film claim 1 , a Ti alloy thin film claim 1 , a pure Mo thin film claim 1 , and a Mo alloy thin film.3. The interconnection structure according to claim 1 , wherein the Si thin film has a thickness of from 3 to 30 nm.4. The interconnection structure according to claim 1 , wherein the metal interconnection film is configured of one selected from the group consisting of a pure Al film claim 1 , an Al alloy film comprising at least 90 at % Al claim 1 , a pure Cu film claim 1 , and a Cu alloy film comprising at least 90 at % Cu.5. The interconnection structure according to claim 1 , wherein the oxide semiconductor is ...

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Номер записи: 69
05-09-2013 дата публикации

Interconnect structures

Номер: US20130228927A1
Автор: Chen-Hua Yu, Hai-Ching Chen, Tien-I Bao
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor structure includes a first dielectric layer over a substrate. At least one first conductive structure is within the first dielectric layer. The first conductive structure includes a cap portion extending above a top surface of the first dielectric layer. At least one first dielectric spacer is on at least one sidewall of the cap portion of the first conductive structure.

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Номер записи: 70
12-09-2013 дата публикации

INTERCONNECT STRUCTURE FOR IMPROVED TIME DEPENDENT DIELECTRIC BREAKDOWN

Номер: US20130234260A1
Автор: Cabral, Engelmann Sebastian U., Fletcher Benjamin, Joseph Eric A., JR. Cyril, Nitta Satyanarayana V.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

The present disclosure provides a method of forming an interconnect to an electrical device. In one embodiment, the method of forming an interconnect includes providing a device layer on a substrate, wherein the device layer comprises at least one electrical device, an intralevel dielectric over the at least one electrical device, and a contact that is in electrical communication with the at least one electrical device. An interconnect metal layer is formed on the device layer, and a tantalum-containing etch mask is formed on a portion of the interconnect metal layer. The interconnect metal layer is etched to provide a trapezoid shaped interconnect in communication with the at least one electrical device. The trapezoid shaped interconnect has a first surface that is in contact with the device layer with a greater width than a second surface of the trapezoid shaped interconnect that is in contact with the tantalum-containing etch mask. 1. A method of forming an interconnect comprising:providing a device layer on a substrate, wherein the device layer comprises at least one electrical device, an intralevel dielectric over the at least one electrical device, and a contact in electrical communication with the at least one electrical device;forming an metal seed layer on the device layer;forming an interlevel dielectric layer on the metal seed layer;etching a trapezoid shaped via in the interlevel dielectric layer exposing a first portion of the metal seed layer, wherein a first width of a first opening of the trapezoid shaped via at an interface between the interlevel dielectric layer and the metal seed layer is greater than a second width of a second opening of the trapezoid shaped via at a surface of the interlevel dielectric layer that is opposite the interface of the interlevel dielectric layer and the metal seed layer; andfilling the trapezoid shaped via with an interconnect metal to provide a trapezoid shaped interconnect in electrical communication with the ...

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Номер записи: 71
12-09-2013 дата публикации

COPPER INTERCONNECTS HAVING A TITANIUM-TITANIUM NITRIDE ASSEMBLY BETWEEN COPPER AND COMPOUND SEMICONDUCTOR

Номер: US20130234333A1
Автор: Cheng Kezia
Принадлежит: SKYWORKS SOLUTIONS, INC.

Disclosed are devices and methods related to metallization of semiconductors. A metalized structure can include a first titanium (Ti) layer disposed over a compound semiconductor, a first titanium nitride (TiN) layer disposed over the first Ti layer, and a copper (Cu) layer disposed over the first TiN layer. The first Ti layer and the first TiN layer can be configured as a barrier between the Cu layer and the compound semiconductor. The metalized structure can further include a second TiN layer disposed over the Cu layer and a first platinum (Pt) layer disposed over the second TiN layer. 1. A metalized structure for a compound semiconductor device , the structure comprising:a first titanium (Ti) layer disposed over a substrate associated with the compound semiconductor device;a first titanium nitride (TiN) layer disposed over the first Ti layer; anda copper (Cu) layer disposed over the first TiN layer.2. The structure of wherein the first Ti layer and the first TiN layer are configured to yield a barrier between the Cu layer and the substrate.3. The structure of further comprising a second TiN layer disposed over the Cu layer and a first platinum (Pt) layer disposed over the second TiN layer.4. The structure of wherein a thickness of the first TiN layer is selected to provide sufficient barrier functionality between the Cu layer and an ohmic metal layer disposed between the first Ti layer and the substrate.5. The structure of wherein the first Ti layer has a thickness of approximately 1 claim 4 ,000 angstroms claim 4 , and the first TiN layer has a thickness of approximately 500 angstroms.6. The structure of wherein the Cu layer has a thickness selected to yield a resistivity value similar to that of a gold layer being replaced by the Cu layer.7. The structure of wherein the Cu layer has a thickness of approximately 25 claim 6 ,000 angstroms.8. The structure of further comprising a gold (Au) layer disposed over the first Pt layer.9. The structure of further ...

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Номер записи: 72
26-09-2013 дата публикации

Semiconductor device and manufacturing method thereof

Номер: US20130249084A1
Автор: Naoki Fujimoto, Tatsuya Usami, Tomoyuki Nakamura
Принадлежит: Renesas Electronics Corp

A semiconductor device includes an interlayer insulating film containing Si, O, C, and H, an under-bump metal film disposed over the interlayer insulating film and containing Ni, and a bump electrode disposed over the under-bump metal film. In the interlayer insulating film, a ratio of a peak height of Si—CH 3 near a wave number 1270 cm −1 to a peak height of Si—O near a wave number 1030 cm −1 obtained by Fourier-transform infrared spectroscopy (FTIR) is 0.15 or greater and 0.27 or less. A ratio of a peak height of Si—CH 2 —Si near a wave number 1360 cm −1 to the peak height of Si—CH 3 near the wave number 1270 cm −1 is 0.031 or greater.

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Номер записи: 73
26-09-2013 дата публикации

Schemes for Forming Barrier Layers for Copper in Interconnect Structures

Номер: US20130249097A1
Автор: BAO Tien-I, CHEN Hai-Ching, Yu Chen-Hua
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided. 1. A semiconductor structure comprising:a dielectric layer over a substrate;an opening extending from a top surface of the dielectric layer into the dielectric layer;a first barrier layer lining the opening;a conductive wiring in a remaining portion of the opening, wherein a top edge of the first barrier layer is recessed from at least a portion of a sidewall of the conductive wiring; anda second barrier layer covering a top surface and the portion of the sidewall of the conductive wiring, wherein the second barrier layer does not extend over the dielectric layer.2. The semiconductor structure of claim 1 , wherein the first barrier layer comprises a metal that can be silicided.3. The semiconductor structure of claim 2 , wherein the metal comprises a material selected from the group consisting essentially of cobalt claim 2 , nickel claim 2 , and combinations thereof.4. The semiconductor structure of claim 1 , wherein the first barrier layer is free from cobalt and nickel.5. The semiconductor structure of claim 1 , wherein the conductive wiring comprises copper.6. The semiconductor structure of claim 1 , wherein the second barrier layer is a derivative of a carbon-based silane.7. A semiconductor device comprising:a conductive material embedded within a dielectric layer over a substrate, the conductive material being planar with the dielectric layer;a first barrier ...

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Номер записи: 74
03-10-2013 дата публикации

DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF

Номер: US20130256892A1
Автор: Osame Mitsuaki, Yamazaki Shunpei
Принадлежит: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

It is an object of the present invention to prevent an influence of voltage drop due to wiring resistance, trouble in writing of a signal into a pixel, and trouble in gray scales, and provide a display device with higher definition, represented by an EL display device and a liquid crystal display device. 1. (canceled)2. A display device comprising:a first wiring;an insulating film over the first wiring;a second wiring over the insulating film; anda semiconductor film under the insulating film,wherein the first wiring is electrically connected to the semiconductor film through a first opening of the insulating film,wherein the second wiring is electrically connected to the semiconductor film through a second opening of the insulating film,wherein the first wiring overlaps with the second wiring,wherein the second wiring comprises a first layer comprising titanium and a second layer comprising copper,wherein the second layer is over and in contact with the first layer, andwherein a width of the second layer is narrower than a width of the first layer.3. The display device according to claim 2 , wherein the second layer comprises a first conductive layer comprising titanium and a second conductive layer comprising titanium nitride.4. The display device according to claim 3 , wherein the second conductive layer is a conductive barrier film.5. The display device according to claim 2 , wherein the second wiring is a taken-around wiring which is electrically connected to a FPC.6. The display device according to claim 2 , wherein the semiconductor film comprises silicon.7. The display device according to claim 2 , wherein the semiconductor film has a zigzag shape.8. A display device comprising:a first wiring;an insulating film over the first wiring;a second wiring and a third wiring over the insulating film; anda semiconductor film under the insulating film,wherein the first wiring is in contact with the third wiring through a first opening of the insulating film,wherein ...

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Номер записи: 75
17-10-2013 дата публикации

Formation of dram capacitor among metal interconnect

Номер: US20130271938A1
Автор: Joseph M. Steigerwald, Kanwal Jit Singh, Nick Lindert
Принадлежит: Intel Corp

Techniques are disclosed for integrating capacitors among the metal interconnect for embedded DRAM applications. In some embodiments, the technique uses a wet etch to completely remove the interconnect metal (e.g., copper) that is exposed prior to the capacitor formation. This interconnect metal removal precludes that metal from contaminating the hi-k dielectric of the capacitor. Another benefit is increased height (surface area) of the capacitor, which allows for increased charge storage. In one example embodiment, an integrated circuit device is provided that includes a substrate having at least a portion of a DRAM bit cell circuitry, an interconnect layer on the substrate and including one or more metal-containing interconnect features, and a capacitor at least partly in the interconnect layer and occupying space from which a metal-containing interconnect feature was removed. The integrated circuit device can be, for example, a processor or a communications device.

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Номер записи: 76
24-10-2013 дата публикации

Method for Producing a Conductor Line

Номер: US20130280879A1
Автор: Andreas Zankl, Anja Gissibl, Markus Menath, Matthias Stecher
Принадлежит: INFINEON TECHNOLOGIES AUSTRIA AG

A method for producing a rounded conductor line of a semiconductor component is disclosed. In that method, a partially completed semiconductor component is provided. The partially completed semiconductor component has a bottom side and a top side spaced distant from the bottom side in a vertical direction. Also provided is an etchant. On the top side, a dielectric layer is arranged. The dielectric layer has at least two different regions that show different etch rates when they are etched with the etchant. Subsequently, a trench is formed in the dielectric layer such that the trench intersects each of the different regions. Then, the trench is widened by etching the trench with the etchant at different etch rates. By filling the widened trench with an electrically conductive material, a conductor line is formed.

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Номер записи: 77
07-11-2013 дата публикации

Semiconductor device and method of fabricating

Номер: US20130292794A1
Автор: Chih-Yang Pai, Chung-Yen Chou, Kuo-Chi Tu, Wen-Chuan Chiang
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A semiconductor device includes a semiconductor substrate, an isolation structure disposed in the semiconductor substrate, a conductive layer disposed over the isolation structure, a capacitor disposed over the isolation structure, the capacitor including a top electrode, a bottom electrode, and a dielectric disposed between the top electrode and the bottom electrode, and a first contact electrically coupling the conductive layer and the bottom electrode, the bottom electrode substantially engaging the first contact on at least two faces.

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Номер записи: 78
14-11-2013 дата публикации

Semiconductor Device and Manufacturing Method Thereof

Номер: US20130299991A1
Автор: TANAKA Tetsuhiro
Принадлежит: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

A semiconductor film having an impurity region to which at least an n-type or p-type impurity is added and a wiring are provided. The wiring includes a diffusion prevention film containing a conductive metal oxide, and a low resistance conductive film over the diffusion prevention film. In a contact portion between the wiring and the semiconductor film, the diffusion prevention film and the impurity region are in contact with each other. The diffusion prevention film is framed in such a manner that a conductive film is exposed to plasma generated from a mixed gas of an oxidizing gas and a halogen-based gas to form an oxide of a metal material contained in the conductive film, the conductive film in which the oxide of the metal material is formed is exposed to an atmosphere containing water to be fluidized, and the fluidized conductive film is solidified. 1. A semiconductor device comprising:a semiconductor film comprising an impurity region to which an impurity imparting one conductive type is added; and a diffusion prevention film comprising a conductive metal oxide; and', 'a low resistance conductive film over the diffusion prevention film, and, 'a wiring over the semiconductor film, wherein the wiring compriseswherein in a contact portion between the wiring and the semiconductor film, the diffusion prevention film and the impurity region are in contact with each other.2. The semiconductor device according to claim 1 , wherein the diffusion prevention film comprises one or more of titanium claim 1 , nickel claim 1 , zinc claim 1 , gallium claim 1 , zirconium claim 1 , niobium claim 1 , molybdenum claim 1 , indium claim 1 , tin claim 1 , and tungsten.3. The semiconductor device according to claim 1 , wherein the conductive metal oxide comprises fluorine at a concentration of 1×10atoms/cmor higher.4. The semiconductor device according to claim 1 , wherein the conductive metal oxide is an oxide of a metal element included in the diffusion prevention film.5. The ...

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Номер записи: 79
14-11-2013 дата публикации

Semiconductor device

Номер: US20130300001A1
Автор: Satoshi Kageyama, Yuichi Nakao
Принадлежит: ROHM CO LTD

The semiconductor device according to the present invention includes a semiconductor layer, an interlayer dielectric film formed on the semiconductor layer, a wire formed on the interlayer dielectric film with a metallic material to have a width of not more than 0.4 μm, and a broad portion integrally formed on the wire to extend from the wire in the width direction thereof.

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Номер записи: 80
21-11-2013 дата публикации

Method to resolve hollow metal defects in interconnects

Номер: US20130307151A1
Автор: Andrew H. Simon, Griselda Bonilla, Junjing Bao, Naftali E. Lustig, Ronald G. Filippi, Samuel S. Choi
Принадлежит: International Business Machines Corp

A method of repairing hollow metal void defects in interconnects and resulting structures. After polishing interconnects, hollow metal void defects become visible. The locations of the defects are largely predictable. A repair method patterns a mask material to have openings over the interconnects (and, sometimes, the adjacent dielectric layer) where defects are likely to appear. A local metal cap is formed in the mask openings to repair the defect. A dielectric cap covers the local metal cap and any recesses formed in the adjacent dielectric layer.

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Номер записи: 81
21-11-2013 дата публикации

Interconnect with titanium-oxide diffusion barrier

Номер: US20130307153A1
Автор: Daniel C. Edelstein, Takeshi Nogami
Принадлежит: International Business Machines Corp

An interconnect structure located on a semiconductor substrate within a dielectric material positioned atop the semiconductor substrate is provided having an opening within the dielectric material, the opening includes an electrically conductive material extending from the bottom to the top, and contacting the sidewall; a first layer located on the sidewall of the opening, the first layer is made from a material including titanium oxide or titanium silicon oxide; a second layer located between the first layer and the electrically conductive material, the second layer is made from a material selected from the group TiXO b , TiXSi a O b , XO b , and XSi a O b , X is Mn, Al, Sn, In, or Zr; and a third layer located along a top surface of the electrically conductive material, the third layer is made from a material selected from the group TiXO b , TiXSi a O b , XO b , and XSi a O b , X is Mn, Al, Sn, In, or Zr.

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Номер записи: 82
21-11-2013 дата публикации

SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING SAME

Номер: US20130309864A1
Автор: Barth Hans-Joachim, BEER Gottfried, Plagmann Joern, POHL Jens, Robl Werner, STEINER Rainer, Vaupel Mathias
Принадлежит:

One or more embodiments relate to a method of forming a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a seed layer over the barrier layer; forming an inhibitor layer over the seed layer; removing a portion of said inhibitor layer to expose a portion of the seed layer; and selectively depositing a fill layer on the exposed seed layer. 1. A method of forming a semiconductor structure , comprising:providing a workpiece;forming a barrier layer over said workpiece;forming a seed layer over said barrier layer;forming an inhibitor layer over said seed layer;removing a portion of said inhibitor layer to expose a portion of said seed layer; andselectively depositing a fill layer on said exposed seed layer.2. The method of claim 1 , wherein said selective deposition includes a process selected from the group consisting of electroplating claim 1 , electroless plating claim 1 , and chemical vapor deposition.3. The method of claim 1 , wherein substantially none of said fill layer selectively deposits on said inhibitor layer.4. The method of claim 3 , wherein said fill layer spills over said inhibitor layer.5. The method of claim 1 , wherein said removing said portion of said inhibitor layer comprises laser ablation.6. The method of claim 1 , wherein said fill layer and/or said seed layer comprises copper metal and/or a copper alloy.7. The method of claim 1 , wherein said barrier layer and/or said inhibitor layer comprises Ta (tantalum).8. The method of claim 1 , wherein said workpiece includes an opening claim 1 , said barrier layer formed within said opening.9. A method of forming an electronic device claim 1 , comprising:providing a workpiece;forming a barrier layer over said workpiece;forming a seed layer over said barrier layer;forming an inhibitor layer over said seed layer;removing a portion of said inhibitor layer to expose a portion of said seed layer; andforming a fill layer on said exposed seed layer, ...

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Номер записи: 83
05-12-2013 дата публикации

SEMICONDUCTOR DEVICE CONTACT STRUCTURES

Номер: US20130320541A1
Автор: Chang Chih-Chung, Chang Shih-Chieh, Chen Kei-Wei, Wang Ying-Lang
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

Semiconductor contact structures extend through a dielectric material and provide contact to multiple different subjacent materials including a silicide material and a non-silicide material such as doped silicon. The contact structures includes a lower composite layer formed using a multi-step ionized metal plasma (IMP) deposition operation. A lower IMP film is formed at a high AC bias power followed by the formation of an upper IMP film at a lower AC bias power. The composite layer may be formed of titanium. A further layer is formed as a liner over the composite layer and the liner layer may advantageously be formed using CVD and may be TiN. A conductive plug material such as tungsten or copper fills the contact openings. 1. A semiconductor device comprising:a contact structure disposed within a contact opening extending through a dielectric layer and terminating at a bottom surface;said contact structure comprising an inner tungsten plug surrounded by a TiN layer surrounded laterally and subjacently by an inner layer of a first material having a first resistivity, said inner layer surrounded laterally and subjacently by an outer layer of said first material having a second resistivity that is lower than said first resistivity, said outer layer contacting said bottom surface, said first material comprising one of titanium and cobalt.2. The semiconductor device as in claim 1 , wherein said bottom surface comprises a silicide surface and said inner layer and said outer layer have a combined thickness of about 250 angstroms or more.3. The semiconductor device as in claim 2 , further comprising a further contact structure disposed within a further contact opening extending through said dielectric layer and wherein said further contact opening terminates at a further bottom surface comprising silicon with a dopant impurity therein.4. The semiconductor device as in claim 1 , wherein said first resistivity is greater than 95 uohm-cm claim 1 , said second resistivity is ...

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Номер записи: 84
05-12-2013 дата публикации

Corrosion/etching protection in integration circuit fabrications

Номер: US20130320544A1
Автор: Son Nguyen, Tuan A. Vo, Vamsi Paruchuri, Wei Lin
Принадлежит: International Business Machines Corp

A method of producing reduced corrosion interconnect structures and structures thereby formed. A method of producing microelectronic interconnects having reduced corrosion begins with a damascene structure having a first dielectric and a first interconnect. A metal oxide layer is deposited selectively to metal or nonselective over the damascene structure and then thermally treated. The treatment converts the metal oxide over the first dielectric to a metal silicate while the metal oxide over the first interconnect remains as a self-aligned protective layer. When a subsequent dielectric stack is formed and patterned, the protective layer acts as an etch stop, oxidation barrier and ion bombardment protector. The protective layer is then removed from the patterned opening and a second interconnect formed. In a preferred embodiment the metal oxide is a manganese oxide and the metal silicate is a MnSiCOH, the interconnects are substantially copper and the dielectric contains ultra low-k.

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Номер записи: 85
05-12-2013 дата публикации

HYBRID COPPER INTERCONNECT STRUCTURE AND METHOD OF FABRICATING SAME

Номер: US20130320545A1
Автор: Horak David V., III Charles W., Koburger, Ponoth Shom, Yang Chih-Chao
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A hybrid interconnect structure containing copper regions that have different impurities levels within a same opening is provided. In one embodiment, the interconnect structure includes a patterned dielectric material having at least one opening located therein. A dual material liner is located at least on sidewalls of the patterned dielectric material within the at least one opening. The structure further includes a first copper region having a first impurity level located within a bottom region of the at least one opening and a second copper region having a second impurity level located within a top region of the at least one opening and atop the first copper region. In accordance with the present disclosure, the first impurity level of the first copper region is different from the second impurity level of the second copper region. 1. An interconnect structure comprising:a patterned dielectric material having at least one opening located therein;a dual material liner located at least on sidewalls of the patterned dielectric material within the at least one opening;a first copper region containing a first impurity level located within a bottom region of said at least one opening; anda second copper region containing a second impurity level located within a top region of said at least one opening and atop the first copper region, wherein said first impurity level of said first copper region is less than the second impurity level of said second copper region.2. The interconnect structure of claim 1 , wherein said second impurity level of the second copper region has an amount of impurities of 100 ppm or greater claim 1 , and the first impurity level of said first copper region has an amount of impurities of less than 20 ppm.3. The interconnect structure of claim 2 , wherein said impurities within said second impurity level of said second region of copper comprises at least one of carbon claim 2 , chloride claim 2 , oxygen and sulfur.4. The interconnect structure of ...

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Номер записи: 86
12-12-2013 дата публикации

ELECTRONIC DEVICE AND METHOD FOR PRODUCTION

Номер: US20130328197A1
Автор: Hosseini Khalil, Stecher Matthias
Принадлежит: INFINEON TECHNOLOGIES AG

An electronic device and method for production is disclosed. One embodiment provides an integrated component having a first layer which is composed of copper or a copper alloy or which contains copper or a copper alloy, and having an electrically conductive second layer, whose material differs from the material of the first layer, and a connection apparatus which is arranged on the first layer and on the second layer. 1. An electronic device comprising:a copper bonding wire bonded to a metallization stack; a first layer comprising copper;', 'a second layer made from a material differing from a material of the first layer; and', 'a barrier layer arranged between the first layer and the second layer., 'wherein the metallization stack comprises2. The electronic device of claim 1 , wherein the first layer is a substantially flat copper pad.3. The electronic device of claim 1 , wherein the barrier layer is thinner than the first layer and thinner than the second layer.4. The electronic device of claim 1 , wherein the barrier layer has a thickness in the range of 1 nanometer to about 20 nanometers.5. The electronic device of claim 1 , wherein the barrier layer comprises a metal from the forth or sixth group in the periodic table.6. The electronic device of claim 1 , wherein the barrier layer comprises at least one of titanium claim 1 , titanium nitride claim 1 , tantalum claim 1 , tantalum nitride and tungsten.7. The electronic device of claim 1 , wherein the second layer comprises at least one of aluminum or an aluminum alloy.8. The electronic device of claim 1 , wherein the second layer has a thickness in the range of 1 nanometer to about 5 micrometer.9. The electronic device of claim 1 , wherein the copper bonding wire at least partially passes through the second layer.10. The electronic device of claim 1 , wherein the copper bonding wire at least partially passes through the second layer and contacts the barrier layer.11. The electronic device of claim 1 , wherein the ...

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Номер записи: 87
12-12-2013 дата публикации

REVERSE DAMASCENE PROCESS

Номер: US20130328198A1
Автор: Chou You-Hua, Hong Min Hao, Hsiang Ko Hsiang, Liao Miao-Cheng, Tsai Jian-Shin
Принадлежит: Taiwan Semiconductor Manufacturing Co., Ltd.

The present disclosure relates to a method of forming a back-end-of-the-line metallization layer. The method is performed by forming a plurality of freestanding metal layer structures (i.e., metal layer structures not surrounded by a dielectric material) on a semiconductor substrate within an area defined by a patterned photoresist layer. A diffusion barrier layer is deposited onto the metal layer structure in a manner such that the diffusion barrier layer conforms to the top and sides of the metal layer structure. A dielectric material is formed on the surface of the substrate to fill areas between metal layer structures. The substrate is planarized to remove excess metal and dielectric material and to expose the top of the metal layer structure. 1. A metallization layer , comprising:a metal layer structure disposed over a semiconductor substrate;a nitride free under metal metallurgy (UMM) metal seed layer extending along a bottom surface the metal layer structure, wherein sidewalls of UMM metal seed layer are aligned with sidewalls of the metal layer structure along a straight line;a nitride based diffusion barrier layer which conforms to the sidewalls of the metal layer structure; andan inter-level dielectric material located between metal layer structures.2. The metallization layer of claim 1 , further comprising a nitride free dielectric film disposed below the UMM layer.3. The metallization layer of claim 2 , wherein the nitride free dielectric film comprises Trimethoxysilane-based silicon dioxide.4. The metallization layer of claim 1 , wherein the nitride based diffusion barrier layer comprises titanium nitride (TiN) claim 1 , tantalum silicon nitride (TaSiN) claim 1 , titanium silicon nitride (TiSiN) claim 1 , tantalum aluminum nitride (TaAIN) claim 1 , tantalum nitride (TaN) claim 1 , or hafnium nitride (HfN).5. The metallization layer of claim 1 , wherein the metal layer structure has linear sidewalls claim 1 , which extend along a straight line.6. The ...

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Номер записи: 88
19-12-2013 дата публикации

Sidewalls of electroplated copper interconnects

Номер: US20130334691A1
Автор: John A. Fitzsimmons, Mukta G. Farooq, Troy L. Graves-Abe
Принадлежит: International Business Machines Corp

A structure formed in an opening having a substantially vertical sidewall defined by a non-metallic material and having a substantially horizontal bottom defined by a conductive pad, the structure including a diffusion barrier covering the sidewall and a fill composed of conductive material. The structure including a first intermetallic compound separating the diffusion barrier from the conductive material, the first intermetallic compound comprises an alloying material and the conductive material, and is mechanically bound to the conductive material, the alloying material is at least one of the materials selected from the group of chromium, tin, nickel, magnesium, cobalt, aluminum, manganese, titanium, zirconium, indium, palladium, and silver; and a first high friction interface located between the diffusion barrier and the first intermetallic compound and parallel to the sidewall of the opening, wherein the first high friction interface results in a mechanical bond between the diffusion barrier and the first intermetallic compound.

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Номер записи: 89
02-01-2014 дата публикации

Electronic device including interconnects with a cavity therebetween and a process of forming the same

Номер: US20140001650A1
Автор: Jay P. John, Vishal P. Trivedi
Принадлежит: FREESCALE SEMICONDUCTOR INC

A process of forming an electronic device can include providing a first interconnect over a substrate having a primary surface, depositing a first insulating layer over the first interconnect, and patterning the first insulating layer to define an opening extending towards the first interconnect. The process can also include depositing a second insulating layer over the first insulating layer to seal the opening and form a cavity within the first opening, and forming a second interconnect over the first and second insulating layers. The cavity can be disposed between the first interconnect and the second interconnect. In another aspect, an electronic device can include a first interconnect, a first insulating layer defining a cavity, and a second interconnect. The cavity can be disposed between the first interconnect and the second interconnect, and a via may not be exposed within the cavity.

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Номер записи: 90
09-01-2014 дата публикации

Cost-Effective TSV Formation

Номер: US20140008802A1
Автор: CHANG Hung-Pin, Chiou Wen-Chih, LIN Yung-Chi, WU Tsang-Jiuh, YANG Ku-Feng
Принадлежит: Taiwan Semiconductor Manufacturing Company, Ltd.

A device includes a substrate having a first surface, and a second surface opposite the first surface. A through-substrate via (TSV) extends from the first surface to the second surface of the substrate. A dielectric layer is disposed over the substrate. A metal pad is disposed in the dielectric layer and physically contacting the TSV, wherein the metal pad and the TSV are formed of a same material, and wherein no layer formed of a material different from the same material is between and spacing the TSV and the metal pad apart from each other. 1. A device comprising:a substrate comprising a first surface, and a second surface opposite the first surface;a through-substrate via (TSV) extending from the first surface to the second surface of the substrate, wherein the TSV is formed of a continuous metallic material;a dielectric liner between the TSV and the substrate, wherein the dielectric liner extends over the first surface of the substrate;a dielectric layer over the substrate, wherein the dielectric layer is on a top surface of the dielectric liner; anda first metal pad in the dielectric layer and physically contacting the TSV, wherein the first metal pad is formed of the continuous metallic material.2. The device of claim 1 , wherein the dielectric layer is on a same side of the substrate as the first surface claim 1 , and wherein the device further comprises a barrier layer continuously extending from a top surface of the dielectric layer to the second surface of the substrate claim 1 , with the barrier layer separating the TSV from the substrate.3. The device of claim 1 , wherein the substrate is a semiconductor substrate claim 1 , and wherein the first metal pad is in a first metal layer immediately over an inter-layer dielectric.4. The device of claim 1 , wherein the substrate is a semiconductor substrate claim 1 , and wherein no active device is formed at the first and the second surfaces of the substrate.5. The device of claim 1 , wherein the substrate is a ...

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Номер записи: 91
09-01-2014 дата публикации

COPPER INTERCONNECTS SEPARATED BY AIR GAPS AND METHOD OF MAKING THEREOF

Номер: US20140008804A1
Автор: Kai James K., Liang Jarrett Jun, Matamis George, PACHAMUTHU Jayavel, Purayath Vinod R.
Принадлежит: SANDISK TECHNOLOGIES, INC.

A semiconductor device including a plurality of copper interconnects. At least a first portion of the plurality of copper interconnects has a meniscus in a top surface. The semiconductor device also includes a plurality of air gaps, wherein each air gap of the plurality of air gaps is located between an adjacent pair of at least the first portion of the plurality of bit lines. 1. A semiconductor device , comprising:a plurality of copper interconnects, at least a first portion of the plurality of copper interconnects having a meniscus in a top surface; anda plurality of air gaps, wherein each air gap of the plurality of air gaps is located between an adjacent pair of at least the first portion of the plurality of bit lines.2. The semiconductor device of claim 1 , further comprising a conformal liner on sidewalls of at least the first plurality of copper interconnects claim 1 , wherein the liner separates each of at least the first plurality of copper interconnects from two adjacent air gaps.3. The semiconductor device of claim 2 , further comprising a cap located in the meniscus on the top surface of at least the first portion of the plurality of copper interconnects.4. The semiconductor device of claim 3 , wherein the liner and the cap comprise tantalum nitride.5. The semiconductor device of claim 3 , further comprising a non-conformal insulating layer located over at least the first portion of the plurality of copper interconnects claim 3 , such that the non-conformal insulating layer does not completely fill spaces between at least the first portion of the plurality of copper interconnects to leave the plurality of air gaps.6. The semiconductor device of claim 5 , wherein the non-conformal insulating layer comprises a silicon oxide layer located in contact with the cap and an upper portion of the liner of at least the first portion of the plurality of copper interconnects.7. The semiconductor device of claim 1 , wherein the semiconductor device comprises a ...

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Номер записи: 92
23-01-2014 дата публикации

Thin film transistor array and el display employing thereof

Номер: US20140021496A1
Автор: Hirofumi Higashi, Nobuto HOSONO, Yoshiharu Hidaka
Принадлежит: Panasonic Corp

An EL display has a luminescence unit having a luminescence layer being disposed between the pair of electrodes, and a transistor array unit controlling the luminescence of the luminescence unit. An interlayer insulating film is disposed between the luminescence unit and the transistor array unit. An electrode of the luminescence unit is connected electrically to the transistor array unit via a contact hole provided in the interlayer insulation film. The transistor array unit has a wiring component made of copper or copper alloy. The wiring component has a lower layer pattern made of copper or copper alloy, and an upper layer pattern made of metal material different from that for the lower layer pattern. The upper layer pattern covers the upper surface and the side surface of the lower layer pattern.

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Номер записи: 93
23-01-2014 дата публикации

CHIP PACKAGES WITH POWER MANAGEMENT INTEGRATED CIRCUITS AND RELATED TECHNIQUES

Номер: US20140021522A1
Автор: Lee Jin-Yuan, Lin Mou-Shiung
Принадлежит: Megica Corporation

Chip packages having power management integrated circuits are described. Power management integrated circuits can be combined with on-chip passive devices, and can provide voltage regulation, voltage conversion, dynamic voltage scaling, and battery management or charging. The on-chip passive devices can include inductors, capacitors, or resistors. Power management using a built-in voltage regulator or converter can provide for immediate adjustment of the voltage range to that which is needed. This improvement allows for easier control of electrical devices of different working voltages and decreases response time of electrical devices. Related fabrication techniques are described. 1. A semiconductor chip comprising:a semiconductor substrate;a first double-diffused metal oxide semiconductor (DMOS) device on the semiconductor substrate;a second DMOS device on the semiconductor substrate;a capacitor coupled to the semiconductor substrate; andan inductor coupled to the semiconductor substrate, the inductor including a first terminal coupled to the first and second DMOS devices, and a second terminal coupled to the capacitor.2. The semiconductor chip of further comprising a passivation layer coupled to the semiconductor substrate and the capacitor claim 1 , the passivation layer comprising a nitride layer.3. The semiconductor chip of claim 2 , wherein the nitride layer comprises a silicon-nitride layer having a thickness greater than 0.3 micrometers.4. The semiconductor chip of further comprising a passivation layer coupled to the semiconductor substrate and the inductor claim 1 , the passivation layer comprising a nitride layer.5. The semiconductor chip of claim 4 , wherein the nitride layer comprises a silicon-nitride layer having a thickness greater than 0.3 micrometers.6. The semiconductor chip of further comprising a polymer layer coupled to the inductor.7. The semiconductor chip of further comprising a tin-containing joint at a bottom of the capacitor.8. The ...

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Номер записи: 94
30-01-2014 дата публикации

THREE-DIMENSIONAL INTEGRATED CIRCUIT LAMINATE, AND INTERLAYER FILLER FOR THREE-DIMENSIONAL INTEGRATED CIRCUIT LAMINATE

Номер: US20140027885A1
Автор: IKEMOTO Makoto, Kawase Yasuhiro, Kiritani Hideki
Принадлежит: MITSUBISHI CHEMICAL CORPORATION

To provide a three-dimensional integrated circuit laminate filled in with an interlayer filler composition having both high thermal conductivity and low linear expansion property. 1. A three-dimensional integrated circuit laminate , which comprises a semiconductor substrate laminate having at least two semiconductor substrates each having a semiconductor device layer formed thereon laminated , and has a first interlayer filler layer containing a resin (A) and an inorganic filler (B) and having a thermal conductivity of at least 0.8 W/(m·K) between the semiconductor substrates.2. The three-dimensional integrated circuit laminate according to claim 1 , wherein the coefficient of linear thermal expansion of the first interlayer filler layer is at least 3 ppm/K and at most 70 ppm/K.3. The three-dimensional integrated circuit laminate according to claim 1 , wherein the dielectric constant of the inorganic filler (B) contained in the first interlayer filler layer is at most 6.4. The three-dimensional integrated circuit laminate according to claim 1 , wherein the inorganic filler (B) contained in the first interlayer filler layer has an average particle size of at least 0.1 μm and at most 10 μm claim 1 , a maximum particle size of 10 μm claim 1 , and a thermal conductivity of at least 2 W/(m·K).5. A three-dimensional integrated circuit laminate claim 1 , which comprises a semiconductor substrate laminate having at least two semiconductor substrates each having a semiconductor device layer formed thereon laminated claim 1 , and has a first interlayer filler layer containing a resin (A) and an inorganic filler (B) and having a coefficient of linear thermal expansion of at least 3 ppm/K and at most 70 ppm/K between the semiconductor substrates claim 1 , and the inorganic filler (B) having an average particle size of at least 0.1 μm and at most 10 μm and a maximum particle size of 10 μm.6. A three-dimensional integrated circuit laminate claim 1 , which comprises a ...

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Номер записи: 95
30-01-2014 дата публикации

SIDEWALLS OF ELECTROPLATED COPPER INTERCONNECTS

Номер: US20140027911A1
Автор: Farooq Mukta G., Fitzsimmons John A., Graves-Abe Troy L.
Принадлежит: INTERNATIONAL BUSINESS MACHINES CORPORATION

A structure formed in an opening having a substantially vertical sidewall defined by a non-metallic material and having a substantially horizontal bottom defined by a conductive pad, the structure including a diffusion barrier covering the sidewall and a fill composed of conductive material. The structure including a first intermetallic compound separating the diffusion barrier from the conductive material, the first intermetallic compound comprises an alloying material and the conductive material, and is mechanically bound to the conductive material, the alloying material is at least one of the materials selected from the group of chromium, tin, nickel, magnesium, cobalt, aluminum, manganese, titanium, zirconium, indium, palladium, and silver; and a first high friction interface located between the diffusion barrier and the first intermetallic compound and parallel to the sidewall of the opening, wherein the first high friction interface results in a mechanical bond between the diffusion barrier and the first intermetallic compound. 1. A structure formed in an opening , the opening having a substantially vertical sidewall defined by a non-metallic material and having a substantially horizontal bottom defined by a conductive pad , the structure comprising a diffusion barrier covering the sidewall and a fill composed of conductive material , the structure comprising:a first intermetallic compound separating the diffusion barrier from the conductive material, wherein the first intermetallic compound comprises an alloying material and the conductive material, and is mechanically bound to the conductive material, wherein the alloying material is at least one of the materials selected from the group consisting of chromium, tin, nickel, magnesium, cobalt, aluminum, manganese, titanium, zirconium, indium, palladium, and silver; anda first high friction interface located between the diffusion barrier and the first intermetallic compound and parallel to the sidewall of the ...

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Номер записи: 96
06-02-2014 дата публикации

Forming Metal-Insulator-Metal Capacitors Over a Top Metal Layer

Номер: US20140038384A1
Автор: Chih-Hsun Lin, Kuan-Chi Tsai, Kun-Mao Wu, Yu-Lung Yeh
Принадлежит: Taiwan Semiconductor Manufacturing Co TSMC Ltd

A plurality of metal layers includes a top metal layer. An Ultra-Thick Metal (UTM) layer is disposed over the top metal layer, wherein no additional metal layer is located between the UTM layer and the top metal layer. A Metal-Insulator-Metal (MIM) capacitor is disposed under the UTM layer and over the top metal layer.

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Номер записи: 97
06-02-2014 дата публикации

Fluorine depleted adhesion layer for metal interconnect structure

Номер: US20140038407A1
Автор: Emily R. Kinser, Mukta G. Farooq
Принадлежит: International Business Machines Corp

A line trough and a via cavity are formed within a dielectric layer comprising a fluorosilicate glass (FSG) layer. A fluorine depleted adhesion layer is formed within the line trough and the via cavity either by a plasma treatment that removes fluorine from exposed surfaces of the FSG layer, or by deposition of a substantially fluorine-free dielectric layer. Metal is deposited within the line trough and the via cavity to form a metal line and a metal via. The fluorine depleted adhesion layer provides enhanced adhesion to the metal line compared with prior art structures in which a metal line directly contacts a FSG layer. The enhanced adhesion of metal with an underlying dielectric layer provides higher resistance to delamination for a semiconductor package employing lead-free C4 balls on a metal interconnect structure.

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Номер записи: 98
20-02-2014 дата публикации

SEMICONDUCTOR DEVICE HAVING METAL PLUG AND METHOD OF MANUFACTURING THE SAME

Номер: US20140048939A1
Автор: Choi Wonsang, Han Jeongnam, Kwon Kee-Sang, Park Sangjine, Yoon Boun
Принадлежит: SAMSUNG ELECTRONICS CO., LTD.

A semiconductor device includes a first insulating layer on a substrate; a first contact hole passing through the first insulating layer and exposing an upper surface of the substrate; a first barrier metal layer disposed on a sidewall and at a bottom of the first contact hole and a first metal plug disposed on the first barrier metal layer and in the first contact hole. A recess region is between the first insulating layer and the first metal plug. A gap-fill layer fills the recess region; and a second insulating layer is on the gap-fill layer. A second contact hole passes through the second insulating layer and exposes the upper surface of the first metal plug. A second barrier metal layer is on a sidewall and at the bottom of the second contact hole; and a second metal plug is on the second barrier metal layer. 1. A semiconductor device , comprising:a first insulating layer on a substrate;a first contact hole passing through the first insulating layer and exposing an upper surface of the substrate;a first barrier metal layer on a sidewall and at a bottom of the first contact hole;a first metal plug on the first barrier metal layer and in the first contact hole;a recess region between the first insulating layer and the first metal plug, the recess region defined by an upper surface of the barrier metal layer and sidewalls of the first metal plug and the first insulating layer, the upper surface of the first barrier metal layer being lower than upper surfaces of the first insulating layer and the first metal plug;a gap-fill layer filling the recess region;a second insulating layer on the gap-fill layer;a second contact hole passing through the second insulating layer and exposing the upper surface of the first metal plug, a bottom of the second contact hole overlapping with the recess region;a second barrier metal layer on a sidewall and at the bottom of the second contact hole; anda second metal plug on the second barrier metal layer, the second metal plug filling ...

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Номер записи: 99
20-02-2014 дата публикации

Semiconductor device including through via structures and redistribution structures

Номер: US20140048952A1
Автор: Byung-lyul Park, Gil-heyun Choi, Ho-Jin Lee, Kyu-Ha Lee, Pil-Kyu Kang, Tae-Yeong Kim
Принадлежит: SAMSUNG ELECTRONICS CO LTD

Semiconductor device including through via structure and redistribution structures is provided. The semiconductor device may include internal circuits on a first side of a substrate, a through via structure vertically penetrating the substrate to be electrically connected to one of the internal circuits, a redistribution structure on a second side of the substrate and electrically connected to the through via structure, and an insulating layer between the second side of the substrate and the redistribution structure. The redistribution structure may include a redistribution barrier layer and a redistribution metal layer, and the redistribution barrier layer may extend on a bottom surface of the redistribution metal layer and may partially surround a side of the redistribution metal layer.

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Номер записи: 100
06-03-2014 дата публикации

Electroplated Metallic Interconnects And Products

Номер: US20140061919A1
Автор: COHEN URI
Принадлежит:

One embodiment of the present invention is a device including at least a portion of a void-free electroplated metallic interconnect embedded in an opening, said opening having sidewalls, said sidewalls include at least one dielectric layer, wherein the opening has an aspect ratio in a range from 7:1 to 20:1, and wherein the portion of the electroplated metallic interconnect includes a material selected from a group consisting of Cu, Ag, and alloys including at least one of these metals. 1. A device comprising at least a portion of a void-free electroplated metallic interconnect embedded in an opening , said opening having sidewalls , said sidewalls comprising at least one dielectric layer , wherein the opening has an aspect ratio in a range from 7:1 to 20:1 , and wherein the portion of the electroplated metallic interconnect comprises a material selected from a group consisting of Cu , Ag , and alloys comprising at least one of these metals.2. The device of claim 1 , further comprising at least one seed layer disposed between the embedded portion of the electroplated metallic interconnect and the sidewalls of the opening.3. The device of claim 2 , further comprising one or more barrier layers disposed between the at least one seed layer and the sidewalls of the opening.4. The device of claim 3 , wherein at least one seed layer comprises a continuous PVD seed layer over the sidewalls of the opening.5. The device of claim 3 , wherein at least one seed layer comprises a continuous CVD seed layer over the sidewalls of the opening.6. The device of claim 5 , wherein the CVD seed layer comprises a continuous ALD seed layer over the sidewalls of the opening.7. The device of claim 5 , further comprising a PVD seed layer disposed between the embedded portion of the electroplated metallic interconnect and the CVD seed layer over the sidewalls of the opening.8. The device of claim 5 , further comprising a PVD seed layer disposed between the CVD seed layer and the one or more ...

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Номер записи: 101