IMPATT-DIODE.

In an IMPATT diode consisting of a monocrystalline silicon substrate, on which is applied a heterostructure semiconductor layer sequence comprising an alternating arrangement of at least two different semiconductor layers forming one or more hetero-junctions, the novelty is that the generation zone contains at least one SiGe layer (2).

Silizium-Germanium-Heterobipolartransistor

Mehrere Verspannungszustände in epitaktischem Transistorkanalmaterial durch Einbau von Spannungsentlastungsdefekten in ein zugrunde liegendes Keimmaterial

Mehrere Verspannungszustände in epitaktischem Transistorkanalmaterial können durch Einbau von Spannungsentlastungsdefekten in ein Keimmaterial erreicht werden. Die selektive Anwendung von Verspannung kann die Kanalmobilität eines Trägertyps verbessern, ohne die Kanalmobilität des anderen Trägertyps zu behindern. Eine Transistorstruktur kann eine heteroepitaktische Finne aufweisen, die eine erste Schicht aus kristallinem Material direkt auf einer zweiten Schicht aus kristallinem Material aufweist. Innerhalb der zweiten Schicht sind eine Anzahl defekter Bereiche mit einer Schwellenminimaldimension vorhanden, wodurch die erste Schicht aus kristallinem Material veranlasst wird, sich in einen Zustand geringerer Verspannung zu entspannen. Die defekten Bereiche können selektiv eingeführt werden, beispielsweise durch eine maskierte Verunreinigungsimplantation, so dass die defekten Bereiche in einigen Transistorstrukturen fehlen können, in denen ein Zustand mit höherer Verspannung in der ersten ...

Verfahren zur selecktiven Dotierung von dem Kollektor eines vertikalen bipolaren Transistors mit epitaxialer Basis

VERFAHREN ZUR GEZIELTEN HERSTELLUNG VON N-LEITENDEN BEREICHEN IN DIAMANTSCHICHTEN MITTELS IONENIMPLANTATION

Replacement gate electrode with planar work function material layers

In a replacement gate scheme, a continuous material layer is deposited on a bottom surface and a sidewall surface in a gate cavity. A vertical portion of the continuous material layer is removed to form a gate component of which a vertical portion does not extend to a top of the gate cavity. The gate component can be employed as a gate dielectric or a work function material portion to form a gate structure that enhances performance of a replacement gate field effect transistor.

PROCEDURE FOR THE PRODUCTION A DUAL GATE OF A FET

TRANSISTOR STRUCTURE.

Semiconductor nanocrystal heterostructures

GERMANIUM CHANNEL SILICON MOSFET

YO986-100 GERMANIUM CHANNEL SILICON MOSFET An alloy layer comprising germanium and silicon is grown on top of a silicon substrate. The alloy layer is kept thin enough for proper pseudomorphic, dislocation free growth. A layer of silicon is applied to the alloy layer. The initial silicon layer is from two to three times as thick as the alloy layer. Approximately the upper two-thirds of the silicon layer is oxidized, either thermally, anodically or by plasma anodization. The silicon layer that remains between the silicon dioxide and the alloy layer is kept thin enough so that a parasitic channel does not form on the interface between the silicon and the silicon dioxide. The germanium alloyed channel is thus suitably bounded by silicon crystalline structures on both of the channel layer surfaces. The barrier heights between silicon dioxide and silicon are very large thus providing good carrier confinement. A suitably applied voltage will result in a region of high mobility charge carriers ...

Improved strained-silicon CMOS device and method

一种特别适用于光学、电子学或光电子学器件的基片加工方法和由该方法获得的基片

... 本发明涉及一种加工基片的方法，该基片包括一构成机械支承的一层来承载的薄层；这一加工方法特别适用于光学、电子学或光电子学器件。根据本发明的方法包括以下步骤：自源基片(6)上分离一层材料，以形成薄层(2)；而后在薄层(2)上沉积材料制备一厚层(4)，以形成构成机械支承的所述层。 ...

Semiconductor device and method for producing same

Photoconductive member comprising amorphous germanium, amorphous silicon and nitrogen

METHOD FOR PREVENTING the BORON DIFFUSION IN a COMPOSANTSEMICONDUCTEUR BY CREATION OF BARRIERS Of NITROGEN, AND COMPOSING OBTAINED

METHOD FOR PREVENTING the BORON DIFFUSION IN a COMPOSANTSEMICONDUCTEUR BY CREATION OF BARRIERS Of NITROGEN, AND COMPOSING OBTAINED

METHOD FOR PREVENTING the BORON DIFFUSION IN a COMPOSANTSEMICONDUCTEUR BY CREATION OF BARRIERS Of NITROGEN, AND COMPOSING OBTAINED

METHOD FOR PREVENTING the BORON DIFFUSION IN a COMPOSANTSEMICONDUCTEUR BY CREATION OF BARRIERS Of NITROGEN, AND COMPOSING OBTAINED

METHOD FOR PREVENTING the BORON DIFFUSION IN a COMPOSANTSEMICONDUCTEUR BY CREATION OF BARRIERS Of NITROGEN, AND COMPOSING OBTAINED

강화 박막 필름 장치

... 본 발명은 강화 박막 장치(100, 200, 500)에 관한 것으로, 에피레이어(Epilayer)를 지지하기 위한 상부 표면을 가지는 기판(101); 상기 기판(101) 상에 배치되어 니들 패드(Needle Pad)를 형성하는 복수의 나노 사이즈의 캐비티(Cavity)로 패턴화되어 있는 마스크 레이어(103); 상기 마스크 레이어(103) 상에 배치된 격자 부정합 반도체(Lattice-mismatched Semiconductor)의 박막(105) - 상기 박막(105)은 이에 내장된 상기 격자 부정합 반도체의 복수의 병렬 이격된 반도체 니들을 포함하고, 상기 복수의 반도체 니들은 상기 마스크 레이어(103)의 상기 복수의 나노 사이즈의 캐비티 내에 상기 기판(101)을 향해 축 방향으로 실질적으로 수직으로 배치됨 -; 및 자신에 의해 지지되는 상기 박막 상에 제공되는 격자 부정합 반도체 에피레이어(106)를 포함한다.

Epitaxial semiconductor material and method for fabricating same

PIN DIODE WITH SIGE LOW CONTACT RESISTANCE AND METHOD FOR FORMING THE SAME

A semiconductor p-i-n diode and method for forming the same are described herein. In one aspect, a SiGe region is formed between a region doped to have one conductivity (either p+ or n+) and an electrical contact to the p-i-n diode. The SiGe region may serve to lower the contact resistance, which may increase the forward bias current. The doped region extends below the SiGe region such that it is between the SiGe region and an intrinsic region of the diode. The p-i-n diode may be formed from silicon. The doped region below the SiGe region may serve to keep the reverse bias current from increasing as result of the added SiGe region. In one embodiment, the SiGe is formed such that the forward bias current of an up-pointing p-i-n diode in a memory array substantially matches the forward bias current of a down-pointing p-i-n diode which may achieve better switching results when these diodes are used with the R/W material in a 3D memory array.

SILICON/GERMANIUM BIPOLAR TRANSISTOR WITH AN OPTIMIZED GERMANIUM PROFILE

The invention relates to a silicon/germanium bipolar transistor, wherein a first n doped emitter region (1) and a second subsequent p doped base region and a third subsequent n doped collector region are formed in a silicon substrate (7). A first space charge region (4) is formed between the emitter region (1) and the base region (2). A second space charge region (5) is formed between the base region (2) and a collector region (3). The base region (2) and the edge region of the bordering emitter region (1) is alloyed with germanium. The concentration of germanium increases in the emitter region (1) leading towards the base region (2). The concentration of germanium in a transition area in which the first space charge zone (4) is located increases to a lesser degree than in the emitter region (1) or even decreases. The concentration of germanium in the base region (2) increases to a greater degree than in the transition region.

PRODUCTION METHOD FOR SEMICONDUCTOR SUBSTRATE AND PRODUCTION METHOD FOR FIELD EFFECT TRANSISTOR AND SEMICONDUCTOR SUBSTRATE AND FIELD EFFECT TRANSISTOR

A production method for a semiconductor substrate and a production method for a field effect transistor and a semiconductor substrate and a field effect transistor, wherein a penetration dislocation density is low, a surface roughness is small, and a deterioration in surface or interface roughness at heat treating during a device production step or the like can be prevented. A production method for a semiconductor substrate having an SiGe layers (2, 3) formed on an Si substrate (1), comprising the heat treating step of conducting heat treating at temperatures exceeding an epitaxial growth temperature while or after SiGe layers are formed by epitaxial growing, and the polishing step of removing by polishing a surface unevenness produced by the heat treating after the SiGe layers are formed.

A METHOD OF MANUFACTURING A TRENCH GATED VDMOS

A semiconductor body (1) is provided having a first semiconductor region (3) of one conductivity type separated from a first major surface (5a) by a second semiconductor region (5) of the opposite conductivity type. A trench (7) is etched through the second semiconductor region (5) to an etch stop layer (4) provided in the region of the pn junction between the first (3) and second (5) regions, by using an etching process which enables the etching process to be stopped at the etch stop layer. A gate (8, 9) is provided within the trench (7). A source (12) separated from the first region (3) by the second region (5) is formed adjacent the trench so that a conduction channel area (50) of the second region (5) adjacent the trench provides a conduction path between the source and first regions which is controllable by the gate.

METHOD AND STRUCTURE FOR INCORPORATING STRAIN IN NANOSHEET DEVICES

A semiconductor structure includes a plurality of stacked and suspended semiconductor nanosheets located above a semiconductor substrate. Each semiconductor nanosheet has a pair of end sidewalls that have a V-shaped undercut surface. A functional gate structure is located around the plurality of stacked and suspended semiconductor nanosheets, and a source/drain (S/D) semiconductor material structure is located on each side of the functional gate structure. In accordance with the present application, sidewall portions of each S/D semiconductor material structure are in direct contact with the V-shaped undercut surface of the end sidewalls of each of the semiconductor nanosheets.

METHOD, APPARATUS AND SYSTEM FOR IMPROVED NANOWIRE/NANOSHEET SPACERS

A semiconductor structure, comprising a semiconductor substrate; at least one fin, wherein the at least one fin comprises one or more first layers and one or more second layers, wherein the first layers and the second layers are interspersed and the first layers laterally extend further than the second layers; a dummy gate structure comprising a first spacer material disposed on sidewalls of the dummy gate; a second spacer material disposed adjacent to each of the second layers, wherein sidewalls of the fin comprise exposed portions of each of the first layers and the second spacer material, and an epitaxial source/drain material disposed on at least the exposed portions of each of the first layers. Methods and systems for forming the semiconductor structure.

TECHNIQUES FOR FORMING GE/SIGE-CHANNEL AND III-V-CHANNEL TRANSISTORS ON THE SAME DIE

Techniques are disclosed for forming Ge/SiGe-channel and III-V-channel transistors on the same die. The techniques include depositing a pseudo-substrate of Ge/SiGe or III-V material on a Si or insulator substrate. The pseudo-substrate can then be patterned into fins and a subset of the fins can be replaced by the other of Ge/SiGe or III-V material. The Ge/SiGe fins can be used for p-MOS transistors and the III-V material fins can be used for n-MOS transistors, and both sets of fins can be used for CMOS devices, for example. In some instances, only the channel region of the subset of fins are replaced during, for example, a replacement gate process. In some instances, some or all of the fins may be formed into or replaced by one or more nanowires or nanoribbons.

NOVEL EMBEDDED SHAPE SIGE FOR NFET CHANNEL STRAIN

An integrated circuit die includes a silicon substrate. PMOS and NMOS transistors are formed on the silicon substrate. The carrier mobilities of the PMOS and NMOS transistors are increased by introducing tensile stress to the channel region of the NMOS transistors and compressive stress to the channel regions of the PMOS transistors. Tensile stress is introduced by including a region of SiGe below the channel region of the NMOS transistors. Compressive stress is introduced by including regions of SiGe in the source and drain regions of the PMOS transistors.

Selective germanium P-contact metalization through trench

Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.

Ge/SiGe-channel and III-V-channel transistors on the same die

Techniques are disclosed for forming Ge/SiGe-channel and III-V-channel transistors on the same die. The techniques include depositing a pseudo-substrate of Ge/SiGe or III-V material on a Si or insulator substrate. The pseudo-substrate can then be patterned into fins and a subset of the fins can be replaced by the other of Ge/SiGe or III-V material. The Ge/SiGe fins can be used for p-MOS transistors and the III-V material fins can be used for n-MOS transistors, and both sets of fins can be used for CMOS devices, for example. In some instances, only the channel region of the subset of fins are replaced during, for example, a replacement gate process. In some instances, some or all of the fins may be formed into or replaced by one or more nanowires or nanoribbons.

Single-chip field effect transistor (FET) switch with silicon germanium (SiGe) power amplifier and methods of forming

Various embodiments include field effect transistors (FETs) and methods of forming such FETs. One method includes: forming a first set of openings in a precursor structure having: a silicon substrate having a crystal direction, the silicon substrate substantially abutted by a first oxide; a silicon germanium (SiGe) layer overlying the silicon substrate; a silicon layer overlying the SiGe layer; a second oxide overlying the silicon layer; and a sacrificial layer overlying the second oxide, wherein the first set of openings each expose the silicon substrate; undercut etching the silicon substrate in a direction perpendicular to the crystal direction of the silicon substrate to form a trench corresponding with each of the first set of openings; passivating exposed surfaces of at least one of the SiGe layer or the silicon layer in the first set of openings; and at least partially filling each trench with a dielectric.

Semiconductor device having asymmetric active region and method of forming the same

Provided are a semiconductor device and a method of forming the same. The semiconductor device includes an active region defined by an isolation layer. A source region portion, a drain region portion and a channel region are located in the active region. The channel region includes a first portion located close to the source region portion and a second portion having a higher threshold voltage than the first portion.

Method of definition of two self-aligned areas at the upper surface of a substrate

A method for defining, on the upper surface of a substrate, two self-aligned areas, including the steps of depositing a protective layer; depositing a covering layer; opening the protective and covering layers at a location substantially corresponding to the desired border of the two areas; forming a spacer along the side of the opening, this spacer having a rear portion against said border and an opposite front portion; opening the protective and covering layers behind the rear portion of the spacer; and removing the protection layer to reach the rear portion of the spacer; whereby two self-aligned areas are defined on either side of the spacer length.

Semiconductor devices including field effect transistors and methods of forming the same

A semiconductor device includes an active pattern provided on a substrate and a gate electrode crossing over the active pattern. The active pattern includes a first buffer pattern on the substrate, a channel pattern on the first buffer pattern, a doped pattern between the first buffer pattern and the channel pattern, and a second buffer pattern between the doped pattern and the channel pattern. The doped pattern includes graphene injected with an impurity.

Method for reducing loss of silicon cap layer over SiGe source/drain in a CMOS device

A method for forming a semiconductor device includes providing a semiconductor substrate including a PMOS region and an NMOS region. A spacer material layer is deposited. Then, a first photo masking and etch process is used to form first sidewall spacers on the sidewalls of the gate structures in the NMOS region. A sacrificial surface layer is formed. Next, a second photo masking and etch process is used to form second sidewall spacers on the sidewalls of the gate structures in the PMOS region. After the second photoresist layer is removed, with the sacrificial layer masking the NMOS region, stress layers are formed in source/drain regions in the PMOS region, and a cover layer is formed on the stress layers. The method further includes removing the sacrificial material layer, the first sidewall spacers, and the second sidewall spacer.

ULTRA SCALABLE HIGH SPEED HETEROJUNCTION VERTICAL n-CHANNEL MISFETS AND METHODS THEREOF

A method for forming and the structure of a strained vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect to the body region and wherein the drain region contains a carbon doped region to prevent the diffusion of dopants (boron) into the body. The invention reduces the problem of leakage current from the source region via the hetero-junction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials.

Diamond electric device on silicon

A diamond electric device is described. The device comprises a diamond film deposited on a semiconductor substrate and an upper electrode. The electrical contact between the diamond film and the electrode is formed only through an intervening silicon semiconductor film which prevents direct contact between the diamond film and the electrode. By this structure, the stability of electric performance is substantially improved.

Method for making heterojunction bipolar transistor with self-aligned retrograde emitter profile

A high gain, high frequency transistor is formed having a combination of a moderately doped retrograde emitter and a collector which is formed by self-aligned implantation through an emitter opening window. This combination allows continued base width scaling and ensures high current capability yet limits the electric field at the emitter-base junction, particularly near the base contacts, in order to reduce leakage and capacitance and to enhance breakdown voltage. Cut-off frequencies on the order of 100 GHz can thus be obtained in the performance of a transistor with a 30 nm base width in a SiGe device.

OXIDES AND NITRIDES OF METASTABALE GROUP IV ALLOYS AND NITRIDES OF GROUP IV ELEMENTS AND SEMICONDUCTOR DEVICES FORMED THEREOF

A process and resultant devices is described for forming MOSFET, CMOS and BICMOS devices of Group IV alloys, in particular SixGe1-x wherein 0 Подробнее

Semiconductor device having SiGe spacer under an active layer

A semiconductor device which does not allow production of leak current or a drop of the Early voltage and includes a diffused layer having a reduced depth. A silicon layer containing an impurity of a second conduction type is formed on a semiconductor substrate of a first conduction type, and a spacer layer formed from a single crystalline silicon layer containing germanium is provided under the silicon layer.

Approach to minimization of strain loss in strained fin field effect transistors

A method of fabricating a vertical fin field effect transistor with a strained channel, including, forming a strained vertical fin on a substrate, forming a plurality of gate structures on the strained vertical fin, forming an interlevel dielectric on the strained vertical fin, forming a source/drain contact on the vertical fin adjacent to each of the plurality of gate structures, and selectively removing one or more of the source/drain contacts to form a trench adjacent to a gate structure.

Semiconductor device having embedded strain-inducing pattern and method of forming the same

In a semiconductor device, a first active region has a first -shape, and the second active region has a second -shape. When a line that is perpendicular to the substrate and passes a side surface of a first gate electrode in the first region is defined as a first vertical line, when a line that is perpendicular to the substrate and passes a side surface of a second gate electrode in the second region is defined as a second vertical line, when a shortest distance between the first vertical line and the first trench is defined as a first horizontal distance, and when a shortest distance between the second vertical line and the second trench is defined as a second horizontal distance, a difference between the first horizontal distance and the second horizontal distance is equal to or less than 1 nm.

Semiconductor devices with depleted heterojunction current blocking regions

A semiconductor device includes an upper and lower mirror. At least one active region for light generation is between the upper and lower mirror. At least one cavity spacer layer is between at least one of the upper and lower mirror and the active region. The device includes an inner mode confinement region and an outer current blocking region. A depleted heterojunction current blocking region (DHCBR) including a depleting impurity is within the outer current blocking region of ≥1 of the upper mirror, lower mirror, and the first active region. A middle layer including a conducting channel is within the inner mode confinement region that is framed by the DHCBR. The DHCBR forces current flow into the conducting channel during normal operation of the light source.

Method of co-integration of strained silicon and strained germanium in semiconductor devices including fin structures

A method of forming a semiconductor device that includes forming an at least partially relaxed semiconductor material, and forming a plurality of fin trenches in the partially relaxed semiconductor material. At least a portion of the plurality of fin trenches is filled with a first strained semiconductor material that is formed using epitaxial deposition. A remaining portion of the at least partially relaxed semiconductor material is removed to provide a plurality of fin structure of the first strained semiconductor material.

SIDEWALL IMAGE TRANSFER NANOSHEET

A method for forming active regions of a semiconductor device comprising forming a nanosheet stack on a substrate, forming the nanosheet stack comprising forming a sacrificial nanosheet layer on the substrate, and forming a nanosheet layer on the sacrificial nanosheet layer, forming an etch stop layer on the nanosheet stack, forming a mandrel layer on the etch stop layer, removing portions of the mandrel layer to form a mandrel on the etch stop layer, forming sidewalls adjacent to sidewalls of the mandrel, depositing a fill layer on exposed portions of the etch stop layer, removing the sidewalls and removing exposed portions of the etch stop layer and the nanosheet stack to expose portions of the substrate.

P-FET with graded silicon-germanium channel

A method of forming a semiconductor structure includes forming a silicon-germanium layer on a semiconductor region of a substrate having a specific concentration of germanium atoms. The semiconductor region and the silicon-germanium layer are annealed to induce a non-homogenous thermal diffusion of germanium atoms from the silicon-germanium layer into the semiconductor region to form a graded silicon-germanium region. Another method of forming a semiconductor structure includes etching a semiconductor region of the substrate to form a thinned semiconductor region. A silicon-germanium layer is formed on the thinned semiconductor region having a graded germanium concentration profile.

SUPERLATTICE MATERIALS AND APPLICATIONS

A superlattice cell that includes Group IV elements is repeated multiple times so as to form the superlattice. Each superlattice cell has multiple ordered atomic planes that are parallel to one another. At least two of the atomic planes in the superlattice cell have different chemical compositions. One or more of the atomic planes in the superlattice cell one or more components selected from the group consisting of carbon, tin, and lead. These superlattices make a variety of applications including, but not limited to, transistors, light sensors, and light sources.

SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND METHOD OF EVALUATING SEMICONDUCTOR DEVICE

A semiconductor device has: a silicon (semiconductor) substrate; a gate insulating film and a gate electrode, which are formed on the silicon substrate in this order; and source/drain material layers formed in recesses (holes) in the silicon substrate, the recesses being located beside the gate electrode. Here, each of side surfaces of the recesses, which are closer to the gate electrode, is constituted of at least one crystal plane of the silicon substrate.

Semiconductor structure and fabricating method thereof

A semiconductor structure and a method of fabricating the semiconductor structure are provided. The semiconductor structure includes a substrate; a metal gate structure on the substrate; and a spacer next to the metal gate structure having a skirting part extending into the metal gate structure and contacting the substrate. The metal gate structure includes a high-k dielectric layer and a metal gate electrode on the high-k dielectric layer.

Semiconductor device and manufacturing method thereof

A semiconductor device includes a substrate, an inter-layer dielectric layer, a contact plug, and a contact hole liner. The substrate has a source/drain region. The inter-layer dielectric layer is over the substrate and has a contact hole therein. The contact plug is electrically connected to the source/drain region through the contact hole of the inter-layer dielectric layer. The contact hole liner extends between the contact plug and a sidewall of a first portion of the contact hole. The contact hole liner terminates prior to reaching a second portion of the contact hole. The first portion is between the second portion and the source/drain region.

Strain compensation in transistors

An embodiment includes a device comprising: a first epitaxial layer, coupled to a substrate, having a first lattice constant; a second epitaxial layer, on the first layer, having a second lattice constant; a third epitaxial layer, contacting an upper surface of the second layer, having a third lattice constant unequal to the second lattice constant; and an epitaxial device layer, on the third layer, including a channel region; wherein (a) the first layer is relaxed and includes defects, (b) the second layer is compressive strained and the third layer is tensile strained, and (c) the first, second, third, and device layers are all included in a trench. Other embodiments are described herein.

METHOD OF FORMING FIN SHAPE STRUCTURE

A fin shaped structure and a method of forming the same. The method includes providing a substrate having a first fin structure and a second fin structure. Next, an insulation material layer is formed on the substrate. Then, a portion of the first fin structure is removed, to form a first recess. Following this, a first buffer layer and a first channel layer are formed sequentially in the first recess. Next, a portion of the second fin structure is removed, to form a second recess. Then, a second buffer layer and a second channel layer are formed in the second recess sequentially, wherein the second buffer layer is different from the first buffer layer.

SEMICONDUCTOR DEVICE

A semiconductor device including a first fin pattern and a second fin pattern, which are in parallel in a lengthwise direction; a first trench between the first fin pattern and the second fin pattern; a field insulating film partially filling the first trench, an upper surface of the field insulating film being lower than an upper surface of the first fin pattern and an upper surface of the second fin pattern; a spacer spaced apart from the first fin pattern and the second fin pattern, the spacer being on the field insulating film and defining a second trench, the second trench including an upper portion and an lower portion; an insulating line pattern on a sidewall of the lower portion of the second trench; and a conductive pattern filling an upper portion of the second trench and being on the insulating line pattern.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A method of manufacturing a semiconductor device includes forming an alloy semiconductor material layer comprising a first element and a second element on a semiconductor substrate. A mask is formed on the alloy semiconductor material layer to provide a masked portion and an unmasked portion of the alloy semiconductor material layer. The unmasked portion of the alloy semiconductor material layer not covered by the mask is irradiated with radiation from a radiation source to transform the alloy semiconductor material layer so that a surface region of the unmasked portion of the alloy semiconductor material layer has a higher concentration of the second element than an internal region of the unmasked portion of the alloy semiconductor material layer. The surface region surrounds the internal region.

ELECTROSTATIC DISCHARGE PROTECTION DEVICES AND METHODS OF FORMING ELECTROSTATIC DISCHARGE PROTECTION DEVICES

An electrostatic discharge (ESD) protection device may be provided, including a substrate having a conductivity region arranged therein, a first terminal region and a second terminal region arranged within the conductivity region, and a field distribution structure. The field distribution structure may include an intermediate region arranged within the conductivity region between the first terminal region and the second terminal region, an isolation element arranged over the intermediate region, and a first conductive plate and a second conductive plate arranged over the isolation element. The first conductive plate may be electrically connected to the first terminal region and the second conductive plate may be electrically connected to the second terminal region.

SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME

Semiconductor devices and methods of forming the same are provided. The methods may implanting dopants into a substrate to form a preliminary impurity region and heating the substrate to convert the preliminary impurity region into an impurity region. Heating the substrate may be performed at an ambient temperature of from about 800° C. to about 950° C. for from about 20 min to about 50 min. The method may also include forming first and second trenches in the impurity region to define an active tin and forming a first isolation layer and a second isolation layer in the first and second trenches, respectively. The first and second isolation layers may expose opposing sides of the active fin. The method may further include forming a gate insulation layer extending on the opposing sides and an upper surface of the active fin and forming a gate electrode traversing the active fin ...

Semiconductor device structure having multi-layered insulating cap layers over metal gate

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure further includes a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer, a metal gate over the gate dielectric layer, a first insulating layer over the metal gate and a second insulating layer over the first insulating layer. Materials of the first insulating layer and the second insulating layer are different. The semiconductor device structure also includes spacers over opposite sidewalls of the gate stack. The spacers and the metal gate surround a recess, and the first insulating layer and the second insulating layer are in the recess.

METHOD FOR REDUCING CONTACT RESISTANCE IN SEMICONDUCTOR STRUCTURES

Semiconductor structures and methods reduce contact resistance, while retaining cost effectiveness for integration into the process flow by introducing a heavily-doped contact layer disposed between two adjacent layers. The heavily-doped contact layer may be formed through a solid-phase epitaxial regrowth method. The contact resistance may be tuned by adjusting dopant concentration and contact area configuration of the heavily-doped epitaxial contact layer.

SEMICONDUCTOR STRUCTURE WITH SELF-ALIGNED WELLS AND MULTIPLE CHANNEL MATERIALS

Embodiments of the present invention provide a semiconductor structure having a strain relaxed buffer, and method of fabrication. A strain relaxed buffer is disposed on a semiconductor substrate. A silicon region and silicon germanium region are disposed adjacent to each other on the strain relaxed buffer. An additional region of silicon or silicon germanium provides quantum well isolation.

Method for selectively depositing a Group IV semiconductor and related semiconductor device structures

A method for selectively depositing a Group IV semiconductor on a surface of a substrate is disclosed. The method may include, providing a substrate within a reaction chamber and heating the substrate to a deposition temperature. The method may further include, exposing the substrate to at least one Group IV precursor, and exposing the substrate to at least one Group IIIA halide dopant precursor. Semiconductor device structures including a Group IV semiconductor deposited by the methods of the disclosure are also provided.

FinFET source-drain merged by silicide-based material

A method includes conducting a laser-based anneal treatment on a metal layer positioned above and in direct contact with a top portion of a silicon cap layer located in direct contact with a first diamond shaped epitaxial layer surrounding a first fin and a second diamond shaped epitaxial layer surrounding a second fin. The metal layer extends from the top portion of the silicon cap layer in direct contact with the first diamond shaped epitaxial layer to the top portion of the silicon cap layer in direct contact with the second diamond shaped epitaxial layer. The conducted laser-based anneal treatment forms a silicide layer, a portion of the silicide layer between the first and the second diamond shaped epitaxial layers is substantially thicker than a portion of the silicide layer in contact with the first and the second diamond shaped epitaxial layers.

GAP FILL SELF PLANARIZATION ON POST EPI

The present disclosure relates to an integrated chip having gate electrodes separated from an epitaxial source/drain region by gaps filled with a flowable dielectric material. In some embodiments, the integrated chip has an epitaxial source/drain region protruding outward from a substrate. A first gate structure, having a conductive gate electrode, is separated from the epitaxial source/drain region by a gap. A flowable dielectric material is disposed within the gap, and a pre-metal dielectric (PMD) layer is arranged above the flowable dielectric material. The PMD layer continuously extends between a sidewall of the first gate structure and a sidewall of a second gate structure, and has an upper surface that is substantially aligned with an upper surface of the conductive gate electrode. A metal contact is electrically coupled to the conductive gate electrode and is disposed within an inter-level dielectric layer over the PMD layer and the first gate structure.

Structure of a Fin Field Effect Transistor (FinFET)

A fin field effect transistor (FinFET) includes a fin extending from a substrate, where the fin includes a lower region, a mid region, and an upper region, the upper region having sidewalls that extend laterally beyond sidewalls of the mid region. The FinFET also includes a gate stack disposed over a channel region of the fin, the gate stack including a gate dielectric, a gate electrode, and a gate spacer on either side of the gate stack. A dielectric material is included that surrounds the lower region and the first interface. A fin spacer is included which is disposed on the sidewalls of the mid region, the fin spacer tapering from a top surface of the dielectric material to the second interface, where the fin spacer is a distinct layer from the gate spacers. The upper region may include epitaxial source/drain material.

Methods of forming dislocation enhanced strain in NMOS structures

Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device.

Trench contact structures for advanced integrated circuit structure fabrication

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A gate dielectric layer is over the top of the fin and laterally adjacent the sidewalls of the fin. A gate electrode is over the gate dielectric layer over the top of the fin and laterally adjacent the sidewalls of the fin. First and second semiconductor source or drain regions are adjacent the first and second sides of the gate electrode, respectively. First and second trench contact structures are over the first and second semiconductor source or drain regions, respectively, the first and second trench contact structures both comprising a U-shaped metal layer and a T-shaped metal layer on and over the entirety of the U-shaped metal layer.

Surface passivation for germanium-based semiconductor structure

The present disclosure provides a method forming a semiconductor device in accordance with some embodiments. The method includes receiving a substrate having a fin protruding through the substrate, wherein the fin is formed of a first semiconductor material, exposing the substrate in an environment including hydrogen radicals, thereby passivating the protruded fin using the hydrogen radicals, and epitaxially growing a cap layer of a second semiconductor material to cover the protruded fin.

SiC field effect transistor

A SiC field effect transistor includes: a SiC semiconductor layer; and a MIS transistor structure including a first conductivity type source region in the semiconductor layer, a second conductivity type body region in the semiconductor layer in contact with the source region, a first conductivity type drift region in the semiconductor layer in contact with the body region, a gate electrode opposed to the body region with a gate insulation film interposed between the electrode and the body region for forming a channel in the body region to cause electric current to flow between the drift region and the source region, and a barrier forming layer in contact with the drift region to form a junction barrier by the contact with the drift region, the junction barrier being lower than a diffusion potential of a body diode defined by a junction between the body region and the drift region.

Semiconductor device having epitaxial layer

A semiconductor device includes a semiconductor substrate and a plurality of transistors. The semiconductor substrate includes at least an iso region (namely an open region) and at least a dense region. The transistors are disposed in the iso region and the dense region respectively. Each transistor includes at least a source/drain region. The source/drain region includes a first epitaxial layer having a bottom thickness and a side thickness, and the bottom thickness is substantially larger than or equal to the side thickness.

Contact resistance optimization via EPI growth engineering

A transistor contact structure and methods of making the same. The method includes forming a first semiconductor layer in a source/drain opening of a substrate, the first layer having a non-planar top surface; forming a second semiconductor layer directly on the first layer, the second layer having a defect density greater than the first layer; and forming a silicide region formed with the second layer, the silicide region having a non-planar interface with the first layer. A portion of the silicide interface may be higher than a top surface of the substrate and another portion may be below.

High dose implantation for ultrathin semiconductor-on-insulator substrates

Methods and structures for forming highly-doped, ultrathin layers for transistors formed in semiconductor-on-insulator substrates are described. High dopant concentrations may be achieved in ultrathin semiconductor layers to improve device characteristics. Ion implantation at elevated temperatures may mitigate defect formation for stoichiometric dopant concentrations up to about 30%. In-plane stressors may be formed adjacent to channels of transistors formed in ultrathin semiconductor layers.

Plugs for interconnect lines for advanced integrated circuit structure fabrication

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An isolation structure surrounds a lower fin portion, the isolation structure comprising an insulating material having a top surface, and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin. A gate dielectric layer is over the top of an upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further on the semiconductor material on the portion of the top surface of the insulating material. A gate electrode is over the gate dielectric layer.

Diode

A diode of the present disclosure includes a stacked structure, and a first connection section and a second connection section provided at respective ends of the stacked structure in a length direction. The stacked structure includes a first structure and a second structure each having a nanowire structure or a nanosheet structure and stacked alternately in a thickness direction. The first connection section has a first conductivity type, and the second connection section has a second conductivity type. The diode A further includes a control electrode section formed to extend at least from a top portion to a side surface of the stacked structure and spaced apart from the first connection section and the second connection section. The first connection section and the control electrode section or the second connection section and the control electrode section are connected electrically.

Semiconductor device and method

A manufacturing process and device are provided in which a first opening in formed within a substrate. The first opening is reshaped into a second opening using a second etching process. The second etching process is performed with a radical etch in which neutral ions are utilized. As such, substrate push is reduced.

Metal-insensitive epitaxy formation

The present disclosure provides a semiconductor device structure in accordance with some embodiments. In some embodiments, the semiconductor device structure includes a semiconductor substrate of a first semiconductor material and having first recesses. The semiconductor device structure further includes a first gate stack formed on the semiconductor substrate and being adjacent the first recesses. In some examples, a passivation material layer of a second semiconductor material is formed in the first recesses. In some embodiments, first source and drain (S/D) features of a third semiconductor material are formed in the first recesses and are separated from the semiconductor substrate by the passivation material layer. In some cases, the passivation material layer is free of chlorine.

Power reduction in finFET structures

The present disclosure describes a method to reduce power consumption in a fin structure. For example, the method includes forming a first and a second semiconductor fins on a substrate with different heights. The method also includes forming insulating fins between and adjacent to the first and the second semiconductor fins. Further, the method includes forming a first and second epitaxial stacks with different heights on each of the first and second semiconductor fins.

Semiconductor apparatus including different thermal resistance values for different heat transfer paths

A semiconductor apparatus includes a substrate, plural transistor groups disposed on the substrate, an insulating film, and a metal member. Each of the plural transistor groups includes plural unit transistors arranged in a first direction within a plane of a top surface of the substrate. The plural transistor groups are arranged in a second direction perpendicular to the first direction. The insulating film covers the plural unit transistors and includes at least one cavity. The metal member is disposed on the insulating film and is electrically connected to the plural unit transistors via the at least one cavity. A heat transfer path is formed by a metal in a region from each of the plural unit transistors to a top surface of the metal member. Thermal resistance values of the heat transfer paths are different from each other among the plural unit transistors.

Heterojunction bipolar transistor and method for fabricating the same

A heterojunction bipolar transistor is fabricated by stacking a Si collector layer, a SiGeC base layer and a Si emitter layer in this order. By making the amount of a lattice strain in the SiGeC base layer on the Si collector layer 1.0% or less, the band gap can be narrower than the band gap of the conventional practical SiGe (the Ge content is about 10%), and good crystalline can be maintained after a heat treatment. As a result, a narrow band gap base with no practical inconvenience can be realized.

Semiconductor structure and method of manufacturing a semiconductor structure

La présente invention concerne une structure semiconductrice (100) comportant un support (101) et au moins un bloc (104) reposant sur le support. Le bloc comporte un empilement incluant une alternance de couches (1061, 1062, 1063) à base d'un premier matériau semiconducteur et de couches (1071, 1072, 1073) à base d'un deuxième matériau semiconducteur différent du premier matériau, lesdites couches (1061, 1062, 1063) présentant des dimensions supérieures aux couches (1071, 1072, 1073) de sorte que l'empilement possède un profil latéral dentelé (108, 308) et une pluralité de bouchons (1121, 1122, 1123 ,1131, 1132, 1133) comblant les espaces formés par le profil dentelé (108), les bouchons étant réalisés dans un troisième matériau différent du premier matériau de sorte que chacune des faces latérales (110) du bloc (104) présente une alternance de bandes latérales à base du premier matériau et de bandes latérales à base du troisième matériau. Au moins une des faces latérales (110, 111) du bloc ...

Semiconductor device

OXIDES AND NITRIDES OF METASTABILE GROUPE IV ALLOYS AND NITRIDES OF GROUP IV ELEMENTS AND SEMICONDUCTOR DEVICES FORMED THEREOF

A process and resultant devices are described for forming MOSFET, CMOS and BICMOS devices of Group IV alloys, in particular SixGe1-x wherein 0 Подробнее

METHOD FOR MAKING A SUBSTRATE IN PARTICULAR FOR OPTICS, ELECTRONICS OR OPTOELECTRONICS AND RESULTING SUBSTRATE

The invention concerns a method for making a substrate comprising a thin layer borne by a layer forming a mechanical support, in particular for optics, electronics or optoelectronics. The invention is characterised in that the method comprises the following steps: removing from a source substrate (6) a layer of a material to form the thin layer (2); then producing on the thin layer (2) a deposition of material in a thick layer (4) to form the layer forming the mechanical support.

SEMICONDUCTOR DEVICE HAVING EPITAXIAL REGION AND ITS METHODS OF FABRICATION

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

A semiconductor device includes a substrate (100) including an active pattern (AP), a channel pattern (CH1) and a source/drain pattern (SD) that are on the active pattern (AP) and connected to each other, and an active contact (AC) electrically connected to the source/drain pattern (SD). The active contact (AC) includes a first barrier metal (BM) and a first filler metal (FM) on the first barrier metal (BM), and the first barrier metal (BM) includes a metal nitride layer. The first filler metal (FM) includes at least one of molybdenum, tungsten, ruthenium, cobalt, or vanadium. The first filler metal (FM) includes a first crystalline region (CRS1) having a body-centered cubic, BCC, structure and a second crystalline region (CRS2) having a face-centered cubic, FCC, structure. A proportion of the first crystalline region (CRS1) in the first filler metal ranges from 60% to 99%.

SEMICONDUCTOR DEVICES

A semiconductor device includes a substrate including an active region extending in a first direction, a gate structure intersecting the active region on the substrate and extending in a second direction, a plurality of channel layers spaced apart from each other in a third direction, perpendicular to an upper surface of the substrate, on the active region and surrounded by the gate structure, and source/drain regions in recess regions of the active region, on opposite sides adjacent to the gate structure and electrically connected to the plurality of channel layers. Each of the plurality of channel layers includes first to third semiconductor layers sequentially stacked in the third direction, the first and third semiconductor layers include silicon (Si), and the second semiconductor layer includes silicon-germanium (SiGe). Side surfaces of the first to third semiconductor layers in the second direction are in contact with the gate structure.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device includes a lower pattern (BP1) on a substrate (100) and protruding in a first direction (D1), a source/drain pattern (150) on the lower pattern (BP1) and including a semiconductor liner film (151) in contact with the lower pattern (BP1), and an epitaxial insulating liner (150SP) extending along at least a portion of a sidewall (150SW) of the semiconductor liner film (151), wherein the epitaxial insulating liner (150SP) is in contact with the semiconductor liner film (151), wherein the semiconductor liner film (151) includes a first portion (151_HP1), wherein the first portion of the semiconductor liner film (151) includes a first point (P1) spaced apart from the lower pattern (BP1) at a first height (H11), and a second point (P2) spaced apart from the lower pattern (BP1) at a second height (H12), wherein the second height is greater than the first height, wherein a width of the semiconductor liner film (151) in a second direction (D2) at the first point (P1) is less ...

BIPOLAR TRANSISTOR

PROBLEM TO BE SOLVED: To obtain a bipolar transistor, which is superior in electrical characteristics and has reliability. SOLUTION: A bipolar transistor is constituted such a structure that the transistor is provided with an n-type Si substrate 11, a p-type SiGe film 12 provided on this substrate 11, an n-type Si film 13 provided on this film 12 and electrodes 15 to 17 which are respectively provided on the film 13, the film 12 and the rear of the substrate 11, apertures 14 are formed in the films 13 and 12 in such a way that the p-n junction surface between the films 12 and 13 is exposed by etching the films 13 and 12, and the etching depth of the film 12 is formed into a depth of 100 to 150 nm. COPYRIGHT: (C)2000,JPO ...

SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF

PROBLEM TO BE SOLVED: To improve process controllability of a semiconductor device by reducing the area and leakage current of the device. SOLUTION: A collector layer 102 is formed in a region lying between shallow trenches 103 in an Si substrate 100, and a first deposited oxide film 108 is deposited on the substrate 100. In addition, a collector opening 110 partly extending astride the trenches 103 is formed. In the collector opening 110, an Si/Si1-xGex layer is epitaxially grown on the substrate 100. Then a second deposited oxide film 112 is deposited on the substrate 100, and a base opening 118 and openings 114 for base junction are respectively formed on the central part and in the end section of the Si/Si1-xGex layer. In addition, a junction leak preventing layer 113 of the same conductivity as that of an external base is formed by implanting impurity ions into the substrate 100 from the openings 114. Moreover, junction leakage is suppressed, while the occupancy area is reduced by ...

MANUFACTURE OF BIPOLAR TRANSISTOR

PROBLEM TO BE SOLVED: To reduce the change in characteristics and deterioration in reliability by forming first and second semiconductor films on a silicon substrate, injecting impurities with a member corresponding to an emitter region formed on the second semiconductor film as a mask, and introducing impurities of opposite conductivity to that of the collector region into the collector region. SOLUTION: A silicon oxide film 2 which is to be an element isolation region is formed on a silicon substrate 1 having a bipolar transistor forming region 3, and then after an excessive silicon oxide film 2 on a surface of the bipolar transistor forming region 3 is removed, a first P-type silicon film 4 is grown as a first semiconductor film. Subsequently, a second silicon film 5 of N-type is grown as a second semiconductor film. Impurities are introduced with a silicon oxide film 6, corresponding to an emitter region formed on the second silicon film 5 as a mask, and impurities of opposite conductivity ...

SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF

PURPOSE: To realize a bipolar semiconductor device having a high speed and high performance. CONSTITUTION: A collector buried layer 2, an epitaxial layer 3 and an oxide film 110 are sequentially formed on an Si substrate 1, and an opening 120 is formed at the film 110. Further, a polycrystalline Si film is formed on the exposed layer 3 and film 110, and the Si film is substituted for a single crystalline Ge film 8 and a polycrystalline SiGe film 9 by a solid epitaxy method. Then, an emitter layer 10 is formed on the film 8. A junction capacity between a base and a collector is reduced, and further a base layer and a base electrode extraction layer can be formed in a self-alignment manner. COPYRIGHT: (C)1992,JPO&Japio ...

Vertical transport CMOS transistors with asymmetric threshold voltage

A semiconductor structure for triggering asymmetric threshold voltage along a channel of a vertical transport field effect transistor (VTFET) is provided. The semiconductor structure includes a first set of fins including a SiGe layer and a first material layer formed on the SiGe layer, a second set of fins including the SiGe layer and a second material layer formed on the SiGe layer, a first high-κ metal gate disposed over the first set of fins, and a second high-κmetal gate disposed over the second set of fins. An asymmetric threshold voltage is present along the channel of the VTFET in a region defined at a bottom of the first and second set of fins, and a Ge content of the second material layer is higher than a Ge content of the SiGe layer.

SILICON GERMANIUM HETERO BIPOLAR TRANSISTOR

A semiconductor device

Mos devices and corresponding manufacturing methods and circuits

SiC heterojunction transistor epitaxial structure and device

ELEMENT PHOTOCONDUCTEUR POUR ELECTROPHOTOGRAPHIE

L'INVENTION CONCERNE UN ELEMENT PHOTOCONDUCTEUR100 MONTE SUR UN SUBSTRAT101. L'ELEMENT COMPREND UNE COUCHE DE RECEPTION DE LUMIERE102 AYANT UNE CONSTITUTION DE COUCHES SELON LAQUELLE UNE PREMIERE REGION DE COUCHEG103 COMPRENANT UNE MATIERE AMORPHE CONTENANT DES ATOMES DE GERMANIUM ET UNE SECONDE REGION DE COUCHES104 PRESENTANT UNE PHOTOCONDUCTIBILITE COMPRENANT UNE MATIERE AMORPHE CONTENANT DES ATOMES DE SILICIUM SONT SUCCESSIVEMENT PREVUES A PARTIR DU COTE DU SUBSTRAT101, LA COUCHE DE RECEPTION DE LUMIERE102 CONTENANT DES ATOMES D'AZOTE. APPLICATION EN PARTICULIER A L'ELECTROPHOTOGRAPHIE.

BIPOLAR MANUFACTORING PROCESS AUTOALIGNE OF TRANSISTORS

Transistor with asymmetric silicon germanium source region

The present invention is directed to a transistor with an asymmetric silicon germanium source region, and various methods of making same. In one illustrative embodiment, the transistor includes a gate electrode formed above a semiconducting substrate comprised of silicon, a doped source region comprising a region of epitaxially grown silicon that is doped with germanium formed in the semiconducting substrate and a doped drain region formed in the semiconducting substrate.

FinFET with novel body contact for multiple Vt applications

FinFET devices are formed with body contact structures enabling the fabrication of such devices having different gate threshold voltages (Vt). A body contact layer is formed to contact the gate electrode (contact) enabling a forward body bias and a reduction in Vt. Two example methods of fabrication (and resulting structures) are provided. In one method, the gate electrode (silicon-based) and body contact layer (silicon) are connected by growing epitaxy which merges the two structures forming electrical contact. In another method, a via is formed that intersects with the gate electrode (suitable conductive material) and body contact layer and is filled with conductive material to electrically connect the two structures. As a result, various FinFETs with different Vt can be fabricated for different applications.

Semiconductor device with side-junction and method for fabricating the same

A method for fabricating a semiconductor device includes forming a plurality of bodies that are each isolated from another by a trench and each include a diffusion barrier region with a sidewall exposed to the trench, forming a doped layer gap-filling the trench, forming a sidewall junction at the exposed sidewall of the diffusion barrier region by annealing the doped layer, and forming a conductive line coupled with the sidewall junction to fill the trench.

Semiconductor wafer, semiconductor device and method of fabricating the same

A semiconductor substrate according to an embodiment includes: a first semiconductor wafer having a first crystal; and a second semiconductor wafer formed of a second crystal substantially same as the first crystal on the first semiconductor wafer, a crystal-axis direction of unit cell thereof being twisted at a predetermined angle around a direction vertical to a principal surface of the second semiconductor wafer from that of the first semiconductor wafer.

Methods of manufacturing semiconductor devices

A semiconductor device and a method of manufacturing a semiconductor device are provided. In a method of manufacturing a semiconductor device, a gate structure is formed on a substrate. An epitaxial layer is formed on a top surface of the substrate adjacent to the gate structure. An elevated source/drain (ESD) layer and an impurity region are formed by implanting impurities and carbon in the epitaxial layer and an upper portion of the substrate using the gate structure as an ion implantation mask. A metal silicide layer is formed on the ESD layer.

INTEGRATED METHOD FOR FORMING METAL GATE FinFET DEVICES

Provided is a high-k metal gate structure formed over a semiconductor fin. A nitride layer is formed over the gate structure and the semiconductor fin, using two separate deposition operations, the first forming a very thin nitride film. Implantation operations may be carried out in between the two nitride film deposition operations. The first nitride film may be SiN x or SiCN x and the second nitride film is SiCN x . The nitride films may be combined to form low wet etch rate spacers enabling further processing operations to be carried out without damaging underlying structures and without requiring the formation of further dummy spacers. Further processing operations include epitaxial silicon/SiGe processing sequences and source/drain implanting operations carried out with the low etch rate spacers intact.

Finfet semiconductor device

The present disclosure provides a FinFET element. The FinFET element includes a germanium-FinFET element (e.g., a multi-gate device including a Ge-fin). In one embodiment, device includes a fin having a first portion including Ge and a second portion, underlying the first portion and including an insulating material (e.g., silicon dioxide). A gate structure may be formed on the fin.

Strain Engineering in Three-Dimensional Transistors Based on a Strained Channel Semiconductor Material

In three-dimensional transistor configurations, such as finFETs, at least one surface of the semiconductor fin may be provided with a strained semiconductor material, which may thus have a pronounced uniaxial strain component along the current flow direction. The strained semiconductor material may be provided at any appropriate manufacturing stage, for instance, prior to actually patterning the semiconductor fins and/or after the patterning the semiconductor fins, thereby providing superior performance and flexibility in adjusting the overall characteristics of three-dimensional transistors.

Graded high germanium compound films for strained semiconductor devices

Embodiments of an apparatus and methods for providing a graded high germanium compound region are generally described herein. Other embodiments may be described and claimed.

Metal semiconductor alloy structure for low contact resistance

Contact via holes are etched in a dielectric material layer overlying a semiconductor layer to expose the topmost surface of the semiconductor layer. The contact via holes are extended into the semiconductor material layer by continuing to etch the semiconductor layer so that a trench having semiconductor sidewalls is formed in the semiconductor material layer. A metal layer is deposited over the dielectric material layer and the sidewalls and bottom surface of the trench. Upon an anneal at an elevated temperature, a metal semiconductor alloy region is formed, which includes a top metal semiconductor alloy portion that includes a cavity therein and a bottom metal semiconductor alloy portion that underlies the cavity and including a horizontal portion. A metal contact via is formed within the cavity so that the top metal semiconductor alloy portion laterally surrounds a bottom portion of a bottom portion of the metal contact via.

Shallow pn junction formed by in situ doping during selective growth of an embedded semiconductor alloy by a cyclic growth/etch deposition process

A silicon/carbon alloy may be formed in drain and source regions, wherein another portion may be provided as an in situ doped material with a reduced offset with respect to the gate electrode material. For this purpose, in one illustrative embodiment, a cyclic epitaxial growth process including a plurality of growth/etch cycles may be used at low temperatures in an ultra-high vacuum ambient, thereby obtaining a substantially bottom to top fill behavior.

Sea-of-fins structure on a semiconductor substrate and method of fabrication

A semiconductor device and a method of fabricating a semiconductor device, wherein the method comprises forming, on a substrate, a plurality of planarized fin bodies to be used for customized fin field effect transistor (FinFET) device formation; forming a nitride spacer around each of the plurality of fin bodies; forming an isolation region in between each of the fin bodies; and coating the plurality of fin bodies, the nitride spacers, and the isolation regions with a protective film. The fabricated semiconductor device is used in customized applications as a customized semiconductor device.

Methods of forming memory cells, memory cells, and semiconductor devices

A memory device and method of making the memory device. Memory device may include a storage transistor at a surface of a substrate. The storage transistor comprises a body portion between first and second source/drain regions, wherein the source/drain regions are regions of a first conductivity type. The storage transistor also comprises a gate structure that wraps at least partially around the body portion in at least two spatial planes. A bit line is connected to the first source/drain region and a word line is connected to the gate structure.

Method and structure for forming high-k/metal gate extremely thin semiconductor on insulator device

A semiconductor device is provided that includes a gate structure present on a substrate. The gate structure includes a gate conductor with an undercut region in sidewalls of a first portion of the gate conductor, wherein a second portion of the gate conductor is present over the first portion of the gate conductor and includes a protruding portion over the undercut region. A spacer is adjacent to sidewalls of the gate structure, wherein the spacer includes an extending portion filling the undercut region. A raised source region and a raised drain region is present adjacent to the spacers. The raised source region and the raised drain region are separated from the gate conductor by the extending portion of the spacers.

Ultra-thin body transistor and method for manufcturing the same

An ultra-thin body transistor and a method for manufacturing an ultra-thin body transistor are disclosed. The ultra-thin body transistor comprises: a semiconductor substrate; a gate structure on the semiconductor substrate; and a source region and a drain region in the semiconductor substrate and on either side of the gate structure; in which the gate structure comprises a gate dielectric layer, a gate embedded in the gate dielectric layer, and a spacer on both sides of the gate; the ultra-thin body transistor further comprises: a body region and a buried insulated region located sequentially under the gate structure and in a well region; two ends of the body region and the buried insulated region are connected with the source region and the drain region respectively; and the body region is isolated from other regions in the well region by the buried insulated region under the body region. The ultra-thin body transistor has a thinner body region, which decreases the short channel effect. In the method for manufacturing an ultra-thin body transistor together with the replacement-gate process, the forming of the buried insulated region is self-aligned with the gate, which reduces the parasitic resistance under the spacer.

Transistor devices and methods of making

In an embodiment, a method of fabricating a transistor device comprises: providing a semiconductor topography comprising a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers; anisotropically etching exposed regions of the semiconductor substrate on opposite sides of the dielectric spacers to form recessed regions in the substrate; oxidizing exposed surfaces of the substrate in the recessed regions to form an oxide thereon; removing the oxide from bottoms of the recessed regions while retaining the oxide upon sidewalls of the recessed regions; and isotropically etching the substrate such that the recessed regions undercut the pair of dielectric spacers.

Lateral Uniformity in Silicon Recess Etch

A method of etching recesses into silicon prior to formation of embedded silicon alloy source/drain regions. The recess etch includes a plasma etch component, using an etch chemistry of a primary fluorine-based or chlorine-based etchant, in combination with a similar concentration of hydrogen bromide. The concentration of both the primary etchant and the hydrogen bromide is relatively low; a diluent of an inert gas or oxygen is added to the reactive species. Loading effects on the undercut of the recess etch are greatly reduced, resulting in reduced transistor performance variation.

Structure and method for increasing strain in a device

A method and structure are disclosed for increasing strain in a device, specifically an n-type field effect transistor (NFET) complementary metal-oxide-semiconductor (CMOS) device. Embodiments of this invention include growing an epitaxial layer, performing a cold carbon or cluster carbon pre-amorphization implantation to implant substitutional carbon into the epitaxial layer, forming a tensile cap over the epitaxial layer, and then annealing to recrystallize the amorphous layer to create a stress memorization technique (SMT) effect. The epitaxial layer will therefore include substitutional carbon and have a memorized tensile stress induced by the SMT. Embodiments of this invention can also include a lower epitaxial layer under the epitaxial layer, the lower epitaxial layer comprising for example, a silicon carbon phosphorous (SiCP) layer.

Semiconductor Device

A method for fabricating a semiconductor device comprises forming a partial-insulated substrate comprising an insulating region located below both a channel region of a cell transistor and one of a storage node contact region and a bit line contact region, and forming a cell transistor comprising a fin region on the partial-insulated substrate.

Fet structures with trench implantation to improve back channel leakage and body resistance

An FET structure on a semiconductor substrate which includes forming recesses for a source and a drain of the gate structure on a semiconductor substrate, halo implanting regions through the bottom of the source and drain recesses, the halo implanted regions being underneath the gate stack, implanting junction butting at the bottom of the source and drain recesses, and filling the source and drain recesses with a doped epitaxial material. In exemplary embodiments, the semiconductor substrate is a semiconductor on insulator substrate including a semiconductor layer on a buried oxide layer. In exemplary embodiments, the junction butting and halo implanted regions are in contact with the buried oxide layer. In other exemplary embodiments, there is no junction butting. In exemplary embodiments, halo implants implanted to a lower part of the FET body underneath the gate structure provide higher doping level in lower part of the FET body to reduce body resistance, without interfering with FET threshold voltage.

Strained structure of a p-type field effect transistor

In a p-type field effect transistor, a pair of spacers are formed over the top surface of a substrate. A channel recess cavity includes an indentation in the substrate top surface between the pair of spacers. A gate stack has a bottom portion in the channel recess cavity and a top portion extending outside the channel recess cavity. A source/drain (S/D) recess cavity has a bottom surface and sidewalls below the substrate top surface. The S/D recess cavity has a portion extending below the gate stack. A strained material is filled the S/D recess cavity

Method for fabricating mos transistors

A method for fabricating a MOS transistor is disclosed. First, a semiconductor substrate having a gate thereon is provided. A spacer is then formed on the sidewall of the gate, and two recesses are formed adjacent to the spacer and within the semiconductor substrate. Next, the spacer is thinned, and epitaxial layer is grown in each of the two recesses. By thinning the spacer before the epitaxial layer is formed, the present invention could stop the epitaxial layer to grow against the sidewall of the spacer, thereby preventing problem such as Ion degradation.

Semiconductor integrated circuit device and a method of fabricating the same

A method of fabricating a semiconductor integrated circuit includes forming a first dielectric layer on a semiconductor substrate, patterning the first dielectric layer to form a first patterned dielectric layer, forming a non-single crystal seed layer on the first patterned dielectric layer, removing a portion of the seed layer to form a patterned seed layer, forming a second dielectric layer on the first patterned dielectric layer and the patterned seed layer, removing portions of the second dielectric layer to form a second patterned dielectric layer, irradiating the patterned seed layer to single-crystallize the patterned seed layer, removing portions of the first patterned dielectric layer and the second patterned dielectric layer such that the single-crystallized seed layer protrudes in the vertical direction with respect to the first and/or the second patterned dielectric layer, and forming a gate electrode in contact with the single-crystal active pattern.

Semiconductor device and a method for manufacturing a semiconductor device

A semiconductor device of the present invention has a (110)-plane-orientation silicon substrate and a p channel type field effect transistor formed in a pMIS region. The p channel type field effect transistor includes a gate electrode disposed via a gate insulation film, and source/drain regions disposed inside a trench disposed in the silicon substrate on the opposite sides of the gate electrode, and including SiGe larger in lattice constant than Si. The trench has a (100)-plane-orientation first inclined surface, and a (100)-plane-orientation second inclined surface crossing the first inclined surface at a sidewall part situated on the gate electrode side. With the configuration, the angle formed between the surface (110) plane and the (100) plane of the substrate is 45°, so that the first inclined surface is formed at a relatively acute angle. This can effectively apply a compressive strain to a channel region of the p channel type MISFET.

Reacted Conductive Gate Electrodes and Methods of Making the Same

A semiconductor device and a method for fabricating a semiconductor device involve a semiconductor layer that includes a first material and a second material. The first and second materials can be silicon and germanium. A contact of the device has a portion proximal to the semiconductor layer and a portion distal to the semiconductor layer. The distal portion includes the first material and the second material. A metal layer formed adjacent to the relaxed semiconductor layer and adjacent to the distal portion of the contact is simultaneously reacted with the relaxed semiconductor layer and with the distal portion of the contact to provide metallic contact material.

Simultaneous formation of finfet and mugfet

A method and structure comprise a field effect transistor structure that includes a first rectangular fin structure position on a substrate. The first rectangular fin structure has a bottom contacting the substrate, a top opposite the bottom, and sides between the top and the bottom. The structure additionally includes a second rectangular fin structure position on the substrate. Similarly, the second rectangular fin structure also has a bottom contacting the substrate, a top opposite the bottom, and sides between the top and the bottom. The sides of the second rectangular fin structure are parallel to the sides of the first rectangular fin structure. Further, a trench insulator is positioned on the substrate and is positioned between a side of the first rectangular fin structure and a side of the second rectangular fin structure. Additionally, a gate conductor is positioned on the trench insulator, positioned over the sides and the top of the first rectangular fin structure, and positioned over the sides and the top of the second rectangular fin structure. The gate conductor runs perpendicular to the sides of the first rectangular fin structure and the sides of the second rectangular fin structure. Also, a gate insulator is positioned between the gate conductor and the first rectangular fin structure and between the gate conductor and the second rectangular fin structure. The structure further includes a first cap on the top of the first rectangular fin structure. The first cap separates the gate conductor from the first rectangular fin structure.

Method of fabricating semiconductor device

A method of fabricating a semiconductor device includes sequentially forming a first gate insulating layer and a second gate insulating layer on a substrate, implanting impurity ions into the substrate and performing a first thermal process for activating the impurity ions to form a source and drain region, and forming a third gate insulating layer on the substrate after the first thermal process has been completed.

Field effect transistors (fets) and methods of manufacture

An improved field effect transistors (FETs) and methods of manufacturing the field effect transistors (FETs) are provided. The method of manufacturing a zero capacitance random access memory cell (ZRAM) includes comprises forming a finFET on a substrate and enhancing a storage capacitance of the finFET. The enhancement can be by either adding a storage capacity to the finFET or altering a portion of the finFET after formation of a fin body of the finFET.

Method of manufacturing a semiconductor device

A method of manufacturing a semiconductor device which includes forming a gate insulating film and a gate electrode over a semiconductor substrate, forming a first recess in the first semiconductor substrate on both sides of the gate electrode by dry etching, forming a second recess by removing a bottom and sidewalls of the first recess by wet etching, and forming a semiconductor layer in the second recess.

Semiconductor Device Comprising Transistor Structures and Methods for Forming Same

A method for forming an opening within a semiconductor material comprises forming a neck portion, a rounded portion below the neck portion and, in some embodiments, a protruding portion below the rounded portion. This opening may be filled with a conductor, a dielectric, or both. Embodiments to form a transistor gate, shallow trench isolation, and an isolation material separating a transistor source and drain are disclosed. Device structures formed by the method are also described.

Replacement Gate Having Work Function at Valence Band Edge

Replacement gate stacks are provided, which increase the work function of the gate electrode of a p-type field effect transistor (PFET). In one embodiment, the work function metal stack includes a titanium-oxide-nitride layer located between a lower titanium nitride layer and an upper titanium nitride layer. The stack of the lower titanium nitride layer, the titanium-oxide-nitride layer, and the upper titanium nitride layer produces the unexpected result of increasing the work function of the work function metal stack significantly. In another embodiment, the work function metal stack includes an aluminum layer deposited at a temperature not greater than 420° C. The aluminum layer deposited at a temperature not greater than 420° C. produces the unexpected result of increasing the work function of the work function metal stack significantly.

Source tip optimization for high voltage transistor devices

The present disclosure provides a method for fabricating a high-voltage semiconductor device. The method includes designating first, second, and third regions in a substrate. The first and second regions are regions where a source and a drain of the semiconductor device will be formed, respectively. The third region separates the first and second regions. The method further includes forming a slotted implant mask layer at least partially over the third region. The method also includes implanting dopants into the first, second, and third regions. The slotted implant mask layer protects portions of the third region therebelow during the implanting. The method further includes annealing the substrate in a manner to cause diffusion of the dopants in the third region.

Semiconductor device and method of manufacturing the same

Aimed at providing a highly reliable semiconductor device appropriately increased in stress at the channel region so as to improve carrier injection rate, thereby dramatically improved in transistor characteristics, and made adaptable also to recent narrower channel width, and a method of manufacturing the same, and a method of manufacturing the same, a first sidewall composed of a stress film having expandability is formed on the side faces of a gate electrode, a second sidewall composed of a film having smaller stress is formed on the first sidewall, and a semiconductor, which is a SiC layer for example, is formed as being positioned apart from the first sidewall while placing the second sidewall in between.

Structure and method for mobility enhanced mosfets with unalloyed silicide

While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed silicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed silicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices.

Method for manufacturing a strained channel mos transistor

A method for manufacturing a strained channel MOS transistor including the steps of: forming, at the surface of a semiconductor substrate, a MOS transistor comprising source and drain regions and an insulated sacrificial gate which partly extends over insulation areas surrounding the transistor; forming a layer of a dielectric material having its upper surface level with the upper surface of the sacrificial gate; removing the sacrificial gate; etching at least an upper portion of the exposed insulation areas to form trenches therein; filling the trenches with a material capable of applying a strain to the substrate; and forming, in the space left free by the sacrificial gate, an insulated MOS transistor gate.

Transistor and method for forming the same

The invention discloses a semiconductor device which comprises an NMOS transistor and a PMOS transistor formed on a substrate; and grid electrodes, source cathode doped areas, drain doped areas, and side walls formed on two sides of the grid electrodes are arranged on the NMOS transistor and the PMOS transistor respectively. The device is characterized in that the side walls on the two sides of the grid electrode of the NMOS transistor possess tensile stress, and the side walls on the two sides of the grid electrode of the PMOS transistor possess compressive stress. The stress gives the side walls a greater role in adjusting the stress applied to channels and the source/drain areas, with the carrier mobility further enhanced and the performance of the device improved.

Semiconductor device

A source region and a drain region are disposed in a substrate. A gate insulating film is disposed on the substrate. A gate electrode is disposed on the gate insulating film. The gate electrode may include a first gate portion adjacent to the source region and a second gate portion adjacent to the drain region. The first and second gate portions have different work functions from each other.

Semiconductor structures and methods of manufacturing the same

A semiconductor structure has embedded stressor material for enhanced transistor performance. The method of forming the semiconductor structure includes etching an undercut in a substrate material under one or more gate structures while protecting an implant with a liner material. The method further includes removing the liner material on a side of the implant and depositing stressor material in the undercut under the one or more gate structures.

Stressed channel fet with source/drain buffers

A method for forming a stressed channel field effect transistor (FET) with source/drain buffers includes etching cavities in a substrate on either side of a gate stack located on the substrate; depositing source/drain buffer material in the cavities; etching the source/drain buffer material to form vertical source/drain buffers adjacent to a channel region of the FET; and depositing source/drain stressor material in the cavities adjacent to and over the vertical source/drain buffers.

Non-volatile finfet memory array and manufacturing method thereof

An electronic device includes a substrate with a semiconducting surface having a plurality of fin-type projections coextending in a first direction through a memory cell region and select gate regions. The electronic device further includes a dielectric isolation material disposed in spaces between the projections. In the electronic device, the dielectric isolation material in the memory cell regions have a height less than a height of the projections in the memory cell regions, and the dielectric isolation material in the select gate regions have a height greater than or equal to than a height of the projections in the select gate regions. The electronic device further includes gate features disposed on the substrate within the memory cell region and the select gate regions over the projections and the dielectric isolation material, where the gate features coextend in a second direction transverse to the first direction.

Fabrication of a vertical heterojunction tunnel-fet

Exemplary embodiments include a method for fabricating a heterojunction tunnel field-effect-transistor (FET), the method including forming a gate region on a silicon layer of a silicon-on-insulator (SOI) substrate, forming a drain region on the silicon layer adjacent the gate region and forming a vertical heterojunction source region adjacent the gate region, wherein the vertical heterojunction source region generates a tunnel path inline with a gate field associated with the gate region.

FinFET STRUCTURE HAVING FULLY SILICIDED FIN

A semiconductor device which includes fins of a semiconductor material formed on a semiconductor substrate and then a gate electrode formed over and in contact with the fins. An insulator layer is deposited over the gate electrode and the fins. A trench opening is then etched in the insulator layer. The trench opening exposes the fins and extends between the fins. The fins are then silicided through the trench opening. Then, the trench opening is filled with a metal in contact with the silicided fins to form a local interconnect connecting the fins.

Devices and methods to optimize materials and properties for replacement metal gate structures

Devices and methods for device fabrication include forming a gate structure with a sacrificial material. Silicided regions are formed on source/drain regions adjacent to the gate structure or formed at the bottom of trench contacts within source/drain areas. The source/drain regions or the silicided regions are processed to build resistance to subsequent thermal processing and adjust Schottky barrier height and thus reduce contact resistance. Metal contacts are formed in contact with the silicided regions. The sacrificial material is removed and replaced with a replacement conductor.

Finfet structures and methods for fabricating the same

A method for fabricating a FinFET structure includes fabricating a plurality of parallel fins overlying a semiconductor substrate, each of the plurality of parallel fins having sidewalls and forming an electrode over the semiconductor substrate and between the parallel fins. The electrode is configured to direct an electrical field into the fins, thereby affecting the threshold voltage of the FinFET structure.

System and Method for Source/Drain Contact Processing

System and method for reducing contact resistance and prevent variations due to misalignment of contacts is disclosed. A preferred embodiment comprises a non-planar transistor with source/drain regions located within a fin. An inter-layer dielectric overlies the non-planar transistor, and contacts are formed to the source/drain region through the inter-layer dielectric. The contacts preferably come into contact with multiple surfaces of the fin so as to increase the contact area between the contacts and the fin.

Semiconductor device

A semiconductor device according to an embodiment includes: a semiconductor region on a semiconductor substrate, an upper face and side faces of the semiconductor region forming a saddle-like shape, convex portions being formed at both ends of a region including a saddle point in the upper face; a gate insulating film on the upper face of the semiconductor region except upper faces of the convex portions, and on side faces of the convex portions on a side of the region including the saddle point in the upper face; a gate electrode on the gate insulating film and including: a main body part located immediately above the region including the saddle point in the upper face; and leg portions leading to the main body portion and covering the side faces of the semiconductor region, a length of the leg portions being greater than a length of the main body portion.

Semiconductor devices and methods of fabricating the same

A method of fabricating one or more semiconductor devices includes forming a trench in a semiconductor substrate, performing a cycling process to remove contaminants from the trench, and forming an epitaxial layer on the trench. The cycling process includes sequentially supplying a first reaction gas containing germane, hydrogen chloride and hydrogen and a second reaction gas containing hydrogen chloride and hydrogen onto the semiconductor substrate.

Methods of fabricating semiconductor devices

A substrate including an NMOS transistor region and a PMOS transistor region is prepared. A silicon-germanium layer is formed on the PMOS transistor region. Nitrogen atoms are injected in an upper portion of the silicon-germanium layer. A first gate dielectric layer is formed on the NMOS transistor region and the PMOS transistor region. The nitrogen atoms are injected into the upper portion of the silicon-germanium layer before forming the first gate dielectric layer.

Methods for fabricating semiconductor devices

A method of fabricating a semiconductor device includes providing a semiconductor substrate including a channel region, forming a gate electrode structure on the channel region of the semiconductor substrate, forming a first trench in the semiconductor substrate, and forming a second trench in the semiconductor device. The first trench may include a first tip that protrudes toward the channel. The second trench may be an enlargement of the first trench and may include a second tip that also protrudes toward the channel region. In some examples, the second tip may protrude further towards the channel region than the first tip.

Backside bevel protection

The disclosure provides methods and structures for preventing exposing polysilicon layer and silicon substrate on the substrate backside to polysilicon etching chemistry during removal of the dummy polysilicon layer in replacement gate structures. A thermal deposition process or processes are used to deposit a dielectric layer for offset spacers and/or a contact etch stop layer (CESL) to cover the polysilicon layer on the substrate backside. Such mechanisms reduce or eliminate particles originated at bevel of substrate backside, due to complete removal of the polysilicon layer at the backside bevel and the resultant etching of silicon substrate.

Semiconductor device and fabrication method

A semiconductor device includes a semiconductor substrate including a well having a first conductivity type defined by a device isolation region, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film and including a first side surface and a second side surface facing the first side surface, and a first side wall insulating film formed on the first side surface and a second side wall insulating film formed on the second side surface.

Method of gate work function adjustment and metal gate transistor

A method of gate work function adjustment includes the steps as follow. First, a substrate is provided, wherein a metal gate is disposed on the substrate, a source doping region and a drain doping region are disposed in the substrate at opposite sites of the metal gate, wherein the metal gate is divided into a source side adjacent to the source doping region, and a drain side adjacent to the drain doping region. Later, a mask layer is formed to cover the source doping region and the drain doping region. After that, an implantation process is performed to implant nitrogen into the metal gate so as to make a first nitrogen concentration of the source side higher than a second nitrogen concentration of the drain side. Finally, the mask layer is removed.

Semiconductor device and method for manufacturing the same

A semiconductor device comprising: a semiconductor substrate; an STI embedded into the semiconductor substrate and having at least a semiconductor opening region; a channel region in the semiconductor opening region; a gate stack comprising a gate dielectric layer and a gate conductive layer and located above the channel region; and source/drain regions located on both sides of the channel region, and comprising first seed layers on opposite sides of the gate stack adjacent to the STI, wherein the upper surface of the STI is higher than or sufficiently closed to the upper surface of the gate dielectric layer. The semiconductor device and the method for manufacturing the same can enhance the stress of the channel region so as to improve device performance.

Cavity-free interface between extension regions and embedded silicon-carbon alloy source/drain regions

A gate stack is formed on a silicon substrate, and source/drain extension regions are formed around the gate stack. A dielectric spacer is formed around the gate stack. A pair of trenches is formed around the gate stack and the dielectric spacer by an etch so that sidewalls of the source/drain extension regions are exposed. Within each trench, an n-doped silicon liner is deposited on the sidewalls of the trenches by a first selective epitaxy process so that the interface between the dielectric spacer and the source/drain extension region is covered. Within each trench, an n-doped single crystalline silicon-carbon alloy is subsequently deposited to fill the trench by a second selective epitaxy process. A combination of an n-doped single crystalline silicon liner and an n-doped single crystalline silicon-carbon alloy functions as embedded source/drain regions of an n-type field effect transistor (NFET), which applies a tensile stress to the channel of the transistor.

SOI SiGe-BASE LATERAL BIPOLAR JUNCTION TRANSISTOR

A lateral heterojunction bipolar transistor (HBT) is formed on a semiconductor-on-insulator substrate. The HBT includes a base including a doped silicon-germanium alloy base region, an emitter including doped silicon and laterally contacting the base, and a collector including doped silicon and laterally contacting the base. Because the collector current is channeled through the doped silicon-germanium base region, the HBT can accommodate a greater current density than a comparable bipolar transistor employing a silicon channel. The base may also include an upper silicon base region and/or a lower silicon base region. In this case, the collector current is concentrated in the doped silicon-germanium base region, thereby minimizing noise introduced to carrier scattering at the periphery of the base. Further, parasitic capacitance is minimized because the emitter-base junction area is the same as the collector-base junction area.

Semiconductor device and method for fabricating the same

A semiconductor device comprising a silicon substrate, a gate structure and a heteroatom-containing epitaxial structure is provided. The gate structure is disposed on a surface of the silicon substrate. The heteroatom-containing epitaxial structure is disposed adjacent to the gate structure and has a major portion and an extension portion, wherein the major portion virtual vertically extends downwards into the silicon substrate from the surface; and the extension portion further extends downwards into the silicon substrate with a tapered cross-section continuing with the major portion.

Finfet transistor structure and method for making the same

A FINFET transistor structure includes a substrate, a fin structure, an insulating layer and a gate structure. The fin structure is disposed on the substrate and directly connected to the substrate. Besides, the fin structure includes a fin conductive layer and a bottle neck. The insulating layer covers the substrate and has a protruding side which is formed by partially surrounding the bottle neck of the fin structure, and a bottom side in direct contact with the substrate so that the protruding side extend to and under the fin structure. The gate structure partially surrounds the fin structure.

PMOS Threshold Voltage Control by Germanium Implantation

Disclosed herein is a method of forming a semiconductor device. In one example, the method comprises forming a P-active region in a silicon containing semiconducting substrate, performing an ion implantation process to implant germanium into the P-active region to form an implanted silicon-germanium region in the P-active region, and forming a gate electrode structure for a PMOS transistor above the implanted silicon-germanium region.

Method of fabricating semiconductor devices

A method of fabricating a semiconductor device is provided. The method includes forming a gate having a first material on a substrate and a layer of a second material overlaying the gate. Sidewall spacers are formed on opposite sides of the gate. A characteristic of a portion of the substrate between adjacent sidewall spacers is changed using the layer of second material and the sidewall spacers as a mask. An isotropic wet etch process is performed to remove the substrate portion with a changed characteristic to form a recess in the substrate. An orientation selective wet etching process is performed on the recess to shape the inner walls of the recess into sigma-shape. Changing a substrate characteristic in conjunction with isotropic wet etching prevents the substrate from being damaged, and therefore can obtain defect free epitaxial SiGe growth performance.

Method for fabricating semiconductor device

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a dummy gate on the substrate; forming a contact etch stop layer on the dummy gate and the substrate; performing a planarizing process to partially remove the contact etch stop layer; partially removing the dummy gate; and performing a thermal treatment on the contact etch stop layer.

Devices and methods to optimize materials and properties for replacement metal gate structures

Devices and methods for device fabrication include forming a gate structure with a sacrificial material. Silicided regions are formed on source/drain regions adjacent to the gate structure or formed at the bottom of trench contacts within source/drain areas. The source/drain regions or the silicided regions are processed to build resistance to subsequent thermal processing and adjust Schottky barrier height and thus reduce contact resistance. Metal contacts are formed in contact with the silicided regions. The sacrificial material is removed and replaced with a replacement conductor.

Method to modify the shape of a cavity using angled implantation

A method of modifying a shape of a cavity in a substrate. The method includes forming one or more cavities on a surface of the substrate between adjacent relief structures. The method also includes directing ions toward the substrate at a non-normal angle of incidence, wherein the ions strike an upper portion of a cavity sidewall, and wherein the ions do not strike a lower portion of the cavity sidewall. The method further includes etching the one or more cavities wherein the upper portion of a cavity sidewall etches more slowly than the lower portion of the sidewall cavity.

Fabricating method of mos transistor, fin field-effect transistor and fabrication method thereof

A fabricating method of a MOS transistor includes the following steps. A substrate is provided. A gate dielectric layer is formed on the substrate. A nitridation process containing nitrogen plasma and helium gas is performed to nitride the gate dielectric layer. A fin field-effect transistor and fabrication method thereof are also provided.

Integrated circuit having a stressor and method of forming the same

An embodiment of the disclosure includes a method of forming a semiconductor structure. A substrate has a region adjacent to a shallow trench isolation (STI) structure in the substrate. A patterned mask layer is formed over the substrate. The patterned mask layer covers the STI structure and a portion of the region, and leaves a remaining portion of the region exposed. A distance between an edge of the remaining portion and an edge of the STI structure is substantially longer than 1 nm. The remaining portion of the region is etched thereby forms a recess in the substrate. A stressor is epitaxially grown in the recess. A conductive plug contacting the stressor is formed.

Recessed contact for multi-gate fet optimizing series resistance

A method to fabricate a transistor including forming at least one electrically conductive channel structure over a substrate, the channel having a length, a width and a first height (h 1 ); forming a gate structure over the substrate, the gate structure having a length, a width and a height, the gate structure being perpendicular to the channel structure and being formed over the channel structure such that the channel structure passes through the width of the gate structure, where the height of the gate structure is greater than h 1 ; reducing the height of the channel structure external to the gate structure so as to have a second height (h 2 ); and depositing a silicide layer at least partially over the at least one channel structure external to the gate structure.

Replacement source/drain finfet fabrication

A finFET is formed having a fin with a source region, a drain region, and a channel region between the source and drain regions. The fin is etched on a semiconductor wafer. A gate stack is formed having an insulating layer in direct contact with the channel region and a conductive gate material in direct contact with the insulating layer. The source and drain regions are etched leaving the channel region of the fin. Epitaxial semiconductor is grown on the sides of the channel region that were adjacent the source and drain regions to form a source epitaxy region and a drain epitaxy region. The source and drain epitaxy regions are doped in-situ while growing the epitaxial semiconductor.

Semiconductor device

In one embodiment, a semiconductor device includes a semiconductor substrate, a gate electrode provided on the semiconductor substrate via an insulating layer, and a gate insulator provided on a side surface of the gate electrode. The device includes a stacked layer including a lower main terminal layer of a first conductivity type, an intermediate layer, and an upper main terminal layer of a second conductivity type which are successively stacked on the semiconductor substrate, the stacked layer being provided on the side surface of the gate electrode via the gate insulator. The upper or lower main terminal layer is provided on the side surface of the gate electrode via the gate insulator and the semiconductor layer.

Mechanisms for forming ultra shallow junction

The embodiments of methods and structures are for doping fin structures by plasma doping processes to enable formation of shallow lightly doped source and drain (LDD) regions. The methods involve a two-step plasma doping process. The first step plasma process uses a heavy carrier gas, such as a carrier gas with an atomic weight equal to or greater than about 20 amu, to make the surfaces of fin structures amorphous and to reduce the dependence of doping rate on crystalline orientation. The second step plasma process uses a lighter carrier gas, which is lighter than the carrier gas for the first step plasma process, to drive the dopants deeper into the fin structures. The two-step plasma doping process produces uniform dopant profile beneath the outer surfaces of the fin structures.

Semiconductor device and method of manufacturing the same

According to one embodiment, there is provided a method of manufacturing a semiconductor device. In the method, a substrate portion and a fin portion on the substrate portion are formed. A first silicon oxide film is formed on each side surface of the fin portion. A polysilazane film having an upper surface lower than the upper surface of the first silicon oxide film is formed on each side surface of the first silicon oxide film. The polysilazane film is converted into a silicon oxynitride film. The first silicon oxide film is etched to make the upper surface of the first silicon oxide film not higher than the upper surface of the silicon oxynitride film. A heavily doped semiconductor layer is formed in the fin portion.

Semiconductor device and manufacturing method of semiconductor device

According to one embodiment, a semiconductor device includes a fin-type semiconductor, a gate electrode that is formed on a side surface of the fin-type semiconductor with a gate dielectric film therebetween in a state where both end portions of the fin-type semiconductor are exposed, source/drain formed in both end portions of the fin-type semiconductor, an offset spacer and a sidewall spacer that are formed on a side surface of the source/drain and a side surface of the gate electrode in a state where a surface of an upper portion of the fin-type semiconductor is exposed, and a silicide layer that is formed on a surface of the source/drain in the upper portion of the fin-type semiconductor.

Method to enable compressively strained pfet channel in a finfet structure by implant and thermal diffusion

A method of making a semiconductor device patterns a first fin in a pFET region, and patterns a second fin in an nFET region. A plurality of conformal microlayers containing a straining material are deposited on the first and second fins. A protective cap material is formed on the first fin, and the conformal layers are selectively removed from the second fin. The straining material is then thermally diffused into the first fin. The protective cap material is removed from the first fin after the thermal annealing and after the conformal micro layers are selectively removed from the second fin.

Circuit simulation method and semiconductor integrated circuit

A simulation method of a circuit in which a transistor is formed of a material (e.g., SiGe, etc.) having a lattice constant different from that of a semiconductor substrate, on source and drain regions, an adjacent active region is formed near the transistor, and a gate electrode is formed in the active region, where a region not overlapping with the gate electrode in the adjacent active region is formed of a material such as SiGe, includes a step of calculating an electrical characteristic (e.g., flowing current, threshold voltage, etc.) of the transistor based on a distance between an edge closer to the transistor, of both edges of the adjacent active region disposed near the transistor, and the gate electrode formed in the adjacent active region. Thus, circuit simulation can be performed with high accuracy with respect to an electrical characteristic of the transistor.

Method of isolating nanowires from a substrate

A method is provided. The method includes forming a plurality of nanowires on a top surface of a substrate and forming an oxide layer adjacent to a bottom surface of each of the plurality of nanowires, wherein the oxide layer is to isolate each of the plurality of nanowires from the substrate.

Semiconductor device and manufacturing method for the same

A semiconductor device and manufacturing method for the same are disclosed. The method includes providing a substrate that has an insulator layer and a semiconductor layer overlying the insulator layer. The method further includes forming a hard mask layer pattern on the semiconductor layer and etching the semiconductor layer using the patterned hard mask layer to form portions having different thickness in the semiconductor layer. The method also includes performing an oxygen-based treatment on the semiconductor layer to form a supporting oxide layer. A portion of the semiconductor layer is buried in the supporting oxide layer.

Semiconductor device and method for manufacturing the same

A semiconductor device and a method for manufacturing the same are disclosed. In one embodiment, the semiconductor device may comprise a semiconductor layer, a fin formed by patterning the semiconductor layer, and a gate stack crossing over the fin. The fin may comprise a doped block region at the bottom portion thereof. According to the embodiment, it is possible to effectively suppress current leakage at the bottom portion of the fin by the block region.

Semiconductor device and manufacturing method thereof

In a method, a gate dielectric film is formed on a semiconductor substrate. A gate electrode is formed on the gate dielectric film. Impurities of a first conduction-type are introduced into a drain-layer formation region. The impurities of the first conduction-type in the drain-layer formation region are activated by performing heat treatment. Single crystals of the semiconductor substrate in a source-layer formation region are amorphized by introducing inert impurities into the source-layer formation region. Impurities of a second conduction-type is introduced into the source-layer formation region. At least an amorphous semiconductor in the source-layer formation region is brought into a single crystal semiconductor and the impurities of the second conduction-type in the source-layer formation region is activated by irradiating the semiconductor substrate with microwaves. The impurities of the second conduction-type in the source-layer formation region is shallower than the impurities of the first conduction-type in the drain-layer formation region.

Selective Epitaxial Growth of Semiconductor Materials with Reduced Defects

A semiconductor device includes a substrate formed of a first semiconductor material; two insulators on the substrate; and a semiconductor region having a portion between the two insulators and over the substrate. The semiconductor region has a bottom surface contacting the substrate and having sloped sidewalls. The semiconductor region is formed of a second semiconductor material different from the first semiconductor material. 1. A device comprising:a first semiconductor layer of a first semiconductor material;a first insulator layer disposed on the first semiconductor layer; anda semiconductor region having a first portion disposed in the first insulator layer and a second portion disposed in the first semiconductor layer, the second portion in contact with the first portion and having a width greater than a width of the first portion, and the first portion of a second semiconductor material different from the first semiconductor material.2. The device of claim 1 , wherein a sidewall of the first portion and a sidewall of the second portion are substantially vertical.3. The device of claim 1 , further comprising:a substrate of a third semiconductor material; anda second insulator layer in contact with and disposed between the substrate and the first semiconductor layer, the second portion of the semiconductor region extending through the first semiconductor layer and in contact with the second insulator layer.4. The device of claim 3 , wherein the second insulator layer is a buried oxide claim 3 , and wherein the first semiconductor material and the third semiconductor material are a same material.5. The device of claim 1 , wherein the first insulator layer is an oxide of the first semiconductor material.6. The device of claim 1 , wherein the second portion of the semiconductor region is formed of a fourth semiconductor material different from the second semiconductor material claim 1 , the second semiconductor material and fourth semiconductor material both ...

Controlling the Shape of Source/Drain Regions in FinFETs

An integrated circuit structure includes a fin field-effect transistor (FinFET) including a semiconductor fin over and adjacent to insulation regions; and a source/drain region over the insulation regions. The source/drain region includes a first and a second semiconductor region. The first semiconductor region includes silicon and an element selected from the group consisting of germanium and carbon, wherein the element has a first atomic percentage in the first semiconductor region. The first semiconductor region has an up-slant facet and a down-slant facet. The second semiconductor region includes silicon and the element. The element has a second atomic percentage lower than the first atomic percentage. The second semiconductor region has a first portion on the up-slant facet and has a first thickness. A second portion of the second semiconductor region, if any, on the down-slant facet has a second thickness smaller than the first thickness. 1. A method comprising: forming a semiconductor fin over and adjacent insulation regions, wherein the;', 'forming a gate dielectric on a top surface, and extending on sidewalls, of the semiconductor fin;', 'forming a gate electrode on the gate dielectric; and', forming a first semiconductor region comprising silicon and an element selected from the group consisting of germanium and carbon, wherein the element has a first atomic percentage in the first semiconductor region, and wherein the first semiconductor region comprises an up-slant facet and a down-slant facet; and', 'forming a second semiconductor region comprising silicon and the element, wherein the element has a second atomic percentage in the second semiconductor region with the second atomic percentage being lower than the first atomic percentage, wherein the second semiconductor region comprises a first portion on the up-slant facet and having a first thickness, and wherein a second portion of the second semiconductor region on the down-slant facet has a second ...

Finfet parasitic capacitance reduction using air gap

A transistor, for example a FinFET, includes a gate structure disposed over a substrate. The gate structure has a width and also a length and a height defining two opposing sidewalls of the gate structure. The transistor further includes at least one electrically conductive channel between a source region and a drain region that passes through the sidewalls of the gate structure; a dielectric layer disposed over the gate structure and portions of the electrically conductive channel that are external to the gate structure; and an air gap underlying the dielectric layer. The air gap is disposed adjacent to the sidewalls of the gate structure and functions to reduce parasitic capacitance of the transistor. At least one method to fabricate the transistor is also disclosed.

Semiconductor structure and process thereof

A semiconductor structure includes a substrate, a recess and a material. The recess is located in the substrate, wherein the recess has an upper part and a lower part. The minimum width of the upper part is larger than the maximum width of the lower part. The material is located in the recess.

Method for manufacturing multi-gate transistor device

A method for manufacturing multi-gate transistor device includes providing a semiconductor substrate having a patterned semiconductor layer, a gate dielectric layer and a gate layer sequentially formed thereon, forming a multiple insulating layer sequentially having a first insulating layer and a second insulating layer and covering the patterned semiconductor layer and the gate layer, removing a portion of the multiple insulating layer to simultaneously form a first spacer around the gate layer and a second spacer around the patterned semiconductor layer, removing the second spacer to expose a portion of the first insulating layer covering the patterned semiconductor layer and simultaneously removing a portion of the first spacer to form a third spacer around the gate layer, and removing the exposed first insulating layer to expose the patterned semiconductor layer.

Bulk fin-field effect transistors with well defined isolation

A fin field-effect-transistor fabricated by forming a dummy fin structure on a semiconductor substrate. A dielectric layer is formed on the semiconductor substrate. The dielectric layer surrounds the dummy fin structure. The dummy fin structure is removed to form a cavity within the dielectric layer. The cavity exposes a portion of the semiconductor substrate thereby forming an exposed portion of the semiconductor substrate within the cavity. A dopant is implanted into the exposed portion of the semiconductor substrate within the cavity thereby creating a dopant implanted exposed portion of the semiconductor substrate within the cavity. A semiconductor layer is epitaxially grown within the cavity atop the dopant implanted exposed portion of the semiconductor substrate.

Mosfet with thin semiconductor channel and embedded stressor with enhanced junction isolation and method of fabrication

A field effect transistor structure that uses thin semiconductor on insulator channel to control the electrostatic integrity of the device. Embedded stressors are epitaxially grown in the source/drain area from a template in the silicon substrate through an opening made in the buried oxide in the source/drain region. In addition, a dielectric layer is formed between the embedded stressor and the semiconductor region under the buried oxide layer, which is located directly beneath the channel to suppress junction capacitance and leakage.

Semiconductor device and method of forming epitaxial layer

A semiconductor device includes a semiconductor substrate and a plurality of transistors. The semiconductor substrate includes at least an iso region (namely an open region) and at least a dense region. The transistors are disposed in the iso region and the dense region respectively. Each transistor includes at least a source/drain region. The source/drain region includes a first epitaxial layer having a bottom thickness and a side thickness, and the bottom thickness is substantially larger than or equal to the side thickness.

Semiconductor Device and Method of Manufacture

A system and method for etching a substrate is provided. An embodiment comprises utilizing an inert carrier gas in order to introduce a liquid etchant to a substrate. The inert carrier gas may prevent undesirable chemical reactions from taking place during the etching process, thereby helping to reduce the number of defects that occur to the substrate and other structures during the etching process.

Method of making lower parasitic capacitance finfet

An integrated circuit device includes a gate region extending above a semiconductor substrate and extending in a first longitudinal direction. A first fin has a first sidewall that extends in a second longitudinal direction above the semiconductor substrate such that the first fin intersects the gate region. A second fin has a second sidewall extending in the second direction above the semiconductor substrate such that the second fin intersects the gate region. A shallow trench isolation (STI) region is formed in the semiconductor substrate between the first and second sidewalls of the first and second fins. A conductive layer disposed over the first insulating layer and over top surfaces of the first and second fins. A first insulating layer is disposed between an upper surface of the STI region and a lower surface of the conductive layer to separate the STI region from the conductive layer.

Method for fabricating oxides/semiconductor interfaces

By depositing a layer of oxidizing metal on the semiconductor surface first and then depositing a layer of the high-k oxide material over the layer of oxidizing metal by an atomic layer deposition, a high-k metal oxide is formed at the interface between the semiconductor substrate and the high-k oxide and prevents formation of the undesirable low-k semiconductor oxide layer at the semiconductor/high-k oxide interface.

Method for manufacturing multi-gate transistor device

A method for manufacturing multi-gate transistor device includes providing a semiconductor substrate having a patterned semiconductor layer and a patterned hard mask sequentially formed thereon, removing the patterned hard mask, performing a thermal treatment to rounding the patterned semiconductor layer with a process temperature lower than 800° C., and sequentially forming a gate dielectric layer and a gate layer covering a portion of the patterned semiconductor layer on the semiconductor substrate.

Semiconductor device and method for fabricating the same

A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate of a first conductivity type, a fin, a gate, source and drain regions of a second conductivity type, and a first doped region of the second conductivity type. A plurality of isolation structures is formed on the substrate. The fin is disposed on the substrate between two adjacent isolation structures. The gate is disposed on the isolation structures and covers a portion of the fin, wherein the portion of the fin covered by the gate is of the first conductivity type. The source and drain regions is configured in the fin at respective sides of the gate. The first doped region is configured in the fin underlying the source and drain regions and adjoining the substrate. The first doped region has an impurity concentration lower than that of the source and drain regions.

Semiconductor Field-Effect Transistor Structure and Method for Manufacturing the Same

The present application discloses a semiconductor Field-Effect Transistor (FET) structure and a method for manufacturing the same, wherein the method comprises: forming a semiconductor substrate comprising an SOI structure having a body-contact hole; forming a fin on the SOI structure of the semiconductor substrate; forming a gate stack structure on top and side faces of the fin; forming source/drain structures in the fin on both sides of the gate stack structure; and performing metallization. The present invention makes use of traditional quasi-planar based top-down processes, thus the manufacturing process thereof becomes simple to implement; the present invention exhibits good compatibility with CMOS planar process and can be easily integrated; the present invention also is favorable for suppressing short channel effects desirably, and boosts MOSFETs to develop towards a trend of downscaling size. 1. A semiconductor Field-Effect Transistor (FET) structure , comprising:a fin located on a buried isolation dielectric layer, wherein the bottom of a channel region of the fin is connected to a substrate through a body-contact;wherein the isolation dielectric layer isolates other part of the fin than the channel region connected with the substrate through a body-contact from the substrate; andthe body-contact enables at least part of the channel region of the fin to form direct physical and electrical contact with the substrate;a gate electrode the direction of which is perpendicular to the direction of the fin, and a channel region is formed at a region where the fin and the gate electrode cross;gate dielectric, existing between the gate electrode and the fin; andsource and drain regions, which are located on both sides of the channel region and the gate electrode.2. A manufacturing method , comprising:forming a semiconductor substrate comprising an SOI structure having a body-contact hole;forming a fin on the SOI structure of the semiconductor substrate;forming a gate ...

Manufacturing techniques to limit damage on workpiece with varying topographies

Some embodiments relate to a method for processing a workpiece. In the method, a first photoresist layer is provided over the workpiece, wherein the first photoresist layer has a first photoresist tone. The first photoresist layer is patterned to provide a first opening exposing a first portion of the workpiece. A second photoresist layer is then provided over the patterned first photoresist layer, wherein the second photoresist layer has a second photoresist tone opposite the first photoresist tone. The second photoresist layer is then patterned to provide a second opening that at least partially overlaps the first opening to define a coincidentally exposed workpiece region. A treatment is then performed on the coincidentally exposed workpiece region. Other embodiments are also disclosed.

STRESSED CHANNEL FET WITH SOURCE/DRAIN BUFFERS

A stressed channel field effect transistor (FET) includes a substrate; a gate stack located on the substrate; a channel region located in the substrate under the gate stack; source/drain stressor material located in cavities in the substrate on either side of the channel region; and vertical source/drain buffers located in the cavities in the substrate between the source/drain stressor material and the substrate, wherein the source/drain stressor material abuts the channel region above the source/drain buffers. 1. A stressed channel field effect transistor (FET) , comprising:a substrate;a gate stack located on the substrate;a channel region located in the substrate under the gate stack;source/drain stressor material located in cavities in the substrate on either side of the channel region; andvertical source/drain buffers located in the cavities in the substrate between the source/drain stressor material and the substrate, wherein the source/drain stressor material abuts the channel region above the source/drain buffers.2. The FET of claim 1 , wherein the vertical source/drain buffers comprise undoped or lightly boron doped silicon germanium in the event the FET comprises a p-type FET claim 1 , and undoped or lightly phosphorous doped silicon carbide in the event the FET comprises an n-type FET.3. The FET of claim 1 , wherein the source/drain stressor material comprises highly boron doped silicon germanium in the event the FET comprises a p-type FET claim 1 , and highly phosphorous doped silicon carbide in the event the FET comprises an n-type FET.4. The FET of claim 1 , wherein the region in which the source/drain stressor material abuts the channel region above the vertical source/drain buffers has a depth from about 5 nanometers to about 15 nanometers below the bottom of the gate stack.5. The FET of claim 1 , wherein the substrate comprises a silicon-on-insulator (SOI) substrate claim 1 , and wherein the cavities are located in a top silicon layer of the SOI ...

Method for Making FinFETs and Semiconductor Structures Formed Therefrom

A method for making FinFETs and semiconductor structures formed therefrom is disclosed, comprising: providing a SiGe layer on a Si semiconductor substrate and a Si layer on the SiGe layer, wherein the lattice constant of the SiGe layer matches that of the substrate; patterning the Si layer and the SiGe layer to form a Fin structure; forming a gate stack on top and both sides of the Fin structure and a spacer surrounding the gate stack; removing a portion of the Si layer which is outside the spacer with the spacer as a mask, while keeping a portion of the Si layer which is inside the spacer; removing a portion of the SiGe layer which is kept after the patterning, to form a void; forming an insulator in the void; and epitaxially growing stressed source and drain regions on both sides of the Fin structure and the insulator. 1. A method for making a Fin field-effect transistor , comprising:providing a semiconductor substrate, a SiGe layer on the semiconductor substrate and a Si layer on the SiGe layer, wherein the lattice constant of the SiGe layer matches with that of the substrate;patterning the Si layer and the SiGe layer to form a Fin structure;forming a gate stack on top and both sides of the Fin structure and a spacer surrounding the gate stack;removing a portion of the Si layer which is outside the spacer with the spacer as a mask, while keeping a portion of the Si layer which is inside the spacer;removing a portion of the SiGe layer which is kept after the patterning, to form a void;forming an insulator in the void; andepitaxially growing stressed source and drain regions located on both sides of the Fin structure and the insulator.2. The method according to claim 1 , wherein the step of forming the Fin structure comprises:using a patterned photo-resist material layer as a mask, etching portions of the Si layer and the SiGe layer which are outside the photo-resist material layer, while keeping portions of the Si layer and SiGe layer which are inside the photo- ...

Mechanisms for forming stressor regions in a semiconductor device

The embodiments of processes and structures described above provide mechanisms for improving mobility of carriers. The dislocations in the source and drain regions and the strain created by the doped epitaxial materials next to the channel region of a transistor both contribute to the strain in the channel region. As a result, the device performance is improved.

CROSS-HAIR CELL WORDLINE FORMATION

Methods and devices depicting fabrication of non-planar access devices having fins and narrow trenches, among which is a method that includes wet etching a conductor to form a recessed region and subsequently etching the conductor to form gates on the fins. The wet etching may include formation of recesses which are may be backfilled with a fill material to form spacers on the conductor. Portions of a plug may be removed during the wet etch to form overhanging spacers to provide further protection of the conductor during the dry etch. 1. A method of fabricating an access device , comprising:forming a trench having a first sidewall, second sidewall, and bottom surface;depositing a gate oxide on the first sidewall, second sidewall, and bottom surface;depositing a conductor on the gate oxide;depositing a plug in the trench;etching the conductor to form one or more recesses;removing a portion of the plug to form a region that extends substantially over the conductor;filling the recesses with a fill material to form an overhanging spacer that extends substantially over the conductor; andspacer etching the conductor to form a first wordline on the first sidewall and a second wordline on the second sidewall.2. The method of claim 1 , wherein the overhanging spacer protects a portion of the conductor during the spacer etching.3. The method of claim 1 , wherein a first fin having the first sidewall comprises a first silicon nitride cap and a first pad oxide cap claim 1 , wherein the first silicon nitride cap protects the first fin during the dry spacer etching.4. The method of claim 3 , wherein a second fin having the second sidewall comprises a second silicon nitride cap and a second pad oxide cap claim 3 , wherein the second silicon nitride cap protects the fin during the spacer etching.5. The method of claim 4 , wherein the recess extends about 60 nanometers from the top of the first fin claim 4 , the second fin claim 4 , or a combination thereof.6. The method of claim 1 ...

Semiconductor devices having stressor regions and related fabrication methods

Apparatus for semiconductor device structures and related fabrication methods are provided. One method for fabricating a semiconductor device structure involves forming a gate structure overlying a region of semiconductor material, wherein the width of the gate structure is aligned with a <100> crystal direction of the semiconductor material. The method continues by forming recesses about the gate structure and forming a stress-inducing semiconductor material in the recesses.

Integrated Circuit Device, System, and Method of Fabrication

A semiconductor device, comprising a first semiconductor portion having a first end, a second end, and a slit portion, wherein the width of the slit portion is less than the width of at least one of the first end and the second end; a second portion that is a different material than the first semiconductor portion, a third portion that is a different material than the first semiconductor portion, wherein the second and third portions are on opposite sides of the slit portion, and at least three terminals selected from a group consisting of a first terminal connected to the first end, a second terminal connected to the second end, a third terminal connected to the second portion, and a fourth terminal connected to the third portion.

DEVICE WITH SELF ALIGNED STRESSOR AND METHOD OF MAKING SAME

A method includes providing a substrate comprising a substrate material, a gate dielectric film above the substrate, and a first spacer adjacent the gate dielectric film. The spacer has a first portion in contact with a surface of the substrate and a second portion in contact with a side of the gate dielectric film. A recess is formed in a region of the substrate adjacent to the spacer. The recess is defined by a first sidewall of the substrate material. At least a portion of the first sidewall underlies at least a portion of the spacer. The substrate material beneath the first portion of the spacer is reflowed, so that a top portion of the first sidewall of the substrate material defining the recess is substantially aligned with a boundary between the gate dielectric film and the spacer. The recess is filled with a stressor material. 1. A transistor comprising ,a substrate comprising a substrate material, a gate dielectric film above the substrate, a gate above the gate dielectric film and first and second spacers adjacent to the gate dielectric film, the first spacer having a portion in contact with a first side of the gate dielectric film, the second spacer having a portion in contact with a second side of the gate dielectric film;a source stressor region and a drain stressor region in the substrate, the source stressor region having an edge substantially aligned with a boundary between the gate dielectric film and the first spacer, the drain stressor region having an edge substantially aligned with a boundary between the gate dielectric film and the second spacer, the source stressor region and drain stressor region each filled with a stressor material that causes a stress in a channel between the source stressor region and drain stressor region, the source stressor region and the drain stressor region each having a curved bottom edge.2. The transistor of claim 1 , wherein the aligned edges of the source and drain stressor regions have straight portions ...

Source/drain extension control for advanced transistors

A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate is positioned over the substantially undoped channel on the substrate. Implanted source/drain extensions contact the source and the drain, with the implanted source/drain extensions having a dopant concentration of less than about 1×10 19 atoms/cm 3 ′, or alternatively, less than one-quarter the dopant concentration of the source and the drain.

Method for growing conformal epi layers and structure thereof

A method for forming a conformal buffer layer of uniform thickness and a resulting semiconductor structure are disclosed. The conformal buffer layer is used to protect highly-doped extension regions during formation of an epitaxial layer that is used for inducing mechanical stress on the channel region of transistors.