Efficient use of wafer area with device under the pad approach
Номер патента: EP1709685A1
Опубликовано: 11-10-2006
Автор(ы): Darlene G. Hamilton, Hiroyuki Ogawa, Kuo-Tung Chang, Nian Yang, Yider Wu, Yu Sun
Принадлежит: SPANSION LLC
Опубликовано: 11-10-2006
Автор(ы): Darlene G. Hamilton, Hiroyuki Ogawa, Kuo-Tung Chang, Nian Yang, Yider Wu, Yu Sun
Принадлежит: SPANSION LLC
Реферат: More efficient use of silicon area is achieved by incorporating an active device (25) beneath a pad area (21) of a semiconductor structure (20). The pad area (21) includes a substrate (22) having a first metal layer (23) above it. A second metal layer (26) is below the first metal layer (23). The active device (25) resides in the substrate (22) below the second metal layer (26). A layet of dielectric layer (24) separates the first (26) and second metal layers (23). A via (27) within the dielectric layer (24) electrically couples the first (23) and second metal layers (26). A via (27) connects to the active component (25). Subsequent metal layers (424, 425, 426) can be arranged between the first (23) and second metal layers (26).
Method of wafer dicing for backside metallization
Номер патента: US20170358537A1. Автор: Colby Rampley,L. Scott KLINGBEIL. Владелец: NXP USA Inc. Дата публикации: 2017-12-14.