Reset and safe state logic generation in dual power flow devices
Номер патента: EP4187789A1
Опубликовано: 31-05-2023
Автор(ы): Dhulipalla Phaneendra KUMAR, Gourav Garg, Mayankkumar Hareshbhai Niranjani, Sourabh Banzal, V Narayanan SRINIVASAN
Принадлежит: STMicroelectronics International NV Switzerland
Опубликовано: 31-05-2023
Автор(ы): Dhulipalla Phaneendra KUMAR, Gourav Garg, Mayankkumar Hareshbhai Niranjani, Sourabh Banzal, V Narayanan SRINIVASAN
Принадлежит: STMicroelectronics International NV Switzerland
Реферат: An electric device (100) includes: a first power domain (101); a second power domain (103); a third power domain (105), where during power-up, the third, the second, and the first power domains are configured to be powered up sequentially, where during standby-exit, the first, the second, and the third power domains are configured to be powered up sequentially; isolation paths (111, 112, 113, 114, 115, 116) that provide controlled signal transmission among the first, the second, and the third power domains, where each isolation path includes an isolation circuit between an input power domain and an output power domain of the isolation path; and a control circuit in the first power domain, where for each isolation path, the control circuit is configured to generate an isolation control signal (ISO_CTRLS) for the isolation circuit, where the isolation circuit is configured enable or disable signal transmission along the isolation path.
Reset and safe state logic generation in dual power flow devices
Номер патента: US20230168699A1. Автор: Venkata Narayanan Srinivasan,Dhulipalla Phaneendra KUMAR,Mayankkumar Hareshbhai Niranjani,Gourav Garg,Sourabh Banzal. Владелец: STMicroelectronics International NV Switzerland. Дата публикации: 2023-06-01.