Configurable oversampling for an analog-to-digital converter
Номер патента: EP3811519A2
Опубликовано: 28-04-2021
Автор(ы): David Peter Foley, Devin Allen COTTIER, Manish Bhardwaj
Принадлежит: Texas Instruments Inc
Опубликовано: 28-04-2021
Автор(ы): David Peter Foley, Devin Allen COTTIER, Manish Bhardwaj
Принадлежит: Texas Instruments Inc
Реферат: A system includes a central processing unit (CPU) core (102), and a pulse width modulator (PWM) controller (110) configured to generate a PWM control signal having a PWM cycle. The system also includes an analog-to-digital converter (ADC) (162), an accumulator (170), a sum register (178), and an oversampling register set (120). The oversampling register set (120) is configurable by the CPU core (102) to specify time points during each PWM cycle when the ADC (162) is to convert an analog signal to a digital sample to produce a plurality of digital samples. The time spacing between consecutive digital samples varies among the specified time points. The accumulator (170) accumulates digital samples from the ADC and stores an accumulated sum in the sum register (178). The CPU core reads the accumulated sum from the sum register (178), and can use the accumulated sum to calculate a metric (e.g., an average) of the digital samples.
Configurable oversampling for an analog-to-digital converter
Номер патента: WO2020040855A2. Автор: Manish Bhardwaj,David Peter Foley,Devin Allen COTTIER. Владелец: Texas Instruments Japan Limited. Дата публикации: 2020-02-27.