Memory bit cell circuit including a bit line coupled to a static random-access memory (sram) bit cell circuit and a non-volatile memory (nvm) bit cell circuit and a memory bit cell array circuit
Номер патента: EP4260320A1
Опубликовано: 18-10-2023
Автор(ы): Bharani Chava, Khaja Ahmad SHAIK
Принадлежит: Qualcomm Inc
Опубликовано: 18-10-2023
Автор(ы): Bharani Chava, Khaja Ahmad SHAIK
Принадлежит: Qualcomm Inc
Реферат: An exemplary memory bit cell circuit, including a bit line coupled to an SRAM bit cell circuit and an NVM bit cell circuit, with reduced area and reduced power consumption, included in a memory bit cell array circuit, is disclosed. The SRAM bit cell circuit includes cross-coupled true and complement inverters and a first access circuit coupled to the bit line. The NVM bit cell circuit includes an NVM device coupled to the bit line by a second access circuit and is coupled to the SRAM bit cell circuit. Data stored in the SRAM bit cell circuit and the NVM bit cell circuit are accessed based on voltages on the bit line. A true SRAM data is determined by an SRAM read voltage on the bit line, and an NVM data in the NVM bit cell circuit is determined by a first NVM read voltage on the bit line.
Non-volatile static random access memory (nvsram) with multiple magnetic tunnel junction cells
Номер патента: US20240296887A1. Автор: Yih Wang,Hiroki Noguchi,Perng-Fei Yuh,Jui-che Tsai,Fu-An Wu,Ku-Feng Lin. Владелец: Taiwan Semiconductor Manufacturing Co TSMC Ltd. Дата публикации: 2024-09-05.