Method and apparatus for concurrent emulation of multiple circuit designs on an emulation system
Номер патента: EP1135736A1
Опубликовано: 26-09-2001
Автор(ы): Frederic Reblewski
Принадлежит: Mentor Graphics Corp
Опубликовано: 26-09-2001
Автор(ы): Frederic Reblewski
Принадлежит: Mentor Graphics Corp
Реферат: An emulation system equipped to emulate multiple circuit designs concurrently is disclosed. The emulation system includes an emulator having reconfigurable emulation resources for emulating circuit designs, and a host system programmed with programming instructions that operate to generate coordinated configuration information for a number of circuit designs to enable the recofigurable emulation resources to be configured in a coordinated manner to allow the circuit designs to be emulated concurrently.
Method and computer program for estimating speed-up and slow-down net delays for an integrated circuit design
Номер патента: US20060294482A1. Автор: Alexander Tetelbaum. Владелец: LSI Logic Corp. Дата публикации: 2006-12-28.