Comparator with complementary differential input stages
Номер патента: EP2122829A1
Опубликовано: 25-11-2009
Автор(ы): Roger Colbeck
Принадлежит: Power Integrations Inc
Опубликовано: 25-11-2009
Автор(ы): Roger Colbeck
Принадлежит: Power Integrations Inc
Реферат: A comparator comprises complementary (e.g. NMOS and PMOS) comparator cells (40, 41) having overlapping common mode input voltage ranges which together extend approximately from rail to rail. A digital logic arrangement, including edge detectors (42, 43), gates (44, 45), and a latch (48), is responsive to transitions at the outputs of the comparator cells to set the latch in response to the earliest rising edge and to reset the latch in response to the earliest falling edge. An output of the latch constitutes an output of the comparator. Consequently the comparator is edge-sensitive with a speed optimized for a wide common mode input voltage range. Additional logic gates (46, 47) can provide level-sensitive control of the latch.
Comparator with complementary differential input stages
Номер патента: EP2122829A4. Автор: Roger Colbeck. Владелец: Power Integrations Inc. Дата публикации: 2010-05-26.