SEMICONDUCTOR ELEMENT INCLUDING CAPACITOR

Advantages and features of the present invention, achieve the appended drawing method and an electronic component connected to the reference surface with specifically carry activitycopyright will in the embodiment. In the present invention refers to hereinafter however limited to the disclosure in the embodiment but can be embodied in the form of various different, in the embodiment of the present invention disclosure is to only the completely, to complete the present invention of the invention is provided to a target number for informing a person with skill in the art categories in which ball, defined by category of the present invention refers to claim only disclosed. The same references refer to the same components across special specification.

The specification describes in the embodiment for the present invention the term used in which relayed a number that is even endured. In the specification, a plurality type comprises a unit in a single may be phrase will not specially mentioned. Used in specification 'includes (comprises)' and/or 'including (comprising)' handle components, steps, operation and/or element comprises at least one other components, steps, operation and/or devices does not number the presence or addition times.

In addition, in the embodiment of the present invention are discussed specification the ideal example products on be described and/or plane view that excels in the cross-sectional drawing are disclosed. Substrate in drawing, description and technical content of effective for exaggerated thickness regions are disclosed. The, number bath techniques and/or tolerances of form can be modified by example degrees. Thus, the specific number of the present invention in the embodiment shown are but one type of change including process for preparing produced in accordance number are disclosed. For example, the etching area shown at right angles having angular or round for conveniently discharging may be in the form disclosed. The, drawing exemplified regions are coarse has attribute, for example the shape for drawing exemplified areas in the region of the invention which form relayed number categories for endured.

Figure 1 shows a unit memory cell of the present invention in the embodiment according to method for formatting data are also are disclosed.

The reference also 1, memory cell (MC) intersect one another word line and a bit line (BL) (WL) can be electrically connecting between them. Said memory cell (MC) is connected to said word line (WL) transistor (TR), and said transistor (TR) (CA) can be connected to a capacitor. Said transistor (TR) number 1 of said bit line (BL) can be connected to the impurity region, the impurity region of said transistor (TR) number 2 can be connected to said capacitor (CA). Said transistor (TR) includes a capacitor (CA) under [e flow of charge flowing into said number can be configured. The charge stored in said capacitor (CA) said memory cell (MC) whether 0 or 1 according can be stores.

In hereinafter, said capacitor (CA) of the present invention in the embodiment according to said semiconductor device are included in mammals are also described therein.

Figure 3 shows a cross-section of the present invention in the embodiment 2 and are also representing semiconductor according to also are disclosed.

The reference 2 also and also 3, substrate (100) on the first oxide layer (110) is 1308. ball number. Said substrate (100) be a semiconductor substrate. E.g., said substrate (100) silicon substrate includes, germanium substrate, or a silicon - germanium may be the substrate disclosed. According to some in the embodiment, said substrate (100) (not shown) such as a transistor (e.g., number 1 and number 2 impurity regions) comprising a portion of the configuration can be, said interlayer insulating film (110) thereof can thin the. Said interlayer insulation film (110) silicon, silicon nitride, or silicon oxynitride comprising and/can be.

Said interlayer insulation film (110) in, said interlayer insulating film (110) through said substrate (100) is electrically connected to the capping (112) is 1308. ball number. Said contact plug (112) is electrically connected to one terminal of said transistor (e.g., number 2 impurity region) can be. Said contact plug (112) can be a conductive material. In one example, said contact plug (112) is impurity doped semiconductor (e.g., doped silicon, doped germanium, doped silicon - germanium or the like), metal (e.g., titanium, tantalum hafnium, tungsten and the like), conductive metal nitride (e.g., titanium nitride, tantalum nitride or the like), and/or metal - semiconductor compound comprising (e.g., metal silicide) can be.

Said interlayer insulation film (110) on the storage electrode (BE) is 1308. ball number. Said lower electrode (BE) is said contact plug (112) through said substrate (100) can be electrically connected. Said lower electrode of the capacitor in the form of etched 9a to 9c (BE) also refers to carry. Said lower electrode (BE) an impurity-doped silicon, metal, conductive metal nitride, and/or metal - semiconductor compound can be.

(BE) dielectric layer on said lower electrode is co 1308. (DL) number. Said dielectric layer (DL) comprises at least one oxidizing agent, at least one silicon oxide film, and at least one aluminum oxide layer can be.

According to some in the embodiment, as shown in 2 or 3 may also, said dielectric layer (DL) is high dielectric (HDL), silicon oxide film (SOL), and aluminum oxide comprising (AOL) can be.

the lower electrode on said high dielectric (HDL) (BE) 1308. ball number. According to some in the embodiment, the lower electrode directly on said high dielectric (HDL) said number ball 1308. (BE) (directly on). In other words, according to some in the embodiment, the lower electrode can be in contact with said said high dielectric (HDL) (BE). the high dielectric (HDL) (SOL) and said aluminum oxide layer and the external electrode than said silicon oxide film (AOL) may have. For example, the high dielectric (HDL) ZrO₂ Film, TiO₂ Film, HfO₂ Film, Ta₂ O₅ Film, Nb₂ O₅ Film, SrTiO₃ Film, BaTiO₃ Film, and Ba_x Sr_1-x TiO₃ (0<X<1) film can be at least one. Said thickness of said silicon oxide film comprises a high dielectric (HDL) (HDL_TH) (SOL) (SOL_TH) and aluminum oxide (AOL) greater than said thickness of thickness of (AOL_TH) can be. For example, thickness of about 20 Å to about 70 Å (HDL_TH) said high dielectric (HDL) implementation being. Said high dielectric (HDL) is, for example, can be formed using atomic layer deposition (Atomic Layer Deposition; ALD), crystalline (crystalline) implementation being.

On said high dielectric (HDL), said silicon oxide film (SOL) and said aluminum oxide is co 1308. (AOL) number. According to some in the embodiment, as shown in fig. 2, said silicon oxide film (SOL) is interposed between said high dielectric (HDL) and said aluminum oxide (AOL) can be. According to another in the embodiment, as shown in fig. 3, the high dielectric (HDL) and said aluminum oxide (AOL) (SOL) can be interposed between said silicon oxide film.

Said silicon oxide film is SiO (SOL)₂ And include, said Al is aluminum oxide (AOL)₂ O₃ Can be a. Said silicon oxide film (SOL) and said aluminum oxide (AOL) is greater than said high dielectric (HDL) may have a band gap (band gap), the leakage current is generated from the dielectric layer (DL) can number billion. In some in the embodiment, the thickness of said silicon oxide film (SOL) has a thickness of about 0 (HDL_TH) (SOL_TH) said high dielectric (HDL). 003 From about 1.5 to about 0. 5 Bail be. For example, the thickness of said silicon oxide film (SOL) (SOL_TH) about 0. 2 Å to about 10 Å implementation being. In some in the embodiment, said thickness of said high dielectric (HDL) aluminum oxide (AOL) (AOL_TH) has a thickness of about 0 (HDL_TH). 005 From about 1.5 to about 0. 5 Bail be. For example, aluminum oxide (AOL) (AOL_TH) said thickness of about 0. 3 Å to about 10 Å implementation being. According to some in the embodiment, the thickness of said silicon oxide film has a thickness of said aluminum oxide layer (SOL) (SOL_TH) (AOL_TH) (AOL) may be less than disclosed. However, the present invention herein are limited endured. Said silicon oxide film (SOL) and said aluminum oxide (AOL) is, for example, atomic layer deposition (ALD) can be formed using, amorphous (amorphous) implementation being. According to some in the embodiment, also shown in 2 and 3 also alternatively, said silicon oxide film (SOL) and/or the extending underneath said aluminum oxide (AOL) to secure (to partially cover) can be formed.

(DL) on said dielectric layer, the upper electrode (TE) 1308. ball number. Said upper electrode (TE) an impurity-doped silicon, metal, conductive metal nitride, and/or metal - semiconductor compound can be. (BE) said lower electrode, said dielectric layer (DL), and said upper electrode (TE) constituting said capacitor (CA) described with reference to the 1 also can be. Said capacitor (CA) is said contact plug (112) through said substrate (100) (not shown) formed on one terminal of said transistor (e.g., number 2 impurity region) can be electrically connected.

A leakage current of a capacitor of the present invention in the embodiment according to the 4a represents a are also are disclosed.

Specifically, 4a also includes a lower electrode are sequentially stacked, high dielectric, silicon oxide, aluminum oxide, silicon oxide thickness (transverse axis) according to voltage of said capacitor and a personal record are - leakage current density exhibits (longitudinal axis) curve. Said lower electrode and an upper electrode is formed into an TiN. Said a tunnel about 40 Å of ZrO₂ A transparent conductive layer uses a membrane, said aluminum oxide layer of about 5 Å Al₂ O₃ Film was used. Said silicon oxide film is 0 Å (i.e., silicon oxide film not), 0. 4 Å, and 0. 8 Å of SiO₂ Each film was used.

The 4a also reference, it is confirmed whether the silicon compared, when silicon in the same low leakage current density can be confirmed. In addition, a thick oxide film is 0. One as an 4 Å, a thick oxide film is 0. 8 Å in leakage current density when making sure that the supports can be the same.

I.e., according to of the present invention in the embodiment, a dry oxide layer including the aluminum oxide layer in a silicon-on dielectric layer by introducing reducing leakage current of capacitor can be.

According to equivalent oxide thickness (EOT) represents a capacitor of the present invention in the embodiment are 4b is also are disclosed.

Specifically, 4b also includes a lower electrode are sequentially stacked, high dielectric, silicon oxide, aluminum oxide, and a personal record are equivalent oxide film thickness expected values and measured value (transverse axis) capacitor, and said capacitor leakage current density 10^-3 (A/cm² ) (Longitudinal axis) corresponding to negative voltage value by a goniophotometer. Fig. 4a measure taught are the same as capacitor. Capacitor equivalent oxide film thickness relative to the thickness of an equivalent oxide defined expected value (=equivalent oxide thickness (thickness of a dielectric film) * (SiO₂ Dielectric constant)/(dielectric layer)) is a value obtained using, hollow won shown disclosed. Capacitor equivalent oxide thickness number equivalent oxide film thickness determining the capacitor prepared by the number to a measure of the chamber which, filled rectangular shown disclosed.

The 4b also reference, the predicted value and the measured value equivalent oxide thickness silicon without the oxide capacitor when compared to relate to, expected value equivalent oxide film thickness than when introduced silicon capacitor confirm a measurement value can be small. In addition, a thick oxide film is 0. One as an 4 Å, a thick oxide film is 0. When the value of the predicted value and the measured equivalent oxide thickness 8 Å is also used for large can be.

I.e., according to of the present invention in the embodiment, a dry oxide layer including the aluminum oxide layer in a silicon-on dielectric layer by introducing capacitor reduces the leakage current, the increase in equivalent oxide thickness can be reduced.

Figure 6 shows a cross-section of the present invention in the embodiment according to semiconductor representing 5 and also are also are disclosed.

5 And 6 may also reference surface, a semiconductor device includes a substrate (100), an interlayer insulating film (110), contact plug (112), a capacitor (CA) can be. Said capacitor comprises a lower electrode (BE) (CA) are sequentially stacked, dielectric layer (DL), and an upper electrode comprising (TE) can be.

Said substrate (100), said interlayer insulating film (110), said contact plug (112), said lower electrode (BE), and said upper electrode (TE) 3 2 and also with reference to the pulverized product can be also substantially the same, details description for the dispensed to each other.

Said upper electrode and the lower electrode (BE) said dielectric layer (DL) between said ball 1308. (TE) number. Said dielectric layer (DL) comprises at least one oxidizing agent, at least one silicon oxide film, and at least one aluminum oxide layer can be.

According to some in the embodiment, as shown in also 5 or 6 also, said dielectric layer (DL) high dielectric (HDL1) the number 1, number 2 (HDL2) high dielectric, silicon oxide film (SOL1) number 1, number 2 (SOL2) silicon oxide film, and comprising aluminum oxide (AOL) can be.

Said number 1 and number 2 before just the lower electrode on said unique number ball 1308. (HDL1 and HDL2) (BE). According to some in the embodiment, the lower electrode directly on said high dielectric (HDL1) said number 1 (BE) 1308. ball number. In other words, according to some in the embodiment, the lower electrode can be in contact with said said number 1 high dielectric (HDL1) (BE). Said number 2 (HDL2) said number 1 on the high dielectric high dielectric (HDL1) can be ball number, said number 1 and number 2 (HDL1 and HDL2) (SOL1) before just unique number 1 can be interposed between the silicon oxide film. Said number 1 and number 2 (SOL1 and SOL2) said number 1 and number 2 is unique before just (HDL1 and HDL2) silicon oxide films, and said dielectric constant greater than aluminum oxide (AOL) may have. For example, each of the number 1 and number 2 before just unique (HDL1 and HDL2) ZrO₂ Film, TiO₂ Film, HfO₂ Film, Ta₂ O₅ Film, Nb₂ O₅ Film, SrTiO₃ Film, BaTiO₃ Film, and Ba_x Sr_1-x TiO₃ (0<X<1) film can be at least one. Said number 1 and number 2 before just unique thicknesses of each of the number 1 and number 2 (HDL1 and HDL2) silicon oxide films (SOL1 and SOL2) (HDL1_TH and HDL2_TH) (SOL1_TH and SOL2_TH) and said aluminum oxide layer thicknesses of greater than thickness of (AOL) (AOL_TH) can be. Further, high dielectric thickness of said number 1 (HDL1) is greater than the thickness of said number 2 (HDL1_TH) high dielectric (HDL2) (HDL2_TH) can be. For example, thickness of about 20 Å to about 70 Å (HDL1_TH) high dielectric (HDL1) said number 1 may be, thickness of about 30 Å to about 40 Å (HDL2_TH) said number 2 high dielectric (HDL2) implementation being. Said number 1 and number 2 (HDL1 and HDL2) unique before just each of the, e.g., atomic layer deposition (ALD) can be formed using.

According to some in the embodiment, high dielectric (HDL1) said number 1 may be crystalline, amorphous or crystalline lower than said number 2 (HDL2) high dielectric having high dielectric (HDL1) said number 1 can be crystalline (crystallinity). (Crystalline any film that is high in comparison with other films, included atoms are relatively regular membrane structural arrangement that can be interpreted as meaning. On the contrary, some film crystallinity that is lower than the other films, included atoms are relatively regular membrane structural arrangement can be interpreted as meaning no.) this, said number 1 (BE) lower electrode formed on the high dielectric (HDL1) said crystalline, said number 2 high dielectric (HDL2) (SOL1) is formed on the amorphous silicon oxide film on said number 1 be a. In this case, the high dielectric constant greater than said number 1 high dielectric (HDL1) said number 2 (HDL2) may have. For example, high dielectric (HDL1) said number 1 and said number 2 both high dielectric (HDL2) ZrO₂ Even if film, high dielectric (HDL1) said number 2 (HDL2) said number 1 can be greater than the second conductive layer of high dielectric constant.

Said number 1 (SOL1) said number 1 and number 2 (HDL1, HDL2) silicon oxide film before just the unique number between ball 1308. Said number 2 (AOL) (SOL2) and said aluminum oxide layer is a silicon oxide film on said number 2 high dielectric (HDL2) 1308. ball number. According to some in the embodiment, as shown in fig. 5, silicon oxide and aluminum oxide high dielectric (HDL2) (SOL2) said number 2 is said number 2 (AOL) can be interposed between said. According to another in the embodiment, as shown in fig. 6, said dielectric and said number 2 (HDL2) is aluminum oxide (AOL) said number 2 (SOL2) can be interposed between the silicon oxide film.

The silicon oxide films (SOL1 and SOL2) said number 1 and number 2 SiO₂ And include, said Al is aluminum oxide (AOL)₂ O₃ Can be a. Silicon oxide films (SOL1 and SOL2) said number 1 and number 2, and said greater than the band gap of the aluminum oxide (AOL) said high dielectric (HDL) may have, the leakage current is generated from the dielectric layer (DL) can number billion. In some in the embodiment, silicon oxide films (SOL1 and SOL2) said number 1 and number 2 thicknesses of each of the number 1 (SOL1_TH and SOL2_TH) high dielectric (HDL1) (HDL1_TH) thickness of about 0. 003 From about 1.5 to about 0. 5 Bail be. For example, silicon oxide films (SOL1 and SOL2) said number 1 and number 2 of each of the thicknesses (SOL1_TH and SOL2_TH) about 0. 2 Å to about 10 Å implementation being. In some in the embodiment, the thickness of said aluminum oxide layer has a thickness of said number 1 (AOL) (AOL_TH) (HDL1_TH) high dielectric (HDL1) about 0. 005 From about 1.5 to about 0. 5 Bail be. For example, aluminum oxide (AOL) (AOL_TH) said thickness of about 0. 3 Å to about 10 Å implementation being. According to some in the embodiment, silicon oxide films (SOL1 and SOL2) said number 1 and number 2 of each of the thickness of said aluminum oxide layer thicknesses (SOL1_TH and SOL2_TH) (AOL_TH) (AOL) may be less than disclosed. However, the present invention herein are limited endured. Silicon oxide films (SOL1 and SOL2) said number 1 and number 2, and said aluminum oxide (AOL) is, for example, atomic layer deposition (ALD) can be formed using, can be amorphous. According to some in the embodiment, also shown in 5 and 6 also alternatively, said number 1 (SOL1) silicon oxide film, a silicon oxide film (SOL2) said number 2, and/or aluminum oxide layer underneath said (AOL) is partially covers the film can be formed.

Also 4a and 4b through a browser as a also, according to of the present invention in the embodiment, a dry oxide layer including the aluminum oxide layer in a silicon-on dielectric layer by introducing capacitor reduces the leakage current, the increase in equivalent oxide thickness can be reduced.

Figure 8 shows a cross-section of the present invention in the embodiment according to semiconductor representing 7 and also are also are disclosed.

Also 7 and 8 also reference surface, a semiconductor device includes a substrate (100), an interlayer insulating film (110), contact plug (112), a capacitor (CA) can be. Said capacitor comprises a lower electrode (BE) (CA) are sequentially stacked, dielectric layer (DL), and an upper electrode comprising (TE) can be.

Said substrate (100), said interlayer insulating film (110), said contact plug (112), said lower electrode (BE), and said upper electrode (TE) 3 2 and also with reference to the pulverized product can be also substantially the same, details description for the dispensed to each other.

Said upper electrode and the lower electrode (BE) said dielectric layer (DL) between said ball 1308. (TE) number. Said dielectric layer (DL) comprises at least one oxidizing agent, at least one silicon oxide film, and at least one aluminum oxide layer can be.

According to some in the embodiment, as shown in 7 or 8 may also, said dielectric layer (DL) high dielectric (HDL1) the number 1, number 2 high dielectric (HDL2), aluminum oxide (AOL1) number 1, number 2 (AOL2) aluminum oxide, comprising silicon oxide layer (SOL) can be.

Said number 1 and number 2 before just the lower electrode on said unique number ball 1308. (HDL1 and HDL2) (BE). According to some in the embodiment, the lower electrode directly on said high dielectric (HDL1) said number 1 (BE) 1308. ball number. In other words, according to some in the embodiment, the lower electrode can be in contact with said said number 1 high dielectric (HDL1) (BE). Said number 2 (HDL2) said number 1 on the high dielectric high dielectric (HDL1) can be ball number, said number 1 and number 2 (HDL1 and HDL2) unique before just can be interposed between aluminum oxide (AOL1) number 1. Said number 1 and number 2 before just said number 1 and number 2 (AOL1 and AOL2) aluminium oxynitride films (HDL1 and HDL2) is unique, and said dielectric constant greater than silicon oxide film (SOL) may have. For example, each of the number 1 and number 2 before just unique (HDL1 and HDL2) ZrO₂ Film, TiO₂ Film, HfO₂ Film, Ta₂ O₅ Film, Nb₂ O₅ Film, SrTiO₃ Film, BaTiO₃ Film, and Ba_x Sr_1-x TiO₃ (0<X<1) film can be at least one. Said number 1 and number 2 before just unique thicknesses of each of the number 1 and number 2 (HDL1 and HDL2) (HDL1_TH and HDL2_TH) aluminium oxynitride films of thicknesses (AOL1 and AOL2) and greater than the thickness of said silicon oxide film (SOL) (AOL1_TH and AOL2_TH) (SOL_TH) can be. Further, high dielectric thickness of said number 1 (HDL1) is greater than the thickness of said number 2 (HDL1_TH) high dielectric (HDL2) (HDL2_TH) can be. For example, thickness of about 20 Å to about 70 Å (HDL1_TH) high dielectric (HDL1) said number 1 may be, thickness of about 30 Å to about 40 Å (HDL2_TH) said number 2 high dielectric (HDL2) implementation being. Said number 1 and number 2 (HDL1 and HDL2) unique before just each of the, e.g., atomic layer deposition (ALD) can be formed using.

According to some in the embodiment, high dielectric (HDL1) said number 1 may be crystalline, amorphous or crystalline lower than said number 2 (HDL2) high dielectric having high dielectric (HDL1) said number 1 can be crystalline (crystallinity). This, said number 1 (BE) lower electrode formed on said high dielectric (HDL1) is crystalline, amorphous aluminum oxide layer formed on the high dielectric said number 2 (HDL2) because said number 1 (AOL1) can be. In this case, the high dielectric constant greater than said number 1 high dielectric (HDL1) said number 2 (HDL2) may have. For example, high dielectric (HDL1) said number 1 and said number 2 both high dielectric (HDL2) ZrO₂ Even if film, high dielectric (HDL1) said number 2 (HDL2) said number 1 can be greater than the second conductive layer of high dielectric constant.

Said number 1 and number 2 (HDL1, HDL2) aluminum oxide (AOL1) is unique before just 1308. ball number between said number 1. Said number 2 (AOL2) and said aluminum oxide layer is a silicon oxide film (SOL) high dielectric (HDL2) 1308. ball number on said number 2. According to some in the embodiment, as shown in fig. 7, said number 2 (AOL2) said number 2 (HDL2) and said aluminum oxide dielectric is a silicon oxide film (SOL) can be interposed between. According to another in the embodiment, as shown in fig. 8, said silicon oxide film is high dielectric (HDL2) and aluminum oxide (SOL) said number 2 (AOL2) can be interposed between said number 2.

Said number 1 and number 2 (AOL1 and AOL2) is Al aluminium oxynitride films₂ O₃ And include, said silicon oxide film is SiO (SOL)₂ Can be a. Said number 1 and number 2 (AOL1 and AOL2) aluminium oxynitride films, and said greater than the band gap of the silicon oxide film (SOL) said high dielectric (HDL) may have, the leakage current is generated from the dielectric layer (DL) can number billion. In some in the embodiment, said number 1 and number 2 of each of the aluminium oxynitride films (AOL1 and AOL2) thicknesses (AOL1_TH and AOL2_TH) said number 1 (HDL1) (HDL1_TH) high dielectric thickness of about 0. 005 From about 1.5 to about 0. 5 Bail be. For example, said number 1 and number 2 of each of the aluminium oxynitride films (AOL1 and AOL2) thicknesses (AOL1_TH and AOL2_TH) about 0. 3 Å to about 10 Å implementation being. In some in the embodiment, the thickness of said silicon oxide film has a thickness of said number 1 (SOL) (SOL_TH) (HDL1_TH) high dielectric (HDL1) about 0. 003 From about 1.5 to about 0. 5 Bail be. For example, the thickness of said silicon oxide film (SOL) (SOL_TH) about 0. 2 Å to about 10 Å implementation being. According to some in the embodiment, the thickness of said silicon oxide film is said number 1 and number 2 (SOL) (SOL_TH) (AOL_TH) thickness of aluminium oxynitride films (AOL1 and AOL2) may be less than disclosed. However, the present invention herein are limited endured. Silicon oxide films (SOL1 and SOL2) said number 1 and number 2, and said aluminum oxide (AOL) is, for example, atomic layer deposition (ALD) can be formed using, can be amorphous. According to some in the embodiment, also shown in 7 and 8 also alternatively, said number 1 (AOL1) aluminum oxide, aluminum oxide (AOL2) said number 2, and/or said silicon oxide film (SOL) underneath the film partially covering can be formed.

Also 4a and 4b through a browser as a also, according to of the present invention in the embodiment, a dry oxide layer including the aluminum oxide layer in a silicon-on dielectric layer by introducing capacitor reduces the leakage current, the increase in equivalent oxide thickness can be reduced.

9A to 9c are also form a capacitor lower electrode of the present invention in the embodiment according to semiconductor device also is in the form of cross-sectional drawing representing are disclosed.

Also 9a to 9c also reference the, substrate (100) on the first oxide layer (110) is 1308. ball number. Said interlayer insulation film (110) in, said interlayer insulating film (110) through said substrate (100) electrically connected to the contact plug (112) is 1308. ball number.

Said interlayer insulation film (110) on, said substrate (100) is electrically connected to the capacitors (CA) co number can be disclosed. Each of said capacitors (CA), said interlayer insulating film (110) is ball number on said contact plug (112) is coupled to one corresponding one lower electrode comprising (BE) can be. Said lower electrode (BE) is said contact plug (112) through said substrate (100) can be electrically connected.

Said each of the lower electrodes (BE), in one example, as shown in also 9a, pillar (pillar) form may have. As another alternative, each of the lower electrodes (BE) said, also as shown in 9b, lower magnet is may have a hollow cylindrical shape.

In this case, each of said capacitors (CA), said interlayer insulating film (110) to said lower electrode covering the upper electrode (TE) on ball number (BE), and said upper electrode and lower electrode (BE) (TE) interposed between said further comprises dielectric (DL) can be. The upper electrode (TE) each including said capacitor (CA) to said plurality of said lower electrode (BE) be a common overlapping the common electrode. Each of said lower electrode (BE), as shown in also 9b to have a hollow cylindrical form, said inner wall of each of said upper electrode (TE) (BE) covering the lower electrode thereof can. the top and sidewalls each said dielectric layer (DL) (BE) the resultant structure makes it possible to cover the lower electrode, said upper electrode (TE) and said interlayer insulation film (110) can be extending between.

Each of said lower electrode (BE), in another example, as shown in also 9c, said interlayer insulating film (110) which ball number on an upper insulating layer (114) in 1308. ball number. Each of the lower electrodes (BE) said lower magnet is have a hollow cylindrical shape, the lower electrode (BE) said sidewalls of said upper insulating film (114) can be placed against the disclosed. According to some in the embodiment, each said lower electrode (BE) said upper insulating film (114) extending over an extensions may have.

In this case, the upper electrode (TE) said said upper insulating film (114) can be applied to ball number on, said inner wall of each of the lower electrode (BE) covering disclosed. Said upper electrode and the lower electrode (BE) said dielectric layer (DL) between said ball 1308. (TE) number. Said dielectric layer (DL) lower electrode (BE) the resultant structure makes it possible to cover the top and each said wall, said upper insulating film and said upper electrode (TE) (114) can be extending between.

Said dielectric layer (DL) is also 2, 3 also, also 5, 6 also, 7 also, a dielectric layer (DL) 8 or also through a browser can be substantially equal.

Or more, of the present invention in the embodiment described with reference to the attached drawing but, in the present invention is provided to the present invention is technical idea or person with skill in the art without changing its essential features can be understand other specific embodiment can form are disclosed. In the embodiment described above the exemplary non-limiting which is understood to all sides must substrate.