Verfahren zur Herstellung eines Films für eine Halbleiteranordnung bei niedriger Temperatur

Insulator deposition using focused ion beam

A method for depositing an insulating layer comprises directing a focused beam of gallium ions onto a localised surface region of a substrate along with a gas dissociatable into silicon and oxygen and a second gas which is capable of reacting with the gallium ions of the beam. The reactive gas may be carbon tetrabromide or ammonium carbonate while the dissociatable compound is preferably di-t-butoxydiacetoxy-silane. This method is useful when repairing an integrated circuit and especially for depositing a layer of insulator on an exposed metal line to prevent shorting.

Semiconductor devices and methods of making them

... 946,229. Semi-conductor devices. RADIO CORPORATION OF AMERICA. April 1, 1960 [April 15, 1959], No. 11684/60. Heading H1K. A method of making a semi-conductor device comprises the steps of depositing a silicon oxide coating on the surface of a semi-conductor wafer by heating the wafer in the vapours of an organic siloxane compound at a temperature between the decomposition temperature of the compound and the melting point of the wafer, removing a predetermined portion of the oxide coating, and diffusing a significant impurity from vapour into the coating-free portion of the wafer. The coating is believed to be a mixture of silicon monoxide and silicon dioxide. In a preferred example, for making an NPN transistor, the surface zone of a wafer of N-type germanium is converted to P-type, as by being heated in a powder composed of 99.9% Ge- 0.1% In. The thickness of the wafer is halved by grinding and etching one face to remove the P-type layer therefrom. Fig. 1e shows a resulting N-type wafer ...

PROCEDURE FOR THE PRODUCTION OF FLUORINIERTER SILICONE OXIDE COATINGS USING PLASMA CVD

FABRICATION OF DEVICES WITH A SILICON OXIDE REGION

LIFT-OFF SHADOW MASK

Semiconductor structures including tight pitch contacts and methods to form same

Method for planarizing film of semiconductor device

Improvements with the methods of formation of layers

PROCEDE DE DEPOT EN PHASE VAPEUR PAR FLASH THERMIQUE D'UNE COUCHE ISOLANTE SUR UN SUBSTRAT EN MATERIAU III-V, APPLICATION A LA FABRICATION D'UNE STRUCTURE MIS

CE PROCEDE CONSISTE, DANS LA MEME ENCEINTE, A REALISER UN DECAPAGE D'UN SUBSTRAT III-V 2, A FORMER SUR CE SUBSTRAT AU MOINS UNE COUCHE DE PROTECTION 8, 10 DE LA SURFACE DU SUBSTRAT CONSTITUANT LA ZONE ACTIVE 6 DE LA STRUCTURE MIS, OU MEME A REALISER LA COUCHE ACTIVE PAR EPITAXIE, A DEPOSER UNE COUCHE D'ISOLANT 12 PAR CVD A HAUTE TEMPERATURE PRODUITE PAR IRRADIATION DE LA SURFACE DE L'ECHANTILLON 1 AVEC DES LAMPES A HALOGENE, ET EVENTUELLEMENT A FORMER SUR LA COUCHE ISOLANTE 12 UNE COUCHE CONDUCTRICE 14 A HAUTE TEMPERATURE PAR IRRADIATION AVEC LES LAMPES A HALOGENE, ACHEVANT AINSI LA STRUCTURE MIS.

MANUFACTORING PROCESS Of a SEMICONDUCTOR DEVICE INCLUDING/UNDERSTANDING a REFRACTORY METAL ELECTRODE ON a SEMI-INSULATING SUBSTRATE

Dans un procédé de fabrication d'un dispositif semi-conducteur, consistant à produire une électrode porte 3, 3a en métal réfractaire sur une région préétablie de la surface d'un substrat semi-isolant 1 et à produire ensuite une pellicule isolante sur toute la surface du dispositif, puis à mettre à nu l'électrode porte 3, 3a en décapant cette pellicule de façon à obtenir une pellicule isolante 5c, la pellicule isolante initiale et la pellicule 5c sont réalisées respectivement par déposition et décapage selon la technique CVD au plasma à absorption d'énergie par des électrons dans un champ électrique alternatif de fréquence égale à celle de résonance de cyclotron, ou " electron cyclotron resonance " ECR, en soumettant le substrat à une polarisation à haute fréquence. In a method of manufacturing a semiconductor device, consisting in producing a refractory metal door electrode 3, 3a on a predetermined region of the surface of a semi-insulating substrate 1 and then in producing an insulating film over the entire surface of the device, then to expose the electrode door 3, 3a by pickling this film so as to obtain an insulating film 5c, the initial insulating film and the film 5c are produced respectively by deposition and pickling according to the CVD plasma technique with energy absorption by electrons in an alternating electric field of frequency equal to that of cyclotron resonance, or "electron cyclotron resonance" ECR, by subjecting the substrate to a high frequency polarization.

Doped dielectric film deposition at low temp and press - using plasma discharge to initiate reaction of organometallic cpd in inert gas, silane and nitrogen dioxide

Forming different zones in semiconductor simultaneously - by applying onto semiconductor a common insulating layer with doping substances having different diffusion rates and heating the assembly

METHOD OF DEPOSITING A STABLE FLUORINATED TEOS FILM

METHOD FOR FORMING A SILICON OXIDE FILM FROM AN ORGANIC AMINO SILANE PRECURSOR

PURPOSE: A method for depositing a silicon oxide film on a base is provided to obtain a silane precursor with long lifetime and safety. CONSTITUTION: A method for forming a silicon oxide film by a deposition process comprises: a step of providing a substrate to a deposition chamber; a step of introducing amino silane of chemical formulas A, B, or C or a mixture thereof to the deposition chamber; and a step of introducing oxidizer of oxygen, hydrogen peroxide, ozone, or nitrogen monoxide to the inside of the deposition chamber. The deposition process includes chemical vapor deposition, low pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, or atomic layer deposition. COPYRIGHT KIPO 2012 ...

METHOD FOR FORMING THIN FILM

A method for forming a thin film, characterized in that it comprises a surfactant film formation step of forming a film containing a surfactant on the surface of a substrate for forming the thin film, a vapor phase film growth step of contacting the resultant substrate with a gas containing a silica derivative, to form a thin film containing the silica derivative, and a step of firing the substrate having the thin film containing a silica derivative to decompose and remove the substrate. The method allows the production of a dielectric thin film which has a high porosity and also a high mechanical strength with good productivity. © KIPO & WIPO 2007 ...

METHOD OF MANUFACTURING NONVOLATILE MEMORY DEVICE USING ATOMIC LAYER DEPOSITIONS FOR ACQUIRING NANO-CRYSTAL WITH UNIFORM SIZE AND PROPER DENSITY

PURPOSE: A method of manufacturing a nonvolatile memory device is provided to acquire a nano-crystal structure with uniform size and proper density by performing repeatedly ALDs(Atomic Layer Depositions). CONSTITUTION: A tunnel insulating layer is formed on a semiconductor substrate(13). The substrate is loaded into an ALD apparatus(15). An aiming nano-crystal structure is formed on the tunnel insulating layer by using a plurality of ALDs(30). The substrate is unloaded from the ALD apparatus(32). A control gate insulating layer is formed on the resultant structure(35). A control gate electrode is formed on the control gate insulating layer(37). © KIPO 2006 ...

FILM FOR PREVENTING MOISTURE INFILTRATION ND METHOD FOR MANUFACTURING SAME

The present invention provides a film for preventing moisture infiltration and a method for manufacturing the same. The moisture infiltration preventing film includes: a Si-based inorganic insulation layer; a Si-based organic insulation layer; and a Si-based intermediate layer provided between the Si-based inorganic insulation layer and the Si-based organic insulation layer, wherein the Si-based intermediate layer has a lower content of carbon than the Si-based organic insulation layer. The present invention improves an effect of preventing moisture infiltration. COPYRIGHT KIPO 2017 ...

Semiconductor processing

Embodiments of the present disclosure include semiconductor processing methods and systems. One method includes forming a material layer on a semiconductor substrate by exposing a deposition surface of the substrate to at least a first and a second reactant sequentially introduced into a reaction chamber having an associated process temperature. The method includes removing residual first reactant from the chamber after introduction of the first reactant, removing residual second reactant from the chamber after introduction of the second reactant, and establishing a temperature differential substantially between an edge of the substrate and a center of the substrate via a purge process.

INORGANIC SUBSTRATE WITH A THIN SILICA TYPE GLASS LAYER, METHOD OF MANUFACTURING THE AFOREMENTIONED SUBSTRATE, COATING AGENT, AND A SEMICONDUCTOR DEVICE

A method of manufacturing an inorganic substrate coated with a thin silica type glass layer of 2H to 9H pencil hardness, said method comprising the steps of: coating an inorganic substrate with a cyclic dihydrogenpolysiloxane and/or a hydrogenpolysiloxane represented by a specific unit formula, and curing it; an inorganic substrate coated with a thin silica type glass layer; a coating agent for an inorganic substrate that is composed of a cyclic dihydrogenpolysiloxane and/or a hydrogenpolysiloxane represented by a specific unit formula; and a semiconductor device having an inorganic substrate coated with a thin silica type glass layer.

GATE INSULATING FILM COMPRISING SILICON AND OXYGEN

A gate insulating film 3 is formed of an insulative inorganic material containing silicon and oxygen as a main material. The gate insulating film 3 contains hydrogen atoms. A part of the absorbance of infrared radiation of which wave number is in the range of 830 to 900 cm-1 is less than both the absorbance of infrared radiation at the wave number of 830 cm-1 and the absorbance of infrared radiation at the wave number of 900 cm-1 when the insulating film to which an electric field has never been applied is measured by means of Fourier Transform Infrared Spectroscopy at room temperature. Further, in the case where the absolute value of the difference between the absorbance of infrared radiation at the wave number of 830 cm-1 and the absorbance of infrared radiation at the wave number of 770 cm-1 is defined as A and the absolute value of the difference between the absorbance of infrared radiation at the wave number of 900 cm-1and the absorbance of infrared radiation at the wave number of ...

SYSTEM AND METHOD FOR FORMING MULTI-COMPONENT DIELECTRIC FILMS

The present invention provides systems and methods for mixing precursors such that a mixture of precursors are present together in a chamber during a single pulse step in an atomic layer deposition (ALD) process to form a multi-component film. The precursors are comprised of at least one different chemical component, and such different components will form a mono-layer to produce a multi-component film. In a further aspect of the present invention, a dielectric film having a composition gradient is provided.

FABRICATION OF INTERCONNECT STRUCTURES

Interconnect structures are fabricated by methods that comprise depositing a thin conformal passivation dielectric and/or diffusion barrier cap and/or hard mask by an atomic layer deposition or supercritical fluid based process.

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device comprising a first insulating film formed on a semiconductor substrate, a charge storage layer formed on the first insulating film, a second insulating film formed on the charge storage layer, and a control electrode formed on the second insulating film, forming the second insulating film comprises forming a lower insulating film containing oxygen and a metal element, thermally treating the lower insulating film in an atmosphere containing oxidizing gas, and forming an upper insulating film on the thermally treated lower insulating film using film forming gas containing at least one of hydrogen and chlorine.

Methods of forming a thin layer including hafnium silicon oxide using atomic layer deposition and methods of forming a gate structure and a capacitor including the same

Methods of forming a thin film include applying a first reactant to a substrate, chemisorbing a first portion of the first reactant and physisorbing a second portion of the first reactant on the substrate, applying a first oxidizer to the substrate, chemically reacting the first oxidizer with the first portion of the first reactant to form a first solid material on the substrate, applying a second reactant to the first solid material, chemisorbing a first portion of the second reactant and physisorbing a second portion of the second reactant on the first solid material, applying a second oxidizer to the first solid material; and chemically reacting the second oxidizer with the first portion of the second reactant to form a second solid material on the first solid material.

Article comprising a semiconductor laser with stble facet coating

Disclosed are high reliability semiconductor lasers that need not be maintained inside a hermetic enclosure. Such lasers can advantageously be used in a variety of applications, e.g., in optical fiber telecommunications, and in compact disc players. Such "non-hermetic" lasers comprise facet coatings that comprise a dielectric layer that has very low water saturation value. In preferred embodiments this dielectric layer is SiOx(1 Подробнее

Method of forming silicon dioxide

A method of depositing a layer comprising SiO2 on a surface of a substrate at a rate which is temperature independent is disclosed. The method includes combining dichlorosilane (SiH2Cl2) with an oxidizing gas, such as O2, CO2, N2O, H2O, to form SiO2.

METHODS OF FORMING TITANIUM SILICON OXIDE

A dielectric containing a titanium silicon oxide film and a method of fabricating such a dielectric provide a dielectric for use in a variety of electronic devices. Embodiments may include a dielectric containing a titanium silicon oxide film arranged as one or more monolayers. Embodiments may include structures for capacitors, transistors, memory devices, and electronic systems with dielectrics containing a titanium silicon oxide film, and methods for forming such structures.

Method of producing insulator thin film, insulator thin film, method of manufacturing semiconductor device, and semiconductor device

A method of producing an insulator thin film, for forming a thin film on a substrate by use of the atomic layer deposition process, includes a first step of forming a silicon atomic layer on the substrate and forming an oxygen atomic layer on the silicon atomic layer, and a second step of forming a metal atomic layer on the substrate and forming an oxygen atomic layer on the metal atomic layer, wherein the concentration of the metal atoms in the insulator thin film is controlled by controlling the number of times the first step and the second step are carried out.

Verfahren zum Herstellen eines isolierenden Zwischenfilms

Producing isolator thin film on substrate involves atom deposition of silicon atom layer on substrate, oxygen atom layer on silicon atom layer and atom deposition of metal-atom layer on substrate, oxygen atom layer on metal-atom layer

The method involves a first step of producing a silicon atom layer on the substrate (100) and an oxygen atom layer on the silicon atom layer and a second step of producing a metal-atom layer on the substrate and an oxygen atom layer on the metal-atom layer, whereby all the layers are produced by an atom deposition process. The concentration of metal atoms in the thin film is controlled by controlling the number of implementations of the first and second steps. An independent claim is also included for a method of manufacturing a semiconductor component including a step for producing an isolator thin film.

Verfahren zur Herstellung dünner Schichten durch einen thermisch aktivierten Prozess unter Anwendung eines Temperaturgradienten über das Substrat hinweg

Ein thermisch aktivierter Stapelprozess dient zur Herstellung dünner Materialschichten in Halbleiterbauelementen, wobei das Erzeugen eines Überhitzungstemperaturprofils vor dem eigentlichen Bilden einer Materialschicht durch beispielsweise Abscheiden enthalten ist, so dass eine Gasverarmung im Zentrum des Substrats während des Abscheideprozesses kompensiert werden kann. Somit kann eine verbesserte Dickengleichmäßigkeit für dünne Materialschichten im Bereich von 1 bis 50 nm erreicht werden, ohne dass längere Prozesszeiten erforderlich sind, oder wobei sogar eine geringere Prozesszeit ermöglicht wird.

Methods of forming intermetallic insulating layers in semiconductor devices

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE WITH PASSIVATION FILM

... 1,237,662. Semi-conductor devices. HITACHI Ltd. 2 May, 1969 [7 May, 1968 (2)], No. 22634/69. Heading H1K. A method of forming a passivation film to protect the surface of a semi-conductor device comprises the steps of cleaning the surface of a silicon substrate 1 containing base 3 and emitter 4 regions by etching with hydrofluoric acid solution to remove the silicon oxide remaining after the diffusion process, etching with a mixture of nitric acid and hydrofluoric acid and washing in alcohol and pure water to clean the surface, drying, heating the device in a tetraethoxysilane atmosphere to form a pyrolytic silicon oxide film 5, heating in an atmosphere containing phosphorus oxychloride and oxygen to form a phosphorus oxide layer over the silicon oxide layer, these two layers combining and forming a glass mixture layer 7a and a surface layer 7b rich in phosphorus oxide, and forming a second pyrolytic layer 8 of silicon oxide by decomposition of tetraethoxysilane as before to isolate the ...

STABILIZERS, AROUND THE POLYMERIZATION OF SUBSTITUTING CYCLOTETRASILOXANE TO PREVENTING

STABILIZERS AS POLYMERIZATION INHIBITORS OF SUBSTITUTED CYCLOTETRASILOXANEN

PROCEDURE FOR MANUFACTURING A FROM AT LEAST ONE METAL OXIDE EXISTING INSULATING LAYER ON THE SURFACE OF A SEMICONDUCTOR CRYSTAL

MANUFACTURE PROCEDURE FOR A WHEN INTERCMETAL DIELECTRIC FUNCTIONING INSULATOR LAYER

METHOD OF FORMING DOPED DIELECTRIC LAYERS UTILIZING REACTIVE PLASMA DEPOSITION

METHOD OF ANNEALING A COMPOUND SEMICONDUCTOR SUBSTRATE

An annealing method for activating ion-implanted layers of a compound semiconductor substrate comprises converting gas containing prescribed components into plasma through an electron cyclotron resonance process and producing the same reaction with reactive gas to accumulate reaction products on the surface of the compound semiconductor substrate having the ion-implanted layers thereby to form a protective film and performing heat treatment for activating the ion-implanted layers. The gas N2, O2, NH3 or a gaseous mixture gas thereof.

METHOD FOR FORMING RECESSED ISOLATED REGIONS

INSULATOR DEPOSIT USING a BEAM Of IONS FOCUSES

INSULATOR DEPOSIT USING a BEAM Of IONS FOCUSES

Des procédés et des appareils sont proposés pour déposer un matériau isolant dans une zone prédéfinie d'un circuit intégré. Des molécules d'un composé contenant des atomes de silicium et des atomes d'oxygène sont mélangées à un gaz réactif et injectées dans la région de la surface du circuit intégré devant être traité, tandis qu'un faisceau d'ions focalisé est dirigé vers cette région. Le matériau qui en résulte et qui est déposé sélectivement dans des régions localisées de la surface du circuit intégré, présente une résistivité élevée. Le dépôt d'isolant est utile lors de la réparation d'un circuit intégré à semi-conducteur à l'aide d'un faisceau de particules chargées tel qu'un faisceau d'ions focalisé, ce qui permet d'effectuer certains types de réparations et de minimiser le temps de réparation. A titre d'exemple, un système à FIF est mis en oeuvre conformément à l'invention pour déposer une couche d'isolant au-dessus d'une ligne métallique exposée quelconque, afin de protéger la ligne ...

IMPROVEMENTS IN OR RELATING TO THE PRODUCTION OF AN INSULATING LAYER ON THE SURFACE OF A SEMICONDUCTOR CRYSTAL

Fabrication method of trench isolation of semiconductor device

갭 충전 특성이 우수하면서 결함이 발생하지 않는 반도체 소자의 트렌치 소자 분리 방법이 제공된다. 트렌치 소자 분리 방법은 트렌치가 형성된 기판을 고밀도 플라즈마(HDP) 화학기상증착 장치에 로딩하는 단계, 기판을 제1 히트 업하는 단계, 장치에 제1 바이어스 파워를 인가하여 트렌치의 내벽과 바닥에 HDP 산화막 라이너를 형성하는 단계, 제1 바이어스 파워를 오프하고 기판을 제2 히트 업하는 단계, 제1 바이어스 파워보다 큰 제2 바이어스 파워를 인가하여 트렌치 내부 갭을 충전하는 HDP 산화막을 형성하는 단계, 및 기판을 장치로부터 언로딩하는 단계를 포함한다. Provided are a trench element isolation method for a semiconductor element having excellent gap filling characteristics and no defects. The trench isolation method includes loading a trench-formed substrate into a high density plasma (HDP) chemical vapor deposition apparatus, first heating up the substrate, and applying a first bias power to the apparatus to apply an HDP oxide film to the inner wall and the bottom of the trench. Forming a liner, off first bias power and second heat up the substrate, applying a second bias power greater than the first bias power to form an HDP oxide film filling the trench internal gap, and the substrate Unloading from the device. 트렌치 소자 분리, 버블 결함, 라이너 분리 Trench element isolation, bubble defects, liner isolation

STABILIZERS TO INHIBIT THE POLYMERIZATION OF SUBSTITUTED CYCLOTETRASILOXANE

A METHOD OF FORMING SILICON CONTAINING THIN FILMS BY ATOMIC LAYER DEPOSITION UTILIZING TRISDIMETHYLAMINOSILANE

LIMITED THERMAL BUDGET FORMATION OF PMD LAYERS

기판 상에서 인접한 융기된 피처들에 의해 형성된 갭을 충진하는 방법은 상기 기판을 수용하는 챔버에 실리콘-함유 처리가스의 흐름을 제공하는 단계, 상기 챔버에 산화 처리가스의 흐름을 제공하는 단계, 및 상기 챔버에 인-함유 처리가스의 흐름을 제공하는 단계를 포함한다. 상기 방법은 상기 실리콘-함유 처리가스, 상기 인-함유 처리가스 및 상기 산화 처리가스 사이에 반응을 유발시킴으로써 상기 갭 내에 실질적으로 컨포멀한 층으로서 P-도핑 실리콘 산화물막의 제 1 부분을 증착하는 단계를 포함한다. 상기 컨포멀한 층을 증착하는 단계는 (실리콘-함유 처리가스 + 인-함유 처리가스):(산화 처리가스)의 비율을 시간에 따라 바꾸고 상기 컨포멀한 층의 증착 동안 내내 상기 기판의 온도를 약 500℃ 미만으로 유지시키는 것을 포함한다. 또한 상기 방법은 벌크층으로서 상기 P-도핑 실리콘 산화물막의 제 2 부분을 증착하는 단계를 포함한다. 상기 막의 제 2 부분을 증착하는 단계는 (실리콘-함유 처리가스 + 인-함유 처리가스):(산화 처리가스)의 비율을 상기 벌크층의 증착 동안 내내 실질적으로 일정하게 유지시키고 상기 벌크층의 증착 동안 내내 상기 기판의 온도를 약 500℃ 이하로 유지시키는 것을 포함한다. A method for filling a gap formed by adjacent raised features on a substrate includes providing a flow of silicon-containing process gas to a chamber containing the substrate, providing a flow of an oxidizing process gas to the chamber, and Providing a flow of phosphorus-containing process gas to the chamber. The method includes depositing a first portion of a P-doped silicon oxide film as a substantially conformal layer in the gap by causing a reaction between the silicon-containing process gas, the phosphorus-containing process gas, and the oxidation process gas. It includes. The step of depositing the conformal layer changes the ratio of (silicon-containing process gas + phosphorus-containing process gas) :( oxidation process gas) over time and changes the temperature of the substrate throughout the deposition of the conformal layer. Maintaining below about 500 ° C. The method also includes depositing a second portion of the P-doped silicon oxide film as a bulk layer. Deposition of the second portion of the film comprises maintaining a ratio of (silicon-containing process gas + phosphorus-containing process gas) :( oxidation process gas) substantially constant throughout the deposition of the bulk layer and depositing the bulk layer. Maintaining the temperature of the substrate below about 500 ° C. throughout.

METHOD OF FORMING GATE INSULATING FILM, STORAGE MEDIUM AND COMPUTER PROGRAM

ARRANGEMENT CVD METHOD, AN APPARATUS THEREOF, AND A COMPUTER READABLE RECORD MEDIUM FOR PROCESSING SEMICONDUCTOR FORMING A PRODUCTION LAYER ON AN OBJECT

PURPOSE: An arrangement CVD method, an apparatus thereof, and a computer readable record medium for processing semiconductor are provided to improve the property on layer quality, throughput, and raw material gas consumption. CONSTITUTION: An exhaust system(78) comprises a discharging valve for adjusting the amount of discharge. A controller(84) controls the operation of the apparatus. The controller is configured in advance to implement the arrangement CVD method. COPYRIGHT KIPO 2011 ...

METHOD OF FORMING A THIN FILM INCLUDING SILICON DIOXIDE USING DISILANE COMPOUND AS A SILICON SOURCE

PURPOSE: A method of forming a thin film including silicon dioxide is provided to obtain a high deposition rate and material uniformity when silicon dioxide is formed on a substrate. CONSTITUTION: An atomic layer deposition method(100) forms a thin film including silicon dioxide on a substrate. The substrate is brought into contact with vaporized silicon compound such that the silicon compound adheres onto the silicon(110). The silicon compound adhering onto the substrate is brought into contact with vaporized reactive oxygen source compound to convert the silicon compound into silicon dioxide(120). © KIPO 2009 ...

LIMITED THERMAL BUDGET FORMATION OF PMD LAYERS

A method of filling a gap which is defined by adjacent raised features on a substrate includes providing a flow of a silicon-containing processing gas to a chamber housing the substrate, providing a flow of an oxidizing processing gas to the chamber, and providing a flow of a phosphorous-containing processing gas to the chamber. The method also includes depositing a first portion of a P-doped silicon oxide film as a substantially conformal layer in the gap by causing a reaction between the silicon-containing processing gas, the phosphorous-containing processing gas, and the oxidizing processing gas. Depositing the conformal layer includes varying over time a ratio of the (silicon-containing processing gas plus phosphorous-containing processing gas):(oxidizing processing gas) and maintaining the temperature of the substrate below about 500°C throughout deposition of the conformal layer. The method also includes depositing a second portion of the P-doped silicon oxide film as a bulk layer ...

A SEMICONDUCTOR DEVICE, AN ELECTRONIC DEVICE AND AN ELECTRONIC APPARATUS

A gate insulating film 3 is formed of an insulative inorganic material containing silicon and oxygen as a main material. The gate insulating film 3 contains hydrogen atoms. A part of the absorbance of infrared radiation of which wave number is in the range of 830 to 900 cm-1 is less than both the absorbance of infrared radiation at the wave number of 830 cm-1 and the absorbance of infrared radiation at the wave number of 900 cm-1 when the insulating film to which an electric field has never been applied is measured by means of Fourier Transform Infrared Spectroscopy at room temperature. Further, in the case where the absolute value of the difference between the absorbance of infrared radiation at the wave number of 830 cm-1 and the absorbance of infrared radiation at the wave number of 770 cm-1 is defined as A and the absolute value of the difference between the absorbance of infrared radiation at the wave number of 900 cm-1 and the absorbance of infrared radiation at the wave number of ...

ORGANOMETALLIC COMPLEX AND DEPOSITION METHOD OF METAL SILICATE THIN FILM USING THE SAME

PURPOSE: An organometallic complex and a method for chemical depositing metal silicate thin film that is usable as a gate insulating film for semiconductor devices using the complex are provided. CONSTITUTION: The deposition method of metal silicate thin film comprises the process of contacting vapor of organometallic complex having structure of the following Formula 1 with a substrate: [formula 1]: (X)a-b-M-(Y-(Si(R)3)m)b, where M is a trivalent or quadrivalent metal; R is alkyl of C1 to C4; X is halogen; Y is 0 or N; a is 3, and b is an integer of 1 to 3 with the proviso that M is a trivalent metal while a is 4, and b is an integer of 1 to 4 with the proviso that M is a quadrivalent metal; and m is 1 with the proviso that Y is 0 while m is 2 with the proviso that Y is N, wherein the organometallic complex of the Formula 1 is Zr-(OSi(CH3)3)4, Zr-(N(Si(CH3)3)2)4, ZrCl2(OSi(CH3)3)2 or ZrCl2(N(Si(CH3)3)2)2, wherein the substrate is heated to a temperature of 200 to 700 deg.C. The organometallic ...

Gas chemistry cycling to achieve high aspect ratio gapfill with HDP-CVD

A method and apparatus are disclosed for depositing a dielectric film in a gap having an aspect ratio at least as large as 6:1. By cycling the gas chemistry of a high-density-plasma chemical-vapor-deposition system between deposition and etching conditions, the gap may be substantially 100% filled. Such filling is achieved by adjusting the flow rates of the precursor gases such that the deposition to sputtering ratio during the deposition phases is within certain predetermined limits.

Integrated circuit devices including a dual gate stack structure and methods of forming the same

Bilayer high dielectric constant gate insulator

An improved semiconducting polymer field effect transistor is provided having a higher density of carriers in the channel while maintaining high carrier mobility by applying a passivating thin layer of low dielectric constant insulator in contact with and between the layer of high dielectric constant gate insulator and semiconducting polymer.

Process for producing silicon oxide films from organoaminosilane precursors

A silicon oxide layer is deposited on a substrate by chemical vapor deposition (CVD) by reacting an organoaminosilane precursor, selected from specified categories, with an oxidizing agent under conditions for the formation of a silicon oxide film. Diisopropylaminosilane is the preferred organoaminosilane precursor for the formation of the silicon oxide film.

PROCESS FOR SMOOTHENING A SUBSTRATE SURFACE

METHOD OF PRODUCING FLATTENED INTEGRATED CIRCUIT STRUCTURE

Verfahren zur Herstellung einer Grabenisolation eines Halbleiterbauelements

Die Erfindung bezieht sich auf ein Verfahren zur Herstellung einer Grabenisolationsstruktur eines Halbleiterbauelements. DOLLAR A Erfindungsgemäß wird ein Substrat (100) mit einem darin ausgebildeten Graben in eine chemische Gasphasenabscheidungsvorrichtung mit einem Plasma hoher Dichte (HDP) geladen, das Substrat wird ein erstes Mal erwärmt, eine erste Vorspannungsleistung wird an die Vorrichtung angelegt, um so einen HDP-Oxidüberzug (140) auf Seitenwand- und Bodenflächen des Grabens zu bilden, wobei nach der Bildung des HDP-Oxidüberzugs ein Zwischenraum in dem Graben verbleibt, die erste Vorspannungsleistung wird abgeschaltet und das Substrat wird ein zweites Mal erwärmt, eine zweite Vorspannungsleistung mit einem Leistungsniveau, das höher als jenes der ersten Vorspannungsleistung ist, wird an das Substrat angelegt, um so zum Füllen des Zwischenraums in dem Graben einen HDP-Oxidfilm (150) zu bilden, und dann wird das Substrat aus der Vorrichtung entnommen. DOLLAR A Verwendung z.B. zur ...

METHOD OF ANNEALING A COMPOUND SEMICONDUCTOR SUBSTRATE

Laminated body and semiconductor device

Film deposition system

The invention relates to a film deposition system. A cycle of alternately supplying a first reactive gas and a second reactive gas and exhausting them is repeated twice or more in a vacuum vessel to cause reaction between the two gases, thereby depositing thin films on substrate surfaces, the film deposition system includes: a plurality of lower members having substrate-placing areas on which substrates will be placed; a plurality of upper members so placed that they face the lower members to form processing spaces together with the substrate-placing areas; a first reactive gas supply unit and a second reactive gas supply unit for supplying a first reactive gas and a second reactive gas, respectively, to the processing spaces; a purge gas supply unit for supplying a purge gas in the period between a first reactive gas supply period and a second reactive gas supply period; exhaust openings, situated along circumferences of the processing spaces, for communicating the inside of the processing ...

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE WITH PASSIVATION FILM

METHOD FOR PROCESSING A SUBSTRATE, CAPABLE OF MINIMIZING THE DAMAGE DUE TO PLASMA

PURPOSE: A method for processing a substrate is provided to prevent the generation of reflected wave and secure a superior coating quality on a corner of the substrate by mixing the plasma of time modulation mode and the plasma of continuous working mode. CONSTITUTION: A substrate is loaded in a chamber(S10). A first treatment for the substrate is performed at a fist plasma mode(S20). A second treatment for the substrate is performed at a second plasma mode(S30). A third treatment for the substrate is performed at a third plasma mode(S40). At least one of the first plasma mode and the second plasma mode is time modulation mode. COPYRIGHT KIPO 2010 ...

PROCESS FOR DEPOSITING INSULATING FILM ON SUBSTRATE AT LOW TEMPERATURE

본 발명은 플라스틱과 같이 내열성이 낮은 기판 상에 고품위의 절연막을 증착할 수 있도록 하는 저온 증착 방법에 관한 것으로서, 본 발명에 의한 방법은 a) 플라즈마에 의해 절연물질 전구체를 포함하는 반응기체를 기판 상에 증착하여 절연막을 형성하는 단계; 및 b) 반응기체 공급을 중단하고 플라즈마 처리만을 단독으로 실시하는 단계;를 포함하며, 절연막이 소정 두께에 도달할 때까지 상기 a) 및 b) 단계를 반복하는 것을 특징으로 한다. The present invention relates to a low temperature deposition method for depositing a high quality insulating film on a low heat resistance substrate such as plastic, and the method according to the present invention comprises a) a reaction medium comprising an insulating material precursor by plasma; Depositing to form an insulating film; And b) discontinuing supply of the reactor and performing only plasma treatment alone, wherein steps a) and b) are repeated until the insulating film reaches a predetermined thickness.

SEMICONDUCTOR DEVICE USING ENHANCED INSULATING LAYER STRUCTURE FOR IMPROVING FLATNESS AND MANUFACTURING METHOD THEREOF

PURPOSE: A semiconductor device and a manufacturing method thereof are provided to enhance the flatness of a semiconductor substrate by using improved insulating layer structure composed of first and second insulating layers. CONSTITUTION: A semiconductor device includes a substrate(100) with an insulating surface and a single crystal semiconductor layer(190) bonded to the insulating surface of the substrate. The semiconductor device further includes a first insulating layer and a second insulating layer. The first insulating layer is interposed between the insulating surface of the substrate and the single crystal semiconductor layer. The second insulating layer is formed on the substrate except for the first insulating layer region. © KIPO 2006 ...

GAS CHEMISTRY CYCLING TO ACHIEVE HIGH ASPECT RATIO GAPFILL WITH HDP-CVD

PURPOSE: A method and a device are provided to be capable of depositing a dielectric film in a gap having an aspect ratio at least as large as 6:1 by using HDP-CVD(High Density Plasma Chemical Vapor Deposition). CONSTITUTION: A gap is substantially 100% filled by cycling a gas chemistry of a high density plasma chemical vapor deposition system between deposition and etching conditions. Such filling is achieved by adjusting the flow rate of a precursor gas such that the deposition to sputtering ratio during a deposition phase is within certain predetermined limits. © KIPO 2002 ...

METHOD FOR FORMING AN INSULATING LAYER OF SEMICONDUCTOR DEVICES AND APPARATUS THEREOF

A forming method of an insulating layer of semiconductor devices is provided to simplify processes, perform at low temperature and improve an aspect ratio. The method comprises the steps of: forming a conductive pattern(53) on a lower insulating layer(52); performing a plasma treatment at the exposed surface of the conductive pattern(53) and the lower insulating layer(52) in order to be different the polarity of the surface each other; and depositing an insulating layer(54) having a different depositing rate according to the surface polarity on the resultant structure, thereby easily forming flattened insulating layer. Copyright 1999 KIPO ...

System and method for forming multi-component films

The present invention provides systems and methods for mixing vaporized precursors such that a mixture of vaporized precursors are present together in a chamber during a single pulse step in an atomic layer deposition (ALD) process to form a multi-component film. The vaporized precursors are comprised of at least one different chemical component, and such different components will form a mono-layer to produce a multi-component film. In a further aspect of the present invention, a dielectric film having a composition gradient is provided.

METHOD FOR MANUFACTURING SEMICONDUCTOR EPITAXIAL CRYSTAL SUBSTRATE

This invention provides a gallium nitride-type semiconductor epitaxial crystal substrate with a dielectric film, having a low gate leak current and very low and negligible gate lag, drain lag and current collapse characteristics. There is also provided a method for manufacturing a semiconductor epitaxial crystal substrate comprising a dielectric layer of a nitride dielectric material or an oxide dielectric material in an amorphous form as a passivation film or a gate insulating film applied onto the surface of a nitride semiconductor crystal layer grown by an organometal vapor phase epitaxial growth method. After the nitride semiconductor crystal layer is grown within an epitaxial growth furnace, the dielectric layer is also continuously grown on the nitride semiconductor crystal layer in the same epitaxial growth furnace.

FABRICATION OF DEVICES WITH A SILICON OXIDE REGION

Conformal layers of a silicon oxide, such as silicon dioxide, are deposited at temperatures below 600 degrees C through the decomposition of compounds such as diacetoxyditertiarybutoxysilane. The required temperatures do not significantly affect temperature-sensitive structures. Therefore, it is possible to form silicon oxide regions in the processing of devices having these structures.

METHOD OF FABRICATING DIELECTRIC LAYER

A method of fabricating a dielectric layer is described. A twelve-inch wafer having at least three metallic layers thereon is provided. A dielectric layer is formed over the twelve-inch wafer by performing a high-density plasma process. The high-density plasma process includes applying a total bias radio frequency (RF) power and a total source radio frequency (RF) power. Furthermore, the ratio between the total bias RF power and the total source RF power is about 0.7 to 2.5.

Method for forming thin film

It is an object to provide, with a high productivity, a dielectric thin film having a high degree of pore and a very great mechanical strength, and there are included a surfactant film forming step of forming a film including a surfactant on a surface of a substrate on which a thin film is to be formed, a vapor deposition step of causing the substrate to come in contact with a gas phase containing a silica derivative to form a thin film including the silica derivative, and a step of calcining the substrate having the thin film formed thereon and decomposing and removing the surfactant, the thin film being thus formed.

Method of fabricating semiconductor integrated circuit device

A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.

Method of forming interlayer insulating film

A material containing, as a main component, an organic silicon compound represented by the following general formula: R1xSi(OR2)4-x (where R1 is a phenyl group or a vinyl group; R2 is an alkyl group; and x is an integer of 1 to 3) is caused to undergo plasma polymerization or react with an oxidizing agent to form an interlayer insulating film composed of a silicon oxide film containing an organic component. As the organic silicon compound where R1 is a phenyl group, there can be listed phenyltrimethoxysilane or diphenyldimethoxysilane. As the organic silicon compound where R1 is a vinyl group, there can be listed vinyltrimethoxysilane or divinyldimethoxysilane.

Plasma CVD method

In a process of forming a silicon oxide film 116 that constitutes an interlayer insulating film with TEOS as a raw material through the plasma CVD method, the RF output is oscillated at 50 W, and the RF output is gradually increased from 50 W to 250 W (an output value at the time of forming a film) after discharging (after the generation of O2-plasma). A TEOS gas is supplied to start the film formation simultaneously when the RF output becomes 250 W, or while the timing is shifted. As a result, because the RF power supply is oscillated at a low output when starting discharging, a voltage between the RF electrodes can be prevented from changing transitionally and largely.

Apparatus and method for manufacturing a semiconductor circuit

A method and an apparatus for manufacturing, via a single fabrication line, circuits that are radiation tolerant and also circuits that are radiation intolerant. When production calls for radiation-tolerant circuits, low-pressure chemical vapor deposition is advantageously used to deposit an electrically-insulating material, such as silicon dioxide, in trenches to provide electrical isolation between adjacent semiconductor devices. When production requires radiation-intolerant circuits, as may be required for export, then the trenches are filled via a procedure that deposits an electrically-insulating material that, on exposure to ionizing radiation, generates a suitably large amount of "positive charge traps." One procedure suitable for creating such positive charge traps is high-density plasma chemical vapor deposition (HDPCVD).

Pattern forming method and manufacturing method of semiconductor device

A disclosed mask pattern forming method includes isotropically coating a surface of a resist pattern array having a predetermined line width with a silicon oxide film, embedding a gap in the resist pattern array coated by the silicon oxide film with a carbon film, removing the carbon film from the upper portion and etching back the carbon film while leaving the carbon film within the gap in any order, removing the remaining carbon film and etching back the upper portion of the resist pattern array to have a predetermined film thickness in any order, and forming a first mask pattern array which has a center portion having a predetermined width and film sidewall portions sandwiching the predetermined width, and arranged interposing a space width substantially the same as the predetermined line width with an asking process provided to the resist pattern array exposed from the removed silicon oxide film.

Gap processing

Among various methods, devices, and apparatuses, a number of methods are provided for forming a gap between circuitry. One such method includes depositing a first oxide precursor material on at least two conductive lines having at least one gap between the at least two conductive lines, and forming a breadloaf configuration with the first oxide precursor material on a top of each of the at least two conductive lines that leaves a space between a closest approach of at least two adjacent breadloaf configurations. The method also includes depositing a second oxide precursor material over the first oxide precursor material, where depositing the second oxide precursor material results in closing the space between the closest approach of the at least two adjacent breadloaf configurations.

FABRICATION OF DEVICES WITH A SILICON OXIDE REGION

Conformal layers of a silicon oxide, such as silicon dioxide, are deposited at temperatures below 600 degrees C through the decomposition of compounds such as diacetoxyditertiarybutoxysilane. The required temperatures do not significantly affect temperature-sensitive structures. Therefore, it is possible to form silicon oxide regions in the processing of devices having these structures.

Method of making an isolation layer serving as intermetal dielectric

Verfahren zur Herstellung eines Halbleiterbauelements

Ein Verfahren zur Herstellung eines Halbleiterbauelements in einem MLM-Prozess, um einen Druckstress einer Metallleitung oder einer HDP-Oxidschicht zu reduzieren und um einen Druckstress in einem nachfolgenden thermischen Behandlungsprozess einer Metallleitung zu reduzieren. Es ist somit möglich, eine Erzeugung eines Risses, verursacht durch Druckstress, zu reduzieren. Darüber hinaus kann eine Erzeugung eines Risses in einem Halbleiterbauelement reduziert werden, indem dagegen vorgebeugt wird, dass eine heterogene Grenzfläche eine Ursache eines Risses wird und indem die Grenzfläche einer instabilen TEOS-Oxidschicht stabilisiert wird.

Verfahren zum Bemustern einer Schicht aus einem Material

Die vorliegende Erfindung ermöglicht es, Probleme, die durch eine unvollständige Entfernung von Fotoresist bei einem fotolithografischen Verfahren entstehen und die durch eine Diffusion von Verunreinigungen aus einer Antireflexionsbeschichtung in eine Schicht aus Fotoresist entstehen, zu verringern. Eine Schutzschicht wird über der Antireflexionsbeschichtung ausgebildet und die Schicht aus Fotoresist wird über der Schutzschicht ausgebildet. Die Schutzschicht verhindert im Wesentlichen eine Diffusion von Verunreinigungen in den Fotoresist.

FABRICATION OF GROOVED SEMICONDUCTOR DEVICES

Method for forming thin film

本发明公开了一种薄膜形成方法，其制作工序包括：在基板表面形成含有表面活性剂的薄膜的表面活性剂膜形成工序、使基板和含有二氧化硅衍生物的气相接触从而形成含有二氧化硅衍生物的薄膜的气相生长工序、煅烧所述的薄膜形成的基板从而分解除去所述的表面活性剂的工序。本发明形成的电介质薄膜空孔度高，机械强度好，生产率高。

Forming glass films by reactive sputtering

Forming different zones in semiconductor simultaneously - by applying onto semiconductor a common insulating layer with doping substances having different diffusion rates and heating the assembly

Process of application of the silicon dioxide films on solid surfaces of supports

SEMICONDUCTOR DEVICE MANUFACTURING METHOD

METHOD OF FABRICATING SEMICONDUCTOR DEVICE

본 발명은 서로 에칭 특성이 다른 2종류 이상의 산화막의 형성을 수반하는 경우, 에칭 선택비의 악화를 회피할 수 있는 에칭 공정을 포함하는 반도체장치의 제조방법을 제공하는 것을 목적으로 한다. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device including an etching step that can avoid deterioration of the etching selectivity when the formation of two or more kinds of oxide films having different etching characteristics from each other. 게이트전극의 측면 상에 NSG막, TEOS막 등의 제 1 산화막과, BPSG막, PSG막 등의 제 2 산화막을 포함하는 적층막 측벽을 형성한다. 그 후, 적층막 측벽을 MIS 트랜지스터의 소스·드레인형성용 주입마스크로서 사용한 후, 제 2 산화막을 선택적으로 제거할 때, 불소산과 무기산(염산, 황산 등)을 포함하는 혼합수용액으로 습식에칭한다. 이로 인해, 각 산화막의 에칭 선택비를 크게 하여, 상층의 제 2 산화막만을 제거한다. On the side of the gate electrode, a sidewall of a laminated film including a first oxide film such as an NSG film and a TEOS film and a second oxide film such as a BPSG film and a PSG film is formed. Thereafter, the sidewalls of the laminated film are used as the source / drain injection mask of the MIS transistor, and then wet etching is performed with a mixed aqueous solution containing hydrofluoric acid and inorganic acid (hydrochloric acid, sulfuric acid, etc.) when the second oxide film is selectively removed. For this reason, the etching selectivity of each oxide film is made large and only the 2nd oxide film of an upper layer is removed. 게이트전극, 적층막 측벽 Gate electrode, sidewall of laminated film

THIN-FILM TRANSISTOR, METHOD OF PRODUCING THIN-FILM TRANSISTOR, ELECTRONIC CIRCUIT, DISPLAY, AND ELECTRONIC DEVICE

본 발명은 구동 전압이 낮고, 높은 트랜지스터 특성을 갖는 박막 트랜지스터, 이러한 박막 트랜지스터의 제조 방법, 신뢰성이 높은 전자 회로, 표시 장치 및 전자 기기를 제공하는 것이다. SUMMARY OF THE INVENTION The present invention provides a thin film transistor having a low driving voltage and high transistor characteristics, a method of manufacturing such a thin film transistor, an electronic circuit having high reliability, a display device, and an electronic device. 본 발명의 박막 트랜지스터(1)는 기판(2)상에 하지층(9)을 통하여 게이트 전극(3)이 설치되고, 또한 게이트 전극(3)을 덮도록 게이트 절연층(4)이 설치되어 있다. 이 게이트 절연층(4)상에는 소스 전극(5) 및 드레인 전극(6)이 게이트 전극(3)의 직상부를 피하도록 분리되어 설치되고, 이들 전극(5, 6)을 덮도록 유기 반도체층(7)이 설치되어 있다. 이 유기 반도체층(7)의 각 전극(5, 6)간의 영역이 캐리어가 이동하는 채널 영역(71)으로 되어 있다. 유기 반도체층(7)상에는 보호층(8)이 설치되어 있다. 이러한 박막 트랜지스터(1)에서는 유기 반도체층(7)은 게이트 절연층(4)보다 후에 형성되며, 또한 게이트 절연층(4)은 유기 반도체층(7)을 배향시키는 기능을 갖는 것을 특징으로 한다. In the thin film transistor 1 of the present invention, the gate electrode 3 is provided on the substrate 2 via the base layer 9, and the gate insulating layer 4 is provided to cover the gate electrode 3. . The source electrode 5 and the drain electrode 6 are separated and provided on the gate insulating layer 4 to avoid the upper portion of the gate electrode 3, and the organic semiconductor layer 7 so as to cover these electrodes 5, 6. ) Is installed. The area | region between each electrode 5 and 6 of this organic-semiconductor layer 7 becomes the channel area 71 which carrier moves. The protective layer 8 is provided on the organic semiconductor layer 7. In such a thin film transistor 1, the organic semiconductor layer 7 is formed after the gate insulating layer 4, and the gate insulating layer 4 is characterized by having a function of orienting the organic semiconductor layer 7. 박막 트랜지스터, 박막 트랜지스터의 제조 방법, 전자 회로, 표시 장치, 전자 기기 Thin film transistors, methods of manufacturing thin film transistors, electronic circuits, display devices, electronic devices

METHOD FOR CRITICAL DIMENSION SHRINK USING CONFORMAL PECVD FILMS

A method and apparatus for forming narrow vias in a substrate is provided. A pattern recess is etched into a substrate by conventional lithography. A thin conformal layer is formed over the surface of the substrate, including the sidewalls and bottom of the pattern recess. The thickness of the conformal layer reduces the effective width of the pattern recess. The conformal layer is removed from the bottom of the pattern recess by anisotropic etching to expose the substrate beneath. The substrate is then etched using the conformal layer covering the sidewalls of the pattern recess as a mask. The conformal layer is then removed using a wet etchant.

PREVENTION AND REDUCTION OF SOLVENT AND SOLUTION PENETRATION INTO POROUS DIELECTRICS USING A THIN BARRIER LAYER

A method and apparatus for treating a substrate is provided. A porous dielectric layer is formed on the substrate. In some embodiments, the dielectric may be capped by a dense dielectric layer. The dielectric layers are patterned, and a dense dielectric layer deposited conformally over the substrate. The dense conformal dielectric layer seals the pores of the porous dielectric layer against contact with species that may infiltrate the pores. The portion of the dense conformal pore-sealing dielectric layer covering the field region and bottom portions of the pattern openings is removed by directional selective etch.

Pattern forming method and manufacturing method of semiconductor device

A disclosed manufacturing method of a semiconductor device includes laminating a substrate, an etched film, an anti-reflective coating film, and a resist film; forming a pattern made of the resist film using a photolithographic technique; forming the third mask pattern array by a mask pattern forming method; and a seventh step of forming a fourth mask pattern array by processing the etched film using the third mask pattern array.

MASK PATTERN FORMING METHOD, FINE PATTERN FORMING METHOD, AND FILM DEPOSITION APPARATUS

In a mask pattern forming method, a resist film is formed over a thin film, the resist film is processed into resist patterns having a predetermined pitch by photolithography, slimming of the resist patterns is performed, and an oxide film is formed on the thin film and the resist patterns after an end of the slimming step in a film deposition apparatus by supplying a source gas and an oxygen radical or an oxygen-containing gas. In the mask pattern forming method, the slimming and the oxide film forming are continuously performed in the film deposition apparatus. 1. A mask pattern forming method comprising:loading a substrate including a pattern on a thin film into a process chamber, the pattern having lines and spaces therein;slimming the pattern using a first oxygen-containing gas plasma in the process chamber; andforming an oxide film on the slimmed pattern and the thin film in the process chamber by performing a cycle of adsorbing a source gas on the slimmed pattern and the thin film and oxidizing the source gas using a second oxygen-containing gas plasma,wherein the slimming of the pattern and the forming of the oxide film are performed in the same process chamber.2. The mask pattern forming method according to claim 1 , wherein the slimming of the pattern and the forming of the oxide film are consecutively performed.3. The mask pattern forming method according to claim 1 , wherein the pattern is a resist pattern.4. The mask pattern forming method according to claim 1 , wherein the oxide film comprises silicon oxide.5. The mask pattern forming method according to claim 1 , wherein the oxide film comprises metal oxide.6. The mask pattern forming method according to claim 1 , wherein the oxide film comprises silicon oxide and metal oxide.7. The mask pattern forming method according to claim 1 , wherein the slimming of the pattern and the forming of the oxide film are performed at temperatures below a heat-resisting temperature of the pattern.8. The mask pattern ...

Devices Formed With Dual Damascene Process

Structures and methods of forming metallization layers on a semiconductor component are disclosed. The method includes etching a metal line trench using a metal line mask, and etching a via trench using a via mask after etching the metal line trench. The via trench is etched only in regions common to both the metal line mask and the via mask.

Semiconductor structures including tight pitch contacts

Methods of fabricating semiconductor structures incorporating tight pitch contacts aligned with active area features and of simultaneously fabricating self-aligned tight pitch contacts and conductive lines using various techniques for defining patterns having sublithographic dimensions. Semiconductor structures having tight pitch contacts aligned with active area features and, optionally, aligned conductive lines are also disclosed, as are semiconductor structures with tight pitch contact holes and aligned trenches for conductive lines.

Methods of forming semiconductor structures including tight pitch contacts and lines

Methods of fabricating semiconductor structures incorporating tight pitch contacts aligned with active area features and of simultaneously fabricating self-aligned tight pitch contacts and conductive lines using various techniques for defining patterns having sublithographic dimensions. Semiconductor structures having tight pitch contacts aligned with active area features and, optionally, aligned conductive lines are also disclosed, as are semiconductor structures with tight pitch contact holes and aligned trenches for conductive lines.

Enhancing structural integrity of low-k dielectrics in metallization systems of semiconductor devices by using a crack suppressing material layer

During the formation of metallization layers of sophisticated semiconductor devices, the damaging of sensitive dielectric materials, such as ULK materials, may be significantly reduced during a CMP process by applying a compressive stress level. This may be accomplished, in some illustrative embodiments, by forming a compressively stressed cap layer on the ULK material, thereby suppressing the propagation of micro cracks into the ULK material.

Enhancing structural integrity of low-k dielectrics in metallization systems of semiconductor devices by using a crack suppressing material layer

During the formation of metallization layers of sophisticated semiconductor devices, the damaging of sensitive dielectric materials, such as ULK materials, may be significantly reduced during a CMP process by applying a compressive stress level. This may be accomplished, in some illustrative embodiments, by forming a compressively stressed cap layer on the ULK material, thereby suppressing the propagation of micro cracks into the ULK material.

Selective removal chemistries for semiconductor applications, methods of production and uses thereof

Removal chemistry solutions and methods of production thereof are described herein that include at least one fluorine-based constituent, at least one chelating component, surfactant component, oxidizing component or combination thereof, and at least one solvent or solvent mixture. Removal chemistry solutions and methods of production thereof are also described herein that include at least one low H 2 O content fluorine-based constituent and at least one solvent or solvent mixture.

通过使用三(二甲基氨基)硅烷的原子层沉积形成含硅薄膜的方法

本发明提供一种形成含硅固体薄膜层的原子层沉积方法。将基底置入腔体，此后，将含Si和氨基硅烷的第一反应物注入腔体。该第一反应物的第一部分化学吸附于基底上，第一反应物的第二部分物理吸附于基底上。一个优选方案中，通过吹洗和冲洗腔体，将第一反应物的物理吸附的第二部分从基体上清除。然后将第二反应物注入腔体，这里第二反应物的第一部分与第一反应物的化学吸附的第一部分化学反应，在基底上形成含硅固体。然后从腔体中清除第二反应物的未化学反应部分。一个优选方案中，在基底上形成的含硅固体为薄膜层，如氮化硅层。另一个优选方案中，第一反应物至少为选自Si[N(CH 3 ) 2 ] 4 ，SiH[N(CH 3 ) 2 ] 3 ，SiH 2 [N(CH 3 ) 2 ] 2 和SiH 3 [N(CH 3 ) 2 ]中的一种。第二反应物优选为活性NH 3 。腔体的压强优选维持在1.33-13300Pa(0.01-100乇)的范围内，且在优选实施方案中可在整个工艺中保持恒定，或可在四个步骤中的至少一个中改变。上述步骤中的一步或多步可重复进行，以在基底上获得较厚的固体。

Method of forming the multilayer wiring on the semiconductor device

본 발명은 다층 금속배선의 층간 절연막 형성 방법에 관한 것으로, 특히 모든 반도체 소자의 제조시 절연막의 스트레스로 인한 결함을 방지할 수 있는 다층 금속배선의 층간 절연막 형성 방법에 관한 것이다. 본 발명의 방법은 반도체기판 상부의 금속배선들 사이에 층간 절연막 형성시 오존의 농도 3.0∼5.0 mol wt%, 형성온도 390±30℃, 및 TEOS 농도 1.0∼2.0 slpm로 조절하여 상기 반도체기판 상부의 금속배선들 사이에 제 1 절연막을 매립하는 단계와 오존의 농도 3.0∼5.0 mol wt%, 형성 온도 410±30℃, 및 TEOS 농도 0.5 slpm 미만으로 조절하여 상기 제 1 절연막의 상부에 제 2 절연막을 형성하는 단계로 이루어짐을 특징으로 한다. 본 발명에 의하면 절연막의 스트레스 변화를 억제하게 되어 종래의 반도체 소자 제조시 그 소자의 신뢰성을 감소시키게 되는 결함을 최소화 할 수 있다. 또한, 본 발명의 절연막 형성시 동일한 반응로를 사용하여 제조하므로 금속배선들 사이의 절연막을 한번에 형성할 수 있게 되어 최종 절연막 내부의 보이드 형성을 억제할 수 있을 뿐만 아니라, 아에 따른 제조 수율을 향상시킬 수 있다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an interlayer insulating film of multi-layered metal wirings, and more particularly, to a method for forming an interlayer insulating film of multi-layered metal wirings capable of preventing defects due to stress of the insulating film in manufacturing all semiconductor devices. In the method of the present invention, when the interlayer insulating film is formed between the metal wires on the semiconductor substrate, the concentration of ozone is adjusted to 3.0 to 5.0 mol wt%, the forming temperature is 390 ± 30 ° C., and the TEOS concentration is 1.0 to 2.0 slpm. Embedding the first insulating film between the metal wires and adjusting the ozone concentration to 3.0 to 5.0 mol wt%, the forming temperature of 410 ± 30 ° C., and the TEOS concentration of less than 0.5 slpm to form a second insulating film on top of the first insulating film. Characterized in that it consists of the step of forming. According to the present invention, it is possible to minimize the defect that reduces the stress change of the insulating layer, thereby reducing the reliability of the conventional semiconductor device manufacturing. In addition, since the same reaction furnace is used to form the insulating film of the present invention, the insulating film between the metal wirings can be formed ...

Organometal complex and method of depositing a metal silicate thin layer using same

본 발명은 유기금속 착체 및 이를 이용한 금속 실리케이트 박막의 증착방법에 관한 것으로서, 하기 화학식 1의 유기금속 착체의 증기를 기판에 접촉시키는 본 발명의 방법에 의하면, 반도체 소자용 게이트 절연막으로 유용한, 목적하는 조성의 금속 실리케이트 박막을 간편하게 제조할 수 있다: The present invention relates to a method for depositing an organometallic complex and a metal silicate thin film using the same, and according to the method of the present invention in which vapor of an organometallic complex of Formula 1 is brought into contact with a substrate, it is useful as a gate insulating film for a semiconductor device. Metal silicate thin films of composition can be easily produced: (X) a-b -M-(Y-(Si(R) 3 ) m ) b (X) ab -M- (Y- (Si (R) 3 ) m ) b 상기 식에서, Where M은 3가 또는 4가 금속이고; M is a trivalent or tetravalent metal; R은 C 1-4 의 알킬이고; R is C 1-4 alkyl; X는 할로겐이고; X is halogen; Y는 O 또는 N이며; Y is O or N; M이 3가 금속인 경우 a는 3이고, b는 1 내지 3의 정수이고, M이 4가 금속인 경우 a는 4이고, b는 1 내지 4의 정수이고; A is 3 when M is a trivalent metal, b is an integer from 1 to 3, a is 4 when M is a tetravalent metal, b is an integer from 1 to 4; Y가 O인 경우 m은 1이고, Y가 N인 경우 m은 2이다. M is 1 when Y is O and m is 2 when Y is N.

Method for fabricating interlayer of dielectric in semiconductor device

본 발명의 반도체 소자의 층간절연막 형성방법은, 반도체 기판 위의 절연막 위에 배치되는 도전막 패턴들을 갖는 반도체 기판을 준비하는 단계와, 그리고 도전막 패턴들 및 절연막 위에 고밀도 플라즈마 산화막으로 층간절연막을 형성하되, 소스가스 외에 H₂를 첨가가스로서 공급하여 고밀도 플라즈마 산화막을 증착하는 단계를 포함한다. 층간절연막, 고밀도 플라즈마 산화막, 수소, 누설전류

Flat type capacitor for integrated circuit and method for manufacturing the same

캐패시터의 유전막의 열화를 방지하여, 캐패시터의 전기적 특성을 개선할 수 있는 평판형 캐패시터 및 그 제조방법을 개시한다. 개시된 본 발명의 평판형 캐패시터는, 반도체 기판의 소정 부분에 형성되는 하부 배선, 상기 하부 배선과 전기적으로 연결되며 하부 배선 상에 형성되는 하부 전극, 상기 하부 전극 상부에 양 모서리를 갖는 콘케이브 형태로 형성된 유전막, 상기 유전막 표면에 콘케이브 형태로 형성되는 상부 전극, 상기 하부 배선과 전기적으로 연결되는 제 1 상부 배선, 및 상기 상부 전극과 연결되는 제 2 상부 배선을 포함하며, 상기 콘케이브 형태의 상부 전극이 하부 전극 보다 크게 형성된다. Disclosed are a flat plate capacitor and a method of manufacturing the same, which can prevent deterioration of a dielectric film of a capacitor and can improve electrical characteristics of the capacitor. The disclosed flat plate capacitor has a lower wiring formed on a predetermined portion of a semiconductor substrate, a lower electrode electrically connected to the lower wiring and formed on the lower wiring, and in a concave form having both corners on the lower electrode. A dielectric film formed on the surface of the dielectric film, an upper electrode formed in a concave shape on the surface of the dielectric film, a first upper wire electrically connected to the lower wire, and a second upper wire connected to the upper electrode. The electrode is formed larger than the lower electrode.

Dielectric barrier layer films

본 발명에 따르면, 유전체 장벽층이 개시되어 있다. 본 발명에 따른 장벽층은 펄스화-DC, 기판 바이어스 물리적 기상 증착법에 의하여 기판상에 증착된 치밀한 비결정 유전층을 포함하고, 여기서 치밀한 비결정 유전층은 장벽층이다. 본 발명에 따른 장벽층을 형성하는 방법은 기판을 제공하는 단계 및 펄스화-DC, 바이어스화, 광타겟 물리적 기상 증착 단계에서 기판 상에 고도의 치밀한 비결정 유전재료를 증착하는 단계를 포함한다. 또 이 방법은 기판상에 연금속 브레스 처리를 수행하는 단계를 포함할 수 있다. 이러한 장벽층은 전기층, 광학층, 면역층 또는 마찰층과 같이 사용될 수 있다. In accordance with the present invention, a dielectric barrier layer is disclosed. The barrier layer according to the present invention comprises a dense amorphous dielectric layer deposited on a substrate by pulsed-DC, substrate bias physical vapor deposition, wherein the dense amorphous dielectric layer is a barrier layer. A method of forming a barrier layer in accordance with the present invention includes providing a substrate and depositing a highly dense amorphous dielectric material on the substrate in a pulsed-DC, biased, phototarget physical vapor deposition step. The method may also include performing a soft metal breath treatment on the substrate. Such barrier layers can be used such as electrical layers, optical layers, immune layers or friction layers. 유전체, 장벽층, 필름 Dielectric, Barrier Layer, Film

Method for forming PE-TEOS layer of semiconductor device

본 발명은 반도체 소자의 피이-테오스(PE-TEOS)막 형성 방법에 관한 것으로, 다수개의 웨이퍼를 챔버에 공급하여 균일한 두께로 PE-TEOS막을 형성하기 위해서, 본 발명은 챔버 내의 히터 테이블에 탑재된 다수개의 웨이퍼 각각에 대응되게 설치된 샤워 헤드를 통하여 공정 가스를 분사하여 PE-TEOS막을 형성하는 방법으로, (a) PE-TEOS막 증착 공정을 진행할 웨이퍼가 적재된 공급용 웨이퍼 카세트를 준비하는 단계와; (b) 실질적인 PE-TEOS 증착 공정을 진행하기 전에 상기 챔버 내부를 PE-TEOS 증착 공정을 진행할 조건과 동일한 분위기를 형성하는 단계와; (c) PE-TEOS 증착 공정을 진행할 조건과 동일한 분위기가 형성되면 상기 공급용 웨이퍼 카세트에서 웨이퍼들을 차례로 상기 챔버 내부의 상기 히터 테이블로 공급하여 설정된 클리닝 시작 시간이 될 때까지 PE-TEOS 증착 공정을 진행하는 단계와; (d) 상기 클리닝 시작 시간이 되면, 상기 공급용 웨이퍼 카세트에서 챔버로의 웨이퍼 공급을 중단하고 상기 챔버 내의 웨이퍼에 대한 PE-TEOS 증착 공정을 완료한 후 웨이퍼를 챔버 밖으로 반출한 다음 챔버 내부를 RF 클리닝하는 단계; 및 (e) 상기 RF 클리닝 과정에서 상승된 상기 샤워 헤드와 챔버 내부의 온도를 낮추기 위해서, RF 파워를 끈 상태에서 상기 샤워 헤드를 통하여 상기 챔버 내부로 TEOS 가스를 분사시켜 상기 샤워 헤드와 챔버 내부의 온도를 낮추는 단계;를 포함하는 것을 특징으로 하는 반도체 소자의 피이-테오스(PE-TEOS)막 형성 방법을 제공한다. 특히 (e) 단계는, 약 2Torr의 압력에서 RF 파워를 끈 상태에서, TEOS 가스를 2.1㎖/min의 속도로 약 250초 분사하는 단계이다. The present invention relates to a method of forming a PE-TEOS film of a semiconductor device, in order to form a PE-TEOS film with a uniform thickness by supplying a plurality of wafers to the chamber, the present invention is directed to a heater table in the chamber. A method of forming a PE-TEOS film by injecting a process gas through a shower head installed corresponding to each of a plurality of wafers mounted thereon, comprising: (a) preparing a wafer cassette for supplying wafers on which a PE-TEOS film deposition process is to be performed; Steps; (b) forming an atmosphere identical to the conditions under which the PE-TEOS deposition process is to be performed in the chamber before the actual PE-TEOS deposition process; (c) When the same atmosphere as the conditions for the PE-TEOS deposition process is formed, the wafers are sequentially supplied from the supply wafer cassette to the heater table in the chamber, and the PE-TEOS deposition process is performed until the set cleaning start time is reached. Proceeding; (d) When the cleaning start time is reached, the wafer supply from the supply wafer ...

Manufacturing method of insulator thin film

기판 및 전극 계면의 고정 전하를 저감하고, 또한 계면 준위의 증대없이 붕소의 관통을 억제함으로써, Vth 시프트 및 이동도 열화가 없는 양호한 MOSFET를 형성할 수 있는 절연체 박막을 제공하는 것을 가능하게 한다. 원자층 증착법을 이용하여 기판(100) 상에 박막을 형성하는 절연체 박막(102)의 제조 방법으로서, 상기 기판(100)의 처리 표면에 실리콘 원자층을 형성하고, 상기 실리콘 원자층 상에 산소 원자층을 형성하는 제1 공정과, 상기 기판(100)의 처리 표면에 금속 원자층을 형성하고, 상기 금속 원자층 상에 산소 원자층을 형성하는 제2 공정을 갖는 것을 특징으로 하며, 상기 제1 공정 및 상기 제2 공정의 실시 횟수를 제어함으로써 상기 절연체 박막(102) 내의 상기 금속 원자의 농도를 제어하는 절연체 박막의 제조 방법이다. 원자층 증착법, 실리콘 원자층, 산소 원자층, 농도, 어닐링, 불활성 가스

Semiconductor device manufacturing method and substrate processing apparatus

Method of manufacturing semiconductor device and substrate processing apparatus

저온 하(下)에서도, 높은 성막율을 유지하면서, 저비용으로 막 두께 균일성이 양호한 절연막을 형성한다. 기판을 처리 용기 내에 반입하는 공정; 각각 소정 원소를 포함하는 적어도 두 가지 유형(type)의 원료 가스들을 공급하여 상기 기판 상에 소정 원소 함유층을 형성하는 공정 및 상기 처리 용기 내에 상기 적어도 두 가지 유형의 원료 가스들과는 다른 반응 가스를 공급하여 상기 소정 원소 함유층을 개질하는 공정을 교호적으로 반복하여, 상기 기판 상에 막을 형성하는 처리를 수행하는 공정; 및 처리가 완료된 기판을 상기 처리 용기 내로부터 반출하는 공정을 포함하는 반도체 장치의 제조 방법이 제공된다. Even under a low temperature, an insulating film with good film thickness uniformity is formed at low cost while maintaining a high film formation rate. Bringing the substrate into the processing container; Supplying at least two types of source gases each containing a predetermined element to form a predetermined element-containing layer on the substrate, and supplying a reaction gas different from the at least two types of source gases in the processing vessel; Performing a process of alternately repeating the process of modifying the predetermined element-containing layer to form a film on the substrate; And a step of carrying out the processed substrate from the inside of the processing container.

Semiconductor device and producting method of the same

내용 없음. No content.

Method for forming thin film

本发明公开了一种薄膜形成方法，其制作工序包括：在基板表面形成含有表面活性剂的薄膜的表面活性剂膜形成工序、使基板和含有二氧化硅衍生物的气相接触从而形成含有二氧化硅衍生物的薄膜的气相生长工序、煅烧所述的薄膜形成的基板从而分解除去所述的表面活性剂的工序。本发明形成的电介质薄膜空孔度高，机械强度好，生产率高。

Method for manufacturing semiconductor device

Method of forming a film at low temperature for a semiconductor device

반도체 기판상에 250℃ 이하의 온도하에서 전리방사선 또는 광선을 조사하면서 적당한 기능성 가스를 도입하는 것에 의해 반도체 기판상에 P형 불순물층, 실리콘 단결정막, 실리콘 산화막, 실리콘막을 순차 형성한다. 250℃이하의 온도하에 있어서, 실리콘막상에 포토레지스트를 형성한 후, 포토레지스트를 마스크로서 에칭하여 실리콘 산화막으로 되는 게이트 전극 B 및 실리콘 선화막으로 되는 게이트 절연막을 형성하고, 그 후, 게이트 전극을 마스크로서 에칭하는 것에 의해 P형 불순물층으로 되는 채널영역을 형성한다. 반도체 기판상에 250℃ 이하의 온도하에 있어서 전리방사선 또는 광선을 조사하면서 적당한 기능성 가스를 도입하는 것에 의해 반도체 기판상에서의 게이트 전극의 측방에 소드·드레인 전극을 형성한다. A P-type impurity layer, a silicon single crystal film, a silicon oxide film, and a silicon film are sequentially formed on the semiconductor substrate by introducing an appropriate functional gas while irradiating ionizing radiation or light rays on the semiconductor substrate at a temperature of 250 ° C. or lower. After the photoresist is formed on the silicon film at a temperature of 250 ° C. or lower, the photoresist is etched as a mask to form a gate electrode B serving as a silicon oxide film and a gate insulating film serving as a silicon linear film, and then the gate electrode is formed. By etching as a mask, a channel region serving as a P-type impurity layer is formed. By introducing an appropriate functional gas while irradiating ionizing radiation or light rays on a semiconductor substrate at a temperature of 250 ° C. or lower, a sword and drain electrode are formed on the side of the gate electrode on the semiconductor substrate.

Batch cvd method and apparatus for semiconductor process, and computer readable storage medium

배치 CVD 방법은, 흡착 공정과 반응 공정을 잔류 가스를 제거하는 공정과 함께 갖는 사이클을 반복한다. 흡착 공정은, 원료 가스 밸브를 맨 처음의 제1 기간만 열림 상태로 한 후에 닫힘 상태로 함으로써 처리 용기 내로 원료 가스를 공급하는 것과, 반응 가스 밸브를 닫힘 상태로 유지하여 처리 용기 내로 반응 가스를 공급하지 않는 것과, 배기 밸브를 닫힘 상태로 유지하여 처리 용기 내를 배기하지 않는 것으로 행한다. 반응 공정은, 원료 가스 밸브를 닫힘 상태로 유지하여 처리 용기 내로 원료 가스를 공급하지 않는 것과, 반응 가스 밸브를 열림 상태로 하여 처리 용기 내로 반응 가스를 공급하는 것과, 배기 밸브를 소정의 열림 상태로부터 밸브 개도를 서서히 작게 함으로써 처리 용기 내를 배기하는 것으로 행한다. The batch CVD method repeats the cycle having the adsorption step and the reaction step together with the step of removing residual gas. The adsorption step is to supply the source gas into the processing vessel by closing the source gas valve only in the first first period and then to the closed state, and to supply the reaction gas into the processing vessel by keeping the reaction gas valve closed. And do not exhaust the inside of the processing container while the exhaust valve is kept closed. The reaction step is performed by maintaining the source gas valve in the closed state so as not to supply the source gas into the processing container, by supplying the reaction gas into the processing container with the reaction gas valve in the open state, and removing the exhaust valve from the predetermined open state. The inside of the processing vessel is evacuated by gradually decreasing the valve opening degree.

Cvd apparatus

내용 없음. No content.

Method of fabricating trench isolation of semiconductor device

本发明的制造半导体器件的沟槽隔离结构的方法中，在不产生缺陷情况下获得极好的间隙填充属性。在一方面，该方法包括：加载其中形成沟槽的衬底到高密度等离子体(HDP)化学气相沉积装置内；第一次加热衬底；施加第一偏置功率到装置以在沟槽的侧壁和底表面上形成HDP氧化衬里，在HDP氧化衬里形成后在沟槽内仍有一个间隙；去除第一偏置功率的施加并第二次加热衬底；施加比第一偏置功率大的功率水平的第二偏置功率到衬底以形成HDP氧化膜来填充沟槽内的间隙；从装置上卸载衬底。

Method for forming fine pattern of semiconductor device

The fine pattern forming method of the semiconductor device includes the only one photoresist etching mask process step. Therefore the manufacturing cost and processing stage can be simplified, and the production efficiency can be improved. The fine pattern forming method of the semiconductor device comprises as follows. The laminate pattern consisting of the first and third hard mask patterns(113-1, 115-2) is formed on the semiconductor substrate having the etched layer(111). The second hard mask pattern is side-etched by using the third hard mask pattern as the etch barrier. The third hard mask pattern is removed. The spin on carbon layer(123) is formed to expose the upper part of the second hard mask pattern. The etching process is performed to expose the etched layer by using the spin on carbon layer as the etch barrier. The spin on carbon layer is removed.

Limited thermal budget formation of PMD layers

A method of filling a gap which is defined by adjacent raised features on a substrate includes providing a flow of a silicon-containing processing gas to a chamber housing the substrate, providing a flow of an oxidizing processing gas to the chamber, and providing a flow of a phosphorous-containing processing gas to the chamber. The method also includes depositing a first portion of a P-doped silicon oxide film as a substantially conformal layer in the gap by causing a reaction between the silicon-containing processing gas, the phosphorous-containing processing gas, and the oxidizing processing gas. Depositing the conformal layer includes varying over time a ratio of the (silicon-containing processing gas plus phosphorous-containing processing gas):(oxidizing processing gas) and maintaining the temperature of the substrate below about 500 ° C. throughout deposition of the conformal layer. The method also includes depositing a second portion of the P-doped silicon oxide film as a bulk layer. Depositing a second portion of the film includes maintaining the ratio of the (silicon-containing processing gas plus phosphorous-containing processing gas):(oxidizing processing gas) substantially constant throughout deposition of the bulk layer and maintaining the temperature of the substrate below about 500 ° C. throughout deposition of the bulk layer.

Method of manufacturing semiconductor device and substrate processing apparatus

저온 하(下)에서도, 높은 성막율을 유지하면서, 저비용으로 막 두께 균일성이 양호한 절연막을 형성한다. 기판을 처리 용기 내에 반입하는 공정; 처리 용기 내에 소정 원소를 포함하는 제1 원료 가스와 소정 원소를 포함하는 제2 원료 가스를 공급하는 것으로 기판 상에 소정 원소 함유층을 형성하는 공정과, 처리 용기 내에 제1 원료 가스 및 제2 원료 가스와는 다른 반응 가스를 공급하는 것으로 소정 원소 함유층을 산화층, 질화층 또는 산질화층으로 개질하는 공정을 교호적으로 반복하는 것으로 기판 상에 소정 막 두께의 산화막, 질화막 또는 산질화막을 형성하는 처리를 수행하는 공정 및 처리가 완료된 기판을 처리 용기 내로부터 반출하는 공정을 포함하고, 제1 원료 가스는 제2 원료 가스보다도 반응성이 높고, 소정 원소 함유층을 형성하는 공정에서는 제1 원료 가스의 공급량을 제2 원료 가스의 공급량보다도 적게 한다. Even under a low temperature, an insulating film with good film thickness uniformity is formed at low cost while maintaining a high film formation rate. Bringing the substrate into the processing container; Supplying a first source gas containing a predetermined element and a second source gas containing a predetermined element into the processing container to form a predetermined element-containing layer on the substrate; and a first source gas and a second source gas in the processing container. The process of forming an oxide film, nitride film or oxynitride film having a predetermined thickness on the substrate by alternately repeating the process of reforming the predetermined element-containing layer into an oxide layer, a nitride layer or an oxynitride layer by supplying a reaction gas different from And a step of carrying out the substrate to be processed and the processed substrate from within the processing container, wherein the first source gas is more reactive than the second source gas, and in the step of forming the predetermined element-containing layer, the supply amount of the first source gas is reduced. 2 It is made smaller than the supply amount of source gas.

Semiconductor integrated circuit device

SiOF막을 포함하는 층간 절연막에 상감법으로 매립 배선을 형성하는 반도체 집적 회로 장치에 있어서, 매립 배선용 배선 홈을 형성할 때 이용하는 에칭 스토퍼층과 SiOF막과의 계면 박리를 방지한다. SiOF막(26, 29)을 포함하는 층간 절연막을 드라이 에칭하여 형성한 배선 홈(32)의 내부에 상감법으로 Cu 배선(33)을 매립할 때, 상기 드라이 에칭의 에칭 스토퍼층을 구성하는 질화실리콘막(28)과 SiOF막(26) 사이에 산질화실리콘막(27)을 개재시켜, SiOF막(26) 내에서 발생한 유리된 F를 산질화실리콘막(27)으로 트랩한다.

Methods and materials for depositing films on semiconductor substrates

A method of depositing a film on a substrate, comprising placing the substrate in the presence of plasma energy, and contacting the substrate with a reactive gas component comprising a compound of the formula (R—NH) 4−n SiX n , wherein R is an alkyl group, n is 1, 2, or 3, and X is selected from hydrogen or the halogens. The reactive gas composition may further comprise an oxidizer and/or a reducing agent.

Process for producing silicon oxide films from organoaminosilane precursors

The present invention is directed to a method for depositing a silicon oxide layer on a substrate by CVD. The reaction of an organoaminosilane precursor where the alkyl group has at least two carbon atoms in the presence of an oxidizing agent allows for the formation of a silicon oxide film. The organoaminosilanes are represented by the formulas: The use of diisopropylaminosilane is the preferred precursor for the formation of the silicon oxide film.

Method of manufacturing a semiconductor device capable of rapidly forming minute wirings without etching of the minute wirings

다층의 상호 접속 구조를 가진 반도체 장치의 제조 방법에 있어서, 플라즈마 성장을 사용하여 반도체 기판위의 전기 배선상에 실리콘 산화막을 형성할 때, 플라즈마를 생성하기 위해 일정 값의 제1의 고주파를 제공하고 한편으로 상기 반도체 기판상에 소정의 펄스 간격 및 소정의 레스트(rest) 간격을 가진 펄스화된 크기의 제2고주파를 공급한다. A method of manufacturing a semiconductor device having a multi-layer interconnect structure, comprising: providing a first high frequency of a constant value to generate a plasma when forming a silicon oxide film on electrical wiring on a semiconductor substrate using plasma growth; On the other hand, a second high frequency of pulsed magnitude having a predetermined pulse interval and a predetermined rest interval is supplied onto the semiconductor substrate.

A semiconductor device, an electronic device, and an electronic apparatus

게이트 절연막(3)은 주재료로서, 실리콘 및 산소를 포함하는 절연성 무기재료로 형성된다. 이 게이트 절연막(3)은 수소 원자들을 포함한다. 전계가 인가된 적이 없는 절연막(3)을, 실온에서 푸리에 변환 적외선 분광법에 의하여 측정할 때, 파수가 830 내지 900cm -1 의 범위에 있는 적외선 방사 흡광도 중 일부가 파수 830cm -1 에서의 적외선 방사의 흡광도 및 파수 900cm -1 에서의 적외선 방사의 흡광도 양자 모두보다도 작다. 또한, 파수 830cm -1 에서의 적외선 방사의 흡광도와 파수 770cm -1 에서의 적외선 방사의 흡광도 사이의 차의 절대값을 A로서 정의하고, 파수 900cm -1 에서의 적외선 방사의 흡광도와 파수 990cm -1 에서의 적외선 방사의 흡광도 사이의 차의 절대값을 B로서 정의하는 경우에, A 및 B는. A/B 가 1.8 이상이라는 관계를 만족한다. The gate insulating film 3 is formed of an insulating inorganic material containing silicon and oxygen as main materials. This gate insulating film 3 contains hydrogen atoms. When the insulating film 3 to which no electric field was applied is measured by Fourier transform infrared spectroscopy at room temperature, a part of the infrared radiation absorbances in the range of 830 to 900 cm -1 is determined by the infrared radiation at wave number 830 cm -1 . Absorbance and absorbance of infrared radiation at wave number 900 cm −1 are smaller than both. Further, the wave number of 830cm -1 in infrared radiation of wave number and absorbance of 770cm between the infrared radiation from -1 absorbance differences defined as an absolute value A, and the infrared radiation in the wave number-frequency 900cm -1 and 990cm -1 Absorbance When defining the absolute value of the difference between the absorbances of the infrared radiations in as B, A and B are: It satisfies the relationship that A / B is 1.8 or more. 게이트 절연막, 절연막, 반도체 디바이스 Gate insulating film, insulating film, semiconductor device

Organic transistor manufacturing method, active matrix device manufacturing method, display device manufacturing method, and electronic device manufacturing method

Insulating film forming method of semiconductor device and apparatus therefor

A forming method of an insulating layer of semiconductor devices is provided to simplify processes, perform at low temperature and improve an aspect ratio. The method comprises the steps of: forming a conductive pattern(53) on a lower insulating layer(52); performing a plasma treatment at the exposed surface of the conductive pattern(53) and the lower insulating layer(52) in order to be different the polarity of the surface each other; and depositing an insulating layer(54) having a different depositing rate according to the surface polarity on the resultant structure, thereby easily forming flattened insulating layer.

Method for fabricating intermetal dielectric structures including air-gaps between metal leads

A method of manufacturing a metallization scheme with an air gap formed by vaporizing a filler polymer material. The filler material is covered by a critical permeable dielectric layer. The method begins by forming spaced conductive lines over a semiconductor structure. The spaced conductive lines have top surfaces. A filler material is formed over the spaced conductive lines and the semiconductor structure. The filler material is preferably comprised of a material selected from the group consisting of polypropylene glycol (PPG), polybutadine (PB) polyethylene glycol(PEG), fluorinated amorphous carbon and polycaprolactone diol (PCL) and is formed by a spin on process or a CVD process. We etch back the filler material to expose the top surfaces of the spaced conductive lines. Next, the semiconductor structure is loaded into a HDPCVD chamber. In a critical step, a permeable dielectric layer is formed over the filler material. The permeable dielectric layer has a property of allowing decomposed gas phase filler material to diffuse through. In another critical step, we vaporize the filler material changing the filler material into a vapor phase filler material. The vapor phase filler material diffuses through the permeable dielectric layer to form a gap between the spaced conductive lines. An insulating layer is formed over the pexraeable dielectric layer.

Method of depositing electric insulating layer on iii-v group material substrate and manufacture of mis structure utilizing the method

(57)【要約】本公報は電子出願前の出願データであるた め要約のデータは記録されません。

Method of manufacturing semiconductor device, method of processing substrate, and substrate processing apparatus

고온 영역에 있어서, 막 중의 불순물 농도가 지극히 낮고, 막 두께 균일성이 양호한 절연막을 형성한다. 본 발명에 따르면, (a) 기판을 수용한 처리 용기 내에 소정 원소를 포함하는 원료 가스를 공급하고 배기하여 상기 기판 상에 소정 원소 함유층을 형성하는 공정; (b) 가열된 대기압 미만의 압력 분위기 하에 있는 상기 처리 용기 내에 산소 함유 가스와 수소 함유 가스를 공급하고 배기하여 상기 소정 원소 함유층을 산화층으로 변화시키는 공정; (c) 상기 처리 용기 내에 불활성 가스를 공급하고 배기하여 상기 처리 용기 내를 퍼지하는 공정; (d) 상기 공정 (a) 및 상기 공정 (b)를 교호적으로 반복하면서, 상기 공정 (c)가 상기 공정 (a) 및 상기 공정 (b) 사이에 수행되어, 상기 기판 상에 소정 막 두께의 산화막을 형성하는 공정을 포함하고, 상기 공정 (a)에서는, 상기 원료 가스를 상기 기판의 측방(側方)에 설치된 노즐을 개재하여 상기 기판을 향하여 공급하고, 그 때, 그 노즐을 개재하여 상기 원료 가스와 함께 불활성 가스 또는 수소 함유 가스를 상기 기판을 향하여 공급하는 것으로, 상기 기판의 표면과 평행 방향으로 흐르는 상기 원료 가스의 유속을, 상기 공정 (c)에 있어서 상기 기판의 표면과 평행 방향으로 흐르는 불활성 가스의 유속보다도 크게 한다.

METHOD FOR VAPOR PHASE DEPOSITION BY THERMAL FLASH OF AN INSULATING LAYER ON A SUBSTRATE OF III-V MATERIAL, APPLICATION TO THE MANUFACTURE OF A MIS STRUCTURE

Semiconductor integrated circuit and its manufacturing method

(57)【要約】 【課題】 半導体集積回路を形成する場合に高速化を行 う。 【解決手段】 多層配線構造の層間絶縁膜１０６を選択 的に形成を行うことにより、空孔１０５を含んだ層間膜 の構造にすることで静電容量を低減させる。

Semiconductor device and method of fabricating the same

A semiconductor device includes an interlevel film constituted by a first dielectrics film containing dangling bonds and a bonded group of Si and hydrogen, and a second dielectrics film formed on the first dielectrics film.

Staggered in-situ deposition and etching of a dielectric layer for HDP-CVD

A method and apparatus for depositing a conformal dielectric layer employing a dep-etch technique features selectively reducing the flow of deposition gases into a process chamber where a substrate having a stepped surface to be covered by the conformal dielectric layer is disposed. By selectively reducing the flow of deposition gases into the process chamber, the concentration of a sputtering gas, from which a plasma is formed, in the process chamber is increased without increasing the pressure therein. It is preferred that the flow of deposition gases be periodically terminated so as to provide a sputtering gas concentration approaching 100%. In this fashion, the etch rate of a conformal dielectric layer having adequate gap-filling characteristics may be greatly increased, while allowing an increase in the deposition rate of the same.

Apparatus for forming a dielectric layer

A deposition rate of a dielectric material is varied with the electrical polarity of an underlying layer to obtain excellent deposition and planarization characteristics. A conductive layer and the underlying dielectric are surface-treated to have different electrical polarities so that the dielectric is formed by using the difference of deposition rates of the dielectric material between that on the conductive layer and that on the underlying dielectric. A CVD apparatus having a DC power source connected between a susceptor and a gas injection portion thereof is provided. The deposition and planarization can be performed at low temperatures and are simplified in process.

Method for manufacturing semiconductor device

It is an object to provide a method for manufacturing a semiconductor device that has a semiconductor element including a film in which mixing impurities is suppressed. It is another object to provide a method for manufacturing a semiconductor device with high yield. In a method for manufacturing a semiconductor device in which an insulating film is formed in contact with a semiconductor layer provided over a substrate having an insulating surface with use of a plasma CVD apparatus, after an inner wall of a reaction chamber of the plasma CVD apparatus is coated with a film that does not include an impurity to the insulating film, a substrate is introduced in the reaction chamber, and the insulating film is deposited over the substrate. As a result, an insulating film in which the amount of impurities is reduced can be formed.

Process for the production of thin layers of high purity.

Method of manufacturing a semiconductor device

A method of manufacturing a semiconductor integrated circuit device is provided including forming a first insulating film comprised of fluorine-containing silicon oxide over a main surface of a semiconductor substrate is formed together with forming a second insulating film comprising silicon oxide as a major component, forming a third insulating film comprising silicon carbide as a major component, and forming a fourth insulating film comprised of fluorine-containing silicon oxide. The fourth insulating film is removed at a wiring groove-forming region thereof by dry etching using a first photoresist film as a mask. A first conductive layer is buried inside the wiring groove and the first conductive layer is removed from outside of the wiring groove by a chemical mechanical polishing method, thereby forming a first wiring including the first conductive layer inside the wiring groove.

Method of manufacturing an MIS-type semiconductor device

Disclosed is a method of manufacturing an MIS-type semiconductor device having a greatly reduced interface state density. In this method, before the formation of a gate insulating film, the surface of a GaAs substrate is treated with a plasma generated from a gas containing hydrogen and nitrogen or from a gas containing hydrogen and argon, so as to reduce the interface state density. An ECR plasma is used as the plasma, so that the damage caused by the plasma to the GaAs substrate is alleviated. After the surface treatment process, an healing process is performed, which sufficiently removes the damage. During the surface treatment process using the plasma generated from the gas containing hydrogen and nitrogen, a GaN gate insulating film is formed on the surface of the GaAs substrate. The surface treatment process using the plasma generated from the gas containing hydrogen and argon is followed by the process of forming a gate insulating film on the GaAs substrate; the two processes are successively performed within the same apparatus without exposing the GaAs substrate to ambient air.

Process for producing modified porous silica film, modified porous silica film obtained by the process, and semiconductor device employing the modified porous silica film

A hydrophobic compound having at least one each of hydrophobic group (an alkyl group having 1 to 6 carbon atoms or a -C 6 H 5 group) and polymerizable group (a hydrogen atom, a hydroxyl group or a halogen atom) is allowed to undergo a gas-phase polymerization reaction, under reduced pressure (of not more than 30 kPa), in the presence of a raw porous silica film and to thus form a modified porous silica film wherein a hydrophobic polymer thin film is formed on the inner walls of holes present in the raw porous silica film. The resulting porous silica film has a low relative dielectric constant and a low refractive index and the silica film is likewise improved in the mechanical strength and hydrophobicity. A semiconductor device is produced using the porous silica film.

Method for manufacturing semiconductor epitaxial crystal substrate

The present invention provides a method for manufacturing a gallium nitride semiconductor epitaxial crystal substrate with a dielectric film which has a low gate leak current and negligibly low gate lag, drain lag, and current collapse characteristics. The method for manufacturing a semiconductor epitaxial crystal substrate is a method for manufacturing a semiconductor epitaxial crystal substrate in which a dielectric layer of a nitride dielectric material or an oxide dielectric material in an amorphous form functioning as a passivation film or a gate insulator is provided on a surface of a nitride semiconductor crystal layer grown by metal organic chemical vapor deposition. In the method, after the nitride semiconductor crystal layer is grown in an epitaxial growth chamber, the dielectric layer is grown on the nitride semiconductor crystal layer in the epitaxial growth chamber.

Method for manufacturing semiconductor device with passivation film

A method for manufacturing a semiconductor device whose surface is passivated by a silicon oxide film, forming a pyrolytic silicon oxide film on the surface of a semiconductor substrate at a temperature no higher than 900* C., depositing phosphorus oxide from a vapor phase containing phosphorus at a temperature no higher than 900* C. on the surface of said silicon oxide film, and causing a reaction between the surface layer of silicon oxide and phosphorus oxide at a temperature no higher than 900* c., thereby forming in the surface of said deposited film a glass layer mixed with phosphorus oxide and silicon oxide.

Optical waveguide amplifier using high quantum efficiency silicon nanocrystal embedded silicon oxide

A method is provided for optical amplification using a silicon (Si) nanocrystal embedded silicon oxide (SiOx) waveguide. The method provides a Si nanocrystal embedded SiOx waveguide, where x is less than 2, having a quantum efficiency of greater than 10%. An optical input signal is supplied to the Si nanocrystal embedded SiOx waveguide, having a first power at a first wavelength in the range of 700 to 950 nm. The Si nanocrystal embedded SiOx waveguide is pumped with an optical source having a second power at a second wavelength in a range of 250 to 550 nm. As a result, an optical output signal having a third power is generated, greater than the first power, at the first wavelength. In one aspect, the third power increases in response to the length of the waveguide strip.

Fabrication of interconnect structures

Interconnect structures are fabricated by methods that comprise depositing a thin conformal passivation dielectric and/or diffusion barrier cap and/or hard mask by an atomic layer deposition or supercritical fluid based process.

Method for controlling defects in gate dielectrics

A method for improving high-κ gate dielectric film ( 104 ) properties. The high-κ film ( 104 ) is subjected to a two step anneal sequence. The first anneal is performed in a reducing ambient ( 106 ) with low partial pressure of oxidizer to promote film relaxation and increase by-product diffusion and desorption. The second anneal is performed in an oxidizing ambient ( 108 ) with a low partial pressure of reducer to remove defects and impurities.

Film forming apparatus

본 발명은 진공 용기 내에서, 제1 반응 가스와 제2 반응 가스를 교대로 공급하여 배기하는 사이클을 복수회 실행함으로써, 기판의 표면에 박막을 성막하는 성막 장치에 있어서, 상기 진공 용기 내에 설치되고, 각각 기판의 배치 영역을 포함하는 복수의 하부 부재와, 상기 복수의 하부 부재의 각각에 대향하여 설치되며, 상기 배치 영역과의 사이에 처리 공간을 형성하는 복수의 상부 부재와, 상기 처리 공간 내에 가스를 공급하기 위한, 제1 반응 가스 공급부, 제2 반응 가스 공급부, 및, 상기 제1 반응 가스를 공급하는 타이밍과, 상기 제2 반응 가스를 공급하는 타이밍 사이에 퍼지 가스를 공급하기 위한 퍼지 가스 공급부와, 상기 처리 공간의 둘레 방향을 따라 형성되고, 그 처리 공간 내와 그 처리 공간의 외부인 상기 진공 용기 내의 분위기를 연통하기 위한 배기용 개구부와, 상기 처리 공간을, 상기 배기용 개구부 및 상기 진공 용기 내의 분위기를 통해 진공 배기하기 위한 진공 배기 수단을 구비한 것을 특징으로 하는 성막 장치이다. The present invention provides a film forming apparatus for forming a thin film on the surface of a substrate by performing a plurality of cycles of alternately supplying and exhausting a first reaction gas and a second reaction gas in a vacuum vessel, wherein the film deposition apparatus is provided in the vacuum vessel. A plurality of lower members each including an arrangement area of the substrate, a plurality of upper members provided to face each of the plurality of lower members, and forming a processing space between the arrangement areas and the processing space; A purge gas for supplying a purge gas between a first reaction gas supply part, a second reaction gas supply part, and a timing for supplying the first reaction gas and a timing for supplying the second reaction gas for supplying the gas. For communicating with a supply portion and an atmosphere in the vacuum chamber which is formed along the circumferential direction of the processing space and is in the processing space and outside of the processing space; And the opening for the exhaust, a film forming apparatus for the treatment space, characterized in that it includes a vacuum exhaust means for evacuating through the atmosphere in the exhaust opening, and the vacuum container.

Selective removal chemistries for semiconductor applications, methods of production and uses thereof

Removal chemistry solutions and methods of production thereof are described herein that include at least one fluorine-based constituent, at least one chelating component, surfactant component, oxidizing component or combination thereof, and at least one solvent or solvent mixture. Removal chemistry solutions and methods of production thereof are also described herein that include at least one low H2O content fluorine-based constituent and at least one solvent or solvent mixture.

Method of forming silicon nanocrystal embedded silicon oxide electroluminescence device with a mid-bandgap transition layer

A method is provided for forming a silicon (Si) nanocrystal embedded Si oxide electroluminescence (EL) device with a mid-bandgap transition layer. The method provides a highly doped Si bottom electrode, and forms a mid-bandgap electrically insulating dielectric film overlying the electrode. A Si nanocrystal embedded SiOx film layer is formed overlying the mid-bandgap electrically insulating dielectric film, where X is less than 2, and a transparent top electrode overlies the Si nanocrystal embedded SiOx film layer. The bandgap of the mid-bandgap dielectric film is about half that of the bandgap of the Si nanocrystal embedded SiOx film. In one aspect, the Si nanocrystal embedded SiOx film has a bandgap (Eg) of about 10 electronvolts (eV) and mid-bandgap electrically insulating dielectric film has a bandgap of about 5 eV. By dividing the high-energy tunneling processes into two lower energy tunneling steps, potential damage due to high power hot electrons is reduced.

Method and apparatus for depositing and etching a dielectric layer

(57)【要約】 堆積−エッチング（ｄｅｐ−ｅｔｃｈ）技術の特徴を使用して、コンフォーマル誘電体を被覆しようとする段付き表面を有する基板が配置された処理チャンバ内への堆積ガスの流れを選択に減少させて、コンフォーマル誘電層を堆積するための方法および装置。処理チャンバ内への堆積ガスの流れを選択的に低下することによって、処理チャンバ内の圧力を増加することなく、プラズマが形成されるスパッタリングガスの処理チャンバ内の濃度を高める。スパッタリングガス濃度が１００％に近づくように、堆積ガスの流れを定期的に停止することが好ましい。この方法により、適切なギャップ充填特性を持つコンフォーマル誘電層の堆積速度を高めながら、同誘電層のエッチング速度を大幅に高めることができる。

Enhancing structural integrity of low-k dielectrics in metallization systems of semiconductor devices by using a crack suppressing material layer

Plasma CVD method

In a process of forming a silicon oxide film 116 that constitutes an interlayer insulating film with TEOS as a raw material through the plasma CVD method, the RF output is oscillated at 50 W, and the RF output is gradually increased from 50 W to 250 W (an output value at the time of forming a film) after discharging (after the generation of O 2 -plasma). A TEOS gas is supplied to start the film formation simultaneously when the RF output becomes 250 W, or while the timing is shifted. As a result, because the RF power supply is oscillated at a low output when starting discharging, a voltage between the RF electrodes can be prevented from changing transitionally and largely.

Methods of forming dual-damascene interconnect structures using adhesion layers having high internal compressive stress and structures formed thereby

배선 구조물을 형성하는 방법은 제1 유전막 상에 제1 금속 배선 패턴을 형성하고, 상기 제1 구리 배선 패턴 상에 캡핑막(예를 들어, SiCN막)을 형성하는 것을 포함한다. 약 500-700sccm 의 체적유량의 옥타메틸씨클로테트라실란을 포함하는 제1 소스 가스 및 약 1000-3000sccm 범위의 체적유량의 헬륨을 포함하는 제2 가스를 사용하여 캡핑막 상에 접착막을 증착한다. 증착 공정의 목적은 약 150MPa 이상의 내부 압축 스트레스를 가지는 접착막을 형성함으로써, 접착막에 의해 백-엔드 공정을 진행하는 동안의 식각/세정에서의 손상 및 습기 흡수를 줄일 수 있도록 하는 것이다. 접착막 상에는 부가적인 유전막 및 금속막이 증착된다. The method of forming the interconnection structure includes forming a first metal interconnection pattern on a first dielectric layer, and forming a capping layer (eg, a SiCN layer) on the first copper interconnection pattern. An adhesive film is deposited on the capping film using a first source gas comprising a volume flow rate of octamethylcyclotetrasilane of about 500-700 sccm and a second gas comprising volume flow helium in the range of about 1000-3000 sccm. The purpose of the deposition process is to form an adhesive film having an internal compressive stress of about 150 MPa or more, thereby reducing moisture absorption and damage in etching / cleaning during the back-end process by the adhesive film. An additional dielectric film and a metal film are deposited on the adhesive film. 듀얼 다마신 배선 구조물, 압축 스트레스 Dual damascene wiring structure, compressive stress

SEMICONDUCTOR ARRANGEMENT WITH TWO ELECTRODES SEPARATED BY AN INSULATION LAYER.

Lateral silicon di:oxide spacer prodn. in semiconductor structure

A process is disclosed for generating a spacer in a structure. During a first anisotropic dry etching step, a structure is generated, and in another step an oxide layer with an organic silicon precursor is deposited under a pressure p from 0.2 to 1 bar and at a temperature from 200 DEG C to 400 DEG C.

Process for producing silicon oxide films from organoaminosilane precursors

Ramp temperature techniques for improved mean wafer before clean

A method of operating a substrate processing chamber comprising transferring a first substrate into the substrate processing chamber and heating the substrate to a first temperature of at least 510° C.; depositing an insulating layer over the first substrate while reducing the temperature of the substrate from the first temperature to a second temperature that is lower than the first temperature; transferring the first substrate out of the substrate processing chamber; removing unwanted deposition material formed on interior surfaces of the chamber during the depositing step by introducing reactive halogen species into the chamber while increasing the temperature of chamber; transferring a second substrate into the substrate processing chamber and heating the substrate to the first temperature; and depositing an insulating layer over the second substrate while reducing the temperature of the substrate from the first temperature to the second temperature.

Twin tub CMOS process

A method of manufacturing a twin-tub structure for a CMOS (Complementary Metal Oxide Semicondcuctor) device is described. A first conductivity-imparting dopant is implanted in a silicon substrate. A photoresist layer is formed over a portion of the silicon substrate, to act as a mask. A portion of the top surface of the silicon substrate is removed in the region not masked by the photoresist layer. A second conductivity-imparting dopant, of an opposite type to the first conductivity-imparting dopant, is implanted into the region of the silicon substrate not masked by the photoresist layer. The photoresist layer is removed. A first insulating layer is formed over the silicon substrate. A second insulating layer is formed over the first insulating layer. The second insulating layer is patterned to form an active region mask centrally located over the planned location of each tub of the twin tub structure. Tubs are formed in the silicon substrate. Field oxide regions are formed in and on the surface of the silicon substrate, between the active region masks. The remainder of the second insulating layer is removed. A third conductivity-imparting dopant, of the same type as the second conductivity-imparting dopant, is implanted into the same region as the second conductivity-imparting dopant.

Method for forming thin film

Method of manufacturing semiconductor device, substrate processing apparatus and method of processing substrate

[課題]即使在低溫下，也維持高成膜速率且以低成本形成膜厚均勻性良好的絕緣膜。[解決手段]具有：將基板搬入處理容器內之製程；進行藉由交替地重複：利用將包含既定元素之第1原料氣體及包含既定元素之第2原料氣體供給排氣至處理容器內，而在基板上形成含既定元素層之製程、及利用將與第1原料氣體及第2原料氣體不同的反應氣體供給排氣至處理容器內而將含既定元素層改質成氧化層、氮化層或氮氧化層之製程，來在基板上形成既定膜厚的氧化膜、氮化膜或氮氧化膜的處理之製程；及將處理完畢的基板從處理容器內搬出之製程；第1原料氣體係反應性比第2原料氣體高，在形成含既定元素層之製程使第1原料氣體的供給量比第2原料氣體的供給量少。

Process for improving the adhesion between dielectric layers at their interface in semiconductor devices manufacture

Formation of silicon oxide using non-carbon flowable cvd processes

A method of forming a silicon oxide layer is described. The method may include the steps of mixing a carbon-free silicon-and-nitrogen containing precursor with a radical precursor, and depositing a silicon-and-nitrogen containing layer on a substrate. The silicon-and-nitrogen containing layer is then converted to the silicon oxide layer.

Surface treatment method

내용 없음

Method to fabricate high reliable metal capacitor within copper back-end process

A new method is provided for the creation of a high-reliability metal capacitor as part of back-end processing. A first layer of metal interconnect is created, a contact point is provided in the surface of the first layer of interconnect aligned with which a capacitor is to be created. A copper interconnect is formed overlying the contact point using TaN for the bottom plate, a high dielectric-constant dielectric material capacitor and using TaN for the top plate. The deposited layers are patterned and etched, a spacer layer is formed over sidewalls of the capacitor to prevent capacitor sidewall leakage. Top interconnect metal is then formed by first depositing a layer of etch stop material for further interconnection of the capacitor and the semiconductor devices provided in the underlying substrate.

Method of forming thin layers by a thermally activated process using a temperature gradient across the substrate

A thermally activated batch process is disclosed for forming thin material layers in semiconductor devices including the establishment of an overheating temperature profile prior to actually forming a material layer, for instance, by deposition, so that a gas depletion at the centre of the substrate during the deposition process be compensated for. Thus, enhanced thickness uniformity for thin material layers in the range of 1 to 50 nanometers may be obtained without additional process time or even at a reduced process time.

Process for producing modified porous silica film, modified porous silica film obtained by the process, and semiconductor device employing the modified porous silica film

本发明提供一种改性多孔质二氧化硅膜，其对多孔质二氧化硅膜，在减压(30kPa以下)下使具有至少各1个的疏水性基团(碳数1～6的烷基或C 6 H 5 基团)和可聚合性基团(氢原子、羟基或卤原子)的疏水性化合物进行气相聚合反应，使该膜中的空孔内壁生成疏水性聚合薄膜，由此得到该改性多孔质二氧化硅膜。该多孔质二氧化硅膜具有低介电常数及低折射率，且机械强度及疏水性得到改良。本发明还提供一种使用该多孔质二氧化硅膜的半导体装置。

Gas chemistry cycling to achieve high aspect ratio gapfill with HDP-CVD

A method and apparatus are disclosed for depositing a dielectric film in a gap having an aspect ratio at least as large as 6:1. By cycling the gas chemistry of a high-density-plasma chemical-vapor-deposition system between deposition and etching conditions, the gap may be substantially 100% filled. Such filling is achieved by adjusting the flow rates of the precursor gases such that the deposition to sputtering ratio during the deposition phases is within certain predetermined limits.

Mask pattern forming method, fine pattern forming method, and film forming apparatus

Method of forming single crystalline magnesia spinel film

The present invention relates to a method of forming a single crystalline magnesia spinel film on a single crystalline silicon substrate by the use of the vapor-phase epitaxial method. According to the method of the present invention, at first a first single crystalline magnesia spinel layer having a compositional ratio of magnesium maintained at a nearly stoichiometric compositional ratio is epitaxially grown in a vapor-phase on the single crystalline silicon substrate, and then a second single crystalline magnesia spinel layer having a compositional ratio of magnesium which decreases upward is epitaxially grown in a vapor-phase on the first single crystalline magnesia spinel layer. In the event that a Si film is grown on the single crystalline magnesia spinel film formed by the method of the present invention, out of atoms of Mg and Al taken in the Si film in the initial growth stage of the Si film, a concentration of Mg atoms which react more actively upon Si can be reduced. As a result, a reaction between Si and Mg can be suppressed to prevent the Si film from deteriorating its quality, whereby a SOI film having superior quality can be obtained.

Semiconductor device and manufacturing method thereof

Method for forming a high quality insulation layer on a semiconductor device

A method for forming a high quality insulation layer on a semiconductor device is presented. The method includes a first step of supplying any one of a silicon source gas and an oxygen source gas into a process chamber in which a semiconductor substrate is placed; a second step of simultaneously supplying the silicon source gas and the oxygen source gas into the process chamber having undergone the first step and depositing a silicon oxide layer on the semiconductor substrate; and a third step of supplying any one of the silicon source gas and the oxygen source gas into the process chamber having undergone the second step.

Silicon Nanocrystal Embedded Silicon Oxide Electroluminescence Device with a Mid-Bandgap Transition Layer

A method is provided for forming a silicon (Si) nanocrystal embedded Si oxide electroluminescence (EL) device with a mid-bandgap transition layer. The method provides a highly doped Si bottom electrode, and forms a mid-bandgap electrically insulating dielectric film overlying the electrode. A Si nanocrystal embedded SiOx film layer is formed overlying the mid-bandgap electrically insulating dielectric film, where X is less than 2, and a transparent top electrode overlies the Si nanocrystal embedded SiOx film layer. The bandgap of the mid-bandgap dielectric film is about half that of the bandgap of the Si nanocrystal embedded SiOx film. In one aspect, the Si nanocrystal embedded SiOx film has a bandgap (Eg) of about 10 electronvolts (eV) and mid-bandgap electrically insulating dielectric film has a bandgap of about 5 eV. By dividing the high-energy tunneling processes into two lower energy tunneling steps, potential damage due to high power hot electrons is reduced.

Prevention and reduction of solvent and solution penetration into porous dielectrics using a thin barrier layer

A method and apparatus for treating a substrate is provided. A porous dielectric layer is formed on the substrate. In some embodiments, the dielectric may be capped by a dense dielectric layer. The dielectric layers are patterned, and a dense dielectric layer deposited conformally over the substrate. The dense conformal dielectric layer seals the pores of the porous dielectric layer against contact with species that may infiltrate the pores. The portion of the dense conformal pore-sealing dielectric layer covering the field region and bottom portions of the pattern openings is removed by directional selective etch.

Prevention and reduction of solvent and solution penetration into porous dielectrics using a thin barrier layer

A method and apparatus for treating a substrate is provided. A porous dielectric layer is formed on the substrate. In some embodiments, the dielectric may be capped by a dense dielectric layer. The dielectric layers are patterned, and a dense dielectric layer deposited conformally over the substrate. The dense conformal dielectric layer seals the pores of the porous dielectric layer against contact with species that may infiltrate the pores. The portion of the dense conformal pore-sealing dielectric layer covering the field region and bottom portions of the pattern openings is removed by directional selective etch.

Semiconductor constructions comprising particle-containing materials

The invention includes methods of forming particle-containing materials, and also includes semiconductor constructions comprising particle-containing materials. One aspect of the invention includes a method in which a first monolayer is formed across at least a portion of a semiconductor substrate, particles are adhered to the first monolayer, and a second monolayer is formed over the particles. Another aspect of the invention includes a construction containing a semiconductor substrate and a particle-impregnated conductive material over at least a portion of the semiconductor substrate. The particle-impregnated conductive material can include tungsten-containing particles within a layer which includes tantalum or tungsten.

Process for producing silicon oxide films from organoaminosilane precursors

A silicon oxide layer is deposited on a substrate by chemical vapor deposition (CVD) by reacting an organoaminosilane precursor, selected from specified categories, with an oxidizing agent under conditions for the formation of a silicon oxide film. Diisopropylaminosilane is the preferred organoaminosilane precursor for the formation of the silicon oxide film.

Fabrication technique for high frequency, high power group III nitride electronic devices

Fabrication methods of a high frequency (sub-micron gate length) operation of AlInGaN/InGaN/GaN MOS-DHFET, and the HFET device resulting from the fabrication methods, are generally disclosed. The method of forming the HFET device generally includes a novel double-recess etching and a pulsed deposition of an ultra-thin, high-quality silicon dioxide layer as the active gate-insulator. The methods of the present invention can be utilized to form any suitable field effect transistor (FET), and are particular suited for forming high electron mobility transistors (HEMT).

Pulsed bias having high pulse frequency for filling gaps with dielectric material

During bottom filling of high aspect ratio gaps and trenches in an integrated circuit substrate using HDP-CVD, a pulsed HF bias is applied to the substrate. In some embodiments, pulsed HF bias is applied to the substrate during etching operations. The pulsed bias typically has a pulse frequency in a range of about from 500 Hz to 20 kHz and a duty cycle in a range of about from 0.1 to 0.95.

Dielectric barrier layer films

依照本发明，提出一种电介质阻挡层。依照本发明的阻挡层包含用脉冲-DC、衬底偏压的物理气相沉积法沉积在衬底上的致密化的无定形电介质层，其中致密化的无定形电介质层是阻挡层。依照本发明的形成阻挡层的方法包括提供衬底，并用脉冲-DC、偏压、宽靶物理气相沉积方法在衬底上沉积高度致密的、无定形的、电介质材料。而且，该方可以包括在衬底上进行软金属透气处理。这样的阻挡层可以用作电学层、光学层、免疫学层或摩擦层。

Enhanced thin-film oxidation process

A method is provided for additionally oxidizing a thin-film oxide. The method includes: providing a substrate; depositing an MyOx (M oxide) layer overlying the substrate, where M is a solid element having an oxidation state in a range of +2 to +5; treating the MyOx layer to a high density plasma (HDP) source; and, forming an MyOk layer in response to the HDP source, where k>x. In one aspect, the method further includes decreasing the concentration of oxide charge in response to forming the MyOk layer. In another aspect, the MyOx layer is deposited with an impurity N, and the method further includes creating volatile N oxides in response to forming the MyOk layer. For example, the impurity N may be carbon and the method creates a volatile carbon oxide.

Method for manufacturing semiconductor device

A method for producing a film for a semiconductor device at a low temperature

Buried flattening method by bias ECR-CVD method

Flat-type capacitor for integrated circuit and method of manufacturing the same

Embodiments of the invention provide flat-type capacitors that prevent degradation of the dielectric layer, thereby improving the electrical properties of the capacitor. The capacitor includes a lower interconnection formed in a predetermined portion of a semiconductor substrate, a lower electrode formed on the lower interconnection that is electrically coupled to the lower interconnection; a concave dielectric layer formed on the lower electrode; a concave upper electrode formed on the dielectric layer; a first upper interconnection that is electrically coupled to the lower interconnection; and a second upper interconnection that is coupled to the upper electrode. The concave upper electrode is larger than the lower electrode.