ELECTRONIC CIRCUIT DEVICE AND PORDUCTION METHOD THEREFOR

Method of manufacturing a semiconductor device

The present invention discloses a method for manufacturing semiconductor device, wherein, an internal connecting terminal 12 is formed on electrode pads 23 of a plurality of semiconductor chips 11 formed on a semiconductor substrate 35, and there is formed a resin member 13 having a resin member body 13-1 and a protruded portion 13-2 and covering the semiconductor chips 11 on which the internal connecting terminal 12 is formed, a metal layer 39 is formed on the resin member body 13-1 and the protruded portion 13-2 is used as an alignment mark to form a resist film 48 covering the metal layer 39 in a part corresponding to a region in which a wiring pattern 14 is formed and to then carry out etching over the metal layer 39 by using the resist layer 48 as a mask, thereby forming the wiring pattern 14 which is electrically connected to the internal connecting terminal 12.

마주보는（ＦＡＣＥ­ＴＯ­ＦＡＣＥ, Ｆ2Ｆ） 하이브리드 구조를 갖는 집적 회로(ＩＣ), ＩＣ 조립체, ＩＣ 제품 및 이들을 제조하는 방법, 그리고 이를 위한 컴퓨터-판독가능 매체

... 재분배 층(RDL)을 포함하는 집적 회로(IC) 제품이 제공되며, 재분배 층(RDL)은 IC 내에서 전기적 정보를 하나의 위치로부터 또 하나의 위치로 분배하도록 구성된 적어도 하나의 전도성 층을 갖는다. RDL은 또한 복수의 와이어 본드 패드들 및 복수의 솔더 패드들을 포함한다. 복수의 솔더 패드들 각각은 RDL과 직접적으로 전기적 통신을 하는 솔더 가용성 물질을 포함한다.

CHIP STRUCTURE HAVE REDISTRIBUTION LAYER

Uniplanar (single layer) passive circuitry

Under bump metallization structure and method for forming the same and redistribution metallization structure

Through via connected backside embedded circuit features structure and method

A method includes forming through vias in a substrate of an array. Nubs of the through vias are exposed from a backside surface of the substrate. A backside passivation layer is applied to enclose the nubs. Laser-ablated artifacts are formed in the backside passivation layer to expose the nubs. Circuit features are formed within the laser-ablated artifacts. By forming the circuit features within the laser-ablated artifacts in the backside passivation layer, the cost of fabricating the array is minimized. More particularly, the number of operations to form the embedded circuit features is minimized thus minimizing fabrication cost of the array.

Method for fabricating low resistance, low inductance interconnections in high current semiconductor devices

A method for fabricating a low resistance, low inductance device for high current semiconductor flip-chip products. A structure is produced, which comprises a semiconductor chip with metallization traces, copper lines in contact with the traces, and copper bumps located in an orderly and repetitive arrangement on each line so that the bumps of one line are positioned about midway between the corresponding bumps of the neighboring lines. A substrate is provided which has elongated copper leads with first and second surfaces, the leads oriented at right angles to the lines. The first surface of each lead is connected to the corresponding bumps of alternating lines using solder elements. Finally, the assembly is encapsulated in molding compound so that the second lead surfaces remain un-encapsulated.

Interconnect structure comprising fine pitch backside metal redistribution lines combined with vias

A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through-silicon vias (TSVs) and using a “plate through resist” type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and polish stop layer during the process flow.

Chip structure having redistribution layer

A chip structure including a chip and a redistribution layer is provided. The chip includes a plurality of pads. The redistribution layer includes a dielectric layer and a plurality of conductive traces. The dielectric layer is disposed on the chip and has a plurality of contact windows located above the pads. The conductive traces are located on the dielectric layer and are electrically coupled to the pads through the contact windows. At least one of the conductive traces includes a body and at least one protrusion coupled to the body, and the at least one protrusion is coupled to an area of the body other than where the contact windows are coupled to on the body.

Package structure and manufacturing method thereof

A package structure including a first chip, a second chip, a dielectric body, a third chip, an encapsulant, a first conductive terminal, and a circuit layer is provided. The dielectric body covers the first chip and the second chip. The third chip is disposed on the dielectric body such that a third active surface thereof faces a first active surface of the first chip or a second active surface of the second chip. The encapsulant covers the third chip. The first conductive terminal is disposed on the dielectric body and is opposite to the third chip. The circuit layer includes a first circuit portion and a second circuit portion. The first circuit portion penetrates the dielectric body. The first chip, the second chip, or the third chip is electrically connected to the first conductive terminal through the first circuit portion. The second circuit portion is embedded in the dielectric body.

Method for establishing and closing a trench of a semiconductor component

A method for establishing and closing at least one trench of a semiconductor component, in particular a micromechanical or electrical semiconductor component, having the following steps: applying at least one metal layer over the trench to be formed; forming a lattice having lattice openings in the at least one metal layer over the trench to be formed; forming the trench below the metal lattice, and closing the lattice openings over the trench.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

Object is to prevent a coupling failure between a rewiring and a coupling member for coupling to outside. A passivation film and a first polyimide film are formed so as to cover a wiring layer. A first opening portion is formed in the first polyimide film. A rewiring is formed on the first polyimide film so as to be coupled to the wiring layer via the first opening portion. A second polyimide film that covers the rewiring and has a second opening portion communicated with the rewiring is formed. A palladium film is formed as a barrier film by sputtering on a portion of the surface of the rewiring at which the second opening portion exists. A solder ball is coupled to the palladium film.

Semiconductor device and method comprising redistribution layers

A method of making a semiconductor package can include forming a plurality of redistribution layer (RDL) traces disposed over active surfaces of a plurality of semiconductor die and electrically connected to contact pads on the plurality of semiconductor die. The method can include disposing an encapsulant material over the active surfaces, contacting at least four side surfaces of each of the plurality of semiconductor die, and disposed over the plurality of RDL traces. The method can also include forming a via through the encapsulant material to expose at least one of the plurality of RDL traces, forming an electrical interconnect disposed within the via and coupled to the at least one RDL trace, and singulating the plurality of semiconductor packages through the encapsulant material to leave an offset of 30-140 μm of the encapsulant material disposed around a periphery of each of the plurality of semiconductor die.

Method of manufacturing semiconductor device and semiconductor device

Object is to prevent a coupling failure between a rewiring and a coupling member for coupling to outside. A passivation film and a first polyimide film are formed so as to cover a wiring layer. A first opening portion is formed in the first polyimide film. A rewiring is formed on the first polyimide film so as to be coupled to the wiring layer via the first opening portion. A second polyimide film that covers the rewiring and has a second opening portion communicated with the rewiring is formed. A palladium film is formed as a barrier film by sputtering on a portion of the surface of the rewiring at which the second opening portion exists. A solder ball is coupled to the palladium film.

Semiconductor chip and semiconductor device using the same, and method of fabricating semiconductor chip

A semiconductor chip in which a through hole penetrating through its surface and reverse surface is formed in a scribe line region in the vicinity of an active region where a functional device is formed, and a conductive member is arranged in the through portion. The through portion may be a groove opening sideward on a sidewall surface of the semiconductor chip. The through portion may be a through hole blocked from a side part of the semiconductor chip. The semiconductor chip may further include wiring for electrically connecting an internal circuit formed in the active region and the conductive member to each other.

Semiconductor Device with Shield for Electromagnetic Interference

A semiconductor device includes a first die embedded in a molding material, where contact pads of the first die are proximate a first side of the molding material. The semiconductor device further includes a redistribution structure over the first side of the molding material, a first metal coating along sidewalls of the first die and between the first die and the molding material, and a second metal coating along sidewalls of the molding material and on a second side of the molding material opposing the first side.

Semiconductor device and manufacturing method thereof

An electronic device and a method of making an electronic device. As non-limiting examples, various aspects of this disclosure provide various methods of making electronic devices, and electronic devices made thereby, that utilize a film assist mold process.

Semiconductor device and manufacturing method thereof

SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To provide a semiconductor device which is equipped with a capacitance element in the same semiconductor device to make the overall device compact, the capacitance element having larger electrostatic capacity than conventionally. SOLUTION: A semiconductor integrated circuit 1 and a pad electrode 4 are formed on the top surface of a semiconductor substrate 2. A second insulating film 10 is formed on a flank and a reverse surface of the semiconductor substrate 2, and a capacity electrode 9, which is in contact with the reverse surface of the semiconductor substrate 2, is formed between the reverse surface of the semiconductor substrate 2 and the second insulating film 10. The second insulating film 10 is covered with a wiring layer 11 electrically connected to the pad electrode 4, and the wiring layer 11 and capacity electrode 9 overlap each other, via the second insulating film 10 interposed. Accordingly, a capacitor 16 is formed of the capacity electrode 9, the second ...

Halbleiterchip und Herstellungsverfahren

Halbleiterchip mit - einem Halbleitersubstrat (32) mit einer Oberseite (35) und einer Unterseite (39) und wenigstens einer ersten Kontaktstelle (31), die auf der Oberseite benachbart zu einem Seitenrand des Halbleitersubstrats angeordnet ist, - einem Durchgangsloch (41), das durch einen seitlich am Halbleitersubstrat (32) vorgesehenen elektrischen Isolationsbereich hindurch an einer Stelle lateral zwischen der ersten Kontaktstelle und dem betreffenden Seitenrand eingebracht ist, und - einer Verbindungselektrode (43a, 43b), die elektrisch mit der ersten Kontaktstelle verbunden ist und sich einteilig von der ersten Kontaktstelle zu dem Durchgangsloch (41) und durch dieses hindurch zur Unterseite des Isolationsbereichs erstreckt, wobei der elektrische Isolationsbereich mit einer Unterseite koplanar zur Unterseite des Halbleitersubstrats abschließt.

Power management applications of interconnect substrates

Various applications of interconnect substrates in power management systems are described.

INTERCONNECT STRUCTURE COMPRISING FINE PITCH BACKSIDE METAL REDISTRIBUTION LINES COMBINED WITH VIAS

SYSTEM IN PACKAGE AND METHOD FOR FABRICATING THE SAME

반도체 장치 및 이의 제조 방법

... 본 발명은 반도체 장치 및 이의 제조 방법을 제공한다. 이 반도체 장치에서는, 재배선 패턴들 사이에 유기 절연 패턴이 개재된다. 상기 재배선 패턴이 열에 의해 팽창될 경우 발생되는 물리적 스트레스를 상기 유기 절연 패턴이 흡수할 수 있다. 이로써 유연성을 증대시킬 수 있다. 재배선 패턴들 사이에 유기절연 패턴이 개재되므로, 재배선 패턴들 사이에 반도체 패턴이 개재되는 경우에 비해, 절연성을 증대시킬 수 있다. 또한 재배선 패턴과 유기 절연 패턴 사이 그리고 반도체 기판과 유기 절연 패턴 사이에 시드막 패턴이 개재되므로, 재배선 패턴의 접착력이 향상되어 박리 문제를 개선할 수 있다. 또한 재배선 패턴을 구성하는 금속이 유기 절연 패턴으로 확산되는 것을 시드막 패턴이 방지할 수 있다. 이로써, 신뢰성이 향상된 반도체 장치를 구현할 수 있다.

SEMICONDUCTOR DEVICE FOR OBTAINING HIGH RELIABILITY OF ELECTRICAL CONNECTION BETWEEN AN ELECTRIC CONNECTION MEMBER AND A CONDUCTIVE PATTERN BY A CONDUCTIVE PASTE, AND A METHOD OF MANUFACTURING THE SAME

PURPOSE: A semiconductor device and a method of manufacturing the same are provided to increase a contact area for achieving electrical connection between an electrical member and a conductive pattern by filling each opening of the conductive pattern with conductive pastes, thereby obtaining preferable reliability of the electrical connection. CONSTITUTION: A method of manufacturing a semiconductor device(100) comprises the steps of: forming an electrical connection member(104) on an electrode pad(103) formed on a region corresponding to a semiconductor chip(101) on a substrate; forming an insulating layer(105) and a first conductive layer on the substrate; performing pattern etching of the first conductive pattern and exposing the electrical connection member for forming a conductive pattern(106); electrically connecting the conductive pattern to the electrical connection member by a conductive paste(107); and cutting the substrate into individual pieces. © KIPO 2008 ...

Semiconductor structure and manufacturing method thereof

A semiconductor structure includes a substrate, a conductive interconnection exposed from the substrate, a passivation covering the substrate and a portion of the conductive interconnection, an under bump metallurgy (UBM) pad disposed over the passivation and contacted with an exposed portion of the conductive interconnection, and a conductor disposed over the UBM pad, wherein the conductor includes a top surface, a first sloped outer surface extended from the top surface and including a first gradient, and a second sloped outer surface extended from an end of the first sloped outer surface to the UBM pad and including a second gradient substantially smaller than the first gradient.

Image sensor package and fabrication method thereof

An image sensor package includes an image sensor die having an active side and a backside, wherein an image sensor device region and a bond pad are provided on the active side. A through-silicon-via (TSV) structure extending through the thickness of the image sensor die is provided to electrically connect the bond pad. A multi-layer re-distributed interconnection structure is provided on the backside of the image sensor die. A solder mask or passivation layer covers the multi-layer re-distributed interconnection structure.

Ic device and method of manufacturing semiconductor structure

Semiconductor package and method for manufacturing the same

A semiconductor package comprises a chip, a plurality of pad extension traces, a plurality of via holes, a lid and a plurality of metal traces, wherein the chip has an active surface, a back surface opposite to the active surface, an optical component disposed on the active surface, and a plurality of pads disposed on the active surface and electrically connected to the optical component; the pad extension traces are electrically connected to the pads; the via holes are formed through the chip and electrically connected to the pad extension traces; the lid is attached on the active surface of the chip; and the plurality of metal traces are disposed on the back surface of the chip, electrically connected to the plurality of via holes, and defines a plurality of solder pads thereon.

Impedance controlled packages with metal sheet or 2-layer RDL

A microelectronic assembly is disclosed that is capable of achieving a desired impedance for raised conductive elements. The microelectronic assembly may include an interconnection element, a surface conductive element, a microelectronic device, a plurality of raised conductive elements, and a bond element. The microelectronic device may overlie the dielectric element and at least one surface conductive element attached to the front surface. The plurality of raised conductive elements may connect the device contacts with the element contacts. The raised conductive elements may have substantial portions spaced a first height above and extending at least generally parallel to at least one surface conductive element, such that a desired impedance may be achieved for the raised conductive elements. A bond element may electrically connect at least one surface conductive element with at least one reference contact that may be connectable to a source of reference potential.

Redistribution Layers And Methods Of Fabricating The Same In Semiconductor Devices

A semiconductor structure includes a first passivation layer disposed over a metal line, a copper-containing RDL disposed over the first passivation layer, where the copper-containing RDL is electrically coupled to the metal line and where a portion of the copper-containing RDL in contact with a top surface of the first passivation layer forms an acute angle, and a second passivation layer disposed over the copper-containing RDL, where an interface between the second passivation layer and a top surface of the copper-containing RDL is curved. The semiconductor structure may further include a polymeric layer disposed over the second passivation layer, where a portion of the polymeric layer extends to contact the copper-containing RDL, a bump electrically coupled to the copper-containing RDL, and a solder layer disposed over the bump. 1. A method , comprising:providing an interconnect structure disposed over a semiconductor substrate, wherein the interconnect structure includes a metal line;forming a first dielectric layer over the metal line;patterning the first dielectric layer to expose a portion of the metal line in a first opening;forming a pattern-forming layer over the first dielectric layer, thereby filling the first opening;forming a second opening in the pattern-forming layer;forming a footing profile to laterally extend the second opening;forming a redistribution layer (RDL) in the second opening, such that the RDL is electrically coupled to the metal line, wherein the RDL includes a curved top surface; andforming a second dielectric layer over the RDL.2. The method of claim 1 , further comprising:forming a seed layer on the first dielectric layer before forming the pattern-forming layer; andremoving portions of the seed layer not covered by the RDL before forming the second dielectric layer.3. The method of claim 1 , wherein forming the pattern-forming layer includes forming a photoresist layer on the first dielectric layer.4. The method of claim 3 , ...

Top layers of metal for high performance IC's

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Semiconductor package, semiconductor module, and method for fabricating the semiconductor package

Provided is a semiconductor package, a semiconductor module and a method for fabricating the semiconductor package. The method provides a substrate including a bonding pad. The method forms a dielectric layer for exposing the bonding pad on the substrate. The method forms a redistribution line which is electrically connected to the bonding pad, on the dielectric layer. The method forms an external terminal which is electrically connected to the bonding pad without using a solder mask which limits a position of the external terminal, on the redistribution line.

Semiconductor Device with Bond Pad Extensions Formed on Molded Appendage

A semiconductor device includes a semiconductor die having a main surface, a rear surface, outer edge sides extending between the main and rear surfaces, and a first conductive bond pad disposed on the main surface, an electrically insulating mold compound body formed around the outer edge sides of the semiconductor die with the main surface of the semiconductor die exposed from an upper surface of the mold compound body, a first metallization layer formed on the upper surface of the mold compound body and on the main surface of the semiconductor die, and a first bond pad extension formed in the first metallization layer. The first bond pad extension overlaps with the upper surface of the mold compound body. The first bond pad extension is conductively connected with the first conductive bond pad. The first bond pad extension is an externally accessible point of electrical contact of the device.

SEMICONDUCTOR DEVICE MANUFACTURING METHOD

A method of manufacturing a semiconductor device includes a first process in which a first wiring 3 is provided on a first surface 2a of a semiconductor substrate 2; a second process in which a light transmitting substrate 5 is attached to the first surface 2a; a third process in which the semiconductor substrate 2 is thinned so that the thickness of the semiconductor substrate 2 is smaller than the thickness of the light transmitting substrate 5; a fourth process in which a through hole 7 is formed in the semiconductor substrate 2; a fifth process in which a dip coating method is performed using a first resin material and thus a resin insulating layer 10 is provided; a sixth process in which a contact hole 16 is formed in the resin insulating layer 10; and a seventh process in which a second wiring 8 is provided on a surface 10b of the resin insulating layer 10, and the first wiring 3 and the second wiring 8 are electrically connected via a contact hole 16.

ELECTRO-OXIDATIVE METAL REMOVAL IN THROUGH MASK INTERCONNECT FABRICATION

In one implementation a cathode for electrochemical metal removal has a generally disc-shaped body and a plurality of channels in the generally disc-shaped body, where the channels are configured for passing electrolyte through the body of the cathode. The channels may be fitted with non-conductive (e.g., plastic) tubes that in some embodiments extend above the body of the cathode to a height of at least 1 cm. The cathode may also include a plurality of indentations at the edge to facilitate electrolyte flow at the edge of the cathode. In some embodiments the cathode includes a plurality of non-conductive fixation elements on a conductive surface of the cathode, where the fixation elements are attachable to one or more handles for removing the cathode from the electrochemical metal removal apparatus.

Top layers of metal for high performance IC's

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Semiconductor structure and fabrication method thereof

A method of forming a semiconductor structure includes the following steps. A dielectric layer is formed over a conductive line. A photoresist layer is formed over the dielectric layer. The photoresist layer is patterned to form a mask feature and an opening is defined by the mask feature. The opening has a bottom portion and a top portion communicated to the bottom portion, and the top portion is wider than the bottom portion. The dielectric layer is etched to form a via hole in the dielectric layer using the mask feature as an etch mask, such that the via hole has a bottom portion and a tapered portion over the bottom portion. The conductive material is filled in the via hole to form a conductive via.

SEMICONDUCTOR CHIP, METHOD FOR MANUFACTURING SEMICONDUCTOR CHIP, INTEGRATED CIRCUIT DEVICE, AND METHOD FOR MANUFACTURING INTERGRATED CIRCUIT DEVICE

An integrated circuit device includes a support substrate, a first semiconductor chip and a second semiconductor chip provided on the support substrate, and a connection member made of solder. The first semiconductor chip and the second semiconductor chip each includes a semiconductor substrate, an interconnect layer provided on the semiconductor substrate, and a pad provided on a side surface of the interconnect layer. The connection member contacts a side surface of the pad of the first semiconductor chip and a side surface of the pad of the second semiconductor chip.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF

In a method of manufacturing a semiconductor device, an opening is formed in a first dielectric layer so that a part of a lower conductive layer is exposed at a bottom of the opening, one or more liner conductive layers are formed over the part of the lower conductive layer, an inner sidewall of the opening and an upper surface of the first dielectric layer, a main conductive layer is formed over the one or more liner conductive layers, a patterned conductive layer is formed by patterning the main conductive layer and the one or more liner conductive layers, and a cover conductive layer is formed over the patterned conductive layer. The main conductive layer which is patterned is wrapped around by the cover conductive layer and one of the one or more liner conductive layers. 1. A method of manufacturing a semiconductor device , comprising:forming an opening in a first dielectric layer so that a part of a lower conductive layer is exposed at a bottom of the opening;forming one or more liner conductive layers over the part of the lower conductive layer, an inner sidewall of the opening and an upper surface of the first dielectric layer;forming a main conductive layer over the one or more liner conductive layers;forming a patterned conductive layer by patterning the main conductive layer and the one or more liner conductive layers; andforming a cover conductive layer over the patterned conductive layer,wherein the main conductive layer which is patterned is wrapped around by the cover conductive layer and one of the one or more liner conductive layers.2. The method of claim 1 , wherein the one of the one or more liner conductive layers and the cover layer are made of a same metal material.3. The method of claim 2 , wherein the same metal material is Co.4. The method of claim 1 , wherein the patterned conductive layer and the cover layer constitute a redistribution layer.5. The method of claim 1 , wherein the forming the one or more liner conductive layers comprises: ...

Double-sided marking of semiconductor wafers and method of using a double-sided marked semiconductor wafer

SEMICONDUCTOR PACKAGES WITH PILLAR AND BUMP STRUCTURES

Circuit device and method for manufacturing circuit device

Disclosed are a circuit device wherein a wiring layer, an insulating resin and a circuit element are arranged in layers in such a manner that a projection structure is embedded in the insulating resinand a method for manufacturing the circuit device. In this circuit device, connection reliability between the projection structure and an electrode of the circuit element is improved. Specifically disclosed is a circuit device (10) having a structure wherein a wiring layer (20), an insulating resin layer (30) and a circuit element (40) are arranged in this order and bonded together through pressure. The wiring layer (20) has projected electrodes (22) in positions corresponding to the element electrodes (42) of the circuit element (40). The insulating resin layer (30) is made of a material which causes plastic flow when a pressure is applied thereto. The projected electrodes (22) penetrate through the insulating resin layer (30) and are electrically connected with the corresponding elementelectrodes ...

Semiconductor device and manufacturing method

Circuit device and method for manufacturing the circuit device

In a circuit device where a wiring layer, an insulating resin and a circuit element are stacked together in such a manner as to embed a bump structure into the insulating resin, the connection reliability between the bump structure and the circuit element is enhanced. A circuit device (10) has a structure where a wiring layer (20), an insulating resin layer (30) and a circuit element (40) are stacked in this order by a pressure bonding. The wiring layer (20) is provided with bump electrodes (22) in positions that correspond respectively to element electrodes of a circuit element (40). The insulating resin layer (30) is formed of a material that develops plastic flow when pressurized. The bump electrode (22) penetrates the insulating resin layer (30) and is electrically connected to a corresponding element electrode (42).

ELECTRICAL CONNECTION DEVICE COMPRISING CONNECTING ELEMENTS HAVING DEFORMABLE MEMBRANES

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure includes a substrate, a conductive interconnection part exposed from the substrate, a passivation part covering the substrate and a portion of the conductive interconnection part, an under bump metallurgy (UBM) pad disposed on the upper side of the passivation part and touching an exposed portion of the conductive interconnection part, and a conductor disposed on the upper side of the UBM pad. The conductor includes a top surface, a first sloped outer surface extended from the top surface and including a first gradient, and a second sloped outer surface extended from an end of the first sloped outer surface to the UBM pad and including a second gradient substantially smaller than the first gradient. COPYRIGHT KIPO 2016 (AA) W_conductor (BB) W_lower end (CC) W_upper end (DD) W_protrusion (EE) H_protrusion (FF) H_conductor ...

CIRCUIT DEVICE AND METHOD FOR MANUFACTURING CIRCUIT DEVICE

Semiconductor package structure and manufacturing method thereof

A semiconductor package structure including a circuit substrate, at least two chips, an encapsulant, and a redistribution layer is provided. The circuit substrate has a first surface and a second surface opposite the first surface. At least two chips are disposed on the first surface, wherein each of the at least two chips has an active surface facing the circuit substrate and includes a plurality of first conductive connectors and a plurality of second conductive connectors disposed on the active surface. The pitch of the first conductive connectors is less than the pitch of the second conductive connectors. The encapsulant encapsulates at least two chips. The redistribution layer is located on the second surface. The first conductive connectors are electrically connected to the redistribution layer by the circuit substrate. The second conductive connectors are electrically connected to the circuit substrate. A manufacturing method of a semiconductor package structure is also provided.

Post-CMOS Processing and 3D Integration Based on Dry-Film Lithography

A method for performing a post processing pattern on a diced chip having a foot print, comprises the steps of providing a support wafer; applying a first dry film photoresist to the support wafer; positioning a mask corresponding to the footprint of the diced chip on the first dry film photoresist; expose the mask and the first dry film photoresist to UV radiation; remove the mask; photoresist develop the exposed first dry film photoresist to obtain a cavity corresponding to the diced chip; positioning the diced chip inside the cavity; applying a second dry film photoresist to the first film photoresist and the diced chip; and expose and develop the second dry film photoresist applied to the diced chip in accordance with the post processing pattern.

Etchant and method for manufacturing semiconductor device using same

Disclosed are an etchant which is used for redistribution of a semiconductor substrate having an electrode and which is capable of selectively etching copper without etching nickel; and a method for manufacturing a semiconductor device using the same. Specifically disclosed are an etchant which is used for redistribution of a semiconductor substrate and which contains hydrogen peroxide and citric acid and has a content of hydrogen peroxide of from 0.75 to 12% by mass and a content of citric acid of from 1 to 20% by mass, with a molar ratio of hydrogen peroxide and citric acid being in the range of from 0.3 to 5; an etchant for selective etching of copper which is used for redistribution of a semiconductor substrate and which contains hydrogen peroxide and malic acid and has a content of hydrogen peroxide of from 0.75 to 12% by mass and a content of malic acid of from 1.5 to 25% by mass, with a molar ratio of hydrogen peroxide and malic acid being in the range of from 0.2 to 6; and a method ...

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A metal layer is formed on an upper surface of a resin layer provided to cover a plurality of semiconductor chips at a side on which an internal connecting terminal is disposed and the internal connecting terminal, and the metal layer is pressed to cause the metal layer in a corresponding portion to a wiring pattern to come in contact with the internal connecting terminal, and to then bond the metal layer in a portion provided in contact with the internal connecting terminal to the internal connecting terminal in a portion provided in contact with the metal layer.

Post passivation interconnect

An integrated circuit (IC) device includes a first passivation layer over a substrate. The IC device further includes a redistribution line over the first passivation layer, wherein the redistribution line has a barrel-shaped profile. The IC device further includes a second passivation layer over the redistribution line. The IC device further includes a polymer layer over the second passivation layer.

Semiconductor chip, semiconductor package including the same, and method of fabricating the same

A semiconductor chip and/or a semiconductor package including the same are disclosed. The semiconductor chip may include an integrated circuit on a substrate, a center pad electrically connected to the integrated circuit, a lower insulating structure on the center pad and having a contact hole exposing the center pad, the lower insulating structure including a plurality of lower insulating layers sequentially stacked on the substrate, a conductive pattern including a contact portion, a pad portion, a conductive line portion, the contact portion filling the contact hole, the pad portion including a test region and a bonding region, a conductive line portion on the lower insulating structure and connecting the contact portion to the pad portion, and an upper insulating structure on the conductive pattern and having a first opening exposing the pad portion, and the upper insulating structure including an upper insulating layer and a polymer layer.

Laminated semiconductor substrate, laminated chip package and method of manufacturing the same

In a laminated semiconductor substrate, a plurality of semiconductor substrates are laminated. Each of the semiconductor substrate has a plurality of scribe-groove parts formed along scribe lines. Further, each of the semiconductor substrate has a plurality of device regions insulated from each other and has a semiconductor device formed therein, a first wiring electrode and a second wiring electrode extend to the inside of a interposed groove part from a first device region and a second device region respectively, and are separated from each other. In the laminated semiconductor substrate, a through hole which the first wiring electrode appears is formed. The laminated semiconductor substrate has a through electrode. The through electrode is contact with all of the first wiring electrodes appearing in the through hole. The laminated semiconductor substrate has a plurality of laminated chip regions.

ELECTRONIC COMPONENT MOUNTING STRUCTURE

An electronic component mounting structure includes: an electronic component including a plurality of bump electrodes that includes a base resin provided on an active face of the electronic component and a plurality of conductive films that cover a part of a surface of the base resin, expose an area excluding the part of the surface, and are electrically coupled to a plurality of electrode terminals provided on the active face; and a substrate including a plurality of terminals. In the structure, the electronic component is mounted on the substrate, and the base resin includes: a first opening surrounding the plurality of the electrode terminals; a connection portion in which a part of one ends of the plurality of the conductive films that are drawn out on the surface of the base resin is disposed, the other ends of the conductive films being coupled to the electrode terminals; and a bonding portion that is bonded to the substrate, and is formed in an area excluding the first opening and ...

Top layers of metal for high performance IC's

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Top layers of metal for high performance IC's

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Microelectronic assemblies having compliant layers

A compliant semiconductor chip package assembly includes a semiconductor chip having a plurality of chip contacts, and a compliant layer having a top surface, a bottom surface and sloping peripheral edges, whereby the bottom surface of the compliant layer overlies a surface of the semiconductor chip. The assembly also includes a plurality of electrically conductive traces connected to the chip contacts of the semiconductor chip, the traces extending along the sloping edges to the top surface of the compliant layer. The assembly may include conductive terminals overlying the semiconductor chip, with the compliant layer supporting the conductive terminals over the semiconductor chip. The conductive traces have first ends electrically connected with the contacts of the semiconductor chip and second ends electrically connected with the conductive terminals. The conductive terminals are movable relative to the semiconductor chip.

Semiconductor structure and method of forming the same

A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region.

Verfahren zum Sintern, Verfahren zur Schmelzschweissung, Höckerherstellung und Fühler.

Strukturen auf Chip-Rückseite einschließende System-On-Package-Architektur

Ausführungsformen schließen Elemente und Verfahren einschließlich eines Elements, das ein einen Halbleiter umfassendes Substrat einschließt, ein, wobei das Substrat eine aktive Elemente umfassende Vorderseite und eine der Vorderseite gegenüberliegende Rückseite einschließt. Das Element schließt eine dielektrische Schicht auf der Rückseite und eine passive Komponente auf der dielektrischen Schicht auf der Rückseite ein. Bei gewissen Ausführungsformen wird das passive Element auf einer selbstorganisierenden Monoschicht (SAM) gebildet. Weiter Ausführungsformen sind beschrieben und beansprucht.

Packaging structure and forming method thereof

Integrated circuit chip using top post-passivation technology and bottom structure technology

The chip module and manufacturing method thereof

Under bump metallization

INTEGRATED CIRCUIT CHIP USING TOP POST-PASSIVATION TECHNOLOGY AND BOTTOM STRUCTURE TECHNOLOGY

Chip package and fabrication method thereof

Electro-oxidative metal removal in through mask interconnect fabrication

In one implementation a wafer processing method includes filling a plurality of through-resist recessed features with a metal, such that a ratio of fill rate of a first feature to a fill rate of a second feature is R1; followed by electrochemically removing metal such that a ratio of metal removal rate from the first feature to the metal removal rate from the second feature is greater than R1, improving the uniformity of the fill. In some embodiments the method includes contacting an anodically biased substrate with an electrolyte such that the electrolyte has a transverse flow component in a direction that is substantially parallel to the working surface of the substrate. The method can be implemented in an apparatus that is configured for generating the transverse flow at the surface of the substrate. In some implementations the method makes use of distinct electrochemical regimes to achieve improvement in uniformity.

Top layers of metal for high performance IC's

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Top layers of metal for high performance IC's

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Top layers of metal for high performance IC's

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Top layers of metal for high performance IC's

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Method for fabricating low resistance, low inductance interconnections in high current semiconductor devices

A method for fabricating a low resistance, low inductance device for high current semiconductor flip-chip products. A structure is produced, which comprises a semiconductor chip with metallization traces, copper lines in contact with the traces, and copper bumps located in an orderly and repetitive arrangement on each line so that the bumps of one line are positioned about midway between the corresponding bumps of the neighboring lines. A substrate is provided which has elongated copper leads with first and second surfaces, the leads oriented at right angles to the lines. The first surface of each lead is connected to the corresponding bumps of alternating lines using solder elements. Finally, the assembly is encapsulated in molding compound so that the second lead surfaces remain un-encapsulated.

Method of forming through-holes in a wafer and then dicing to form stacked semiconductor devices

A semiconductor chip in which a through hole penetrating through its surface and reverse surface is formed in a scribe line region in the vicinity of an active region where a functional device is formed, and a conductive member is arranged in the through portion. The through portion may be a groove opening sideward on a sidewall surface of the semiconductor chip. The through portion may be a through hole blocked from a side part of the semiconductor chip. The semiconductor chip further includes wiring for electrically connecting an internal circuit formed in the active region and the conductive member to each other.

Top layers of metal for high performance IC's

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

SEMICONDUCTOR DEVICE

A semiconductor device, that is approximately identical in package size to a semiconductor chip, such as a W-CSP, is devised to secure a wider area for sealing such as laser marking. A semiconductor substrate has a plurality of via electrodes extending from the bottom of the semiconductor substrate to top electrodes, a bottom wire net formed at the bottom of the semiconductor substrate such that the bottom wire net is connected to the via electrodes, and an insulative film covering the bottom wire net. A sealing area having a sealing mark is disposed at the bottom of the semiconductor substrate. The sealing area is located such that the outer circumference of the sealing area is spaced apart from the bottom wire net in a direction parallel to a sealing mark forming surface, and the outer circumference of the sealing area is disposed at the edge of the semiconductor substrate.

Manufacturing method of ultra-thin semiconductor device package assembly

A manufacturing method of ultra-thin semiconductor device package structure is provided. Firstly, a wafer including a plurality of semiconductor devices is provided, and one of the semiconductor devices has an active surface having an active region and an outer region and a back surface. A first electrode and a second electrode are arranged in the active region, and the outer region has a cutting portion and a channel portion. Subsequently, a trench is formed in the channel portion, and filled with a conductive structure. The wafer is fixed on a supporting board, and then a thinning process and a deposition process of a back electrode layer are performed on the back surface in sequence. Thereafter, the supporting board is removed and a plurality of contacting pads is formed. A cutting process is performed along the cutting portion.

Top layers of metal for high performance IC's

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Semiconductor device

The semiconductor device includes a semiconductor chip 1, a first electrode pad 21 laminated on the semiconductor chip 1, an intermediate layer 4 having a rectangular shape defined by first edges 49a and second edges, and a plurality of bumps 5 arranged to sandwich the intermediate layer 4 by cooperating with the semiconductor chip 1. The first edges 49a extend in the direction x, whereas the second edges extend in the direction y. The plurality of bumps 5 include a first bump 51 electrically connected to the first electrode pad 21 and a second bump 52 electrically connected to the first electrode pad 21. The first bump 51 is arranged at one end in the direction x and one end in the direction y.

Electronic device, and manufacturing method of electronic device

An electronic device includes a drive substrate (a pressure chamber substrate and a vibration plate) including a piezoelectric element and electrode wirings related to driving of the piezoelectric element formed thereon, and a sealing plate bonded thereto, the electrode wirings are made of wiring metal containing gold (Au) on the drive substrate through an adhesion layer which is a base layer, and has a removed portion in which a portion of the wiring metal in a region containing a part bonded to a bonding resin is removed and the adhesion layer is exposed.

Top layers of metal for high performance IC's

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Electronic device and method of manufacturing the same

The present disclosure relates to a method of manufacturing an electronic device in which a plurality of first bumps (110) serving as external connection terminals are formed on a conductive pattern (106). The method includes: (a) forming a second bump (104) having a projection portion (104A) on an electrode pad (103) formed on a substrate (101); (b) forming an insulating layer (105) on the substrate (101); (c) exposing a portion of the projection portion (104A) from an upper surface of the insulating layer (105); (d) forming a flat stress absorbing layer (120) in a bump providing area (135), in which the first bumps (110) are provided, on the insulating layer; (e) forming a first conductive layer (107) on the insulating layer (105) and the stress absorbing layer (120) and the exposed portion of the projection portion (104A); (f) forming a second conductive layer (108) by an electroplating using the first conductive layer (107) as a power feeding layer; (g) forming the conductive pattern ...

IMAGING DEVICE, MANUFACTURING METHOD, AND ELECTRONIC DEVICE

SEMICONDUCTOR DEVICE MANUFACTURING METHOD

A method of manufacturing a semiconductor device includes a first process in which a first wiring 3 is provided on a first surface 2a of a semiconductor substrate 2; a second process in which a light transmitting substrate 5 is attached to the first surface 2a; a third process in which the semiconductor substrate 2 is thinned so that the thickness of the semiconductor substrate 2 is smaller than the thickness of the light transmitting substrate 5; a fourth process in which a through hole 7 is formed in the semiconductor substrate 2; a fifth process in which a dip coating method is performed using a first resin material and thus a resin insulating layer 10 is provided; a sixth process in which a contact hole 16 is formed in the resin insulating layer 10; and a seventh process in which a second wiring 8 is provided on a surface 10b of the resin insulating layer 10, and the first wiring 3 and the second wiring 8 are electrically connected via a contact hole 16.

Verfahren zur Herstellung von Halbleiter-Chips, Montageverfahren und Halbleiter-Chip für senkrechte Montage auf Schaltungsträger

Ein Halbleiter-Chip mit Kontaktflächen (22) auf einer Oberseite (56) parallel zur Waferebene hat Anschlussflächen (12) auf einer Anschlussflächenseite (14) senkrecht zur Oberseite, wobei jede Anschlussfläche mit einer zugeordneten Kontaktfläche (22) leitend verbunden ist. Dies ermöglicht eine vertikale Montage des Chips auf einem Träger und Kontaktierung mittels üblicher Bond-Techniken. Ein Herstellungsverfahren und zwei Montageverfahren werden beschrieben.

DIE-STAPEL UND DEREN AUSBILDUNGSVERFAHREN

Ein Verfahren umfasst ein Verdünnen eines Halbleitersubstrats eines Vorrichtungs-Dies, so dass Substrat-Durchkontaktierungen freigelegt werden, die sich in das Halbleitersubstrat erstrecken, und ein Ausbilden einer ersten Umverteilungsstruktur, das ein Ausbilden einer ersten Mehrzahl von dielektrischen Schichten über dem Halbleitersubstrat und ein Ausbilden einer ersten Mehrzahl von Umverteilungsleitungen in der ersten Mehrzahl von dielektrischen Schichten umfasst. Die erste Mehrzahl von Umverteilungsleitungen sind elektrisch mit den Substrat-Durchkontaktierungen verbunden. Das Verfahren umfasst ferner ein Anordnen eines ersten Speicher-Dies über der ersten Umverteilungsstruktur und ein Ausbilden einer ersten Mehrzahl von Metallpfosten über der ersten Umverteilungsstruktur. Die erste Mehrzahl von Metallpfosten sind elektrisch mit der ersten Mehrzahl von Umverteilungsleitungen verbunden. Der erste Speicher-Die wird in einem ersten Einkapselungsmittel eingekapselt. Eine zweite Mehrzahl von ...

Semiconductor device and manufacturing method of semiconductor device

REDISTRIBUTION LAYER METALLIC STRUCTURE AND METHOD

Package device and manufacturing method thereof

A package device and a manufacturing method thereof are provided. The manufacturing method of the package device includes providing a substrate and forming a redistribution layer on the substrate. The substrate has at least one device region and a non-device region. The redistribution layer includes at least one inspection structure and at least one wire structure disposed in the device region. A part of the inspection structure and a part of the wire structure are formed of a same layer, and the inspection structure has a trench exposing the part of the inspection structure.

Methods of forming cowos structures

Chip on wafer on substrate structures and methods of forming are provided. The method includes attaching a first die and a second die to an interposer. The method also includes attaching a first substrate to a first surface of the first die and a first surface of the second die. The first substrate includes silicon. The first surface of the first side is opposite to the surface of the first die that is attached to the interposer, and the first surface of the second die is opposite to the surface of the second die that is attached to the interposer. The method includes bonding the interposer to a second substrate.

THREE DIMENSIONAL MICROELECTRONIC COMPONENTS AND FABRICATION METHODS FOR SAME

Aspects and examples include electrical components and methods of forming electrical components. In one example, a method includes selecting a substrate, forming a pattern of a first conductive material on a top surface of the substrate, forming a pattern of a second conductive material on a bottom surface of the substrate, dicing the substrate into one or more die having a first diced surface and a second diced surface, securing the first diced surface of each of the one or more die to a retaining material, encapsulating the one or more die in an encapsulent to form a reconstituted wafer, and forming a pattern of a third conductive material on the second diced surface by metalizing a surface of the reconstituted wafer.

Top layers of metal for high performance IC's

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Redistribution Layer Metallic Structure and Method

The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.

Semiconductor device

A semiconductor device includes a semiconductor chip having a first main surface having an electrode pad in an exposed state, and an interlayer insulation layer formed on the first main surface so that the electrode pad is partially exposed; a re-wiring layer including a wiring pattern having a linear portion having one end portion electrically connected to the electrode pad and extending from the electrode pad, and a post electrode mounting portion with a recessed polygonal shape and connected to the other end portion of the linear portion; a post electrode formed on the post electrode mounting portion and having a bottom surface with a contour crossing an upper contour of the post electrode mounting portion at more than two points; a sealing portion disposed so that a top of the post electrode is exposed; and an outer terminal formed on the top of the post electrode.

Semiconductor Device and Method of Forming RDL Wider than Contact Pad along First Axis and Narrower than Contact Pad Along Second Axis

A semiconductor device has a semiconductor die and first conductive layer formed over a surface of the semiconductor die. A first insulating layer is formed over the surface of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. An opening is formed in the second insulating layer over the first conductive layer. A second conductive layer is formed in the opening over the first conductive layer and second insulating layer. The second conductive layer has a width that is less than a width of the first conductive layer along a first axis. The second conductive layer has a width that is greater than a width of the first conductive layer along a second axis perpendicular to the first axis. A third insulating layer is formed over the second conductive layer and first insulating layer.

Conductive feature for semiconductor substrate and method of manufacture

A conductive feature on a semiconductor component is disclosed. A first passivation layer is formed over a substrate. A bond pad is formed over the first passivation layer. A second passivation layer overlies the first passivation layer and the bond pad. The second passivation layer has a first opening overlying the bond pad and a plurality of second openings exposing a top surface of the first passivation layer. A buffer layer overlies the second passivation layer and fills the plurality of second openings. The buffer layer has a third opening overlapping the first opening and together exposes a portion the bond pad. The combined first opening and third opening has sidewalls. An under bump metallurgy (UBM) layer overlies the sidewalls of the combined first opening and third opening, and contacts the exposed portion of the bond pad. A conductive feature overlies the UBM layer.

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device including the following steps: forming an insulator layer over a first conductor over a semiconductor substrate; forming a barrier layer to coat the surface of the insulator layer; forming a second conductor over the barrier layer; melting the second conductor in an atmosphere containing either hydrogen or carboxylic acid in a condition that the surface of the insulator layer over the first conductor is coated with the barrier layer; and removing the barrier layer partially from the surface of the insulator layer with the second conductor as a mask.

Device mounting board and method of manufacturing the same, semiconductor module, and mobile device

A device mounting board includes: an insulating resin layer; a wiring layer formed on one of the principal surfaces of the insulating resin layer; a protection layer covering the insulating resin layer and the wiring layer; a protruding electrode electrically connected to the wiring layer, the protruding electrode protruding from the wiring layer toward the insulating resin layer and penetrating through the insulating resin layer; a wiring-layer-side convex portion protruding from the wiring layer toward the insulating resin layer and having the top end thereof located inside the insulating resin layer; and a resin-layer-side convex portion protruding from the protection layer toward the insulating resin layer and having the top end thereof located inside the insulating resin layer.

Impedence controlled packages with metal sheet or 2-layer rdl

A microelectronic assembly includes an interconnection element, a conductive plane, a microelectronic device, a plurality of traces, and first and second bond elements. The interconnection element includes a dielectric element, a plurality of element contacts, and at least one reference contact thereon. The microelectronic device includes a front surface with device contacts exposed thereat. The conductive plane overlies a portion of the front surface of the microelectronic device. Traces overlying a surface of the conductive plane are insulated therefrom and electrically connected with the element contacts. The traces also have substantial portions spaced a first height above and extending at least generally parallel to the conductive plane, such that a desired impedance is achieved for the traces. First bond element electrically connects the at least one conductive plane with the at least one reference contact. Second bond elements electrically connect device contacts with the traces.

Layered chip package and method of manufacturing same

A layered chip package includes a main body and wiring. The main body includes: a main part having a top surface and a bottom surface and including three or more layer portions stacked on one another; a plurality of first terminals disposed on the top surface of the main part; and a plurality of second terminals disposed on the bottom surface of the main part. Each layer portion includes a semiconductor chip having first and second surfaces, and a plurality of electrodes electrically connected to the wiring. The plurality of electrodes are disposed on a side of the first surface of the semiconductor chip. A first layer portion located closest to the top surface of the main part and a second layer portion located closest to the bottom surface of the main part are arranged so that the second surfaces of their respective semiconductor chips face toward each other. The plurality of first terminals are formed by using the plurality of electrodes of the first layer portion. The plurality of second terminals are formed by using the plurality of electrodes of the second layer portion.

Method for manufacturing a circuit device

A semiconductor substrate and a copper sheet stacked with an insulating resin layer are bonded together at a temperature of 130° C. or below (first temperature) so that an element electrode provided on the semiconductor substrate connects to the copper sheet before a thinning process. Then the semiconductor substrate and the copper sheet, on which the insulating resin layer has been stacked, are press-bonded at a high temperature of 170° C. or above (second temperature) with the copper sheet thinned to thickness of a wiring layer. Then the wiring layer (rewiring) is formed by patterning the thinned copper sheet.

Integrated circuit and method of making

Circuits and methods of fabricating circuits are disclosed herein. An embodiment of the circuit includes a die having a side, wherein a connection point is located on the side. A dielectric layer having a first side, a second side, and at least one via extending between the first side and the second side, is located proximate the side of the die. The via is electrically connected to the connection point. A conductive layer is located adjacent the second side of the first dielectric layer, wherein at least a portion of the conductive layer is electrically connected to the via.

Power management applications of interconnect substrates

Various applications of interconnect substrates in power management systems are described.

Post-passivation interconnect structure and method of forming the same

A semiconductor device includes a conductive layer formed on the surface of a post-passivation interconnect (PPI) structure by an immersion tin process. A polymer layer is formed on the conductive layer and patterned with an opening to expose a portion of the conductive layer. A solder bump is then formed in the opening of the polymer layer to electrically connect to the PPI structure.

Semiconductor Device and Method of Forming RDL Under Bump for Electrical Connection to Enclosed Bump

A semiconductor device has a semiconductor wafer with a plurality of semiconductor die. A first conductive layer is formed over a surface of the wafer. A first insulating layer is formed over the surface of the wafer and first conductive layer. A second conductive layer has first and second segments formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A UBM layer is formed over the second insulating layer and the first segment of the second conductive layer. A first bump is formed over the UBM layer. The first bump is electrically connected to the second segment and electrically isolated from the first segment of the second conductive layer. A second bump is formed over the surface of the wafer and electrically connected to the first segment of the second conductive layer.

Semiconductor device having a through-substrate via

Semiconductor devices are described that include a via that extends only partially through the substrate. Through-substrate vias (TSV) furnish electrical interconnectivity to electronic components formed in the substrates. In implementations, the semiconductor devices are fabricated by first bonding a semiconductor wafer to a carrier wafer with an adhesive material. The semiconductor wafer includes an etch stop disposed within the wafer (e.g., between a first surface a second surface of the wafer). One or more vias are formed through the wafer. The vias extend from the second surface to the etch stop.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a first bump that is located over a surface of a semiconductor element, and is formed on a first bump formation face distanced from a back surface of the semiconductor element at a first distance, and a second bump that is located over the surface of the semiconductor element, and is formed on a second bump formation face distanced from the back surface of the semiconductor element at a second distance being longer than the first distance, the second bump having a diameter larger than a diameter of the first bump.

Cte adaption in a semiconductor package

A device such as a wafer-level package (WLP) device is proposed in which a dielectric layer is disposed between a surface of a semiconductor device and a surface of a redistribution layer (RDL). The dielectric layer may have at least one interconnect extending through the dielectric layer. The dielectric layer may have a coefficient of thermal expansion (CTE) value in a direction perpendicular to the surface of the semiconductor device that is less than a threshold value, and a Young's modulus that is greater than another threshold value. The dielectric layer may have a CTE value in a direction parallel to the surface of the semiconductor device at a surface of the dielectric layer facing the RDL that is greater than another threshold value

Semiconductor device including bottom surface wiring and manufacturing method of the semiconductor device

Disclosed herein is a semiconductor device including a semiconductor substrate, a wiring layer formed above the semiconductor substrate, a through-hole electrode extending from the bottom surface of the semiconductor substrate to the wiring layer, a bottom surface wiring provided, at the bottom surface of the semiconductor substrate such that the bottom surface wiring is connected to the through-hole electrode, and an external terminal connected to the bottom surface wiring. The bottom surface wiring has a greater film thickness than a film thickness of the through-hole electrode at least a portion of the bottom surface wiring including a connection part between the bottom surface wiring and the external terminal.

Semiconductor device

A semiconductor device includes a protective layer, a redistribution pattern, a pad pattern and an insulating polymer layer. The protective layer may be formed on a substrate. The redistribution pattern may be formed on the protective layer. An upper surface of the redistribution may be substantially flat. The pad pattern may be formed directly on the redistribution pattern. An upper surface of the pad pattern may be substantially flat. The insulating polymer layer may be formed on the redistribution pattern and the pad pattern. An upper surface of the insulating polymer layer may be lower than the upper surface of the pad pattern. The semiconductor device may have a high reliability.

Semiconductor Device with Shielding Structure for Cross-Talk Reduction

A method includes embedding a die in a molding material; forming a first dielectric layer over the molding material and the die; forming a conductive line over an upper surface of the first dielectric layer facing away from the die; and forming a second dielectric layer over the first dielectric layer and the conductive line. The method further includes forming a first trench opening extending through the first dielectric layer or the second dielectric layer, where a longitudinal axis of the first trench is parallel with a longitudinal axis of the conductive line, and where no electrically conductive feature is exposed at a bottom of the first trench opening; and filling the first trench opening with an electrically conductive material to form a first ground trench.

Semiconductor Structure and Method of Forming the Same

A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region. 1. A structure comprising:a device die;an encapsulant encapsulating the device die therein;a first plurality of Redistribution Lines (RDLs) overlying and electrically coupling to the device die, wherein the first plurality of RDLs have a first pitch, and the first plurality of RDLs are substantially free from undercuts; anda second plurality of RDLs overlying and electrically coupling to the device die, wherein the second plurality of RDLs have a second pitch greater than the first pitch, and the second plurality of RDLs have undercuts.2. The structure of claim 1 , wherein each of the first plurality of RDLs and the second plurality of RDLs comprises an adhesion layer and a metal region over the adhesion layer claim 1 , wherein the adhesion layers in the first plurality of RDLs are free from undercuts claim 1 , and the adhesion layers in the second plurality of RDLs have undercuts.3. The structure of claim 1 , wherein all RDLs at a same level as the first plurality of RDLs are substantially free from undercuts claim 1 , and all RDLs at a same level as the second plurality of RDLs have undercuts.4. The structure of claim 1 , wherein all RDLs at levels underlying the first plurality of RDLs and over the device die are substantially free from ...

METHOD OF PATTERN PLACEMENT CORRECTION

In one embodiment of the invention, a method for correcting a pattern placement on a substrate is disclosed. The method begins by detecting three reference points for a substrate. A plurality of sets of three die location points are detected, each set indicative of an orientation of a die structure, the plurality of sets include a first set associated with a first dies and a second set associated with a second die. A local transformation is calculated for the orientation of the first die and the second on the substrate. Three orientation points are selected from the plurality of sets of three die location points wherein the orientation points are not set members of the same die. A first global orientation of the substrate is calculated from the selected three points from the set of points and the first global transformation and the local transformation for the substrate are stored. 1. A system , comprising:a processor; anda memory, wherein the memory includes an application program configured to perform an operation for correcting a pattern placement on a substrate, the operation comprising:detecting three reference points for a substrate;detecting a plurality of sets of three die location points, each set indicative of an orientation of a die, the plurality of sets include a first set associated with a first die and a second set associated with a second die;calculating a local transformation for an orientation of the first die and the second on the substrate;selecting three orientation points from the plurality of sets of three die location points wherein the orientation points are not members of the same set;calculating a first global orientation of the substrate from the selected three points from the set of points; andstoring the first global orientation and the local transformation for the substrate.2. The system of further comprising:positioning the substrate in a lithography tool;detecting the three reference points;calculating a second global transformation ...

METHOD OF FORMING SEMICONDUCTOR DEVICE HAVING A DUAL MATERIAL REDISTRIBUTION LINE AND SEMICONDUCTOR DEVICE

A method of making a semiconductor device includes depositing a second conductive material over a first conductive material, wherein the second conductive material is different from the first conductive material, and the second conductive material defines a redistribution line (RDL). The method further includes depositing a passivation layer over the RDL, wherein depositing the passivation layer comprises forming a plurality of convex sidewalls, and each of the plurality of convex sidewalls extends beyond an edge of the RDL. 1. A method of making a semiconductor device , the method comprising:depositing a second conductive material over a first conductive material, wherein the second conductive material is different from the first conductive material, and the second conductive material defines a redistribution line (RDL); anddepositing a passivation layer over the RDL, wherein depositing the passivation layer comprises forming a plurality of convex sidewalls, and each of the plurality of convex sidewalls extends beyond an edge of the RDL.2. The method of claim 1 , wherein depositing the second conductive material comprises depositing aluminum.3. The method of claim 1 , further comprising depositing the first conductive material over an interconnect structure.4. The method of claim 3 , wherein depositing the first conductive material comprises depositing a copper containing material.5. The method of claim 1 , further comprising patterning the second conductive material to define the RDL.6. The method of claim 1 , wherein depositing the passivation layer comprises depositing the passivation layer to define a flat top surface of the passivation layer over the RDL.7. The method of claim 1 , wherein depositing the passivation layer comprises depositing the passivation layer to a thickness ranging from about 200 nanometers (nm) to about 2 claim 1 ,000 nm.8. A method of making a semiconductor device claim 1 , the method comprising:plating a first conductive material over ...

Integrated Circuit Structures And Methods Of Forming An Opening In A Material

In some embodiments, a method of forming an opening in a material comprises forming RIM over target material. Radiation is impinged onto the RIM through a masking tool over a continuous area of the RIM under which a target-material opening will be formed. The masking tool during the impinging allows more radiation there-through onto a mid-portion of the continuous area of the RIM in a vertical cross-section than onto laterally-opposing portions of the continuous area of the RIM that are laterally-outward of the mid-portion of the RIM in the vertical cross-section. After the impinging, the RIM is developed to form a RIM opening that has at least one pair of laterally-opposing ledges laterally-outward of the mid-portion of the RIM in the vertical cross-section elevationally between a top and a bottom of the RIM opening. The developed RIM is used as masking material while etching the target material through the RIM opening to form the target-material opening to have at least one pair of laterally-opposing ledges laterally-outward of a mid-portion in the target-material opening in the vertical cross-section elevationally between a top and a bottom of the target-material opening. Other aspects and constructions independent of manufacture are disclosed. 119-. (canceled)20. A method of forming an opening in a material , comprising:forming radiation-imageable material (RIM) over target material;impinging radiation onto the RIM through a masking tool over a continuous area of the RIM under which a target-material opening will be formed, the masking tool during the impinging allowing more radiation there-through onto a mid-portion of the continuous area of the RIM in a vertical cross-section than onto laterally-opposing portions of the continuous area of the RIM that are laterally-outward of the mid-portion of the RIM in the vertical cross-section;after the impinging, developing the RIM to form a RIM opening that has at least one pair of laterally-opposing ledges laterally- ...

Methods Of Forming Microvias With Reduced Diameter

A method for forming microvias for packaging applications is disclosed. A sacrificial photosensitive material is developed to form microvias with reduced diameter and improved placement accuracy. The microvias are filled with a conductive material and the surrounding dielectric is removed and replaced with an RDL polymer layer. 1. A method of forming a microvia , the method comprising:depositing a conductive seed layer on a substrate;depositing a first conductive layer on the conductive seed layer;patterning the first conductive layer to form first conductive lines or capture pads;depositing a first dielectric layer;patterning the first dielectric layer to form at least one via having a diameter;depositing a conductive material into the at least one via to form at least one conductive pillar with a height;removing the first dielectric layer and the conductive seed layer from the substrate; anddepositing a second dielectric layer around the at least one conductive pillar.2. (canceled)3. The method of claim 1 , further comprising performing an ashing process after removing the first dielectric layer and the conductive seed layer.4. The method of claim 1 , further comprising:depositing the second dielectric layer with a thickness greater than the height of the at least one conductive pillar; andplanarizing the second dielectric layer to expose a top of the at least one conductive pillar.5. The method of claim 1 , further comprising:depositing a second conductive layer on the second dielectric layer and the at least one conductive pillar; andpatterning the second conductive layer to form second conductive lines or capture pads.6. The method of claim 1 , wherein the conductive seed layer and the conductive material comprise copper.7. The method of claim 1 , wherein the first dielectric layer comprises a photosensitive dielectric and patterning at least one via into the first dielectric layer comprises a photolithography process.8. The method of claim 7 , wherein the ...

Electro-oxidative metal removal in through mask interconnect fabrication

In one implementation a wafer processing method includes filling a plurality of through-resist recessed features with a metal, such that a ratio of fill rate of a first feature to a fill rate of a second feature is R1; followed by electrochemically removing metal such that a ratio of metal removal rate from the first feature to the metal removal rate from the second feature is greater than R1, improving the uniformity of the fill. In some embodiments the method includes contacting an anodically biased substrate with an electrolyte such that the electrolyte has a transverse flow component in a direction that is substantially parallel to the working surface of the substrate. The method can be implemented in an apparatus that is configured for generating the transverse flow at the surface of the substrate. In some implementations the method makes use of distinct electrochemical regimes to achieve improvement in uniformity.

SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor substrate having a chip region and an edge region, a lower dielectric layer on the semiconductor substrate, a chip pad on the lower dielectric layer of the chip region, an upper dielectric layer on the lower dielectric layer, which includes a first opening exposing the chip pad on the chip region and a second opening exposing the lower dielectric layer on the edge region, and a redistribution pad connected to the chip pad. The redistribution pad includes a via portion in the first opening and a pad portion extending from the via portion onto the upper dielectric layer. 1. A semiconductor device , comprising:a semiconductor substrate comprising a chip region and an edge region;a lower dielectric layer on the semiconductor substrate;a chip pad on the lower dielectric layer of the chip region;an upper dielectric layer on the lower dielectric layer, the upper dielectric layer comprising a first opening exposing the chip pad on the chip region and a second opening exposing the lower dielectric layer on the edge region; anda redistribution pad connected to the chip pad, the redistribution pad comprising a via portion in the first opening and a pad portion extending from the via portion onto the upper dielectric layer.2. The semiconductor device of claim 1 , wherein the lower dielectric layer comprises a dielectric material whose dielectric constant is less than that of the upper dielectric layer.3. (canceled)4. The semiconductor device of claim 1 , wherein claim 1 , on the edge region claim 1 , the lower dielectric layer comprises a first segment having a first thickness and a second segment having a second thickness less than the first thickness.5. The semiconductor device of claim 1 , wherein the lower dielectric layer has a first thickness on the chip region and a portion of the lower dielectric layer on the edge region has a second thickness claim 1 , the second thickness being less than the first thickness.6. (canceled) ...

Fan-out sensor package and camera module

The fan-out sensor package includes: a core member having a through-hole; an integrated circuit (IC) for a sensor disposed in the through-hole and having a first surface having a sensor region and first connection pads disposed thereon, a second surface opposing the first surface and having second connection pads disposed thereon, and through-silicon vias (TSVs) penetrating between the first and second surfaces and electrically connecting the first and second connection pads to each other; an encapsulant covering the core member and the second surface of the IC for a sensor and filling at least portions of the through-hole; a redistribution layer disposed on the encapsulant; and vias penetrating through at least portions of the encapsulant and electrically connecting the redistribution layer and the second connection pads to each other.

Semiconductor Structure and Method of Forming the Same

A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region. 1. A method comprising:encapsulating a device die in an encapsulating material;planarizing the encapsulating material and the device die; an adhesion layer; and', 'a metal region over the adhesion layer; and, 'forming a conductive feature over and electrically coupling to the device die, wherein the conductive feature comprisesafter the conductive feature is formed, performing a re-etching process, wherein in the re-etching process, the metal region is etched faster than the adhesion layer.2. The method of claim 1 , wherein before the re-etching process claim 1 , a first edge of the adhesion layer is laterally recessed more than a corresponding second edge of the metal region to form an undercut claim 1 , and the undercut is at least reduced in size by the re-etching process.3. The method of claim 2 , wherein the undercut is eliminated by the re-etching process.4. The method of claim 2 , wherein after the re-etching process claim 2 , the adhesion layer extends laterally beyond the corresponding second edge of the metal region.5. The method of claim 1 , wherein the forming the conductive feature comprises:depositing a first conductive material to form a first seed layer;depositing a second conductive material different from the first conductive ...

Semiconductor device having through silicon vias

The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a conductive feature, a redistribution layer, at least one through silicon via and at least one bump. The conductive feature is disposed over a front surface of the substrate, and the redistribution layer is disposed over a back surface opposite to the front surface. The through silicon via penetrates through the substrate and contacts the conductive feature embedded in an insulative layer. The bump contacts the redistribution layer and the through silicon via and serves as an electrical connection therebetween.

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device. 113-. (canceled)14. A manufacturing method of a semiconductor device , comprising the steps of:(a) providing a semiconductor wafer equipped with a plurality of device formation regions,each device formation region having a semiconductor circuit, a pad electrically coupled to the semiconductor circuit, a first insulating film formed over the pad such that a surface portion of the pad is exposed from an opening of the first insulating film, and a second insulating film formed over the first insulating film such that the surface portion of the pad is exposed from the second insulating film;(b) contacting a probe needle to a first region of the surface portion of the pad of each device formation region; and(c) after the step (b), forming an interconnect layer over a second region of the surface portion of each pad adjacent to the first region by plating, such that the interconnect layer is electrically coupled to the pad at the second region.15. The manufacturing method of a semiconductor device according to claim 14 , further comprising the steps of:(d) after the step (c), coupling a conductive member to one end portion of the ...

Semiconductor device

A semiconductor device suitable for preventing malfunction is provided. The semiconductor device includes a semiconductor chip 1 , a first electrode pad 21 laminated on the semiconductor chip 1 , an intermediate layer 4 having a rectangular shape defined by first edges 49 a and second edges, and a plurality of bumps 5 arranged to sandwich the intermediate layer 4 by cooperating with the semiconductor chip 1 . The first edges 49 a extend in the direction x, whereas the second edges extend in the direction y. The plurality of bumps 5 include a first bump 51 electrically connected to the first electrode pad 21 and a second bump 52 electrically connected to the first electrode pad 21 . The first bump 51 is arranged at one end in the direction x and one end in the direction y.

Semiconductor chip, semiconductor package including the same, and method of fabricating the same

A semiconductor chip and/or a semiconductor package including the same are disclosed. The semiconductor chip may include an integrated circuit on a substrate, a center pad electrically connected to the integrated circuit, a lower insulating structure on the center pad and having a contact hole exposing the center pad, the lower insulating structure including a plurality of lower insulating layers sequentially stacked on the substrate, a conductive pattern including a contact portion, a pad portion, a conductive line portion, the contact portion filling the contact hole, the pad portion including a test region and a bonding region, a conductive line portion on the lower insulating structure and connecting the contact portion to the pad portion, and an upper insulating structure on the conductive pattern and having a first opening exposing the pad portion, and the upper insulating structure including an upper insulating layer and a polymer layer.

STRUCTURE FOR STACKED LOGIC PERFORMANCE IMPROVEMENT

In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a plurality of interconnect layers within an inter-level dielectric (ILD) structure disposed along a front-side of a substrate. A dielectric layer is arranged along a back-side of the substrate and a conductive bond pad is separated from the substrate by the dielectric layer. A back-side through-substrate-via (BTSV) extends through the substrate and the dielectric layer. A conductive bump is arranged over the conductive bond pad. The conductive bond pad has a substantially planar lower surface extending from over the BTSV to below the conductive bump. A BTSV liner separates sidewalls of the BTSV from the substrate. The sidewalls of the BTSV directly contact sides of both the BTSV liner and the dielectric layer. 1. An integrated chip , comprising:a plurality of interconnect layers within an inter-level dielectric (ILD) structure disposed along a front-side of a substrate;a dielectric layer arranged along a back-side of the substrate;a conductive bond pad separated from the substrate by the dielectric layer;a back-side through-substrate-via (BTSV) extending through the substrate and the dielectric layer;a conductive bump arranged over the conductive bond pad, wherein the conductive bond pad has a substantially planar lower surface extending from over the BTSV to below the conductive bump; anda BTSV liner separating sidewalls of the BTSV from the substrate, wherein the sidewalls of the BTSV directly contact sides of both the BTSV liner and the dielectric layer.2. The integrated chip of claim 1 , wherein the sidewalls of the BTSV directly contact the sides of both the BTSV liner and the dielectric layer at positions that are vertically between the back-side of the substrate and the substantially planar lower surface of the conductive bond pad.3. The integrated chip of claim 1 ,wherein the plurality of interconnect layers comprise a first interconnect wire and a ...

Integrated Circuit Features with Obtuse Angles and Method of Forming Same

A method includes forming a seed layer on a semiconductor wafer, coating a photo resist on the seed layer, performing a photo lithography process to expose the photo resist, and developing the photo resist to form an opening in the photo resist. The seed layer is exposed, and the opening includes a first opening of a metal pad and a second opening of a metal line connected to the first opening. At a joining point of the first opening and the second opening, a third opening of a metal patch is formed, so that all angles of the opening and adjacent to the first opening are greater than 90 degrees. The method further includes plating the metal pad, the metal line, and the metal patch in the opening in the photo resist, removing the photo resist, and etching the seed layer to leave the metal pad, the metal line and the metal patch.

METHODS FOR PRODUCING PACKAGED SEMICONDUCTOR DEVICES

A method comprises: arranging a plurality of semiconductor chips above a carrier, wherein active main surfaces of the semiconductor chips face the carrier; filling a cavity with a molding material; pressing the semiconductor chips arranged on the carrier into the molding material; and separating the molding material with the semiconductor chips embedded therein from the carrier, wherein main surfaces of the semiconductor chips that are situated opposite the active main surfaces are covered by the molding material. 1. A method comprising:arranging a plurality of semiconductor chips above a carrier, wherein active main surfaces of the plurality of semiconductor chips face the carrier;filling a cavity with a molding material;pressing the plurality of semiconductor chips arranged on the carrier into the molding material; andseparating the molding material with the plurality of semiconductor chips embedded therein from the carrier, wherein opposite main surfaces of the semiconductor chips that are situated opposite the active main surfaces are covered by the molding material.2. The method as claimed in claim 1 , wherein a thickness of the molding material claim 1 , above the opposite main surfaces of the plurality of semiconductor chips claim 1 , lies in a range of approximately 50 micrometers to approximately 1000 micrometers.3. The method as claimed in claim 1 , wherein the cavity is free of electronic components during the filling of the cavity with the molding material.4. The method as claimed in claim 1 , wherein the cavity is filled with the molding material in a form of granules.5. The method as claimed in claim 1 , wherein the cavity is filled with the molding material in a non-liquid form and the molding material is liquefied by heating the molding material before the pressing of the plurality of semiconductor chips into the molding material.6. The method as claimed in claim 5 , wherein the cavity is formed by a mold and the molding material is liquefied by ...

SEMICONDUCTOR DEVICE

A semiconductor device is provided. The semiconductor device includes a substrate, an insulating film, and a photo sensitive film. The substrate includes a semiconductor chip region and a scribe line region disposed along an edge of the semiconductor chip region. The insulating film includes a first portion disposed on the semiconductor chip region, a second portion disposed on the scribe line region and connected with the first portion, and a third portion disposed on the scribe line region and protruded in a first direction from the second portion. The photo sensitive film is disposed on the insulating film and has a sidewall exposed on the second portion of the insulating film. A first width of the third portion in a second direction perpendicular to the first direction decreases as a distance from the semiconductor chip region increases. 1. A semiconductor device comprising:a substrate comprising a semiconductor chip region and a scribe line region disposed along an edge of the semiconductor chip region;an insulating film comprising a first portion disposed on the semiconductor chip region, a second portion disposed on the scribe line region and connected with the first portion, and a third portion disposed on the scribe line region and protruded in a first direction from the second portion; anda photo sensitive film disposed on the insulating film and having an exposed sidewall exposed on the second portion of the insulating film,wherein a first width of the third portion in a second direction perpendicular to the first direction decreases as a distance from the semiconductor chip region increases.2. The semiconductor device of claim 1 , wherein the third portion comprises a first surface in contact with the second portion claim 1 , a second surface opposing the first surface claim 1 , and a third surface connecting the first surface and the second surface claim 1 , andthe third surface has a flat plane shape.3. The semiconductor device of claim 1 , wherein the ...

FABRICATION OF SOLDER BALLS WITH INJECTION MOLDED SOLDER

Wafers include a contact pad on a surface of a bulk redistribution layer. A final redistribution layer is formed on the surface and in contact with the contact pad. Solder is formed on the contact pad. The solder includes a pedestal portion formed to a same height as the final redistribution layer and a ball portion above the pedestal portion. 1. A wafer , comprising:a contact pad on a surface of a bulk redistribution layer;a final redistribution layer formed on the surface and in contact with the contact pad; andsolder formed on the contact pad, comprising a pedestal portion formed to a same height as the final redistribution layer and a ball portion above the pedestal portion.2. The wafer of claim 1 , wherein the final redistribution layer is formed from a material selected from the group consisting of a photosensitive phenolic resin and a polymide material.3. The wafer of claim 1 , wherein the wafer comprises a plurality of contact pads on the surface and solder formed on respective contact pads.4. The wafer of claim 1 , wherein the final redistribution layer comprises a hole formed directly over the contact pads.5. The wafer of claim 1 , wherein a top surface of the final redistribution layer has a height that is lower than a height of a top of the solder.6. The wafer of claim 1 , wherein a top surface of the final redistribution layer has a height that is greater than a height of a top surface of the contact pad.7. The wafer of claim 1 , wherein the bulk redistribution layers is formed from one or more of the materials selected from the group consisting of a polymide material claim 1 , a polybenzoxazole material claim 1 , and a benocyclobutane material.8. The wafer of claim 1 , wherein the solder has a composition of about 0.5% copper claim 1 , about 96.5% tin claim 1 , and about 3% silver.9. The wafer of claim 1 , wherein the solder has a diameter of about 90 μm.10. The wafer of claim 1 , wherein the ball portion of the solder extends laterally above the final ...

Semiconductor Device and Method of Forming Patterned Repassivation Openings Between RDL and UBM to Reduce Adverse Effects of Electro-Migration

A semiconductor device has a semiconductor wafer with a first conductive layer formed over a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and first conductive layer. A second conductive layer is formed over the first insulating layer and first conductive layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A plurality of openings is formed in the second insulating layer in a bump formation area of the semiconductor wafer to expose the second conductive layer and reduce adverse effects of electro-migration. The openings are separated by portions of the second insulating layer. A UBM layer is formed over the openings in the second insulating layer in the bump formation area electrically connected to the second conductive layer. A bump is formed over the UBM layer.

Method of manufacturing semiconductor device

The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming an interconnect layer on a semiconductor component, wherein the interconnect layer contains at least one metal pad electrically coupled to the semiconductor component; depositing an insulating layer on the interconnect layer; depositing a bonding dielectric on the insulating layer; and forming a re-routing layer penetrating through the bonding dielectric and the insulating layer and contacting the interconnect layer.

PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME

A package structure is provided. The package structure includes a dielectric layer on a die, a RDL structure and a conductive terminal. The RDL structure comprises a redistribution layer in and on the dielectric layer. The redistribution layer comprises a via and a conductive plate. The via is located in and penetrating through the dielectric layer to be connected to the die. The conductive plate is on the via and the dielectric layer, and is connected to the die through the via. The conductive terminal is electrically connected to the die through the RDL structure. The via is ring-shaped. 1. A package structure , comprising:a die;a dielectric layer on the die; a via located in and penetrating through the dielectric layer to be connected to the die, wherein the via is ring-shaped; and', 'a conductive plate on the via and the dielectric layer, and is connected to the die through the via; and, 'an RDL structure comprising a redistribution layer in and on the dielectric layer, wherein the redistribution layer comprisesa conductive terminal, electrically connected to the die through the RDL structure,wherein the dielectric layer comprises a first portion enclosed by an inner sidewall of the via and in physical contact with the die.2. The package structure of claim 1 , wherein the dielectric layer further comprises a second portion outside an outer sidewall of the via claim 1 , wherein the first portion and the second portion of the dielectric layer are separated from each other by the via therebetween.3. The package structure of claim 1 , wherein the via and the conductive plate are coaxial.4. The package structure of claim 3 , wherein the RDL comprises multilayers of the vias and conductive plates stacked alternately claim 3 , and diameters of the conductive plates are increased progressively from bottom to top claim 3 , the vias are staggered with each other or partially overlapped with each other.5. The package structure of claim 1 , wherein the via has a circular ...

ELECTRONIC SYSTEM HAVING INCREASED COUPLING BY USING HORIZONTAL AND VERTICAL COMMUNICATION CHANNELS

An electronic system supports superior coupling by implementing a communication mechanism that provides at least for horizontal communication for example, on the basis of wired and/or wireless communication channels, in the system. Hence, by enhancing vertical and horizontal communication capabilities in the electronic system, a reduced overall size may be achieved, while nevertheless reducing complexity in printed circuit boards coupled to the electronic system. In this manner, overall manufacturing costs and reliability of complex electronic systems may be enhanced. 1. An apparatus , comprising:an integrated circuit die comprising a semiconductor substrate and a metallization structure;wherein the semiconductor substrate includes integrated circuits and has a top surface and an oppositely arranged bottom surface and a side surface where the integrated circuit die was singulated from a wafer;wherein the metallization structure is mounted above the top surface of the semiconductor substrate and includes at least one contact pad and an electrical connection between the at least one contact pad and the integrated circuits; anda dielectric layer disposed in contact with a top surface of the metallization structure and the side surface of the semiconductor substrate;wherein the dielectric layer comprises a first communication pad that is electrically connected to said at least one contact pad and a second communication pad that is electrically connected to said at least one contact pad;wherein the first communication pad is disposed on a first face of the dielectric layer extending parallel to the top surface of the metallization structure and the second communication pad is disposed on a second face of the dielectric layer extending parallel to the side surface of the semiconductor substrate.2. The apparatus of claim 1 , wherein the second communication pad is electrically insulated from the side surface of the semiconductor substrate by said dielectric layer and ...

FULLY MOLDED MINIATURIZED SEMICONDUCTOR MODULE

A semiconductor module can comprise a fully molded base portion comprising a planar surface that further comprises a semiconductor die comprising contact pads, conductive pillars coupled to the contact pads and extending to the planar surface, and an encapsulant material disposed over the active surface, four side surfaces, and around the conductive pillars, wherein ends of the conductive pillars are exposed from the encapsulant material at the planar surface of the fully molded base portion. A build-up interconnect structure comprising a routing layer can be disposed over the fully molded base portion. A photo-imageable solder mask material can be disposed over the routing layer and comprise openings to form surface mount device (SMD) land pads electrically coupled to the semiconductor die and the conductive pillars. A SMD component can be electrically coupled to the SMD land pads with surface mount technology (SMT). 1. A semiconductor module , comprising: a semiconductor die comprising contact pads,', 'conductive pillars coupled to the contact pads and extending to the planar surface, and', 'an encapsulant material disposed over the active surface, four side surfaces, and around the conductive pillars, wherein ends of the conductive pillars are exposed from the encapsulant material at the planar surface of the fully molded base portion;, 'a fully molded base portion comprising a planar surface that further comprisesa build-up interconnect structure comprising a routing layer disposed over the fully molded base portion;a photo-imageable solder mask material disposed over the routing layer and comprising openings to form surface mount device (SMD) land pads electrically coupled to the semiconductor die and the conductive pillars; anda SMD component electrically coupled to the SMD land pads with surface mount technology (SMT).2. The semiconductor module of claim 1 , wherein the photo-imageable solder mask comprises at least one of epoxy solder resist claim 1 , ...

FABRICATION OF SOLDER BALLS WITH INJECTION MOLDED SOLDER

Wafers and methods of forming solder balls include etching a hole in a final redistribution layer over a terminal contact pad on a wafer to expose the terminal contact pad. Solder is injected into the hole using an injection nozzle that is in direct contact with the final redistribution layer. The final redistribution layer is etched back. The injected solder is reflowed to form a solder ball. 1. A method of forming a solder ball , comprising:etching a hole in a final redistribution layer over a terminal contact pad on a wafer to expose the terminal contact pad;injecting solder into the hole using an injection nozzle that is in direct contact with the final redistribution layer;etching back the final redistribution layer; andreflowing the injected solder to form a solder ball.2. The method of claim 1 , wherein the final redistribution layer is formed from one of the group consisting of a phenol material and a polymide material.3. The method of claim 1 , wherein the final redistribution layer is formed from a material different from a material of the plurality of bulk redistribution layers.4. The method of claim 1 , wherein etching back the final redistribution layer exposes sidewalls of the injected solder.5. The method of claim 1 , wherein the wafer comprises a plurality of terminal contact pads claim 1 , wherein etching the hole comprises etching a respective hole over each of the terminal contact pads claim 1 , and wherein injecting solder comprises injecting solder into each of the holes.6. The method of claim 5 , wherein injecting solder into each of the holes comprises sliding the injection nozzle between holes while maintaining direct contact with the final redistribution layer.7. The method of claim 1 , wherein etching back the final redistribution layer comprises a plasma etch.8. The method of claim 1 , wherein injecting the solder is performed in a vacuum to prevent the formation of air pockets in the injected solder.9. A method of forming a solder ball ...

Semiconductor Device With shield for Electromagnetic interference

A semiconductor device includes a first die embedded in a molding material, where contact pads of the first die are proximate a first side of the molding material. The semiconductor device further includes a redistribution structure over the first side of the molding material, a first metal coating along sidewalls of the first die and between the first die and the molding material, and a second metal coating along sidewalls of the molding material and on a second side of the molding material opposing the first side.

Gallium arsenide devices with copper backside for direct die solder attach

Systems, apparatuses, and methods related to the design, fabrication, and manufacture of gallium arsenide (GaAs) integrated circuits are disclosed. Copper can be used as the contact material for a GaAs integrated circuit. Metallization of the wafer and through-wafer vias can be achieved through copper plating processes disclosed herein. Direct die solder (DDS) attach can be achieved by use of electroless nickel plating of the copper contact layer followed by a palladium flash. GaAs integrated circuits can be singulated, packaged, and incorporated into various electronic devices.

Forming Large Chips Through Stitching

A method includes performing a first light-exposure and a second a second light-exposure on a photo resist. The first light-exposure is performed using a first lithograph mask, which covers a first portion of the photo resist. The first portion of the photo resist has a first strip portion exposed in the first light-exposure. The second light-exposure is performed using a second lithograph mask, which covers a second portion of the photo resist. The second portion of the photo resist has a second strip portion exposed in the second light-exposure. The first strip portion and the second strip portion have an overlapping portion that is double exposed. The method further includes developing the photo resist to remove the first strip portion and the second strip portion, etching a dielectric layer underlying the photo resist to form a trench, and filling the trench with a conductive feature.

Packages with Solder Ball Revealed Through Layer

An integrated circuit structure includes a substrate, a PPI over the substrate, a solder region over and electrically coupled to a portion of the PPI, and a molding compound molding a lower portion of the solder region therein. A top surface of the molding compound is level with or lower than a maximum-diameter plane, wherein the maximum-diameter plane is parallel to a major surface of the substrate, and the maximum-diameter of the solder region is in the maximum-diameter plane.

ELECTRONIC SYSTEM HAVING INCREASED COUPLING BY USING HORIZONTAL AND VERTICAL COMMUNICATION CHANNELS

An electronic system supports superior coupling by implementing a communication mechanism that provides at least for horizontal communication for example, on the basis of wired and/or wireless communication channels, in the system. Hence, by enhancing vertical and horizontal communication capabilities in the electronic system, a reduced overall size may be achieved, while nevertheless reducing complexity in printed circuit boards coupled to the electronic system. In this manner, overall manufacturing costs and reliability of complex electronic systems may be enhanced. 1. An apparatus , comprising:a first integrated circuit die singulated from a wafer and comprising a first semiconductor substrate and a first metallization structure mounted to the first semiconductor substrate, wherein the first metallization structure includes a first contact pad;a second integrated circuit die singulated from a wafer and comprising a second semiconductor substrate and a second metallization structure mounted to the second semiconductor substrate, wherein the second metallization structure includes a second contact pad;a first dielectric layer disposed in contact with the first metallization structure and a side surface of the first semiconductor substrate, said first dielectric layer including a first communication pad that is electrically connected to said first contact pad;a second dielectric layer disposed in contact with the second metallization structure and a side surface of the second semiconductor substrate, said second dielectric layer including a second communication pad that is electrically connected to said second contact pad;wherein the first dielectric layer is positioned in physical contact with the second dielectric layer, andwherein the first communication pad is positioned for direct mechanical and electrical connection with the second communication pad.2. The apparatus of claim 1 , wherein the first communication pad is disposed on a face of the first dielectric ...

Semiconductor device

Provided is a semiconductor device including: a first substrate having a first primary surface, a second primary surface, and a side surface; a semiconductor element formed on the first primary surface; a first electrode formed on the first primary surface and connected to the semiconductor element on the first primary surface; a second electrode formed on the second primary surface; a through-electrode formed so as to penetrate the first substrate and connecting the first electrode and the second electrode to each other; a second substrate bonded to the first substrate so as to face the first primary surface; and a third electrode formed on the side surface of the first substrate and connected to the second electrode.

METHOD FOR MANUFACTURING REDISTRIBUTION LAYER

In a method for manufacturing a semiconductor device, a semiconductor substrate having a top surface is provided. A top metal layer is formed in the top surface. A first passivation layer is formed to cover the top metal layer and the top surface. The first passivation layer has a via hole exposing a portion of the top metal layer. A redistribution layer is formed to cover the first passivation layer, the portion of the top metal layer, and a side surface of the via hole. The redistribution layer includes an overhang structure over the via hole. An etching process is performed on the redistribution layer to remove the overhang structure and a portion of the redistribution layer to expose a portion of the first passivation layer. A second passivation layer is formed to cover the redistribution layer and the portion of the first passivation layer. 1. A method for manufacturing a semiconductor device , the method comprising:providing a semiconductor substrate having a top surface;forming a top metal layer in the top surface of the semiconductor substrate;forming a first passivation layer to cover the top metal layer and the top surface of the semiconductor substrate, wherein the first passivation layer is formed to have at least one via hole exposing at least one portion of the top metal layer;forming a redistribution layer to cover the first passivation layer, said at least one portion of the top metal layer, and a side surface of the at least one via hole, wherein the redistribution layer is formed to comprise at least one overhang structure over the at least one via hole;performing an etching process on the redistribution layer to remove the at least one overhang structure and at least one portion of the redistribution layer, wherein said at least one portion of the redistribution layer is removed to expose at least one portion of the first passivation layer; andforming a second passivation layer to cover the redistribution layer and said at least one portion of the ...

POST PASSIVATION INTERCONNECT AND FABRICATION METHOD THEREFOR

A method of manufacturing a semiconductor structure. The method includes depositing a conductive material over a substrate, and removing a portion of the conductive material to form a conductive structure having a barrel shape. A width of a body portion of the conductive structure is greater than a width of an upper portion and a width of a bottom portion of the conductive structure. 1. A method of manufacturing a semiconductor structure , comprising:depositing a conductive material over a substrate; andremoving a portion of the conductive material to form a conductive structure having a barrel shape, wherein a width of a body portion of the conductive structure is greater than a width of an upper portion and a width of a bottom portion of the conductive structure.2. The method of claim 1 , wherein removing the portion of the conductive material comprises:performing an anisotropic etching process to form an upper portion of the conductive structure, wherein the upper portion of the conductive structure has a trapezoidal shape; andperforming an isotropic etching process to form a bottom portion of the conductive structure, wherein the bottom portion of the conductive structure has an undercut.3. The method of claim 2 , wherein performing the isotropic etching process comprises performing a wet etching.4. The method of claim 1 , wherein removing the portion of the conductive material comprises:performing a first reactive ion etching (RIE) process to form an upper portion of the conductive structure; andperforming a second RIE process to form a bottom portion of the conductive structure, wherein a radical/plasma ratio of the first RIE process is greater than a radical/plasma ratio of the second RIE process.5. The method of claim 1 , wherein removing the portion of the conductive material comprises:performing a first plasma etching process to form an upper portion of the conductive structure; andperforming a second plasma etching process to form a bottom portion of the ...

Redistribution layer structure and fabrication method therefor

A method of manufacturing a semiconductor device includes depositing a first passivation layer over a substrate, depositing a conductive material over the first passivation layer, patterning the conductive material to form a redistribution layer (RDL) structure, and depositing a second passivation layer configured to change a shape of a top portion of the RDL structure.

SEMICONDUCTOR LOGIC DEVICE AND SYSTEM AND METHOD OF EMBEDDED PACKAGING OF SAME

A reconfigured semiconductor device includes a semiconductor device comprising an active surface having a plurality of input/output (I/O) pads spaced at a non-solderable pitch thereon and at least one redistribution layer overlying the active surface of the semiconductor device. Each at least one redistribution layer includes an insulating layer and a patterned conductive layer comprising a plurality of discrete terminal pads formed on the insulating layer, each of the plurality of discrete terminal pads electrically coupled to a respective I/O pad of the plurality of I/O pads by a conductive via formed through the insulating layer. 1. A reconfigured semiconductor device comprising:a semiconductor device comprising an active surface having a plurality of input/output (I/O) pads spaced at a non-solderable pitch thereon; and an insulating layer; and', 'a patterned conductive layer comprising a plurality of discrete terminal pads formed on the insulating layer, each of the plurality of discrete terminal pads electrically coupled to a respective I/O pad of the plurality of I/O pads by a conductive via formed through the insulating layer., 'at least one redistribution layer overlying the active surface of the semiconductor device, each at least one redistribution layer comprising2. The reconfigured semiconductor device of wherein the plurality of I/O pads comprise a plurality of signal I/O pads claim 1 , a plurality of power I/O pads claim 1 , and a plurality of ground I/O pads; and a first plurality of discrete terminal pads electrically coupled to the plurality of signal I/O pads; and', 'a second plurality of discrete terminal pads electrically coupled to respective I/O pads of the plurality of power I/O pads and the plurality of ground I/O pads, the second plurality of discrete terminal pads larger than the first plurality of discrete terminal pads., 'wherein the plurality of discrete terminal pads comprise3. The reconfigured semiconductor device of wherein the ...

Three-step Etching to Form RDL

A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region. 1. A method comprising:encapsulating a device in an encapsulating material;planarizing the encapsulating material and the device; and depositing a first conductive material to from a first seed layer;', 'depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer;', 'plating a metal region over the second seed layer;', 'performing a first etching on the second seed layer;', 'performing a second etching on the first seed layer; and', 'after the first seed layer is etched, performing a third etching on the second seed layer and the metal region., 'forming a conductive feature over the encapsulating material and the device, wherein the forming the conductive feature comprises2. The method of claim 1 , wherein the first seed layer comprises titanium claim 1 , tantalum claim 1 , titanium nitride claim 1 , or tantalum nitride claim 1 , and the second seed layer and the metal region each comprise copper.3. The method of claim 1 , wherein the third etching comprises a wet etching.4. The method of claim 1 , wherein undercuts are generated by the second etching claim 1 , and the third etching eliminates the undercuts.5. The method of claim 1 , wherein the conductive feature ...

Wafer-level package mitigated undercut

A wafer-level package device and techniques are described that include utilizing a dry-etch process for mitigating metal seed layer undercut. In an implementation, a process for fabricating the wafer-level package device that employs the techniques of the present disclosure includes processing a substrate, depositing a metal seed layer on the substrate, depositing and patterning a resist layer, depositing a redistribution layer structure, removing the photoresist layer, and dry-etching the metal seed layer. In implementations, the wafer-level package device that employs example techniques in accordance with the present disclosure includes a substrate, a metal seed layer disposed on the substrate, and a redistribution layer structure formed on the metal seed layer. The metal seed layer is dry-etched so that undercut is mitigated.

SILICON PHOTONIC INTERPOSER WITH TWO METAL REDISTRIBUTION LAYERS

A silicon integrated circuit. In some embodiments, the silicon integrated circuit includes a first conductive trace, on a top surface of the silicon integrated circuit, a dielectric layer, on the first conductive trace, and a second conductive trace, on the dielectric layer, connected to the first conductive trace through a first via. 1. A silicon integrated circuit , comprising:a first conductive trace, on a top surface of the silicon integrated circuit;a dielectric layer, on the first conductive trace; anda second conductive trace, on the dielectric layer, connected to the first conductive trace through a first via.2. The silicon integrated circuit of claim 1 , further comprising an under bump metallization capture pad claim 1 , on claim 1 , and connected to the first conductive trace through claim 1 , a second via.3. The silicon integrated circuit of claim 2 , wherein the under bump metallization capture pad comprises:a layer of nickel, and a layer of gold on the layer of nickel.4. The silicon integrated circuit of claim 1 , further comprising a wire bond pad claim 1 , on claim 1 , and connected to the first conductive trace through claim 1 , a second via.5. The silicon integrated circuit of claim 1 , wherein the first conductive trace is composed of a material selected from the group consisting of gold claim 1 , aluminum claim 1 , copper claim 1 , and alloys and combinations thereof.6. The silicon integrated circuit of claim 1 , wherein the second conductive trace is composed of a material selected from the group consisting of gold claim 1 , aluminum claim 1 , copper claim 1 , titanium claim 1 , tungsten claim 1 , tantalum claim 1 , and alloys and combinations thereof.7. The silicon integrated circuit of claim 6 , wherein the second conductive trace further comprises a layer of titanium tungsten.8. The silicon integrated circuit of claim 1 , wherein the dielectric layer is composed of a material selected from the group consisting of silicon dioxide claim 1 , ...

STRUCTURE FOR STANDARD LOGIC PERFORMANCE IMPROVEMENT HAVING A BACK-SIDE THROUGH-SUBSTRATE-VIA

In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first plurality of interconnect layers within a first inter-level dielectric (ILD) structure disposed along a front-side of a first substrate. A conductive pad is arranged along a back-side of the first substrate and a first through-substrate-via (TSV) extends between an interconnect wire of the first plurality of interconnect layers and the conductive pad. A second plurality of interconnect layers are within a second ILD structure disposed along a front-side of a second substrate that is bonded to the first substrate. A second through substrate via (TSV) extends through the second substrate. The second TSV has a greater width than the first TSV. 1. An integrated chip , comprising:a first plurality of interconnect layers within a first inter-level dielectric (ILD) structure disposed along a front-side of a first substrate;a conductive pad arranged along a back-side of the first substrate;a first through-substrate-via (TSV) extending between an interconnect wire of the first plurality of interconnect layers and the conductive pad;a second plurality of interconnect layers within a second ILD structure disposed along a front-side of a second substrate that is bonded to the first substrate; anda second TSV extending through the second substrate, wherein the second TSV has a greater width than the first TSV.2. The integrated chip of claim 1 , further comprising:a dielectric liner disposed along sidewalls of the first TSV, wherein the dielectric liner laterally separates the first TSV from the first substrate and the first ILD structure.3. The integrated chip of claim 1 , further comprising:a first passivation layer disposed directly over and along sidewalls of the conductive pad, wherein the first passivation layer has a first thickness laterally outside of the conductive pad and a smaller, second thickness directly over the conductive pad; anda second passivation ...

Integrated Circuit Features With Obtuse Angles and Method Forming Same

A method includes forming a seed layer on a semiconductor wafer, coating a photo resist on the seed layer, performing a photo lithography process to expose the photo resist, and developing the photo resist to form an opening in the photo resist. The seed layer is exposed, and the opening includes a first opening of a metal pad and a second opening of a metal line connected to the first opening. At a joining point of the first opening and the second opening, a third opening of a metal patch is formed, so that all angles of the opening and adjacent to the first are greater than 90 degrees. The method further includes plating the metal pad, the metal line, and the metal patch in the opening in the photo resist, removing the photo resist, and etching the seed layer to leave the metal pad, the metal line and the metal patch. 1. A method comprising:forming a seed layer on a semiconductor wafer;coating a photo resist on the seed layer;performing a photo lithography process to expose the photo resist;developing the photo resist to form an opening in the photo resist, wherein the seed layer is exposed, and wherein the opening comprises a first opening of a metal pad and a second opening of a metal line connected to the first opening, wherein at a joining point of the first opening and the second opening, a third opening of a metal patch is formed, so that all angles of the opening and adjacent to the first are greater than 90 degrees;plating the metal pad, the metal line, and the metal patch in the opening in the photo resist;removing the photo resist; andetching the seed layer to leave the metal pad, the metal line and the metal patch.2. The method of claim 1 , wherein the photo resist is light-exposed using a lithography mask claim 1 , and the lithography mask comprises a pattern of the metal pad claim 1 , a pattern of the metal line claim 1 , and a pattern of the metal patch.3. The method of further comprising performing Boolean operations on an initial pattern claim 1 , ...

Semiconductor package structure and manufacturing method thereof

A semiconductor package structure, including a circuit substrate, at least two chips, an encapsulant, and a redistribution layer, is provided. The circuit substrate has a first surface and a second surface opposite to the first surface. The at least two chips are disposed on the first surface. Each of the at least two chips has an active surface facing the circuit substrate and includes multiple first conductive connectors and multiple second conductive connectors disposed on the active surface. A pitch of the first conductive connectors is less than a pitch of the second conductive connectors. The encapsulant encapsulates the at least two chips. The redistribution layer is located on the second surface. The first conductive connectors are electrically connected to the redistribution layer by the circuit substrate. The second conductive connectors are electrically connected to the circuit substrate. A manufacturing method of a semiconductor package structure is also provided.

Package structure and manufacturing method thereof

A package structure including a redistribution circuit structure, a first chip, a second chip, a first circuit board, a second circuit board, and a plurality of conductive terminals is provided. The redistribution circuit structure has a first connection surface and a second connection surface opposite to the first connection surface. The first chip and the second chip are disposed on the first connection surface and are electrically connected to the redistribution circuit structure. The first circuit board and the second circuit board are disposed on the second connection surface and are electrically connected to the redistribution circuit structure. The conductive terminals are disposed on the first circuit board or the second circuit board. The conductive terminals are electrically connected to the first circuit board or the second circuit board. A manufacturing method of a package structure is also provided.

SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor package structure includes a first semiconductor die, a second semiconductor die, a third semiconductor die and an external contact. The second semiconductor die is disposed adjacent to the first semiconductor die. The third semiconductor die electrically connects the first semiconductor die and the second semiconductor die. The external contact is electrically connected to the third semiconductor die. An electrical path between the third semiconductor die and the external contact extends through a space between the first semiconductor die and the second semiconductor die. 1. A semiconductor package structure , comprising:a first semiconductor die;a second semiconductor die disposed adjacent to the first semiconductor die;a third semiconductor die electrically connecting the first semiconductor die and the second semiconductor die; andan external contact electrically connected to the third semiconductor die, wherein an electrical path between the third semiconductor die and the external contact extends through a space between the first semiconductor die and the second semiconductor die.2. The semiconductor package structure of claim 1 , further comprising a plurality of first pillars disposed adjacent to the first semiconductor die and/or the second semiconductor die claim 1 , and a plurality of second pillars disposed adjacent to the third semiconductor die.3. The semiconductor package structure of claim 2 , wherein a maximum length of the first pillars is less than a maximum length of the second pillars.4. The semiconductor package structure of claim 2 , wherein a pillar space between the first pillars is less than a pillar space between the second pillars.5. The semiconductor package structure of claim 2 , wherein the electrical path between the third semiconductor die and the external contact includes at least one of the first pillars.6. The semiconductor package structure of claim 2 , further comprising a wiring structure claim 2 , wherein the ...

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

A package structure including a first chip, a second chip, a dielectric body, a third chip, an encapsulant, a first conductive terminal, and a circuit layer is provided. The dielectric body covers the first chip and the second chip. The third chip is disposed on the dielectric body such that a third active surface thereof faces a first active surface of the first chip or a second active surface of the second chip. The encapsulant covers the third chip. The first conductive terminal is disposed on the dielectric body and is opposite to the third chip. The circuit layer includes a first circuit portion and a second circuit portion. The first circuit portion penetrates the dielectric body. The first chip, the second chip, or the third chip is electrically connected to the first conductive terminal through the first circuit portion. The second circuit portion is embedded in the dielectric body. 1. A package structure , comprising:a first chip, having a first active surface;a second chip, having a second active surface;a dielectric body, covering the first chip and the second chip;a third chip, having a third active surface, and the third chip being disposed on the dielectric body in a way that the third active surface faces the first active surface or the second active surface;an encapsulant, covering the third chip;a first conductive terminal, disposed on the dielectric body and opposite to the third chip; and the first circuit portion penetrates through the dielectric body, and the first chip, the second chip, or the third chip is electrically connected to the first conductive terminal through the first circuit portion; and', 'the second circuit portion is embedded in the dielectric body, and the first chip or the second chip is electrically connected to the third chip through the second circuit portion., 'a circuit layer, comprising a first circuit portion and a second circuit portion, wherein'}2. The package structure as claimed in claim 1 , wherein the encapsulant ...

Semiconductor device and method comprising thickened redistribution layers

A method of making a semiconductor package can comprise forming a plurality of thick redistribution layer (RDL) traces over active surfaces of a plurality of semiconductor die that are electrically connected to contact pads on the plurality of semiconductor die, singulating the plurality of semiconductor die comprising the plurality of thick RDL traces, mounting the singulated plurality of semiconductor die over a temporary carrier with the active surfaces of the plurality of semiconductor die oriented away from the temporary carrier, disposing encapsulant material over the active surfaces and at least four side surfaces of each of the plurality of semiconductor die, over the plurality of thick RDL traces, and over the temporary carrier, forming a via through the encapsulant material to expose at least one of the plurality of thickened RDL traces with respect to the encapsulant material, removing the temporary carrier, and singulating the plurality of semiconductor die.

Semiconductor device, pad structure and fabrication method thereof

A semiconductor device, a pad structure, and fabricating methods thereof are provided, relating to the field of semiconductor technology. The pad structure includes a substrate, a first dielectric layer, a groove, a bonding pad and a test pad. The first dielectric layer is disposed on the substrate, and the groove is disposed in the first dielectric layer. One of the bonding pad and the test pad is disposed outside the groove and on the surface of the first dielectric layer not adjacent to the substrate, and the other one is disposed on a bottom of the groove. The semiconductor device, the pad structure, and related fabricating methods improve the production yield and stability of the semiconductor device.

DUAL-DAMASCENE ZERO-MISALIGNMENT-VIA PROCESS FOR SEMICONDUCTOR PACKAGING

Techniques that can assist with fabricating a package layer that includes a plurality of dual-damascene zero-misalignment-vias (dual-damascene ZMVs) and a trace between the dual-damascene ZMVs are described. The disclosed techniques allow for the dual-damascene ZMVs and their corresponding trace to be plated simultaneously in a single step or operation. As such, there is little or no misalignment between the dual-damascene ZMVs, the trace, and the metal pads connected to the ZMVs. In this way, one or more of the embodiments described herein can assist with reducing manufacturing costs, reducing development time of fabricating a package layer, and with increasing the I/O density in a semiconductor package. 1. A method of forming a semiconductor package , the method comprising:depositing a first resist layer on a buildup film, wherein one or more metal pads are formed in the buildup film;depositing a second resist layer on the first resist layer;exposing portions of the first and second resist layers using light that passes through a photomask;removing portions of the first and second resist layers to form a plurality of cavities and a plurality of pillars, wherein two of the cavities uncover a top side of the buildup film, wherein one of the cavities uncovers a top side of a pillar formed from the first resist layer, and wherein two of the pillars are formed from the first and second resist layers;removing any remaining portions of the resist layers to reveal top surfaces of the buildup film and the one or more metal pads;plating a conductive material into the cavities to fill the cavities and cover top sides of the buildup film and the one or more metal pads; andpolishing the conductive material such that top sides of the buildup film are co-planar with a top side of the conductive material, wherein the polished conductive material forms a plurality of dual-damascene zero misalignment vias (ZMVs) and a trace between the plurality of dual-damascene ZMVs.2. The method ...

Self-alignment structure for wafer level chip scale package

A packaged semiconductor device includes a semiconductor substrate, a metal pad, a metal base, a polymer insulating layer, a copper-containing structure and a conductive bump. The metal pad and the metal base are disposed on the semiconductor substrate. The polymer insulating layer overlies the metal base and the semiconductor substrate. The copper-containing structure is disposed over the polymer insulating layer, and includes a support structure and a post-passivation interconnect (PPI) line. The support structure is aligned with the metal base. The PPI line is located partially within the support structure, and extends out through an opening of the support structure, in which a top of the support structure is elevated higher than a top of the PPI line. The conductive bump is held by the support structure.

METHOD OF PATTERN PLACEMENT CORRECTION

In one embodiment of the invention, a method for correcting a pattern placement on a substrate is disclosed. The method begins by detecting three reference points for a substrate. A plurality of sets of three die location points are detected, each set indicative of an orientation of a die structure, the plurality of sets include a first set associated with a first dies and a second set associated with a second die. A local transformation is calculated for the orientation of the first die and the second on the substrate. Three orientation points are selected from the plurality of sets of three die location points wherein the orientation points are not set members of the same die. A first global orientation of the substrate is calculated from the selected three points from the set of points and the first global transformation and the local transformation for the substrate are stored. 1. A method for correcting a pattern placement on a substrate , the method comprising:detecting three reference points for a substrate;detecting a plurality of sets of three die location points, each set indicative of an orientation of a die, the plurality of sets include a first set associated with a first die and a second set associated with a second die;calculating a local transformation for an orientation of the first die and the second die on the substrate;selecting three orientation points from the plurality of sets of three die location points wherein the orientation points are not members of the same set;calculating a first global transformation of the substrate from the selected three points from the set of points; andstoring the first global transformation and the local transformation for the substrate.2. The method of further comprising:positioning the substrate in a lithography tool;detecting the three reference points;calculating a second global transformation from the three reference points;combining the second global transformation with the local transformation to calculate ...

Semiconductor Device and Method

A semiconductor device and method utilizing a dummy structure in association with a redistribution layer is provided. By providing the dummy structure adjacent to the redistribution layer, damage to the redistribution layer may be reduced from a patterning of an overlying passivation layer, such as by laser drilling. By reducing or eliminating the damage caused by the patterning, a more effective bond to an overlying structure, such as a package, may be achieved. 1. A method comprising:forming a first redistribution layer on a substrate;plating conductive features on the first redistribution layer until the conductive features have a first thickness;covering a first subset of the conductive features with a first photoresist, a second subset of the conductive features not covered by the first photoresist;plating the second subset of the conductive features until the conductive features have a second thickness greater than the first thickness;removing the first photoresist;attaching a die laterally separated from the conductive features; andencapsulating the die and the conductive features with an encapsulant.2. The method of claim 1 , wherein the plating the conductive features on the first redistribution layer comprises:forming a passivation layer over the first redistribution layer;patterning the passivation layer with openings exposing the first redistribution layer;depositing a seed layer over the passivation layer and in the openings; andplating the conductive features from the seed layer.3. The method of claim 2 , further comprising:removing portions of the seed layer not covered by the conductive features to expose a portion of the passivation layer between each of the conductive features.4. The method of claim 3 , wherein:the conductive features have a first width after the plating the conductive features on the first redistribution layer, andthe conductive features have a second width after the removing the portions of the seed layer, the first width greater ...

Semiconductor package

A semiconductor package includes a redistribution layer and a semiconductor chip provided on the redistribution layer having a first surface and a second surface opposite to the first surface. The semiconductor chip includes a first chip pad and a second chip pad which are exposed at the first surface. The semiconductor package further includes a capacitor chip disposed between the first surface and the redistribution layer and including a capacitor chip pad connected to the first chip pad, an insulating layer covering the first surface and the capacitor chip, and a conductive post being in contact with the second chip pad and penetrating the insulating layer so as to be connected to the redistribution layer. The conductive post may be spaced apart from the capacitor chip.

SEMICONDUCTOR PACKAGE

A semiconductor package includes a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface, an encapsulant encapsulating at least a portion of the semiconductor chip, and a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer and a via electrically connected to the connection pads of the semiconductor chip, wherein at least a portion of the redistribution layer and the via is formed of a metal layer having a concave portion depressed from a lower surface thereof and filled with an insulating material. 1. A semiconductor package comprising:a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;an encapsulant encapsulating at least a portion of the semiconductor chip; anda connection member disposed on the active surface of the semiconductor chip and including a redistribution layer and a via electrically connected to the connection pads of the semiconductor chip,wherein at least a portion of the redistribution layer and the via is formed of a metal layer having a concave portion depressed from a lower surface thereof, the concave portion being filled with an insulating material.2. The semiconductor package of claim 1 , whereinthe metal layer includes a bonding metal layer exposed through the lower surface of the metal layer and forming the concave portion.3. The semiconductor package of claim 1 , whereinthe connection member further includes an insulating layer disposed around the redistribution layer and the via, andthe metal layer includes a bonding metal layer disposed on an interface with the insulating layer.4. The semiconductor package of claim 1 , whereinthe metal layer includes a first bonding metal layer, a seed metal layer, a plating metal layer, and a second bonding metal layer which are sequentially stacked.5. The semiconductor package ...

Integrated circuit chip, integrated circuit package and display apparatus including the integrated circuit chip

An integrated circuit chip includes an SOI substrate having a structure in which a bulk substrate, a buried insulating film, and a semiconductor body layer are sequentially stacked, a conductive ion implantation region formed at a position adjacent to the buried insulating film in the bulk substrate, an integrated circuit portion formed on an active surface of the semiconductor body layer, and a penetrating electrode portion arranged at a position spaced apart from the integrated circuit portion in a horizontal direction, the penetrating electrode portion penetrating the semiconductor body layer and the buried insulating layer in a vertical direction, and the penetrating electrode portion connected to the conductive ion implantation region. An integrated circuit package and a display device include the integrated circuit chip.

Semiconductor arrangement and formation thereof

A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a metal trace under at least a first dielectric layer and a second dielectric layer. The metal trace is connected to a ball connection by a first via in the first dielectric layer and second via in the second dielectric layer. The metal trace is connected to a test pad at a connection point, where the connection point is under the first dielectric layer. The metal trace under at least the first dielectric layer and the second dielectric layer has increased stability and decreased susceptibility to cracking in least one of the ball connection, the connection point, the first via or the second via as compared to a metal trace that is not under at least a first dielectric layer and a second dielectric layer.

ELECTRONIC SYSTEM HAVING INCREASED COUPLING BY USING HORIZONTAL AND VERTICAL COMMUNICATION CHANNELS

An electronic system supports superior coupling by implementing a communication mechanism that provides at least for horizontal communication for example, on the basis of wired and/or wireless communication channels, in the system. Hence, by enhancing vertical and horizontal communication capabilities in the electronic system, a reduced overall size may be achieved, while nevertheless reducing complexity in printed circuit boards coupled to the electronic system. In this manner, overall manufacturing costs and reliability of complex electronic systems may be enhanced. 1. An apparatus , comprising:a first integrated circuit die singulated from a wafer and comprising a first semiconductor substrate and a first metallization structure mounted to the first semiconductor substrate, wherein the first metallization structure includes a first contact pad and wherein the first semiconductor substrate includes a first through silicon via having a first end exposed at a bottom surface of the first semiconductor substrate;a second integrated circuit die singulated from a wafer and comprising a second semiconductor substrate and a second metallization structure mounted to the second semiconductor substrate, wherein the second metallization structure includes a second contact pad and wherein the second semiconductor substrate includes a second through silicon via having a second end exposed at a bottom surface of the second semiconductor substrate;a first dielectric layer disposed in contact with the first metallization structure and a side surface of the first semiconductor substrate, said first dielectric layer including a first communication pad that is electrically connected to said first contact pad;a second dielectric layer disposed in contact with the second metallization structure and a side surface of the second semiconductor substrate, said second dielectric layer including a second communication pad that is electrically connected to said second contact pad;wherein the ...

SEMICONDUCTOR DEVICE AND METHOD OF PACKAGING

A semiconductor device may comprise a semiconductor die comprising an active surface and contact pads disposed. Conductive interconnects comprising first ends may be coupled to the contact pads and second ends may be disposed opposite the first ends. An encapsulant may comprise a planar surface disposed over the active surface of the semiconductor die. The planar surface may be offset from the second surface of the conductive interconnects by a distance greater than or equal to 1 micrometer. A build-up interconnect layer may be disposed over the planar surface and extend into the openings to electrically connect with the conductive interconnects. A method of making the semiconductor device may further comprise grinding a surface of the encapsulant to form the planar surface and the conductive residue across the planar surface. The conductive residue may be etched to remove the conductive residue and to reduce a height of the conductive interconnects. 1. A semiconductor device comprising:a semiconductor die comprising four side surfaces and an active surface, the semiconductor die further comprising contact pads disposed over the active surface;conductive interconnects comprising first ends coupled to the contact pads and second ends opposite the first ends, the second ends of the conductive interconnects offset from the active surface by a height of at least 8 micrometers (μm);an encapsulant contacting the four side surfaces of the semiconductor die and further comprising a planar surface disposed over the active surface of the semiconductor die, the planar surface being offset from the active surface by more than the height of the conductive interconnects;openings formed through the planar surface of the encapsulant and extending to the second ends of the conductive interconnects, the openings comprising a depth greater than or equal to 1 μm; anda build-up interconnect layer disposed over the planar surface and extending into the openings to electrically connect ...

CHIP PACKAGE AND METHOD THEREOF

The present invention provides a chip package that includes a semiconductor chip, at least one recess, a plurality of first redistribution metal lines, and at least one protrusion. The semiconductor chip has a plurality of conductive pads disposed on an upper surface of the semiconductor chip. The recess extends from the upper surface to a lower surface of the semiconductor chip, and is arranged on the side of the semiconductor chip. The first redistribution metal lines are disposed on the upper surface, electrically connected to the conductive pad individually, and extended into the recesses separately. The protrusion is disposed in the recess and located between the adjacent first redistribution metal lines. 1. A chip package , comprising:a semiconductor chip having a plurality of conductive pads disposed on an upper surface of the semiconductor chip;at least one recess extended from the upper surface to a lower surface of the semiconductor chip, and arranged on a side of the semiconductor chip;a plurality of first redistribution metal lines disposed on the upper surface, electrically connected to the conductive pads individually, and extended into the recess separately; andat least one protrusion disposed in the recess and located between the adjacent first redistribution metal lines.2. The chip package of claim 1 , further comprising a plurality of second redistribution metal lines disposed on the upper surface claim 1 , the semiconductor chip having a plurality of ground pads disposed on the upper surface claim 1 , and the second redistribution metal lines electrically connected to the ground pads individually claim 1 , and extended into the recess separately.3. The chip package of claim 2 , wherein the second redistribution metal lines are electrically connected to each other in the recess.4. The chip package of claim 1 , further comprising a plurality of third redistribution metal lines disposed on the upper surface claim 1 , extended into the recess ...

Semiconductor device

A semiconductor device suitable for preventing malfunction is provided. The semiconductor device includes a semiconductor chip 1, a first electrode pad 21 laminated on the semiconductor chip 1, an intermediate layer 4 having a rectangular shape defined by first edges 49 a and second edges, and a plurality of bumps 5 arranged to sandwich the intermediate layer 4 by cooperating with the semiconductor chip 1. The first edges 49 a extend in the direction x, whereas the second edges extend in the direction y. The plurality of bumps 5 include a first bump 51 electrically connected to the first electrode pad 21 and a second bump 52 electrically connected to the first electrode pad 21. The first bump 51 is arranged at one end in the direction x and one end in the direction y.

SEMICONDUCTOR STRUCTURE AND FABRICATING METHOD THEREOF

A method of fabricating a semiconductor structure includes: forming a conductive layer on a first insulating layer; etching a portion of the conductive layer to expose a portion of the first insulating layer; deforming a surface of the portion of the first insulating layer to form a rough surface of the first insulating layer; and removing a residue of the conductive layer on the rough surface of the first insulating layer. 1. A method of fabricating a semiconductor structure , comprising:forming a conductive layer on a first insulating layer;etching a portion of the conductive layer to expose a portion of the first insulating layer;deforming a surface of the portion of the first insulating layer to form a rough surface of the first insulating layer; andremoving a residue of the conductive layer from the rough surface of the first insulating layer.2. The method of claim 1 , further comprising:disposing a second insulating layer on the conductive layer and the rough surface of the first insulating layer.3. The method of claim 1 , wherein deforming the surface of the portion of the first insulating layer to form the rough surface of the first insulating layer comprises:performing a first plasma treatment upon the surface of the portion of the first insulating layer to form the rough surface of the first insulating layer.4. The method of claim 3 , wherein the first plasma treatment is an oxygen plasma treatment.5. The method of claim 2 , wherein removing the residue of the conductive layer on the rough surface of the first insulating layer comprises:performing a second plasma treatment upon the rough surface of the first insulating layer surface to remove the residue of the conductive layer; andperforming a third plasma treatment upon the rough surface of the first insulating layer to further remove the residue of the conductive layer after the second plasma treatment; wherein the second plasma treatment is different form the first plasma treatment, and the third ...

Wafer Level UGA (UBM Grid Array) & PGA (Pad Grid Array) for Low Cost Package

A method to fabricate a land grid array wafer level chip scale package is described. A plurality of silicon dies are provided on a wafer. Openings are etched through a dielectric layer to metal pads on the silicon dies. At least one redistribution layer is formed over the dielectric layer and contacting at least one metal pad. A second dielectric layer is deposited on the at least one redistribution layer. An opening is etched through the second dielectric layer to the at least one redistribution layer and a landing pad is formed on the redistribution layer in the opening. The landing pad may be a portion of the redistribution layer exposed by the opening. Alternatively, the landing pad may be an under bump metal (UBM) layer deposited on the exposed redistribution layer and patterned. The landing pad is covered with an oxidation preventing layer.

INTEGRATED FAN-OUT PACKAGE AND MANUFACTURING METHOD THEREOF

An integrated fan-out (InFO) package includes a die, a plurality of conductive structures aside the die, an encapsulant laterally encapsulating the die and the conductive structure, and a redistribution structure. The redistribution structure is disposed on the encapsulant. The redistribution structure includes a plurality of routing patterns, a plurality of conductive vias, and a plurality of alignment marks. The routing patterns and the conductive vias are electrically connected to the die and the conductive structures. The alignment marks surround the routing patterns and the conductive vias. The alignment marks are electrically insulated from the die and the conductive structures. At least one of the alignment marks is in physical contact with the encapsulant, and vertical projections of the alignment marks onto the encapsulant have an offset from one another. 1. An integrated fan-out (InFO) package , comprising:a die;a plurality of conductive structures aside the die;an encapsulant laterally encapsulating the die and the plurality of conductive structures; anda redistribution structure disposed on the encapsulant, wherein the redistribution structure comprises a plurality of routing patterns, a plurality of conductive vias, and a plurality of alignment marks, the plurality of routing patterns and the plurality of conductive vias are electrically connected to the die and the plurality of conductive structures, the plurality of alignment marks surrounds the plurality of routing patterns and the plurality of conductive vias, the plurality of alignment marks is electrically insulated from the die and the plurality of conductive structures, at least one of the plurality of alignment marks is in physical contact with the encapsulant, and vertical projections of the plurality of alignment marks onto the encapsulant have an offset from one another.2. The InFO package according to claim 1 , wherein each of the plurality of alignment marks comprises a grid pattern.3. The ...

Semiconductor package and method of fabricating semiconductor package

A method of fabricating a semiconductor package includes providing a substrate having at least one contact and forming a redistribution layer on the substrate. The formation of the redistribution layer includes forming a dielectric material layer over the substrate and performing a double exposure process to the dielectric material layer. A development process is then performed and a dual damascene opening is formed in the dielectric material layer. A seed metallic layer is formed over the dual damascene opening and over the dielectric material layer. A metal layer is formed over the seed metallic layer. A redistribution pattern is formed in the first dual damascene opening and is electrically connected with the at least one contact.

Semiconductor chip and semiconductor package including the same

A semiconductor package may include a package substrate, a first semiconductor chip on the package substrate, and a second semiconductor chip on the first semiconductor chip. The first semiconductor chip comprises a chip substrate including a first surface and a second surface opposite to the first surface, a plurality of first chip pads between the package substrate and the chip substrate, and electrically connecting the first semiconductor chip to the package substrate, a plurality of second chip pads disposed on the second surface and between the second semiconductor chip and the second surface, and a plurality of redistribution lines on the second surface, the redistribution lines electrically connecting to the second semiconductor chip, and a plurality of bonding wires electrically connecting the redistribution lines to the package substrate.

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

The present disclosure provides a semiconductor device including: a substrate including, in a central portion the substrate, n first element formation regions having a rectangular shape and are arrayed along a first direction, and n+m second element formation regions arrayed along the first direction adjacent to the first element formation regions; plural projecting electrodes formed at each of the first and the second element formation regions; and plural dummy projecting electrodes formed, at a peripheral portion, overlapping a triangle defined by a first edge of the first element formation region that forms a boundary between the first element formation region and the peripheral portion, and a second edge of the second element formation region that is adjacent to a corner of the first edge and that forms a boundary between the second element formation region and the peripheral portion. 1. A semiconductor device comprising:a substrate including, in a central portion of a main face of the substrate, a first element formation region having a rectangular flat plane shape;a plurality of projecting electrodes formed above the first element formation region; anda first row of dummy projecting electrodes arrayed, above a peripheral portion of the main face, along a first edge of the first element formation region that forms a boundary between the first element formation region and the peripheral portion,wherein the first row of dummy projecting electrodes opposes a row of the plurality of projecting electrodes that are arrayed above the first element formation region with the first edge therebetween.2. The semiconductor device of claim 1 , wherein:the first element formation region includes a second edge that touches a corner of the first edge, and that forms a boundary between the first element formation region and the peripheral portion; andthe semiconductor device further comprises a second row of dummy projecting electrodes arrayed above the peripheral portion of the ...

Reliable passivation for integrated circuits

Device and method for forming a device are presented. A substrate having circuit component and a back-end-of-line (BEOL) dielectric layer with interconnects is provided. A pad dielectric layer is formed over the BEOL dielectric layer. The pad dielectric layer includes a pad via opening which exposes a surface of one of the interconnects in the BEOL dielectric layer. A pad interconnect is formed on the pad dielectric layer and the pad interconnect is coupled to one of the interconnect in the BEOL dielectric by a pad via contact in the pad via opening. The pad interconnect comprises a pad interconnect pattern which is devoid of 90° angles and any angled structures contained in the pad interconnect pattern less than 90°. A passivation layer is formed on the substrate. The passivation layer lines the pad interconnect and covers an exposed surface of the pad dielectric layer.

FULLY MOLDED PERIPHERAL PACKAGE ON PACKAGE DEVICE

A method of making a semiconductor device may include providing a carrier comprising a semiconductor die mounting site. A build-up interconnect structure may be formed over the carrier. A first portion of a conductive interconnect may be formed over the build-up interconnect structure in a periphery of the semiconductor die mounting site. An etch stop layer and a second portion of the conductive interconnect may be formed over the first portion of the conductive interconnect. A semiconductor die may be mounted to the build-up interconnect at the semiconductor die mounting site. The conductive interconnect and the semiconductor die may be encapsulated with a mold compound. A first end of the conductive interconnect on the second portion of the conductive interconnect may be exposed. The carrier may be removed to expose the build-up interconnect structure. The first portion of the conductive interconnect may be etched to expose the etch stop layer. 1. A method of making a semiconductor device , comprising:providing a carrier comprising a semiconductor die mounting site;forming a build-up interconnect structure over the carrier;forming a first portion of a conductive interconnect over the build-up interconnect structure in a periphery of the semiconductor die mounting site;forming an etch stop layer over the first portion of the conductive interconnect;forming a second portion of the conductive interconnect over the etch stop layer and over the first portion of the conductive interconnect;mounting a facedown semiconductor die to the build-up interconnect at the semiconductor die mounting site;encapsulating the conductive interconnect and semiconductor die with a mold compound;exposing a first end of the conductive interconnect on the second portion of the conductive interconnect;removing the carrier to expose the build-up interconnect structure; andetching the first portion of the conductive interconnect to expose the etch stop layer.2. The method of claim 1 , wherein ...

Power management application of interconnect substrates

Various applications of interconnect substrates in power management systems are described.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device. 113-. (canceled)14. A method of manufacturing a semiconductor device , comprising the steps of:(a) providing a semiconductor wafer including a plurality of device formation regions, each device formation region having a semiconductor circuit, a pad electrically coupled to the semiconductor circuit, and a first insulating film formed on the pad such that a surface portion of the pad is exposed from the first insulating film at a first opening of the first insulating film;(b) after the step (a), forming a second insulating film on the first insulating film such that the surface portion of the pad is exposed from the second insulating film at a second opening of the second insulating film;(c) after the step (b), bringing a probe needle into contact with the surface potion of the pad; and(d) after the step (c), forming an interconnect layer on the second insulating film, and electrically coupling the interconnect layer to the pad at the surface portion,wherein in the step (b), the second insulating film is formed with application of a heat load to the semiconductor wafer.15. The method according to claim 14 , wherein in the step (a) ...

Package structure and method thereof

A package structure can include: (i) a substrate having opposite first and second surfaces; (ii) a die having opposite active and back surfaces, where the die is arranged above the first surface of the substrate, the back surface of the die is adjacent to the first surface of the substrate; (iii) pads arranged on the active surface of the die; (iv) a first encapsulator configured to encapsulate the die; (v) an interconnection structure configured to electrically connect to the pads through the first encapsulator; (vi) a second encapsulator configured to encapsulate the interconnection structure; and (vii) a redistribution structure configured to electrically connect to the interconnection structure and to provide external electrical connectivity.

DUAL-DAMASCENE ZERO-MISALIGNMENT-VIA PROCESS FOR SEMICONDUCTOR PACKAGING

Techniques that can assist with fabricating a package layer that includes a plurality of dual-damascene zero-misalignment-vias (dual-damascene ZMVs) and a trace between the dual-damascene ZMVs are described. The disclosed techniques allow for the dual-damascene ZMVs and their corresponding trace to be plated simultaneously in a single step or operation. As such, there is little or no misalignment between the dual-damascene ZMVs, the trace, and the metal pads connected to the ZMVs. In this way, one or more of the embodiments described herein can assist with reducing manufacturing costs, reducing development time of fabricating a package layer, and with increasing the I/O density in a semiconductor package. 1. A semiconductor package , comprising:a buildup film, wherein one or more metal pads are disposed in the buildup film; anda plurality of dual-damascene zero misalignment vias (ZMVs) and a trace between the plurality of dual-damascene ZMVs, wherein the plurality of dual-damascene ZMVs and the trace are disposed in the buildup film and wherein the plurality of dual-damascene ZMVs connect with the one or more metal pads in the buildup film.2. The semiconductor package of claim 1 , wherein each of the plurality of dual-damascene ZMVs has a first size in a dimension and the trace has a second size in the dimension and wherein the first size is substantially equal to the second size.3. The semiconductor package of claim 2 , wherein each of the one or more metal pads has a third size and wherein the third size is substantially equal to or greater than the first size.4. The semiconductor package of claim 1 , wherein a sidewall of one of the plurality of dual-damascene ZMVs and a sidewall of the trace are co-planar with each other.5. A semiconductor package claim 1 , comprising:a buildup film, wherein one or more metal pads are formed in the buildup film;a first photoimageable dielectric (PID) layer on the buildup film;a second PID layer on the first PID layer; anda ...

Integrated Circuit Structures And Methods Of Forming An Opening In A Material

In some embodiments, a method of forming an opening in a material comprises forming RIM over target material. Radiation is impinged onto the RIM through a masking tool over a continuous area of the RIM under which a target-material opening will be formed. The masking tool during the impinging allows more radiation there-through onto a mid-portion of the continuous area of the RIM in a vertical cross-section than onto laterally-opposing portions of the continuous area of the RIM that are laterally-outward of the mid-portion of the RIM in the vertical cross-section. After the impinging, the RIM is developed to form a RIM opening that has at least one pair of laterally-opposing ledges laterally-outward of the mid-portion of the RIM in the vertical cross-section elevationally between a top and a bottom of the RIM opening. The developed RIM is used as masking material while etching the target material through the RIM opening to form the target-material opening to have at least one pair of laterally-opposing ledges laterally-outward of a mid-portion in the target-material opening in the vertical cross-section elevationally between a top and a bottom of the target-material opening. Other aspects and constructions independent of manufacture are disclosed. 1. An integrated circuit structure comprising:an insulating material above integrated circuitry, the insulating material having an opening therein that extends elevationally inward to an upper conductive node of the integrated circuitry, the opening having at least one annular ledge elevationally between a top and a bottom of the opening;a conductive line of a redistribution layer (RDL) above the insulating material, the RDL conductive line extending elevationally inward into the opening over the at least one annular ledge and being directly electrically coupled to the upper conductive node;a first insulative material in the opening in the insulating material; anda second insulative material in the opening in the ...

Semiconductor device and method comprising redistribution layers

A method of making a semiconductor package can include placing a single layer dielectric film on a temporary carrier substrate. A plurality of semiconductor die can be placed directly on the first surface of the single layer dielectric film. The single layer dielectric film can be cured to lock the plurality of semiconductor die in place on the single layer dielectric film. The plurality of semiconductor die can be encapsulated while directly on the single layer dielectric film with an encapsulant. The single layer dielectric film can be patterned utilizing a mask-less patterning technique to form a via hole after removing the temporary carrier substrate. A conductive layer can be formed directly on, substantially parallel to, and extending across, the second surface of the patterned single layer dielectric film, within the vial hole, and over the plurality of semiconductor die.

INTEGRATED FAN-OUT PACKAGE AND MANUFACTURING METHOD THEREOF

An integrated fan-out (InFO) package includes an encapsulant, a die, a plurality of conductive structures, and a redistribution structure. The die and the conductive structures are encapsulated by the encapsulant. The conductive structures surround the die. The redistribution structure is disposed on the encapsulant. The redistribution structure includes a plurality of routing patterns, a plurality of conductive vias, and a plurality of alignment marks. The conductive vias interconnects the routing patterns. At least one of the alignment mark is in physical contact with the encapsulant. 1. An integrated fan-out (InFO) package , comprising:an encapsulant;a die and a plurality of conductive structures encapsulated by the encapsulant, wherein the plurality of conductive structures surround the die;a redistribution structure disposed on the encapsulant, wherein the redistribution structure comprises a plurality of routing patterns, a plurality of conductive vias, and a plurality of alignment marks, the plurality of conductive vias interconnect the plurality of routing patterns, at least one of the plurality of alignment marks is in physical contact with the encapsulant, and the plurality of alignment marks are electrically floating.2. The InFO package according to claim 1 , wherein each of the plurality of alignment marks comprises a grid pattern.3. The InFO package according to claim 1 , further comprising a plurality of conductive terminals over the redistribution structure claim 1 , wherein the plurality of conductive terminals are electrically connected to the redistribution structure.4. (canceled)5. The InFO package according to claim 1 , wherein the redistribution structure further comprises a plurality of dielectric layers stacked on each other claim 1 , at least one of the plurality of dielectric layers wraps around the corresponding routing pattern claim 1 , the corresponding conductive via claim 1 , and the corresponding alignment mark claim 1 , and a top ...

Semiconductor structure and fabrication method thereof

A method of forming a semiconductor structure includes the following steps. A dielectric layer is formed over a conductive line. A photoresist layer is formed over the dielectric layer. The photoresist layer is patterned to form a mask feature and an opening is defined by the mask feature. The opening has a bottom portion and a top portion communicated to the bottom portion, and the top portion is wider than the bottom portion. The dielectric layer is etched to form a via hole in the dielectric layer using the mask feature as an etch mask, such that the via hole has a bottom portion and a tapered portion over the bottom portion. The conductive material is filled in the via hole to form a conductive via.

SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME

A semiconductor package structure includes a first semiconductor die, an encapsulant surrounding the first semiconductor die, and a redistribution layer (RDL) electrically coupled to the first semiconductor die. The encapsulant has a first surface over the first semiconductor die and a second surface under the first semiconductor die. The RDL has a first portion under the first surface of the encapsulant and a second portion over the first surface of the encapsulant. 1. A semiconductor package structure , comprising:a first semiconductor die;an encapsulant surrounding the first semiconductor die, the encapsulant having a first surface over the first semiconductor die and a second surface under the first semiconductor die; and a first portion under the first surface of the encapsulant; and', 'a second portion over the first surface of the encapsulant., 'a redistribution layer (RDL) electrically coupled to the first semiconductor die, the RDL comprising2. The semiconductor package structure of claim 1 , wherein the first semiconductor die is disposed under the first surface of the encapsulant.3. The semiconductor package structure of claim 1 , wherein a top surface of the first portion of the RDL is substantially non-coplanar with the first surface of the encapsulant.4. The semiconductor package structure of claim 3 , wherein the top surface of the RDL comprises an upper level over the first surface claim 3 , a lower level under the first surface claim 3 , and a middle level connecting the upper level and the lower level.5. The semiconductor package structure of claim 4 , further comprising a second semiconductor die disposed on lower level of the top surface of the RDL.6. The semiconductor package structure of claim 5 , wherein the second semiconductor die is electrically connected to the first semiconductor die through the RDL.7. The semiconductor package structure of claim 1 , wherein the RDL includes a fan-out structure.8. The semiconductor package structure of ...

SOLID-STATE IMAGE-CAPTURING DEVICE, SEMICONDUCTOR APPARATUS, ELECTRONIC APPARATUS, AND MANUFACTURING METHOD

The present disclosure relates to a solid-state image-capturing device, a semiconductor apparatus, an electronic apparatus, and a manufacturing method that enable improvement in reliability of through electrodes and increase in density of through electrodes. 1. A solid-state image-capturing device , comprising:a plurality of through electrodes electrically connected respectively to a plurality of electrode pads provided on a second main plane side from a first main plane of a semiconductor substrate;a common opening portion formed including a through electrode formation region that is a region in which the plurality of through electrodes is formed;a plurality of through portions formed so as to penetrate to the plurality of respective electrode pads in the common opening portion; andwiring formed from the electrode pads to the first main plane corresponding to the respective through electrodes.2. The solid-state image-capturing device according to claim 1 , whereinthe common opening portion is formed at a depth shallower than a depth from the first main plane to the electrode pad, andthe wiring is formed along the common opening portion and the through portion.3. The solid-state image-capturing device according to claim 1 , whereinthe common opening portion is formed at a depth to the electrode pad from the first main plane,an insulation film is embedded in at least the common opening portion, and the through portion is formed so as to penetrate the insulation film, andthe wiring is formed by being layered on the insulation film.4. The solid-state image-capturing device according to claim 3 , whereinthe insulation film is formed with a recess portion inside the common opening portion so as to include the plurality of through electrodes at a depth shallower than a depth to the electrode pad from the first main plane, andthe through portion is formed so as to penetrate to each of the plurality of electrode pads from a bottom surface of the recess portion.5. The solid- ...

Apparatus and Method for the Minimization of Undercut During a UBM Etch Process

A semiconductor etch process is provided in which an undercut is minimized during an etch process through tight control of etch profile, recognition of etch completion, and minimization of over etch time to increase productivity. 1. A system for endpoint detection of a wet etching process of substrates comprising:a wet etching chamber having a rotatable chuck for receiving and supporting a wafer, the wet etching chamber including an endpoint detection device that is configured to detect an end point of the wet etching process, the endpoint detection device including a high intensity light emitter and a light detector that face the rotatable chuck so that light emitted from the light emitter can illuminate the wafer, wherein a longitudinal axis passing through the endpoint detection device intersects a top plane of the rotatable chuck at an angle other than 90 degrees.2. The system of claim 1 , wherein the wet etching chamber further includes a dome lid claim 1 , the endpoint detection device being mounted to a side wall of the dome lid.3. The system of claim 1 , wherein the high intensity light emitter and the light detector are contained within a single housing.4. The system of claim 1 , wherein at least a substantial portion of the endpoint detection device is located laterally outside of the wafer chuck.5. The system of claim 2 , wherein at least a portion of an underside of the dome lid includes a light blocking panel that is positioned so as to minimize light reflections within an interior of the chamber and provide a more uniform lighting therein.6. The system of claim 5 , wherein the light blocking panel is disposed above the wafer chuck and is white colored.7. The system of claim 2 , wherein the light detection device is positioned so that light reflections off of the wafer are reflected onto the underside of the dome lid.8. The system of claim 1 , wherein the light emitter comprises a high intensity LED and the light detector comprise one of a CMOS detector ...

Integrated structure and method for fabricating the same

A method for fabricating integrated structure is disclosed. The method includes the steps of: providing a substrate; forming a through-silicon hole in the substrate; forming a patterned resist on the substrate, wherein the patterned resist comprises at least one opening corresponding to a redistribution layer (RDL) pattern and exposing the through-silicon hole and at least another opening corresponding to another redistribution layer (RDL) pattern and connecting to the at least one opening; and forming a conductive layer to fill the through-silicon hole, the at least one opening and the at least another opening in the patterned resist so as to form a through-silicon via, a through-silicon via RDL pattern and another RDL pattern in one structure.

SEMICONDUCTOR DEVICE HAVING A DUAL MATERIAL REDISTRIBUTION LINE

A semiconductor device includes a first conductive element electrically connected to an interconnect structure, wherein the first conductive element includes a first conductive material. The semiconductor device further includes an RDL over the first conductive element and electrically connected to the first conductive element, wherein the RDL includes a second conductive material different from the first conductive material. The semiconductor device further includes a passivation layer over the RDL, wherein a top portion of a sidewall of the second passivation layer includes a convex curve protruding in a direction parallel to a top surface of the interconnect structure, a width of the top portion at a bottom of the convex curve is less than a width of the top portion at a middle of the convex curve, and the middle of the convex curve is above the bottom of the convex curve. 1. A semiconductor device comprising:a first conductive element electrically connects to an interconnect structure, wherein the first conductive element comprises a first conductive material;an RDL over the first conductive element and electrically connected to the first conductive element, wherein the RDL comprises a second conductive material different from the first conductive material; anda passivation layer over the RDL, wherein a top portion of a sidewall of the passivation layer includes a convex curve protruding in a direction parallel to a top surface of the interconnect structure, a width of the top portion at a bottom of the convex curve is less than a width of the top portion at a middle of the convex curve, and the middle of the convex curve is above the bottom of the convex curve.2. The semiconductor device of claim 1 , wherein the first conductive element comprises copper.3. The semiconductor device of claim 2 , wherein the RDL comprises aluminum.4. The semiconductor device of claim 2 , wherein an entirety of the passivation layer over a top surface of the RDL via has a planar ...

Metal-Bump Sidewall Protection

A method includes forming a metal bump on a top surface of a first package component, forming a solder region on a top surface of the metal bump, forming a protection layer extending on a sidewall of the metal bump, reflowing the solder region to bond the first package component to a second package component, and dispensing an underfill between the first package component and the second package component. The underfill is in contact with the protection layer.

電子デバイス、および、電子デバイスの製造方法