Leistungshalbleiterchip und Verfahren zur Herstellung eines Leistungshalbleiterchips und Leistungshalbleitereinrichtung

Leistungshalbleiterchip mit einem Halbleiterbauelementkörper (2) und mit einer auf dem Halbleiterbauelementkörper (2) angeordneten mehrschichtigen Metallisierung (10), die eine über dem Halbleiterbauelementkörper (2) angeordnete Nickelschicht (6) aufweist, wobei die Metallisierung (10) eine auf dem Halbleiterbauelementkörper (2) angeordnete, Aluminium aufweisende erste Metallschicht (3) aufweist, wobei die Nickelschicht (6) über der ersten Metallschicht (3) angeordnet ist, wobei die Metallisierung (10) eine zweite Metallschicht (4), die als Chromschicht ausgebildet ist und eine auf der zweiten Metallschicht (4) angeordnete Zwischenschicht (13), die aus Nickel besteht und eine auf der Zwischenschicht (13) angeordnete dritte Metallschicht (5), die als Silberschicht ausgebildet ist, aufweist, wobei die zweite Metallschicht (4) auf der ersten Metallschicht (3) angeordnet ist, wobei die Nickelschicht (6) auf der dritten Metallschicht (5) angeordnet ist, wobei die Nickelschicht (6) eine Dicke ...

Semiconductor device comprising a chip substrate, a mold, and a buffer layer

A semiconductor device and a method of manufacturing the semiconductor device are disclosed. The semiconductor device includes a chip substrate, a mold, and a buffer layer. The mold is disposed over the chip substrate. The buffer layer is externally embedded between the chip substrate and the mold. The buffer layer has an elastic modulus or a coefficient of thermal expansion less than that of the mold. The method includes disposing a buffer layer at least covering scribe lines of a substrate, forming a mold over the substrate and covering the buffer layer, and cutting along the scribe lines and through the mold, the buffer layer and the substrate.

NON-DESTRUCTIVE TESTING OF INTEGRATED CIRCUIT CHIPS

Semiconductor devices and electronics packaging methods include integrated circuit chips having redundant signal bond pads along with signal bond pads connected to the same signal port for non-destructive testing of the integrated circuit chips prior to packaging. Electrical testing is made via the redundant signal bond after which qualified integrated circuit chips can be attached to a pristine and bumped final interposer or printed circuit board to provide increased reliability to the assembled electronic package.

HETERO-INTEGRATED STRUCTURE AND MEHOD OF FABRICATING THE SAME

A hetero-integrated structure includes a substrate, a die, a passivation layer, a first redistribution layer, a second redistribution layer, and connecting portions. The die is attached on the substrate. The die has an active surface and a non-active surface. The active surface has pads. The passivation layer covers sidewalls and a surface of the die to expose a surface of the pads. The first redistribution layer is located on the passivation layer and electrically connected to the pads. The second redistribution layer is located on the substrate and adjacent to the die. The connecting portions are connected to the first redistribution layer and the second redistribution layer.

Halbleiterbauelemente und Verfahren zur Herstellung von Halbleiterbauelementen

Bauelement, umfassend:ein Halbleitermaterial (1), das eine erste Hauptoberfläche (2), eine gegenüberliegende Oberfläche (3), die der ersten Hauptoberfläche gegenüberliegt, und eine seitliche Oberfläche (4), die sich von der ersten Hauptoberfläche zur gegenüberliegenden Oberfläche erstreckt, umfasst, wobei das Halbleitermaterial eine Funktionsfläche umfasst, die in einem Hochfrequenzbereich betrieben wird;ein erstes elektrisches Kontaktelement (5), das auf der ersten Hauptoberfläche (2) des Halbleitermaterials angeordnet ist;ein Glasmaterial (6), das eine zweite Hauptoberfläche (7) umfasst, wobei das Glasmaterial die seitliche Oberfläche (4) des Halbleitermaterials kontaktiert und wobei die erste Hauptoberfläche (2) des Halbleitermaterials und die zweite Hauptoberfläche des Glasmaterials in einer gemeinsamen Ebene angeordnet sind; undeine Metallschicht (11), die über der ersten Hauptoberfläche (2) des Halbleitermaterials und über dem Glasmaterial angeordnet ist, wobei eine passive elektronische ...

Semiconductor device

The invention relates to a semiconductor device. The top surface of a semiconductor substrate is provided with at least one bonding pad. A passivation layer is located on the top surface of the semiconductor substrate. At least one opening located within the passivation layer exposes the bonding pad. A metal layer is stacked on the bonding pad.

Chip having metal pillar structure

The present invention relates to a chip having metal pillar structure. The chip includes a chip body, at least one chip pad, a first passivation layer, an under ball metal layer and at least one metal pillar structure. The chip body has an active surface. The chip pad is disposed on the active surface. The first passivation layer is disposed on the active surface, and has at least one first opening so as to expose part of the chip pad. The under ball metal layer is disposed on the chip pad. The metal pillar structure is disposed on the under ball metal layer, and includes a metal pillar and a solder. The metal pillar is disposed on the under ball metal layer. The solder is disposed on the metal pillar, and the diameter of the solder is smaller than or equals to that of the metal pillar. Therefore, when the pitch between two metal pillar structures of the chip is fine pitch, the problem of solder bridge can be avoided, so that the yield rate is raised.

NON-DESTRUCTIVE TESTING OF INTEGRATED CIRCUIT CHIPS

Semiconductor devices and electronics packaging methods include integrated circuit chips having redundant signal bond pads along with signal bond pads connected to the same signal port for non-destructive testing of the integrated circuit chips prior to packaging. Electrical testing is made via the redundant signal bond after which qualified integrated circuit chips can be attached to a pristine and bumped final interposer or printed circuit board to provide increased reliability to the assembled electronic package.

Solder ball fabricating process

A solder ball fabricating process for forming solder balls over a wafer having an active layer is provided. A patterned solder mask layer is formed over the active surface of the wafer. The patterned solder mask layer has an opening that exposes a bonding pad on the wafer. Solder material is deposited into the opening over the bonding pad. A reflow process is conducted to form a pre-solder body. The aforementioned steps are repeated so that various solder materials are fused together to form a solder ball over the bonding pad.

HALBLEITERVORRICHTUNG MIT METALLISIERUNGSSTRUKTUR UND HERSTELLUNGSVERFAHREN FÜR DIESE

Eine Halbleitervorrichtung (100) beinhaltet ein Halbleitersubstrat (110) mit einer ersten Seite (101) und einer zweiten Seite (102) und wenigstens ein Dotierungsgebiet (111, 112), das an der ersten Seite (101) des Halbleitersubstrats (110) gebildet ist. Die Halbleitervorrichtung (100) beinhaltet ferner eine erste Metallisierungsstruktur (120) an der ersten Seite (101) des Halbleitersubstrats (110) und auf und in Kontakt mit dem wenigstens einen Dotierungsgebiet (111, 112) und eine zweite Metallisierungsstruktur (130) an der zweiten Seite (102) des Halbleitersubstrats (110). Die zweite Metallisierungsstruktur (130) bildet ein Silicidgrenzflächengebiet (135) mit dem Halbleitersubstrat (110) und ein Nichtsilicidgrenzflächengebiet (136) mit dem Halbleitersubstrat (110).

반도체 장치

... 반도체 장치가 제공된다. 반도체 장치는 기판, 기판 상에 배치되는 보호막으로, 보호막을 관통하는 트렌치를 포함하는 보호막, 트렌치의 적어도 일부를 채우는 제1 부분과, 보호막 상에 배치되는 제2 부분을 포함하는 하부 범프 및 하부 범프 상에 배치되는 상부 범프를 포함하고, 보호막은, 트렌치의 측벽을 포함하는 제1 부분 및 제2 부분을 포함하고, 기판의 상면으로부터 상기 보호막의 제1 부분의 상면까지의 제1 높이는, 기판의 상면으로부터 상기 보호막의 제2 부분의 상면까지의 제2 높이보다 크다.

Silicon Carbide Device and Method for Forming a Silicon Carbide Device

A silicon carbide device includes a silicon carbide substrate, a contact layer including nickel, silicon and aluminum, a barrier layer structure including titanium and tungsten, and a metallization layer including copper. The contact layer is located on the silicon carbide substrate. The contact layer is located between the silicon carbide substrate and at least a part of the barrier layer structure. The barrier layer structure is located between the silicon carbide substrate and the metallization layer.

Semiconductor Device with Metallization Structure and Method for Manufacturing Thereof

A semiconductor device includes a semiconductor substrate with a first side and a second side, and at least one doping region formed at the first side of the semiconductor substrate. The semiconductor device further includes a first metallization structure at the first side of the semiconductor substrate and on and in contact with the at least one doping region, and a second metallization structure at the second side of the semiconductor substrate. The second metallization structure forms a silicide interface region with the semiconductor substrate and a non-silicide interface region with the semiconductor substrate.

CHIP-SCALE PACKAGE

A semiconductor device such as a chip-scale package is provided. Aspects of the present disclosure further relate to a method for manufacturing such a device. According to an aspect of the present disclosure, a semiconductor device is provided that includes a conformal coating arranged on its sidewalls and on the perimeter part of the semiconductor die of the semiconductor device. To prevent the conformal coating from covering unwanted areas, such as electrical terminals, a sacrificial layer is arranged prior to arranging the conformal coating. By removing the sacrificial layer, the conformal coating can be removed locally. The conformal coating covers the perimeter part of the semiconductor die by the semiconductor device, in which part a remainder of a sawing line or dicing street is provided.

CHIPGEHÄUSE UND VERFAHREN ZUR HERSTELLUNG EINES CHIPGEHÄUSES

Es wird ein Verfahren zur Herstellung eines Chipgehäuses bereitgestellt, wobei das Verfahren folgende Schritte aufweist: Bilden (210) einer Schichtanordnung über einem Träger, Anordnen (220) eines Chips, einschließlich einer oder mehrerer Kontaktstellen, über der Schichtanordnung, wobei der Chip zumindest einen Teil der Schichtanordnung bedeckt, und selektives Entfernen (230) eines oder mehrerer Abschnitte der Schichtanordnung und Verwenden des Chips als Maske, so dass zumindest ein Teil der Schichtanordnung, der vom Chip nicht bedeckt ist, nicht entfernt wird.

Halbleiterchip und Leistungsmodul und dessen Herstellungsverfahren

Ein Halbleiter-Chip enthält ein Halbleitersubstrat aus SiC, eine Stirnflächenelektrode, die an einer Hauptfläche des Halbleitersubstrats ausgebildet ist, und eine Rückflächenelektrode (eine Drain-Elektrode), die an einer Rückfläche des Halbleitersubstrats ausgebildet ist. Die Stirnflächenelektrode ist an einen Draht gebondet und enthält einen Al-Legierungs-Film, der ein Metall mit hohem Schmelzpunkt enthält. Der Al-Legierungs-Film enthält einen säulenförmigen Al-Kristall, der sich entlang einer Dickenrichtung des Al-Legierungs-Films erstreckt, wobei darin eine intermetallische Verbindung abgeschieden ist.

Processing of Thick Metal Pads

Fabricating method of light emitting device

... 색 온도를 조절할 수 있는 발광 장치의 제조 방법이 제공된다. 상기 발광 장치의 제조 방법은 기판 상에 다수의 발광 유닛을 형성하고, 다수의 발광 유닛 각각의 광특성을 측정하고, 다수의 발광 유닛 상에 프린트 방식을 이용하여 형광체를 도포하되, 각 발광 유닛 상에 도포되는 형광체는 상기 측정된 상기 각 발광 유닛의 광특성에 따라 조절되고, 상기 기판을 절삭하여, 상기 형광체가 도포된 다수의 발광 유닛을 유닛별로 분리하는 것을 포함한다.

WAFER-LEVEL PACKAGE INCLUDING UNDER BUMP METAL LAYER

A semiconductor package includes a semiconductor chip comprising a first surface and a second surface, a redistribution layer on the first surface of the semiconductor chip, an under bump metal (UBM) layer on the redistribution layer, and a solder bump on the UBM layer, and the solder bump covers both outer side surfaces of the UBM layer.

SEMICONDUCTOR DEVICE HAVING SOLDER JOINT AND FORMING METHOD THEREOF

The present invention relates to a semiconductor device having a high-reliability solder joint. A high-temperature solder is formed on a conductive pad. A low-temperature solder having a lower melting point than the high-temperature solder is formed on the high-temperature solder. A barrier layer is formed between the high-temperature solder and the low-temperature solder. A Sn content of the high-temperature solder is higher than a Sn content of the low-temperature solder. COPYRIGHT KIPO 2016 ...

SOLDER BUMP COUPLING WITHIN A CHIP SCALE PACKAGE WHICH INCLUDES A NON-CONDUCTIVE LAYER

PURPOSE: A solder bump coupling within a chip scale package is provided to improve reliability by preventing the generation of cracks of a solder bump. CONSTITUTION: A semiconductor substrate(150) comprises one or more semiconductor devices. An UBM layer(140) is formed on the semiconductor device. A non-conductive layer(130) comprises a cross-section portion which defines a protrusion(132) at the top of a recess within the UBM layer. The protrusion is aligned along interface(142) between the UBM layer and the non-conductive layer. A solder bump(160) is coupled to the UBM layer through an opening(134) within the non-conductive layer. The solder bump comprises a part arranged between the protrusions. COPYRIGHT KIPO 2013 ...

Integrated circuit system with stress redistribution layer and method of manufacture thereof

Chip having a metal pillar structure

The present invention relates to a chip having a metal pillar structure. The chip includes a chip body, at least one chip pad, a first passivation layer, an under ball metal layer and at least one metal pillar structure. The chip body has an active surface. The chip pad is disposed on the active surface. The first passivation layer is disposed on the active surface, and has at least one first opening so as to expose part of the chip pad. The under ball metal layer is disposed on the chip pad. The metal pillar structure is disposed on the under ball metal layer, and includes a metal pillar and a solder. The metal pillar is disposed on the under ball metal layer. The solder is disposed on the metal pillar, and the maximum diameter formed by the solder is shorter than or equal to the diameter of the metal pillar. Therefore, when the pitch between two adjacent metal pillar structures of the chip is a fine pitch, the defect of solder bridge can be avoided, so that the yield rate is improved.

Halbleiterbauelemente und Verfahren zur Herstellung von Halbleiterbauelementen

Ein Bauelement enthält ein Halbleitermaterial, das eine erste Hauptoberfläche, eine gegenüberliegende Oberfläche, die der ersten Hauptoberfläche gegenüberliegt, und eine seitliche Oberfläche, die sich von der ersten Hauptoberfläche bis zur gegenüberliegenden Oberfläche erstreckt, aufweist. Das Bauelement enthält weiterhin ein erstes elektrisches Kontaktelement, das auf der ersten Hauptoberfläche des Halbleitermaterials angeordnet ist, und ein Glasmaterial. Das Glasmaterial enthält eine zweite Hauptoberfläche, wobei das Glasmaterial die seitliche Oberfläche des Halbleitermaterials kontaktiert und wobei die erste Hauptoberfläche des Halbleitermaterials und die zweite Hauptoberfläche des Glasmaterials in einer gemeinsamen Ebene angeordnet sind.

BONDING STRUCTURE FOR SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

The present disclosure relates to bonding structures useful in semiconductor packages and methods of manufacturing the same. In an embodiment, the bonding structure comprises a substrate, having a top surface and including at least one bonding pad, wherein each bonding pad is disposed adjacent to the top surface of the substrate and has a sloped surface; and a semiconductor element including at least one pillar, wherein each pillar is bonded to a portion of the sloped surface of a corresponding bonding pad, and a gap is formed between a sidewall of the pillar and the sloped surface of the corresponding bonding pad.

FIN PITCH AND HIGH ASPECT RATIO WIRING STRUCTURE AND INTERCONNECTION METHOD FOR THE SAME

PROBLEM TO BE SOLVED: To provide a metal structure of an IC having patterned metallization protected by two or more contact pads and coating layers. SOLUTION: The structure 300 has a plurality of windows 301a on a coating film 303, 306 to selectively expose the metalization 301 of a chip. These windows are separated by 150 μm or less from center to center. A metal column 308 is disposed on each window. The suitable metal is copper and the column has an upper surface made wettable with the metal which can be reflow soldered and with height and width aspect ratio of larger than 1.25. The suitable height and width aspect ratio of the column is between 2.0-4.0, and it can operate to absorb the thermal mechanical stress. A metal cap 309 which can be reflow soldered is disposed on each column. This metal structure is used to attach an IC chip to an outer part 311. COPYRIGHT: (C)2004,JPO ...

Bearbeiten von dicken Metallpads

Verfahren zum Bilden eines Halbleiterbauteils, wobei das Verfahren Folgendes aufweist:Bereitstellen eines Halbleitersubstrats (10), das einen ersten Chipbereich und einen zweiten Chipbereich aufweist;Bilden eines ersten Kontaktpads (50, 51) über dem ersten Chipbereich und eines zweiten Kontaktpads (50, 51) über dem zweiten Chipbereich, wobei das erste und das zweite Kontaktpad (50, 51) mindestens so dick sind wie das Halbleitersubstrat (10);Die-Vereinzeln durch das Halbleitersubstrat (10) zwischen dem ersten und dem zweiten Kontaktpad (50, 51) hindurch, wobei das Die-Vereinzeln von einer Seite des Halbleitersubstrats (10) aus erfolgt, die das erste Kontaktpad (50, 51) und das zweite Kontaktpad (50, 51) aufweist; undBilden eines leitfähigen Liners (60) über dem ersten und dem zweiten Kontaktpad (50, 51) und den Seitenwänden des Halbleitersubstrats (10), die durch das Die-Vereinzeln freigelegt werden.

SEMICONDUCTOR DEVICE AND METHOD OF FORMING MICRO INTERCONNECT STRUCTURES

A semiconductor device has a first semiconductor die and second semiconductor die with a conductive layer formed over the first semiconductor die and second semiconductor die. The second semiconductor die is disposed adjacent to the first semiconductor die with a side surface and the conductive layer of the first semiconductor die contacting a side surface and the conductive layer of the second semiconductor die. An interconnect, such as a conductive material, is formed across a junction between the conductive layers of the first and second semiconductor die. The conductive layer may extend down the side surface of the first semiconductor die and further down the side surface of the second semiconductor die. An extension of the side surface of the first semiconductor die can interlock with a recess of the side surface of the second semiconductor die. The conductive layer extends over the extension and into the recess.

Semiconductor chip and power module, and manufacturing method of the same

A semiconductor chip includes a semiconductor substrate made of SiC, a front surface electrode formed in a principal surface of the semiconductor substrate, and a rear surface electrode (drain electrode) formed in a rear surface of the semiconductor substrate. The front surface electrode is bonded to a wire, and includes an Al alloy film containing a high melting-point metal. The Al alloy film contains a columnar Al crystal which extends along a thickness direction of the Al alloy film, and an intermetallic compound is precipitated therein.

Method of fabricating cylindrical bonding structure

A cylindrical bonding structure and its method of manufacture. The cylindrical bonding structure is formed over the bonding pad of a silicon chip and the chip is flipped over to connect with a substrate board in the process of forming a flip-chip package. The cylindrical bonding structure mainly includes a conductive pillar and a solder cap. The conductive pillar is formed over the bonding pad of the silicon chip and the solder cap is attached to the upper end of the conductive pillar. The solder cap has a melting point lower than the conductive pillar. The solder cap can be configured into a cylindrical, spherical or hemispherical shape. To fabricate the cylindrical bonding structure, a patterned mask layer having a plurality of openings that correspond in position to the bonding pads on the wafer is formed over a silicon wafer. Conductive material is deposited into the openings to form conductive pillars and finally a solder cap is attached to the end of each conductive pillar.

Photoresist cleaning composition used in photolithography and a method for treating substrate therewith

Solder ball process

There is provided a solder ball process suitable for forming solder balls on the pads of a wafer, which comprises first forming a patterned solder mask layer on the active surface of the wafer so that the opening of the solder mask layer exposes the pad of the wafer; next, filling solder in the opening and piling up solder on the pad; then performing a refolw process to make the solder form a pre-solder and repeating the above steps to melt the solder thereby forming solder balls on the pads.

Stacked semiconductor device structure and method

A method of forming stacked semiconductor device structure includes providing a first semiconductor device and a second semiconductor device. The first semiconductor device includes a recessed region bounded by sidewall portions and a conductive layer disposed adjoining at least portions of the recessed region. The method includes electrically connecting the second semiconductor device to the conductive layer within the recessed region such that at least a portion of the second semiconductor device is disposed within the recessed region.

Rod soldering structure and manufacturing process thereof

The present invention relates to a rod solder structure and manufacturing process thereof, wherein the rod soldering structure is deployed on a pad of a chip, and during a flip-chip package process, chip can be connected with a substrate by means of the rod soldering structure. In addition, the rod soldering structure mainly includes one conducting rod and one solder block, in which the conducting rod is disposed on the pad of the chip, while the solder block is disposed on the conducting rod. The melting point of the solder block is lower than that of the conducting rod, and the contour of solder block could be rod-shaped, spherical, hemispherical, or the like. Moreover, the manufacturing process of the rod soldering structure includes steps of preparing a patterned mask layer on a wafer such that an opening of mask layer is located on the solder pad of the wafer, filling a conductive material in the opening by electroplating to form the conducting rod, and in subsequent process forming ...

Semiconductor device

Semiconductor package structure, semiconductor device and method for manufacturing the same

A semiconductor package structure includes a substrate, at least one first semiconductor element, a heat dissipation structure and an insulation layer. The at least one first semiconductor element is attached to the substrate, and has a first surface and a second surface opposite to the first surface. The first surface of the at least one first semiconductor element faces the substrate. The heat dissipation structure is disposed on the second surface of the at least one first semiconductor element. The insulation layer is disposed on the heat dissipation structure, and defines a plurality of openings extending through the insulation layer and exposing a plurality of exposed portions of the heat dissipation structure.

Integrated circuit system with stress redistribution layer and method of manufacture thereof

Method of Forming an Interconnection between an Electric Component and an Electronic Component

A method of forming an interconnection includes: providing an electronic component having a first main face and a first metallic layer disposed on the first main face; providing an electric component having a second main face and a second metallic layer disposed on the second main face, at least one of the first or second metallic layers including an oxide layer provided on a main face thereof; disposing a reducing agent on one or both of the electronic component and the electric component such that the reducing agent is enabled to remove the oxide layer; and connecting the electronic component to the electric component by directly connecting the first metallic layer of the electronic component with the second metallic layer of the electric component by applying pressure and heat.

Cylindrical bonding structure and method of manufacture

A cylindrical bonding structure and its method of manufacture. The cylindrical bonding structure is formed over the bonding pad of a silicon chip and the chip is flipped over to connect with a substrate board in the process of forming a flip-chip package. The cylindrical bonding structure mainly includes a conductive cylinder and a solder block. The conductive cylinder is formed over the bonding pad of the silicon chip and the solder block is attached to the upper end of the conductive cylinder. The solder block has a melting point lower than the conductive cylinder. The solder block can be configured into a cylindrical, spherical or hemispherical shape. To fabricate the cylindrical bonding structure, a patterned mask layer having a plurality of openings that correspond in position to the bonding pads on the wafer is formed over a silicon wafer. Conductive material is deposited into the openings to form conductive cylinders and finally a solder block is attached to the end of each conductive ...

Glass carrier with embedded semiconductor device and metal layers on the top surface

A device includes a semiconductor material having a first main surface, an opposite surface opposite to the first main surface and a side surface extending from the first main surface to the opposite surface. The device further includes a first electrical contact element arranged on the first main surface of the semiconductor material and a glass material. The glass material includes a second main surface wherein the glass material contacts the side surface of the semiconductor material and wherein the first main surface of the semiconductor material and the second main surface of the glass material are arranged in a common plane.

CHIP PACKAGE AND METHOD FOR FORMING THE SAME

A chip package includes: a substrate; a drain and a source regions located in the substrate; a gate located on or buried in the substrate; a drain conducting structure, a source conducting structure, and a gate conducting structure, disposed on the substrate and electrically connected to the drain region, the source region, and the gate, respectively; a second substrate disposed beside the substrate; a second drain and a second source region located in the second substrate, wherein the second drain region is electrically connected to the source region; a second gate located on or buried in the second substrate; and a second source and a second gate conducting structure disposed on the second substrate and electrically connected to the second source region and the second gate, respectively, wherein terminal points of the drain, the source, the gate, the second source, and the second gate conducting structures are substantially coplanar.

RECONSTITUTED INTERPOSER SEMICONDUCTOR PACKAGE

本发明涉及重构的插入式半导体封装件。本发明描述了重构的半导体封装件以及制造该重构的半导体封装件的方法。在载体上形成晶圆附着基板的阵列。将半导体装置安装到每个所述晶圆附着基板的第一表面上。将插入基板安装在每个半导体装置上。插入基板电连接至相应的晶圆附着基板的第一表面。将模塑料填充在所述插入基板内和之间的空间中，以形成重构的半导体封装件的阵列，所述插入基板被安装至它们相应的所述晶圆附着基板。电气连接件安装至所述晶圆附着基板的第二表面。分离重构的半导体封装件的阵列穿过在每个晶圆附着基板之间和在相应的被安装的插入基板之间的模塑料。

포토리소그래피에 사용되는 포토레지스트 세정 조성물 및 이로 기판을 처리하는 방법

... (a) 4차 암모늄 하이드록사이드, (b) 수용성 유기 용매의 혼합물, (c) 적어도 하나의 부식 억제제, 및 (d) 물을 함유하는, 3-150 ㎛의 막 두께를 갖는 포토레지스트 패턴을 스트립핑하기 위한 포토레지스트 세정 조성물, 및 이로 기판을 처리하는 방법이 개시된다.

Wafer structure with a buffer layer

The invention relates to a wafer structure with a buffer layer. The wafer structure comprises a wafer which has at least a pad formed thereon, a passivation layer formed on the wafer and partially expose the pad, a buffer layer formed on the passivation layer and the pad, and an under bump metallurgy (UBM) layer formed on the buffer layer. The buffer layer includes a thickness-increased inner buffering member made of aluminum based material located between the UBM layer and the pad to enhance the shock-absorbing ability in a drop test and to avoid conductive bumps joined to a substrate dropping and cracking. The invention can also enhances the joining ability between the conductive bumps and the under bump metallurgy(UBM). The buffer layer may further comprise a polyimide-made outer buffering member coated on the passivation layer and partially arranged between the UMB layer and the passivation layer.

Chip package and method for forming the same

A chip package includes a substrate; a drain region and a source region located in the substrate; a gate located on or buried in the substrate; a drain conducting structure, a source conducting structure, and a gate conducting structure disposed on the substrate and electrically connected to the drain region, the source region, and the gate, respectively; a second substrate disposed beside the substrate; a second drain region and a second source region located in the second substrate, the second drain region electrically connected to the source region; a second gate located on or buried in the second substrate; and a second source conducting structure and a second gate conducting structure disposed on the second substrate and electrically connected to the second source region and the second gate, respectively, wherein terminal points of the drain conducting structure, the source conducting structure, the gate conducting structure, the second source conducting structure, and the second gate ...

Power semiconductor device, method of manufacturing the device and bonding wire

It is an object of the present invention to provide a power semiconductor device, which is capable of being operable regardless of thermal stress generation, reducing a heat generation from wire, securing the reliability of bonding portion when the device is used for dealing with a large amount current and/or under a high temperature atmosphere, a method of manufacturing the device and a bonding wire. A power semiconductor device in which a metal electrode (die electrode 3) on a power semiconductor die 2 and another metal electrode (connection electrode 4) are connected by metal wire 5 using wedge bonding connection, wherein the metal wire is Ag or Ag alloy wire of which diameter is greater than 50 mgr; m and not greater than 2mm and the die 3 has thereon one or more metal and/or alloy layers, each of the layer(s) being 50 or more in thickness and a metal for the layer is selected from Ni, Cr, Cu, Pd, V, Ti, Pt, Zn, Ag, Au, W and Al.

Method for fabricating circuit component

A cylindrical bonding structure and its method of manufacture. The cylindrical bonding structure is formed over the bonding pad of a silicon chip and the chip is flipped over to connect with a substrate board in the process of forming a flip-chip package. The cylindrical bonding structure mainly includes a conductive pillar and a solder cap. The conductive pillar is formed over the bonding pad of the silicon chip and the solder cap is attached to the upper end of the conductive pillar. The solder cap has a melting point lower than the conductive pillar. The solder cap can be configured into a cylindrical, spherical or hemispherical shape. To fabricate the cylindrical bonding structure, a patterned mask layer having a plurality of openings that correspond in position to the bonding pads on the wafer is formed over a silicon wafer. Conductive material is deposited into the openings to form conductive pillars and finally a solder cap is attached to the end of each conductive pillar.

Semiconductor device and semiconductor package

The present disclosure relates to bonding structures useful in semiconductor packages. In an embodiment, a semiconductor device includes a semiconductor element, two pillar structures, and an insulation layer. The semiconductor element has a surface and includes at least one bonding pad disposed adjacent to the surface. The two pillar structures are disposed on a single bonding pad. The insulation layer is disposed adjacent to the surface of the semiconductor element. The insulation layer defines an opening, the opening exposes a portion of the single bonding pad, and the two pillar structures are disposed in the opening.

Leistungshalbleiterchip und Verfahren zur Herstellung eines Leistungshalbleiterchips und Leistungshalbleitereinrichtung

Die Erfindung betrifft einen Leistungshalbleiterchip mit einem Halbleiterbauelementkörper (2) und mit einer auf dem Halbleiterbauelementkörper (2) angeordneten mehrschichtigen Metallisierung (10), die eine über dem Halbleiterbauelementkörper (2) angeordnete Nickelschicht (6) aufweist. Weiterhin betrifft die Erfindung ein Verfahren zur Herstellung eines Leistungshalbleiterchips (1). Weiterhin betrifft die Erfindung eine Leistungshalbleitereinrichtung. Die Erfindung schafft einen Leistungshalbleiterchip (1), der eine Metallisierung (10) aufweist, an die ein ohne eine dicke metallische Beschichtung versehener Kupferdraht (11) zuverlässig gebondet werden kann, ohne dass beim Bonden der Leistungshalbleiterchip (1) beschädigt wird.

METHOD FOR FORMING A CONNECTION TERMINAL INCLUDING A SOLDER UNIT AND A SOLDER UNIT SUPPORTER

PURPOSE: A method for forming a connection terminal including a solder unit and a solder unit supporter is provided to efficiently reduce an external impact by changing the propagation direction of a crack. CONSTITUTION: A substrate with a UBM(Under Bump Metallurgy)(116) is prepared. A solder unit(141) comprised of a lower side of a cylindrical shape and an upper side of a sphere shape is formed. The lower side is combined with the UBM. A solder unit supporter(130) is formed on the substrate and surrounds the lower side. The solder unit supporter is arranged on the UBM. COPYRIGHT KIPO 2010 ...

Semiconductor devices and methods of manufacturing the same

A semiconductor package includes a first semiconductor component, a second semiconductor component, and a connecting element. The first semiconductor component includes a first substrate, and a first bonding pad disposed adjacent to a first surface of the first substrate, and at least one conductive via structure extending from a second surface of the first substrate to the first bonding pad. The second semiconductor component includes a second substrate, a redistribution layer disposed adjacent to a first surface of the second substrate, and a second bonding pad disposed on the redistribution layer. The connecting element is disposed between the first bonding pad and the second bonding pad.

Wafer-level method for fine-pitch, high aspect ratio chip interconnect

A metal structure 300 for an integrated circuit having a plurality of contact pads and a patterned metallization 301 protected by an overcoat layer 303,306. The structure comprises a plurality of windows in the overcoat, selectively exposing the chip metallization, wherein the windows are spaced apart by less than 150 µm center to center. A metal column 308 is positioned on each of the windows; the preferred metal is copper; the column has a height-to-width aspect ratio larger than 1.25 and an upper surface wettable by re-flowable metal. The preferred column height-to-width aspect ratio is between 2.0 and 4.0, operable to absorb thermomechanical stress. A cap of a re-flowable metal 309 is positioned on each of the columns. The metal structure is used for attaching the IC chip to an external part 311.

Verfahren zur Herstellung einer Verbindung und Anordnung für eine Chipzusammenstellung mit Direktverbindung

Verschiedene Ausführungsformen schaffen ein Verfahren zum Herstellen einer Verbindung zwischen einer elektrischen Komponente und einer elektronischen Komponente, wobei das Verfahren Folgendes umfasst: das Bilden einer ersten Verbindungsteilschicht auf einer elektrischen Komponente, wobei die erste Verbindungsteilschicht ein Metall umfasst und eine der elektrischen Komponente gegenüberliegende Hauptoberfläche aufweist, wobei der Hauptoberfläche eine erste Oberflächenrauheit hat; das Bilden einer zweiten Verbindungsteilschicht auf einer elektronischen Komponente, wobei die zweite Verbindungsteilschicht das Metall umfasst und eine der elektronischen Komponente gegenüberliegende Oberfläche aufweist, wobei die Oberfläche eine zweite Oberflächenrauheit hat, wobei die erste Oberflächenrauheit und die zweite Oberflächenrauheit in der gleichen Größenordnung liegen; und das Verbinden der ersten Verbindungsteilschicht und der zweiten Verbindungsteilschicht durch Inkontaktbringen derselben und Anwenden ...

Semiconductor device and semiconductor package

A semiconductor device and a semiconductor package comprising the same are provided. The semiconductor device includes a semiconductor element; a protective layer disposed adjacent to the surface of the semiconductor element, the protective layer defining an opening to expose the semiconductor element; a first bump disposed on the semiconductor element; and a second bump disposed onto the surface of the protective layer. The first bump has larger cross-section surface area than the second bump.

Heterogeneous integrated assembly structure and method of fabricating the same

A heterogeneous integrated assembly structure includes a substrate, a die, a passivation layer, a first redistribution layer, a second redistribution layer, and a connection. A die is attached on the substrate. The die has an active surface and a non-active surface. The active surface has pads formed thereon. A passivation layer covers the sidewalls and surfaces of the die and exposes a surface of the pad. The first redistribution layer is disposed on the passivation layer and electrically connected to the pads. The second redistribution layer is disposed on the substrate adjacent to the die. The connection portion connects the first redistribution layer and the second redistribution layer.

Semiconductor device and method of aligning semiconductor wafers for bonding

A semiconductor device has a first semiconductor wafer. The first semiconductor wafer is singulated to provide a first wafer section including at least one first semiconductor die or a plurality of first semiconductor die. The first wafer section is a fractional portion of the first semiconductor wafer. An edge support structure is formed around the first wafer section. A second wafer section includes at least one second semiconductor die. The second wafer section can be an entire second semiconductor wafer. The first semiconductor die is a first type of semiconductor device and the second semiconductor die is a second type of semiconductor device. An alignment opening is formed through the first wafer section and second wafer section with a light source projected through the opening. The first wafer section is bonded to the second wafer section with the first semiconductor die aligned with the second semiconductor die.

Semiconductor component and assumbly with projecting electrode

A semiconductor component has a substrate and a projecting electrode on the substrate. The projecting electrode is configured suitably for electrically and mechanically connecting the semiconductor component to an external substrate. Furthermore, the projecting electrode is formed by a one-dimensional or two-dimensional array of projecting sub-electrodes, which are separated from each other by an electrically insulating fluid beginning from a substrate surface. The semiconductor component has an improved projecting-electrode. It provides the projecting electrode with a sub-structure, which achieves sufficient flexibility without introducing much constructive complexity and processing complexity during fabrication.

Silicon carbide device and method for forming a silicon carbide device

A silicon carbide device includes a silicon carbide substrate, a contact layer including nickel, silicon and aluminum, a barrier layer structure including titanium and tungsten, and a metallization layer including copper. The contact layer is located on the silicon carbide substrate. The contact layer is located between the silicon carbide substrate and at least a part of the barrier layer structure. The barrier layer structure is located between the silicon carbide substrate and the metallization layer.

Bonding pad on ic substrate and method for making the same

CHIP PACKAGE ASSEMBLY WITH ENHANCED INTERCONNECTS AND METHOD FOR FABRICATING THE SAME

An integrated circuit interconnects are described herein that are suitable for forming integrated circuit chip packages. In one example, an integrated circuit interconnect is embodied in a wafer that includes a substrate having a plurality of integrated circuit (IC) dice formed thereon. The plurality of IC dice include a first IC die having first solid state circuitry and a second IC die having second solid state circuitry. A first contact pad is disposed on the substrate and is coupled to the first solid state circuitry. A first solder ball is disposed on the first contact pad. The first solder ball has a substantially uniform oxide coating formed thereon.

Semiconductor Module and Method for Production Thereof

This invention relates to a module including a semiconductor chip, at least two contact elements and an insulating material between the two contact elements. Furthermore, the invention relates to a method for production of such a module.

SEMICONDUCTOR DEVICE AND METHOD OF FORMING A CURVED IMAGE SENSOR

A semiconductor device has a semiconductor die containing a base material having a first surface and a second surface with an image sensor area. A masking layer with varying width openings is disposed over the first surface of the base material. The openings in the masking layer are larger in a center region of the semiconductor die and smaller toward edges of the semiconductor die. A portion of the first surface of the base material is removed by plasma etching to form a first curved surface. A metal layer is formed over the first curved surface of the base material. The semiconductor die is positioned over a substrate with the first curved surface oriented toward the substrate. Pressure and temperature is applied to assert movement of the base material to change orientation of the second surface with the image sensor area into a second curved surface.

Bonding pad on IC substrate and method for making the same

A bonding pad structure is fabricated on an integrated circuit (IC) substrate having at least a contact layer on its top surface. A passivation layer covers the top surface of the IC substrate and the contact layer. The passivation layer has an opening exposing a portion of the contact layer. An electrically conductive adhesion/barrier layer directly is bonded to the contact layer. The electrically conductive adhesion/barrier layer extends to a top surface of the passivation layer. A bonding metal layer is stacked on the electrically conductive adhesion/barrier layer.

Package of electronic device with bump buffer spring pad and method for manufacturing the same

Power semiconductor device, method of manufacturing the device and bonding wire

It is an object of the present invention to provide a power semiconductor device, which is capable of being operable regardless of thermal stress generation, reducing a heat generation from wire, securing the reliability of bonding portion when the device is used for dealing with a large amount current and/or under a high temperature atmosphere, a method of manufacturing the device and a bonding wire. In a power semiconductor device in which a metal electrode (die electrode 3) on a power semiconductor die 2 and another metal electrode (connection electrode 4) are connected by metal wire 5 using wedge bonding connection, the metal wire is Ag or Ag alloy wire of which diameter is greater than 50 m and not greater than 2 mm and the die 3 has thereon one or more metal and/or alloy layers, each of the layer(s) being 50 or more in thickness and a metal for the layer is selected from Ni, Cr, Cu, Pd, V, Ti, Pt, Zn, Ag, Au, W and Al.

Wafer Level Semiconductor Package

There are disclosed herein various implementations of improved wafer level semiconductor packages. One exemplary implementation comprises forming a post-fabrication redistribution layer (post-Fab RDL) between first and second dielectric layers affixed over a surface of a wafer, and forming a window for receiving an electrical contact body in the second dielectric layer, the window exposing the post-Fab RDL. At least one of the first and second dielectric layers is a pre-formed dielectric layer, which may be affixed over the surface of the wafer using a lamination process. In one implementation, the window is formed using a direct laser ablation process.

Semiconductor device and method of forming micro interconnect structures

A semiconductor device has a first semiconductor die and second semiconductor die with a conductive layer formed over the first semiconductor die and second semiconductor die. The second semiconductor die is disposed adjacent to the first semiconductor die with a side surface and the conductive layer of the first semiconductor die contacting a side surface and the conductive layer of the second semiconductor die. An interconnect, such as a conductive material, is formed across a junction between the conductive layers of the first and second semiconductor die. The conductive layer may extend down the side surface of the first semiconductor die and further down the side surface of the second semiconductor die. An extension of the side surface of the first semiconductor die can interlock with a recess of the side surface of the second semiconductor die. The conductive layer extends over the extension and into the recess.

Power semiconductor chip, method for producing a power semiconductor chip, and power semiconductor device

A power semiconductor chip having: a semiconductor component body; a multilayer metallization arranged on the semiconductor component body; and a nickel layer arranged over the semiconductor component body. The invention further relates to a method for producing a power semiconductor chip and to a power semiconductor device. The invention provides a power semiconductor chip which has a metallization to which a copper wire, provided without a thick metallic coating, can be reliably bonded without damage to the power semiconductor chip during bonding.

Semiconductor device and method of forming cantilevered protrusion on a semiconductor die

A semiconductor device has a first semiconductor die with a base material. A covering layer is formed over a surface of the base material. The covering layer can be made of an insulating material or metal. A trench is formed in the surface of the base material. The covering layer extends into the trench to provide the cantilevered protrusion of the covering layer. A portion of the base material is removed by plasma etching to form a cantilevered protrusion extending beyond an edge of the base material. The cantilevered protrusion can be formed by removing the base material to the covering layer, or the cantilevered protrusion can be formed within the base material under the covering layer. A second semiconductor die is disposed partially under the cantilevered protrusion. An interconnect structure is formed between the cantilevered protrusion and second semiconductor die.

Methods for forming pillar bumps on semiconductor wafers

The subject matter contained herein discloses methods for forming a vertical metallic pillar overlying an under bump metal pad further overlying a semiconductor substrate, and applying a discrete solder cap on a top surface of the pillar, wherein the metallic pillar is defined by at least one photoresist layer. The method includes heating a multi-element metallic paste containing a variable amount of metallic powder, a melting point depressant and a flux such that the metal powder sinters to form the metallic pillar and simultaneously adheres the metallic pillar to the underbump metal pad.

Cylindrical bonding structure and method of manufacture

A cylindrical bonding structure and its method of manufacture. The cylindrical bonding structure is formed over the bonding pad of a silicon chip and the chip is flipped over to connect with a substrate board in the process of forming a flip-chip package. The cylindrical bonding structure mainly includes a conductive cylinder and a solder block. The conductive cylinder is formed over the bonding pad of the silicon chip and the solder block is attached to the upper end of the conductive cylinder. The solder block has a melting point lower than the conductive cylinder. The solder block can be configured into a cylindrical, spherical or hemispherical shape. To fabricate the cylindrical bonding structure, a patterned mask layer having a plurality of openings that correspond in position to the bonding pads on the wafer is formed over a silicon wafer. Conductive material is deposited into the openings to form conductive cylinders and finally a solder block is attached to the end of each conductive ...

반도체 디바이스 및 반도체 디바이스를 제조하는 방법

반도체 디바이스 및 반도체 디바이스를 제조하는 방법이 개시된다. 반도체 디바이스는 칩 기판, 몰드 및 버퍼 층을 포함한다. 몰드는 칩 기판 위에 배치된다. 버퍼 층은 칩 기판과 몰드 사이에 외부적으로 임베디드된다. 버퍼 층은 몰드의 탄성률 또는 열 팽창 계수보다 작은 탄성률 또는 열 팽창 계수를 갖는다. 방법은 적어도 기판의 스크라이브 라인들을 커버하는 버퍼 층을 배치하는 단계, 기판 위에 몰드를 형성하며 버퍼 층을 커버하는 단계, 및 스크라이브 라인들을 따라 그리고 몰드, 버퍼 층 및 기판을 통해 컷팅하는 단계를 포함한다.

METAL PAD OR METAL BUMP OVER PAD EXPOSED BY PASSIVATION LAYER

A circuitry component comprising a semiconductor substrate, a pad over said semiconductor substrate, a tantalum-containing layer on a side wall and a bottom surface of said pad, a passivation layer over said semiconductor substrate, an opening in said passivation layer exposing said pad, a titanium-containing layer over said pad exposed by said opening, and a gold layer over said titanium-containing layer. Figure no. 11 is suggested for publication.

SEMICONDUCTOR DEVICE AND METHOD OF FORMING A CURVED IMAGE SENSOR

A semiconductor device has a semiconductor die containing a base material having a first surface and a second surface with an image sensor area. A masking layer with varying width openings is disposed over the first surface of the base material. The openings in the masking layer are larger in a center region of the semiconductor die and smaller toward edges of the semiconductor die. A portion of the first surface of the base material is removed by plasma etching to form a first curved surface. A metal layer is formed over the first curved surface of the base material. The semiconductor die is positioned over a substrate with the first curved surface oriented toward the substrate. Pressure and temperature is applied to assert movement of the base material to change orientation of the second surface with the image sensor area into a second curved surface.

Silicon Carbide Device and Method for Forming a Silicon Carbide Device

A silicon carbide device includes a silicon carbide substrate, a contact layer located on the silicon carbide substrate and including nickel and silicon, a barrier layer structure including titanium and tungsten, and a metallization layer comprising copper, wherein the contact layer is located between the silicon carbide substrate and at least a part of the barrier layer structure, wherein the barrier layer structure is located between the silicon carbide substrate and the metallization layer, wherein the metallization layer is configured as a contact pad of the silicon carbide device.

반도체 디바이스 및 반도체 디바이스를 제조하는 방법

... 반도체 디바이스 및 반도체 디바이스를 제조하는 방법이 개시된다. 반도체 디바이스는 칩 기판, 몰드 및 버퍼 층을 포함한다. 몰드는 칩 기판 위에 배치된다. 버퍼 층은 칩 기판과 몰드 사이에 외부적으로 임베디드된다. 버퍼 층은 몰드의 탄성률 또는 열 팽창 계수보다 작은 탄성률 또는 열 팽창 계수를 갖는다. 방법은 적어도 기판의 스크라이브 라인들을 커버하는 버퍼 층을 배치하는 단계, 기판 위에 몰드를 형성하며 버퍼 층을 커버하는 단계, 및 스크라이브 라인들을 따라 그리고 몰드, 버퍼 층 및 기판을 통해 컷팅하는 단계를 포함한다.

Photoresist cleaning composition used in photolithography and a method for treating substrate therewith

It is disclosed a photoresist cleaning composition for stripping a photoresist pattern having a film thickness of 3-150 μm, which contains (a) quaternary ammonium hydroxide (b) a mixture of water-soluble organic solvents (c) at least one corrosion inhibitor and (d) water, and a method for treating a substrate therewith.

VERFAHREN ZUR HERSTELLUNG EINES CHIPGEHÄUSES

Verfahren (200) zur Herstellung eines Chipgehäuses, welches folgende Schritte aufweist: • Bilden (210) einer Schichtanordnung über einem Träger, wobei das Bilden (210) einer Schichtanordnung über dem Träger folgende Schritte aufweist: – Aufbringen einer Barriereschicht über dem Träger und – Aufbringen einer Opferschicht über der Barriereschicht. • Anordnen (220) eines Chips einschließlich einer oder mehrerer Kontaktstellen, über der Schichtanordnung, wobei der Chip zumindest einen Teil der Schichtanordnung bedeckt, und • selektives Entfernen (230) eines oder mehrerer Abschnitte der Schichtanordnung und Verwenden des Chips als Maske, so dass zumindest ein Teil der Schichtanordnung, der vom Chip bedeckt ist, nicht entfernt wird.

Semiconductor device

WAFER AND SEMICONDUCTOR PACKAGE

A wafer defines a plurality of chips arranged in array manner. Each chip includes at least one aluminum pad and a middle material. The middle material covers the aluminum pad and is mounted on the aluminum pad.

Improved high temperature resistant backside metallization for compound semiconductors

Method of manufacturing a semiconductor device having reduced on-state resistance and structure

A semiconductor device includes a singulated region of semiconductor material having a first major surface and a second major surface opposite to the first major surface. In one embodiment, the second major surface includes a recessed surface portion bounded by opposing sidewall portions extending outward from the region of semiconductor material in cross-sectional view. The sidewall portions have outer surfaces defining peripheral edge segments of the singulated region of semiconductor material. An active device region is disposed adjacent to the first major surface and a first conductive layer is disposed adjoining the recessed surface portion. The recessed surface portion provides a semiconductor device having improved electrical characteristics, and the sidewall portions provide a semiconductor device that is less susceptible to warpage, breakage, and other reliability issues.

Electronic device packages including bump buffer spring pads and methods of manufacturing the same

Electronic device packages and related methods are provided. The electronic device package includes a first substrate having a first contact portion disposed thereon, a bump having a first contact surface connected to the first contact portion and a second contact surface disposed opposite to the first contact surface, and a buffer spring pad portion between the first contact portion of the first substrate and the first contact surface of the bump. The buffer spring pad portion includes at least two different conductive material layers which are stacked.

Methods of fabricating a light-emitting device

Methods of fabricating of a light-emitting device are provided, the methods include forming a plurality of light-emitting units on a substrate, measuring light characteristics of the plurality of light-emitting units, respectively, depositing a phosphor layer on the plurality of light-emitting units using a printing method, and cutting the substrate to separate the plurality of light-emitting units into unit by unit. The phosphor layer is adjustably deposited according to the measured light characteristics of the plurality of light-emitting units.

SEMICONDUCTOR PACKAGE STRUCTURE, SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor package structure includes a substrate, at least one first semiconductor element, a heat dissipation structure and an insulation layer. The at least one first semiconductor element is attached to the substrate, and has a first surface and a second surface opposite to the first surface. The first surface of the at least one first semiconductor element faces the substrate. The heat dissipation structure is disposed on the second surface of the at least one first semiconductor element. The insulation layer is disposed on the heat dissipation structure, and defines a plurality of openings extending through the insulation layer and exposing a plurality of exposed portions of the heat dissipation structure.

Halbleitermodul und Verfahren zu seiner Herstellung

Diese Erfindung betrifft ein Modul, das einen Halbleiterchip (10), mindestens zwei Kontaktelemente (13, 14) und ein Isoliermaterial (16) zwischen den zwei Kontaktelementen (13, 14) enthält. Des Weiteren betrifft die Erfindung ein Verfahren zur Herstellung eines solchen Moduls.

For photolithography in the photoresist cleaning composition and its use for substrate processing method

STACKED SEMICONDUCTOR DEVICE STRUCTURE AND METHOD

A method of forming stacked semiconductor device structure includes providing a first semiconductor device and a second semiconductor device. The first semiconductor device includes a recessed region bounded by sidewall portions and a conductive layer disposed adjoining at least portions of the recessed region. The method includes electrically connecting the second semiconductor device to the conductive layer within the recessed region such that at least a portion of the second semiconductor device is disposed within the recessed region.

Semiconductor device and die bonding structure thereof

An embodiment of the present invention relates to a semiconductor device and a die bonding structure thereof. The purpose of the present invention is to provide the semiconductor device and the die bonding structure thereof, which improve electrical conductivity and mechanical properties by not forming a compound between a semiconductor die or a lead frame and metal, improve wetting properties, and reduce aggregation. To achieve this, the semiconductor device comprises a semiconductor die; a barrier layer formed on the surface of the semiconductor die; a first metal layer formed on the barrier layer; a central metal layer formed on the first metal layer; and a second metal layer formed on the central metal layer, wherein the first and second metal layers have a first melting temperature, and the central metal layer has a second melting temperature lower than the first melting temperature.

Metallization with tailorable coefficient of thermal expansion

The present invention is directed to an interconnect for an implantable medical device. The interconnect includes a pad and a first layer introduced over the pad. At least one of the pad or the first layer comprise a negative coefficient of thermal expansion (CTE) material.

Wafer-level package device having solder bump assemblies that include an inner pillar structure

Wafer-level package (semiconductor) devices are described that have a pillar structure that extends at least partially into a solder bump to mitigate thermal stresses to the solder bump. In implementations, the wafer-level package device may comprise an integrated circuit chip having a surface and a solder bump disposed over the surface. The wafer-level package device may also include a pillar structure disposed over the surface that extends at least partially into the solder bump.

Methods of fabricating a light-emitting device

Methods of fabricating of a light-emitting device are provided, the methods include forming a plurality of light-emitting units on a substrate, measuring light characteristics of the plurality of light-emitting units, respectively, depositing a phosphor layer on the plurality of light-emitting units using a printing method, and cutting the substrate to separate the plurality of light-emitting units into unit by unit. The phosphor layer is adjustably deposited according to the measured light characteristics of the plurality of light-emitting units.

Method for manufacturing a chip package

A method for manufacturing a chip package is provided, the method including: forming a layer arrangement over a carrier; arranging a chip including one or more contact pads over the layer arrangement wherein the chip covers at least part of the layer arrangement; and selectively removing one or more portions of the layer arrangement and using the chip as a mask such that at least part of the layer arrangement covered by the chip is not removed.

Photoresist Cleaning Composition Used in Photolithography and a Method for Treating Substrate Therewith

It is disclosed a photoresist cleaning composition for stripping a photoresist pattern having a film thickness of 3-150 μm, which contains (a) quaternary ammonium hydroxide (b) a mixture of water-soluble organic solvents (c) at least one corrosion inhibitor and (d) water, and a method for treating a substrate therewith.

SEMICONDUCTOR CHIP WITH PATTERNED UNDERBUMP METALLIZATION AND POLYMER FILM

Various semiconductor chip solder bump and underbump metallization (UBM) structures and methods of making the same are disclosed. In one aspect, a method is provided that includes forming a first underbump metallization layer on a semiconductor chip is provided. The first underbump metallization layer has a hub, a first portion extending laterally from the hub, and a spoke connecting the hub to the first portion. A polymer layer is applied to the first underbump metallization layer. The polymer layer includes a first opening in alignment with the hub and a second opening in alignment with the spoke. A portion of the spoke is removed via the second opening to sever the connection between the hub and the first portion.

METHOD OF FORMING CONNECTION TERMINAL

A method of forming a connection terminal may include preparing a substrate, forming a first conductor of a tube shape having an opened upper portion on the substrate, forming a second conductor on the first conductor, and annealing the second conductor so that a portion of the second conductor extends in an internal space of the first conductor through the opened upper portion.

Bearbeiten von dicken Metallpads

In einer Ausführungsform der vorliegenden Erfindung umfasst ein Verfahren zum Bilden eines Halbleiterbauteils das Bereitstellen eines Halbleitersubstrats (10) mit einem ersten Chipbereich und einem zweiten Chipbereich. Ein erstes Kontaktpad (50, 51) wird über dem ersten Chipbereich gebildet, und ein zweites Kontaktpad (50, 51) wird über dem zweiten Chipbereich gebildet. Das erste und das zweite Kontaktpad (50, 51) sind mindestens so dick wie das Halbleitersubstrat (10). Das Verfahren umfasst weiterhin das Die-Vereinzeln des Halbleitersubstrats (10) zwischen dem ersten und dem zweiten Kontaktpad (50, 51). Das Die-Vereinzeln erfolgt von einer Seite des Halbleitersubstrats (10) aus, die das erste Kontaktpad (50, 51) und das zweite Kontaktpad (50, 51) aufweist. Über dem ersten und dem zweiten Kontaktpad (50, 51) und den Seitenwänden des Halbleitersubstrats (10), die durch das Die-Vereinzeln freigelegt werden, wird ein leitfähiger Liner (60) gebildet.

범프 버퍼 스프링패드부를 포함하는 전자 소자의 패키지 및 제조 방법

... 접촉부가 형성된 기판, 접촉부에 연결될 접촉면을 가지는 범프(bump) 및 접촉부 표면과 범프의 접촉면 사이 계면에 도입되어 범프에 유발되는 응력이 접촉부 및 기판으로 전달되는 것을 완화하도록 이종 도전층들이 적층된 버퍼 스프링패드부(buffering spring pad)를 포함하는 전자 소자의 패키지 및 제조 방법을 제시한다.

INTEGRATED CIRCUIT SYSTEM WITH STRESSREDISTRIBUTION LAYER AND METHOD OFMANUFACTURE THEREOF

INTEGRATED CIRCUIT SYSTEM WITH STRESS REDISTRIBUTION LAYER AND METHOD OF MANUFACTURE THEREOFA method of manufacture of an integrated circuit system includes: providing a substrate having a transistor and a metallization layer; forming a metal pad in direct contact with the metallization layer of the substrate; forming a passivation layer in direct contact with the metal pad and covering the substrate; forming a routing trace above the passivation layer in direct contact with the metal pad, and the routing trace is substantially larger than the metal pad, and the routing trace is not electrically insulated by a subsequent layer; and forming a bump connected to the metal pad with the routing trace.(Fig. 2) ...

POWER SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SAME, AND BONDING WIRE

The present invention addresses the issue of providing: a power semiconductor device, which can be used without a problem even if heat stress is generated, and which is capable of reducing heat generated by a wire, and is capable of ensuring reliability of a bonding section even under high-temperature environments, at the time when the current capacity of the power semiconductor device is increased and the power semiconductor device is used under high-temperature environments; a method for manufacturing the power semiconductor device; and a bonding wire. In a power semiconductor device (1), a metal electrode (element electrode (3)) and the other metal electrode (connecting electrode (4)), which are on a power semiconductor element (2), are both wedge-connected by means of a metal wire (5). The metal wire (5) is an Ag wire or an Ag alloy wire having a diameter larger than 50 μm but equal to or smaller than 2 mm, and the element electrode (3) has, on the surface thereof, one or more metal layers or alloy layers, each of which has a thickness of 50 Å or more, said metal layers being composed of a metal selected from among Ni, Cr, Cu, Pd, V, Ti, Pt, Zn, Ag, Au, W, and Al, and said alloy layers being composed of metals selected from among such metals. Consequently, irrespective of the fact that the Ag wire is used, reliability of a bonding section to the electrode can be ensured, heat generated by the metal wire can be reduced when a large current is used, and heat resistance at a high temperature is improved.

Wafer Level Semiconductor Package

There are disclosed herein various implementations of improved wafer level semiconductor packages. One exemplary implementation comprises forming a post-fabrication redistribution layer (post-Fab RDL) between first and second dielectric layers affixed over a surface of a wafer, and forming a window for receiving an electrical contact body in the second dielectric layer, the window exposing the post-Fab RDL. At least one of the first and second dielectric layers is a pre-formed dielectric layer, which may be affixed over the surface of the wafer using a lamination process. In one implementation, the window is formed using a direct laser ablation process.

SEMICONDUCTOR DEVICES

A semiconductor device includes a substrate, a protection layer on the substrate that includes a trench that penetrates therethrough, a lower bump that includes a first part that fills at least a portion of the trench and a second part on the protection layer; and an upper bump on the lower bump. The protection layer includes a first part that surrounds the trench and a second part that surrounds the first part. A first height from an upper surface of the substrate to an upper surface of the first part of the protection layer is greater than a second height from the upper surface of the substrate to an upper surface of the second part of the protection layer. 1. A semiconductor device , comprising:a substrate;a protection layer on the substrate, the protection layer including a trench that penetrates therethrough;a lower bump that includes a first part that fills at least a portion of the trench and a second part on the protection layer, wherein an upper surface of the first art of the lower bump is curved downward toward the substrate; andan upper bump on the lower bump,wherein the protection layer includes a first part that surrounds the trench and a second part that surrounds the first part, anda first height from an upper surface of the substrate to an upper surface of the first part of the protection layer is greater than a second height from the upper surface of the substrate to an upper surface of the second part of the protection layer.2. The semiconductor device according to claim 1 , wherein the lower bump includes a recess claim 1 , andthe upper bump includes a first part in the recess and a second part on the first part.3. The semiconductor device according to claim 1 , wherein an upper surface of the first part of the lower bump includes a second point spaced apart by a first distance from a first point on a sidewall of the trench in a first direction parallel to the upper surface of the substrate and a third point spaced apart by a second distance from ...

BONDING STRUCTURE FOR SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

A method of manufacturing a bonding structure includes (a) providing a substrate, wherein the substrate includes a top surface and at least one bonding pad disposed adjacent to the top surface of the substrate, at least one bonding pad having a sloped surface with a first slope; (b) providing a semiconductor element, wherein the semiconductor element includes at least one pillar, and at least one pillar has a sidewall with a second slope, wherein the absolute value of the first slope is smaller than the absolute value of the second slope; and (c) bonding at least one pillar to a portion of the sloped surface of corresponding ones of the at least one bonding pad. 1. A method of manufacturing a bonding structure , comprising:(a) providing a substrate, wherein the substrate includes a top surface and at least one bonding pad disposed adjacent to the top surface of the substrate, at least one bonding pad having a sloped surface with a first slope;(b) providing a semiconductor element, wherein the semiconductor element includes at least one pillar, and at least one pillar has a sidewall with a second slope, wherein the absolute value of the first slope is smaller than the absolute value of the second slope; and(c) bonding at least one pillar to a portion of the sloped surface of corresponding ones of the at least one bonding pad.2. The method of claim 1 , wherein in (a) claim 1 , a space defined by the sloped surface of at least one bonding pad has a maximum width and a minimum width claim 1 , and in (b) claim 1 , a width of a corresponding one of the at least one pillar is greater than the minimum width of the space and less than the maximum width of the space.3. The method of claim 1 , wherein in (c) claim 1 , a gap is formed between the sidewall of the at least one pillar and the sloped surface of a corresponding bonding pad.4. The method of claim 1 , wherein in (b) claim 1 , at least one pillar further has a top surface and an edge portion claim 1 , wherein the edge ...

Semiconductor device and semiconductor package

The present disclosure relates to bonding structures useful in semiconductor packages. In an embodiment, a semiconductor device includes a semiconductor element, two pillar structures, and an insulation layer. The semiconductor element has a surface and includes at least one bonding pad disposed adjacent to the surface. The two pillar structures are disposed on a single bonding pad. The insulation layer is disposed adjacent to the surface of the semiconductor element. The insulation layer defines an opening, the opening exposes a portion of the single bonding pad, and the two pillar structures are disposed in the opening.

Semiconductor device and method of forming micro interconnect structures

A semiconductor device has a first semiconductor die and second semiconductor die with a conductive layer formed over the first semiconductor die and second semiconductor die. The second semiconductor die is disposed adjacent to the first semiconductor die with a side surface and the conductive layer of the first semiconductor die contacting a side surface and the conductive layer of the second semiconductor die. An interconnect, such as a conductive material, is formed across a junction between the conductive layers of the first and second semiconductor die. The conductive layer may extend down the side surface of the first semiconductor die and further down the side surface of the second semiconductor die. An extension of the side surface of the first semiconductor die can interlock with a recess of the side surface of the second semiconductor die. The conductive layer extends over the extension and into the recess.

Semiconductor device and method of forming cantilevered protrusion on a semiconductor die

A semiconductor device has a first semiconductor die with a base material. A covering layer is formed over a surface of the base material. The covering layer can be made of an insulating material or metal. A trench is formed in the surface of the base material. The covering layer extends into the trench to provide the cantilevered protrusion of the covering layer. A portion of the base material is removed by plasma etching to form a cantilevered protrusion extending beyond an edge of the base material. The cantilevered protrusion can be formed by removing the base material to the covering layer, or the cantilevered protrusion can be formed within the base material under the covering layer. A second semiconductor die is disposed partially under the cantilevered protrusion. An interconnect structure is formed between the cantilevered protrusion and second semiconductor die.

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

A method of manufacturing a semiconductor device includes forming a first metal film on a first insulating region and a first metal region directly adjacent to the first insulating region, wherein the first metal film comprises a metal other than the metal of the first metal region, forming a second metal film on a second insulating region and a second metal region directly adjacent to the second insulating region, wherein the second metal film comprises a metal other than the metal of the second metal region, bringing the first metal film and the second metal film into contact with each other, and heat treating the first substrate and the second substrate and thereby electrically connecting the first metal region and the second metal region to each other and simultaneously forming an insulating interface film between the first insulating region and the second insulating region. 1. A method of manufacturing a semiconductor device comprising:providing a first substrate comprising a first surface including a first insulating region and at least one first metal region directly adjacent to the first insulating region;forming a first metal film on the first insulating region and the first metal region, wherein the first metal film comprises a metal other than the metal of the first metal region;providing a second substrate comprising a second surface including a second insulating region and at least one second metal region directly adjacent to the second insulating region;forming a second metal film on the second insulating region and the second metal region, wherein the second metal film comprises a metal other than the metal of the second metal region;bringing the first metal film and the second metal film into contact with each other so that the first surface of the first substrate faces the second surface of the second substrate; andheat treating the first substrate and the second substrate and thereby electrically connecting the first metal region and the second ...

Silicon Carbide Device and Method for Forming a Silicon Carbide Device

A power semiconductor device includes a semiconductor substrate having a wide bandgap semiconductor material and a first surface, an insulation layer above the first surface of the semiconductor substrate, the insulation layer including at least one opening extending through the insulation layer in a vertical direction, a front metallization above the insulation layer with the insulation layer being interposed between the front metallization and the first surface of the semiconductor substrate, and a metal connection arranged in the opening of the insulation layer and electrically conductively connecting the front metallization with the semiconductor substrate; wherein the front metallization includes at least one layer that is a metal or a metal alloy having a higher melting temperature than an intrinsic temperature of the wide bandgap semiconductor material of the semiconductor substrate. 1. A power semiconductor device , comprising:a semiconductor substrate comprising a wide bandgap semiconductor material and a first surface;an insulation layer above the first surface of the semiconductor substrate, the insulation layer comprising at least one opening extending through the insulation layer in a vertical direction;a front metallization above the insulation layer with the insulation layer being interposed between the front metallization and the first surface of the semiconductor substrate; anda metal connection arranged in the opening of the insulation layer and electrically conductively connecting the front metallization with the semiconductor substrate;wherein the front metallization comprises at least one layer that is a metal or a metal alloy having a higher melting temperature than an intrinsic temperature of the wide bandgap semiconductor material of the semiconductor substrate.2. The power semiconductor device of claim 1 , wherein the intrinsic temperature of the wide bandgap semiconductor material of the semiconductor substrate is at least 600° C.3. The ...

Power Semiconductor Chip, Method for Producing a Power Semiconductor Chip, and Power Semiconductor Device

A power semiconductor chip having: a semiconductor component body; a multilayer metallization arranged on the semiconductor component body; and a nickel layer arranged over the semiconductor component body. The invention further relates to a method for producing a power semiconductor chip and to a power semiconductor device. The invention provides a power semiconductor chip which has a metallization to which a copper wire, provided without a thick metallic coating, can be reliably bonded without damage to the power semiconductor chip during bonding.

RECONSTITUTED INTERPOSER SEMICONDUCTOR PACKAGE

A reconstituted semiconductor package and a method of making a reconstituted semiconductor package are described. An array of die-attach substrates is formed onto a carrier. A semiconductor device is mounted onto a first surface of each of the die-attach substrates. An interposer substrate is mounted over each of the semiconductor devices. The interposer substrates are electrically connected to the first surface of the respective die-attach substrates. A molding compound is filled in open spaces within and between the interposer substrates mounted to their respective die-attach substrates to form an array of reconstituted semiconductor packages. Electrical connections are mounted to a second surface of the die-attach substrates. The array of reconstituted semiconductor packages is singulated through the molding compound between each of the die-attach substrates and respective mounted interposer substrates. 1. A reconstituted interposer package comprising:an interposer substrate electrically mounted to a first surface of a reconstituted die-attach substrate and straddling an integrated circuit mounted on the first surface of the reconstituted die-attach substrate;a molding compound filled within open spaces between the interposer substrate and the first surface of the reconstituted die-attach substrate, wherein singulated surfaces of the molding compound reside along edges of the interposer substrate and the reconstituted die-attach substrate; andexternal electrical connections formed in a grid array on a second surface of the reconstituted die-attach substrate.2. The reconstituted interposer package of claim 1 , wherein one or more of the reconstituted interposer packages are assembled into one of a baseband microprocessor claim 1 , a set-top-box microprocessor claim 1 , a server message block microprocessor claim 1 , or an encryption/security microprocessor.3. The reconstituted semiconductor package of claim 1 , wherein the molding compound covers side walls of the ...

POWER SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE DEVICE AND BONDING WIRE

It is an object of the present invention to provide a power semiconductor device, which is capable of being operable regardless of thermal stress generation, reducing a heat generation from wire, securing the reliability of bonding portion when the device is used for dealing with a large amount current and/or under a high temperature atmosphere, a method of manufacturing the device and a bonding wire. In a power semiconductor device in which a metal electrode (die electrode ) on a power semiconductor die and another metal electrode (connection electrode ) are connected by metal wire using wedge bonding connection, the metal wire is Ag or Ag alloy wire of which diameter is greater than 50 μm and not greater than 2 mm and the die has thereon one or more metal and/or alloy layers, each of the layer(s) being 50 Å or more in thickness and a metal for the layer is selected from Ni, Cr, Cu, Pd, V, Ti, Pt, Zn, Ag, Au, W and Al. 2. A power semiconductor device according to claim 1 ,wherein the Ag or Ag alloy wire is covered by a wire coating layer of which thickness is 30 Å or more, the wire coating layer contains one or more metals, an alloy including the metal, or an oxide or nitride of the metal, and each of the metal(s) is one selected from the group consisting of Pd, Au, Zn, Pt, Ni and Sn.3. A power semiconductor device according to claim 1 ,wherein connection between the Ag or Ag alloy wire and the die electrode and/or the connection electrode is made by using ultrasonic waves while temperature of either the wire or the electrode is kept at 60° C. or more.4. A power semiconductor device according to claim 2 ,wherein the wire coating layer on the surface of the wire is formed by a wet coating, a dry coating or a nano-particle metal depositing after the wire and the electrode are bonded.5. A power semiconductor device according to claim 1 ,wherein the power semiconductor die uses a SiC semiconductor.6. A method of manufacturing a power semiconductor device according to ...

Photoresist cleaning composition used in photolithography and a method for treating substrate therewith

Semiconductor module and method for production thereof

本发明涉及半导体模块及其制造方法。本发明涉及一种包括半导体芯片、至少两个接触元件和两个接触元件之间的绝缘材料的模块。此外，本发明还涉及用于制造这种模块的方法。一种模块，包括：半导体芯片；第一接触元件和第二接触元件，其与半导体芯片隔开并电耦合到半导体芯片，其中第一接触元件的表面和第二接触元件的表面被布置在公共平面中；电绝缘材料，其具有在第一接触元件和第二接触元件之间的区域中的平坦表面；从电绝缘材料的平坦表面突出的突出元件和/或在电绝缘材料的平坦表面中的凹陷。

Wafer-level package including under bump metal layer

반도체 패키지는 제1 면과 제2 면을 포함하는 반도체 칩; 상기 제1 면 상에 배치되는 재배선층; 상기 재배선층 상에 배치되는 UBM; 및 상기 UBM 상에 배치되는 솔더 범프를 포함하며, 상기 솔더 범프는 상기 UBM의 양 외측면을 덮을 수 있다.

Package structure and method for forming the same

提供一种封装结构及其形成方法。所述封装结构包括第一管芯、第二管芯、中介层、底部填充层、热界面材料及粘合剂图案。所述第一管芯及所述第二管芯并排设置在所述中介层上。所述底部填充层设置在所述第一管芯与所述第二管芯之间。所述热界面材料设置在所述第一管芯、所述第二管芯及所述底部填充层上。所述粘合剂图案设置在所述底部填充层与所述热界面材料之间，以将所述底部填充层与所述热界面材料分隔开。

Batch diffusion soldering and electronic devices produced by batch diffusion soldering

A method of batch soldering includes: forming a soldered joint between a metal region of a first semiconductor die and a metal region of a substrate using a solder preform via a soldering process which does not apply pressure directly to the first semiconductor die, the solder preform having a maximum thickness of 30 μm and a lower melting point than the metal regions; setting a soldering temperature of the soldering process so that the solder preform melts and fully reacts with the metal region of the first semiconductor die and the metal region of the substrate to form one or more intermetallic phases throughout the entire soldered joint, each intermetallic phase having a melting point above the preform melting point and the soldering temperature; and soldering a second semiconductor die to the same or different metal region of the substrate, without applying pressure directly to the second semiconductor die.

Semiconductor device with electrically floating contacts between signal-transmitting contacts

The present disclosure provides a semiconductor device including a first semiconductor structure, a first connecting structure positioned on the first semiconductor structure, a second connecting structure positioned on the first connecting structure, and a second semiconductor structure positioned on the second connecting structure. The first connecting structure includes a plurality of first connecting contacts and a plurality of first supporting contacts positioned in a first connecting insulating layer. The second connecting structure includes a plurality of second connecting contacts and a plurality of second supporting contacts positioned in the second connecting insulating layer positioned on the first connecting structure. The plurality of first connecting contacts contact the plurality of second connecting contacts, forming signal-transmitting contacts. The plurality of first supporting contacts contact the plurality of second supporting contacts, forming electrically floating contacts for implementing electro-magnetic interference shielding between the signal-transmitting contacts.

Method of fabricating cylindrical bonding structure

A cylindrical bonding structure and its method of manufacture. The cylindrical bonding structure is formed over the bonding pad of a silicon chip and the chip is flipped over to connect with a substrate board in the process of forming a flip-chip package. The cylindrical bonding structure mainly includes a conductive cylinder and a solder block. The conductive cylinder is formed over the bonding pad of the silicon chip and the solder block is attached to the upper end of the conductive cylinder. The solder block has a melting point lower than the conductive cylinder. The solder block can be configured into a cylindrical, spherical or hemispherical shape. To fabricate the cylindrical bonding structure, a patterned mask layer having a plurality of openings that correspond in position to the bonding pads on the wafer is formed over a silicon wafer. Conductive material is deposited into the openings to form conductive cylinders and finally a solder block is attached to the end of each conductive cylinder.

Photoresist cleaning composition for use in photolithography and method for treating substrate using the same

本文公开了用于剥离膜厚度为3‑150μm的光刻胶图案的光刻胶清洁组合物，其包含(a)季铵氢氧化物、(b)水溶性有机溶剂的混合物、(c)至少一种腐蚀抑制剂和(d)水，及用该光刻胶清洁组合物处理衬底的方法。

Semiconductor device

The present invention relates to a semiconductor device. The semiconductor device includes a substrate and a chip. The chip is electrically connected to the substrate. The chip includes a chip body, at least one chip pad, a first passivation, an under ball metal layer and at least one metal pillar structure. The chip pad is disposed adjacent to an active surface of the chip body. The first passivation is disposed adjacent to the active surface, and exposes part of the chip pad. The under ball metal layer is disposed adjacent to the chip pad. The metal pillar structure contacts the under ball metal layer to form a first contact surface having a first diameter. The metal pillar structure is electrically connected to a substrate pad of the substrate to form a second contact surface having a second diameter. The ratio of the first diameter to the second diameter is between 0.7 and 1.0. As a result, the first contact surface and the second contact surface have an equivalent bonding force, which prevents the metal pillar structure from cracking due to a shear stress. Thus, the structure strength of the semiconductor device is enhanced and the semiconductor device can pass the reliability test.

Semiconductor element and fabrication method thereof

Hetero-integrated structure

A hetero-integrated structure includes a substrate, a die, a passivation layer, a first redistribution layer, a second redistribution layer, and connecting portions. The die is attached on the substrate. The die has an active surface and a non-active surface. The active surface has pads. The passivation layer covers sidewalls and a surface of the die to expose a surface of the pads. The first redistribution layer is located on the passivation layer and electrically connected to the pads. The second redistribution layer is located on the substrate and adjacent to the die. The connecting portions are connected to the first redistribution layer and the second redistribution layer.

Semiconductor module and method for production thereof

This invention relates to a module including a semiconductor chip, at least two contact elements and an insulating material between the two contact elements. Furthermore, the invention relates to a method for production of such a module.

Molded chip combination

Method for fabricating circuit component

A cylindrical bonding structure and its method of manufacture. The cylindrical bonding structure is formed over the bonding pad of a silicon chip and the chip is flipped over to connect with a substrate board in the process of forming a flip-chip package. The cylindrical bonding structure mainly includes a conductive pillar and a solder cap. The conductive pillar is formed over the bonding pad of the silicon chip and the solder cap is attached to the upper end of the conductive pillar. The solder cap has a melting point lower than the conductive pillar. The solder cap can be configured into a cylindrical, spherical or hemispherical shape. To fabricate the cylindrical bonding structure, a patterned mask layer having a plurality of openings that correspond in position to the bonding pads on the wafer is formed over a silicon wafer. Conductive material is deposited into the openings to form conductive pillars and finally a solder cap is attached to the end of each conductive pillar.

Chip package and method for forming the same

Through-substrate via structure and method of fabricating the same

本发明涉及贯穿衬底通孔结构及其制造方法。本发明公开了一种贯穿衬底通孔结构，该结构包括具有相对的第一主表面和第二主表面的衬底。一个或多个导电通孔结构被设置成在所述衬底内从所述第一主表面延伸到第一垂直距离。凹陷区域在所述衬底内从所述第二主表面延伸到第二垂直距离，并邻接所述导电通孔的下表面。在一个实施方案中，所述第二垂直距离大于所述第一垂直距离。导电区域被设置在所述凹陷区域内，并被构造成与所述导电通孔电导通和/或热连通。

Semiconductor device and method of forming micro interconnect structures

A semiconductor device has a first semiconductor die and second semiconductor die with a conductive layer formed over the first semiconductor die and second semiconductor die. The second semiconductor die is disposed adjacent to the first semiconductor die with a side surface and the conductive layer of the first semiconductor die contacting a side surface and the conductive layer of the second semiconductor die. An interconnect, such as a conductive material, is formed across a junction between the conductive layers of the first and second semiconductor die. The conductive layer may extend down the side surface of the first semiconductor die and further down the side surface of the second semiconductor die. An extension of the side surface of the first semiconductor die can interlock with a recess of the side surface of the second semiconductor die. The conductive layer extends over the extension and into the recess.

Wafer with a plurality of chips

本公开涉及一种晶片。本文中描述了适用于形成集成电路芯片封装的集成电路互连。在一个示例中，集成电路互连体现在晶片中，该晶片包括其上形成有多个集成电路(IC)裸片的基板。多个IC裸片包括具有第一固态电路的第一IC裸片和具有第二固态电路的第二IC裸片。第一接触焊盘设置在基板上并且耦合到第一固态电路。第一焊球设置在第一接触焊盘上。第一焊球具有形成在其上的基本上均匀的氧化物涂层。

Method for fabricating semiconductor device with connecting structure

The present application discloses a method for fabricating a semiconductor device. The method includes providing a first semiconductor structure; and forming a first connecting structure comprising a first connecting insulating layer on the first semiconductor structure, two first conductive layers in the first connecting insulating layer, and a first porous layer between the two first conductive layers; wherein a porosity of the first porous layer is between about 25% and about 100%.

Semiconductor device

반도체 장치가 제공된다. 반도체 장치는 기판, 기판 상에 배치되는 보호막으로, 보호막을 관통하는 트렌치를 포함하는 보호막, 트렌치의 적어도 일부를 채우는 제1 부분과, 보호막 상에 배치되는 제2 부분을 포함하는 하부 범프 및 하부 범프 상에 배치되는 상부 범프를 포함하고, 보호막은, 트렌치의 측벽을 포함하는 제1 부분 및 제2 부분을 포함하고, 기판의 상면으로부터 상기 보호막의 제1 부분의 상면까지의 제1 높이는, 기판의 상면으로부터 상기 보호막의 제2 부분의 상면까지의 제2 높이보다 크다.

Semiconductor device having solder joint and method of forming the same

Provided is a semiconductor device having a high-reliability solder joint. The semiconductor device includes a high-temperature solder formed on a conductive pad. A low-temperature solder having a lower melting point than the high-temperature solder is formed on the high-temperature solder. A barrier layer is formed between the high-temperature solder and the low-temperature solder. An Sn content of the high-temperature solder is higher than that of the low-temperature solder.

Semiconductor assembly

本发明涉及一种半导体组件，其结构在此半导体基底的顶部表面上设有至少一接垫；一保护层(passivation layer)是位于半导体基底的顶部表面上，且位于此保护层内的至少一开口暴露出接垫；及一金属层是堆栈形成在接垫上。

Semiconductor component and assembly with projecting electrode

一种具有基板和基板上的凸出电极的半导体元件。凸出电极被构成为适合将半导体元件电连接和机械连接到外部基板。另外，凸出电极由凸出次电极的一维或二维阵列形成，这些凸出次电极被从基板表面开始的电绝缘流彼此分开。该半导体元件具有改进了的凸出电极。其提供了具有次结构的凸出电极，这实现了足够的柔性，而且不会在制作过程中引入过多的构建复杂性和工艺复杂性。

Diffusion soldering preform with varying surface profile

A method of soldering includes providing a substrate having a first metal joining surface, providing a semiconductor die having a second metal joining surface, providing a solder preform having a first interface surface and a second interface surface, arranging the solder preform between the substrate and the semiconductor die such that the first interface surface faces the first metal joining surface and such that the second interface surface faces the second metal joining surface, and performing a mechanical pressure-free diffusion soldering process that forms a soldered joint between the substrate and the semiconductor die by melting the solder preform and forming intermetallic phases in the solder. One or both of the first interface surface and the second interface surface has a varying surface profile that creates voids between the solder preform and one or both of the substrate and the semiconductor die before the melting of the solder preform.

The method of chip package and manufacture chip package

本发明涉及芯片封装和制造芯片封装的方法。提供一种制造芯片封装的方法，该方法包括：在载体上形成层布置；在层布置上布置包括一个或多个接触焊盘的芯片，其中芯片覆盖层布置的至少一部分；以及选择性地去除层布置的一个或多个部分，并使用芯片作为掩模，使得由芯片覆盖的层布置的至少一部分不被去除。

Heterogeneous integrated assembly structure and manufacturing method thereof

本发明公开一种异质整合组装结构及其制造方法，其中该异质整合组装结构包括基底、管芯、钝化层、第一重布线层、第二重布线层以及连接部。管芯安装于所述基底上。管芯具有有源面与无源面。有源面具有接垫。钝化层覆盖所述管芯的侧壁与表面，裸露出所述接垫的表面。第一重布线层位于钝化层上，电连接接垫。第二重布线层位于基底上，与管芯相邻。连接部连接第一重布线层与第二重布线层。

Methods for forming pillar bumps on semiconductor wafers

本案所含之請求標的揭示用於在半導體晶圓上的凸塊下金屬墊上形成垂直金屬柱及在該金屬柱之頂表面上施用不連續焊帽的方法，其中該金屬柱是由至少一光阻層所界定而成。該方法包括加熱多元素金屬膏，該多元素金屬膏含有可變量的金屬粉末、熔點降低劑及助焊劑，以使金屬粉末燒結成金屬柱並同時使該金屬柱附著於該凸塊下金屬墊。

A semiconductor device with a solder joint having a Sn / Sb connection

Die Halbleitervorrichtung (10; 20) umfasst einen Halbleiterdie, der eine erste Oberfläche und eine der ersten Oberfläche gegenüberliegende zweite Oberfläche, eine erste Metallisierungsschicht, die auf der ersten Oberfläche des Halbleiterdie angeordnet ist, eine erste Lotschicht, die auf der ersten Metallisierungsschicht angeordnet ist, wobei die erste Lotschicht eine Verbindung Sn/Sb enthält, und ein erstes Kontaktelement, das einen Grundkörper auf Cu-Basis und eine auf Ni-Basis angeordnete Schicht auf einer Hauptoberfläche des Grundkörpers auf Cu-Basis umfasst, wobei das erste Kontaktelement mit der Ni-basierten Schicht mit der ersten Lotschicht verbunden ist. The semiconductor device (10; 20) comprises a semiconductor die having a first surface and a second surface opposite the first surface, a first metallization layer arranged on the first surface of the semiconductor die, a first solder layer arranged on the first metallization layer, wherein the first solder layer contains a connection Sn / Sb, and a first contact element, which comprises a Cu-based base body and a Ni-based layer arranged on a main surface of the Cu-based base body, the first contact element with the Ni based layer is connected to the first solder layer.

Wafer-level method for fine-pitch, high aspect ratio chip interconnect

A metal structure 300 for an integrated circuit having a plurality of contact pads and a patterned metallization 301 protected by an overcoat layer 303,306. The structure comprises a plurality of windows in the overcoat, selectively exposing the chip metallization, wherein the windows are spaced apart by less than 150 µm center to center. A metal column 308 is positioned on each of the windows; the preferred metal is copper; the column has a height-to-width aspect ratio larger than 1.25 and an upper surface wettable by re-flowable metal. The preferred column height-to-width aspect ratio is between 2.0 and 4.0, operable to absorb thermomechanical stress. A cap of a re-flowable metal 309 is positioned on each of the columns. The metal structure is used for attaching the IC chip to an external part 311.

Power semiconductor device, manufacturing method thereof, and bonding wire

パワー半導体装置の電流容量の大容量化、高温環境での使用に際し、熱応力が発生しても問題なく使用でき、ワイヤ自身の発熱を低減でき、高温環境でも接合部の信頼性を確保することができるパワー半導体装置及びその製造方法並びにボンディングワイヤを提供することを課題とする。パワー半導体素子２上の金属電極（素子電極３）ともう一方の金属電極（接続電極４）とを金属ワイヤ５によって双方ともウェッジ接続したパワー半導体装置１において、金属ワイヤ５は直径５０μｍ超２ｍｍ以下のＡｇ又はＡｇ合金ワイヤであり、素子電極３は表面に５０Å厚以上のＮｉ、Ｃｒ、Ｃｕ、Ｐｄ、Ｖ、Ｔｉ、Ｐｔ、Ｚｎ、Ａｇ、Ａｕ、Ｗ、Ａｌの金属層又はこれらの合金層を１層以上有する。これにより、Ａｇワイヤを用いるにもかかわらず電極との接合部信頼性を確保でき、大電流での使用時に金属ワイヤ自身の発熱を低減でき、高温での耐熱性を改善することができる。 When the current capacity of a power semiconductor device is increased and it is used in a high-temperature environment, it can be used without problems even if thermal stress occurs, the heat generation of the wire itself can be reduced, and the reliability of the joint can be ensured even in a high-temperature environment. It is an object of the present invention to provide a power semiconductor device, a manufacturing method thereof, and a bonding wire. In the power semiconductor device 1 in which the metal electrode (element electrode 3) on the power semiconductor element 2 and the other metal electrode (connection electrode 4) are both wedge-connected by the metal wire 5, the metal wire 5 has a diameter of more than 50 μm and less than 2 mm. Ag or Ag alloy wire, and the element electrode 3 has a metal layer of Ni, Cr, Cu, Pd, V, Ti, Pt, Zn, Ag, Au, W, Al or an alloy layer thereof having a thickness of 50 mm or more on the surface. 1 or more layers. As a result, the reliability of the joint with the electrode can be ensured despite the use of the Ag wire, the heat generation of the metal wire itself can be reduced during use at a large current, and the heat resistance at high temperatures can be improved.

Integrated circuit system with stress redistribution layer and method of manufacture thereof

A method of manufacture of an integrated circuit system includes: providing a substrate having a transistor and a metallization layer; forming a metal pad in direct contact with the metallization layer of the substrate; forming a passivation layer in direct contact with the metal pad and covering the substrate; forming a routing trace above the passivation layer in direct contact with the metal pad, and the routing trace is substantially larger than the metal pad, and the routing trace is not electrically insulated by a subsequent layer; and forming a bump connected to the metal pad with the routing trace.

Bonding structure for semiconductor package and method of manufacturing the same

A method of manufacturing a bonding structure includes (a) providing a substrate, wherein the substrate includes a top surface and at least one bonding pad disposed adjacent to the top surface of the substrate, at least one bonding pad having a sloped surface with a first slope; (b) providing a semiconductor element, wherein the semiconductor element includes at least one pillar, and at least one pillar has a sidewall with a second slope, wherein the absolute value of the first slope is smaller than the absolute value of the second slope; and (c) bonding at least one pillar to a portion of the sloped surface of corresponding ones of the at least one bonding pad.

Photoresist cleaning compositions used in photolithography and methods of treating substrates therewith

(a) 4차 암모늄 하이드록사이드, (b) 수용성 유기 용매의 혼합물, (c) 적어도 하나의 부식 억제제, 및 (d) 물을 함유하는, 3-150 ㎛의 막 두께를 갖는 포토레지스트 패턴을 스트립핑하기 위한 포토레지스트 세정 조성물, 및 이로 기판을 처리하는 방법이 개시된다. a photoresist pattern having a film thickness of 3-150 μm containing (a) a quaternary ammonium hydroxide, (b) a mixture of a water soluble organic solvent, (c) at least one corrosion inhibitor, and (d) water. Photoresist cleaning compositions for stripping, and methods of treating the substrates are disclosed.

Adhesive and thermal interface material on a plurality of dies covered by a lid

Provided are a package structure and a method of forming the same. The package structure includes a first die, a second die group, an interposer, an underfill layer, a thermal interface material (TIM), and an adhesive pattern. The first die and the second die group are disposed side by side on the interposer. The underfill layer is disposed between the first die and the second die group. The adhesive pattern at least overlay the underfill layer between the first die and the second die group. The TIM has a bottom surface being in direct contact with the first die, the second die group, and the adhesive pattern. The adhesive pattern separates the underfill layer from the TIM.

Chip-scale package

Aspects of the present disclosure relate to a semiconductor device such as a chip-scale package. Aspects of the present disclosure further relate to a method for manufacturing such a device.According to an aspect of the present disclosure, a semiconductor device is provided that comprises a conformal coating arranged on its sidewalls and on the perimeter part of the semiconductor die of the semiconductor device. To prevent the conformal coating from covering unwanted areas, such as electrical terminals, a sacrificial layer is arranged prior to arranging the conformal coating. By removing the sacrificial layer, the conformal coating can be removed locally. The conformal coating covers the perimeter part of the semiconductor die comprises by the semiconductor device, in which part a remainder of a sawing line or dicing street is provided.

Wafer-level package including under bump metal layer

A semiconductor package includes a semiconductor chip comprising a first surface and a second surface, a redistribution layer on the first surface of the semiconductor chip, an under bump metal (UBM) layer on the redistribution layer, and a solder bump on the UBM layer, and the solder bump covers both outer side surfaces of the UBM layer.

Wafer-level package including under bump metal layer

A semiconductor package includes a semiconductor chip comprising a first surface and a second surface, a redistribution layer on the first surface of the semiconductor chip, an under bump metal (UBM) layer on the redistribution layer, and a solder bump on the UBM layer, and the solder bump covers both outer side surfaces of the UBM layer.

Solder ball fabricating process

A solder ball fabricating process for forming solder balls over a wafer having an active layer is provided. A patterned solder mask layer is formed over the active surface of the wafer. The patterned solder mask layer has an opening that exposes a bonding pad on the wafer. Solder material is deposited into the opening over the bonding pad. A reflow process is conducted to form a pre-solder body. The aforementioned steps are repeated so that various solder materials are fused together to form a solder ball over the bonding pad.

使用湿法蚀刻和干法蚀刻制造半导体器件的方法以及半导体器件

本公开内容涉及使用湿法蚀刻和干法蚀刻制造半导体器件的方法以及半导体器件。一种用于制造半导体器件的方法包括：在半导体衬底上沉积TiW层，在TiW层上沉积Ti层，在Ti层上沉积Ni合金层，在Ni合金层上沉积Ag层，用光致抗蚀剂至少部分地覆盖Ag层，对Ag层和Ni合金层进行湿法蚀刻，以及对Ti层和TiW层进行干法蚀刻。

Ubm을 포함하는 웨이퍼-레벨 반도체 패키지

반도체 패키지는 제1 면과 제2 면을 포함하는 반도체 칩; 상기 제1 면 상에 배치되는 재배선층; 상기 재배선층 상에 배치되는 UBM; 및 상기 UBM 상에 배치되는 솔더 범프를 포함하며, 상기 솔더 범프는 상기 UBM의 양 외측면을 덮을 수 있다.

Semiconductor device and method of manufacturing the same

A semiconductor device and a method of manufacturing the semiconductor device are disclosed. The semiconductor device includes a chip substrate, a mold, and a buffer layer. The mold is disposed over the chip substrate. The buffer layer is externally embedded between the chip substrate and the mold. The buffer layer has an elastic modulus or a coefficient of thermal expansion less than that of the mold. The method includes disposing a buffer layer at least covering scribe lines of a substrate, forming a mold over the substrate and covering the buffer layer, and cutting along the scribe lines and through the mold, the buffer layer and the substrate.

Semiconductor device and semiconductor package

Semiconductor device and method of forming micro interconnect structures

A semiconductor device has a first semiconductor die and second semiconductor die with a conductive layer formed over the first semiconductor die and second semiconductor die. The second semiconductor die is disposed adjacent to the first semiconductor die with a side surface and the conductive layer of the first semiconductor die contacting a side surface and the conductive layer of the second semiconductor die. An interconnect, such as a conductive material, is formed across a junction between the conductive layers of the first and second semiconductor die. The conductive layer may extend down the side surface of the first semiconductor die and further down the side surface of the second semiconductor die. An extension of the side surface of the first semiconductor die can interlock with a recess of the side surface of the second semiconductor die. The conductive layer extends over the extension and into the recess.

Semiconductor device with composite connection structure and method for fabricating the same

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a first insulating layer positioned above the substrate, a second insulating layer positioned above the first insulating layer, a plurality of first conductive features positioned in the first insulating layer and the second insulating layer, and an alleviation structure positioned between the first insulating layer and the second insulating layer. The alleviation structure includes a first connecting interlayer respectively electrically coupled to the plurality of first conductive features positioned in the first insulating layer and the second insulating layer, and a plurality of alleviation structures positioned between the plurality of first conductive features in the first insulating layer and the plurality of first conductive features in the second insulating layer, wherein a porosity of the plurality of alleviation structures is between about 25% and about 100%.

半导体元件及其制备方法

本公开提供一种半导体元件及其制备方法。该半导体元件具有一基底、一第一隔离层、一第二隔离层、多个第一导电特征以及一调和结构，该第一隔离层位在该基底上，该第二隔离层位在该第一隔离层上，该多个第一导电特征位在该第一隔离层与该第二隔离层中，该调和结构位在该第一隔离层与该第二隔离层之间。该调和结构具有一第一连接夹层以及多个第一调和层，该第一连接夹层分别电性耦接到位在该第一隔离层与该第二隔离层中的该多个第一导电特征，且该多个第一调和层位在该第一隔离层中的该多个第一导电特征与该第二隔离层中的该多个第一导电特征之间，其中该多个调和结构的一孔隙率介于大约25％到大约100％之间。

制造半导体装置的方法

一种制造半导体装置的方法包含：在第一绝缘区域和紧邻所述第一绝缘区域的第一金属区域上形成第一金属膜，其中所述第一金属膜包括不同于所述第一金属区域的所述金属的金属；在第二绝缘区域和紧邻所述第二绝缘区域的第二金属区域上形成第二金属膜，其中所述第二金属膜包括不同于所述第二金属区域的所述金属的金属；使所述第一金属膜与所述第二金属膜相互接触；和热处理所述第一衬底与所述第二衬底，且由此将所述第一金属区域与所述第二金属区域相互电连接且同时在所述第一绝缘区域与所述第二绝缘区域之间形成绝缘界面膜。

Lids for integrated circuit packages with solder thermal interface materials

Disclosed herein are lids for integrated circuit (IC) packages with solder thermal interface materials (STIMs), as well as related methods and devices. For example, in some embodiments, an IC package may include a STIM between a die of the IC package and a lid of the IC package. The lid of the IC package may include nickel, the IC package may include an intermetallic compound (IMC) between the STIM and the nickel, and the lid may include an intermediate material between the nickel and the IMC.

Silicon carbide device and method for forming a silicon carbide device

A power semiconductor device includes a semiconductor substrate having a wide bandgap semiconductor material and a first surface, an insulation layer above the first surface of the semiconductor substrate, the insulation layer including at least one opening extending through the insulation layer in a vertical direction, a front metallization above the insulation layer with the insulation layer being interposed between the front metallization and the first surface of the semiconductor substrate, and a metal connection arranged in the opening of the insulation layer and electrically conductively connecting the front metallization with the semiconductor substrate; wherein the front metallization includes at least one layer that is a metal or a metal alloy having a higher melting temperature than an intrinsic temperature of the wide bandgap semiconductor material of the semiconductor substrate.

Fabricating a Wafer Level Semiconductor Package Having a Pre-formed Dielectric Layer

There are disclosed herein various implementations of improved wafer level semiconductor packages. One exemplary implementation comprises forming a post-fabrication redistribution layer (post-Fab RDL) between first and second dielectric layers affixed over a surface of a wafer, and forming a window for receiving an electrical contact body in the second dielectric layer, the window exposing the post-Fab RDL. At least one of the first and second dielectric layers is a pre-formed dielectric layer, which may be affixed over the surface of the wafer using a lamination process. In one implementation, the window is formed using a direct laser ablation process.

Fabricating a wafer level semiconductor package having a pre-formed dielectric layer

There are disclosed herein various implementations of improved wafer level semiconductor packages. One exemplary implementation comprises forming a post-fabrication redistribution layer (post-Fab RDL) between first and second dielectric layers affixed over a surface of a wafer, and forming a window for receiving an electrical contact body in the second dielectric layer, the window exposing the post-Fab RDL. At least one of the first and second dielectric layers is a pre-formed dielectric layer, which may be affixed over the surface of the wafer using a lamination process. In one implementation, the window is formed using a direct laser ablation process.

Wafer level semiconductor package

There are disclosed herein various implementations of improved wafer level semiconductor packages. One exemplary implementation comprises forming a post-fabrication redistribution layer (post-Fab RDL) between first and second dielectric layers affixed over a surface of a wafer, and forming a window for receiving an electrical contact body in the second dielectric layer, the window exposing the post-Fab RDL. At least one of the first and second dielectric layers is a pre-formed dielectric layer, which may be affixed over the surface of the wafer using a lamination process. In one implementation, the window is formed using a direct laser ablation process.

Chip-scale packaged vertical semiconductor device

Aspects of the present disclosure relate to a vertical semiconductor device. Aspects of the present disclosure further relate to a method for manufacturing such a vertical semiconductor device.According to an aspect of the present disclosure, a vertical semiconductor device is provided that comprises a conformal coating arranged on its sidewalls. To prevent the conformal coating from covering unwanted areas, such as electrical terminals, a sacrificial layer is arranged prior to arranging the conformal coating. By removing the sacrificial layer, the conformal coating can be removed locally.

Methods of fabricating a light-emitting device

Methods of fabricating of a light-emitting device are provided, the methods include forming a plurality of light-emitting units on a substrate, measuring light characteristics of the plurality of light-emitting units, respectively, depositing a phosphor layer on the plurality of light-emitting units using a printing method, and cutting the substrate to separate the plurality of light-emitting units into unit by unit. The phosphor layer is adjustably deposited according to the measured light characteristics of the plurality of light-emitting units.

半导体元件

本公开提供一种半导体元件，包括一第一半导体结构、一第一连接结构、一第二连接结构以及一第二半导体结构；该第一连接结构包括一第一连接隔离层、多个第一连接接触点以及多个第一支撑接触点，该第一连接隔离层位于该第一半导体结构上，该多个第一连接接触点位于该第一连接隔离层中，该多个第一支撑接触点位于该第一连接隔离层中。该第二连接结构位于该第一连接结构上，该第二半导体结构位于该第二连接结构上，其中该第二连接结构包括一第二连接隔离层、多个第二连接接触点以及多个第二支撑接触点，该第二连接隔离层位于该第一连接结构上，该多个第二连接接触点位于该第二连接隔离层中，该多个第二支撑接触点位于该第二连接隔离层中。

耐高溫之化合物半導體基板之背面金屬改良結構

一種耐高溫之化合物半導體基板之背面金屬改良結構，包括：一正面金屬層係形成於一化合物半導體基板之一上表面；至少一基板通孔係貫穿化合物半導體基板，基板通孔具有一內表面之一頂部係為正面金屬層；至少一種子金屬層、至少一背面金屬層以及至少一擴散阻礙層係依序係形成覆蓋於化合物半導體基板之一下表面以及每一基板通孔之內表面，種子金屬層係藉由基板通孔與正面金屬層電性連接；以及一晶粒黏著金屬層係形成於基板通孔之一鄰近區域之外及基板通孔之外之擴散阻礙層之一下表面。藉由擴散阻礙層以防止背面金屬層擴散至晶粒黏著金屬層。

반도체 디바이스 및 반도체 디바이스를 제조하는 방법

반도체 디바이스 및 반도체 디바이스를 제조하는 방법이 개시된다. 반도체 디바이스는 칩 기판, 몰드 및 버퍼 층을 포함한다. 몰드는 칩 기판 위에 배치된다. 버퍼 층은 칩 기판과 몰드 사이에 외부적으로 임베디드된다. 버퍼 층은 몰드의 탄성률 또는 열 팽창 계수보다 작은 탄성률 또는 열 팽창 계수를 갖는다. 방법은 적어도 기판의 스크라이브 라인들을 커버하는 버퍼 층을 배치하는 단계, 기판 위에 몰드를 형성하며 버퍼 층을 커버하는 단계, 및 스크라이브 라인들을 따라 그리고 몰드, 버퍼 층 및 기판을 통해 컷팅하는 단계를 포함한다.

具应力再分布层的集成电路系统

一种制造集成电路系统的方法，包含：提供具有晶体管与金属化层的基板；形成与所述基板的所述金属化层直接接触的金属垫；形成与所述金属垫直接接触以及覆盖所述基板的钝化层；在所述钝化层上方，形成与所述金属垫直接接触的路由追踪，并且所述路由追踪实质大于所述金属垫，以及所述路由追踪并未通过后续层而电性绝缘；以及形成凸块，以所述路由追踪连接至所述金属垫。

Diffusion soldering preform with varying surface profile

A method of soldering includes providing a substrate having a first metal joining surface, providing a semiconductor die having a second metal joining surface, providing a solder preform having a first interface surface and a second interface surface, arranging the solder preform between the substrate and the semiconductor die such that the first interface surface faces the first metal joining surface and such that the second interface surface faces the second metal joining surface, and performing a mechanical pressure-free diffusion soldering process that forms a soldered joint between the substrate and the semiconductor die by melting the solder preform and forming intermetallic phases in the solder. One or both of the first interface surface and the second interface surface has a varying surface profile that creates voids between the solder preform and one or both of the substrate and the semiconductor die before the melting of the solder preform.

半導體裝置及半導體封裝

本案提供一種半導體裝置及一種包含該半導體裝置之半導體封裝。該半導體裝置包括：半導體元件；保護層，其設置鄰近於該半導體元件之表面，該保護層界定開口以曝露該半導體元件；第一凸塊，其設置於該半導體元件上；及第二凸塊，其設置至該保護層之表面上。該第一凸塊相比於該第二凸塊具有較大橫截面表面積。

半导体元件及其制备方法

本公开提供一种半导体元件及该半导体元件的制备方法。该半导体元件具有一第一半导体结构以及一第一连接结构，其中该第一连接结构具有一第一连接隔离层、两个第一导电层以及一第一多孔层，该第一连接隔离层位在该第一半导体结构上，所述两个第一导电层位在该第一连接隔离层中，该第一多孔层位在所述两个第一导电层之间。该第一多孔层的一孔隙率介于大约25％到大约100％之间。

칩-스케일 패키지

본 발명의 양태는 칩-스케일 패키지와 같은 반도체 디바이스에 관한 것이다. 본 발명의 양태는 또한 이러한 디바이스를 제조하는 방법에 관한 것이다. 본 발명의 양태에 따르면, 반도체 디바이스의 반도체 다이의 측벽 상에 그리고 주변 부분 상에 배열된 컨포멀 코팅을 포함하는 반도체 디바이스가 제공된다. 컨포멀 코팅이 전기 터미널과 같은 원하지 않는 영역을 덮는 것을 방지하기 위해 컨포멀 코팅을 배열하기 전에 희생층이 배열된다. 희생층을 제거함으로써, 컨포멀 코팅을 국부적으로 제거될 수 있다. 컨포멀 코팅은 반도체 디바이스에 포함된 반도체 다이의 주변 부분을 덮으며, 이 부분에 소잉 라인 또는 다이싱 스트리트의 나머지 부분이 제공된다.

チップスケールパッケージ

【課題】短絡の危険が存在しないチップスケールパッケージ及びそのようなデバイスを製造する方法を提供する。【解決手段】側壁及び半導体デバイスの半導体ダイ３０’の周囲部分に配置されたコンフォーマルコーティング３４を備える半導体デバイスの製造方法であって、コンフォーマルコーティング３４が電気端子Ｔ１、Ｔ２等の領域を覆うことを防ぐために、コンフォーマルコーティング３４を配置Ｓ１＿４する前に犠牲層３２を配置しＳ１＿２、犠牲層３２をフォトアブレーションによって除去するＳ１＿５ことにより、コンフォーマルコーティング３４を局所的に除去する。コンフォーマルコーティング３４は、半導体デバイスによって構成される半導体ダイ３０’の周囲部分を覆い、その部分には、ソーイングライン又はダイシングストリートの残部が設けられる。【選択図】図６

晶片級封裝

本公開的各方面涉及諸如晶片級封裝件的半導體裝置。本公開的各方面還涉及一種用於製造這種裝置的方法。根據本公開的一方面，提供了一種半導體裝置，該半導體裝置包括佈置在其側壁上和半導體裝置的半導體裸片的周邊部分上的共形塗層。為了防止共形塗層覆蓋諸如電端子的不需要的區域，在佈置共形塗層之前佈置犧牲層。通過去除犧牲層，可以局部地去除共形塗層。共形塗層覆蓋半導體裝置所包括的半導體裸片的周邊部分，在該周邊部分中提供了鋸切線或切割道的剩餘部分。

Chip-scale package

Aspects of the present disclosure relate to a semiconductor device such as a chip-scale package. Aspects of the present disclosure further relate to a method for manufacturing such a device. According to an aspect of the present disclosure, a semiconductor device is provided that comprises a conformal coating arranged on its sidewalls and on the perimeter part of the semiconductor die of the semiconductor device. To prevent the conformal coating from covering unwanted areas, such as electrical terminals, a sacrificial layer is arranged prior to arranging the conformal coating. By removing the sacrificial layer, the conformal coating can be removed locally. The conformal coating covers the perimeter part of the semiconductor die comprises by the semiconductor device, in which part a remainder of a sawing line or dicing street is provided.

在电气部件与电子部件之间形成互连的方法

一种在电气部件与电子部件之间形成互连的方法包括：提供电子部件，所述电子部件包括第一主面和设置在所述第一主面上的第一金属层；提供电气部件，所述电气部件包括第二主面和设置在所述第二主面上的第二金属层；其中，所述第一金属层或所述第二金属层中的至少一个包括提供在其主面上的氧化物层；在所述电子部件和所述电气部件中的一个或两个上设置还原剂，使得所述还原剂能够去除所述氧化物层；以及通过施加压力和热将所述电子部件的所述第一金属层与所述电气部件的所述第二金属层直接连接，来将所述电子部件连接到所述电气部件。

High Temperature Resistant Backside Metallization for Compound Semiconductors

An improved high temperature resistant backside metallization for compound semiconductors comprises a front-side metal layer formed on a compound semiconductor substrate; at least one via hole penetrating the compound semiconductor substrate, a top of an inner surface of the via hole is defined by the front-side metal layer; at least one seed metal layer, at least one backside metal layer and at least one diffusion barrier layer sequentially formed on a bottom surface of the compound semiconductor substrate and the inner surface of the via hole, the seed metal layer and the front-side metal layer are electrically connected through the via hole; a die attachment metal layer formed on a bottom surface of the diffusion barrier layer other than the via hole and an adjacent area near the via hole. The diffusion barrier layer prevents the backside metal layer from diffusing into the die attachment metal layer.

Semiconductor device and method of manufacturing the same

The method of manufacturing a semiconductor device includes receiving a substrate. The substrate comprises at least one chip region and at least one scribe line next to the chip region, and each chip region comprises an active region. The method further includes disposing a buffer layer at least covering the scribe line, disposing a dielectric layer including an opening over each chip region, and disposing a bump material to the opening of the dielectric layer and electrically connecting to the active region. The method further includes forming a mold over the substrate, covering the buffer layer and cutting the substrate along the scribe line. Furthermore, the buffer layer includes an elastic modulus less than that of the mold, or the buffer layer includes a coefficient of thermal expansion less than that of the mold.

半導體裝置之製造方法

一種製造一半導體裝置之方法包括：在一第一絕緣區域及緊鄰該第一絕緣區域之一第一金屬區域上形成一第一金屬膜，其中該第一金屬膜包含不同於該第一金屬區域之金屬的一金屬；在一第二絕緣區域及緊鄰該第二絕緣區域之一第二金屬區域上形成一第二金屬膜，其中該第二金屬膜包含不同於該第二金屬區域之金屬的一金屬；使該第一金屬膜與該第二金屬膜相互接觸；及熱處理第一基板與第二基板，且由此將該第一金屬區域與該第二金屬區域相互電連接且同時在該第一絕緣區域與該第二絕緣區域之間形成一絕緣界面膜。

Semiconductor module having a double-sided heat dissipation structure and A Method for fabricating the same

A semiconductor module having a double-sided heat dissipation structure according to one aspect of the present invention, which can secure the gap between the first and second heat dissipation substrates without using existing spacers, includes a first heat dissipation substrate and a second heat dissipation substrate arranged to face each other; a guide stack disposed between the first heat dissipation substrate and the second heat dissipation substrate, and having an opening area for mounting a semiconductor die in a pattern; and a semiconductor die mounted within the opening area.

半导体元件及其制备方法

本公开提供一种半导体元件及该半导体元件的制备方法。该半导体元件具有一第一半导体结构、一第二半导体结构以及一连接结构，该第一半导体结构具有多个第一导电特征，邻近该第一半导体结构的一上表面处设置，该第二半导体结构位在该第一半导体结构上，且具有多个第二导电特征，邻近该第二半导体结构的一下表面处设置，该连接结构位在该第一半导体结构与该第二半导体结构之间。该连接结构包括一连接层以及多个第一多孔夹层，该连接层电性耦接到该多个第一导电特征与该多个第二导电特征，该多个第一多孔夹层位在该多个第一导电特征与该多个第二导电特征之间。该多个第一多孔夹层的一孔隙率介于大约25％到大约100％之间。

半導體元件及其製備方法

本揭露提供一種半導體元件及該半導體元件的製備方法。該半導體元件具有一第一半導體結構以及一第一連接結構，其中該第一連接結構具有一第一連接隔離層、二第一導電層以及一第一多孔層，該第一連接隔離層位在該第一半導體結構上，該二第一導電層位在該第一連接隔離層中，該第一多孔層位在該二第一導電層之間。該第一多孔層的一孔隙率介於大約25%到大約100%之間。

半導體元件及其製備方法

本揭露提供一種半導體元件及其製備方法。該半導體元件包括一第一半導體結構；一第一連接結構，包括一第一連接隔離層、複數個第一連接接觸點以及複數個第一支撐接觸點，該第一連接隔離層位在該第一半導體結構上，該複數個第一連接接觸點位在該第一連接隔離層中，該複數個第一支撐接觸點位在該第一連接隔離層中；以及一第二半導體結構，設置於該第一連接結構上，其中該複數個第一連接接觸點的上表面接觸該第二半導體結構的一下表面；其中該複數個第一連接接觸點的上表面以及該複數個第一支撐接觸點的上表面凸出該第一連接隔離層的上表面。

半導體元件及其製備方法

本揭露提供一種半導體元件及該半導體元件的製備方法。該半導體元件具有一基底、一第一隔離層、一第二隔離層、複數個第一導電特徵以及一調和結構，該第一隔離層位在該基底上，該第二隔離層位在該第一隔離層上，該複數個第一導電特徵位在該第一隔離層與該第二隔離層中，該調和結構位在該第一隔離層與該第二隔離層之間。該調和結構具有一第一連接夾層以及複數個第一調和層，該第一連接夾層分別電性耦接到位在該第一隔離層與該第二隔離層中的該複數個第一導電特徵，且該複數個第一調和層位在該第一隔離層中的該複數個第一導電特徵與該第二隔離層中的該複數個第一導電特徵之間，其中該複數個調和結構的一孔隙率介於大約25%到大約100%之間。

半導體元件及其製備方法

本揭露提供一種半導體元件及該半導體元件的製備方法。該半導體元件具有一基底、一第一隔離層、一第二隔離層、複數個第一導電特徵以及一調和結構，該第一隔離層位在該基底上，該第二隔離層位在該第一隔離層上，該複數個第一導電特徵位在該第一隔離層與該第二隔離層中，該調和結構位在該第一隔離層與該第二隔離層之間。該調和結構具有一第一連接夾層以及複數個第一調和層，該第一連接夾層分別電性耦接到位在該第一隔離層與該第二隔離層中的該複數個第一導電特徵，且該複數個第一調和層位在該第一隔離層中的該複數個第一導電特徵與該第二隔離層中的該複數個第一導電特徵之間，其中該複數個調和結構的一孔隙率介於大約25%到大約100%之間。

발광 장치의 제조 방법

색 온도를 조절할 수 있는 발광 장치의 제조 방법이 제공된다. 상기 발광 장치의 제조 방법은 기판 상에 다수의 발광 유닛을 형성하고, 다수의 발광 유닛 각각의 광특성을 측정하고, 다수의 발광 유닛 상에 프린트 방식을 이용하여 형광체를 도포하되, 각 발광 유닛 상에 도포되는 형광체는 상기 측정된 상기 각 발광 유닛의 광특성에 따라 조절되고, 상기 기판을 절삭하여, 상기 형광체가 도포된 다수의 발광 유닛을 유닛별로 분리하는 것을 포함한다. 광특성 측정, 프린트 방식, 형광체 도포