Package-Struktur und Verfahren

In einer Ausführungsform umfasst eine Vorrichtung: ein Substrat mit einer ersten Seite und einer zweiten Seite gegenüber der ersten Seite; eine Verbindungsstruktur benachbart zu der ersten Seite des Substrats; und eine IC-Vorrichtung, welche an der Verbindungsstruktur befestigt ist; eine Durchkontaktierung, welche sich von der ersten Seite des Substrats bis zu der zweiten Seite des Substrats erstreckt, wobei die Durchkontaktierung mit der IC-Vorrichtung elektrisch verbunden ist; eine Under-Bump-Metallurgie (UBM) benachbart zu der zweiten Seite des Substrats und die Durchkontaktierung kontaktierend; einen leitfähigen Höcker auf der UBM, wobei es sich bei dem leitfähigen Höcker und der UBM um ein durchgängiges leitfähiges Material handelt, wobei der leitfähige Höcker von der Durchkontaktierung seitlich versetzt ist; und eine Unterfüllung, welche die UBM und den leitfähigen Höcker umgibt.

ELEKTRONISCHES BAUELEMENTGEHÄUSE

Die Technologie eines elektronischen Bauelementgehäuses ist offenbart. Ein elektronisches Bauelementgehäuse gemäß der vorliegenden Offenbarung kann ein Gehäusesubstrat, eine elektronische Komponente, eine Formmasse, die die elektronische Komponente einkapselt, und eine Redistributionsschicht umfassen, die derart angeordnet ist, dass die Formmasse zwischen dem Gehäusesubstrat und der Redistributionsschicht ist. Die Redistributionsschicht und das Gehäusesubstrat können elektrisch gekoppelt sein. Außerdem können die Redistributionsschicht und die elektronische Komponente elektrisch gekoppelt sein, um die elektronische Komponente und das Gehäusesubstrat elektrisch zu koppeln. Zugeordnete Systeme und Verfahren sind auch offenbart.

Dreidimensionale (3D) integrierte Schaltung mit verbessertem Kupfer-Kupfer-Bonding

Mindestens eine metallische Adhäsionsschicht wird auf mindestens einer Cu-Fläche eines ersten Bauelement-Wafers gebildet. Ein zweiter Bauelement-Wafer mit einer weiteren Cu-Fläche wird über der Cu-Fläche des ersten Bauelement-Wafers und auf der mindestens einen metallischen Adhäsionsschicht positioniert. Der erste und der zweite Bauelement-Wafer werden dann zusammengebondet. Das Bonden beinhaltet das Erwärmen der Bauelement-Wafer auf eine Temperatur von weniger als 400°C mit oder ohne Anwendung eines äußerlich angewandten Drucks. Während des Erwärmens werden die beiden Cu-Flächen zusammengebondet und die mindestens eine metallische Adhäsionsschicht erhält Sauerstoffatome von den beiden Cu-Flächen und bildet mindestens eine Metalloxid-Bondschicht zwischen den Cu-Flächen.

Dreidimensionale integrierte Schaltungsstruktur und Verfahren zu deren Herstellung

Es wird eine dreidimensionale integrierte Schaltungsstruktur bereitgestellt, die ein erstes Dia, eine Trägerschichtdurchkontaktierung und ein Verbindungselement enthält. Das erste Die ist an ein zweites Die mit einer ersten dielektrischen Schicht des ersten Dies und einer zweiten dielektrischen Schicht des zweiten Dies gebunden, wobei eine erste Passivierungsschicht zwischen der ersten dielektrischen Schicht und einer ersten Trägerschicht des ersten Dies liegt und ein erstes Testpad in der ersten Passivierungsschicht eingebettet ist. Die Trägerschichtdurchkontaktierung durchdringt das erste Die und ist elektrisch mit dem zweiten Die verbunden. Das Verbindungselement ist elektrisch mit dem ersten Die und dem zweiten Die durch die Trägerschichtdurchkontaktierung verbunden.

INTEGRIERTES SCHALTUNGSPACKAGE UND VERFAHREN

In einer Ausführungsform weist eine Struktur Folgendes auf: einen ersten integrierten Schaltungsdie, der erste Die-Anschlüsse aufweist; eine erste Dielektrikumsschicht auf den ersten Die-Anschlüssen; erste leitfähige Durchkontaktierungen, die sich durch die erste Dielektrikumsschicht hindurch erstrecken, wobei die ersten leitfähigen Durchkontaktierungen an eine erste Untergruppe der ersten Die-Anschlüsse angeschlossen sind; einen zweiten integrierten Schaltungsdie, der an eine zweite Untergruppe der ersten Die-Anschlüsse mit ersten aufschmelzbaren Anschlüssen gebondet ist; ein erstes Verkapselungsmaterial, das den zweiten integrierten Schaltungsdie und die ersten leitfähigen Durchkontaktierungen umgibt, wobei das erste Verkapselungsmaterial und der erste integrierte Schaltungsdie seitlich angrenzend sind; zweite leitfähige Durchkontaktierungen benachbart zu dem ersten integrierten Schaltungsdie; ein zweites Verkapselungsmaterial, das die zweiten leitfähigen Durchkontaktierungen, das erste ...

Bondpads mit unterschiedlich dimensionierten Öffnungen

Integrierter-Schaltkreis-Die (400), der Folgendes umfasst:mehrere Bondpads (401); undeine Die-Passivierungsschicht mit mehreren unterschiedlich dimensionierten Öffnungen (411, 421, 431, 441), die mehrere der Bondpads (401) freilegen, wobei die mehreren unterschiedlich dimensionierten Öffnungen (411, 421, 431, 441) zwei oder mehr Gruppen von Öffnungen umfassen, wobei jede Gruppe relativ zu der/den anderen Gruppe(n) eine unterschiedliche durchschnittliche Öffnungsgröße aufweist; und wobei Größen der mehreren unterschiedlich dimensionierten Öffnungen auf eine solche Weise variieren, dass Spannungen auf dem Die (400) aufgrund einer asymmetrischen Verteilung der mehreren Bondpads (401) wenigstens teilweise kompensiert werden.

Integration von Silicium-Photonik-IC für hohe Datenrate

Integrierte Komponentenbaugruppe, die umfasst:eine Leiterplatte (PCB);eine integrierte Photonikschaltung (PIC), die mit der PCB auf einer ersten Seite der PIC mechanisch gekoppelt ist; undeine Treiber-IC mit einer ersten Seite, wobei die erste Seite der Treiber-IC(i) mit einer zweiten Seite der PIC über einen ersten Satz von Höcker-Bondverbindungen direkt mechanisch und elektrisch gekoppelt ist, und(ii) mit der PCB über einen zweiten Satz von Höcker-Bondverbindungen elektrisch gekoppelt ist.

Wiring substrate for pressure sensors, acceleration sensors and ultrasonic sensors, comprises electrode cushion pad, which is arranged in opening, formed in protection insulation film

The wiring substrate has a wiring layer (15) formed on the surface of a silicon substrate (11), another wiring layer (16) formed on the surface of the former wiring layer. A protection insulation film (14) is so formed that it covers the latter wiring layer. An opening (14a) is formed in the protection insulation film, and an electrode cushion pad is arranged in the opening. The opening in the protection insulation film and the former wiring layer are formed at such positions that they do not overlap each other toward the card thickness of the substrate.

HALBLEITER-WAFERBEARBEITUNGSVERFAHREN

Ein Halbleiter-Waferbearbeitungsverfahren beinhaltet einen Schritt zum Ausbilden einer laserbearbeiteten Nut an der ersten vorderen Seite des Halbleiter-Wafers entlang jeder Teilungslinie, einen Schritt zum Ausbilden einer Maskenschicht an einer Schutzschicht mit Ausnahme eines Bereichs oberhalb einer Metallelektrode, die in jedem Bauelement an der vorderen Seite des Wafers ausgebildet ist, einen ersten Ätzschritt zum Ätzen der Schutzschicht unter Verwendung der Maskenschicht, um jede Metallelektrode freizulegen, einen zweiten Ätzschritt zum Ätzen der inneren Oberfläche von jeder laserbearbeiteten Nut unter Verwendung der Maskenschicht, die in dem ersten Ätzschritt verwendet wird, wodurch jede laserbearbeitete Nut freigelegt wird, und einen Teilungsschritt zum Teilen des Wafers entlang jeder laserbearbeiteten Nut, die in dem zweiten Ätzschritt ausgedehnt wurde.

Halbleitervorrichtung mit einer Kupfersäule-Zwischenverbindungsstruktur

Ein Verfahren zur Herstellung einer Halbleitervorrichtung wird beschrieben. Das Verfahren umfasst das Abscheiden einer Photoresist-Schicht über einem Halbleitersubstrat. Die Photoresist-Schicht wird strukturiert, um eine Öffnung in der Photoresist-Schicht zu bilden. Eine Kupfersäule wird in der Öffnung gebildet. Eine Diffusionsbarriereschicht wird über der Kupfersäule und über einem Photoresist-Abschnitt der Photoresist-Schicht, der direkt an die Öffnung angrenzt, gebildet. Eine Lotstruktur wird über der Diffusionsbarriereschicht abgeschieden.

Integrierte Schaltung oder Platine mit einer Höckerelektrode und Verfahren zu Ihrer Herstellung

Lötverfahren und Schaltung

Vorgeschlagen wird ein Lötverfahren zum Verbinden eines Halbleiterchips (1) mit einer Leiterplatte (2) über wenigstens einen Lötkontakt (7) und zum Herstellen einer Schaltung (14), wobei der Halbleiterchip wenigstens ein elektrisch leitendes Pad (5) aufweist und die Leiterplatte wenigstens einen Leiterbahnabschnitt (9) zur Kontaktierung mit wenigstens einem der Pads des Halbleiterchips umfasst, umfassend: eine Auftragung von Lötpaste (10) auf den wenigstens einen Leiterbahnabschnitt, einen Bondingprozess, bei dem ein Höcker (7) auf wenigstens einem Materialabschnitt (6) auf wenigstens eines der Pads gebondet wird, einen Bestückungsvorgang, bei dem die Leiterplatte so mit wenigstens einem der Halbleiterchips bestückt wird, dass wenigstens einer der Lötkontakte mit der Lötpaste in Berührung kommt, einen Heizprozess, bei dem eine elektrisch leitende Verbindung zwischen dem Leiterbahnabschnitt und dem Pad hergestellt wird. Zur Verbesserung des Lötverfahrens wird als Lötkontakt ausschließlich ...

Stacked wafer or die packaging with enhanced thermal and device performance

Forming electrical/mechanical connections

Devices and methods related to radio-frequency filters on silicon-on-insulator substrate

MULTILEVEL FOIL FOR SHARPENING A DISK BACK

Method for maintaining solder thickness in flipchip attach packaging processes

METHOD OF FORMING A MULTI-LAYER SEMICONDUCTOR STRUCTURE HAVING A SEAMLESS BONDING INTERFACE

ELECTRONIC CIRCUIT DEVICE AND PORDUCTION METHOD THEREFOR

Electrical contact structures from flexible wire

METHOD OF PROVIDING RAISED CONTACT PORTIONS ON CONTACT AREAS OF AN ELECTRONIC MICROCIRCUIT

... : "Method of providing raised contact portions on contact areas of an electronic microcircuit". A method of providing raised contact portions on contact areas of an electronic microcircuit in which a ball is formed at one end of a metal wire by means of thermal energy, the ball is pressed against a contact area of the electronic microcircuit and is connected to said contact area, a weakening being provided in the wire near the ball and the wire being severed at the area of the weakening.

COPPER-TO-GOLD THERMAL COMPRESSION GANG BONDING OF INTERCONNECT LEADS TO SEMICONDUCTIVE DEVICES

Mikroverbindung für auf eine Trägerplatte aufzubringende Mikroschaltungselemente

Verfahren zum Anbringen eines elektrischen Anschlusses auf einer Fläche einer elektronischen Schaltungsanordnung

PROCEDURE FOR THE ATTACHMENT OF CONTACT CONTACTS TO CONTACT POINTS OF AN ELECTRONIC MICROCIRCUIT.

DUAL SOLDER METHODOLOGIES FOR ULTRAHIGH DENSITY FIRST LEVEL INTERCONNECTIONS

Semiconductor chip and method of manufacturing wafer stack package

The invention discloses a semiconductor chip and a method of manufacturing the wafer stack package. The method of manufacturing the semiconductor chip includes following steps: forming a first via hole in the front surface of the substrate; forming a first conductive plug in the first via hole using a first conductive material, the first conductive plug including a first portion in the substrate and a second portion protruding from the substrate; forming a second conductive plug on an upper surface of the first conductive plug using a second conductive material, the second conductive plug having a smaller cross-sectional area than the first conductive plug; back-lapping a rear surface of the substrate; and forming a second via hole in the back-lapped rear surface of the substrate, the second via hole aligned with the first via hole.

Backside metal treatment of semiconductor chips

An integrated circuit structure includes a semiconductor substrate having a front side and a backside. A through-silicon via (TSV) penetrates the semiconductor substrate. The TSV has a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is over the backside of the semiconductor substrate and connected to the back end of the TSV. A silicide layer is over and contacting the RDL.

For bare chip IC of warping reducing the assembly of the compensating TCE of the package substrate,

Wafer level system packaging method and packaging structure

Method of manufacturing semiconductor device and semiconductor device

Semiconductor device manufacturing method and semiconductor device

In a state wherein a plurality of protruding electrodes (4) on a semiconductor chip (1) abut a plurality of electrodes (13), which are formed on a semiconductor substrate (11), with a plurality of solder sections therebetween, the solder sections are melted, and a plurality of solder bonding sections (7), which are bonded to the protruding electrodes (4) of the semiconductor chip (1) and the electrodes (13) of the semiconductor substrate (11), are formed. Then, the interval (A) between a part of the semiconductor chip (1) and the semiconductor substrate (11) is made larger than the interval (B) between another part of the semiconductor chip (1) and the semiconductor substrate (11), and at least some solder bonding sections among the solder bonding sections (7) are stretched. Consequently, variance in the height of the solder bonding sections (7) is generated. Then, a hole (8) is formed in at least the solder bonding section (7a) having the maximum height among the solder bonding sections ...

Semiconductor package and method of manufacturing thereof

Semiconductor device free from short-circuit between bump electrodes and separation from circuit board and process of fabrication thereof

Integrated circuit structure

An integrated circuit structure includes a first work piece and a second work piece. The first work piece includes a semiconductor substrate, and a copper bump over the semiconductor substrate. The second work piece includes a bond pad. A solder is between and adjoining the first work piece and the second work piece, wherein the solder electrically connects the copper bump to the bond pad. The solder includes palladium. The invention improves the reliability of solder obviously.

A lead frame package structure and manufacturing method thereof

Interconnection [...] structure and method

Multilayer substrate

Semiconductor device and method for manufacturing the same

DEVICE OF CONNECTION AND PROCESS OF CONNECTION

A METHOD OF JOINING TWO ELECTRONIC COMPONENTS, FLIP-BY ANNEALING THE UV, OBTAINED ASSEMBLY

SUBMOUNT FOR SEMICONDUCTOR ASSEMBLY

Method for assembly of two electronic systems, involves placing flat front face of bonding pad of electronic device on another bonding pad, where former bonding pad is welded to another bonding pad of another electronic device

Procédé d'assemblage d'un premier dispositif électronique sur un second dispositif électronique, comprenant : réaliser au moins un plot de connexion électrique en saillie (9) sur le premier dispositif électronique, dont la paroi périphérique (9a) s'étend sensiblement perpendiculairement à une face frontale (3) du premier dispositif électronique (1) et présentant une face frontale d'extrémité sensiblement plate (12a), placer la face frontale plate (12a) du plot de connexion électrique (9) du premier dispositif électronique sur un plot de connexion électrique (101) du second dispositif électronique (100), et réaliser la soudure du plot de connexion électrique (9) du premier dispositif électronique (1) sur le plot de connexion électrique (101) du second dispositif électronique (100). Structure comprenant lesdits dispositifs électroniques.

A METHOD OF JOINING TWO ELECTRONIC COMPONENTS, FLIP UV BY ANNEALING, RESULTING ASSEMBLY

L'invention concerne un procédé d'assemblage de type Flip-Chip, entre un premier (1) et un deuxième (2) composants comportant chacun des plots de connexion (11, 21) sur une de leurs faces, dites faces d'assemblage, selon lequel on reporte les composants l'un sur l'autre par leurs faces d'assemblage de sorte à réaliser des interconnexions électriques entre les plots du premier et ceux du deuxième composant. Selon l'invention, on réalise une transformation de l'oxyde de cuivre en cuivre par recuit UV, très localement dans l'espacement entre composants au moins autour des zones au droit des plots de connexion. Le procédé selon l'invention peut être utilisé pour n'importe quel composant transparent aux UV, y compris pour des substrats en matière plastique tels que des substrats en PEN ou en PET.

ASSEMBLING AN INTEGRATED CIRCUIT DIE AND A PLATE

METHOD OF ASSEMBLING ELECTRICAL CONNECTORS

Method for assembling integrated circuits for forming integrated three-dimensional structure, involves fusing alloy layer at low melting point to form conducting connection between metal lines of two integrated circuits

Structure intégrée tridimensionnelle, et procédé de fabrication correspondant, comprenant un assemblage d'un premier circuit intégré (CI1) et d'un deuxième circuit intégré (CI2), ledit premier circuit intégré comportant une face avant(F11), une face arrière (F12), au moins une ligne métallique (LM1) d'un niveau de métallisation disposée au voisinage de sa face avant et un pilier conducteur (PC) saillant d'une de ses faces et électriquement connecté avec ladite ligne métallique (LM1) du premier circuit intégré, ledit pilier conducteur étant recouvert à son extrémité d'une couche (SAC) d'un alliage à basse température de fusion, ledit deuxième circuit intégré (CI2) comportant une face avant (F21), une face arrière, au moins une ligne métallique (LM2) disposée au voisinage de sa face avant et une cavité (CV) sur sa face arrière (F22) débouchant sur ladite ligne métallique du deuxième circuit intégré, ladite face du premier circuit intégré d'où saille ledit pilier conducteur (PC) et la face ...

METHOD FOR MAKING AN ELECTRICAL INTERCONNECT LEVEL

IMPROVEMENTS IN AND RELATING TO METHODS OF FORMING AN ELECTRICALLY CONDUCTIVE CONNECTION ON AN ELECTRONIC DEVICE

Method for making three-dimensional integrated structures, involves thinning substrates of integrated circuits by holding resin layer, and forming electrically conductive through-connection in thinned substrates

Procédé de réalisation de structures intégrées tridimensionnelles comprenant : a) un assemblage sur plusieurs premiers circuits intégrés (IC1) réalisés au sein d'une plaque semi-conductrice de plusieurs deuxièmes circuits intégrés (IC2) ; b) un dépôt d'une couche de résine encapsulant les deuxièmes circuits intégrés (IC2) et comblant les espaces latéraux entre les deuxièmes circuits intégrés (IC2) ; c) un amincissement des substrats des premiers (IC1) ou des deuxièmes circuits intégrés (IC2) en utilisant comme poignée de maintien la couche de résine ou le substrat des premiers circuits intégrés ; d) une réalisation d'au moins une liaison traversante électriquement conductrice dans le substrat de chaque circuit intégré aminci ; et e) une découpe des assemblages des premiers (IC1) et deuxièmes circuits intégrés (IC2) de manière à former les structures intégrées tridimensionnelles.

SEMICONDUCTOR DEVICE AND PROCESS FOR PRODUCING SAME

Integrated circuit device having through-silicon via structure and method of manufacturing the same

플립 칩형 반도체 이면용 필름, 다이싱 테이프 일체형 반도체 이면용 필름, 반도체 장치의 제조 방법 및 플립 칩형 반도체 장치

... 본 발명은, 피착체 상에 플립 칩-접속된 반도체 소자의 이면에 형성하기 위한 플립 칩형 반도체 이면용 필름으로서, 파장 532nm 또는 1064nm에서의 광선 투과율이 20% 이하이고, 레이저 마킹한 후의 마킹부와 마킹부 이외 부분 간의 콘트라스트가 20% 이상인 플립 칩형 반도체 이면용 필름에 관한 것이다.

마주보는（ＦＡＣＥ­ＴＯ­ＦＡＣＥ, Ｆ2Ｆ） 하이브리드 구조를 갖는 집적 회로(ＩＣ), ＩＣ 조립체, ＩＣ 제품 및 이들을 제조하는 방법, 그리고 이를 위한 컴퓨터-판독가능 매체

... 재분배 층(RDL)을 포함하는 집적 회로(IC) 제품이 제공되며, 재분배 층(RDL)은 IC 내에서 전기적 정보를 하나의 위치로부터 또 하나의 위치로 분배하도록 구성된 적어도 하나의 전도성 층을 갖는다. RDL은 또한 복수의 와이어 본드 패드들 및 복수의 솔더 패드들을 포함한다. 복수의 솔더 패드들 각각은 RDL과 직접적으로 전기적 통신을 하는 솔더 가용성 물질을 포함한다.

이미다졸 및 비스에폭사이드 화합물의 반응 산물을 함유하는 구리 전기도금조로부터 포토레지스트 정의된 특징부의 전기도금 방법

... 전기도금 방법은 실질적으로 균일한 형태를 갖는 포토레지스트 정의된 특징부의 도금을 가능케 한다. 전기도금 방법에는 포토레지스트 정의된 특징부를 전기도금하기 위해 이미다졸 및 비스에폭사이드의 반응 산물을 포함하는 구리 전기도금조가 포함된다. 이러한 특징부에는 기둥, 결합 패드 및 라인 스페이스 특징부가 포함된다.

반도체 패키지 및 반도체 패키지 모듈

... 범프를 통하여 회로 기판과 연결되는 반도체 패키지가 제공된다. 본 발명의 일 실시예에 따른 반도체 패키지는, 복수개의 접속 패드가 노출되도록 형성된 반도체 칩; 상기 각 접속 패드 상에 형성되며, 제1 필라부 및 상기 제1 필라부 상측에 형성되는 제1 솔더부를 포함하는 연결용 범프들; 상기 접속 패드 주변에서 상기 접속 패드의 상부 표면 보다 높은 위치에 형성되며, 솔더 유도부가 형성되어 있는 제2 필라부 및 상기 제2 필라부 상측에 형성되는 제2 솔더부를 포함하는 지지용 범프들;을 포함한다.

DIE LEVEL METAL DENSITY GRADIENT FOR IMPROVED FLIP CHIP PACKAGE RELIABILITY

마이크로 전자 패키지

... 마이크로 전자 패키지(100)는 기판(102)과 마이크로 전자 요소(130)를 포함하며, 마이크로 전자 요소는 면(134)과 이 면에서 노출되는 컨택(132)의 하나 이상의 컬럼(138, 139)을 가지며, 컨택(132)이 기판의 표면(120)에서 노출되는 대응하는 컨택을 바라보고 이 컨택에 연결된다. 축면(140)은 제1 방향(142)으로 연장하는 라인을 따라 마이크로 전자 요소의 면을 교차하고, 요소 컨택(132)의 컬럼에 대하여 센터링될 수 있다. 패키지 단자의 컬럼(104A, 104B)은 제1 방향으로 연장할 수 있다. 제2 표면의 중앙 영역(112)에서 노출된 제1 단자는 마이크로 전자 요소 내의 어드레스 가능 메모리 지점을 결정하기 위해 이용할 수 있는 어드레스 정보를 전달하도록 구성될 수 있다. 중앙 영역(112)은 패키지 단자의 컬럼들 간의 최소 피치(150)의 3.5배보다 크지 않은 폭(152)을 가질 수 있다. 축면은 중앙 영역을 교차할 수 있다.

ELECTRONIC DEVICE

개선된 인터커넥트 대역폭을 갖는 적층된 반도체 디바이스 패키지

... 본 개시는 적층된 반도체 디바이스 패키지 및 연관 기술들 및 구성들의 실시예들을 설명한다. 패키지는, 인터커넥트들, 및 일 측면에 부착되는 제 1 반도체 디바이스 및 대향 측면에 부착되는 제 2 반도체 디바이스를 갖는 패키징 기판을 포함할 수 있다. 디바이스들은, 패드 측면들이 기판의 대향하는 측면들 상에서 서로를 향하는 플립 칩 구성으로 부착될 수 있다. 디바이스들은 인터커넥트들에 의해 전기적으로 커플링될 수 있다. 디바이스들은 기판 상의 팬아웃 패드들에 전기적으로 커플링될 수 있다. 유전체 층은 기판의 제 2 측면에 커플링되고 제 2 디바이스를 캡슐화할 수 있다. 비아들은 전기 신호들을, 유전체 층을 통해 팬아웃 영역으로부터 그리고 유전체 층에 커플링된 재분배 층으로 라우팅할 수 있다. 다른 실시예들이 설명 및/또는 주장될 수 있다.

Via Connection Structures and Semiconductor Devices Having the Same, and methods of Fabricating the Sames

METHOD FOR MANUFACTURING A BUMP FOR A COPPER WIRE CHIP AND A UMB BY USING A NON ELECTROLYSIS COATING TECHNIQUE

PURPOSE: A method for fabricating a bump and a UBM by using a non electrolysis coating technique is provided to reduce the processing time and the manufacturing cost by coating a copper material onto a copper pad. CONSTITUTION: A copper coating layer(2) is formed on a copper pad(1) by coating a copper material on to the copper pad(2). The copper coating layer(2) is created by a non electrolysis coating technique. Then, a Ni coating layer(3) is formed on the copper coating layer(2) by coating a Ni material on to the copper coating layer(2) The Ni coating layer(3) is created by the non electrolysis coating technique. Alternatively, the copper coating layer(2) and the Ni coating layer(3) forming process is repeated several times so that a multi Ni/copper layer is formed. COPYRIGHT 2000 KIPO ...

PROCESS FOR PRODUCTION OF ELECTRONIC DEVICE, ELECTRONIC DEVICE, AND DEVICE FOR PRODUCTION OF ELECTRONIC DEVICE

THREE-DIMENSIONAL CHIP STACK AND METHOD OF FORMING THE SAME

BONDING METHOD FOR THREE-DIMENSIONAL INTEGRATED CIRCUIT AND THREE-DIMENSIONAL INTEGRATED CIRCUIT THEREOF

PURPOSE: A three-dimensional integrated circuit and a method for bonding the same are provided to simplify a manufacturing process by using a metal common deposition layer. CONSTITUTION: A layer(12) is deposited on a substrate(11). Light is irradiated on the layer to form a graphic structure. A metal common deposition layer(13) is formed on the layer by depositing a first metal and a second metal. A first integrated circuit is bonded to a second integrated circuit in a temperature to form a three-dimensional integrated circuit. COPYRIGHT KIPO 2013 ...

SEMICONDUCTOR PACKAGE CAPABLE OF PREVENTING A DEFLECTION PHENOMENON DUE TO VOLUME EXPANSION AND CONTRACTION OF A SEMICONDUCTOR CHIP AND A METHOD FOR MANUFACTURING THE SAME

PURPOSE: A semiconductor package and a method for manufacturing the same are provided to improve mounting reliability by improving bonding power between a substrate and semiconductor chips. CONSTITUTION: A substrate(100) comprises a connection terminal(102) having a groove(H) on the surface. Nano-powder(104) is arranged at the bottom of the connection terminal. The nano-powder comprises either copper or silver. A semiconductor chip(110) is flip-chip-bonded on the substrate by the medium of a connection member. The connection member comprises a bonding pad(112) and a bump(114) arranged on the bonding pad. Filler(108) is placed between the substrate and the semiconductor chip. The connection member is inserted in an opening of the filler. COPYRIGHT KIPO 2012 ...

DIRECTLY SAWING WAFERS COVERED WITH LIQUID MOLDING COMPOUND

SENSOR WITH A SINGLE ELECTRICAL CARRIER MEANS

Lead-Free Solder Ball

저온 부착을 위한 하이브리드 인터커넥트

... 증가된 z 높이 및 감소된 리플로우 온도를 갖는 인터커넥트에 관한 장치, 프로세스 및 시스템이 본 명세서에 기술되어 있다. 실시예들에서, 인터커넥트는 솔더 볼을 기판에 접속하기 위해 솔더 볼 및 솔더 페이스트를 포함할 수 있다. 솔더 볼 및/또는 솔더 페이스트는 상대적으로 낮은 용융점을 갖는 합금 및 상대적으로 높은 용융점을 갖는 합금으로 구성될 수 있다.

SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD

PURPOSE: To prevent a α-ray soft error of a semiconductor device wherein a solder bump is connected to a Cu wiring formed on an Al wiring. CONSTITUTION: A bump-land 6 connecting with the solder bump 10A and the Cu wiring 10 formed together with it in one-piece, consists of a stacked-layer film of a Cu film and a Ni film formed on its upper portion. The film thickness of the stacked-layer film is larger than film thickness of each of a photosensitive polyimide resin film 11 formed on the lower layers of the Cu wiring 10 and the bump-land 10A, an inorganic passivation film 26, a third Al wiring 25, the bump-pad BP, and a second inter-layer insulating film 24. That is, the bump-land 10A is constructed by film thickness larger than those of an insulating component and wiring component which are interposed between a MISFET (n- channel-type MISFETQn and p-channel-type MISFETQp) and the bump-land 10A. © KIPO & JPO 2003 ...

METHOD OF ELECTROPLATING PHOTORESIST DEFINED FEATURES FROM COPPER ELECTROPLATING BATHS CONTAINING REACTION PRODUCTS OF ALPHA AMINO ACIDS AND BISEPOXDES

THERMAL INTERFACE MATERIAL HAVING DIFFERENT THICKNESSES IN PACKAGES

Preparation method of semiconductor device, and semiconductor device

Semiconductor product with interlocking metal-to-metal bonds and method for manufacturing thereof

High quality factor inductor implemented in wafer level packaging (WLP)

Some novel features pertain to a first example provides a semiconductor device that includes a printed circuit board (PCB), asset of solder balls and a die. The PCB includes a first metal layer. The set of solder balls is coupled to the PCB. The die is coupled to the PCB through the set of solder balls. The die includes a second metal layer and a third metal layer. The first metal layer of the PCB, the set of solder balls, the second and third metal layers of the die are configured to operate as an inductor in the semiconductor device. In some implementations, the die further includes a passivation layer. The passivation layer is positioned between the second metal layer and the third metal layer. In some implementations, the second metal layer is positioned between the passivation layer and the set of solder balls.

Epoxy resin composition for sealing packing of semiconductor, semiconductor device, and manufacturing method thereof

An epoxy resin composition for a underfilling of a semiconductor comprising an epoxy resin, an acid anhydride, a curing accelerator and a flux agent as essential components, wherein the curing accelerator is a quaternary phosphonium salt, as well as a semiconductor device and manufacturing method employing the same.

Semiconductor packages

Semiconductor packages are provided. One of the semiconductor packages includes a first chip, a second chip and a molding compound. The first chip has at least one first via and a protection layer thereon, and the at least one first via is formed in the protection layer. The second chip has at least one second via thereon. The molding layer encapsulates the first and second chips. The at least one second via is disposed in and contact with the molding layer, and top surfaces of the protection layer, the at least one first via and the at least one second via are substantially coplanar with a top surface of the molding layer.

Semiconductor device and process for manufacturing the same

A semiconductor device has a pad structure with a ring-shaped stress buffer layer between a metal pad and an under-bump metallization (UBM) layer. The stress buffer layer is formed of a dielectric layer with a dielectric constant less than 3.5, a polymer layer, or an aluminum layer. The stress buffer layer is a circular ring, a square ring, an octagonal ring, or any other geometric ring.

Semiconductor device and method of manufacturing semiconductor device

A semiconductor device includes a semiconductor element; a pad electrode that is formed on the semiconductor element; an alignment mark that is formed on the semiconductor element; a connection electrode that is formed on the pad electrode; and an underfill resin that is formed to cover the connection electrode. The height of the alignment mark from the semiconductor element is greater than that of the connection electrode.

Semiconductor element and a producing method for the same, and a semiconductor device and a producing method for the same

A columnar bump formed of copper etc. is formed on a wiring film of a semiconductor chip through an interconnected film and an adhesive film in a wafer unit by electrolytic plating in which package formation is possible. An oxidation prevention film is formed of such as gold on an upper surface or a part of the upper surface and side surface. A wet prevention film of such as an oxide film is formed on the columnar bump side as needed. If this bump is soldered to the pad on a packaging substrate, solder gets wet in the whole region of the columnar bump upper surface and only a part of the side surface. Stabilized and reliable junction form can be thus formed. Moreover, since the columnar bump does not fuse, the distance between a semiconductor board and a packaging board is not be narrowed by solder.

Semiconductor device, method for manufacturing semiconductor device, circuit board, and electronic instrument

A semiconductor device includes: a semiconductor substrate having an active surface and a back surface; an integrated circuit formed on the active surface; a feedthrough electrode penetrating the semiconductor substrate, and projecting from the active surface and the back surface; a first resin layer formed on the active surface, having a thickness greater than a height of a portion of the feedthrough electrode that projects from the active surface, and having an opening portion for exposing at least a portion of the feedthrough electrode; a wiring layer which is formed on the first resin layer, and which is connected to the feedthrough electrode through the opening portion; and an external connecting terminal connected to the wiring layer.

Vertical semiconductor device with thinned substrate

A vertical semiconductor device (e. g. a vertical power device, an IGBT device, a vertical bipolar transistor, a UMOS device or a GTO thyristor) is formed with an active semiconductor region, within which a plurality of semiconductor structures have been fabricated to form an active device, and below which at least a portion of a substrate material has been removed to isolate the active device, to expose at least one of the semiconductor structures for bottom side electrical connection and to enhance thermal dissipation. At least one of the semiconductor structures is preferably contacted by an electrode at the bottom side of the active semiconductor region.

Device and method for an integrated ultra-high-density device

A device and method for an integrated device includes a first redistribution layer comprising one or more first conductors, one or more first dies mounted to a first surface of the first redistribution layer and electrically coupled to the first conductors, one or more first posts having first ends attached to the first dies and second ends opposite the first ends, one or more second posts having third ends attached to the first surface of the first redistribution layer and fourth ends opposite the third ends, and a second redistribution layer comprising one or more second conductors, the second redistribution layer being attached to the second ends of the first posts and to the fourth ends of the second posts. In some embodiments, the integrated device further includes a heat spreader mounted to a second surface of the first redistribution layer. The second surface is opposite the first surface.

Semiconductor device and method of forming pad layout for flipchip semiconductor die

A semiconductor device has a semiconductor die with a die pad layout. Signal pads in the die pad layout are located primarily near a perimeter of the semiconductor die, and power pads and ground pads are located primarily inboard from the signal pads. The signal pads are arranged in a peripheral row or in a peripheral array generally parallel to an edge of the semiconductor die. Bumps are formed over the signal pads, power pads, and ground pads. The bumps can have a fusible portion and non-fusible portion. Conductive traces with interconnect sites are formed over a substrate. The bumps are wider than the interconnect sites. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surfaces of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate.

Die encapsulation in oxide bonded wafer stack

Structures and methods of fabricating semiconductor wafer assemblies that encapsulate one or die in a cavity etched into an oxide bonded semiconductor wafer stack. The methods generally include the steps of positioning the die in the cavity, mechanically and electrically mounting the die to the wafer stack, and encapsulating the die within the cavity by bonding a lid wafer to the wafer stack in one of multiple ways. Semiconductor processing steps are applied to construct the assemblies (e.g., deposition, annealing, chemical and mechanical polishing, etching, etc.) and connecting the die (e.g., bump bonding, wire interconnecting, ultrasonic bonding, oxide bonding, etc.) according to the embodiments described above.

Method for forming the package structure

A method for forming the package structure is provided. The method includes forming a die structure over a first surface of a first substrate, and forming a plurality of electrical connectors below a second surface of the first substrate. The method also includes forming a first protruding structure below the second surface of the first substrate, and the electrical connectors are surrounded by the first protruding structure. The method further includes forming a second protruding structure over a second substrate, and bonding the first substrate to the second substrate. The electrical connectors are surrounded by the second protruding structure, and the first protruding structure does not overlap with the second protruding structure.

PLATING BATH AND METHOD

PLATING BATH AND METHODAbstract of the DisclosureSilver electroplating baths having certain sulfide compounds and methods of electrodepositing a silver-containing layer using these baths are disclosed. Such electroplating baths are useful to provide silver-containing solder deposits having reduced void formation and improved within-die uniformity.NO FIGURE ...

Manufacturing method of package-on-package structure

SEMICONDUCTOR DEVICE PACKAGE AND MANUFACTURING METHOD THEREOF

Double molded chip scale package

Chip scale semiconductor packages and methods for making and using the same are described. The chip scale semiconductor packages (CSPs) contain a die with an integrated circuit device, a patterned plating layer, and a second interconnect structure formed from a Cu etched substrate that has a portion of an upper surface connected to the patterned plating layer, a side surface, and a bottom surface. The die can be attached to the patterned plating layer by a first interconnect structure that uses wirebonding or that uses a flip chip attachment process. The CSP contains a double molded structure where a first molding layer encapsulates the die, the patterned plating layer, the first interconnect structure, and the upper surface of the second interconnect structure. The second molding layer encapsulates the side surface of the second interconnect structure without encapsulating the bottom surface of the second interconnect structure. With such a configuration, the second molding layer helps control warpage during the manufacturing process and no printed circuit board (PCB) substrate is needed when the package is used in an electronic device since the signal routing is performed by the second interconnect structure. Other embodiments are described.

Method for manufacture of integrated circuit package system with protected conductive layers for pads

A method for manufacture of an integrated circuit package system includes: providing an integrated circuit die having a contact pad; forming a protection cover over the contact pad; forming a passivation layer having a first opening over the protection cover with the first opening exposing the protection cover; developing a conductive layer over the passivation layer; forming a pad opening in the protection cover for exposing the contact pad having the conductive layer partially removed; and an interconnect directly on the contact pad and only adjacent to the protection cover and the passivation layer.

Method of forming cu pillar capped by barrier layer

A nickel barrier layer is formed on an upper sidewall surface of a Cu pillar. A mask layer with an opening for defining the Cu pillar window has an upper portion and a lower portion. The upper portion of the mask layer is removed after the formation of the Cu pillar so as to expose the upper sidewall surface of the Cu pillar. The nickel barrier layer is then deposited on the exposed sidewall surface of the Cu pillar followed by removing and the lower portion of the mask layer.

Microelectronic packages with dual or multiple-etched flip-chip connectors

A packaged microelectronic element includes a microelectronic element having a front surface and a plurality of first solid metal posts extending away from the front surface. A substrate has a major surface and a plurality of conductive elements exposed at the major surface and joined to the first solid metal posts. In particular examples, the conductive elements can be bond pads or can be second posts having top surfaces and edge surfaces extending at substantial angles away therefrom. Each first solid metal post includes a base region adjacent the microelectronic element and a tip region remote from the microelectronic element, the base region and tip region having respective concave circumferential surfaces. Each first solid metal post has a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region.

Conductive Sidewall for Microbumps

Electromigration in microbump connections causes voids in the microbumps, which reduces the lifetime of an integrated circuit containing the microbump. Electromigration lifetime may be increased in microbumps by forming a copper shell around the solder. The copper shell of one microbump contacts the copper shell of a second microbump to enclose the solder of the microbump connection. The copper shell allows higher current densities through the microbump. Thus, smaller microbumps may be manufactured on a smaller pitch without suffering failure from electromigration. Additionally, the copper shell reduces shorting or bridging between microbump connections on a substrate.

Semiconductor Device and Method of Forming RDL Wider than Contact Pad along First Axis and Narrower than Contact Pad Along Second Axis

A semiconductor device has a semiconductor die and first conductive layer formed over a surface of the semiconductor die. A first insulating layer is formed over the surface of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. An opening is formed in the second insulating layer over the first conductive layer. A second conductive layer is formed in the opening over the first conductive layer and second insulating layer. The second conductive layer has a width that is less than a width of the first conductive layer along a first axis. The second conductive layer has a width that is greater than a width of the first conductive layer along a second axis perpendicular to the first axis. A third insulating layer is formed over the second conductive layer and first insulating layer.

Film for flip chip type semiconductor back surface, dicing tape-integrated film for semiconductor back surface, process for producing semiconductor device, and flip chip type semiconductor device

The present invention relates to a film for flip chip type semiconductor back surface to be formed on a back surface of a semiconductor element flip chip-connected onto an adherend, in which the film for flip chip type semiconductor back surface before thermal curing has, at the thermal curing thereof, a volume contraction ratio within a range of 23° C. to 165° C. of 100 ppm/° C. to 400 ppm/° C.

Mechanisms for forming copper pillar bumps using patterned anodes

The mechanisms of preparing bump structures described by using patterned anodes may simplify bump-making process, reduce manufacturing cost, and improve thickness uniformity within die and across the wafer. In addition, the mechanisms described above allow forming bumps with different heights to allow bumps to be integrated with elements on a substrate with different heights. Bumps with different heights expand the application of copper post bumps to enable further chip integration.

Conductive connection structure with stress reduction arrangement for a semiconductor device, and related fabrication method

A semiconductor device disclosed herein includes a conductive connection structure having a stepped profile that serves as a stress relief feature. The conductive connection structure includes a stress buffer arrangement for a contact pad. The stress buffer arrangement has a stepped via that terminates at the contact pad, and the stepped via has a plurality of inwardly sloped and concentric sections in a stacked orientation. The connection structure also includes underbump metallization overlying at least a portion of the contact pad and lining the stepped via, and a conductive connection element coupled to the underbump metallization. The conductive connection element fills the lined recess.

Semiconductor device having pad structure with stress buffer layer

A semiconductor device has a pad structure with a ring-shaped stress buffer layer between a metal pad and an under-bump metallization (UBM) layer. The stress buffer layer is formed of a dielectric layer with a dielectric constant less than 3.5, a polymer layer, or an aluminum layer. The stress buffer layer is a circular ring, a square ring, an octagonal ring, or any other geometric ring.

Semiconductor device and manufacturing method thereof

Semiconductor devices of embodiments include a plurality of solder bumps electrically connected on a plurality of electrode pads disposed on a semiconductor substrate in parallel at a pitch of 40 μm or less via under bump metals. The ratio of the diameter (the top diameter) of the portion of each solder bump most away from the semiconductor substrate and the diameter (the bottom diameter) of the bottom side of each solder bump is 1:1 to 1:4.

Semiconductor assembly and semiconductor package including a solder channel

Semiconductor packages connecting a semiconductor chip to an external device by bumps are provided. The semiconductor packages may include a connection pad on a semiconductor chip, a connecting bump on and configured to be electrically connected to the connection pad and a supporting bump on the semiconductor chip and configured to be electrically isolated from the connection pad. The connection bump may include a first pillar and a first solder ball and the supporting bump may include a second pillar and a second solder ball. The semiconductor packages may further include a solder channel in the second pillar configured to allow a portion of the second solder ball to extend into the solder channel along a predetermined direction.

Semiconductor device, method for forming the same, and data processing system

A semiconductor device includes a semiconductor substrate, a first interlayer insulating film over the semiconductor substrate, a first interconnect over the first interlayer insulating film, and a via plug penetrating the semiconductor substrate and the first interlayer insulating film. The via plug is coupled to the first interconnect.

Microelectronic assemblies having compliancy and methods therefor

A microelectronic assembly is disclosed that includes a semiconductor wafer with contacts, compliant bumps of dielectric material overlying the first surface of the semiconductor wafer, and a dielectric layer overlying the first surface of the semiconductor wafer and edges of the compliant bumps. The compliant bumps have planar top surfaces which are accessible through the dielectric layer. Conductive traces may be electrically connected with contacts and extend therefrom to overlie the planar top surfaces of the compliant bumps. Conductive elements may overlie the planar top surfaces in contact with the conductive traces.

Conductive feature for semiconductor substrate and method of manufacture

A conductive feature on a semiconductor component is disclosed. A first passivation layer is formed over a substrate. A bond pad is formed over the first passivation layer. A second passivation layer overlies the first passivation layer and the bond pad. The second passivation layer has a first opening overlying the bond pad and a plurality of second openings exposing a top surface of the first passivation layer. A buffer layer overlies the second passivation layer and fills the plurality of second openings. The buffer layer has a third opening overlapping the first opening and together exposes a portion the bond pad. The combined first opening and third opening has sidewalls. An under bump metallurgy (UBM) layer overlies the sidewalls of the combined first opening and third opening, and contacts the exposed portion of the bond pad. A conductive feature overlies the UBM layer.

Structures and methods for improving solder bump connections in semiconductor devices

Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The structure includes a trench formed in a dielectric layer which has at least a portion thereof devoid of a fluorine boundary layer. The structure further includes a copper wire in the trench having at least a bottom portion thereof in contact with the non-fluoride boundary layer of the trench. A lead free solder bump is in electrical contact with the copper wire.

Mechanisms for resistivity measurement of bump structures

The embodiments described above provide mechanisms for bump resistivity measurement. By using designated bumps on one or more corners of dies, the resistivity of bumps may be measured without damaging devices and without a customized probing card. In addition, bump resistivity may be collected across the entire wafer. The collected resistivity data may be used to monitor the stability and/or health of processes used to form bumps and their underlying layers.

Semiconductor Device and Method of Forming an Inductor Within Interconnect Layer Vertically Separated from Semiconductor Die

A semiconductor device has an adhesive layer formed over a carrier. A semiconductor die has bumps formed over an active surface of the semiconductor die. The semiconductor die is mounted to the carrier with the bumps partially disposed in the adhesive layer to form a gap between the semiconductor die and adhesive layer. An encapsulant is deposited over the semiconductor die and within the gap between the semiconductor die and adhesive layer. The carrier and adhesive layer are removed to expose the bumps from the encapsulant. An insulating layer is formed over the encapsulant. A conductive layer is formed over the insulating layer in a wound configuration to exhibit inductive properties and electrically connected to the bumps. The conductive layer is partially disposed within a footprint of the semiconductor die. The conductive layer has a separation from the semiconductor die as determined by the gap and insulating layer.

Bonding pad structure and integrated circuit comprising a plurality of bonding pad structures

A bonding pad structure positioned on an integrated circuit includes a connecting pad, an insulation layer and a gold bump. The connecting pad is formed on the integrated circuit. The insulation layer is formed on the connecting pad, where the insulation layer has only one opening and a shape of the opening includes at least a bend. The gold bump is formed on the insulation layer, where the gold bump is electrically connected to the connecting pad through the opening of the insulation layer.

Semiconductor chip assembly and method for making same

A microelectronic assembly may include a substrate including a rigid dielectric layer having electrically conductive elements, a microelectronic element having a plurality of contacts exposed at a face thereof, and conductive vias extending through a compliant dielectric layer overlying the rigid dielectric layer. The vias electrically connect the substrate contacts respectively to the conductive elements, and the substrate contacts are joined respectively to the contacts of the microelectronic element. The vias, compliant layer and substrate contacts are adapted to appreciably relieve stress at the substrate contacts associated with differential thermal contact and expansion of the assembly.

Methods for vacuum assisted underfilling

Methods for applying an underfill with vacuum assistance. The method may include dispensing the underfill onto a substrate proximate to at least one exterior edge of an electronic device attached to the substrate. A space between the electronic device and the substrate is evacuated through at least one gap in the underfill. The method further includes heating the underfill to cause the underfill to flow into the space. Because a vacuum condition is supplied in the open portion of the space before flow is initiated, the incidence of underfill voiding is lowered.

Increasing Dielectric Strength by Optimizing Dummy Metal Distribution

A method includes providing a wafer representation including a metal layer and a plurality of bump pads over the metal layer, wherein the metal layer includes directly-under-bump-pad regions. A solid metal pattern is inserted into the metal layer, wherein the solid metal pattern includes first parts in the directly-under-bump-pad regions and second parts outside the directly-under-bump-pad regions. Portions of the second parts of the solid metal pattern are removed, wherein substantially no portions of the first parts of the solid metal pattern are removed. The remaining portions of the solid metal pattern not removed during the step of removing form dummy metal patterns. The dummy metal patterns and the plurality of bump pads are implemented in a semiconductor wafer.

Packaging substrate with conductive structure

A packaging substrate with conductive structure is provided, including a substrate body having at least one conductive pad on a surface thereof, a stress buffer metal layer disposed on the conductive pad and a thickness of the stress buffer metal layer being 1-20 μm, a solder resist layer disposed on the substrate body and having at least one opening therein for correspondingly exposing a portion of top surface of the stress buffer metal layer, a metal post disposed on a central portion of the surface of the stress buffer metal layer, and a solder bump covering the surfaces of the metal post. Therefore, a highly reliable conductive structure is provided, by using the stress buffer metal layer to release thermal stresses, and using the metal post and the solder bump to increase the height of the conductive structure.

Integrated structures of high performance active devices and passive devices

Integrated structures having high performance CMOS active devices mounted on passive devices are provided. The structure includes an integrated passive device chip having a plurality of through wafer vias, mounted to a ground plane. The structure further includes at least one CMOS device mounted on the integrated passive device chip using flip chip technology and being grounded to the ground plane through the through wafer vias of the integrated passive device chip.

Compliant spring interposer for wafer level three dimensional (3d) integration and method of manufacturing

The present invention is an apparatus for integrating multiple devices. The apparatus includes a substrate having a first via and a second via, a semiconductor chip positioned on a top portion of the substrate and positioned between the first via and the second via, first and second bumps positioned on the semiconductor chip, and an interposer wafer having a first interposer spring assembly and a second interposer spring assembly, the first interposer spring assembly having a first interposer spring and a first electrical connection attached to the first interposer spring, and the second interposer spring assembly having a second interposer spring and a second electrical connection attached to the second interposer spring.

Customized rf mems capacitor array using redistribution layer

Disclosed is a method for fabricating a customized micro-electromechanical systems (MEMS) integrated circuit using at least one redistribution layer. The method includes steps of providing a substrate on which MEMS components are fabricated and coupling predetermined ones of the MEMS components via the redistribution traces.

Semiconductor device and method of fabricating the semiconductor device

A semiconductor device includes a first device including a first substrate and a first external connection terminal for connecting outside the first device; a second device stacked on the first device, the second device including a second substrate and a second external connection terminal for connecting outside the second device; an adhesive pattern disposed between the first device and second device, the adhesive pattern disposed in locations other than locations where the first external connection terminal and second external connection terminal are disposed, and the adhesive pattern causing the first device and second device, when stacked, to be spaced apart by a predetermined distance; and a plated layer disposed between and electrically and physically connecting the first external connection terminal and the second external connection terminal.

Semiconductor Device and Method of Forming Narrow Interconnect Sites on Substrate with Elongated Mask Openings

A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the semiconductor die. A plurality of conductive traces is formed over a surface of the substrate with interconnect sites. A masking layer is formed over the surface of the substrate. The masking layer has a plurality of parallel elongated openings each exposing at least two of the conductive traces and permitting a flow of bump material along a length of the plurality of conductive traces within the plurality of elongated openings while preventing the flow of bump material past a boundary of the plurality of elongated openings. One of the conductive traces passes beneath at least two of the elongated openings. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate.

Chip package with plank stack of semiconductor dies

In a chip package, semiconductor dies in a vertical stack of semiconductor dies or chips (which is referred to as a ‘plank stack’) are separated by a mechanical spacer (such as a filler material or an adhesive). Moreover, the chip package includes a substrate at a right angle to the plank stack, which is electrically coupled to the semiconductor dies along an edge of the plank stack. In particular, electrical pads proximate to a surface of the substrate (which are along a stacking direction of the plank stack) are electrically coupled to pads that are proximate to edges of the semiconductor dies by an intervening conductive material, such as: solder, stud bumps, plated traces, wire bonds, spring connectors, a conductive adhesive and/or an anisotropic conducting film. Note that the chip package may facilitate high-bandwidth communication of signals between the semiconductor dies and the substrate.

Semiconductor Device and Method of Forming a Wafer Level Package Structure Using Conductive Via and Exposed Bump

A semiconductor device has a carrier. A semiconductor wafer including a semiconductor die is mounted to the carrier with an active surface of the semiconductor die facing away from the carrier. A plurality of bumps is formed over the active surface of the semiconductor die. An opening is formed in a periphery of the semiconductor die. An encapsulant is deposited over the carrier and semiconductor die, in the opening, and around the plurality of bumps such that an exposed portion of the plurality of bumps is devoid of encapsulant. A conductive via is formed through the encapsulant, within the opening, and extends to the carrier. A conductive layer is formed over the encapsulant and electrically connects to the conductive via and the exposed portion of the plurality of bumps. The carrier is removed to expose an end of the conductive via.

Vertical ballast technology for power hbt device

Power amplification devices are disclosed having a vertical ballast configuration to prevent thermal runaway in at least one stack of bipolar transistors formed on a semiconductor substrate. To provide a negative feedback to prevent thermal runaway in the bipolar transistors, a conductive layer is formed over and coupled to the stack. A resistivity of the conductive layer provides an effective resistance that prevents thermal runaway in the bipolar transistors. The vertical placement of the conductive layer allows for vertical heat dissipation and thus provides ballasting without concentrating heat.

Semiconductor device and manufacturing method of the same

A semiconductor device, includes: a wiring substrate, a stacked body mounted on the wiring substrate, an underfill layer filled into gaps between respective semiconductor chips of the stacked body; and a molding body made up of a molding resin covered and formed at outside of the stacked body and so on. The underfill layer is made up of a cured product of a resin material containing an amine-based curing agent, and the cured product has a Tg of 65° C. or more and 100° C. or less.

Apparatuses and methods to enhance passivation and ild reliability

Some embodiments of the present invention include apparatuses and methods relating to processing and packaging microelectronic devices that reduce stresses on and limit or eliminate crack propagation in the devices.

Solder ball contact susceptible to lower stress

A solder ball contact and a method of making a solder ball contact includes: a first insulating layer with a via formed on an integrated circuit (IC) chip and a metal pad; an under bump metallurgy (UBM) structure disposed within the via and on a portion of the first insulating layer, surrounding the via; a second insulating layer formed on an upper surface of an outer portion of the UBM structure that is centered on the via; and a solder ball that fills the via and is disposed above an upper surface of an inner portion of the UBM structure that contacts the via, in which the UBM structure that underlies the solder ball is of a greater diameter than the solder ball.

Bridging arrangement and method for manufacturing a bridging arrangement

A bridging arrangement for coupling a first terminal to a second terminal includes a plurality of particles of a first type forming at least one path between the first terminal and the second terminal, wherein the particles of the first type are attached to each other; a plurality of particles of a second type arranged in a vicinity of a contact region between a first particle of the first type and a second particle of the first type, wherein at least a portion of the plurality of particles of the second type is attached to the first particle of the first type and the second particle of the first type.

Semiconductor Device and Method of Making a Semiconductor Device

A semiconductor device and a method of manufacturing a semiconductor device are disclosed. An embodiment comprises forming a bump on a die, the bump having a solder top, melting the solder top by pressing the solder top directly on a contact pad of a support substrate, and forming a contact between the die and the support substrate.

Method of manufacturing chip-stacked semiconductor package

A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.

Electrode arrays and methods of fabricating the same using printing plates to arrange particles in an array

Electrode arrays and methods of fabricating the same using a printing plate to arrange conductive particles in alignment with an array of electrodes are provided. In one embodiment, a semiconductor device comprises: a semiconductor topography comprising an array of electrodes disposed upon a semiconductor substrate; a dielectric layer residing upon the semiconductor topography; and at least one conductive particle disposed in or on the dielectric layer in alignment with at least one of the array of electrodes.

Method of manufacturing semiconductor device

Provided is a technology of suppressing, in forming an initial ball by using an easily oxidizable conductive wire and pressing the initial ball onto a pad to form a press-bonded ball, an initial ball from having a shape defect, thereby reducing damage to the pad. To achieve this, a ball formation unit is equipped with a gas outlet portion for discharging an antioxidant gas and a discharging path through this gas outlet portion is placed in a direction different from a direction of introducing the antioxidant gas into a ball formation portion. Such a structure widens a region for discharging the antioxidant gas, making it possible to prevent a gas flow supplied from the side of one side surface of the ball formation portion from being reflected by the other side surface facing with the one side surface and thereby forming a turbulent flow.

Method for producing reconstituted wafers and method for producing semiconductor devices

In order to provide a method for producing semiconductor devices that can use the highly productive W to W method, and achieve a high yield, a method for producing semiconductor devices comprises a step (S 401 ) in which a reconstituted wafer is prepared by replacing defective chips with non-defective chips, a step (S 403 ) in which the reconstituted wafer and the base wafer are connected to one another by laminating, a step (S 406 ) in which through-electrodes are formed in the reconstituted wafer, and a step (S 409 ) in which a separate reconstituted wafer is laminated onto and connected to the reconstituted wafer having through-electrodes.

Metal Bump Formation

A system and method for forming metal bumps is provided. An embodiment comprises attaching conductive material to a carrier medium and then contacting the conductive material to conductive regions of a substrate. Portions of the conductive material are then bonded to the conductive regions using a bonding process to form conductive caps on the conductive regions, and residual conductive material and the carrier medium are removed. A reflow process is used to reflow the conductive caps into conductive bumps.

Low profile package and method

In a method aspect, a multiplicity of ICs are attached to routing on a structurally supportive carrier (such as a wafer). The dice are encapsulated and then both the dice and the encapsulant layer are thinned with the carrier in place. A second routing layer is formed over the first encapsulant layer and conductive vias are provided to electrically couple the first and second routing layers as desired. External I/O contacts (e.g. solder bumps) are provided to facilitate electrical connection of the second routing layer (or a subsequent routing layer in stacked packages) to external devices. A contact encapsulant layer is then formed over the first encapsulant layer and the second routing layer in a manner that embeds the external I/O contacts at least partially therein. After the contact encapsulant layer has been formed, the carrier itself may be thinned significantly and singulated to provide a number of very low profile packages. The described approach can also be used to form stacked multi-chip packages.

Method of manufacturing semiconductor device

To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W 1 and a narrow part (a second portion) with a second width W 2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.

Bump-on-trace (bot) structures

A bump-on-trace (BOT) structure is described. The BOT structure includes a first work piece with a metal trace on a surface of the first work piece, wherein the metal trace has a first axis. The BOT structure further includes a second work piece with an elongated metal bump, wherein the elongated metal bump has a second axis, wherein the second axis is at a non-zero angle from the first axis. The BOT structure further includes a metal bump, wherein the metal bump electrically connects the metal trace and the elongated metal bump. A package having a BOT structure and a method of forming the BOT structure are also described.

Semiconductor chip and flip-chip package comprising the same

A semiconductor chip includes stress-relief to mitigate the effects of differences in coefficients of thermal expansion (CTE) between a printed circuit board (PCB) and a semiconductor chip and a flip-chip package including the semiconductor chip. The semiconductor chip includes a stress-relief buffer coupling a bump and a semiconductor chip pad.

Solder Bump with Inner Core Pillar in Semiconductor Package

A flip chip semiconductor package has a substrate with a plurality of active devices. A contact pad is formed on the substrate in electrical contact with the plurality of active devices. A passivation layer, second barrier layer, and adhesion layer are formed between the substrate and an intermediate conductive layer. The intermediate conductive layer is in electrical contact with the contact pad. A copper inner core pillar is formed by plating over the intermediate conductive layer. The inner core pillar has a rectangular, cylindrical, toroidal, or hollow cylinder form factor. A solder bump is formed around the inner core pillar by plating solder material and reflowing the solder material to form the solder bump. A first barrier layer and wetting layer are formed between the inner core pillar and solder bump. The solder bump is in electrical contact with the intermediate conductive layer.

Interconnection and assembly of three-dimensional chip packages

In a chip package, semiconductor dies in a vertical stack of semiconductor dies or chips (which is referred to as a ‘plank stack’) are aligned by positive features that are mechanically coupled to negative features recessed below the surfaces of adjacent semiconductor dies. Moreover, the chip package includes an interposer plate at approximately a right angle to the plank stack, which is electrically coupled to the semiconductor dies along an edge of the plank stack. In particular, electrical pads proximate to a surface of the interposer plate (which are along a stacking direction of the plank stack) are electrically coupled to pads that are proximate to edges of the semiconductor dies by an intervening conductive material, such as solder balls or spring connectors. Note that the chip package may facilitate high-bandwidth communication of signals between the semiconductor dies and the interposer plate.

Adhesive film for semiconductor device, film for backside of flip-chip semiconductor, and dicing tape-integrated film for backside of semiconductor

Provided is an adhesive film for a semiconductor device that is capable of having the same physical properties as these at the time of manufacture even after it is stored for a long time. The adhesive film for a semiconductor device of the present invention contains a thermosetting resin, and in which the amount of reaction heat generated in a temperature range of ±80° C. of a reaction heat peak temperature measured by a differential scanning calorimeter after the adhesive film is stored at 25° C. for 4 weeks is 0.8 to 1 time the amount of reaction heat generated before storage.

Semiconductor device, semiconductor device unit, and semiconductor device production method

An example of a semiconductor device according to the present invention includes: a protective film ( 1 ) which has an opening to expose a part of the surface of an electrode pad ( 4 ) and covers the surface of the electrode pad ( 4 ) excluding the opening; and a bump ( 6 ) which is electrically connected with the electrode pad ( 4 ) through the opening of the protective film ( 1 ) and has a part exposed outside within the area of the electrode pad ( 4 ), wherein probe marks ( 7 ) are formed by a probe brought into contact with the electrode pad ( 4 ) for electrical characteristic inspection, and the probe marks ( 7 ) are positioned within a region where the protective film ( 1 ) is formed and are covered by the protective film ( 1 ).

TCE Compensation for Package Substrates for Reduced Die Warpage Assembly

A method for assembling die packages includes attaching contacts on a first side of a plurality of first die to substrate pads on a top surface of a composite carrier. The composite carrier includes a package substrate including at least one embedded metal layer having its bottom surface secured to a semiconductor wafer. The composite carrier minimizes effects of the CTE mismatch between the die and the package substrate during assembly reduces warpage of the die. After the attaching, the semiconductor wafer is removed from the package substrate. Electrically conductive connectors are attached to the bottom surface of the package substrate, and the package substrate is sawed to form a plurality of singulated die packages.

Integrated Inductor

A system and method for providing an integrated inductor with a high Quality factor (Q) is provided. An embodiment comprises a magnetic core that is in a center of a conductive spiral. The magnetic core increases the inductance of the integrated inductor to allow the inductor to be used in applications such as a RF choke. The magnetic core may be formed in the same manner and time as an underbump metallization.

Semiconductor Devices and Methods of Manufacturing and Packaging Thereof

Semiconductor devices and methods of manufacturing and packaging thereof are disclosed. In one embodiment, a semiconductor device includes an integrated circuit and a plurality of copper pillars coupled to a surface of the integrated circuit. The plurality of copper pillars has an elongated shape. At least 50% of the plurality of copper pillars is arranged in a substantially centripetal orientation.

Solder cap bump in semiconductor package and method of manufacturing the same

A semiconductor package with improved height uniformity of solder cap bumps therein is disclosed. In one embodiment, the semiconductor package includes a semiconductor substrate comprising a plurality of pads spacedly disposed on a top surface of the substrate, and a passivation layer formed on top of the pads, wherein a plurality of pad openings are created to expose at least a portion of the pads; a plurality of solder cap bumps formed at the pad openings of the passivation layer; and a carrier substrate having a plurality of bond pads electrically connected to the solder caps of the solder cap bumps on the semiconductor substrate. The solder cap bump includes a solder cap on top of a conductive pillar, and a patternable layer can be coated and patterned on a top surface of the conductive pillar to define an area for the solder ball to be deposited. The deposited solder ball can be reflowed to form the solder cap.

Multi-Chip and Multi-Substrate Reconstitution Based Packaging

Embodiments for multi-chip and multi-substrate reconstitution based packaging are provided. Example packages are formed using substrates from a reconstitution. substrate panel or strip. The reconstitution substrate panel or strip may include known good substrates of same or different material types and/or same of different layer counts and sizes. As such, different combinations of reconstitution substrates and chips can be used within the same package, thereby allowing substrate customization according to semiconductor chip block(s) and types contained in the package.

Forming Packages Having Polymer-Based Substrates

A method includes applying a polymer-comprising material over a carrier, and forming a via over the carrier. The via is located inside the polymer-comprising material, and substantially penetrates through the polymer-comprising material. A first redistribution line is formed on a first side of the polymer-comprising material. A second redistribution line is formed on a second side of the polymer-comprising material opposite to the first side. The first redistribution line is electrically coupled to the second redistribution line through the via.

Zener Diode Structure and Process

A vertically stacked, planar junction Zener diode is concurrently formed with epitaxially grown FET raised S/D terminals. The structure and process of the Zener diode are compatible with Gate-Last high-k FET structures and processes. Lateral separation of diode and transistor structures is provided by modified STI masking. No additional photolithography steps are required. In some embodiments, the non junction face of the uppermost diode terminal is silicided with nickel to additionally perform as a copper diffusion barrier.

Power management applications of interconnect substrates

Various applications of interconnect substrates in power management systems are described.

Semiconductor Device and Method of Forming Interposer Frame Electrically Connected to Embedded Semiconductor Die

A semiconductor device has an interposer frame mounted over a carrier. A semiconductor die has an active surface and bumps formed over the active surface. The semiconductor die can be mounted within a die opening of the interposer frame or over the interposer frame. Stacked semiconductor die can also be mounted within the die opening of the interposer frame or over the interposer frame. Bond wires or bumps are formed between the semiconductor die and interposer frame. An encapsulant is deposited over the interposer frame and semiconductor die. An interconnect structure is formed over the encapsulant and bumps of the first semiconductor die. An electronic component, such as a discrete passive device, semiconductor die, or stacked semiconductor die, is mounted over the semiconductor die and interposer frame. The electronic component has an I/O count less than an I/O count of the semiconductor die.

Multiple die stacking for two or more die

A microelectronic package can include a substrate having first and second opposed surfaces, and first and second microelectronic elements having front surfaces facing the first surface. The substrate can have a plurality of substrate contacts at the first surface and a plurality of terminals at the second surface. Each microelectronic element can have a plurality of element contacts at the front surface thereof. The element contacts can be joined with corresponding ones of the substrate contacts. The front surface of the second microelectronic element can partially overlie a rear surface of the first microelectronic element and can be attached thereto. The element contacts of the first microelectronic element can be arranged in an area array and are flip-chip bonded with a first set of the substrate contacts. The element contacts of the second microelectronic element can be joined with a second set of the substrate contacts by conductive masses.

Method to form solder deposits and non-melting bump structures on substrates

Described is a method of forming a metal or metal alloy layer onto a substrate comprising the following steps i) provide a substrate including a permanent resin layer on top of at least one contact area and a temporary resin layer on top of the permanent resin layer, ii) contact the entire substrate area including the at least one contact area with a solution suitable to provide a conductive layer on the substrate surface and i) electroplate a metal or metal alloy layer onto the conductive layer.

Semiconductor Device and Method of Forming Interposer Frame Over Semiconductor Die to Provide Vertical Interconnect

A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.

Semiconductor Device and Method of Forming a Metallurgical Interconnection Between a Chip and a Substrate in a Flip Chip Package

A method for forming metallurgical interconnections and polymer adhesion of a flip chip to a substrate includes providing a chip having a set of bumps formed on a bump side thereof and a substrate having a set of interconnect points on a metallization thereon, providing a measured quantity of a polymer adhesive in a middle region of the chip on the bump side, aligning the chip with the substrate so that the set of bumps aligns with the set of interconnect points, pressing the chip and the substrate toward one another so that a portion of the polymer adhesive contacts the substrate and the bumps contact the interconnect points, and heating the bumps to a temperature sufficiently high to form a metallurgical connection between the bumps and the interconnect points.

Post-passivation interconnect structure and method of forming the same

A semiconductor device includes a conductive layer formed on the surface of a post-passivation interconnect (PPI) structure by an immersion tin process. A polymer layer is formed on the conductive layer and patterned with an opening to expose a portion of the conductive layer. A solder bump is then formed in the opening of the polymer layer to electrically connect to the PPI structure.

Test Structure and Method of Testing Electrical Characteristics of Through Vias

A method and apparatus for testing the electrical characteristics, such as electrical continuity, is provided. A substrate, such as a wafer or an interposer, having a plurality of through vias (TVs) is provided. Along one side of the substrate, a conductive layer electrically couples two or more of the TVs. Thereafter, the electrical characteristics of the TVs may be test by, for example, a probe card in electrical contact with the TVs on the other side of the substrate. During testing, current passes through a first TV from a first side of the substrate, to the conductive layer on a second side of the substrate, to a second TV, and back to the first side of the substrate through the second TV.

Adjusting Sizes of Connectors of Package Components

A device includes a plurality of connectors on a top surface of a package component. The plurality of connectors includes a first connector having a first lateral dimension, and a second connector having a second lateral dimension. The second lateral dimension is greater than the first lateral dimension. The first and the second lateral dimensions are measured in directions parallel to a major surface of the package component.

Packaging Process Tools and Systems, and Packaging Methods for Semiconductor Devices

Packaging process tools and systems, and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging process tool for semiconductor devices includes a mechanical structure for supporting package substrates or integrated circuit die during a packaging process for the integrated circuit die. The mechanical structure includes a low thermal conductivity material disposed thereon.

Method of processing solder bump by vacuum annealing

A method includes vacuum annealing on a substrate having at least one solder bump to reduce voids at an interface of the at least one solder bump. A die is mounted over the substrate.

Electrical Contact Alignment Posts

An electronic apparatus and method of fabrication of the apparatus, the apparatus including a first electronic device having an interconnection surface with a first plurality of interconnection pads extending from the surface by a first distance and a second plurality of alignment posts extending from the surface by a second distance greater than the first distance, and a second electrical device having an interconnection surface with a first plurality of electrical interconnection pads, each pad arranged to contact a corresponding first electronic device interconnection surface pad upon assembly of the first electronic device interconnection surface upon the second electronic device interconnection surface, the second electronic device interconnection surface including a third plurality of alignment posts, each located to be adjacent to at least one of the first electronic device alignment posts upon assembly.

Semiconductor device having a through-substrate via

Semiconductor devices are described that include a via that extends only partially through the substrate. Through-substrate vias (TSV) furnish electrical interconnectivity to electronic components formed in the substrates. In implementations, the semiconductor devices are fabricated by first bonding a semiconductor wafer to a carrier wafer with an adhesive material. The semiconductor wafer includes an etch stop disposed within the wafer (e.g., between a first surface a second surface of the wafer). One or more vias are formed through the wafer. The vias extend from the second surface to the etch stop.

Bump structure and electronic packaging solder joint structure and fabricating method thereof

A bump structure includes a substrate, a pad, an electrode and a protruding electrode. The pad is disposed on the substrate. The electrode is formed by a first metal material and disposed on the pad. The protruding electrode is formed by a second metal material and disposed on the electrode, wherein a cross-sectional area of the protruding electrode is less than a cross-sectional area of the electrode.

Semiconductor Package with a Bridge Interposer

There are disclosed herein various implementations of semiconductor packages including a bridge interposer. One exemplary implementation includes a first active die having a first portion situated over the bridge interposer, and a second portion not situated over the bridge interposer. The semiconductor package also includes a second active die having a first portion situated over the bridge interposer, and a second portion not situated over the bridge interposer. The second portion of the first active die and the second portion of the second active die include solder balls mounted on a package substrate, and are configured to communicate electrical signals to the package substrate utilizing the solder balls and without utilizing through-semiconductor vias (TSVs).

Molded interposer package and method for fabricating the same

The invention provides a molded interposer package and a method for fabricating the same. The molded interposer package includes a plurality of metal studs. A molding material encapsulates the metal studs leaving the bottom surfaces of the metal studs exposed. A first chip is disposed on the molding material, connecting to the top surfaces of the metal studs. A plurality of solder balls connects and contacts to the bottom surfaces of the metal studs.

Semiconductor Packaging Structure and Method

A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a first bump that is located over a surface of a semiconductor element, and is formed on a first bump formation face distanced from a back surface of the semiconductor element at a first distance, and a second bump that is located over the surface of the semiconductor element, and is formed on a second bump formation face distanced from the back surface of the semiconductor element at a second distance being longer than the first distance, the second bump having a diameter larger than a diameter of the first bump.

Package-in-Package Using Through-Hole Via Die on Saw Streets

A semiconductor device includes a first die having top, bottom, and peripheral surfaces. A bond pad is formed over the top surface. An organic material is connected to the first die and disposed around the peripheral surface. A via hole is formed in the organic material. A metal trace connects the via hole to the bond pad. A conductive material is deposited in the via hole. A redistribution layer (RDL) has an interconnection pad disposed over the top surface of the first die.

Mechanisms of forming connectors for package on package

The described embodiments of mechanisms of forming connectors for package on package enable smaller connectors with finer pitch, which allow smaller package size and additional connections. The conductive elements on one package are partially embedded in the molding compound of the package to bond with contacts or metal pads on another package. By embedding the conductive elements, the conductive elements may be made smaller and there are is gaps between the conductive elements and the molding compound. A pitch of the connectors can be determined by adding a space margin to a maximum width of the connectors. Various types of contacts on the other package can be bonded to the conductive elements.

Flip-chip packaging techniques and configurations

Embodiments of the present disclosure flip-chip packaging techniques and configurations. An apparatus may include a package substrate having a plurality of pads formed on the package substrate, the plurality of pads being configured to receive a corresponding plurality of interconnect structures formed on a die and a fluxing underfill material disposed on the package substrate, the fluxing underfill material comprising a fluxing agent configured to facilitate formation of solder bonds between individual interconnect structures of the plurality of interconnect structures and individual pads of the plurality of pads and an epoxy material configured to harden during formation of the solder bonds to mechanically strengthen the solder bonds. Other embodiments may also be described and/or claimed.

Contact Test Structure and Method

A system and method for testing electrical connections is provided. In an embodiment one or more floating pads may be manufactured in electrical connection with an underbump metallization structure. A test may then be performed to measure the electrical characteristics of the underbump metallization structure through the floating pad in order to test for defects. Alternatively, a conductive connection may be formed on the underbump metallization and the test may be performed on the conductive connection and the underbump metallization together.

Method of manufacturing a semiconductor integrated circuit device

The TSV technology has been popular as one of stacking technologies of a plurality of semiconductor chips. It has however been revealed by the present inventors that when TSV is formed using a so-called first via process, via middle process, front-via via last process, or the like, there is a possibility of defects such as gate breakdown occurring due to electrostatic breakdown in the subsequent process. In order to overcome the above problem, the present invention provides a method of manufacturing a semiconductor integrated circuit device, in which a through via electrode is formed by forming a hole in a semiconductor substrate, forming an insulating member in the hole, and burying a conductive member in the resulting hole while covering a portion of the hole except for the bottom portion with the insulating member.

Semiconductor package

Provided is a semiconductor package including a circuit substrate including a substrate pad, a semiconductor chip spaced apart from and facing the circuit substrate, the semiconductor chip including a chip pad, and a connection pattern electrically connecting the circuit substrate with the semiconductor chip. The semiconductor chip may include a plurality of first circuit patterns extending substantially perpendicular toward a top surface of the semiconductor chip and at least one first via electrically connecting the chip pad to the first circuit patterns. The chip pad may include a first region in contact with the connection pattern and a second region outside the first region, and the first via may be connected to the second region of the chip pad.

Substrate and semiconductor device

A substrate includes a base member having a predetermined thickness, and an electrode array provided in one surface in a thickness direction of the base member and having a plurality of electrodes arranged two-dimensionally in a plan view, and the electrode array includes a central portion and an incremental region provided around the central portion in the planar view and is formed so that a height of the electrodes in the incremental region gradually increase as approaching toward the central portion.

Method and apparatus for reducing package warpage

Embodiments of mechanisms for flattening a packaged structure are provided. The mechanisms involve a flattening apparatus and the utilization of protection layer(s) between the packaged structure and the surface(s) of the flattening apparatus. The protection layer(s) is made of a soft and non-sticking material to allow protecting exposed fragile elements of the packaged structure and easy separation after processing. The embodiments of flattening process involve flattening the warped packaged structure by pressure under elevated processing temperature. Processing under elevated temperature allows the package structure to be flattened within a reasonable processing time.

Self-aligned wafer bonding

A wafer article includes a substrate, two or more hydrophilic areas disposed on the substrate, hydrophobic areas surrounding the hydrophilic areas, and a eutectic bonding material disposed on the substrate. A wafer apparatus including two wafers having complimentary hydrophilic regions and eutectic bonding material is disclosed and a method of forming a bonded wafer articles is disclosed.

Cleaning Methods and Compositions

Methods and chemical solvents used for cleaning residues on metal contacts during a semiconductor device packaging process are disclosed. A chemical solvent for cleaning a residue formed on a metal contact may comprise a reactive inorganic component and a reactive organic component. The method may comprise spraying a semiconductor device with a chemical solvent at a first pressure, and spraying the semiconductor device with the chemical solvent at a second pressure less than the first pressure.

Method and structure of sensors and mems devices using vertical mounting with interconnections

A method and structure for fabricating sensor(s) or electronic device(s) using vertical mounting with interconnections. The method includes providing a resulting device including at least one sensor or electronic device, formed on a die member, having contact region(s) with one or more conductive materials formed thereon. The resulting device can then be singulated within a vicinity of the contact region(s) to form one or more singulated dies, each having a singulated surface region. The singulated die(s) can be coupled to a substrate member, having a first surface region, such that the singulated surface region(s) of the singulated die(s) are coupled to a portion of the first surface region. Interconnections can be formed between the die(s) and the substrate member with conductive adhesives, solder processes, or other conductive bonding processes.

Semiconductor device

To provide a semiconductor device characterized in that lands for mounting thereon solder balls placed in an inner area of a chip mounting area have an NSMD structure. This means that lands for mounting thereon solder balls placed in an area of the back surface of a through-hole wiring board overlapping with a chip mounting area in a plan view have an NSMD structure. According to the invention, a semiconductor device to be mounted on a mounting substrate with balls has improved reliability.

Semiconductor Device and Method of Forming Guard Ring Around Conductive TSV Through Semiconductor Wafer

A semiconductor device has a plurality of conductive vias formed into a semiconductor wafer. An insulating lining is formed around the conductive vias and a conductive layer is formed over the insulating lining. A portion of the semiconductor wafer is removed so the conductive vias extend above a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and conductive vias. A first portion of the first insulating layer is removed and a second portion of the first insulating layer remains as guard rings around the conductive vias. A conductive layer is formed over the conductive vias. A second insulating layer is formed over the surface of the semiconductor wafer, guard rings, and conductive vias. A portion of the second insulating layer is removed to expose the conductive vias and a portion of the guard rings.

Cross flow manifold for electroplating apparatus

The embodiments herein relate to methods and apparatus for electroplating one or more materials onto a substrate. In many cases the material is a metal and the substrate is a semiconductor wafer, though the embodiments are no so limited. Typically, the embodiments herein utilize a channeled plate positioned near the substrate, creating a cross flow manifold defined on the bottom by the channeled plate, on the top by the substrate, and on the sides by a cross flow confinement ring. During plating, fluid enters the cross flow manifold both upward through the channels in the channeled plate, and laterally through a cross flow side inlet positioned on one side of the cross flow confinement ring. The flow paths combine in the cross flow manifold and exit at the cross flow exit, which is positioned opposite the cross flow inlet. These combined flow paths result in improved plating uniformity.

Semiconductor integrated circuit device

In semiconductor integrated circuit devices for vehicle use, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding using a gold wire for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 degrees C.). A semiconductor integrated circuit device can include a semiconductor chip as a part of the device, an electrolytic gold plated surface film (gold-based metal plated film) provided over an aluminum-based bonding pad on a semiconductor chip via a barrier metal film, and a gold bonding wire (gold-based bonding wire) for interconnection between the plated surface film and an external lead provided over a wiring board (wiring substrate).

Low-temperature flip chip die attach

A mechanism for electrically coupling a semiconductor device die to a semiconductor device package substrate that avoids introduction of excessive temperature induced stresses to the semiconductor device die interconnect is provided. In one embodiment, the semiconductor device die is mechanically attached to the package substrate (or another semiconductor device die) at room temperature through the use of a plug-in socket or wedge connection having corresponding mating features formed on the die and substrate. The mechanical interconnect features can be formed on the die and substrate interconnects using an electroplating process. The surfaces of the semiconductor device die and package substrate can then be coupled using an underfill material. A low-temperature solid state bonding process can then be used to diffuse the materials forming the plug and socket features in order to form the electrical connection.

Discrete semiconductor device package and manufacturing method

Disclosed is a discrete semiconductor device package ( 100 ) comprising a semiconductor die ( 110 ) having a first surface and a second surface opposite said first surface carrying a contact ( 112 ); a conductive body ( 120 ) on said contact; an encapsulation material ( 130 ) laterally encapsulating said conductive body; and a capping member ( 140, 610 ) such as a solder cap, a further semiconductor die or a combination thereof in conductive contact with the solder portion, said solder cap extending over the encapsulation material. A further solder cap ( 150 ) may be provided over the first surface. A method of manufacturing such a discrete semiconductor device package is also disclosed.

Semiconductor chip with expansive underbump metallization structures

Methods and apparatus to protect fragile dielectric layers in a semiconductor chip are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first polymer layer over a conductor pad of a semiconductor chip where the conductor pad has a first lateral dimension. An underbump metallization structure is formed on the first polymer layer and in ohmic contact with the conductor pad. The underbump metallization structure has a second lateral dimension greater than the first lateral dimension. A second polymer layer is formed on the first polymer layer with a first opening exposing at least a portion of the underbump metallization structure.

Simultaneous wafer bonding and interconnect joining

Disclosed are a microelectronic assembly of two elements and a method of forming same. A microelectronic element includes a major surface, and a dielectric layer and at least one bond pad exposed at the major surface. The microelectronic element may contain a plurality of active circuit elements. A first metal layer is deposited overlying the at least one bond pad and the dielectric layer. A second element having a second metal layer deposited thereon is provided, and the first metal layer is joined with the second metal layer. The assembly may be severed along dicing lanes into individual units each including a chip.

Method of manufacturing semiconductor device

To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W 1 and a narrow part (a second portion) with a second width W 2 . When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.

Wafer-level device packaging

The present invention relates to a semiconductor device packaged at the wafer level such that an entire packaged device is formed prior to separation of individual devices. The semiconductor device package includes a semiconductor chip having one or more bonding pads associated with the chip and a protective layer bonded over the semiconductor chip. An insulation layer is positioned on at least side edges and a lower surface of the semiconductor chip. Interconnection/bump metallization is positioned adjacent one or more side edges of the semiconductor chip and is electrically connected to at least one bonding pad. A compact image sensor package can be formed that is vertically integrated with a digital signal processor and memory chip along with lenses and a protective cover.

Semiconductor manufacturing method and semiconductor structure thereof

A semiconductor manufacturing method includes providing a carrier; forming a first photoresist layer; forming plural core portions; removing the first photoresist layer; forming a second photoresist layer; forming a plurality of connection portions, each of the plurality of connection portions includes a first connection layer and a second connection layer and connects to each of the core portions to form a hybrid bump, wherein each of the first connection layers comprises a base portion, a projecting portion and an accommodating space, each base portion comprises an upper surface, each projecting portion is protruded to the upper surface and located on top of each core portion, each accommodating space is located outside each projecting portion, the second connection layers cover the projecting portions and the upper surfaces, and the accommodating spaces are filled by the second connection layers; removing the second photoresist layer to reveal the hybrid bumps.

Packaging Structures and Methods with a Metal Pillar

A package component is free from active devices therein. The package component includes a substrate, a through-via in the substrate, a top dielectric layer over the substrate, and a metal pillar having a top surface over a top surface of the top dielectric layer. The metal pillar is electrically coupled to the through-via. A diffusion barrier is over the top surface of the metal pillar. A solder cap is disposed over the diffusion barrier.

Multi-Chip Module with Multiple Interposers

A Multi-Chip Module is presented herein that comprises a package substrate, at least two integrated circuit devices, each of which is electrically coupled to the package substrate, and an interposer. Formed in the interposer are electrical connections which are predominantly horizontal interconnects. The first interposer is arranged to electrically couple the two integrated circuit devices to each other. Methods for manufacturing a Multi-Chip Module are also presented herein.

Semiconductor device including through via structures and redistribution structures

Semiconductor device including through via structure and redistribution structures is provided. The semiconductor device may include internal circuits on a first side of a substrate, a through via structure vertically penetrating the substrate to be electrically connected to one of the internal circuits, a redistribution structure on a second side of the substrate and electrically connected to the through via structure, and an insulating layer between the second side of the substrate and the redistribution structure. The redistribution structure may include a redistribution barrier layer and a redistribution metal layer, and the redistribution barrier layer may extend on a bottom surface of the redistribution metal layer and may partially surround a side of the redistribution metal layer.

Methods and Apparatus of Packaging Semiconductor Devices

Methods and apparatuses for wafer level packaging (WLP) semiconductor devices are disclosed. A redistribution layer (RDL) is formed on a first passivation layer in contact with a conductive pad over a surface of a die. The RDL layer is on top of a first region of the first passivation layer. A second passivation layer is formed on the RDL layer with an opening to expose the RDL layer, and over the first passivation layer. An under bump metallization (UBM) layer is formed over the second passivation layer in contact with the exposed RDL layer. A second region of the first passivation layer disjoint from the first region is determined by projecting an outer periphery of a solder ball or other connector onto the surface.