DIE LEVEL METAL DENSITY GRADIENT FOR IMPROVED FLIP CHIP PACKAGE RELIABILITY

Simple description to and clearly shown in drawing the elements necessarily at a constant rate is that it is not need to be drawn and will recognized. For example, some elements with the spectral output of the sizes elcellent distinctions and understanding the purpose and promotes improved and other elements is volatile compared to. Furthermore, used to locate which are regarded as where the, reference the signs corresponding or similar elements to indicate. repeated in drawing.

(Backend) backend ULK copper/package flip chip die of different stress ULK copper/weak zones the die plate to rigidly layers method using tiling level having improved reliability device and method for manufacturing semiconductor device is is described. Die different stress zones different metal density by providing a, die relative strength and intensity higher metal density (such as and edge or corner) areas can be increased. Structural integrity a conductive bond pads extends over a part integrated circuit immediately below the then the laterally expanded a distance a force or stressed by increasing the metal density region that when stronger. Layer defined zones metal to increase density, defined zones the metal density as a response of the request threshold the layer are irradiated and an to determine whether to meet, otherwise the metallic features (such as tiles or metal filler structure) of the desired density threshold is met until a repeating is mounted from which tiles very small to a pattern process to form a are inserted in its layout designed. As so apparent, metal density a tiles, tiling, dummy charging, metal filler, dummy features, dummy charging inserted metallic features or additional fillers, such as any type of features can be increased by inserted. This the whole process can be applied to layer, each layer can be applied separately from the vehicle. Furthermore, each threshold density different requirements on stress zone and/or in a stress region can be established for the, die horizontal and/or vertical that is defined as different stress zones and regions results in different metal density is, each stress zone of metal traces layers comprising ULK has a density from hardware which dispenses and its own, each stress region in the stress each ULK hardware which dispenses and its metal traces of layers has a density. Tiling (for example, center edges to and final metal the substrate at) is displayed to a screen of the gradient (gradient) in the whole on a die in density of tiles, spacing and position can be used to provide, thus die design to interference provide at least the package toughness can meet the requirements (low modulus) a low coefficient, low hardness, low dielectric constant material improved die using enables the design of circuit interconnect in a.

In the embodiment of the present invention in several exemplary examples, the footwear accompanying drawing are described specifically in reference to will. Various details are hereinafter enumerated in while the, the present invention is this specific detailed computations can be without, the designer's device are especially crystalline run-numerous to attain the particular application purpose, for example in one implementation other implementations changing process pharmaceutical-related or the design method according to a specification described the present invention can be done to an will method recognizes that. Thus selected is complicated and time-consumption despite, such specification a has one skilled in the art having benefits of the people will routine. For example, selected aspects or defining the present invention to avoid ambiguous all the device characteristic or model which does not contain semiconductor device a simlified cross-sectional drawing is shown in reference to. Furthermore, through rotating said (such as ring layers metal tile) any materials are formed for fabricating semiconductor structures would be overfulfilled and removed is to be noted. These materials forming or removed from a procedure described hereinafter are in where the, gelation of fixing solution for film formation and sizes such layers growth, deposition, masking, etching, or otherwise removing techniques are form an can be used to one skilled in the art. The are is publicly known, the present invention are performed teaches to one skilled in the art for method or using the non-volatile memory elements is considered not it is necessary.

Also 1 back to back mask, part are located among flip-chip metalization bumps (for example, 30, 31, 32, 33, 34, 35) is one or more of the defined stress a die located at each of the zone (10) is shown is shaving of. In an illustrated in one example, all possible at only a subset die flip-chip bump (10) are shown the resulting corner at right lower of, any minimum vertical spacing (for example, 38) and horizontal spacing (for example, 40) present in between the bumps. In any layer, die (10) has corner stress zones (for example, 12, 14, 16, 18), edge stress zones (for example, 20, 22, 24, 26), and/or internal stresses zones (for example, 28) can be defined to includes. 2 stress zones of least amount of die area (for example, edge and internal) by separated into, internal stresses region a predetermined minimal number 1 a metal density to meet critical density which can be set so that the, edge stress a metal density region number 2 and on whether a predetermined threshold a minimum higher density to be set up to meet the. Understructure images may be recognized, each of the sections of metal density levels are subjected to an upper metal layer in metal number 1 disclosure and that it does not go below the individual on each one of a of a device can be established. However, in selected in the embodiment, upper 4 two metal interconnect layer for metal density levels are subjected to an stress region and established by the region while, lower metal interconnect layer for metal density level are independently is established.

Minimal and on whether a predetermined threshold densities each layer within the region of stress each stress zone (for example, an interior area (28)) may be set to, a pad metal density interconnect stack located below the annular dielectric and metallized a predetermined layout peripheral and each pad the stress forces or below in the area can be further increased. In method is, one or more stress regions are vertically is defined. The substrate (102) on of flip chip having a bond pad integrated circuit (11) of a portion of is cross-sectional drawing door 2 can be described by referring to. Substrate (102) any material, and, is a semiconductor, such as silicon, typically. Substrate (102) of one or more semiconductor devices (not shown) may be formed as. Substrate (102) on the layers and layer plurality of interconnected between dielectrics (ILDs) (81) is connected to the semiconductor layer.. For example, a final interconnect or end metal (LM) layer (91) the final ILD (LILD) or via layer (via layer; 92). is positioned over. Final ILD (92) stores end (LM-1) front of interconnection or metal line layer (93). is positioned over. Final front of interconnect layer (93) the final front of ILD (LILD-1) or via layer (94). is positioned over. ILD (94) final front of second smallest stores end (LM-2) interconnect layer (95). is positioned over. Final second smallest interconnect layer (95) the final second smallest ILD (LILD-2) or via layer (96). is positioned over. Final second smallest ILD (96) in stores end third (LM-3) interconnect layer (97). is positioned over.

Furthermore, also an integrated circuit that is shown in 2 (11) embodiment the rigid or rigid or relate the structure of device (82) (for example, copper, tantalum, tungsten, chromium and the like) and/or conductive solder ball (80) (for example, tin (Sn) and lead (Pb) solder, or any other electrically conductive materials or alloy) including a conductive bump contact structure (21) includes. Conductive bump contact structure (21) for example an, final metal line layer (91) in metallization layer (are) (84), metal cap (86) or bond pads (92) on and by connecting the option below is situated on an upper surface of attached complete. Understructure can see changes in the, variety of metal or other conductive material a conductive bump contact structure (21) and lower contact layers (84, 86, 92) can be used to form the. Furthermore, insulating layers (90) and polyamide layers (88) the final interconnect layer (91) with a passivation for lower metal feature of conductive bump contact structure (21) can be formed adjacent to. For example, passivation layer (90) the final interconnect layer (91) and bonding pad (92) on selected portion of dielectric Si₃ N₄ or can be formed by deposition of SiON, the electrical and physical contact (for example, metal cap layer (86) by using) bonding pad (92) made in passivation layer used (90) form openings or holes. Additional passivation layer (88) the number 1 passivation layer (90) and metal cap layer (86) poly selected portions of polyimide layer (stress buffer for providing a) or other passivation materials (for example, Si₃ N₄ or SiON) selectively may be formed, thereby lower metallization layer (84) the metal cap layer (86) between the negative electrode and/or restarted by making a contact and physical form sequential transmission of opening.

Also as shown in 2, interconnect layers (81) the number 1 stress region (78) (conductive bump (21) below) and number 1 stress region (78) other number 2 stress region (79) vertically. can be dispensed. The present invention refers to number 1 stress region (78) is of interconnect layer number 1 density or concentration value while allows commands to be set (concentration value), number 2 stress region (79) number 2 a metal density of interconnect layer (for example, lowest) density or concentration is set to a value that is.

For example, the interconnect layers concentration value density or number 1 (91, 93, 95, 97) one or more metals among which layers (1, 2, 3, 4) support structure in a pattern predetermined (83) by forming a stress region number 1 (78) can be set in the.. In in an illustrated in the embodiment, each interconnect layer (91, 93, 95, 97) the metal lines electrically insulate and separation of the dielectric layers (5, 6, 7, 8) includes. Support structure (83) to width side of, stress boundary (77) a conductive bond pad (92) extends over a part of integrated circuit just below the and delimited lateral extensions and thus a distance defining a force (force region) region. Conductive bump region force (21) interconnected by an integrated circuit in any way layers (11) is regions in. The type and volume of the region force and model device technology by applying spherically is defined exclusively according to, having the lateral dimensions of the nanostructure 75×75 microns square bond pads (92) including an exemplary in the embodiment in a, stress boundary (77) has an approximately conductive pad (92) a 140×140 microns forces in relation to the side having a size. region is defined on the force volume. Alternatively, stress boundary (77) the pad side region of proportion of the boundary stress source (for example, pad region/stress boundary area =. 287) can be defined by.

Drive the discharge lamp, number 1 stress region (78) of each interconnect layer (91, 93, 95, 97) receives the-type lines, for example LM layer (91) of metal lines (1), LM-1 layer (93) of metal lines (2), LM-2 layer (95) of metal lines (3), and LM-3 layer (99) of metal lines (4) includes. However, normal or vertical-shaped patterns, Cartesian or " the very it did and it sprouted " organizational structure in a right-angled and are organized in combination of parallel lines, random x-y pattern, or metal line the entire random pattern including other patterns can be used. Interconnect layers (91, 93, 95, 97) for moving cursor in on-metal layers (1, 2, 3, 4) density of a predetermined or required metal density by increasing the, conductive bump (21) die in the vicinity of (11) the total intensity and rigid can be improved. For example, integrated circuit (11) a cover or an edge of a region (83), and becomes strong against density large dielectric metal 30-35% in can be. In other in the embodiment, a predetermined metal density is a 40%. Typically, number 1 stress region (78) of the minimum metal on density for ranges are 30-70% but, the range values are not in an metal lines and materials used in the structural support according to a layout of appropriately be displayed on the touch screen panel should method recognizes.

In a similarly shaped, number 2 density or concentration value one or more of the interconnects layers (91, 93, 95, 97) in dielectric layers (5, 6, 7, 8) separated by metal layers, which (13, 15, 17, 19) of a predetermined pattern (87) by forming a stress region number 2 (79) to be set up in. Any metal lines is used whose desired patterns, number 2 also Figure 2 shows a stress region (79) of each interconnect layer (91, 93, 95, 97) is metal lines, for example LM layer (91) of metal lines (13), LM-1 layer (93) of metal lines (15), LM-2 layer (95) of metal lines (17), and LM-3 layer (97) of metal lines (19) of parallel-type pattern is in to including. Number 2 stress region (79) the city metal line density stress region number 1 (78) is low as regards a than the density of line by forming metal patterns made of, the present invention refers to any stress region is a minimum threshold number 2 (79) to existing allows the siding plank to be obtained from circuit design on randomly appear as well as a stress region number 2 (79) line by forming metal patterns made of increased more density allows. Number 2 stress region (79) of interconnect layers (91, 93, 95, 97) for moving cursor in on-metal layers (13, 15, 17, 19) by increasing the density of, a die outside the region stress number 1 (11) the total intensity and rigid can be improved. For example, integrated circuit (11) stress region the number 2 (79), and becomes strong against density large dielectric metal 20-30% in.. In other in the embodiment, a predetermined metal density is a 40%. Typically, stress region number 2 (79) minimum metal density the range of 20% to 70% but, is not within range value are metal lines to the layout of the traces structural support according to material using appropriately be displayed on the touch screen panel should method recognizes.

Entire die layer metal density defines stress zones and force on the determined result in addition to the use of region, the present specification is die level metal density gradient techniques are each die individually layer is either applied or die layer can be applied to the groups of. For example, stress zones metal density have upper layers (for example, to a level below LM-3 metals top) that may be set on a port in a uniform manner while, lower layers (for example number 1 metal to a level below) the metal density of can be the set area are changed independently. Also this 2 to described in which the, number 1 stress region (78) plurality of interconnect layers (81) number 1 is top or vertical stress zone (83) and lower portion, or vertical stress zone number 2 (85) is shown, which is distributed in perpendicular of wet liquid to flow down. In method is, interconnect stack at least upper stress zone and a lower stress related thereto is measured during each test vertical zone, internal stresses zones most mat and is upper and lower stress zones separately in allows defined.

Also 3 to Figure 5 shows a-conductive phase different metal density are stress regions different in different zones which can be applied is provided lock is shown that method. For example, also also shown in 1 Figure 3 shows a die (10) of corner stress zone (16) being located on the 2 of exemplary metal bumps (30, 31) associated with selected stress regions (42, 44) is in lobated of. Drive the discharge lamp, each bump (30, 31) a relatively high metal density is formed associated forces or stress region (42, 44) has, stress region (42, 44) are outside the area of the (46) a lower formed in herein such that it has a distribution has a metal density. Corner stress zone (16) is minimal and on whether a predetermined threshold metal density (for example, 30-35%) in a selected having in the embodiment, corner stress zone (16) stress regions (42, 44), to obtain a relatively high metal density (for example, 35-40%) has a. Understructure can see changes in the, other stress zones different metal densities stress regions can be designed for low. For example, 1 also also shown in Figure 4 shows a die (10) of internal stresses zone (28) located in a exemplary of bumps 2 (34, 35) associated with selected stress regions (48, 50) is in lobated of. In other words, each bump (34, 35) is formed a relatively high metal density associated forces or stress regions (48, 50) has, stress regions (48, 50) are outside the area of the (52) a lower formed in herein such that it has a distribution has a metal density. Internal stresses zone (28) is minimal and on whether a predetermined threshold metal density (for example, 20%)in the embodiment in a selected having, internal stresses zone (28) stress regions (48, 50), to obtain a relatively high metal density (for example, 30%)has a. 1 also also shown in Figure 5 shows a die (10) edge of stress zone (24) being located on the 2 of exemplary bump pads (32, 33) associated with selected stress regions (54, 56) is another example of an shaving of and can be guided into the in a. As the aforementioned, a metal density desired any, stress regions (54, 56) of metal density (for example, 35%)is stress regions (54, 56) outside the area of the (58) of metal density (for example, 30%)higher than when stress regions (54, 56) can be formed to.

Understructure can see changes in the, bump associated with stress region 2 to layer one or more stress cases an the side plate overlapping zones, for example conductive bumps is die randomly when placed in generating a case where the device can be. there is a. This overlapping any stress region of stress 2 metal density at metal density zones thereof is higher than by means of an AGC mechanism can be processed. Also this is shown in 6, plurality of stress regions (63-75) the internal stresses zone (62) and an edge stress zone (61) attaching the die with the (60) a simlified on. it is shown a shaving. 7×7mm in an exemplary of the die in the embodiment, stress edge (edge seal) sealing edges of die zone is defined to 613 in micro m, internal stresses zone inside the boundary stress zone is defined by die area. Drive the discharge lamp, internal stresses zone (62) (any stress region away) number 1 a metal density of a predetermined minimum threshold (for example, 20%)may be set to, edge stress zone (61) (any stress region away) number 2 a metal density of a predetermined minimum threshold (for example, 30%)can be set to. Internal stresses zone (62) entirely included in stress regions (for example, stress regions (66, 67, 70, 71)) is provided to, such stress a metal density regions number 1 high metal density (for example, 30%)can be set to. Eventually, edge stress zone (61) or entirely included in an the side plate overlapping stress regions (for example, stress regions (63, 64, 65, 68, 69, 72, 73, 74, 75)) the number 2 high metal density (for example, 35%)μm as established by material may have a metal density.

As described, the present invention refers to interconnect rigid layers in order to improve the reliability 3 2 one or two different metal densities can be by using the. For example, die is 20% and 30% minimum metal density internal stresses which are each assigned into stress and an edge zone when the horizontal separation zone, and each conductive metal bump or pad regions are stress associated with lower the minimum metal than the density of 10% when assigned to the increased density, entire die tiling densities is 3-20% (any stress regions other internal stresses zone respect to parts of), 30% (any stress regions other edge stress zone parts of or internal stresses zone adjacent to the top stress any), and 40% (edge stress zone adjacent to the top stress any) will made.

Furthermore, the present invention refers to layer different in different regions and provides metal density, different layers in an integrated circuit different metal density used to provide can be. This stress zones two 3 (corner, edge, internal) I.C. with metal layer below top-circuit listing the available metal density by door 7 shown in table described, wherein the densities applicable stress zone and stress the basis of the new zone associated with each layer is provided in relation to the area of chip. Each row in the table corresponding to the metal layer and, upper metal layer (the is labeled TM) the disclosure in TM-N metal layer (for example, number 1 metal layer) is performed on down the. Number 1 heat (density corner bump relative to the is labeled DCB) to apex locations stress bump any stress which contain values metal density region, wherein of each row density values (for example, D1, D11, D21, D31, D41...DN1) any desired can be transient engine speed period is each set value. Number 2 heat (density corner opening is labeled the DCO for) the bump away region stress to apex for arbitrary regions on stress region metal density values (for example, D2, D12, D22, D32, D42...DN2) includes. Edge stress zones DBB values are density (density for bump edge) and a DBO (for opening edge density) the plural cameras each having a label number 3 and number 4 is listed in heat. In other words, any stress bump region stress edge locations listed in the metal density values (for example, D3, D13, D23, D33, D43...DN3) for regions of away region stress bump and density values (for example, D4, D14, D24, D34, D44...DN4) any desired can be transient engine speed period is each set value. Eventually, internal stresses zones DIB values are density (density for internal bump) and (for opening internal density) DIO the plural cameras each having a label listed in which heat in number 5 and number 6, wherein any internal stresses region bump stress regions listed in the metal density values (for example, D5, D15, D25, D35, D45...DN5) stress regions outside the area of the bump and for metal density values (for example, D6, D16, D26, D36, D46...DN6) any desired can be transient engine speed period is each set value. Typically, bump density values (for example, DCB) opening of the zones a predetermined density values (for example, DCO) will higher than that.

According to various of the present invention in the embodiment, the design and manufacturing method, the minimum metal concentration the entire die metal over the interconnect layer are provided at is provided to it ensures that the. In such method, integrated circuit are different layers and different regions of conductive metal bumps concerning and for any defined stress and relation to position of the area which individually based on is a strong. Figure 8 shows a die also with predetermined areas controlling a density ring metal tile area of the pixel is an exemplary method of is in flow scheme. Method is selected in the embodiment described in Figure 8 are while a, a sequence of steps described unison with the specification of the present invention and can be changed, can be decreases or increases will is recognized. For example, optionally comprise one or more steps can be or eliminating. Therefore, the of the present invention method, although in parallel steps, different order, or mating but can be carried out as independent operations, also 8 identified into the order in which they were shown in performing a sequence of steps can be believed to be a contributing will is recognized.

Drive the discharge lamp, in step 180 the disclosure method, integrated circuit interconnect layer a prior circuit design is is accommodated. Through layers interconnect the circuit components existing for connecting circuit design having metal lines by disclosure, additional metal tile that is completely circuit design existing ring portion has in addition to tile ring inserted as a minimum threshold density requirements to meet the different regions of layer which may be added to, thereby allows for increasing metal density of these regions is. A refers to insertion ring tile additional process repeated as can be done, depending on the same different sizing (sizing) method available any tile added to region is carried out by using an acidulous penetrating hole ring.

In particular, number 1 of stress effects of layer 182 is specified in step region. Number 1 region of stress effects, dummy tile ring bond pad stress regions is added to allowing the strong bond-pads or defined by region stress below, or a dummy tile ring around the exterior of the treating elements same and to make it becomes strong against regions added stress and the bond pad that other regions defined into an area of predefined can substitute by. Conductive pad beneath and surrounding area with in a tiling is selected in the embodiment, the area of the stress effects conductive bump in the vicinity from centering a force is defined with reference region, each layer consists of below conductive bump interconnections at circuit design existing patterns process from metallic layers including have a stress region. Alternatively, tiling process in each layer in addition the predetermined area to define check-box type method using away region stress bond pad may be applied to. Check box size of region portions a is checked method are controlled by changing the measuring box of metal density by calculating an enforce a more evenly than a tile ring. Check box [...] edge-to-edge or may be, or region priori for the described density is met each passing through the metal density when the check box be indexed on has overlap element.

When region is defined of stress effects once, existing region predetermined metal density of circuit design threshold density (for example, 40%)to determine whether to meet is to irradiate at step 184. Existing in a region defined predetermined metal density exceeds a threshold density when (step 184 of positive output), zone sends tile that no additional etchstop layer therefore need to be inserted, processing (step 200) a part which requires high-any other stress effects is determined whether a of areas with.

On the other hand, defined zones existing metal density predetermined density when not satisfying the threshold (step 184 a negation of the filter coefficient output), computation or evaluation, using one or more method of sizing any defined zones tiles added to available space respectively formed on both sides of the metal density can be increased is carried out to determine whether. For example, the tiles are defined zones threshold density predetermined density of an apparatus for pulling becoming more iteratively at higher density. and can be inserted. Also 8 is shown in this iterative process, wherein feature space and a width number 1 is retrieved from which tiles are having (step 186), inserted into available space or 2000 (step 188). For example, number 1 width and characteristics the tiles are rectangular space is inserted perpendicularly to first available space, the printed circuit board is following the contact is inserted in parallel. A circuit design the calculated defined zones of metal density (number 1 feature space having an embedded tile and includes) predetermined threshold density (for example, 40%)to determine whether to meet is to irradiate at step 190. Defined zones predetermined metal density calculated to satisfy threshold density when (step 190 of positive output), the tiles are additional a circuit for an defined zones is output design (step 198), processing (step 200) a part which requires high-any other stress effects is determined whether a of areas with.

Defined zones calculated metal density predetermined density when not satisfying the threshold (step 190 in a pneumatic output), does not fit in having different feature space and a width is determined whether a tiles are any addition (step 192). Additional available, if any, tile, from which tiles are this additional is retrieved (step 194) inserted into available space of defined zones or 2000 (step 188). In view of this, the defined zones (number 1 and additional feature space having including an embedded tiles) calculated predetermined metal density of a circuit design threshold density (for example, 40%)to determine whether to meet the layer are irradiated and an the, predetermined density threshold is met (step 190 of positive output) until is continues loop (step 190). Tiles are additional available whenever no (step 192 a negation of the filter coefficient output), the tiles are defined a certain applications region for outputted from circuit design (step 198). Furthermore, the layer can be a monolayer of a 2d blit operation requires processing amount is calculated by dividing the unit other areas any stress effects when it is determined whether (step 200 a negation of the filter coefficient output), at this time, stress effects of the next zone is defined (step 196) in the irradiating step density process 184 each different transmit the disclosure. Regions are additional processing region when no (step 200 a negation of the filter coefficient output), and terminated to the layer and besides process (step 202), then layer is formed in the process is repeated.

In method is, entire layer a predetermined metal density over a threshold density can be increased. Addition or alternatively, different density thresholds are different in layer stress zones, or different stress regions may be located on the one layer can be used. For example, each area for increasing the density ring metal tile are treated with an order or region of interest stress effects, or reaction products of said area each order to by a gas including iodine process can be processed or parallel. Furthermore, from which tiles are to-relevant area pad-of stress effects after insertion, the remaining area of the stress effects layer one or more stress zone respect to area location is pre-determined according to target densities to be a minimum threshold the tile array is set using leveling process and. can be tiled. On each one of a a process by repetition, inner layer and interlayer effects dependence is density metal of the die for increasing the density tile ring insert. can be accounted for in the process.

Furthermore, stress areas stress regions in the n-type silicon metal of the zones at different domains are optimal width of metals maximum or minimum line width control or it is thus desirable to limit as.. Required density or concentration to achieve while varying the size of the tiles, tile position in addition such line width limited to tissues in the original independently of requirements performed at a step s5. as the requirements for the design data. Furthermore, tile tile added to layouts size of line width to optimize, the control be required can be or limiting. For example, narrow lines the event that the gas/pedal found to is inserted, chip with corner and edge zones the maximum permissible areas are limited to line width may be proposed. Preferably similar, meet metal density target region is selected to that the corners and an edge-zones a sizing method less than areas is held lines.

Method for manufacturing an integrated circuit was and is provided should recognized have now. As problem pre, integrated circuit design number 1 metal interconnect layer on an upper surface of an integrated circuit and having a metal bump of a design locations to which to including integrated circuit design is provided. At least relative to metal interconnect layer number 1, metal bump dispensing a portion is defined region stress including number 1, number 1 stress region required, so that the finally obtained has a concentration metal number 1. Furthermore, of metal interconnect layer number 1 number 1 stress region adjacent to, but, metal bump position and is positioned under the number 2 is that does not stress region is defined. Number 2 stress region a desired less than concentration metal number 1 number 2 has a concentration metal. Integrated circuit, least number 1 metal concentration to achieve stress region number 1 of metal interconnect layer number 1 to increase the metal density, least number 2 stress region number 2 number 2 metal concentration to achieve stress region is formed by increasing the metal density. Furthermore, the method, each of the device in layer number 1 zone (for example, edge portion or corner of an integrated circuit) and a number 2 zone (for example, integrated circuit the corner portion of the flow or includes an inner portion not a rim portion with a) includes for it is specified. In this region, of interconnect layer number 1 number 1 and number 2 stress regions are is located zone number 1, number 3 stress region (metal bump protrusion number 1 metal concentration less than a desired number 3 metal having a concentration) and an adjacent number 4 stress region (metal bump, at a lower portion any which does not have number 1 metal concentration less than a desired number 4 metal having a concentration) placed in the zone is defined to point the number 2. In region stress this additional defined, integrated which circuitry contains at least number 3 metal concentration of a porous member to achieve a of metal interconnect layer number 1 number 3 stress region to increase the metal density, number 4 metal concentration least number 4 stress region of a porous member to achieve a stress number 4 by increasing the metal density region is formed. The number 5 stress region said method (metal bump below with a portion of number 3 metal concentration less than a desired number 5 metal having a concentration) and an adjacent number 6 stress region (metal bump below any portion of also which does not have, number 4 metal concentration less than a desired number 6 metal having a concentration) zone number 3 is located (for example, edge or to a corner portions which does not contain a integrated circuit interior portion of the) defining further includes a. In region stress this additional defined, integrated which circuitry contains at least number 5 metal concentration in the area of a porous member to achieve a stress number 5 of metal interconnect layer number 1 to increase the metal density, number 6 stress contour of a porous member to achieve a concentration metal number 6 number 6 stress region is formed by increasing the metal density. Said method the respective demand metal concentrations (for example, number 3 and number 4 request metal concentrations) having regions the stress metal interconnect layer number 2 (for example, number 3 and number 4 stress regions) by defining procedure is repeated for metal interconnect layer number 2 and, thereby to achieve at least respective demand metal concentration each stress areas of metal interconnect layer number 2 by increasing the metal density prepare silk fibroin fibre integrated circuit. Understructure can see changes in the, the metal interconnect layer number 2 number 1 placed above or below the metal interconnect layer is, number 1 metal interconnect layer and on metal interconnect layer number 2, therebetween or below the a plurality of metal interconnect layer are. In selected in the embodiment, metal density adding a metal layer in that region based on sizing method number 1 number 1 the proposed metal calculate the concentration by for the color temperature. in each of the regions. Number 1 the proposed metal concentration as a response of the request when less than concentration metal number 1, number 2 sizing method (for example, number 1 sizing method in tile ring method to change the desired random crystal orientation can) number 1 metal concentration at least required to achieve additional applies a metal to a interconnect layer number 1 are used to. A plurality of different sizing method adding a metal strips width number 1 number 1 sizing method and, plurality of number 2 of different widths, a metal strips adding a method includes sizing number 2.

In a further aspect, method for manufacturing an integrated circuit is provided. Introductory problem as, integrated circuit on an upper surface having a metal bump of a locations a design for the metal interconnect layer number 1 including integrated circuit design is provided. At least relative to metal interconnect layer number 1, metal bump dispensing is defined region stress including a portion, number 1 wherein stress region required, so that the finally obtained has a concentration metal number 1. Number 1 in the area stress, stress number 1 a metal density adding a metal region based on sizing method number 1 number 1 the proposed metal calculate the concentration is increased by. Number 1 the proposed metal concentration as a response of the request when less than concentration metal number 1, number 2 sizing method (for example, number 1 sizing method in tiling oriented undergo a change in direction the method) metal concentration at least required number 1 number 1 to achieve metal interconnect layer constructing integrated circuit by adding a are used to. In a similar manner, formed to cover stress number 1 number 2 stress region below position metal bump is defined not, wherein, number 1 number 2 stress region a desired less than metal concentration has a concentration metal number 2. Number 2 in the area stress, stress number 2 a metal density adding a metal region based on sizing method number 3 number 2 the proposed metal calculate the concentration is increased by. Number 2 the proposed metal concentration as a response of the request when less than concentration metal number 2, number 4 sizing method (for example, number 3 sizing method in tiling method to change the desired random crystal orientation can) at least required number 1 number 2 metal concentration to achieve metal interconnect layer constructing integrated circuit by adding a are used to. A plurality of different sizing method adding a metal strips width number 1 number 1 sizing method and, plurality of number 2 adding a metal strip of different widths, a method includes sizing number 2. Said method having a concentration metal number 3 required, so that the finally obtained number 2 metal interconnect layer stress regions (for example, number 1 metal interconnect layer to number 1 stress region and aligned a number 3 stress region) of the via opening and defines a, number 3 metal concentration at least required number 3 stress in the area of a porous member to achieve a metal metal interconnect layer number 2 for increasing the density method of sizing using one or more integrated-circuit by building a procedure is repeated for metal interconnect layer number 2.. Understructure can see changes in the, the metal interconnect layer number 2 number 1 placed above or below the metal interconnect layer can be.

In another form the, method for manufacturing an integrated circuit is provided. The first, of the upper surface of integrated circuit number 1 metal interconnect layer and metal bump locations to which to design including integrated circuit design is provided. At least relative to metal interconnect layer number 1, stress regions (for example, number 1 and number 2 stress regions) the metal bump locations respectively is defined in relation to the has a concentration metal required. Each stress in the area, a metal density stress number 1 number 1 adding a metal region based on sizing method, it is proposed that the metal calculate the concentration is increased by. The proposed metal concentration when less than concentration metal as a response of the request, additional sizing method are (for example, number 1 sizing method in tiling method to change the desired random crystal orientation can) required, so that the finally obtained metal concentration is satisfied until metal proposed additional is used to calculate concentrations, which circuitry contains at least integrated at this time, required metal concentration that according to concentration metal proposed added to stress region is formed by adding a metal. Furthermore, each integrated circuit layer said method number 1 number 2 region and includes defining a zone. In this region, of interconnect layer number 1 number 1 and number 2 stress regions are is located zone number 1, number 3 stress region (metal bump below with a portion of number 1 metal concentration less than a desired number 3 having metal concentration) the upper substrate in correspondence to the number 4 stress region (metal bump below the any portion also no number 2 metal concentration less than a desired number 4 having metal concentration) is defined so as to be positioned zone the number 2. In region stress this additional defined, which circuitry contains at least integrated to achieve concentration metal number 3 in the area of metal interconnect layer number 1 number 3 stress to increase the metal density, number 4 stress contour to achieve concentration metal number 4 number 4 stress region is formed by increasing the metal density. Said method required, so that the finally obtained a desired less than concentration metal number 1 number 3 metal having a concentration regions the stress metal interconnect layer number 2 (for example, number 1 metal interconnect layer of number 1 stress stress region aligned region and a number 3) by defining procedure is repeated for metal interconnect layer number 2.. Number 1 sizing method calculated in a proposed number 3 metal concentration number 3 desired region stress number 3 determines whether less than when metal concentration, additional sizing method are (for example, number 1 sizing method in tiling method to change the desired random crystal orientation can) number 3 required, so that the finally obtained metal concentration is satisfied until additional proposed metal concentration is used to compute, which circuitry contains at least integrated at this time, metal concentration that number 3 required added to the proposed metal concentration number 3 according to stress region is formed by adding a metal. In other words, the metal interconnect layer number 2 number 1 metal interconnect layer is placed above or below the.

Human expert at Figures semiconductor manufacturing as part of each die for manufacturing additional, steps of prior art processes (not shown) is executed in a recognizing is will be. As examples, transistor a variety of forming gate electrode is formed under the P layer mutually connected electrically and the, extending injection (extension implant), halo (halo) injection, spacer (spacer) injection, and source/drain implantation steps the transistors to complete the performed at a step. Furthermore, inter-connection of the various levels typically including of the existing method backend process (not shown) to achieve a desired function a desired method. required for connecting the transistors.

The present specification is an exemplary scavenger of a plaque in the embodiment are a variety of semiconductor devices in the spaced-apart structures and method of manufacturing same but relates to, the present invention refers to a wide range of semiconductor process and/or devices bit rate, broadly applicable to an exemplary of the present invention in the embodiment to described aspects are necessarily limited not. Therefore, the present invention is altered and other apparent to one skilled in the art the second device can securely run in the same method of specification teachings of this disclosure as having the same advantages as the organic, the aforementioned specific in the embodiment are the, described here as, for example only, the present invention is provided to defined should not taken as.. Therefore, the aforementioned technique to particular types described intended to define a without the present invention, by issuing an vice versa claim concept and of the present invention defined by such alternatives are compositions and methods using cross-linked, that is intended to to cover and the like, in the form a wide range of most are one skilled in the art of the present invention concept and out of the are multiple variations on without, replacement make and changes it should be understood that the can.

Profits, other benefits, a particular solutions are provided problems in the embodiment regarding the been aforementioned. However the main clock is a or more significantly any profits, advantages, profits that might otherwise introduce solution, advantages, provided solutions are problems, and any element (are) any of or all of the claims important, required, or essential characteristic or a element are not configured as. As used in the present specification, terms "comprising", "includes", or its any other change a non exclusive inclusion in a is intended to cover, including list of elements that process, method, article, device or its elements as well as including, this process, method, article, or device is particularly listed in virtue of the or other element including.