A method of applying a bonding layer

Die Erfindung betrifft ein Verfahren zum Aufbringen einer aus einer Grundschicht und einer Schutzschicht bestehenden Bondschicht auf ein Substrat mit folgenden Verfahrensschritten: Aufbringen eines oxidierbaren Grundmaterials als Grundschicht auf eine Bondseite des Substrats, zumindest teilweises Bedecken der Grundschicht mit einem in dem Grundmaterial zumindest teilweise lösbaren Schutzmaterial als Schutzschicht. Weiterhin betrifft die Erfindung ein korrespondierendes Substrat.

SEMICONDUCTOR COMPONENT.

Three dimensional structure memory

一种三维结构(3DS)存储器(100)使得能够将存储器电路(103)和控制逻辑(101)物理上分离到不同的层(103)上，致使可以分别地优化各个层。几个存储器电路(103)有一个控制逻辑(101)就够了，从而降低了成本。3DS存储器(100)的制造涉及到将存储器电路(103)减薄到厚度小于50微米以及将电路键合到电路叠层，同时仍然呈晶片衬底形式。采用了细粒高密度层间垂直总线互连(105)。3DS存储器(100)制造方法使得能够实现几种性能和物理尺寸效能，并且是用现有的半导体工艺技术实现的。

Solder paste

A solder paste that contains or consists of (i) 10-30% by weight of at least one type of particles that each contain a phosphorus fraction of >0 to ≤500 wt-ppm and are selected from copper particles, copper-rich copper/zinc alloy particles, and copper-rich copper/tin alloy particles, (ii) 60-80% by weight of at least one type of particles selected from tin particles, tin-rich tin/copper alloy particles, tin-rich tin/silver alloy particles, and tin-rich tin/copper/silver alloy particles, and (iii) 3-30% by weight solder flux, in which the mean particle diameter of metallic particles (i) and (ii) is ≤15 μm.

Electronic devices with semiconductor die attached with sintered metallic layers, and methods of formation of such devices

An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a conductive layer underlying the sintered metallic layer, and a conductive substrate underlying the conductive layer.

Lotlegierungen und Anordnungen

Eine Lotlegierung wird bereitgestellt, wobei die Lotlegierung Zink, Aluminium, Magnesium und Gallium aufweist, wobei das Aluminium bezogen auf das Gewicht 8% bis 20% der Legierung ausmacht, das Magnesium bezogen auf das Gewicht 0,5% bis 20% der Legierung ausmacht und das Gallium bezogen auf das Gewicht 0,5 bis 20% der Legierung ausmacht und der Rest der Legierung Zink aufweist.

HALBLEITERVORRICHTUNG

Die Entstehung thermischer Spannungen und eine Verschlechterung der Qualität werden unterdrückt.In einer Halbleitervorrichtung (10) ist in einer seitlichen Querschnittsansicht eine erste Stirnfläche (15a1) einer leitfähigen Struktur (15a) zwischen dem äußersten Rand (16a1) einer Vertiefung (16a) und dem innersten Rand (16b2) einer Vertiefung (16b) angeordnet. Wenn eine thermische Spannung aufgrund von Temperaturänderungen in der Halbleitervorrichtung (10) auf die keramische Leiterplatte (13) einwirkt, unterdrückt die Mehrzahl von Vertiefungen (16a und 16b) eine durch die Temperaturänderungen verursachte Verformung der keramischen Leiterplatte (13). Folglich werden Risse in der keramischen Leiterplatte (13) und eine Abtrennung der Metallplatte (16) und der leitfähigen Struktur (15a) verhindert.

Laminated composite made up of an electronic substrate and an arrangement of layers comprising a reaction solder

Laminated composite (10) comprising at least one electronic substrate (11) and an arrangement of layers (20, 30) made up of at least a first layer (20) of a first metal and/or a first metal alloy and of a second layer (30) of a second metal and/or a second metal alloy adjacent to this first layer (20), wherein the melting temperatures of the first and second layers are different, and wherein, after a thermal treatment of the arrangement of layers (20, 30), a region with at least one intermetallic phase (40) is formed between the first layer and the second layer, wherein the first layer (20) or the second layer (30) is formed by a reaction solder which consists of a mixture of a basic solder with an AgX, CuX or NiX alloy, wherein the component X of the AgX, CuX or NiX alloy is selected from the group consisting of B, Mg, Al, Si, Ca, Se, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Y, Zr, Nb, Mo, Ag, In, Sn, Sb, Ba, Hf, Ta, W, Au, Bi, La, Ce, Pr, Nd, Gd, Dy, Sm, Er, Tb, Eu, Ho, Tm, Yb and Lu ...

Semiconductor apparatus, method for manufacturing the same and electric device

Layered integrated circuit memory

A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 mu m in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

Solder, contact structure and method of fabricating contact structure

Provided is a solder and a contact structure formed by the solder. The solder includes a zinc-based metal layer, a copper film, and a precious metal film. The copper film completely covers the surface of the zinc-based metal layer, and the precious metal film completely covers the copper film. The contact structure includes a zinc-based metal layer and an intermetallic layer. The intermetallic layer consists of zinc and a precious metal and completely covers the surface of the zinc-based metal layer.

Connection arrangement of an electric and/or electronic component

The connection arrangement (100, 200, 300, 400) comprises at least one electric and/or electronic component (1). The at least one electric and/or electronic component (10) has at least one connection face (11), which is connected in a bonded manner to a join partner (40) by means of a connection layer (20). The connection layer (20) can for example be an adhesive, soldered, welded, sintered connection or another known connection that connects joining partners while forming a material connection. Furthermore, a reinforcement layer (30) is arranged adjacent to the connection layer (20) in a bonded manner. The reinforcement layer (30) has a higher modulus of elasticity than the connection layer (20). A particularly good protective effect is achieved if the reinforcement layer (30) is formed in a frame-like manner by an outer and an inner boundary (36, 35) and, at least with the outer boundary (36) thereof, encloses the connection face (11) of the at least one electric and/or electronic component ...

Three dimensional structure memory

A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density interlayer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

CHIP PACKAGE AND A METHOD FOR MANUFACTURING A CHIP PACKAGE

A chip package is provided, the chip package including: a carrier including at least one cavity; a chip disposed at least partially within the at least one cavity; at least one intermediate layer disposed over at least one side wall of the chip; wherein the at least one intermediate layer is configured to thermally conduct heat from the chip to the carrier.

For lead-free solder-connected lead frame structure

Semiconductor device

SOLDERING A CONDUCTOR TO AN ALUMINUM METALLIZATION

A method of making a semiconductor including soldering a conductor to an aluminum metallization is disclosed. In one example, the method includes substituting an aluminum oxide layer on the aluminum metallization by a substitute metal oxide layer or a substitute metal alloy oxide layer. Then, substitute metal oxides in the substitute metal oxide layer or the substitute metal alloy oxide layer are at least partly reduced. The conductor is soldered to the aluminum metallization using a solder material.

HALBLEITERCHIP, VERFAHREN ZUR HERSTELLUNG EINES HALBLEITERCHIPS UND VERFAHREN ZUM VERLÖTEN EINES HALBLEITERCHIPS MIT EINEM TRÄGER

Die Erfindung betrifft einen Halbleiterchip (1') mit einem Halbleiterkörper (10), und einer auf den Halbleiterkörper (10) aufgebrachten Chipmetallisierung (11), die eine dem Halbleiterkörper (10) abgewandte Unterseite (12) aufweist. Auf die Unterseite (12) ist ein Schichtstapel (5) aufgebracht, der eine Anzahl N1 1 oder N1 2 erste Teilschichten (3136) aufweist, sowie eine Anzahl N2 2 zweite Teilschichten (4146). Die ersten Teilschichten (3136) und die zweiten Teilschichten (4146) sind abwechselnd aufeinanderfolgend angeordnet, so dass zwischen den ersten Teilschichten (3136) eines jeden ersten Paares, das sich aus den ersten Teilschichten (3136) bilden lässt, wenigstens eine der zweiten Teilschichten (4146) angeordnet ist, und dass zwischen den zweiten Teilschichten (4146) eines jeden zweiten Paares, das sich aus den zweiten Teilschichten (4146) bilden lässt, wenigstens eine der ersten Teilschichten (3136) angeordnet ist. Eine jede der ersten Teilschichten (3136) weist ein Legierungsmetall ...

Sub-micro connection method for wafer and connection layer

METHOD OF TRANSFERRING AND BONDING AN ARRAY OF MICRO DEVICES

Electrostatic transfer head array assemblies and methods of transferring and bonding an array of micro devices to a receiving substrate are described. In an embodiment, a method includes picking up an array of micro devices from a carrier substrate with an electrostatic transfer head assembly supporting an array of electrostatic transfer heads, contacting a receiving substrate with the array of micro devices, transferring energy from the electrostatic transfer head assembly to bond the array of micro devices to the receiving substrate, and releasing the array of micro devices onto the receiving substrate.

METHOD OF FORMING A CHIP ASSEMBLY AND CHIP ASSEMBLY

A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier. 1. A chip assembly , comprising:a carrier with a top side comprising a cavity formed in the top side of the carrier, the cavity configured to receive a chip;a chip, arranged in the cavity, and comprising a chip contact fixed to the bottom of the cavity; andan interconnect material, between the chip contact and the bottom of the cavity;wherein the top side of the carrier outside the cavity is not flush with the chip; andwherein the chip is diffusion-soldered to the bottom of the cavity.2. The chip assembly of claim 1 ,wherein side walls of the cavity are inclined away from the cavity in a direction from a bottom of the cavity to a top of the cavity.3. The chip assembly of claim 1 ,wherein the cavity is formed with a channel at a bottom of the cavity.4. The chip assembly of claim 1 ,the chip has a thickness that is smaller than a depth of the cavity.5. The chip assembly of claim 1 ,wherein the chip protrudes from the cavity.6. The chip assembly of claim 1 ,wherein the cavity has a convex-shaped bottom that is configured to self-center the chip in the associated cavity.7. The chip assembly of claim 1 ,wherein the cavity has side walls that are convex that are configured to self-center the chip in the cavity.8. The chip assembly of claim 1 ,wherein the cavity has side walls that have a non-constant distance between opposite sides of the cavity along a length of a side.9. The chip assembly of claim 1 ,wherein the chip is ...

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE

A method for manufacturing a semiconductor device comprising: a step for readying each of a semiconductor element (1), a substrate (2) having Cu as a principal element at least on a surface, and a ZnAl solder chip (3') having a smaller shape than that of the semiconductor element; a step for disposing the semiconductor element and the substrate so that respective bonding surfaces face each other, and sandwiching the ZnAl eutectic solder chip between the substrate and the semiconductor element; a step for increasing the temperature of the ZnAl solder chip sandwiched between the substrate and the semiconductor element while applying a load (31) to the ZnAl solder chip, causing the ZnAl solder chip to melt, and forming a ZnAl solder layer (3); and a step for reducing the temperature of the ZnAl solder layer while applying a load to the ZnAl solder layer.

Elektronisches Bauelement und ein Verfahren zur Herstellung eines elektronischen Bauelements

Das elektronische Bauelement enthält einen Träger, ein an dem Träger angebrachtes Halbleiter-Substrat und ein zwischen dem Halbleiter-Substrat und dem Träger angeordnetes Schichtsystem. Das Schichtsystem enthält eine auf dem Halbleiter-Substrat angeordnete elektrische Kontaktschicht. Eine Funktionsschicht ist auf der elektrischen Kontaktschicht angeordnet. Eine Klebeschicht ist auf der Funktionsschicht angeordnet. Eine Lötschicht ist zwischen der Klebeschicht und dem Träger angeordnet.

LOTMATERIAL, SCHICHTSTRUKTUR, CHIPGEHÄUSE, VERFAHREN ZUM BILDEN EINER SCHICHTSTRUKTUR, VERFAHREN ZUM BILDEN EINES CHIPGEHÄUSES, CHIPANORDNUNG UND VERFAHREN ZUM BILDEN EINER CHIPANORDNUNG

Ein Lotmaterial wird bereitgestellt. Das Lotmaterial kann Nickel und Zinn beinhalten, wobei das Nickel einen ersten Anteil an Teilchen und einen zweiten Anteil an Teilchen beinhalten kann, wobei eine Summe des ersten Anteils an Teilchen und des zweiten Anteils an Teilchen ein Gesamtanteil des Nickels oder weniger ist, wobei der erste Anteil an Teilchen zwischen 5 At.-% und 60 At.-% des Gesamtanteils des Nickels beträgt, wobei der zweite Anteil an Teilchen zwischen 10 At.-% und 95 At.-% des Gesamtanteils des Nickels beträgt, wobei die Teilchen des ersten Anteils an Teilchen eine erste Größenverteilung aufweisen, wobei die Teilchen des zweiten Anteils an Teilchen eine zweite Größenverteilung aufweisen, wobei 30 % bis 70 % des ersten Anteils an Teilchen eine Teilchengröße aufweisen, die in einem Bereich von etwa 5 µm um eine Teilchengröße herum liegt, die die höchste Anzahl an Teilchen gemäß der ersten Größenverteilung aufweist, und wobei 30 % bis 70 % des zweiten Anteils an Teilchen eine ...

THREE DIMENSIONAL STRUCTURE MEMORY

A Three Dimensional Structure (3DS) Memory (100) allows for physical separation of the memory circuits (103) and the control logic circuit (101) onto different layers (103) such that each layer may be separately optimized. One control logic circuit (101) suffices for several memory circuits (103), reducing cost. Fabrication of 3DS memory (100) involves thinning of the memory circuit (103) to less than 50 microns in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections (105) are used. The 3DS memory (100) manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques. © KIPO & WIPO 2007 ...

Method of transferring and bonding an array of micro devices

本發明描述了靜電轉印頭(transfer head)陣列總成及傳輸與接合微小元件之陣列至接收基板的方法。在一實施例中，方法包括以下步驟：用支撐靜電轉印頭陣列的靜電轉印頭總成自載體基板拾取微小元件之陣列；令接收基板與微小元件之陣列相接觸；自靜電轉印頭總成傳輸能量以接合微小元件之陣列至接收基板；以及將微小元件之陣列釋放至接收基板上。

Method of transferring micro devices

A method of transferring micro devices is provided. A carrier substrate including a buffer layer and a plurality of micro devices is provided. The buffer layer is located between the carrier substrate and the micro devices. The micro devices are separated from one another and positioned on the carrier substrate through the buffer layer. A receiving substrate contacts the micro devices disposed on the carrier substrate. A temperature of at least one of the carrier substrate and the receiving substrate is changed, so that at least a portion of the micro devices are released from the carrier substrate and transferred onto the receiving substrate. A number of the at least a portion of the micro devices is between 1000 and 2000000.

CHIPGEHÄUSE UND VERFAHREN ZUR HERSTELLUNG EINES CHIPGEHÄUSES

Es wird ein Verfahren zur Herstellung eines Chipgehäuses bereitgestellt, wobei das Verfahren folgende Schritte aufweist: Bilden (210) einer Schichtanordnung über einem Träger, Anordnen (220) eines Chips, einschließlich einer oder mehrerer Kontaktstellen, über der Schichtanordnung, wobei der Chip zumindest einen Teil der Schichtanordnung bedeckt, und selektives Entfernen (230) eines oder mehrerer Abschnitte der Schichtanordnung und Verwenden des Chips als Maske, so dass zumindest ein Teil der Schichtanordnung, der vom Chip nicht bedeckt ist, nicht entfernt wird.

Bondmaterial mit exotherm reaktiven Heterostrukturen

Bondmaterial (30), das ein schmelzbares Verbindungsmaterial (36) und eine Vielzahl von Heterostrukturen (40), die in dem gesamten schmelzbaren Verbindungsmaterial (36) verteilt sind, enthält, wobei die Heterostrukturen (40) mindestens ein erstes Material (42) und ein zweites Material (44) aufweisen, die in der Lage sind, bei Initiierung durch eine externe Energie eine selbstständig ablaufende exotherme Reaktion durchzuführen, um Wärme zu erzeugen, die ausreichend ist, um das schmelzbare Verbindungsmaterial (36) zu schmelzen.

Mit Aktivlot versiegelte Mikrosystemtechnik-Bauelemente, Komponenten hierfür und Lottransferverfahren zu ihrer Herstellung

Bauelement-Komponente in Form eine Substrats (13; 13') oder einer Kappe (4; 4') für ein Einzelbauelement oder für eine Gruppe von verbundenen, zur späteren Vereinzelung vorgesehenen Bauelementen, umfassend mindestens einen für eine spätere Versiegelung vorgesehenen, vollständig umlaufenden erhabenen Rahmen als integralen Bestandteil, der zumindest in seinem oberflächlichen Bereich (5) aus einem Material besteht, das ausgewählt ist unter Metallen, Metalllegierungen, Metall- und Halbmetallverbindungen, die Sauerstoff, Stickstoff und/oder Kohlenstoff enthalten, und Halbleitern, und dessen Breite von der Innen- bis zur Außenseite des Rahmens gemessen im Bereich von 80 µm bis 500 µm liegt, dadurch gekennzeichnet, dass der Rahmen vollständig mit einem Aktivlot-Material (7) mit einem Schmelzpunkt von < 450°C bedeckt ist, wobei das Aktivlot ein Lotmetall oder eine Lotlegierung ist, dem/der mindestens ein Metall, ausgewählt unter den Metallen der IV. und V. Nebengruppe und mindestens ein Metall, ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

The purpose of the present invention is to provide a highly reliable semiconductor device, wherein the thickness of a bonding portion can be controlled even if a part of a second substrate (4) to be bonded with a first substrate (1) is bent. A bonding material of the present invention is configured of a porous metal and a solder, said bonding material bonding the first and the second substrates to each other. In the peripheral portion, the porous metal is provided to both the ends in the thickness direction, and adjusts an interval between both the substrates, and in the center portion, the porous metal is provided not in the whole portion in the thickness direction, thereby absorbing, by means of the solder in the center portion, a design error due to bending of the substrate.

On-chip reconfigurable memory

An on-chip reconfigurable memory is disclosed, comprising: a plurality of data lines, a plurality of gate lines, an array of memory cells, each memory cell storing a data value and comprising circuitry for coupling that data value to one of said data lines in response to the selection of one of said gate lines, a gate line selection circuit for enabling a gate line for a memory operation, said gate line selection circuit comprising programmable gates to receive address assignments for one or more of said gate lines, said address assignments for determining which of said gate lines is selected for each programmed address assignment and a controller for determining that at least one of said memory cells is defective and for altering, in at least one instance, said address assignments of said gate lines to eliminate references to that gate line that causes that defective memory cell to couple a data value to one of said data lines.

VERFAHREN ZUR VERBINDUNG EINES SUBSTRATS UND CHIPANORDNUNG

Es wird ein Verfahren zur Verbindung eines Substrats bereitgestellt, wobei das Substrat eine erste Hauptfläche und eine zweite Hauptfläche gegenüber der ersten Hauptfläche umfassen kann. Das Verfahren kann das Bilden mindestens eines Vorsprungs auf der ersten Hauptfläche des Substrats; Bilden eines Fixiermittels über der ersten Hauptfläche des Substrats und über dem mindestens einen Vorsprung und Anordnen des Substrats auf einem Träger umfassen. Der mindestens eine Vorsprung kann eine Oberfläche des Trägers berühren und so ausgelegt sein, dass er die erste Hauptfläche des Substrats in einem Abstand zur Berührungsfläche des Trägers hält, der einer Höhe des Vorsprungs entspricht, um dadurch einen Raum zwischen der ersten Hauptfläche des Substrats und dem Träger zu bilden. Während des Anordnens des Substrats auf dem Träger kann wenigstens ein Teil des über dem mindestens einen Vorsprung ausgebildeten Fixiermittels in den Raum zwischen der ersten Hauptfläche des Substrats und dem Träger verdrängt ...

The semiconductor element of the joint method and joint structure

本发明提供在界面确保优良的导电性及透明性并将半导体元件接合的方法以及基于该接合方法的接合结构。提供在界面确保优良的导电性并且能够进行有利于元件特性的光学特性的设计的半导体元件的接合方法以及基于该接合方法的接合结构。将未被有机分子覆盖的导电性纳米粒子无光学损失地配置于半导体元件的表面，使另一个半导体元件压接于该导电性纳米粒子上。

CONNECTING MATERIAL, SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

LAYERED COMPOSITE OF A SUBSTRATE FILM AND OF A LAYER ASSEMBLY COMPRISING A SINTERABLE LAYER MADE OF AT LEAST ONE METAL POWDER AND A SOLDER LAYER

The invention relates to a layered composite (10), in particular for connecting electronic components as joining partners, comprising at least one substrate film (11) and a layer assembly (12) applied to the substrate film. The layer assembly comprises at least one sinterable layer (13), which is applied to the substrate film (11) and which contains at least one metal powder, and a solder layer (14) applied to the sinterable layer (13). The invention further relates to a method for forming a layered composite, to a circuit assembly containing a layered composite (10) according to the invention, and to the use of a layered composite (10) in a joining method for electronic components.

SEMICONDUCTOR APPARATUS

A semiconductor apparatus capable of sufficiently securing adhesion between a lead frame and sealing resin body. The semiconductor apparatus includes a lead frame, semiconductor device bonded to a mounting surface of the lead frame, and sealing resin body that covers the surface of the semiconductor device and a surrounding region of the semiconductor device on the mounting surface, in which in the surrounding region, a plurality of circular concave portions is formed with a predetermined pitch in a plurality of rows so as to surround the semiconductor device, and when the pitch and depth of concave portions arranged in at least the innermost peripheral row of the rows that surround the semiconductor device are represented as P[μm] and H[μm],respectively, and the flexural modulus of elasticity of the sealing resin body is represented as E[GPa], the following Formulae (1) and (2) are satisfied: E[GPa]≤20[GPa] (1) 5≤86.4−5.45×E[GPa]+0.164×P[μm]≤H[μm] (2) ...

Semiconductor Device and Electronic Device Having the Same

It is an object of the present invention to provide a wireless chip of which mechanical strength can be increased. Moreover, it is an object of the present invention to provide a wireless chip which can prevent an electric wave from being blocked. The invention is a wireless chip in which a layer having a thin film transistor is fixed to an antenna by an anisotropic conductive adhesive or a conductive layer, and the thin film transistor is connected to the antenna. The antenna has a dielectric layer, a first conductive layer, and a second conductive layer. The dielectric layer is sandwiched between the first conductive layer and the second conductive layer. The first conductive layer serves as a radiating electrode and the second conductive layer serves as a ground contact body.

Semiconductor packages

A semiconductor package includes: a first substrate including a first interconnection structure extending from a surface of the first substrate, the first interconnection structure including grains of a first size, a second substrate including: a second interconnection structure comprising grains of a second size, and a third interconnection structure disposed between the first interconnection structure and the second interconnection structure, the third interconnection structure including grains of a third size, a first sidewall inclined at a first angle to a reference plane and a second sidewall inclined at a second angle to the reference plane, wherein the first angle is different from the second angle, the first sidewall is disposed between the first substrate and the second sidewall, and the third size is smaller than both the first size and the second size.

SOLDER AND DIE-BONDING STRUCTURE

A solder includes zinc as a main component and the solder contains 6 to 8 mass percent of indium. A solder includes zinc as a main component, wherein the solder contains only indium. In a die-bonding structure in which a semiconductor chip is connected to a bonded member by a solder, the solder made of zinc as a main component and contains indium.

Chip assembly

A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.

Verfahren zum Bearbeiten eines Halbleiterwafers oder Dies und Partikelabscheidungsvorrichtung

Gemäß verschiedenen Ausführungsbeispielen wird ein Verfahren zum Bearbeiten eines Halbleiterwafers oder Dies bereitgestellt, wobei das Verfahren aufweist: Zuführen von Partikeln einem Plasma, so dass die Partikel durch das Plasma aktiviert werden und Spritzen der aktivierten Partikel auf ein Halbleiterwafer oder Die, so dass eine Partikelschicht auf dem Halbleiterwafer oder Die erzeugt wird.

SEMICONDUTOR DEVICE

Three-D structure memory

SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE HAVING THE SAME

Semiconductor device and method for manufacturing same

In order to, at the same time, reduce heat resistance and improve thermal deformation absorbing characteristics of a semiconductor device having a mounting structure wherein a semiconductor chip (1) is electrically connected to conductive members (3a, 3b) via bonding members (2a, 2b), each of the bonding members (2a, 2b) has a laminated structure that is provided with, in the following order from the side close to the semiconductor chip (1), a nano-spring layer (4) configured from a plurality of springs having a nano-order size, a planar layer (5) that supports the springs, and a bonding layer (6). The thickness of the nano-spring layer (4) is more than that of the bonding layer (6), and the thickness of the bonding layer (6) is more than that of the planar layer (5).

A package structure and the method to manufacture thereof

Joint material, and jointed body

Disclosed is a jointed body wherein multiple base members are jointed to each other through a jointing layer, and at least one of the base members is a base member of a ceramic material, semiconductor or glass. The joint material layer contains a metal and an oxide. The oxide contains V and Te, and is present between the metal and the base members. Disclosed is also a joint material in the form of a paste containing an oxide glass containing V and Te, metal particles, and a solvent; in the form of a foil piece or plate in which particles of an oxide glass containing V and Te are embedded; or in the form of a foil piece or plate containing a layer of an oxide glass containing V and Te, and a layer of a metal.

Electronic devices with semiconductor die coupled to a thermally conductive substrate

An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a thermally conductive flow layer underlying the sintered metallic layer, and a thermally conductive substrate underlying the thermally conductive flow layer.

ANISOTROPIC ELECTROCONDUCTIVE PARTICLES

An anisotropic electroconductive particle including a first insulating layer, a first conductive layer disposed on the first insulating layer, and a second insulating layer disposed on the first conductive layer. 1. An anisotropic electroconductive particle comprising:a first insulating layer;a first conductive layer disposed on the first insulating layer; anda second insulating layer disposed on the first conductive layer.2. The anisotropic electroconductive particle of claim 1 , wherein the anisotropic electroconductive particle has a hexahedron claim 1 , a polyhedron claim 1 , or a sphere shape.3. The anisotropic electroconductive particle of claim 1 , further comprising:a second conductive layer disposed on the second insulating layer; anda third insulating layer disposed on the second conductive layer.4. The anisotropic electroconductive particle of claim 3 , wherein the first to third insulating layers and the first and second conductive layers are alternately disposed claim 3 , and wherein the first and third insulating layers are disposed on opposite sides of the anisotropic electroconductive particle.5. The anisotropic electroconductive particle of claim 1 , wherein the insulating layer and the conductive layer have a width of about 10 μm or less.6. The anisotropic electroconductive particle of claim 1 , wherein the conductive layer comprises at least one metal alloy selected from Sn—Ag-based metal alloys claim 1 , Sn—Cu-based metal alloys claim 1 , Sn—Bi-based metal alloys claim 1 , and/or Sn—Zn-based metal alloys.7. The anisotropic electroconductive particle of claim 1 , wherein the Sn—Ag-based metal alloys claim 1 , Sn—Cu-based metal alloys claim 1 , Sn—Bi-based metal alloys claim 1 , and Sn—Zn-based metal alloys further comprise at least one metal material selected from Ni claim 1 , Cr claim 1 , Fe claim 1 , Co claim 1 , Ge claim 1 , P claim 1 , and/or Ga.8. The anisotropic electroconductive particle of claim 1 , wherein the insulating layer comprises ...

DISPLAY PANEL

A display panel includes a pixel array substrate, a plurality of vertical light emitting devices and a flip-chip light emitting device. The pixel array substrate has a first pixel area and a second pixel area. The vertical light emitting devices are disposed in the first pixel area and the second pixel area and electrically connected to the pixel array substrate. The flip-chip light emitting device is disposed in the second pixel area and electrically connected to the pixel array substrate. A color of an emitted light beam of the flip-chip light emitting device and a color of an emitted light beam of one of the vertical light emitting devices located in the first pixel area are identical.

Bondmaterial mit exotherm reaktiven Heterostrukturen und Verfahren zum Befestigen mittels einer damit hergestellten Bondverbindung

Bondmaterial (30), aufweisend: ein schmelzbares Verbindungsmaterial (36); und eine Vielzahl von Heterostrukturen (40), die in dem gesamten schmelzbaren Verbindungsmaterial (36) verteilt sind, wobei die Heterostrukturen (40) mindestens ein erstes Material (42) und ein zweites Material (44) aufweisen, die in der Lage sind, bei Initiierung durch eine externe Energie eine selbstständig ablaufende exotherme Reaktion durchzuführen, um Wärme zu erzeugen, die ausreichend ist, um das schmelzbare Material zu schmelzen, wobei die Heterostrukturen (40) Kern-Hülle-Nanopartikel aufweisen, die ein Partikel des ersten Materials (42) aufweisen, das mit dem zweiten Material (44) beschichtet ist, und wobei das erste Material (42) und das zweite Material (44) eine Thermitzusammensetzung bilden.

SEMICONDUTOR DEVICE

Zn-based lead-free solder and semiconductor power module

本发明得到实用的熔点范围为300～350℃的Zn系无铅焊料。Zn系无铅焊料，其含有：0.05～0.2wt％的Cr、0.25～1.0wt％的Al、0.5～2.0wt％的Sb、1.0～5.8wt％的Ge、和5～10wt％的Ga。或者，Zn系无铅焊料，其含有：0.05～0.2wt％的Cr、0.25～1.0wt％的Al、0.5～2.0wt％的Sb、1.0～5.8wt％的Ge、和10～20wt％的In。

THE FABRICATION METHOD OF BONDING METAL AND THE FABRICATION METHOD OF SEMICONDUCTOR LIGHT EMITTING DEVICE USING THE SAME

SEMICONDUCTOR DEVICE AND DICING METHOD

According to an embodiment, a semiconductor device includes a silicon substrate, a semiconductor layer, and a lower layer. The semiconductor layer is formed on an upper surface of the silicon substrate. The lower layer is formed on a lower surface of the silicon substrate and has a side surface connecting to a side surface of the silicon substrate. At least a pair of side surfaces of the semiconductor device has a curved shape widening from an upper side toward a lower side. 1. A semiconductor device comprising:a silicon substrate;a device layer formed on an upper surface of the silicon substrate; anda lower layer formed on a lower surface of the silicon substrate and having a side surface connecting to a side surface of the silicon substrate,wherein at least a pair of side surfaces of the semiconductor device has a curved shape widening from an upper side toward a lower side.2. The semiconductor device according to claim 1 , wherein an upper surface of the device layer is smaller in area than a lower surface of the lower layer.3. The semiconductor device according to claim 1 , wherein the silicon substrate has a curved shape in a lower portion of the silicon substrate claim 1 , and the lower surface of the silicon substrate is larger in area than the upper surface of the silicon substrate.4. The semiconductor device according to claim 2 , wherein the silicon substrate has a curved shape in a lower portion of the silicon substrate claim 2 , and the lower surface of the silicon substrate is larger in area than the upper surface of the silicon substrate.5. The semiconductor device according to claim 1 , wherein the lower layer has a side surface having a curved shape widening from an upper side toward a lower side of the lower layer.6. The semiconductor device according to claim 1 , wherein the lower layer has a vertical side surface.7. The semiconductor device according to claim 1 , wherein the lower layer is a metal layer containing at least one metal selected from ...

Element pressing apparatus and heating system using element pressing apparatus

An element pressing apparatus includes: a base casing having first and second bases couplable to or separable from each other to form an arrangement space where a board and a plurality of electronic components having different heights are arranged while the first and second bases are coupled to each other; oil encapsulated in the arrangement space; an oil seal member deformed depending on a pressure of the oil; and a hydraulic pressure change portion that changes the pressure of the oil, wherein the pressure of the oil changes by the hydraulic pressure change portion to press the oil seal member to a plurality of electronic components and press the electrode terminals against the electrodes when the board and a plurality of electronic components are arranged in the arrangement space by positioning and placing each of the electrode terminals on each of the electrodes.

Semiconductor device and dicing method

According to an embodiment, a semiconductor device includes a silicon substrate, a device layer, and a lower layer. The device layer is formed on an upper surface of the silicon substrate. The lower layer is formed on a lower surface of the silicon substrate and has a side surface connecting to a side surface of the silicon substrate. At least a pair of side surfaces of the semiconductor device has a curved shape widening from an upper side toward a lower side.

Active matrix emissive micro LED display

A display panel and a method of forming a display panel are described. The display panel may include a thin film transistor substrate including a pixel area and a non-pixel area. The pixel area includes an array of bank openings and an array of bottom electrodes within the array of bank openings. An array of micro LED devices are bonded to the corresponding array of bottom electrodes within the array of bank openings. An array of top electrode layers are formed electrically connecting the array of micro LED devices to a ground line in the non-pixel area.

VERFAHREN ZUR VERBINDUNG EINES SUBSTRATS

Verfahren zur Verbindung eines Substrats, wobei das Substrat ein Wafer ist und eine erste Hauptfläche und eine zweite Hauptfläche gegenüber der ersten Hauptfläche umfasst, umfassend: Bilden mindestens eines Vorsprungs auf der ersten Hauptfläche des Substrats, aufweisend ein Bilden einer Struktur, die eine Mehrzahl von Wänden aufweist, auf der ersten Hauptfläche des Substrats, wobei die Mehrzahl von Wänden mindestens eine Vertiefung dazwischen definiert und wobei die Wände in Schnittregionen des Substrats gebildet werden; Bilden eines Fixiermittels über der ersten Hauptfläche des Substrats und über dem mindestens einen Vorsprung; Trennen des Substrats in einzelne Chips vor dem Anordnen des Substrats auf einem Träger; und Anordnen des Substrats auf dem Träger, wobei der mindestens eine Vorsprung eine Oberfläche des Trägers berührt und so ausgelegt ist, dass er die erste Hauptfläche des Substrats in einem Abstand zu einer Berührungsfläche des Trägers hält, der einer Höhe des Vorsprungs entspricht ...

METHOD FOR APPLYING A BONDING LAYER

NANOPARTICLE BACKSIDE DIE ADHESION LAYER

In described examples, a microelectronic device includes a microelectronic die with a die attach surface. The microelectronic device further includes a nanoparticle layer coupled to the die attach surface. The nanoparticle layer may be in direct contact with the die attach surface, or may be coupled to the die attach surface through an intermediate layer, such as an adhesion layer or a contact metal layer. The nanoparticle layer includes nanoparticles having adjacent nanoparticles adhered to each other. The microelectronic die is attached to a package substrate by a die attach material. The die attach material extends into the nanoparticle layer and contacts at least a portion of the nanoparticles.

SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING SEMICONDUCTOR MODULE

A semiconductor module includes a metal plate; a solder applied on the metal plate; a component-to-be-bonded mounted on the solder; and a linear guide portion delineated along a circumference of the component-to-be-bonded on a top surface of the metal plate, and including a metal surface having greater surface roughness than a peripheral region.

Semiconductor device

무연 솔더 접속을 위한 리드 프레임 구조체

... 본 개시내용은 전자 패키징 장치, 전자 패키징 장치에 이용되는 리드 프레임 구조체, 및 전자 패키징 장치를 제조하는 방법을 제공한다. 구리로 이루어지는 리드 프레임은 예컨대 니켈로 된 금속성 배리어층을, 예컨대 리드 프레임의 금속의 산화를 방지하기 위해 포함한다. 예컨대 구리로 된 비교적 얇은 젖음성 촉진층이, 칩이 리드 프레임에 접속되는 다이 접속 공정 중에 리드 프레임에 대해, 무연의 아연계 솔더 등의 솔더의 균일한 젖음성을 촉진시키기 위해 금속성 배리어층 상에 제공된다. 구리/아연 금속간층이 솔더의 플로잉 및 고화(solidification) 시에 형성된다. 구리층에 있는 실질적으로 구리 전체가 구리/아연 금속간층의 형성 중에 소비되고, 금속간층은 전자 패키징 장치의 제조 및 후속 이용 시에 내부 균열 결함에 저항하기에 충분히 얇다.

Semiconductor device and manufacturing method of the same

A semiconductor device includes a die pad (6), an SiC chip (1) mounted on the die pad (6), a porous first sintered Ag layer (16) bonding the die pad (6) and the SiC chip (1), and a reinforcing resin portion (17) covering a surface of the first sintered Ag layer (16) and formed in a fillet shape. The semiconductor device further includes a source lead (9) electrically connected to a source electrode of the SiC chip (1), a gate lead electrically connected to a gate electrode, a drain lead electrically connected to a drain electrode, and a sealing body (14) which covers the SiC chip (1), the first sintered Ag layer (16), and a part of the die pad (6), and the reinforcing resin (17) portion covers a part of a side surface (1c) of the SiC chip (1).

ACTIVE MATRIX EMISSIVE MICRO LED DISPLAY

A display panel and a method of forming a display panel are described. The display panel may include a thin film transistor substrate including a pixel area and a non-pixel area. The pixel area includes an array of bank openings and an array of bottom electrodes within the array of bank openings. An array of micro LED devices are bonded to the corresponding array of bottom electrodes within the array of bank openings. An array of top electrode layers are formed electrically connecting the array of micro LED devices to a ground line in the non-pixel area.

Systems and methods for bonding semiconductor substrates to metal substrates using microwave energy

Systems and methods are disclosed for bonding of substrates using microwave energy. In some embodiments, semiconductor substrates can be bonded through a thin interlayer metal to a metal substrate by using microwave energy. High intensity microwave energy is applied to the substrate assembly positioned within a microwave cavity. A process of selective heating can occur in the thin interlayer metal, resulting in melting of the thin interlayer metal to facilitate bonding of the two substrates. Some of the advantages associated with such bonding process are disclosed.

Copper paste for joining, method for manufacturing joined body, and method for manufacturing semiconductor device

Provided is a copper paste for joining including copper particles, second particles including a metal element other than copper, and a dispersion medium, in which the copper particles include submicro copper particles having a volume-average particle diameter of 0.12 μm or more and 0.8 μm or less and micro copper particles having a volume-average particle diameter of 2 μm or more and 50 μm or less, a sum of a content of the submicro copper particles and a content of the micro copper particles is 80% by mass or more of a sum of masses of the copper particles and the second particles, the content of the submicro copper particles is 30% by mass or more and 90% by mass or less of a sum of a mass of the submicro copper particles and a mass of the micro copper particles, and a content of the second particles is 0.01% by mass or more and 10% by mass or less of the sum of the masses of the copper particles and the second particles.

LAMINATED COMPOSITE MADE UP OF AN ELECTRONIC SUBSTRATE AND A LAYER ARRANGEMENT COMPRISING A REACTION SOLDER

Laminated composite (10) comprising at least one electronic substrate (11) and an arrangement of layers (20, 30) made up of at least a first layer (20) of a first metal and/or a first metal alloy and of a second layer (30) of a second metal and/or a second metal alloy adjacent to this first layer (20), wherein the melting temperatures of the first and second layers are different, and wherein, after a thermal treatment of the arrangement of layers (20, 30), a region with at least one intermetallic phase (40) is formed between the first layer and the second layer, wherein the first layer (20) or the second layer (30) is formed by a reaction solder which consists of a mixture of a basic solder with an AgX, CuX or NiX alloy, wherein the component X of the AgX, CuX or NiX alloy is selected from the group consisting of B, Mg, Al, Si, Ca, Se, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Y, Zr, Nb, Mo, Ag, In, Sn, Sb, Ba, Hf, Ta, W, Au, Bi, La, Ce, Pr, Nd, Gd, Dy, Sm, Er, Tb, Eu, Ho, Tm, Yb and Lu ...

Power converter

The present power converter includes a power conversion semiconductor device, an electrode connection conductor which electrically connects multiple electrodes having the same potential, and also has a generally flat upper surface for electrically connecting to an exterior portion, and a sealing material provided so as to cover the power conversion semiconductor device, and also to expose the generally flat upper surface of the electrode connection conductor.

Semiconductor device

A semiconductor device according to the present invention includes a semiconductor chip, an electrode pad made of a metal material containing aluminum and formed on a top surface of the semiconductor chip, an electrode lead disposed at a periphery of the semiconductor chip, a bonding wire having a linearly-extending main body portion and having a pad bond portion and a lead bond portion formed at respective ends of the main body portion and respectively bonded to the electrode pad and the electrode lead, and a resin package sealing the semiconductor chip, the electrode lead, and the bonding wire, the bonding wire is made of copper, and the entire electrode pad and the entire pad bond portion are integrally covered by a water-impermeable film.

Copper paste for joining, method for manufacturing joined body, and method for manufacturing semiconductor device

This copper paste for joining includes: copper particles; second particles including a metal element other than copper; and a dispersion medium. The copper particles include: sub-micro copper particles having a volume average particle diameter of 0.12-0.8 [mu]m; and micro copper particles having a volume average particle diameter of 2-50 [mu]m. The total content of the sub-micro copper particles and the micro copper particles is at least 80 mass% with respect to the total mass of the copper particles and the second particles; the content of the sub-micro copper particles is 30-90 mass% with respect to the total mass of the sub-micro copper particles and the micro copper particles; and the content of the second particles is 0.01-10 mass% with respect to the total mass of the copper particles and the second particles.

LAYERED COMPOSITE OF A SUBSTRATE FILM AND OF A LAYER ASSEMBLY COMPRISING A SINTERABLE LAYER MADE OF AT LEAST ONE METAL POWDER AND A SOLDER LAYER

The invention relates to a layered composite (10), in particular for connecting electronic components as joining partners, comprising at least one substrate film (11) and a layer assembly (12) applied to the substrate film. The layer assembly comprises at least one sinterable layer (13), which is applied to the substrate film (11) and which contains at least one metal powder, and a solder layer (14) applied to the sinterable layer (13). The invention further relates to a method for forming a layered composite, to a circuit assembly containing a layered composite (10) according to the invention, and to the use of a layered composite (10) in a joining method for electronic components.

METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE

According to various embodiments, a method for manufacturing a semiconductor device may include providing a semiconductor workpiece including a device region at a first side of the semiconductor workpiece, wherein a mechanical stability of the semiconductor workpiece is insufficient to resist at least one back end process without damage, and depositing at least one conductive layer over a second side of the semiconductor workpiece opposite the first side of the semiconductor workpiece, wherein the at least one conductive layer increases the mechanical stability of the semiconductor workpiece to be sufficient to resist the at least one back end process without damage.

LAYERED COMPOSITE OF A SUBSTRATE FILM AND OF A LAYER ASSEMBLY COMPRISING A SINTERABLE LAYER MADE OF AT LEAST ONE METAL POWDER AND A SOLDER LAYER

The welding method for manufacturing products of

마이크로 소자들의 어레이의 이송 및 접합 방법

... 마이크로 소자들의 어레이를 수용 기판으로 이송하고 그에 접합하는 정전기 이송 헤드 어레이 어셈블리 및 방법이 개시된다. 일 실시예에서, 방법은 정전기 이송 헤드들의 어레이를 지지하는 정전기 이송 헤드 어셈블리를 사용하여 마이크로 소자들의 어레이를 캐리어 기판으로부터 픽업하는 단계와, 수용 기판을 마이크로 소자들의 어레이와 접촉시키는 단계와, 마이크로 소자들의 어레이를 수용 기판에 접합하기 위하여 정전기 이송 헤드 어셈블리로부터 에너지를 전달하는 단계와, 그리고 마이크로 소자들의 어레이를 수용 기판 상으로 릴리즈하는 단계를 포함한다.

CONDUCTIVE JUNCTION MATERIAL, CAPABLE OF IMPROVING A HEAT RADIATING PROPERTY AND A JUNCTION RELIABILITY, A JUNCTION METHOD, AND A SEMICONDUCTOR DEVICE USING THE SAME

PURPOSE: A conductive junction material, a junction method, and a semiconductor device using the same are provided to secure the high heat resistant property and the high heat radiating property of a junction part by performing a pressureless junction process without an adhesive. CONSTITUTION: A conductive junction material is arranged between junction units(201). The conductive junction material includes a silver oxide particle(202), silver flake(203), and a dispersing agent. The dispersing agent includes an organic compound with 30 or less carbon numbers. The conductive junction material is heated to be sintered in order to form a sintered silver layer(205). The sintered silver layer is bonded with the junction interface of the junction units by a metallic bond. COPYRIGHT KIPO 2011 ...

Semiconductor device

Provided is a semiconductor device that includes: a semiconductor chip; a an electrode pad that comprises a metal material containing aluminium and is formed on the surface of the semiconductor chip; an electrode lead disposed around the periphery of the semiconductor chip; a main unit that extends in a line; a bonding wire having a pad attachment part and a lead attachment part that are formed on both ends of the main unit and attached to the electrode pad and the electrode lead, respectively; and a resin package that seals the semiconductor chip, the electrode lead, and the bonding wire. The bonding wire comprises copper, and the entire electrode pad and entire pad attachment part are covered together by a moisture-impermeable film.

Method for producing soldered product

The present invention relates to a method for producing a soldered product by which soldering can be accomplished without using a jig. The method for producing a soldered product of the present invention comprises: a provision step of providing a solder and a temporary fixing agent for temporarily fixing the solder; a temporary fixing step of temporarily fixing the solder to a soldering target with the temporary fixing agent; a vaporization step of placing the soldering target with the solder temporarily fixed thereto in a vacuum or heating the soldering target with the solder temporarily fixed thereto to a predetermined temperature lower than the melting temperature of the solder, to vaporize the temporary fixing agent in order to form gaps between the solder and the soldering target; a reduction step, performed concurrently with or after the vaporization step, of reducing, with a reducing gas at a predetermined temperature lower than the melting temperature of the solder, the solder and ...

Method of Bonding Semiconductor Elements and Junction Structure

... [Problem] The present invention provides a method for bonding semiconductor elements while assuring excellent electric conductivity and transparency at an interface, and a junction structure according to the bonding method. The present invention also provides a method for bonding semiconductor elements wherein excellent electric conductivity is assured at an interface and optical characteristics favorable for element characteristics can be designed, and a junction structure according to the bonding method. [Solution] Electrically conductive nano particles which are not covered with organic molecules are arrayed on a surface of one semiconductor element without causing optical loss, and another semiconductor element is pressure-bonded thereagainst.

Bonded structure and method of manufacturing the same

A highly reliable bonded structure having excellent thermal fatigue resistance characteristics and thermal stress relaxation characteristics is provided. The bonded structure of the present invention comprises a first member, a second member capable of being bonded to the first member, and a bonding part interposed between a first bond surface at the first member side and a second bond surface at the second member side to bond the first member and the second member. The bonding part has at least a bonding layer, a reinforcing layer, and an intermediate layer. The bonding layer is composed of an intermetallic compound and bonded to the first bond surface.

SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD THEREOF

PROBLEM TO BE SOLVED: To provide a semiconductor device which achieves low-resistance transmission of a compound semiconductor element in relatively simple configuration and achieves a sufficient heat radiation property of the semiconductor element at a low cost. SOLUTION: A semiconductor package includes a compound semiconductor element 10 with a connecting electrode 11 formed on the surface thereof, a resin circuit board 20 with a connecting electrode 28a and a recess 21 formed on the surface thereof, and metal materials 32 and 33 which fix the compound semiconductor element 10 within the recess 21. Inside the recess 21, the compound semiconductor element 10 is fixed at such an eccentric position that the connecting electrodes 11 and 28a become proximate to each other, the connecting electrodes 11 and 28a are wire-connected, and the metal material 32 covers at least a part from a bottom face to a side face of the compound semiconductor element 10. COPYRIGHT: (C)2012,JPO&INPIT ...

Chipbaugruppe und Verfahren zur Herstellung einer Chipbaugruppe

Chipbaugruppe, die Folgendes aufweist:einen Träger, der wenigstens einen Hohlraum aufweist, wobei der wenigstens eine Hohlraum Hohlraumseitenwände und eine Hohlraumbodenwand aufweist;einen Chip, der wenigstens teilweise innerhalb des wenigstens einen Hohlraums angeordnet ist, wobei eine Chiprückseite des Chips der Hohlraumbodenwand zugewandt ist;wenigstens eine Zwischenschicht, die über wenigstens einer Seitenwand des Chips angeordnet ist;wobei die wenigstens eine Zwischenschicht zum Leiten von Wärme von dem Chip zu dem Träger konfiguriert ist;wobei die wenigstens eine Zwischenschicht Folgendes aufweist:eine erste Metallschicht, die über der Chiprückseite und über der wenigstens einen Seitenwand gebildet ist, wobei die erste Metallschicht wenigstens einen Teil einer Chiprückseiten-Metallisierungsschicht bildet; undeine Einzelchip-Befestigungsschicht, die über der Chiprückseite und über der wenigstens einen Seitenwand über der ersten Metallschicht gebildet ist, wobei die Einzelchip-Befestigungsschicht ...

Zn-Basiertes bleifreies Lot und Halbleiterleistungsmodul

Es wird ein Zn-basiertes bleifreies Lot (2) angegeben, bei dem sein Bereich der praktischen Schmelzpunkte zwischen 300 °C und 350 °C liegt. Das Zn-basierte bleifreie Lot (2) weist Folgendes auf: einen Cr-Gehalt von 0,05 bis 0,2 Gew.-%, einen Al-Gehalt von 0,25 bis 1,0 Gew.-%, einen Sb-Gehalt von 0,5 bis 2,0 Gew.-%, einen Ge-Gehalt von 1,0 bis 5,8 Gew.-% und einen Ga-Gehalt von 5 bis 10 Gew.-%; oder das Zn-basierte bleifreie Lot (2) weist Folgendes auf: einen Cr-Gehalt von 0,05 bis 0,2 Gew.-%, einen Al-Gehalt von 0,25 bis 1,0 Gew.-%, einen Sb-Gehalt von 0,5 bis 2,0 Gew.-%, einen Ge-Gehalt von 1,0 bis 5,8 Gew.-%, und einen In-Gehalt von 10 bis 20 Gew.-%.

JOINT MATERIAL, JOINTED BODY

THREE DIMENSIONAL STRUCTURE MEMORY

A Three Dimensional Structure (3DS) Memory (100) allows for physical separation of the memory circuits (103) and the control logic circuit (101) onto different layers (103) such that each layer may be separately optimized. One control logic circuit (101) suffices for several memory circuits (103), reducing cost. Fabrication of 3DS memory (100) involves thinning of the memory circuit (103) to less than 50 microns in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections (105) are used. The 3DS memory (100) manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques. © KIPO & WIPO 2007 ...

Semiconductor device and manufacturing method of semiconductor device

According to one embodiment, the semiconductor device in the embodiment has an assembly substrate, a semiconductor chip, and a jointing layer. The semiconductor chip is joined to the assembly substrate via the jointing layer. An intervening diffusion barrier layer may be interposed between the chip and jointing layer. The jointing layer is an alloy layer mainly made of any metal selected from Sn, Zn and In or an alloy of Sn, Zn and In, and any metal selected from Cu, Ni, Ag, Cr, Zr, Ti and V or an alloy of any metal selected from Cu, Ni, Ag, Cr, Zr, Ti and V and any metal selected from Sn, Zn and In, where the alloy has a higher melting temperature than that of Sn, Zn and In or an alloy of Sn, Zn and/or In.

Joint Material, and Jointed Body

Disclosed is a jointed body wherein multiple base members are jointed to each other through a jointing layer, and at least one of the base members is a base member of a ceramic material, semiconductor or glass. The joint material layer contains a metal and an oxide. The oxide contains V and Te, and is present between the metal and the base members. Disclosed is also a joint material in the form of a paste containing an oxide glass containing V and Te, metal particles, and a solvent; in the form of a foil piece or plate in which particles of an oxide glass containing V and Te are embedded; or in the form of a foil piece or plate containing a layer of an oxide glass containing V and Te, and a layer of a metal.

Light emitting diode display with redundancy scheme

A display panel and method of manufacture are described. In an embodiment, a display substrate includes a pixel area and a non-pixel area. An array of subpixels and corresponding array of bottom electrodes are in the pixel area. An array of micro LED devices are bonded to the array of bottom electrodes. One or more top electrode layers are formed in electrical contact with the array of micro LED devices. In one embodiment a redundant pair of micro LED devices are bonded to the array of bottom electrodes. In one embodiment, the array of micro LED devices are imaged to detect irregularities.

CONNECTION ARRANGEMENT OF AN ELECTRIC AND/OR ELECTRONIC COMPONENT

The connection arrangement (100, 200, 300, 400) comprises at least one electric and/or electronic component (1). The at least one electric and/or electronic component (10) has at least one connection face (11), which is connected in a bonded manner to a join partner (40) by means of a connection layer (20). The connection layer (20) can for example be an adhesive, soldered, welded, sintered connection or another known connection that connects joining partners while forming a material connection. Furthermore, a reinforcement layer (30) is arranged adjacent to the connection layer (20) in a bonded manner. The reinforcement layer (30) has a higher modulus of elasticity than the connection layer (20). A particularly good protective effect is achieved if the reinforcement layer (30) is formed in a frame-like manner by an outer and an inner boundary (36, 35) and, at least with the outer boundary (36) thereof, encloses the connection face (11) of the at least one electric and/or electronic component ...

SOLDERING A CONDUCTOR TO AN ALUMINUM METALLIZATION

A method of making a semiconductor including soldering a conductor to an aluminum metallization is disclosed. In one example, the method includes substituting an aluminum oxide layer on the aluminum metallization by a substitute metal oxide layer or a substitute metal alloy oxide layer. Then, substitute metal oxides in the substitute metal oxide layer or the substitute metal alloy oxide layer are at least partly reduced. The conductor is soldered to the aluminum metallization using a solder material.

Schichtverbund aus einem elektronischen Substrat und einer Schichtanordnung umfassend ein Reaktionslot

Schichtverbund (10) umfassend mindestens ein elektronisches Substrat (11) und eine Schichtanordnung (20, 30) aus zumindest einer ersten Schicht (20) eines ersten Metalls und/oder einer ersten Metalllegierung und aus einer an diese erste Schicht (20) angrenzenden zweiten Schicht (30) eines zweiten Metalls und/oder einer zweiten Metalllegierung, wobei die Schmelztemperaturen der ersten und der zweiten Schicht unterschiedlich sind, und wobei nach einer Temperaturbehandlung der Schichtanordnung (20, 30) zwischen der ersten Schicht und der zweiten Schicht ein Bereich mit mindestens einer intermetallischen Phase (40) ausgebildet ist, wobei die erste (20) oder die zweite Schicht (30) gebildet wird von einem Reaktionslot, welches aus einer Mischung eines Basislots mit einer AgX-, CuX- oder NiX-Legierung besteht, wobei die Komponente X der AgX-, CuX-, oder NiX-Legierung ausgewählt ist aus der Gruppe bestehend aus B, Mg, Al, Si, Ca, Se, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Y, Zr, Nb, Mo, Ag ...

Method for applying a bonding layer

Semiconductor device and manufacturing method thereof

CONSTRUCTIVE ELEMENT SEMICONDUCTOR

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE

This method for manufacturing a semiconductor device is provided with: a step wherein a semiconductor element (1), a substrate (2) having Cu as a main element of at least the main surface, and a ZnAl eutectic solder chip (3') smaller than the semiconductor element are prepared; a step wherein the semiconductor element and the substrate are disposed such that respective bonding surfaces face each other, and the ZnAl eutectic solder chip is sandwiched between the substrate and the semiconductor element; a step wherein the ZnAl eutectic solder chip is melted by increasing the temperature, while applying a load (31) to the ZnAl eutectic solder chip sandwiched between the substrate and the semiconductor element, and a ZnAl solder layer (3) is formed; and a step wherein the temperature is reduced, while applying the load to the ZnAl solder layer.

Semiconductor apparatus, method for manufacturing the same and electric device

A semiconductor apparatus includes: a semiconductor device including a first electrode; a substrate including a second electrode and a recess; and a heat-dissipating adhesive material to set the semiconductor device in the recess so as to arrange the first electrode close to the second electrode, wherein the first electrode is coupled to the second electrode and the heat-dissipating adhesive material covers a bottom surface and at least part of a side surface of the semiconductor device.

Electronic Device and a Method for Fabricating an Electronic Device

The electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and the carrier. The layer system includes an electrical contact layer disposed on the semiconductor substrate. A functional layer is disposed on the electrical contact layer. An adhesion layer is disposed on the functional layer. A solder layer is disposed between the adhesion layer and the carrier.

Submicron connection layer and method for using the same to connect wafers

A submicron connection layer and a method for using the same to connect wafers is disclosed. The connection layer comprises a bottom metal layer formed on a connection surface of a wafer, an intermediary diffusion-buffer metal layer formed on the bottom metal layer, and a top metal layer formed on the intermediary diffusion-buffer metal layer. The melting point of the intermediary diffusion-buffer metal layer is higher than the melting points of the top and bottom metal layers. The top and bottom metal layers may form a eutectic phase. During bonding wafers, two top metal layers are joined in a liquid state; next the intermediary diffusion-buffer metal layers are distributed uniformly in the molten top metal layers; then the top and bottom metal layers diffuse to each other to form a low-resistivity eutectic intermetallic compound until the top metal layers are completely exhausted by the bottom metal layers.

SEMICONDUCTOR DEVICE

A semiconductor device according to the present invention includes a semiconductor chip, an electrode pad made of a metal material containing aluminum and formed on a top surface of the semiconductor chip, an electrode lead disposed at a periphery of the semiconductor chip, a bonding wire having a linearly-extending main body portion and having a pad bond portion and a lead bond portion formed at respective ends of the main body portion and respectively bonded to the electrode pad and the electrode lead, and a resin package sealing the semiconductor chip, the electrode lead, and the bonding wire, the bonding wire is made of copper, and the entire electrode pad and the entire pad bond portion are integrally covered by a water-impermeable film. 1. A semiconductor device comprising:an interlayer insulating film formed on a semiconductor substrate;an uppermost layer wiring made of copper and formed on the interlayer insulating film;a passivation film formed on the uppermost layer wiring and selectively exposing a top surface of the uppermost layer wiring as an electrode pad; anda bonding wire made of copper and bonded directly to the electrode pad.2. The semiconductor device according to claim 1 , wherein the bonding wire is stitch bonded directly to the electrode pad.3. The semiconductor device according to claim 1 , wherein the bonding wire is bonded to the electrode pad by a stud bump.4. The semiconductor device according to claim 1 , wherein a thickness of the electrode pad is no less than 10 μm.5. The semiconductor device according to claim 1 , wherein a thickness of the electrode pad is 10 μm to 15 μm.6. The semiconductor device according to claim 1 , further comprising a lower layer wiring covered with the interlayer insulating film claim 1 , whereinthe uppermost layer wiring includes a protrusion extending inside the interlayer insulating film,the lower layer wiring is electrically connected to the electrode pad via a pathway including the protrusion.7. The ...

Method for Producing Electronic Device With Multi-Layer Contact

A method for producing an electric device with a multi-layer contact is disclosed. In an embodiment, a method includes providing a carrier, the carrier having a metallic layer disposed on its surface, providing a semiconductor substrate, forming a layer stack on the semiconductor substrate and attaching the layer stack of the semiconductor substrate to the metallic layer of the carrier so that an intermetallic phase is formed between the metallic layer and the solder layer. 1. A method for fabricating an electronic device , the method comprising:providing a carrier, the carrier having a metallic layer disposed on its surface, wherein the metallic layer comprises Ni or NiNiP;providing a semiconductor substrate; directly depositing an electrical contact layer on the semiconductor substrate, the electrical contact layer being a single elemental Al layer;', 'directly depositing a functional layer on the electrical contact layer, the functional layer comprising Ti or an alloy containing Ti;', 'directly depositing an adhesion layer on the functional layer, the adhesion layer comprising Ni or NiV;', 'directly depositing a solder layer on the adhesion layer, the solder layer being a single element Sn layer or a noble metal free alloy layer containing Sn; and', 'directly depositing a protective layer on the solder layer, the protection layer being an Ag layer; and, 'forming a layer stack on the semiconductor substrate bybonding the layer stack of the semiconductor substrate to the metallic layer of the carrier so that an intermetallic phase is formed between the metallic layer and the solder layer, the intermetallic phase comprising a binary alloy of Ni/Sn.2. The method according to claim 1 , wherein the electrical contact layer has a thickness in a range from 100 nm to 1 μm.3.The method according to claim 2 , wherein the functional layer has a thickness in a range from 50 nm to 200 nm.4382. The method according to claim claim 2 , wherein the solder layer has a thickness in ...

Electronic Device with Multi-Layer Contact

An electric device with a multi-layer contact is disclosed. In an embodiment, the electronic device includes a carrier, a semiconductor substrate attached to the carrier, and a layer system disposed between the semiconductor substrate and the carrier. The layer system includes an electrical contact layer disposed on the semiconductor substrate. A functional layer is disposed on the electrical contact layer. An adhesion layer is disposed on the functional layer. A solder layer is disposed between the adhesion layer and the carrier.

Pre-Plating of Solder Layer on Solderable Elements for Diffusion Soldering

A pre-soldered circuit carrier includes a carrier having a metal die attach surface, a plated solder region on the metal die attach surface, wherein a maximum thickness of the plated solder region is at most 50 μm, the plated solder region has a lower melting point than the first bond pad, and the plated solder region forms one or more intermetallic phases with the die attach surface at a soldering temperature that is above the melting point of the plated solder region.

Semiconductor Devices and Methods of Forming Thereof

In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a contact layer over a first major surface of a substrate. The substrate includes device regions separated by kerf regions. The contact layer is disposed in the kerf region and the device regions. A structured solder layer is formed over the device regions. The contact layer is exposed at the kerf region after forming the structured solder layer. The contact layer and the substrate in the kerf regions are diced.

LEAD FRAME CONSTRUCT FOR LEAD-FREE SOLDER CONNECTIONS

An electronics packaging arrangement, a lead frame construct for use in an electronics packaging arrangement, and a method for manufacturing an electronics packaging arrangement. A lead frame made of copper, for example, includes a metallic barrier layer of nickel, for example, to prevent oxidation of the metal of the lead frame. A relatively thin wetting promoting layer of copper, for example, is provided on the metallic barrier layer to promote uniform wetting of a solder, such as a lead-free, zinc-based solder, onto the lead frame during a die connect process by which a chip is connected to the lead frame. A copper/zinc intermetallic layer is formed during the flow and solidification of the solder. Substantially all of the copper in the copper layer is consumed during formation of the copper/zinc intermetallic layer, and the intermetallic layer is sufficiently thin to resist internal cracking failure during manufacture and subsequent use of the electronics packaging arrangement. 110-. (canceled)11. A lead frame construct , comprising:a lead frame having a surface;a metallic barrier layer disposed on said surface of said lead frame; anda wetting promoting layer disposed on said metallic barrier layer.12. The construct of claim 11 , wherein the wetting promoting layer is selected from copper and a copper alloy.13. The construct of claim 11 , wherein the wetting promoting layer is selected from zinc claim 11 , bismuth claim 11 , tin claim 11 , indium claim 11 , gold claim 11 , silver claim 11 , palladium claim 11 , platinum and alloys thereof.14. The construct of wherein said wetting promoting layer has a thickness between 1 μm and 10 μm.15. The construct of claim 11 , wherein said metallic barrier layer comprises one of nickel and a nickel alloy claim 11 , and has a thickness between 1 μm and 10 μm.16. The construct of claim 11 , wherein the metallic barrier layer is a discontinuous layer over a plurality of die pad areas of the lead frame.17. An electronics ...

CONNECTION ARRANGEMENT OF AN ELECTRIC AND/OR ELECTRONIC COMPONENT

A connection arrangement includes at least one electric and/or electronic component. The at least one electric and/or electronic component has at least one connection face, which is connected in a bonded manner to a join partner by means of a connection layer. The connection layer can for example be an adhesive, soldered, welded, sintered connection or another known connection that connects joining partners while forming a material connection. Furthermore, a reinforcement layer is arranged adjacent to the connection layer in a bonded manner. The reinforcement layer has a higher modulus of elasticity than the connection layer. A particularly good protective effect is achieved if the reinforcement layer is formed in a frame-like manner by an outer and an inner boundary and, at least with the outer boundary thereof, encloses the connection face of the at least one electric and/or electronic component. 11002003004001010114020. A connection arrangement ( , , , ) of at least one electric and/or electronic component () , wherein the at least one electric and/or electronic component () has a connection face () , which is connected in a bonded manner to the join partner () by a connection layer () , wherein{'b': 30', '20', '30', '20', '30', '36', '35', '36', '11', '10, 'a reinforcement layer (′) is arranged adjacent to the connection layer (), said reinforcement layer (′) having a higher modulus of elasticity than the connection layer (), wherein the reinforcement layer (′) is formed in a frame-like manner by an outer boundary and an inner boundary (, ) and, at least with the outer boundary () thereof, encloses the connection face () of the at least one electric and/or electronic component (), and'}{'b': '30', 'wherein the reinforcement layer (′) comprises at least one intermetallic phase.'}2203030203030. The connection arrangement according to claim 1 , characterized in that the connection layer () comprises at least one metal and the reinforcement layer (′) is formed from ...

Semiconductor device and semiconductor device manufacturing method

A semiconductor device, including a substrate having an insulating plate and a conductive plate formed on the insulating plate, a semiconductor chip formed on the conductive plate, a contact part arranged on the conductive plate with a bonding member therebetween, a rod-shaped external connection terminal having a lower end portion thereof fitted into the contact part, and a lid plate having a front surface and a back surface facing the substrate. An insertion hole pierces the lid plate, forming an entrance and exit respectively on the back and front surfaces of the lid plate. The external connection terminal is inserted in the insertion hole. The semiconductor device has at least one of a guide portion with an inclined surface, fixed to a portion of the external connection terminal located in the insertion hole, or an inclined inner wall of the insertion hole.

Method of forming a chip assembly and chip assembly

A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.

Electronic Device with Multi-Layer Contact and System

An electronic device with a multi-layer contact and a system is disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate having a first electrode terminal located on a first surface and a second surface electrode terminal located on a second surface, the first surface being opposite to the second surface, an electrical contact layer disposed directly on the first electrode terminal, a functional layer directly disposed on the electrical contact layer, an adhesion layer directly disposed on the functional layer, a solder layer directly disposed on the adhesion layer; and a protection layer directly disposed on the solder layer, wherein the semiconductor device is a power semiconductor device configured to provide a vertical current flow. 1. A semiconductor device comprising:a semiconductor substrate having a first electrode terminal located on a first surface and a second surface electrode terminal located on a second surface, the first surface being opposite to the second surface;an electrical contact layer disposed directly on the first electrode terminal, the electrical contact layer consisting essentially of Al;a functional layer directly disposed on the electrical contact layer, the functional layer consisting essentially of Ti or an alloy containing Ti;an adhesion layer directly disposed on the functional layer, the adhesion layer consisting essentially of Ni or NiV;a solder layer directly disposed on the adhesion layer, the solder layer consisting essentially of Sn; anda protection layer directly disposed on the solder layer,wherein the semiconductor device is a power semiconductor device configured to provide a vertical current flow.2. The device according to claim 1 , wherein the electrical contact layer has a thickness in a range from 100 nm to 1 μm claim 1 , wherein the functional layer has a thickness in a range from 50 nm to 200 nm claim 1 , wherein the adhesion layer has a thickness in a range from 200 nm to 2 μm claim 1 , ...

LIGHT EMITTING DIODE DISPLAY WITH REDUNDANCY SCHEME

A display panel and method of manufacture are described. In an embodiment, a display substrate includes a pixel area and a non-pixel area. An array of subpixels and corresponding array of bottom electrodes are in the pixel area. An array of micro LED devices are bonded to the array of bottom electrodes. One or more top electrode layers are formed in electrical contact with the array of micro LED devices. In one embodiment a redundant pair of micro LED devices are bonded to the array of bottom electrodes. In one embodiment, the array of micro LED devices are imaged to detect irregularities. 1. A display panel with redundancy scheme comprising:a display substrate including a pixel area that includes an array of subpixels, each subpixel including a pair of landing areas;an array of redundant LED bonding site pairs, each landing area including a corresponding LED bonding site;wherein the array of subpixels includes a first subpixel array, a second subpixel array, and a third subpixel array, wherein the first, second, and third subpixel arrays are designed to emit different primary color emissions;circuitry to switch and drive the array of subpixels; andone or more LED device irregularities among the array of redundant LED bonding site pairs, wherein each corresponding landing area containing a micro LED device irregularity is electrically disconnected from the circuitry.2. The display panel of claim 2 , wherein each corresponding landing area is cut to electrically disconnect the corresponding landing area from the circuitry.3. The display panel of claim 3 , wherein the circuitry is contained within an array of micro controller chips.4. The display panel of claim 3 , wherein the array of micro controller chips is bonded to the display substrate.5. The display panel of claim 4 , wherein each micro controller chip is bonded to the display substrate within the pixel area.6. The display panel of claim 5 , wherein each micro controller chip is connected to a scan driver ...

CHIP ARRANGEMENTS

A chip arrangement including: a chip including a chip back side; a substrate including a surface with a plating; and a zinc-based solder alloy which attaches the chip back side to the plating on the surface of the substrate, the zinc-based solder alloy including, by weight, 1% to 30% aluminum, 0.5% to 20% germanium, and 0.5% to 20% gallium, wherein a balance of the zinc-based solder alloy is zinc. 1. A chip arrangement comprising:a chip comprising a chip back side;a substrate comprising a surface with a plating; anda zinc-based solder alloy which attaches the chip back side to the plating on the surface of the substrate, the zinc-based solder alloy comprising, by weight, 1% to 30% aluminum, 0.5% to 20% germanium, and 0.5% to 20% gallium, wherein a balance of the zinc-based solder alloy is zinc.2. The chip arrangement of claim 1 , wherein the zinc-based solder alloy comprises by weight 3% to 8% aluminum.3. The chip arrangement of claim 1 , wherein the zinc-based solder alloy comprises by weight 0.5% to 4% germanium.4. The chip arrangement of claim 1 , wherein the zinc-based solder alloy comprises by weight 0.5% to 4% gallium.5. The chip arrangement of claim 1 , wherein the zinc-based solder alloy further comprises at least one from the following group of materials: silver claim 1 , gold claim 1 , nickel claim 1 , platinum claim 1 , palladium claim 1 , vanadium claim 1 , molybdenum claim 1 , tin claim 1 , copper claim 1 , arsenic claim 1 , antimony claim 1 , niobium claim 1 , tantalum claim 1 , and/or any combination thereof claim 1 , by weight 0.001% to 10% of the zinc-based solder alloy.6. The chip arrangement of claim 1 , wherein the plating comprises at least one of nickel or nickel-phosphorous.7. The chip arrangement of claim 6 , wherein the substrate comprises one or more of copper claim 6 , nickel claim 6 , silver claim 6 , or ceramic.8. The chip arrangement of claim 7 , wherein the at least one of nickel or nickel-phosphorous in the plating provides a reduced ...

METHOD AND APPARATUS FOR CREATING A BOND BETWEEN OBJECTS BASED ON FORMATION OF INTER-DIFFUSION LAYERS

The present disclosure provides a method of creating a bond between a first object and a second object. For example, at least one insert may be provided at a location in a space formed between the first object and the second object. In additional, a filler material may be provided proximal to the location. An inter-diffusion layer may be formed, wherein a first portion of the inter-diffusion layer is formed by diffusion between the filler material and the at least one insert, wherein a second portion of the inter-diffusion layer is formed between the filler material and the first object, wherein a third portion of the inter-diffusion layer is formed between the filler material and the second object, wherein the first portion is coadunate with each of the second portion and third portion. 1. An electronic module comprising:a substrate;at least one chip; a first set of inserts placed inside a space between the substrate and the at least one chip,', "wherein diffusion of the second set of inserts occurs into at least one of the following: the substrate's mating surface, the at least one chip's mating surface and the first set of inserts;", 'a second set of inserts placed inside a space formed by the substrate, the at least one chip and the first set of inserts,'}], 'a plurality of inserts comprisinga gap between the first set of the inserts and the substrate; and 'wherein the diffusion results in formation of at least one of the following: a coadunate inter-diffusion layer along at least one insert of the first set of inserts to the at least one chip and a coadunate inter-diffusion layer along at least one insert of the first set of the inserts to the substrate.', 'a gap between the first set of inserts and the at least one chip,'}21. The electronic module of lain , wherein the at least one insert of the first set of inserts is comprised in at least one of the substrate's mating surface and the chip's mating surface.3. The electronic module of claim 1 , wherein the at ...

LIGHT EMITTING DIODE DISPLAY WITH REDUNDANCY SCHEME

A display panel and method of manufacture are described. In an embodiment, a display substrate includes a pixel area and a non-pixel area. An array of subpixels and corresponding array of bottom electrodes are in the pixel area. An array of micro LED devices are bonded to the array of bottom electrodes. One or more top electrode layers are formed in electrical contact with the array of micro LED devices. In one embodiment a redundant pair of micro LED devices are bonded to the array of bottom electrodes. In one embodiment, the array of micro LED devices are imaged to detect irregularities. 1. A display panel redundancy scheme comprising:a display substrate;a first micro light emitting diode (LED) and a second LED arranged within a subpixel;wherein the first micro LED and the second micro LED each comprises a p-n diode, a top conductive contact, and a bottom conductive contact that is bonded to the display substrate;a passivation material over the second micro LED; anda top electrode layer over the first micro LED and the second micro LED, wherein the top electrode layer is in electrical contact with the first micro LED and the passivation material physically separates the top electrode layer from the second micro LED.2. The display panel of claim 1 , wherein each of the first micro LED and the second micro LED has a maximum width of 1 to 100 μm.3. The display panel of claim 2 , wherein the top electrode layer is formed of a material selected from the group consisting of a transparent conductive oxide and a transparent conducting polymer.4. The display panel of claim 2 , further comprising a Vss tie line.5. The display panel of claim 4 , wherein the top electrode layer is in electrical contact with the Vss tie line.6. The display panel of claim 5 , further comprising a passivation layer covering sidewalls of the first micro LED and the second micro LED claim 5 , and the top electrode layer spans over a top surface of the passivation layer.7. The display panel of ...

Light emitting device

Provided is a light emitting device. In one embodiment, a light emitting device including: a support member; a light emitting structure on the support member, the light emitting structure comprising a first conductive type semiconductor layer, a second conductive type semiconductor layer, and an active layer between the first conductive type semiconductor layer and the second conductive type semiconductor layer; a protective member at a peripheral region of an upper surface of the support member; an electrode including an upper portion being on the first conductive type semiconductor layer, a side portion extended from the upper portion and being on a side surface of the light emitting structure, and an extended portion extended from the side portion and being on the protective member; and an insulation layer between the side surface of the light emitting structure and the electrode.

METHOD FOR APPLYING A BONDING LAYER

A method for applying a bonding layer that is comprised of a basic layer and a protective layer on a substrate with the following method steps: application of an oxidizable basic material as a basic layer on a bonding side of the substrate, at least partial covering of the basic layer with a protective material that is at least partially dissolvable in the basic material as a protective layer. In addition, the invention relates to a corresponding substrate. 111-. (canceled)12. Method for bonding a first substrate with a second substrate , said method comprising:applying an oxidizable basic material as a basic layer on a bonding side of the first substrate,at least partially covering the basic layer with a protective layer comprised of a protective material that is at least partially dissolvable in the basic material, said protective layer having a thickness of less than 100 nm,bonding the first and second substrates, wherein the protective material is dissolved completely in the basic material during the bonding.13. The method according to claim 12 , wherein the basic material is oxygen-affine and is comprised of aluminum and/or copper.14. The method according to claim 12 , wherein the step of applying the basic material as the basic layer and/or covering the basic layer with the protective layer is/are carried out by deposition.15. The method according to claim 12 , wherein the protective layer is applied such that the basic layer is sealed at least predominantly relative to the atmosphere.16. The method according to claim 12 , wherein the protective layer is treated before the step of bonding claim 12 , said protective layer treated with one or more of the following processes:(a) chemical oxide removal;(b) physical oxide removal, in particular with plasma; and(c) ion-assisted chemical etching.17. The method according to claim 12 , wherein one or more of the following materials are selected as the basic material and/or the protective material:(a) metals;(b) alkali ...

COPPER PASTE FOR JOINING, METHOD FOR MANUFACTURING JOINED BODY, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Provided is a copper paste for joining including copper particles, second particles including a metal element other than copper, and a dispersion medium, in which the copper particles include submicro copper particles having a volume-average particle diameter of 0.12 μm or more and 0.8 μm or less and micro copper particles having a volume-average particle diameter of 2 μm or more and 50 μm or less, a sum of a content of the submicro copper particles and a content of the micro copper particles is 80% by mass or more of a sum of masses of the copper particles and the second particles, the content of the submicro copper particles is 30% by mass or more and 90% by mass or less of a sum of a mass of the submicro copper particles and a mass of the micro copper particles, and a content of the second particles is 0.01% by mass or more and 10% by mass or less of the sum of the masses of the copper particles and the second particles. 1. A copper paste for joining comprising:copper particles;second particles including a metal element other than copper; anda dispersion medium,wherein the copper particles include submicro copper particles having a volume-average particle diameter of 0.12 μm or more and 0.8 μm or less and micro copper particles having a volume-average particle diameter of 2 μm or more and 50 μm or less,a sum of a content of the submicro copper particles and a content of the micro copper particles is 80% by mass or more of a sum of masses of the copper particles and the second particles,the content of the submicro copper particles is 30% by mass or more and 90% by mass or less of a sum of a mass of the submicro copper particles and a mass of the micro copper particles, anda content of the second particles is 0.01% by mass or more and 10% by mass or less of the sum of the masses of the copper particles and the second particles.2. The copper paste for joining according to claim 1 ,wherein the second particles are metal particles.3. The copper paste for joining ...

Soldering a conductor to an aluminum metallization

A method of making a semiconductor including soldering a conductor to an aluminum metallization is disclosed. In one example, the method includes substituting an aluminum oxide layer on the aluminum metallization by a substitute metal oxide layer or a substitute metal alloy oxide layer. Then, substitute metal oxides in the substitute metal oxide layer or the substitute metal alloy oxide layer are at least partly reduced. The conductor is soldered to the aluminum metallization using a solder material.

LIGHT EMITTING DIODE DISPLAY WITH REDUNDANCY SCHEME

A display panel and method of manufacture are described. In an embodiment, a display substrate includes a pixel area and a non-pixel area. An array of subpixels and corresponding array of bottom electrodes are in the pixel area. An array of micro LED devices are bonded to the array of bottom electrodes. One or more top electrode layers are formed in electrical contact with the array of micro LED devices. In one embodiment a redundant pair of micro LED devices are bonded to the array of bottom electrodes. In one embodiment, the array of micro LED devices are imaged to detect irregularities. 1. (canceled)2. A display panel redundancy scheme comprising:an array of micro controller chips;an array of micro light emitting diode (LED) pairs connected with the array of micro controller chips in an array of pixel areas;wherein each pixel area includes a micro controller chip connected to a corresponding group of micro LED pairs arranged in a plurality of subpixels; andwherein the group of micro LED pairs includes a group of primary micro LEDs arranged in the plurality of subpixels, and a group of redundant micro LEDs arranged in the plurality of subpixels such that each subpixel includes a micro LED pair.3. The display panel of claim 2 , wherein each pixel area includes a first subpixel claim 2 , a second subpixel claim 2 , and a third subpixel.4. The display panel of claim 3 , wherein:each first subpixel includes a first primary micro LED and a first redundant micro LED to emit a first primary color emission;each second subpixel includes a second primary micro LED and a second redundant micro LED to emit a second primary color emission;each third subpixel includes a third primary micro LED and a third redundant micro LED to emit a third primary color emission; andwherein the first, second and third primary color emissions are different from one another.5. The display panel of claim 2 , wherein each primary micro LED and each redundant micro LED is a separate device that has ...

SEMICONDUCTOR DEVICE

According to one embodiment, a semiconductor device includes a semiconductor chip, first and second conductive members, a first connection member, and a resin portion. The first conductive member includes first and second portions. The second portion is electrically connected to the semiconductor chip. A direction from the semiconductor chip toward the second portion is aligned with a first direction. A direction from the second portion toward the first portion is aligned with a second direction crossing the first direction. The second conductive member includes a third portion. The first connection member is provided between the first and third portion. The first connection member is conductive. The resin portion includes a first partial region. The first partial region is provided around the first and third portions, and the first connection member. The first portion has a first surface opposing the first connection member and including a recess and a protrusion. 1. A semiconductor device , comprising:a semiconductor chip;a first conductive member including a first portion and a second portion, the second portion being electrically connected to the semiconductor chip, a direction from the semiconductor chip toward the second portion being aligned with a first direction, a direction from the second portion toward the first portion being aligned with a second direction crossing the first direction;a second conductive member including a third portion; anda first connection member provided between the first portion and the third portion, the first connection member being conductive,the first portion having a first surface opposing the first connection member,the first surface including a recess and a protrusion,the recess including a first bottom portion, and a second distance,the second distance being a distance along the first direction between the recess and the third portion, the second distance increasing along an orientation from the second portion toward the ...

SOLDER PASTE

A solder paste that contains or consists of (i) 10-30% by weight of at least one type of particles that each contain a phosphorus fraction of >0 to ≦500 wt-ppm and are selected from copper particles, copper-rich copper/zinc alloy particles, and copper-rich copper/tin alloy particles, (ii) 60-80% by weight of at least one type of particles selected from tin particles, tin-rich tin/copper alloy particles, tin-rich tin/silver alloy particles, and tin-rich tin/copper/silver alloy particles, and (iii) 3-30% by weight solder flux, in which the mean particle diameter of metallic particles (i) and (ii) is ≦15 μm.

Semiconductor device

A semiconductor device includes: a semiconductor chip; a case having a frame portion that has an inner wall portion surrounding an housing area in which the semiconductor chip is disposed; a buffer member provided on at last part of the inner wall portion of the case on a side of the housing area; a low expansion member provided on said at least part of the inner wall portion with the buffer member interposed therebetween on the side of the housing area; and a sealing member that seals the housing area, wherein the buffer member has a smaller elastic modulus than the case and the sealing member, and wherein the low expansion member has a smaller linear expansion coefficient than the case and the sealing member.

CHIP ARRANGEMENTS

A chip arrangement including a chip comprising a chip back side; a back side metallization on the chip back side, the back side metallization including a plurality of layers; a substrate comprising a surface with a metal layer; a zinc-based solder alloy configured to attach the back side metallization to the metal layer, the zinc-based solder alloy having by weight 8% to 20% aluminum, 0.5% to 20% magnesium, 0.5% to 20% gallium, and the balance zinc; wherein the metal layer is configured to provide a good wettability of the zinc-based solder alloy on the surface of the substrate. The plurality of layers may include one or more of a contact layer configured to contact a semiconductor material of the chip back side; a barrier layer; a solder reaction, and an oxidation protection layer configured to prevent oxidation of the solder reaction layer. 1. A chip arrangement comprising:a chip comprising a chip back side;a back side metallization on the chip back side, the back side metallization comprising a plurality of layers;a substrate comprising a surface with a metal layer;a zinc-based solder alloy configured to attach the back side metallization to the metal layer, the zinc-based solder alloy having by weight 8% to 20% aluminum, 0.5% to 20% magnesium, 0.5% to 20% gallium, and the balance zinc;wherein the metal layer is configured to provide a good wettability of the zinc-based solder alloy on the surface of the substrate.2. The chip arrangement of claim 1 , wherein the zinc-based solder alloy is represented by the chemical formula ZnAlGaMg.3. The chip arrangement of claim 1 , wherein the zinc-based solder alloy is represented by the chemical formula ZnAlGaMg.4. The chip arrangement of claim 1 , wherein the substrate is formed by a material selected from a group of materials consisting of:lead;copper;nickel;silver; anda ceramic.5. The chip arrangement of claim 1 , wherein the metal layer comprises at least one of: silver claim 1 , gold claim 1 , nickel claim 1 , platinum ...

Semiconductor device

A semiconductor device has a resistance element including a metal block, a resin layer disposed on the metal block, and a resistance film disposed on the resin layer and an insulated circuit board including an insulating plate and a circuit pattern disposed on the insulating plate and having a bonding area on a front surface thereof to which a back surface of the metal block of the resistance element is bonded. The area of the circuit pattern is larger in plan view than that of a front surface of the resistance element. The metal block has a thickness greater than that of the circuit pattern in a direction orthogonal to the back surface of the metal block. As a result, the metal block properly conducts heat generated by the resistance film of the resistance element to the circuit pattern.

Three dimensional structure memory

3차원구조(3DS) 메모리(100)는 다른 층상에서 메모리 회로(103)와 제어 로직 회로(101)간의 물리적 분리를 허용함으로써 각 층이 독립적으로 최적화될 수 있다. 하나의 제어 로직 회로(101)가 감소된 비용으로 수개의 메모리 회로(103)들을 만족시킨다. 3차원구조 메모리(100)의 제작은 메모리 회로(103)를 두께 50 마이크론 이하로 씨닝하고, 아직 웨이퍼 기판 형태인 회로 스택에 접착시키는 것을 포함한다. 고밀도 미립자로 된 층간 수직 버스 배선(105)이 사용된다. 3차원구조 메모리(100)의 제작방법은 몇가지 성능 및 물리적 크기의 효율화를 달성하였으며, 이미 정립된 반도체 공정기술로 실시되어진다. The three-dimensional (3DS) memory 100 allows each layer to be independently optimized by allowing physical separation between the memory circuit 103 and the control logic circuit 101 on different layers. One control logic circuit 101 satisfies several memory circuits 103 at a reduced cost. Fabrication of the three-dimensional structure memory 100 involves thinning the memory circuit 103 to a thickness of 50 microns or less and adhering to a circuit stack still in the form of a wafer substrate. An interlayer vertical bus wiring 105 of high density fine particles is used. The manufacturing method of the three-dimensional structure memory 100 has achieved several performance and efficiency of physical size, and is implemented by the semiconductor processing technology that has already been established.

Light emitting assembly and method of manufacturing light emitting assembly

수직 GaN-계 LED는 실리콘 웨이퍼 위에 에피택셜 LED 구조체를 성장시킴으로써 만들어진다. 은 층이 추가되고 450℃ 초과의 온도를 견딜 수 있을 정도로 어닐링된다. 장벽 층(예를 들어, Ni/Ti)은 결합 금속이 은 내로 확산하는 것을 방지하기 위해 450℃ 초과에서 5분 동안 유효하게 제공된다. 그 다음, 최종 장치 웨이퍼 구조체는 380℃ 초과에서 용융되는 고온 결합 금속(예를 들어, AlGe)을 사용하여 캐리어 웨이퍼 구조체에 웨이퍼 결합된다. 웨이퍼 결합 후, 실리콘은 제거되고 금 무함유 전극(예를 들어, Al)이 추가되고, 구조체는 싱귤레이트된다. 전극 금속과 호환할 수 있는 고온 솔더(예를 들면, ZnAl)가 다이 부착을 위해 사용된다. 다이 부착은 결합 금속을 용융시키거나 그렇지 않으면 장치를 손상시키지 않고도 380℃ 초과에서 10초 동안 발생한다. 전체 LED가 금을 포함하지 않으며, 결과적으로 높은 볼륨의 금 무함유 반도체 제조 시설에서 제조가능하다. Vertical GaN-based LEDs are made by growing an epitaxial LED structure on a silicon wafer. A silver layer is added and annealed to a temperature above 450 [deg.] C. The barrier layer (e.g., Ni / Ti) is effectively provided at 450 占 폚 for 5 minutes to prevent the bonding metal from diffusing into the silver. The final device wafer structure is then wafer bonded to the carrier wafer structure using a high temperature bonding metal (e. G., AlGe) that melts above &lt; RTI ID = 0.0 &gt; 380 C. &lt; / RTI &gt; After wafer bonding, the silicon is removed and a gold-free electrode (e. G., Al) is added and the structure is singulated. High temperature solder (e.g., ZnAl) compatible with the electrode metal is used for die attachment. The die attach occurs for 10 seconds at temperatures above 380 DEG C without melting the bond metal or otherwise damaging the device. The entire LED does not contain gold, and as a result, it can be manufactured in a high volume gold-free semiconductor manufacturing facility.

Batch diffusion soldering and electronic devices produced by batch diffusion soldering

A method of batch soldering includes: forming a soldered joint between a metal region of a first semiconductor die and a metal region of a substrate using a solder preform via a soldering process which does not apply pressure directly to the first semiconductor die, the solder preform having a maximum thickness of 30 μm and a lower melting point than the metal regions; setting a soldering temperature of the soldering process so that the solder preform melts and fully reacts with the metal region of the first semiconductor die and the metal region of the substrate to form one or more intermetallic phases throughout the entire soldered joint, each intermetallic phase having a melting point above the preform melting point and the soldering temperature; and soldering a second semiconductor die to the same or different metal region of the substrate, without applying pressure directly to the second semiconductor die.

High temperature gold-free wafer bonding for light emitting diodes

A vertical GaN-based LED is made by growing an epitaxial LED structure on a silicon wafer. A silver layer is added and annealed to withstand >450° C. temperatures. A barrier layer (e.g., Ni/Ti) is provided that is effective for five minutes at >450° C. at preventing bond metal from diffusing into the silver. The resulting device wafer structure is then wafer bonded to a carrier wafer structure using a high temperature bond metal (e.g., AlGe) that melts at >380° C. After wafer bonding, the silicon is removed, gold-free electrodes (e.g., Al) are added, and the structure is singulated. High temperature solder (e.g., ZnAl) that is compatible with the electrode metal is used for die attach. Die attach occurs at >380° C. for ten seconds without melting the bond metal or otherwise damaging the device. The entire LED contains no gold, and consequently is manufacturable in a high-volume gold-free semiconductor fabrication facility.

Three dimensional structure integrated circuit fabrication process

A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

Copper paste for bonding, manufacturing method of bonded body and manufacturing method of semiconductor device

Laminated composite made up of an electronic substrate and a layer arrangement comprising a reaction solder

Laminated composite ( 10 ) comprising at least one electronic substrate ( 11 ) and an arrangement of layers ( 20, 30 ) made up of at least a first layer ( 20 ) of a first metal and/or a first metal alloy and of a second layer ( 30 ) of a second metal and/or a second metal alloy adjacent to this first layer ( 20 ), wherein the melting temperatures of the first and second layers are different, and wherein, after a thermal treatment of the arrangement of layers ( 20, 30 ), a region with at least one intermetallic phase ( 40 ) is formed between the first layer and the second layer, wherein the first layer ( 20 ) or the second layer ( 30 ) is formed by a reaction solder which consists of a mixture of a basic solder with an AgX, CuX or NiX alloy, wherein the component X of the AgX, CuX or NiX alloy is selected from the group consisting of B, Mg, Al, Si, Ca, Se, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Y, Zr, Nb, Mo, Ag, In, Sn, Sb, Ba, Hf, Ta, W, Au, Bi, La, Ce, Pr, Nd, Gd, Dy, Sm, Er, Tb, Eu, Ho, Tm, Yb and Lu and wherein the melting temperature of the AgX, CuX or NiX alloy is greater than the melting temperature of the basic solder. The invention also relates to a method for forming a laminated composite ( 10 ) and to a circuit arrangement containing a laminated composite ( 10 ) according to the invention.

Method for manufacturing soldered products

【課題】治具を用いることなく半田付けを行う半田付け製品の製造方法を得ること。【解決手段】本願の半田付け製品の製造方法は、半田と、半田を仮止めする仮固定剤とを提供する提供工程と；仮固定剤で半田を半田付け対象物に仮止めする仮止工程と；半田を仮止めした半田付け対象物を、真空中に置くか、または、半田が溶融する温度よりも低い所定の温度に加熱して、仮固定剤を気化させ半田と半田付け対象物の間に間隙を生じさせる気化工程と；気化工程に並行して、またはその後に、半田が溶融する温度よりも低い所定の温度で、気化工程により残された半田と半田付け対象物を還元ガスで還元する還元工程と；還元工程の後に、半田付け対象物を半田が溶融する温度以上の所定の温度に加熱して半田を溶融する半田溶融工程を備える。【選択図】図１ A method for manufacturing a soldered product in which soldering is performed without using a jig is provided. A method of manufacturing a soldered product of the present application includes a providing step of providing solder and a temporary fixing agent for temporarily fixing the solder; and a temporary fixing step of temporarily fixing the solder to the soldering object with the temporary fixing agent. And placing the soldering object temporarily fixed with solder in a vacuum or heating to a predetermined temperature lower than the temperature at which the solder melts to vaporize the temporary fixing agent and A vaporizing step that creates a gap therebetween; parallel to or after the vaporizing step, the solder remaining in the vaporizing step and the soldering object are reduced with a reducing gas at a predetermined temperature lower than the temperature at which the solder melts. A reduction step of reducing; and a solder melting step of melting the solder by heating the soldering object to a predetermined temperature equal to or higher than a temperature at which the solder melts after the reduction step. [Selection] Figure 1

Semiconductor device

A conventional configuration such that the copper electrode bars which are connected to the P, U and N output electrodes of the inverter module respectively are allowed to come in close proximity to each other and are disposed above the upper faces of the chips has been insufficient for the object of lowering unnecessary inductance components. The semiconductor apparatus includes: the first lead frame (1); the second lead frame (2); the second insulation resin (8) which is disposed between the first lead frame (1) and the second lead frame (2); the sealing resin (9) which seals the semiconductor elements (4a) and (4b), the first lead frame (1) and the second lead frame (2); the electric wiring part (5) which electrically connects the semiconductor elements (4a) and (4b) and the first lead frame (1); and the interlayer connecting part (6) which electrically connects the first lead frame (1) and the second lead frame (2).

Semiconductor chip, method for producing semiconductor chip and method for soldering semiconductor chip to carrier

本发明涉及半导体芯片及其制造方法和焊接半导体芯片与载体的方法。公开了一种半导体芯片，具有半导体本体和施加到半导体本体上的芯片金属化，该芯片金属化具有背离半导体本体的下侧。具有数目为N1≥1或者N1≥2的第一子层以及数目为N2≥2的第二子层的层堆叠被施加到下侧上。第一子层和第二子层交替地相继地被布置，使得在能够由第一子层构成的每一个第一对的第一子层之间布置有至少一个第二子层，并且在能够由第二子层构成的每一个第二对的第二子层之间布置有至少一个第一子层。每一个第一子层都具有合金金属或者由合金金属组成，每一个第二子层都具有焊料或者由焊料组成，该焊料能够与邻接有关的第二子层的第一子层的合金金属一起构成金属间相。

Semiconductor device and method for forming the same

A method for forming a semiconductor device is provided. The method includes providing a substrate. The method includes forming a mask layer over a surface of the substrate. The mask layer has an opening over a portion of the surface. The method includes depositing a conductive layer over the surface and the mask layer. The method includes removing the mask layer and the conductive layer over the mask layer. The conductive layer remaining after the removal of the mask layer and the conductive layer over the mask layer forms a conductive pad. The method includes bonding a device to the conductive pad through a solder layer. The conductive pad is embedded in the solder layer.

A method for assembling a carrier with components, pigment for loading a carrier with a component and method for producing a pigment

Das Verfahren zum Bestücken eines Trägers umfasst einen Schritt A), in dem eine Mehrzahl von Pigmenten (100) mit jeweils einem elektronischen Bauelement (1) bereitgestellt wird. Ferner umfasst jedes Pigment ein aufschmelzbares Lötmaterial (2), das unmittelbar an eine Montageseite (10) des Bauelements angrenzt. Zumindest 63 Vol.-% jedes Pigments sind durch das Lötmaterial gebildet. Die Montageseite jedes Bauelements weist eine höhere Benetzbarkeit mit dem aufgeschmolzenen Lötmaterial auf als eine Oberseite (12) und eine Seitenfläche (11) des Bauelements. In einem Schritt B) wird ein Träger (200) mit Pigmentlandeflächen (201) bereitgestellt, wobei die Pigmentlandeflächen eine höhere Benetzbarkeit mit dem aufgeschmolzenen Lötmaterial der Pigmente aufweisen als die Bereiche lateral neben den Pigmentlandeflächen und als die Seitenflächen und als die Oberseiten der Bauelemente. In einem Schritt C) werden die Pigmente auf den Träger aufgebracht. In einem Schritt D) werden die Pigmente aufgeheizt, sodass das Lötmaterial schmilzt. The method for loading a carrier comprises a step A), in which a plurality of pigments (100) is provided, each with an electronic component (1). Further, each pigment comprises a reflowable solder material (2) immediately adjacent to a mounting side (10) of the device. At least 63% by volume of each pigment is formed by the solder material. The mounting side of each device has a higher wettability with the reflowed solder material than an upper surface (12) and a side surface (11) of the device. In step B), a support (200) having pigment land areas (201) is provided, the pigment land areas having higher wettability with the reflowed solder material of the pigments than the areas laterally adjacent to the pigment land areas and the side surfaces and top surfaces of the building elements. In a step C), the pigments are applied to the support. In a step D) the pigments are heated so that the solder material melts.

ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING ELECTRONIC DEVICE

Chip assembly

A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.

Semiconductor device and die bonding structure thereof

An embodiment of the present invention relates to a semiconductor device and a die bonding structure thereof. The purpose of the present invention is to provide the semiconductor device and the die bonding structure thereof, which improve electrical conductivity and mechanical properties by not forming a compound between a semiconductor die or a lead frame and metal, improve wetting properties, and reduce aggregation. To achieve this, the semiconductor device comprises a semiconductor die; a barrier layer formed on the surface of the semiconductor die; a first metal layer formed on the barrier layer; a central metal layer formed on the first metal layer; and a second metal layer formed on the central metal layer, wherein the first and second metal layers have a first melting temperature, and the central metal layer has a second melting temperature lower than the first melting temperature.

Solder and die-bonding structure

A solder includes zinc as a main component and the solder contains 6 to 8 mass percent of indium. A solder includes zinc as a main component, wherein the solder contains only indium. In a die-bonding structure in which a semiconductor chip is connected to a bonded member by a solder, the solder made of zinc as a main component and contains indium.

Method of transferring and bonding an array of micro devices

本发明描述了静电转移头阵列组件和将微型器件阵列转移并键合到接收衬底的方法。在一个实施例中，方法包括：利用支撑静电转移头阵列的静电转移头组件从承载衬底拾取微型器件阵列，使接收衬底与微型器件阵列接触，从静电转移头组件转移能量以将微型器件阵列键合到接收衬底，以及将微型器件阵列释放到接收衬底上。

Semiconductor components and processes for their formation

Verfahren zum Ausbilden eines Halbleiterbauelements (1), wobei das Verfahren aufweist:Ausbilden einer Kontaktschicht (55), die eine oder mehrere Metallschichten aufweist, über einer ersten Hauptoberfläche (12) eines Substrats (10), wobei das Substrat (10) durch Schneidbereiche (121), in denen freiliegende Oberflächen ausgebildet sind, getrennte Bauelementbereiche (23) aufweist, wobei die Kontaktschicht (55) in dem Schneidbereich (121) und den Bauelementbereichen (23) angeordnet ist;Ausbilden einer strukturierten Lötschicht (70) über den Bauelementbereichen (23), wobei die Kontaktschicht (55) nach dem Ausbilden der strukturierten Lötschicht (70) in dem Schneidbereich (121) frei liegt, wobei die strukturierte Lötschicht (70) dicker ist als das Substrat (10); undSchneiden durch die Kontaktschicht (55) und das Substrat (10) in den Schneidbereichen (121). A method for forming a semiconductor component (1), the method comprising: forming a contact layer (55), which has one or more metal layers, over a first main surface (12) of a substrate (10), the substrate (10) being formed by cutting regions ( 121), in which exposed surfaces are formed, has separate component areas (23), the contact layer (55) being arranged in the cutting area (121) and the component areas (23); forming a structured soldering layer (70) over the component areas (23) ), wherein the contact layer (55) is exposed after the formation of the structured soldering layer (70) in the cutting area (121), the structured soldering layer (70) being thicker than the substrate (10); and cutting through the contact layer (55) and the substrate (10) in the cutting areas (121).

Semiconductor device and method for manufacturing the same

According to one embodiment, a semiconductor device includes a semiconductor element, an interconnection layer, and a bonding layer. The interconnection layer includes Cu. The bonding layer includes a first alloy that is an alloy of Cu and a first metal other than Cu between the semiconductor element and the interconnection layer. A melting point of the first alloy is higher than a melting point of the first metal.

Active matrix emissive micro led display

本文描述一種顯示面板及一種形成顯示面板之方法。顯示面板可包括薄膜電晶體基板，該基板包括像元區域及非像元區域。像元區域包括岸開口(bank opening)陣列及岸開口陣列內之底部電極陣列。將微型LED裝置陣列黏合至岸開口陣列內之對應底部電極陣列。形成頂部電極層陣列，從而將微型LED裝置陣列電連接至非像元區域中之接地線。

Bonded structure

於經由以Bi為主成分之接合材料104將半導體元件102接合於Cu電極103上而成之接合構造體106中，經由如楊氏模數自接合材料104朝向被接合材料(半導體元件102、Cu電極103)傾斜地增大之積層體209a而接合半導體元件102與Cu電極103，藉此確保對於功率半導體模組之使用時之溫度循環中產生之熱應力的應力緩和性。

Three dimensional structure memory

一种三维结构(3DS)存储器(100)使得能够将存储器电路(103)和控制逻辑(101)物理上分离到不同的层(103)上，致使可以分别地优化各个层。几个存储器电路(103)有一个控制逻辑(101)就够了，从而降低了成本。3DS存储器(100)的制造涉及到将存储器电路(103)减薄到厚度小于50微米以及将电路键合到电路叠层，同时仍然呈晶片衬底形式。采用了细粒高密度层间垂直总线互连(105)。3DS存储器(100)制造方法使得能够实现几种性能和物理尺寸效能，并且是用现有的半导体工艺技术实现的。

Semiconductor device and manufacturing method for semiconductor device

Semiconductor device and bonding material for semiconductor device

Chip arrangements

A chip arrangement including a chip comprising a chip back side; a back side metallization on the chip back side, the back side metallization including a plurality of layers; a substrate comprising a surface with a metal layer; a zinc-based solder alloy configured to attach the back side metallization to the metal layer, the zinc-based solder alloy having by weight 8% to 20% aluminum, 0.5% to 20% magnesium, 0.5% to 20% gallium, and the balance zinc; wherein the metal layer is configured to provide a good wettability of the zinc-based solder alloy on the surface of the substrate. The plurality of layers may include one or more of a contact layer configured to contact a semiconductor material of the chip back side; a barrier layer; a solder reaction, and an oxidation protection layer configured to prevent oxidation of the solder reaction layer.

Light emitting diode display with redundancy scheme

A display panel and method of manufacture are described. In an embodiment, a display substrate includes a pixel area and a non-pixel area. An array of subpixels and corresponding array of bottom electrodes are in the pixel area. An array of micro LED devices are bonded to the array of bottom electrodes. One or more top electrode layers are formed in electrical contact with the array of micro LED devices. In one embodiment a redundant pair of micro LED devices are bonded to the array of bottom electrodes. In one embodiment, the array of micro LED devices are imaged to detect irregularities.

Semiconductor device, power converter, and method of manufacturing semiconductor device

A semiconductor device includes a first circuit, a second circuit, a wiring member, and a bonding material. The wiring member is connected to one of the first circuit and the second circuit. The bonding material is connected to the other of the first circuit and the second circuit. The wiring member includes a first end, a second end, and a top. The first end and the second end are connected to one of the first circuit and the second circuit. The top is located between the first end and the second end. The top is connected to the other of the first circuit and the second circuit with the bonding material in between.

Hybrid bonding materials comprising ball grid arrays and metal inverse opal bonding layers, and power electronics assemblies incorporating the same

A hybrid bonding layer includes a metal inverse opal (MIO) layer with a plurality of hollow spheres and a predefined porosity, and a ball grid array (BGA) disposed within the MIO layer. The MIO layer and the BGA may be disposed between a pair of bonding layers. The MIO layer and the BGA each have a melting point above a TLP sintering temperature and the pair of bonding layers each have a melting point below the TLP sintering temperature such that the hybrid bonding layer can be transient liquid phase bonded between a substrate and a semiconductor device. The pair of bonding layers may include a first pair of bonding layers with a melting point above the TLP sintering temperature and a second pair of bonding layers with a melting point below the TLP sintering temperature.

Multi-layered composite bonding materials and power electronics assemblies incorporating the same

A multilayer composite bonding material for transient liquid phase bonding a semiconductor device to a metal substrate includes thermal stress compensation layers sandwiched between a pair of bonding layers. The thermal stress compensation layers may include a core layer with a first stiffness sandwiched between a pair of outer layers with a second stiffness that is different than the first stiffness such that a graded stiffness extends across a thickness of the thermal stress compensation layers. The thermal stress compensation layers have a melting point above a sintering temperature and the bonding layers have a melting point below the sintering temperature. The graded stiffness across the thickness of the thermal stress compensation layers compensates for thermal contraction mismatch between the semiconductor device and the metal substrate during cooling from the sintering temperature to ambient temperature.

Layered composite of a substrate film and of a layer assembly comprising a sinterable layer made of at least one metal powder and a solder layer

本发明涉及一种复合层（10）、特别是用于将作为接合副的电子构件连接的复合层，其包括至少一个承载膜（11）和被施加在所述承载膜上的层组件（12），所述层组件包括至少一个被施加在所述承载膜（11）上的、包含至少一种金属粉末的可烧结的层（13）和被施加在所述可烧结的层（13）上的焊接层（14）。此外，本发明涉及一种用于形成复合层的方法、一种包括根据本发明的复合层（10）的电路组件以及复合层（10）在用于电子构件的接合方法中的应用。

Semiconductor component support and semiconductor device

本发明提供半导体元件安装构件以及半导体装置，半导体元件安装构件包括供半导体元件安装的金属的元件安装部，所述元件安装部包括在俯视下一部分形成切口的金属区域，所述金属区域的切口包含第一区域与第二区域，该第二区域与所述第一区域连续且位于比所述第一区域靠外侧的位置，该第二区域比所述第一区域的宽度宽，所述第一区域的至少一部分位于半导体元件的安装侧主表面的正下方。

Semiconductor device and method of manufacturing the same

【課題】半導体装置の信頼性を向上させる。 【解決手段】ダイパッド６と、ダイパッド６に搭載されたＳｉＣチップ１と、ダイパッド６とＳｉＣチップ１とを接合する多孔質の第１焼結Ａｇ層１６と、第１焼結Ａｇ層１６の表面を覆い、かつフィレット状に形成された補強樹脂部１７とを有している。さらにＳｉＣチップ１のソース電極２と電気的に接続するソースリード９と、ゲート電極３と電気的に接続するゲートリードと、ドレイン電極４と電気的に接続するドレインリードと、ＳｉＣチップ１、第１焼結Ａｇ層１６およびダイパッド６の一部を覆う封止体１４とを有しており、補強樹脂部１７は、ＳｉＣチップ１の側面１ｃの一部を覆っている。 【選択図】図２

Diffusion soldering preform with varying surface profile

A method of soldering includes providing a substrate having a first metal joining surface, providing a semiconductor die having a second metal joining surface, providing a solder preform having a first interface surface and a second interface surface, arranging the solder preform between the substrate and the semiconductor die such that the first interface surface faces the first metal joining surface and such that the second interface surface faces the second metal joining surface, and performing a mechanical pressure-free diffusion soldering process that forms a soldered joint between the substrate and the semiconductor die by melting the solder preform and forming intermetallic phases in the solder. One or both of the first interface surface and the second interface surface has a varying surface profile that creates voids between the solder preform and one or both of the substrate and the semiconductor die before the melting of the solder preform.

Semiconductor device

インバータモジュールのＰ、ＵおよびＮ出力電極にそれぞれ接続される銅電極バーを互いに近接させてチップの上面に配置する従来の構成では、不要なインダクタンス成分を低減する目的には不十分であった。第１のリードフレーム（１）と、第２のリードフレーム（２）と、第１のリードフレーム（１）と、第２のリードフレーム（２）と、の間に配置された第２の絶縁樹脂（８）と、半導体素子（４ａ）および（４ｂ）と、第１のリードフレーム（１）と、第２のリードフレーム（２）と、を封止する封止樹脂（９）と、半導体素子（４ａ）および（４ｂ）と、第１のリードフレーム（１）と、を電気的に接続する電気配線部（５）と、第１のリードフレーム（１）と、第２のリードフレーム（２）と、を電気的に接続する層間接続部（６）と、を備える、半導体装置。 The conventional configuration in which the copper electrode bars respectively connected to the P, U and N output electrodes of the inverter module are arranged close to each other on the upper surface of the chip is insufficient for the purpose of reducing unnecessary inductance components. Second insulation disposed between the first lead frame (1), the second lead frame (2), the first lead frame (1), and the second lead frame (2). A sealing resin (9) for sealing the resin (8), the semiconductor elements (4a) and (4b), the first lead frame (1), and the second lead frame (2); An electrical wiring portion (5) for electrically connecting the elements (4a) and (4b) and the first lead frame (1), a first lead frame (1), and a second lead frame ( 2) and an interlayer connection portion (6) for electrically connecting the semiconductor device.

Semiconductor module and method for manufacturing semiconductor module

The method of chip package and manufacture chip package

本发明涉及芯片封装和制造芯片封装的方法。提供一种制造芯片封装的方法，该方法包括：在载体上形成层布置；在层布置上布置包括一个或多个接触焊盘的芯片，其中芯片覆盖层布置的至少一部分；以及选择性地去除层布置的一个或多个部分，并使用芯片作为掩模，使得由芯片覆盖的层布置的至少一部分不被去除。

Method of forming metal bonding layer and method of manufacturing semiconductor light emitting device using the same

A method of forming a metal bonding layer includes forming first and second bonding metal layers on one surfaces of first and second bonding objects, respectively. The second bonding object is disposed on the first bonding object such that the first bonding metal layer and the second bonding metal layer face each other. A eutectic metal bonding layer is formed through a reaction between the first and second bonding metal layers. At least one of the first bonding metal layer and the second bonding metal layer includes an oxidation prevention layer formed on an upper surface thereof. The oxidation prevention layer is formed of a metal having an oxidation reactivity lower than an oxidation reactivity of the bonding metal layer on the upper surface which the oxidation prevention layer is disposed.

Power converter

この電力変換装置は、電力変換用半導体素子（２、３）と、略平坦な上端面（４ａ、５ａ、６ａ、７ａ）を有する電極用導体（４、５、６、７）と、封止材（１０）とを備え、封止材は、封止材の上面において、電極用導体の略平坦な上端面を露出させるとともに、露出された電極用導体の上端面において外部との電気的接続が行われるように構成されている。 This power conversion device includes a power conversion semiconductor element (2, 3), an electrode conductor (4, 5, 6, 7) having a substantially flat upper end surface (4a, 5a, 6a, 7a), a sealing And the sealing material exposes the substantially flat upper end surface of the electrode conductor on the upper surface of the sealing material and electrically connects to the outside on the exposed upper end surface of the electrode conductor. Is configured to be performed.

METHOD OF JOINING METAL JOINTED BODY, SEMICONDUCTOR DEVICE, WAVEGUIDE AND JOINTED MEMBER

Joint product, process for producing the joint product, power semiconductor module, and process for producing the power semiconductor module

本发明的以锌作为主成分的焊接材料(55)，在除去了锌系材料(50)表面的氧化膜(501)后、或者在表面不存在氧化膜(501)的状态下，在所述表面设置以其氧化物比所述氧化膜(501)容易被还原的金属作为主成分的覆盖层(51)。另外，本发明的接合体及功率半导体模块在接合部中使用所述锌系焊接材料(55)，在接合后所述覆盖层(51)消失。

Joint Material, and Jointed Body

不需金屬化處理，而將陶瓷、半導體、玻璃等基材在銲料材程度的處理溫度下接合。 接合構造體，係為複數個基材透過接合層而接合，且至少其中一方的基材為陶瓷、半導體、玻璃任一者之基材，接合材層中含有金屬與氧化物，氧化物含有V與Te，氧化物存在於金屬與基材之間。接合材，係為包含成分中含有V、Te之氧化物玻璃及金屬粒子以及溶媒之膏狀、或為埋入了成分中含有V、Te之氧化物玻璃粒子之箔或板狀、或為包含成分中含有V、Te之氧化物玻璃層以及金屬層之箔或板狀。

Method for soldering one or more components

Die Erfindung betrifft ein Lötverfahren für ein Bauteil auf einen Träger. Dabei wird das Lot als Lotdraht oder Lotbändchen bereitgestellt und mit einem Ultraschallbonder auf eine Montage- oder Befestigungsfläche appliziert. Hernach wird das Bauteil positioniert und das Lot aufgeschmolzen. Schließlich erstarrt das Lot unter Ausbildung einer Lötverbindung des Bauteils mit dem Träger. The invention relates to a soldering method for a component on a carrier. The solder is provided as a solder wire or solder ribbon and applied to a mounting or fastening surface using an ultrasonic bonder. The component is then positioned and the solder melted. Finally, the solder solidifies, forming a soldered connection between the component and the carrier.

SEMICONDUCTOR COMPONENT

Solder material, layer structure and forming method thereof, chip package and forming method thereof, chip arrangement and forming method thereof

焊料材料、层结构及其形成方法、芯片封装及其形成方法、芯片布置及其形成方法。提供一种焊料材料。焊料材料可以包括镍和锡，其中镍可以包括第一量的颗粒和第二量的颗粒，其中第一量的颗粒和第二量的颗粒的和是镍的总量或更少，其中第一量的颗粒在镍的总量的5 at%和60 at%之间，其中第二量的颗粒在镍的总量的10 at%和95 at%之间，其中第一量的颗粒的颗粒具有第一大小分布，其中第二量的颗粒的颗粒具有第二大小分布，其中第一量的颗粒的30%至70%具有根据第一大小分布最高数量的颗粒具有的颗粒大小附近约5μm的范围中的颗粒大小，并且其中第二量的颗粒的30%至70%具有根据第二大小分布最高数量的颗粒具有的颗粒大小附近约5μm的范围中的颗粒大小。

Layer composite of a carrier film and a layer arrangement comprising a sinterable layer of at least one metal powder and a solder layer

Die Erfindung betrifft einen Schichtverbund (10), insbesondere zum Verbinden von elektronischen Bauteilen als Fügepartner, umfassend mindestens eine Trägerfolie (11) und eine darauf aufgebrachte Schichtanordnung (12) umfassend mindestens eine auf die Trägerfolie (11) aufgebrachte, sinterbare Schicht (13) enthaltend mindestens ein Metallpulver und eine auf die sinterbare Schicht (13) aufgebrachte Lotschicht (14). Die Erfindung betrifft weiterhin ein Verfahren zur Ausbildung eines Schichtverbunds, eine Schaltungsanordnung enthaltend einen erfindungsgemäßen Schichtverbund (10) sowie die Verwendung eines Schichtverbunds (10) in einem Fügeverfahren für elektronische Bauteile. The invention relates to a layer composite (10), in particular for joining electronic components as joining partners, comprising at least one carrier film (11) and a layer arrangement (12) applied thereto comprising at least one sinterable layer (13) applied to the carrier film (11) at least one metal powder and a solder layer (14) applied to the sinterable layer (13). The invention further relates to a method for forming a layer composite, a circuit arrangement comprising a layer composite (10) according to the invention and the use of a layer composite (10) in a joining method for electronic components.

Bonded structure

This bonded structure (106) is created by bonding a semiconductor element (102) to a Cu electrode (103) via a bonding material (104) consisting primarily of Bi. The semiconductor element (102) and the Cu electrode (103) are bonded together via a laminated body (209a), which exhibits a Young's modulus that progressively increasing from the bonding material (104) toward the materials (semiconductor element (102), Cu electrode (103)) in order to ensure relaxation of a thermal stress attributable to the temperature cycle of a power semiconductor module during the use.

Semiconductor device and manufacturing method of the same

SEMI-CONDUCTOR COMPONENT

Ein Halbleiterbauteil beinhaltet einen Chip, der eine Montagefläche, eine Nicht-Montagefläche und eine Seitenwand aufweist, die die Montagefläche und die Nicht-Montagefläche verbindet, und der einen Überhangabschnitt aufweist, der an der Seitenwand weiter nach außen vorsteht als die Montagefläche, und mit einer Metallschicht, die die Montagefläche bedeckt. A semiconductor device includes a chip that has a mounting surface, a non-mounting surface, and a side wall connecting the mounting surface and the non-mounting surface, and which has an overhang portion that protrudes further outward on the side wall than the mounting surface, and with a Metal layer that covers the mounting surface.

Junction structure and manufacturing method of junction structure

Conductor is welded to aluminum metallization

一种将导体焊接到铝金属化物的方法包括：用替代金属氧化物层或替代金属合金氧化物层替代所述铝金属化物上的铝氧化物层。然后，至少部分地还原所述替代金属氧化物层中的或所述替代金属合金氧化物层中的替代金属氧化物。使用焊料材料将所述导体焊接到所述铝金属化物。

Display panel, display screen and preparation method of display screen

本申请的目的在于提供一种显示面板、显示屏及显示屏的制备方法，显示面板包括发光组件、驱动组件、多个第一导电件及多个第二导电件，发光组件包括多个发光单元，每个发光单元包括间隔设置的第一电极及第二电极，第一电极环绕第二电极；驱动组件包括多个驱动单元，一个驱动单元与一个发光单元对应设置，且不同的驱动单元对应不同的发光单元，驱动单元包括间隔设置的第三电极及第四电极，第三电极环绕第四电极；第一导电件连接第一电极和第三电极；第二导电件连接第二电极和第四电极。本申请的驱动组件和发光组件电连接的概率更大，有利于提升显示面板的制备良率，进而提高Mini LED显示屏和Micro LED显示屏的制备良率。

Power converter

Disclosed is a power converter which is provided with: semiconductor elements (2, 3) for power conversion; conductor sections (1, 4, 5, 6, 7) for connecting electrodes, said conductor sections electrically connecting a plurality of electrodes at the same potential and having substantially flat upper surfaces for electrically connecting with the outside; and a sealing material (10), which is provided so as to cover the semiconductor elements and expose the substantially flat upper surfaces of the conductor sections.

金属接合体、半导体装置、波导管及被接合构件的接合方法

本发明提供通过大气中的固相接合而接合、不发生接合材料的熔融所引起的溢出、因此能够提高尺寸稳定性的金属接合体。金属接合体(100)通过(A)使在作为被接合构件的Al基材(1)上依次层叠Zn膜(2)和Ag膜(3)的2个金属层叠体(10)的Ag膜(3)彼此对置，(B)使Ag膜(3)彼此接触，然后(C)一边加压一边进行加热，使Ag膜(3)彼此密合，进行固相接合而形成。完成的金属接合体(100)是在Ag‑Zn‑Al合金层(5)的两面设置Al‑Ag合金层(4)、将Al基材(1)彼此接合的部分。

半導体装置及び半導体装置の製造方法

显示面板、显示屏及显示屏的制备方法

本申请的目的在于提供一种显示面板、显示屏及显示屏的制备方法，显示面板包括发光组件、驱动组件、多个第一导电件及多个第二导电件，发光组件包括多个发光单元，每个发光单元包括间隔设置的第一电极及第二电极，第一电极环绕第二电极；驱动组件包括多个驱动单元，一个驱动单元与一个发光单元对应设置，且不同的驱动单元对应不同的发光单元，驱动单元包括间隔设置的第三电极及第四电极，第三电极环绕第四电极；第一导电件连接第一电极和第三电极；第二导电件连接第二电极和第四电极。本申请的驱动组件和发光组件电连接的概率更大，有利于提升显示面板的制备良率，进而提高Mini LED显示屏和Micro LED显示屏的制备良率。

半導体装置

半导体装置

本发明的目的在于提供一种能够提高半导体装置的散热性或者可靠性的技术。半导体装置(1)具有：基板(6)；多个焊料(7a、7b)，它们相互相邻且成分及浓度的至少一个相互不同；以及半导体芯片(8)，其具有通过多个焊料(7a、7b)而与基板(6)接合的接合面。半导体芯片(8)的接合面包含半导体芯片(8)的发热或者对接合对象的应力相互不同的多个接合区域(8a、8b)，多个焊料(7a、7b)与多个接合区域(8a、8b)对应地配设。

Height adaptable multilayer spacer

The invention relates to a metal layer stack for use in electronic components, in particular as a spacer in power electronic components, comprising n bulk metal layers and n or n+1 contact material layers, wherein the bulk metal layers and the contact material layers are stacked in an alternating manner and n is at least two. Additionally, the invention relates to a process for preparing the metal layer stack and a semiconductor module comprising such a metal layer stack.