METHOD AND APPARATUS FOR WIRE BONDING OF COATED WIRE

PURPOSE: To increase an adhesion between an outer lead and a coated wire while keeping the temperature at the chip side lower than the circuit destruction temperature by joining the coated wire to a second bonding section at the outer lead side by thermocompression or by thermocompression together with ultrasonic waves with the second bonding section heated to higher temperature than a first bonding section at the Chip side. CONSTITUTION: Betweem a bonding stage B and the central part A1 of a lead frame on which a chip 1 is mounted, a heat stage 4a is installed which is almost the same size with the chip 1. Apart from the heat stage 4a at the chip 1 side, another heat stages 4b are installed between the bonding stage B and the outer part A2 of the lead frame on which outer leads 2 are formed. On the upper surface of the chip 1, electrodes 1a and first bonding sections 1b where one end of coated wire 3 are joined by ball bonding using a capillary are formed. The outer lead 2 is made of Cu ...

BONDING WIRE AND INTEGRATED CIRCUIT DEVICE USING THE SAME

A bonding wire, characterized in that it comprises a core material comprising copper as its primary material, a different metal layer comprising a metal except copper formed on the core material, and a coating layer comprising an oxidation-resistant metal having a melting point higher than that of copper formed on the different metal layer; and an integrated circuit device using the bonding wire. The bonding wire can form a ball having a true circle shape over a wide range of the diameter of the ball, can be produced using a plating technique with no deterioration of a plating solution, and is excellent in the adhesion of the coating layer to the core material. © KIPO & WIPO 2007 ...

Light emitting device mount, light emitting apparatus including the same, and leadframe

Bounding wire and IC device using the same

A bounding wire, having the cord material and the capping layer formed on the aforementioned cord, wherein the capping layer is a made of metal having higher melting point than the cord, characterized by at least one of the followings: 1. The damped touching angle between the bounding wire and the capping material used when the cord melts is above 20 DEG; 2. Hang the bounding wire as its tip touches the horizontal plane then cut the bounding wire at 15 cm away from the tip, thus the circular curvature radius formed while the bounding wire drops to the aforementioned horizontal plane is above 35mm; 3. 0.2% of tolerance is above 0.115mN/m2 and under 0.165 mN/m2; 4. Vickers hardness of the capping layer is under 300.

METHOD OF BONDING METALS TOGETHER

Electronic component of a high frequency current suppression type and bonding wire for the same

In order to provide an electronic component of a high frequency current suppression type, which can completely suppress a high frequency current to prevent an electromagnetic interference from occurring even when it is used at a high frequency, and a bonding wire for the same, the semiconductor integrated circuit device (IC) (17) operates at a high speed in using at a high frequency band, and a predetermined number of terminals (19) are provided with a high frequency current suppressor (21) for attenuating a high frequency current passing through the terminals themselves. This high frequency current suppressor (21) is a thin film magnetic substance having a range from 0.3 to 20 (mum) in thickness, and is disposed on the entire surface of each terminal (19), covering a mounting portion to be mounted on a printed wiring circuit board (23) for mounting IC (17) and an edge including a connecting portion to a conductive pattern (25) disposed on the printed wiring circuit board (23). When the ...

BONDING WIRE AND INTEGRATED CIRCUIT DEVICE USING THE SAME

A bonding wire which has a core material and, formed on the core material, a coating layer comprising a metal having a melting point higher than that of the core material and further has at least one of the following characteristics: 1. the wet contact angle of the molten core material with the coating material is 20 degree or more, 2. the curvature radius of a circular arc, which is formed when the bonding wire is allowed to hang down so that the tip thereof contacts with a horizontal plane and the wire is cut at the point being upper from the tip by 15 cm and the cut wire is allowed to fall on the horizontal plane, is 35 mm or more. 3. 0.2 % offset yield strength is 0.115 to 0.165 mN/μm2, and 4. the coating layer has a Vickers hardness of 300 or less.

Verfahren zum Verbinden von Metallen

LIGHT EMITTING DEVICE MOUNT, LIGHT EMITTING APPARATUS INCLUDING THE SAME, AND LEADFRAME

METHOD OF BONDING METALS TOGETHER

METHOD OF BONDING METAL BODIES TOGETHER BY VIBRATORY ENERGY

... 1333848 Welding by pressure RCA CORPORATION 19 April 1971 [18 March 1970] 23835/71 Heading B3R In bonding a first body of gold, silver or copper to another metal body, a thin layer of nickel, iron, cobalt, magnesium, aluminium, palladium, germanium or silicon is disposed between the bodies and ultrasonic vibratory energy is applied to one of the bodies until the layer is worn away and the first metal body is adhered to the other body. A terminal wire 10 of gold, silver or copper coated by electroless plating or electroplating with the thin layer, is held in contact with a metal contact film 12 on a semi-conductor wafer and ultrasonic energy is applied to one of the bodies. The layer wears away to expose the surface of the wire which becomes welded to the layer 12. The metal layer may be between 200 and 25,000Š. In an example, gold wires plated with nickel are bonded to gold plated "Kovar" (Registered Trade Mark).

METHOD OF BONDING METALS TOGETHER

Electronic component of a high frequency current suppression type and bonding wire for the same

In order to provide an electronic component of a high frequency current suppression type, which can completely suppress a high frequency current to prevent an electromagnetic interference from occurring even when it is used at a high frequency, and a bonding wire for the same, the semiconductor integrated circuit device (IC) (17) operates at a high speed in using at a high frequency band, and a predetermined number of terminals (19) are provided with a high frequency current suppressor (21) for attenuating a high frequency current passing through the terminals themselves. This high frequency current suppressor (21) is a thin film magnetic substance having a range from 0.3 to 20 (m) in thickness, and is disposed on the entire surface of each terminal (19), covering a mounting portion to be mounted on a printed wiring circuit board (23) for mounting IC (17) and an edge including a connecting portion to a conductive pattern (25) disposed on the printed wiring circuit board (23). When the top ...

Elektronisches Bauteil bei dem hochfrequente Ströme unterdrückt werden und Bonddraht dafür

BONDING WIRE AND INTEGRATED CIRCUIT DEVICE USING THE SAME

LIGHT EMITTING DEVICE MOUNT, LEADFRAME, AND LIGHT EMITTING APPARATUS

A light emitting device mount includes a positive lead terminal, and a negative lead terminal. Each of the positive and negative lead terminal includes a first main surface, a second main surface, and an end surface. The end surface is provided between the first main surface and the second main surface. The end surface includes a first recessed surface area and a second recessed surface area. The first recessed surface area is extending from a first point of the first main surface in cross section. The second recessed surface area is extending from a second point of the second main surface in cross section. The first and second recessed surface areas define a protruding portion protruding outwardly.

AI WIRING MATERIAL

There is provided a novel Al wiring material that achieves both of a suppression of chip damage and a thermal shock resistance. In aspect 1, the Al wiring material includes an Al core material and an Al coating layer formed on a surface of the Al core material, and satisfies 1.2≤H1h/H1swhere H1his a Vickers hardness of the Al core material (Hv) and H1sis a Vickers hardness of the Al coating layer (Hv). In aspect 2, the Al wiring material includes an Al core material and an Al coating layer formed on a surface of the Al core material, and satisfies 1.2≤H2h/H2swhere H2sis a Vickers hardness of the Al core material (Hv) and H2his a Vickers hardness of the Al coating layer (Hv).

Bonding wire for use in power-electronic module and electrical component, has filament whose melting temperature at specific pressure is higher than melting temperature of matrix at specific pressure

The bonding wire (1) has several filaments (10) and a matrix (20). The matrix is embedded into the filaments. The melting temperature of each filament at a pressure of 1013.25hPa is higher over 450[deg] C than the melting temperature of the matrix at a pressure of 1013.25hPa. The filament is made of materials consists of alloy, zinc, magnesium, aluminum, silver, gold, copper, beryllium, nickel, iron, palladium, platinum, chrome, rhodium, iridium, ruthenium, molybdenum, tantalum and tungsten. An independent claim is included for method for manufacturing an electrical component.

Elektronisches Bauteil bei dem hochfrequente Ströme unterdrückt werden und Bonddraht dafür

Verfahren zur Herstellung eines verkupferten Aluminium Drahts

Bonding wire and an integrated circuit device using the same

Method of fabricating a copper plated aluminium wire, a plated aluminium wire, an insulating plated aluminium wire, methods of fabricating thereof, and a composite lightweighted plated aluminium wire

A copper plated aluminum wire improved in the adhesion is fabricated by a method which comprises a zinc displacement step of forming a zinc thin layer by zinc displacement on the surface of an aluminum or aluminum alloy conductor, an electroplating step of coating the surface of the zinc thin layer continuously with copper layers by electroplating to have a copper coated aluminum conductor, and a thermal diffusion step of heat treating the copper coated aluminum conductor at a temperature of 120 ºC to 600 ºC under an inert gas atmosphere for thermal diffusion to ease the electrodeposition stress. Accordingly, the resultant copper plated aluminum wire can easily be shaped by cold plastic working process, decreased in the diameter at higher efficiency, and improved in the power of adhesion. A plated aluminum wire is provided comprising an anchor metal layer by displacement plating, a low thermally conductive metal layer by electroplating, and a high electrically conductive metal layer by ...

Verfahren zur Herstellung eines verkupferten Aluminium Drahts

BONDING WIRE AND INTEGRATED CIRCUIT DEVICE USING THE SAME

A bonding wire comprising a core and a coating layer formed on the core, wherein the coating layer is formed from a metal having a higher melting point than the core, and further has at least one of the following characteristics; 1. the wet contact angle with the coating layer when the core is melted is not smaller than 20 degrees; 2. when the bonding wire is hung down with its end touching a horizontal surface, and is cut at a point 15 cm above the end and thus let drop onto the horizontal surface, the curvature radius of the formed arc is 35 mm or larger; 3. the 0.2% yield strength is not smaller than 0.115 mN/µm2 but not greater than 0.165 mN/µm2; or 4. the Vickers hardness of the coating layer is 300 or lower.

Electronic component of a high frequency current suppression type and bonding wire for the same

In order to provide an electronic component of a high frequency current suppression type, which can completely suppress a high frequency current to prevent an electromagnetic interference from occurring even when it is used at a high frequency, and a bonding wire for the same, the semiconductor integrated circuit device (IC) ( 17 ) operates at a high speed in using at a high frequency band, and a predetermined number of terminals ( 19 ) are provided with a high frequency current suppressor ( 21 ) for attenuating a high frequency current passing through the terminals themselves. This high frequency current suppressor ( 21 ) is a thin film magnetic substance having a range from 0.3 to 20 (mum) in thickness, and is disposed on the entire surface of each terminal ( 19 ), covering a mounting portion to be mounted on a printed wiring circuit board ( 23 ) for mounting IC ( 17 ) and an edge including a connecting portion to a conductive pattern ( 25 ) disposed on the printed wiring circuit board ...

Bonding Wire and Integrated Circuit Device Using the Same

A bonding wire comprising a core and a coating layer formed on the core, wherein the coating layer is formed from a metal having a higher melting point than the core, and further has at least one of the following characteristics; 1. the wet contact angle with the coating layer when the core is melted is not smaller than 20 degrees; 2. when the bonding wire is hung down with its end touching a horizontal surface, and is cut at a point 15 cm above the end and thus let drop onto the horizontal surface, the curvature radius of the formed arc is 35 mm or larger; 3. the 0.2% yield strength is not smaller than 0.115 mN/mum² but not greater than 0.165 mN/mum²; or 4. the Vickers hardness of the coating layer is 300 or lower.

Light emitting device mount, and light emitting apparatus

LIGHT EMITTING APPARATUS

A light emitting apparatus includes a positive lead terminal and a negative lead terminal, each of which includes a first main surface, a second main surface, and an end surface including a first recessed surface area extending from a first point of the first main surface in cross section, and a second recessed surface area extending from a second point of the second main surface in cross section. A distance between a first part of the end surface of the positive lead terminal and a second part of the end surface of the negative lead terminal than a first distance between the first points of the positive lead terminal and the negative lead terminal and a second distance between the second points of the positive lead terminal and the negative lead terminal. The first part and the second part are separated from the first point and the second point.

Bonding wires and used for producing the bonded connection method

LEAD WIRE FOR DIODE

PURPOSE: To maintain high strength without deteriorating the magnetic attraction by a method wherein a composite cord made of a nickel alloy core with an iron coated layer is coated with copper of specific weight. CONSTITUTION: The first layer made of Ni alloy core 7 is composed of either a nickel alloy composed of part containing Ni as well as Si and Mn as a microelement and the residual part containing iron or another Ni alloy composed of a part containing eithr Mn or Si or both of them and the residual part containing Ni. In such a composition, the Ni alloy core 7 is provided with the tensile strength of 50W65kg/mm2 even after being softened. It is recommended that a mild steel (0.05W0.15C) layer 8 provided as the second layer on the Ni alloy core 7 may be provided with the core weight ratio of 1:0.5 assuming the core weight to be 1 while a copper layer 9 coating the second layer 8 as the third layer is made of oxygen free copper with weight ratio of 80W90%. COPYRIGHT: (C)1985,JPO&Japio ...

VERFAHREN ZUM VERBINDEN VON METALLEN

Bonding Wire and Integrated Circuit Device Using the Same

A bonding wire comprising a core and a coating layer formed on the core, wherein the coating layer is formed from a metal having a higher melting point than the core, and further has at least one of the following characteristics; 1. the wet contact angle with the coating layer when the core is melted is not smaller than 20 degrees; 2. when the bonding wire is hung down with its end touching a horizontal surface, and is cut at a point 15 cm above the end and thus let drop onto the horizontal surface, the curvature radius of the formed arc is 35 mm or larger; 3. the 0.2% yield strength is not smaller than 0.115 mN/μm2 but not greater than 0.165 mN/μm2; or 4. the Vickers hardness of the coating layer is 300 or lower.

BONDING WIRE AND INTEGRATED CIRCUIT DEVICE USING THE SAME

A bonding wire, characterized in that it comprises a core material comprising copper as its primary material, a different metal layer comprising a metal except copper formed on the core material, and a coating layer comprising an oxidation-resistant metal having a melting point higher than that of copper formed on the different metal layer; and an integrated circuit device using the bonding wire. The bonding wire can form a ball having a true circle shape over a wide range of the diameter of the ball, can be produced using a plating technique with no deterioration of a plating solution, and is excellent in the adhesion of the coating layer to the core material.

Method of fabricating a copper plated aluminium wire, a plated aluminium wire, an insulating plated aluminium wire, methods of fabricating thereof, and a composite lightweighted plated aluminium wire

A copper plated aluminum wire improved in the adhesion is fabricated by a method which comprises a zinc displacement step of forming a zinc thin layer by zinc displacement on the surface of an aluminum or aluminum alloy conductor, an electroplating step of coating the surface of the zinc thin layer continuously with copper layers by electroplating to have a copper coated aluminum conductor, and a thermal diffusion step of heat treating the copper coated aluminum conductor at a temperature of 120 °C to 600 °C under an inert gas atmosphere for thermal diffusion to ease the electrodeposition stress. Accordingly, the resultant copper plated aluminum wire can easily be shaped by cold plastic working process, decreased in the diameter at higher efficiency, and improved in the power of adhesion. A plated aluminum wire is provided comprising an anchor metal layer by displacement plating, a low thermally conductive metal layer by electroplating, and a high electrically conductive metal layer by ...

Magnetic plating layer-equipped copper bonding wire and manufacturing method therefor

Light emitting device mount, light emitting apparatus and leadframe

BONDING WIRE AND INTEGRATED CIRCUIT DEVICE USING THE SAME

A bonding wire which has a core material and, formed on the core material, a coating layer comprising a metal having a melting point higher than that of the core material and further has at least one of the following characteristics: 1. the wet contact angle of the molten core material with the coating material is 20 degree or more, 2. the curvature radius of a circular arc, which is formed when the bonding wire is allowed to hang down so that the tip thereof contacts with a horizontal plane and the wire is cut at the point being upper from the tip by 15 cm and the cut wire is allowed to fall on the horizontal plane, is 35 mm or more. 3. 0.2 % offset yield strength is 0.115 to 0.165 mN/μm, and 4. the coating layer has a Vickers hardness of 300 or less.2 © KIPO & WIPO 2007 ...

Bonding wire and an integrated circuit device using the same

A bonding wire comprising a core mainly consisting of copper, a different metal layer formed of a metal other than copper and formed on the core, and a coating layer formed of an oxidation-resistant metal having a melting point higher than that of copper and formed on the different metal layer, from which balls having the shape of a true sphere in a wide ball diameter range can be formed stably, which can be produced without causing the deterioration of a plating solution at the time of plating, and in which the adhesiveness between the coating layer and the core thereof is excellent; and an integrated circuit device using the bonding wire are provided.

Electronic component of a high frequency current suppression type and bonding wire for the same

In order to provide an electronic component of a high frequency current suppression type, which can completely suppress a high frequency current to prevent an electromagnetic interference from occurring even when it is used at a high frequency, and a bonding wire for the same, the semiconductor integrated circuit device (IC) (17) operates at a high speed in using at a high frequency band, and a predetermined number of terminals (19) are provided with a high frequency current suppressor (21) for attenuating a high frequency current passing through the terminals themselves. This high frequency current suppressor (21) is a thin film magnetic substance having a range from 0.3 to 20 (mum) in thickness, and is disposed on the entire surface of each terminal (19), covering a mounting portion to be mounted on a printed wiring circuit board (23) for mounting IC (17) and an edge including a connecting portion to a conductive pattern (25) disposed on the printed wiring circuit board (23). When the ...

ELECTRONIC COMPONENT OF A HIGH FREQUENCY CURRENT SUPPRESSION TYPE AND BONDING WIRE FOR THE SAME

Light emitting apparatus

A light emitting apparatus includes a positive lead terminal and a negative lead terminal, each of which includes a first main surface, a second main surface, and an end surface including a first recessed surface area extending from a first point of the first main surface in cross section, and a second recessed surface area extending from a second point of the second main surface in cross section. A distance between a first part of the end surface of the positive lead terminal and a second part of the end surface of the negative lead terminal than a first distance between the first points of the positive lead terminal and the negative lead terminal and a second distance between the second points of the positive lead terminal and the negative lead terminal. The first part and the second part are separated from the first point and the second point.

Light emitting device mount, leadframe, and light emitting apparatus

A light emitting device mount includes a positive lead terminal, and a negative lead terminal. Each of the positive and negative lead terminal includes a first main surface, a second main surface, and an end surface. The end surface is provided between the first main surface and the second main surface. The end surface includes a first recessed surface area and a second recessed surface area. The first recessed surface area is extending from a first point of the first main surface in cross section. The second recessed surface area is extending from a second point of the second main surface in cross section. The first and second recessed surface areas define a protruding portion protruding outwardly.

Bonding wire and an integrated circuit device using the same

A bonding wire comprising a core mainly consisting of copper, a different metal layer formed of a metal other than copper and formed on the core, and a coating layer formed of an oxidation-resistant metal having a melting point higher than that of copper and formed on the different metal layer, from which balls having the shape of a true sphere in a wide ball diameter range can be formed stably, which can be produced without causing the deterioration of a plating solution at the time of plating, and in which the adhesiveness between the coating layer and the core thereof is excellent; and an integrated circuit device using the bonding wire are provided.

Base body for installing light emitting element and light emitting apparatus having same

Preparation method of copper bonding wire with magnetic coating

METHOD FOR METAL WELDING

Composite lightweight copper plated aluminum wire

A copper plated aluminum wire with improvement in adhesive properties is fabricated by a method which includes a displacement step of forming a thin layer of a metal by displacement on a surface of an aluminum or aluminum alloy conductor, an electroplating step of coating a surface of the thin layer continuously with copper layers by electroplating to have a copper coated aluminum conductor, and a thermal diffusion step of heat treating the copper coated aluminum conductor at a temperature of 120° C. to 600° C. under an inert gas atmosphere for thermal diffusion. A plated aluminum wire is provided having an anchor metal layer formed by displacement plating, a low thermally conductive metal layer formed by electroplating, and a high electrically conductive metal layer formed by electroplating in which all of the layers are sequentially deposited on an outer surface of an aluminum or aluminum alloy conductor. A plated aluminum wire is provided having an anchor metal layer formed by displacement ...

Preparation method of magnetic coating copper bonding wire

Bonding wire and IC device using the bonding wire

There is a bonding wire and an IC device that uses the bonding wire. The characteristic of which is that, in the wide range of ball diameter, the true ball is steadily formed, and the wire is produced without degrading electroplating liquid while electroplate is running. Furthermore, the bonding wire is with excellent adhesion of covering layer to wire core. And it has the core made of main material of copper, different kind metal layer made of the metal other than copper and formed on the core, covering layer made of the metal with anti-oxidation and higher melting point than copper's and formed on the different kind metal layer.

High frequency current inhibiting type electronic component and its conjunction wire

BONDING WIRE AND INTEGRATED CIRCUIT DEVICE USING THE SAME

PROBLEM TO BE SOLVED: To provide a bonding wire that stably forms a spherical ball over a wide ball-diameter range, can be manufactured without degrading a plating liquid in plating, and preferably is improved in adhesion property between a covering layer and a core. SOLUTION: The core that makes copper a principal component has a layer made of a different species metal made of a metal other than copper formed on the core member, and a covering layer that is formed on the layer made of the different species metal and is made of an oxidation resistant metal having a higher melting point as compared with the copper. COPYRIGHT: (C)2004,JPO ...

LIGHT EMITTING DEVICE MOUNT, LIGHT EMITTING APPARATUS INCLUDING THE SAME, AND LEADFRAME

A mount includes a terminal, and a resin portion. The terminal includes a first surface, a second surface, and an end surface having first and second recessed areas that are extend from the first and second surfaces, respectively. The resin portion is integrally formed with the terminal, and at least partially covers the end surface so that the first and second surfaces are at least partially exposed. The resin portion forms a recessed part to accommodate the light emitting device. The second recessed area includes a closest point that is positioned closest to the first surface, and an extension part that extends outward of the closest point and toward the second surface side. The extension part is formed at least on opposing end surfaces of the pair of positive and negative lead terminal. The first recessed area is arranged on the exterior side relative to the closest point.

Bonding wire and method for producing a bond connection

The invention relates to a bonding wire (1) which comprises one or more filaments (10-17) made of a first material, the one or more filaments are or embedded in a matrix (20) made of a second material. Each of said filaments (10-17) has a first melting temperature at a pressure of 1013.25 hPa. The matrix (20) has, at a pressure of 1013.25 hPa, a second melting temperature. The first melting temperature is at least 450 DEG C higher than the second melting temperature.

Method of fabricating a copper plated aluminium wire

Light emitting device mount, leadframe, and light emitting apparatus

A light emitting device mount includes a positive lead terminal, a negative lead terminal, and a resin portion. Each of the positive and negative lead terminal includes a first main surface, a second main surface, and an end surface. The end surface is provided between the first main surface and the second main surface. The end surface includes a first recessed surface area and a second recessed surface area. The first recessed surface area is extending from a first point of the first main surface in cross section. The second recessed surface area is extending from a second point of the second main surface in cross section. The first and second recessed surface areas define a protruding portion protruding outwardly. The resin portion is positioned at least between the end surface of the positive lead terminal and the end surface of the negative lead terminal.

A magnetic coating of the copper bonding wire and its preparation method

Light emitting device mount, and light emitting apparatus

A mount includes a terminal, and a resin portion. The terminal includes a first surface, a second surface, and an end surface having first and second recessed areas that are extend from the first and second surfaces, respectively. The resin portion is integrally formed with the terminal, and at least partially covers the end surface so that the first and second surfaces are at least partially exposed. The resin portion forms a recessed part to accommodate the light emitting device. The second recessed area includes a closest point that is positioned closest to the first surface, and an extension part that extends outward of the closest point and toward the second surface side. The extension part is formed at least on an end surface facing the pair of positive and negative lead terminal. The first recessed area is arranged on the exterior side relative to the closest point.

LIGHT EMITTING DEVICE MOUNT, LEADFRAME, AND LIGHT EMITTING APPARATUS

A light emitting device mount includes a positive lead terminal, a negative lead terminal, and a resin portion. Each of the positive and negative lead terminal includes a first main surface, a second main surface, and an end surface. The end surface is provided between the first main surface and the second main surface. The end surface includes a first recessed surface area and a second recessed surface area. The first recessed surface area is extending from a first point of the first main surface in cross section. The second recessed surface area is extending from a second point of the second main surface in cross section. The first and second recessed surface areas define a protruding portion protruding outwardly. The resin portion is positioned at least between the end surface of the positive lead terminal and the end surface of the negative lead terminal.

Light emitting device mount, light emitting apparatus and leadframe

A mount includes a terminal, and a resin portion. The terminal includes a first surface, a second surface, and an end surface having first and second recessed areas that are extend from the first and second surfaces, respectively. The resin portion is integrally formed with the terminal, and at least partially covers the end surface so that the first and second surfaces are at least partially exposed. The resin portion forms a recessed part to accommodate the light emitting device. The second recessed area includes a closest point that is positioned closest to the first surface, and an extension part that extends outward of the closest point and toward the second surface side. The extension part is formed at least on an end surface facing the pair of positive and negative lead terminal. The first recessed area is arranged on the exterior side relative to the closest point.

Light emitting device mount, and light emitting apparatus

A mount includes a terminal, and a resin portion. The terminal includes a first surface, a second surface, and an end surface having first and second recessed areas that are extend from the first and second surfaces, respectively. The resin portion is integrally formed with the terminal, and at least partially covers the end surface so that the first and second surfaces are at least partially exposed. The resin portion forms a recessed part to accommodate the light emitting device. The second recessed area includes a closest point that is positioned closest to the first surface, and an extension part that extends outward of the closest point and toward the second surface side. The extension part is formed at least on an end surface facing the pair of positive and negative lead terminal. The first recessed area is arranged on the exterior side relative to the closest point.

BONDING WIRE FOR SEMICONDUCTOR DEVICES

There is provided a bonding wire for semiconductor devices that exhibits a favorable bondability even when being applied to wedge bonding at the room temperature, and also achieves an excellent bond reliability. The bonding wire includes a core material of Cu or Cu alloy (hereinafter referred to as a “Cu core material”), and a coating containing a noble metal formed on a surface of the Cu core material. A concentration of Cu at a surface of the wire is 30 to 80 at%.

Composite lightweight copper plated aluminum wire

A copper plated aluminum wire with improvement in adhesive properties is fabricated by a method which includes a displacement step of forming a thin layer of a metal by displacement on a surface of an aluminum or aluminum alloy conductor, an electroplating step of coating a surface of the thin layer continuously with copper layers by electroplating to have a copper coated aluminum conductor, and a thermal diffusion step of heat treating the copper coated aluminum conductor at a temperature of 120° C. to 600° C. under an inert gas atmosphere for thermal diffusion. A plated aluminum wire is provided having an anchor metal layer formed by displacement plating, a low thermally conductive metal layer formed by electroplating, and a high electrically conductive metal layer formed by electroplating in which all of the layers are sequentially deposited on an outer surface of an aluminum or aluminum alloy conductor. A plated aluminum wire is provided having an anchor metal layer formed by displacement ...

METHOD FOR METAL WELDING

Electronic component of a high frequency current suppression type and bonding wire for the same

In order to provide an electronic component of a high frequency current suppression type, which can completely suppress a high frequency current to prevent an electromagnetic interference from occurring even when it is used at a high frequency, and a bonding wire for the same, the semiconductor integrated circuit device (IC) (17) operates at a high speed in using at a high frequency band, and a predetermined number of terminals (19) are provided with a high frequency current suppressor (21) for attenuating a high frequency current passing through the terminals themselves. This high frequency current suppressor (21) is a thin film magnetic substance having a range from 0.3 to 20 (mum) in thickness, and is disposed on the entire surface of each terminal (19), covering a mounting portion to be mounted on a printed wiring circuit board (23) for mounting IC (17) and an edge including a connecting portion to a conductive pattern (25) disposed on the printed wiring circuit board (23). When the ...

Light emitting device mount, light emitting apparatus including the same, and leadframe

A mount includes a terminal, and a resin portion. The terminal includes a first surface, a second surface, and an end surface having first and second recessed areas that are extend from the first and second surfaces, respectively. The resin portion is integrally formed with the terminal, and at least partially covers the end surface so that the first and second surfaces are at least partially exposed. The resin portion forms a recessed part to accommodate the light emitting device. The second recessed area includes a closest point that is positioned closest to the first surface, and an extension part that extends outward of the closest point and toward the second surface side. The extension part is formed at least on an end surface facing the pair of positive and negative lead terminal. The first recessed area is arranged on the exterior side relative to the closest point.

Light emitting device mount, light emitting apparatus including the same, and leadframe

A mount includes a terminal, and a resin portion. The terminal includes a first surface, a second surface, and an end surface having first and second recessed areas that are extend from the first and second surfaces, respectively. The resin portion is integrally formed with the terminal, and at least partially covers the end surface so that the first and second surfaces are at least partially exposed. The resin portion forms a recessed part to accommodate the light emitting device. The second recessed area includes a closest point that is positioned closest to the first surface, and an extension part that extends outward of the closest point and toward the second surface side. The extension part is formed at least on opposing end surfaces of the pair of positive and negative lead terminal. The first recessed area is arranged on the exterior side relative to the closest point.

Bonding wire and an integrated circuit device using the same

The light-emitting element mounting substrate and having the light-emitting device and the lead frame

PRODUCTION OF COPPER-COATED ALUMINUM WIRE

PROBLEM TO BE SOLVED: To provide a method for producing a copper-coated aluminum wire easy to be subjected to cold plastic working, capable of efficiently reducing wire diameter and excellent in adhesion. SOLUTION: This copper-coated aluminum alloy wire excellent in adhesion is formed by a zinc-substituting stage F1 in which zinc thin film is formed by zinc-substituting on the outer curcumferential surface of an aluminum conductor or an aluminum alloy conductor, an electroplating stage F2 in which the outer circumference of the zinc thin film is continuously applied with electroplating to form into a cooper-coated aluminum conductor and a thermal diffusion treating stage F3 in which the copper-coated aluminum conductor is subjected to heat treatment at 120 to 600°C in an inert gas atmosphere to undergo thermal diffusion so as to mitigate electrodeposition stress. COPYRIGHT: (C)1999,JPO ...

Semiconductor device

A semiconductor device is configured that two or more semiconductor elements are stacked and mount on a lead frame, the aforementioned lead frame is electrically joined to the semiconductor element with a wire, and the semiconductor element, the wire and an electric junction are encapsulated with a cured product of an epoxy resin composition for encapsulating semiconductor device, and that the epoxy resin composition for encapsulating semiconductor device contains (A) an epoxy resin; (B) a curing agent; and (C) an inorganic filler, and that the (C) inorganic filler contains particles having particle diameter of equal to or smaller than two-thirds of a thinnest filled thickness at a rate of equal to or higher than 99.9% by mass.

Semiconductor device and method of packaging same

A Quad Flat Pack (QFP) device includes a semiconductor die attached to a flag of a lead frame. Bonding pads of the die are electrically connected to inner and outer rows of leads of the lead frame with bond wires. The die, die flag, bond wires and portions of the inner and outer leads are covered with a mold compound, which defines a package body. The outer leads are similar to the gull-wing leads of a conventional QFP device while the inner leads form contact points at a bottom surface of the package body. A cut is performed on an inner side of the inner leads to separate the inner leads from the die pad.

Wire loops, methods of forming wire loops, and related processes

A method of forming a wire loop is provided. The method includes the steps of: ( 1 ) forming a conductive bump on a bonding location using a wire bonding tool; ( 2 ) bonding a portion of wire to another bonding location using the wire bonding tool; ( 3 ) extending a length of wire from the bonded portion of wire toward the bonding location; ( 4 ) lowering the bonding tool toward the bonding location while detecting a height of a tip of the wire bonding tool; and ( 5 ) interrupting the lowering of the wire bonding tool during step ( 4 ) if the wire bonding tool reaches a predetermined height.

Alloy wire and methods for manufacturing the same

An alloy wire made of a material selected from one of a group consisting of a silver-gold alloy, a silver-palladium alloy and a silver-gold-palladium alloy is provided. The alloy wire is with a polycrystalline structure of a face-centered cubic lattice and includes a plurality of grains. A central part of the alloy wire includes slender grains or equi-axial grains, and the other parts of the alloy wire consist of equi-axial grains. A quantity of the grains having annealing twins was 20 percent or more of the total quantity of the grains of the alloy wire.

WIRE BONDING SYSTEMS AND RELATED METHODS

A wire bond system. Implementations may include: a bond wire including copper (Cu), a bond pad including aluminum (Al) and a sacrificial anode electrically coupled with the bond pad, where the sacrificial anode includes one or more elements having a standard electrode potential below a standard electrode potential of Al. 1. A method for forming a wire bond comprising:bonding a wire comprising Cu with a bond pad comprising an aluminum alloy; andelectrically coupling a sacrificial anode with the bond pad;wherein the sacrificial anode does not physically contact the bond pad.2. The method of claim 1 , wherein the sacrificial anode comprises one of Mg claim 1 , Hf claim 1 , Be claim 1 , or any combination thereof.3. A method of forming a wire bond comprising:physically and electrically coupling a sacrificial anode over at least a portion of a bond pad, wherein the bond pad comprises an aluminum alloy; andforming one of an alloy stack or an intermetallic layer by bonding a wire comprising Cu through the sacrificial anode and to the bond pad.4. The method of claim 3 , wherein the sacrificial anode comprises one of Mg claim 3 , Hf claim 3 , Be claim 3 , and any combination thereof.5. The method of claim 3 , wherein the sacrificial anode comprises W.6. The method of claim 3 , wherein the sacrificial anode comprises Zn.7. The method of claim 3 , wherein the sacrificial anode comprises Cr.8. The method of claim 3 , wherein the sacrificial anode comprises Sn.9. The method of claim 3 , wherein the sacrificial anode comprises one of Mo claim 3 , Cd claim 3 , Ni claim 3 , Co claim 3 , Fe claim 3 , Cu claim 3 , or any combination thereof.10. The method of claim 3 , wherein the sacrificial anode is entirely over the bond pad.11. A wire bond system comprising:a bond wire comprising Cu; anda bond pad coupled to the bond wire, the bond pad comprising a sacrificial anode.12. The system of claim 11 , wherein the sacrificial anode comprises W.13. The system of claim 11 , wherein the ...

Cu ALLOY CORE BONDING WIRE WITH Pd COATING FOR SEMICONDUCTOR DEVICE

A bonding wire for a semiconductor device includes a Cu alloy core material and a Pd coating layer formed on a surface thereof, and the boding wire contains one or more elements of As, Te, Sn, Sb, Bi and Se in a total amount of 0.1 to 100 ppm by mass. The bonding longevity of a ball bonded part can increase in a high-temperature and high-humidity environment, improving the bonding reliability. When the Cu alloy core material further contains one or more of Ni, Zn, Rh, In, Ir, Pt, Ga and Ge in an amount, for each, of 0.011 to 1.2% by mass, it is able to increase the reliability of a ball bonded part in a high-temperature environment of 170° C. or more. When an alloy skin layer containing Au and Pd is further formed on a surface of the Pd coating layer, wedge bondability improves.

CHIP PACKAGE AND METHOD OF FORMING A CHIP PACKAGE WITH A METAL CONTACT STRUCTURE AND PROTECTIVE LAYER, AND METHOD OF FORMING AN ELECTRICAL CONTACT

In various embodiments, a chip package is provided. The chip package may include a chip, a metal contact structure including a non-noble metal and electrically contacting the chip, a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure. 1. A method of forming an electrical contact , comprising:arranging an intermediate layer on the metal surface;arranging a metal contact structure over or on a metal surface; andplating a metal layer on the metal surface and on the metal contact structure, thereby fixing the metal contact structure to the metal surface and forming an electrical contact between the metal contact structure and the metal surface or strengthening or thickening an existing electrical contact between the metal contact structure and the metal surface.2. The method of claim 1 , further comprising:before plating the metal layer on the metal surface and on the metal contact structure, treating the metal surface and the metal contact structure by a process involving wet chemistry, dry chemistry, and/or a plasma in order to prepare a surface of the metal surface and of the metal contact structure for the plating.3. The method of claim 1 , wherein the metal contact structure claim 1 , the metal surface and/or a metallization material comprises or consists of copper.4. The method of claim 1 , wherein the metal contact structure may contain or consist of the same metal as the metal surface.5. The method of claim 3 , wherein the metallization comprises a galvanic deposit or an electroless deposit.6. The method of ...

PROCESS FOR ELECTRICALLY CONNECTING CONTACT SURFACES OF ELECTRONIC COMPONENTS

A process for electrically connecting contact surfaces of electronic components by capillary wedge bonding a round wire of 8 to 80 μm to the contact surface of a first electronic component, forming a wire loop, and stitch bonding the wire to the contact surface of a second electronic component, wherein the wire comprises a wire core having a silver or silver-based wire core with a double-layered coating comprised of a 1 to 50 nm thick inner layer of nickel or palladium and an adjacent 5 to 200 nm thick outer layer of gold. 1. A process for electrically connecting a contact surface of a first electronic component with a contact surface of a second electronic component comprising the subsequent steps:(1) capillary wedge bonding a wire having a circular cross-section with an average diameter in the range of 8 to 80 μm to the contact surface of the first electronic component,(2) raising the capillary wedge bonded wire to form a wire loop between the capillary wedge bond formed in step (1) and the contact surface of the second electronic component, and(3) stitch bonding the wire to the contact surface of the second electronic component,wherein the capillary wedge bonding of step (1) is carried out with a ceramic capillary having a lower face angle within the range of from zero to 4 degrees,wherein the wire comprises a wire core with a surface, the wire core having a double-layered coating superimposed on its surface,wherein the wire core consists of a material selected from the group consisting of pure silver, doped silver with a silver content of >99.5 wt.-% and silver alloys with a silver content of at least 89 wt.-%, andwherein the double-layered coating comprises a 1 to 50 nm thick inner layer of nickel or palladium and an adjacent 5 to 200 nm thick outer layer of gold.2. The process of claim 1 , (a′) an ultrasonic energy in a range of 50 to 100 mA,', '(b′) a force in a range of 10 to 30 g,', '(c′) a constant velocity in a range of 0.3 to 0.7 μm/s,', '(d′) a contact ...

Method for manufacturing bonding wire and manufacturing apparatus thereof

A method for manufacturing a bonding wire includes: putting a surface layer metal of a bonding wire in a crucible having a die cooler provided at the lower part thereof and melting the same; putting a main component metal core of the bonding wire in a core guide located at the upper part of the die cooler of the crucible and heating the core guide to the melting point or below of the metal core; transferring the metal core toward the die cooler so as to allow the molten surface layer metal to be injected to the surface of the metal core; and manufacturing a 50 □m to 350 □m bonding wire from the cast wire precursor by using a drawing die.

System and method for cleaning bond wire

A system for cleaning bond wire for use by a wire bonding machine includes a bond wire supply station, a bond wire cleaning bath station, a bond wire neutralizing station, a bond wire drying station, and a wire bonding machine. In operation, the bonding machine is supplied with bond wire stored at the supply station, which is firstly de-oxidized with a cleaning solution in the cleaning bath station. Next, the cleaning solution on the bond wire is neutralized with a neutralizing liquid in the neutralizing station. The bond wire is then dried in the drying station. The speed of the bond wire passing through the cleaning bath station, neutralizing station and drying station is controlled by the wire bonding machine.

BONDING WIRE FOR SEMICONDUCTOR DEVICE

There is provided a bonding wire that improves bonding reliability of a ball bonded part and ball formability and is suitable for on-vehicle devices. 1. A bonding wire for a semiconductor device comprising:a Cu alloy core material; anda Pd coating layer formed on a surface of the Cu alloy core material, whereinthe Cu alloy core material contains Ni,a concentration of Ni is 0.1 to 1.2 wt. % relative to the entire wire, anda thickness of the Pd coating layer is 0.015 to 0.150 □m.2. The bonding wire for a semiconductor device according to claim 1 , further comprising an Au skin layer on the Pd coating layer.3. The bonding wire for a semiconductor device according to claim 2 , wherein a thickness of the Au skin layer is 0.0005 to 0.050 □m.4. The bonding wire for a semiconductor device according to claim 1 , whereinthe Cu alloy core material further contains at least one element selected from B, In, Ca, P and Ti, anda concentration of the elements is 3 to 100 wt. ppm relative to the entire wire.5. The bonding wire for a semiconductor device according to claim 1 , whereinthe Cu alloy core material further contains Pt or Pd, anda concentration of Pt or Pd contained in the Cu alloy core material is 0.05 to 1.20 wt. %.6. The bonding wire for a semiconductor device according to claim 1 , wherein Cu is present at an outermost surface of the bonding wire. The present invention relates to a bonding wire for a semiconductor device used to connect electrodes on a semiconductor device and wiring of a circuit wiring board such as external leads.As a bonding wire for a semiconductor device which connects electrodes on a semiconductor device and external leads (hereinafter referred to as a “bonding wire”), a thin wire with a wire diameter of about 15 to 50 μm is mainly used today. For a bonding method with bonding wire, there is generally used a thermal compressive bonding technique with the aid of ultrasound, in which a general bonding device, a capillary tool used for bonding by ...

NOBLE METAL-COATED SILVER WIRE FOR BALL BONDING AND METHOD FOR PRODUCING THE SAME, AND SEMICONDUCTOR DEVICE USING NOBLE METAL-COATED SILVER WIRE FOR BALL BONDING AND METHOD FOR PRODUCING THE SAME

A noble metal-coated silver bonding wire suppresses corrosion at the bonding interface under severe conditions of high temperature and high humidity, and the noble metal-coated silver bonding wire can be ball-bonded in the air. The noble metal-coated silver wire for ball bonding is a noble metal-coated silver wire including a noble metal coating layer on a core material made of pure silver or a silver alloy, wherein the wire contains at least one sulfur group element, the noble metal coating layer includes a palladium intermediate layer and a gold skin layer, the palladium content relative to the entire wire is 0.01 mass % or more and 5.0 mass % or less, the gold content relative to the entire wire is 1.0 mass % or more and 6.0 mass % or less, and the sulfur group element content relative to the entire wire is 0.1 mass ppm or more and 100 mass ppm or less. 1. A noble metal-coated silver wire for ball bonding comprising a noble metal coating layer on a core material made of pure silver or a silver alloy ,wherein the wire contains at least one sulfur group element,the noble metal coating layer comprises a palladium intermediate layer and a gold skin layer,a palladium content relative to an entire wire is 0.01 mass % or more and 5.0 mass % or less,a gold content relative to the entire wire is 1.0 mass % or more and 6.0 mass % or less, anda content of the sulfur group element relative to the entire wire is 0.1 mass ppm or more and 100 mass ppm or less.2. The noble metal-coated silver wire for ball bonding according to claim 1 , wherein the noble metal coating layer further comprises a gold intermediate layer on a core material surface of the palladium intermediate layer.3. The noble metal-coated silver wire for ball bonding according to claim 1 , wherein the core material further contains copper claim 1 , and a copper content relative to the entire wire is 0.005 mass % or more and 2.0 mass % or less.46-. (canceled)7. A semiconductor device comprising at least one ...

Package-On-Package (PoP) Structure Including Stud Bulbs

Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs. 1. A device comprising:a first pad on a first surface of a first substrate;a second pad on a second surface of a second substrate;a metallic element interposed between the first pad and the second pad, the metallic element electrically coupled to the first pad, the metallic element comprising a base portion and an elongated portion extending from the base portion toward the second pad;a solder connector in contact with the elongated portion and electrically coupled to the second pad; andan inter-metallic compound (IMC) between the elongated portion and the solder connector.2. The device of claim 1 , further comprising a protection layer extending over the base portion and the elongated portion.3. The device of claim 1 , further comprising a die attached to the first substrate adjacent the metallic element.4. The device of claim 3 , wherein a height of the metallic element from the first substrate is greater than a height of the die from the first substrate.5. The device of claim 1 , wherein the metallic element comprises a copper wire.6. The device of claim 1 , wherein the base portion and the elongated portion comprises a single continuous element.7. A device comprising:a first substrate having a first pad;a second substrate having a second pad;a first connector interposed between the first pad and the second pad, the first connector having a first wide portion and a second elongated portion, the first wide portion being ...

Palladium (pd)-coated copper wire for ball bonding

A palladium coated copper wire for ball bonding includes a core formed of pure copper or copper alloy having a purity of 98% by mass or more, and a palladium draw coated layer coated on the core. The copper wire has a diameter of 10 to 25 μm, and the palladium drawn layer contains sulfur, phosphorus, boron or carbon.

METALLIC RIBBON FOR POWER MODULE PACKAGING

A metallic ribbon for power module packaging is described. The metallic ribbon has a rectangular, oval or oblong cross section. The composition of the metallic ribbon is silver-palladium alloy containing 0.2 to 6 wt % Pd. The metallic ribbon has a thickness of 10 μm to 500 μm. The width of the metallic ribbon is 2 to 100 times its thickness. The metallic ribbon includes a plurality of grains. The average grain size of the grains observed in the transverse cross section is 2 μm to 10 μm. The metallic ribbon has a plurality of twin grains observed in the transverse cross section, and the number of twin grains observed in the transverse cross section accounts for at least 5% of the total number of grains observed in the transverse cross section. 1. A metallic ribbon for power module packaging , wherein:the metallic ribbon has a rectangular, oval or oblong cross section;a composition of the metallic ribbon is a silver-palladium alloy comprising 0.2 to 6 wt % palladium;the metallic ribbon has a thickness of 10 μm to 500 μm;a width of the metallic ribbon is 2 to 100 times the thickness;the metallic ribbon comprises a plurality of grains, an average grain size of grains observed in a transverse cross section of the metallic ribbon is 2 μm to 10 μm; andthe metallic ribbon has a plurality of twin grains observed in the transverse cross section of the metallic ribbon, and a number of the twin grains observed in the transverse cross section accounts for at least 5% of a total number of the grains observed in the transverse cross section.2. The metallic ribbon for power module packaging of claim 1 , wherein a hardness of the metallic ribbon is 40 Hv to 70 Hv.3. The metallic ribbon for power module packaging of claim 1 , wherein the width of the metallic ribbon is not greater than 5 mm.4. The metallic ribbon for power module packaging of claim 1 , wherein a surface of the metallic ribbon is covered by one or more metal layers claim 1 , wherein a composition of the one or more ...

Chip package, method of forming a chip package and method of forming an electrical contact

In various embodiments, a method of forming an electrical contact is provided. The method may include depositing, by atomic layer deposition, a passivation layer over at least a region of a metal surface, wherein the passivation layer may include aluminum oxide, and electrically contacting the region of the metal surface with a metal contact structure, wherein the metal contact structure may include copper.

SEMICONDUCTOR DEVICE

An inventive semiconductor device includes: a semiconductor chip including an integrated circuit; a plurality of electrode pads provided on the semiconductor chip and connected to the integrated circuit; a rewiring to which the electrode pads are electrically connected together, the rewiring being exposed on an outermost surface of the semiconductor chip and having an exposed surface area greater than the total area of the electrode pads; and a resin package which seals the semiconductor chip. 1. A semiconductor device comprising:a semiconductor chip including an integrated circuit;a plurality of electrode pads provided on the semiconductor chip and connected to the integrated circuit;a rewiring to which the electrode pads are electrically connected together, the rewiring being exposed on an outermost surface of the semiconductor chip and having an exposed surface area greater than a total area of the electrode pads; anda resin package which seals the semiconductor chip.2. The semiconductor device according to claim 1 , wherein the rewiring covers the plurality of electrode pads.3. The semiconductor device according to claim 1 , wherein the rewiring includes a plurality of rewirings provided on the semiconductor chip and spaced from each other along the surface of the semiconductor chip.4. The semiconductor device according to claim 1 , further comprising:a lead selectively sealed in the resin package; anda connection member sealed in the resin package for electrical connection between the rewiring and the lead.5. The semiconductor device according to claim 4 , wherein the connection member includes an electrically conductive plate.6. The semiconductor device according to claim 4 , wherein the semiconductor chip is connected to the connection member in an attitude such that a surface of the semiconductor chip formed with the rewiring faces up.7. The semiconductor device according to claim 6 , wherein the rewiring is connected to the connection member via solder.8. ...

Semiconductor die package and method for making the same

Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.

FLOATING DIE PACKAGE

A floating die package including a cavity formed through sublimation of a sacrificial die encapsulant and sublimation or separation of die attach materials after molding assembly. A pinhole vent in the molding structure is provided as a sublimation path to allow gases to escape, whereby the die or die stack is released from the substrate and suspended in the cavity by the bond wires only. 1. A semiconductor package comprising:a lead frame including a die paddle and a first plurality of conductors and a second plurality of conductors;a first semiconductor die electrically connected to the first plurality of conductors through a first set of bond wires;a second semiconductor die electrically connected to the second plurality of conductors through a second set of bond wires, the second semiconductor die attached to the first semiconductor die;a molding structure covering portions of the lead frame, the first semiconductor die, the second semiconductor die, the first set of bond wires, and the second set of bond wires; anda cavity within the molding structure and covering portions of top surfaces of the first semiconductor die and attached to the second semiconductor die, wherein a portion of the cavity is in between the first semiconductor die and the die paddle, wherein one surface of each of the first plurality of conductors and two surfaces of each of the second plurality of conductors are exposed from the semiconductor package, and wherein the first semiconductor die is suspended by the first set of bond wires to float inside the cavity.2. The semiconductor package of claim 1 , wherein the second set of bond wires is below the first set of bond wires in a cross-sectional view of the semiconductor package.3. The semiconductor package of further comprising a film layer in contact with portions of the molding structure and covering a portion of the cavity.4. The semiconductor package of claim 3 , wherein the film layer includes a screen-printed film.5. The ...

Wedge tool and wedge bonding method

A bonding tool includes a wedge tool that presses a bonding wire against a principal plane of a structure such as an electrode to which the bonding wire is to be bonded. A groove formed in an end portion of a wedge tool body of the wedge tool is inclined along a longitudinal direction of the bonding wire so that a heel side of the groove is closer to the principal plane of the structure than a toe side of the groove. As a result, the wedge tool is inclined at a tilt angle and the bonding wire fits the groove in the end portion of the wedge tool body along the longitudinal direction of the bonding wire. Thus, a corner portion of the wedge tool does not contact the electrode.

METHOD FOR FORMING BALL IN BONDING WIRE

The present invention provides a ball forming method for forming a ball portion at a tip of a bonding wire which includes a core material mainly composed of Cu, and a coating layer mainly composed of Pd and formed over a surface of the core material, wherein the ball portion is formed in non-oxidizing atmosphere gas including hydrocarbon which is gas at room temperature and atmospheric pressure, the method being capable of improving Pd coverage on a ball surface in forming a ball at a tip of the Pd-coated Cu bonding wire. 1. A ball forming method for forming a ball portion at a tip of a bonding wire which includes a core material mainly composed of Cu , and a coating layer mainly composed of Pd and formed over a surface of the core material , wherein the ball portion is formed in non-oxidizing atmosphere gas including hydrocarbon which is gas at room temperature and atmospheric pressure.2. The ball forming method according to claim 1 , wherein a carbon number of the hydrocarbon is 1 to 4.3. The ball forming method according to claim 1 , wherein the hydrocarbon includes one or more of methane claim 1 , ethane claim 1 , propane claim 1 , and butane.4. The ball forming method according to claim 1 , wherein a concentration of the hydrocarbon in the non-oxidizing atmosphere gas is 0.08 to 12.50 vol %.5. The ball forming method according to claim 4 , wherein a concentration of methane in the non-oxidizing atmosphere gas is 0.25 to 12.50 vol %.6. The ball forming method according to claim 4 , wherein a concentration of ethane in the non-oxidizing atmosphere gas is 0.14 to 7.00 vol %.7. The ball forming method according to claim 4 , wherein a concentration of propane in the non-oxidizing atmosphere gas is 0.10 to 5.00 vol %.8. The ball forming method according to claim 4 , wherein a concentration of butane in the non-oxidizing atmosphere gas is 0.08 to 4.00 vol %.9. The ball forming method according to claim 1 , wherein the non-oxidizing atmosphere gas includes hydrogen.10. ...

SUBSTRATE-LESS STACKABLE PACKAGE WITH WIRE-BOND INTERCONNECT

A method for making a microelectronic unit includes forming a plurality of wire bonds on a first surface in the form of a conductive bonding surface of a structure comprising a patternable metallic element. The wire bonds are formed having bases joined to the first surface and end surfaces remote from the first surface. The wire bonds have edge surfaces extending between the bases and the end surfaces. The method also includes forming a dielectric encapsulation layer over a portion of the first surface of the conductive layer and over portions of the wire bonds such that unencapsulated portions of the wire bonds are defined by end surfaces or portions of the edge surfaces that are unconvered by the encapsulation layer. The metallic element is patterned to form first conductive elements beneath the wire bonds and insulated from one another by portions of the encapsulation layer. 1. A microelectronic package , comprising:first conductive elements, including a first trace, obtained from a same conductive layer located on a lower side of the microelectronic package;wire bond wires connected to and extending away from upper surfaces of the first conductive elements;a first microelectronic component coupled with a first attachment layer to the first trace;a first conductive via in the first attachment layer and interconnecting the first trace and a first contact structure of the first microelectronic component;a second microelectronic component coupled to the first microelectronic component with a second attachment layer;second conductive elements, including a second trace, respectively connected to upper surfaces of the wire bond wires; anda second conductive via in a dielectric layer and interconnecting the second trace and a second contact structure of the second microelectronic component.2. The microelectronic package according to claim 1 , wherein the first trace is for a first redistribution.3. The a microelectronic package according to claim 2 , wherein the second ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

To improve the reliability of a semiconductor device. 110-. (canceled)11. A method of manufacturing a semiconductor device , the method comprising:(a) preparing a semiconductor substrate which includes a plurality of wiring layers and a pad formed on an uppermost wiring layer of the plurality of wiring layers;(b) forming a surface protection film which includes an opening on the pad and is made of an inorganic insulating film;(c) forming a rewiring, which is electrically connected to the pad via the opening, on the surface protection film;(d) forming a pad electrode on the rewiring; and(e) forming a ball at a tip end of a wire, and connecting the ball to the pad electrode while applying ultrasonic vibration to the ball in a first direction,wherein the rewiring includes a pad electrode mounting portion on which the pad electrode is mounted, a connection portion which is connected to the pad, and an extended wiring portion that couples the pad electrode mounting portion and the connection portion, andthe pad electrode mounting portion has a rectangular shape with long sides and short sides.12. The method of manufacturing the semiconductor device according to claim 11 ,wherein the first direction is a direction along the long side.13. The method of manufacturing the semiconductor device according to claim 12 ,wherein the pad electrode covers a front surface of the pad electrode mounting portion, and extends to a side wall of the pad electrode mounting portion.14. The method of manufacturing the semiconductor device according to claim 11 ,wherein the first direction is a direction along the short side.15. The method of manufacturing the semiconductor device according to claim 11 ,wherein the pad electrode mounting portion includes a fin portion which extends from the long side or the short side to an outer side of the pad electrode mounting portion. The present application claims priority from Japanese Patent Application No. 2015-029409 filed on Feb. 18, 2015, the ...

ELECTRONIC DEVICE HAVING COATED CONTACT PADS

A system and method for bonding an electrically conductive mechanical interconnector (e.g., a bonding wire, solder, etc.) to an electrical contact (e.g., contact pad, termination on a printed circuit board (PCB), etc.) made from an electrically conductive metal (e.g., aluminum) on an electronic device (e.g., integrated circuit (IC), die, wafer, PCB, etc.) is provided. The electrical contact is chemically coated with a metal (e.g., cobalt) that provides a protective barrier between the mechanical interconnector and the electrical contact. The protective barrier provides a diffusion barrier to inhibit galvanic corrosion (i.e. ion diffusion) between the mechanical interconnector and the electrical contact. 1. A method , comprising:providing an array of electrical devices, each of the electrical devices having an aluminum pad;immersing the array of electrical devices into a cobalt ion solution to chemically displace an aluminum oxide layer from each aluminum pad, wherein the aluminum oxide layer is oxidized to form an aluminum ion and free electrons, wherein the cobalt ion liquid solution combines with the free electrons to form a cobalt metal, and wherein a layer of the cobalt metal is deposited on each aluminum pad in place of the aluminum oxide layer; andbonding an electrically conductive mechanical interconnector to the layer of cobalt metal.2. The method of claim 1 , wherein bonding the electrically conductive mechanical interconnector includes bonding a copper bonding wire to the layer of cobalt metal.3. The method of claim 1 , wherein bonding the electrically conductive mechanical interconnector includes disposing a solder ball comprised at least one of copper claim 1 , tin claim 1 , and silver on the layer of cobalt metal.4. The method of claim 1 , wherein prior to immersing the electrical device into the cobalt ion solution claim 1 , the method comprising mixing cobalt citrate claim 1 , polyethylenimine claim 1 , and aluminum fluoride to form the cobalt ion ...

BONDING WIRE FOR SEMICONDUCTOR DEVICE

A bonding wire for a semiconductor device includes a Cu alloy core material and a Pd coating layer formed on a surface thereof, and the boding wire contains one or more elements of As, Te, Sn, Sb, Bi and Se in a total amount of 0.1 to 100 ppm by mass. The bonding longevity of a ball bonded part can increase in a high-temperature and high-humidity environment, improving the bonding reliability. When the Cu alloy core material further contains one or more of Ni, Zn, Rh, In, Ir, Pt, Ga and Ge in an amount, for each, of 0.011 to 1.2% by mass, it is able to increase the reliability of a ball bonded part in a high-temperature environment of 170° C. or more. When an alloy skin layer containing Au and Pd is further formed on a surface of the Pd coating layer, wedge bondability improves. 1. A bonding wire for a semiconductor device comprising:a Cu alloy core material; anda Pd coating layer formed on a surface of the Cu alloy core material, whereinthe bonding wire contains at least one or more elements selected from As and Te, anda concentration of the elements in total is 0.1 ppm by mass or more and 100 ppm by mass or less relative to the entire wire.2. The bonding wire for a semiconductor device according to claim 1 , wherein the concentration of the at least one or more elements selected from As and Te in total is 1 ppm by mass or more and 100 ppm by mass or less relative to the entire wire.3. The bonding wire for a semiconductor device according to claim 1 , wherein a thickness of the Pd coating layer is 0.015 μm or more and 0.150 μm or less.4. The bonding wire for a semiconductor device according to claim 1 , further comprising an alloy skin layer containing Au and Pd on the Pd coating layer.5. The bonding wire for a semiconductor device according to claim 4 , wherein a thickness of the alloy skin layer containing Au and Pd is 0.0005 μm or more and 0.050 μm or less.6. The bonding wire for a semiconductor device according to claim 1 , whereinthe bonding wire further ...

COATED BONDING WIRE AND METHODS FOR BONDING USING SAME

A semiconductor device includes a bond formed on a bond pad. The bond is formed of a wire that includes a central core of conductive metal, a first coating over the central core of conductive metal that is more chemically active than the conductive metal, and a second coating over the central core of conductive metal that is less chemically active than the central core of conductive metal. 18-. (canceled)9. A semiconductor device comprising:a packaging mold compound;a wire bond embedded in the packaging mold compound, whereina wire of the wire bond includes a central core of electrically conductive material, a sacrificial coating over the central core of electrically conductive material, and a second coating over the central core of conductive material, andthe central core of electrically conductive material includes at least one of a group consisting of copper and silver, and the sacrificial coating is formed of a material that has a lower reduction potential than the central core of electrically conductive material and the second coating, and the second coating has a higher reduction potential than the central core of electrically conductive material.10. The device of claim 9 , wherein an interface between the central core and a bond pad is devoid of the sacrificial coating claim 9 , and the second coating is between the bond pad and the central core of electrically conductive material.11. The device of claim 9 , wherein a thickness of the sacrificial coating is between 0.05 and 0.20 micrometers.12. The device of claim 9 , wherein the bond is one of a group consisting of a ball bond claim 9 , a wedge bond claim 9 , and a stitch bond.13. The device of claim 9 , wherein the sacrificial coating includes one of group consisting of zinc claim 9 , aluminum claim 9 , and magnesium.14. The device of claim 9 , wherein the second coating includes palladium.15. The device of claim 10 , wherein the sacrificial coating is in direct contact with the central core of electrically ...

Bonding wire for semiconductor device

A bonding wire for a semiconductor device includes a Cu alloy core material and a Pd coating layer on a surface of the Cu alloy core material, and contains Ga and Ge of 0.011 to 1.2% by mass in total, which is able to increase bonding longevity of the ball bonded part in the high-temperature, high-humidity environment, and thus to improve the bonding reliability. The thickness of the Pd coating layer is preferably 0.015 to 0.150 μm. When the bonding wire further contains one or more elements of Ni, Ir, and Pt in an amount, for each element, of 0.011 to 1.2% by mass, it is able to improve the reliability of the ball bonded part in a high-temperature environment at 175° C. or more. When an alloy skin layer containing Au and Pd is further formed on a surface of the Pd coating layer, wedge bondability improves.

Package-On-Package (PoP) Structure Including Stud Bulbs

Embodiments concern Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures. According to an embodiment, a structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs. 1. A device comprising:a first pad on a first surface of a first package;a second pad on a second surface of a second package;a metallic element interposed between the first pad and the second pad, the metallic element comprising a base portion and an elongated portion, the base portion being coupled to the first pad, the elongated portion extending from the base portion toward the second pad, wherein a width of the base portion is greater than a width of the elongated portion;a solder connector in contact with the elongated portion and electrically coupled to the second pad; andan inter-metallic compound (IMC) between the elongated portion and the solder connector.2. The device of claim 1 , wherein the first package comprises a first substrate and a first integrated circuit die attached to the first substrate claim 1 , wherein the second package comprises a second substrate and a second integrated circuit die attached to the second substrate.3. The device of claim 2 , wherein the metallic element is laterally adjacent the first integrated circuit die with the first integrated circuit die and the metallic element being interposed between the first substrate and the second substrate.4. The device of claim 3 , wherein the metallic element extends closer to the second substrate than the first integrated circuit die.5. The device of claim 1 , wherein a height of the metallic element is between about 20 micrometers and about 200 ...

Aluminum coated copper ribbon

A ribbon, preferably a bonding ribbon for bonding in microelectronics, contains a first layer containing copper, a coating layer containing aluminum superimposed over the first layer, and an intermediate layer. In a cross-sectional view of the ribbon, the area share of the first layer is from 50 to 96% and the aspect ratio between the width and the height of the ribbon in a cross-sectional view is from 0.03 to less than 0.8. The ribbon has a cross-sectional area of 25,000 μm 2 to 800,000 μm 2 . The intermediate layer contains at least one intermetallic phase containing materials of the first and coating layers. The invention further relates to a process for making a wire, to a wire obtained by the process, to an electric device containing the wire, to a propelled device comprising said electric device and to a process of connecting two elements through the wire by wedge-bonding.

BONDING WIRE FOR SEMICONDUCTOR DEVICE

A bonding wire for a semiconductor device includes a Cu alloy core material and a Pd coating layer formed on a surface thereof. Containing an element that provides bonding reliability in a high-temperature environment improves the bonding reliability of the ball bonded part in high temperature. Furthermore, making an orientation proportion of a crystal orientation <100> angled at 15 degrees or less to a wire longitudinal direction among crystal orientations in the wire longitudinal direction 30% or more when measuring crystal orientations on a cross-section of the core material in a direction perpendicular to a wire axis of the bonding wire, and making an average crystal grain size in the cross-section of the core material in the direction perpendicular to the wire axis of the bonding wire 0.9 to 1.5 μm provides a strength ratio of 1.6 or less. 1. A bonding wire for a semiconductor device , the bonding wire comprising:a Cu alloy core material; anda Pd coating layer formed on a surface of the Cu alloy core material, whereinwhen measuring crystal orientations on a cross-section of the core material in a direction perpendicular to a wire axis of the bonding wire, a crystal orientation <100> angled at 15 degrees or less to a wire longitudinal direction has a proportion of 30% or more among crystal orientations in the wire longitudinal direction,an average crystal grain size in the cross-section of the core material in the direction perpendicular to the wire axis of the bonding wire is 0.9 μm or more and 1.5 μm or less, andthe bonding wire contains one or more elements selected from Co, Rh, Ir, Ni, Pd, Pt, Ag, Au, Zn, Al, In, Sn, P, As, Sb, Bi, Se and Te.2. The bonding wire for a semiconductor device according to claim 1 , wherein a strength ratio defined by the following Equation (1) is 1.1 or more and 1.6 or less:{'br': None, 'Strength ratio=ultimate strength/0.2% offset yield strength.\u2003\u2003(1)'}3. The bonding wire for a semiconductor device according to claim 1 ...

Image Sensor Device

An image sensor device, as well as methods therefor, is disclosed. This image sensor device includes a substrate having bond pads. The substrate has a through substrate channel defined therein extending between a front side surface and a back side surface thereof. The front side surface is associated with an optically-activatable surface. The bond pads are located at or proximal to the front side surface aligned for access via the through substrate channel. Wire bond wires are bonded to the bond pads at first ends thereof extending away from the bond pads with second ends of the wire bond wires located outside of an opening of the channel at the back side surface. A molding layer is disposed along the back side surface and in the through substrate channel. A redistribution layer is in contact with the molding layer and interconnected to the second ends of the wire bond wires.

Method for manufacturing a semiconductor device

After a die bonding step, a wire bonding step is performed to electrically connect the plurality of pad electrodes and the plurality of leads of the semiconductor chip via a plurality of copper wires. A plating layer is formed on a surface of the lead, and a copper wire is connected to the plating layer in the wire bonding step. The plating layer is a silver plating layer. After the die bonding step, an oxygen plasma treatment is performed on the lead frame and the semiconductor chip before the wire bonding step, and then the surface of the plating layer is reduced.

PACKAGED SEMICONDUCTOR ASSEMBLIES AND METHODS FOR MANUFACTURING SUCH ASSEMBLIES

Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of a packaged semiconductor assembly includes a support member having a first bond-site and a die carried by the support member having a second bond-site. An interconnect structure is connected between the first and second bond-sites and includes a wire that is coupled to at least one of the first and second bond-sites. The interconnect structure also includes a third bond-site coupled to the wire between the first and second bond-sites. 1. A method of forming a semiconductor assembly , comprising:forming a conductive pedestal at a first bond-site of a support member, wherein the pedestal has a surface spaced apart from the support member;attaching the support member to a die having a second bond-site;disposing an encapsulant adjacent to the pedestal;removing at least a portion of the encapsulant to at least partially expose the surface of the pedestal; andforming a redistribution structure connected to the surface of the pedestal and the first bond-site and having a third bond-site between the first and second bond-sites and spaced apart from the die.2. The method of wherein removing at least a portion of the encapsulant comprises forming a via through the encapsulant that terminates at the surface of the pedestal.3. The method of claim 2 , further comprising disposing a conductive member in the via and coupling the conductive member to the surface of the pedestal with the conductive member exposed for an electrical connection external to the assembly.4. A method of forming a stacked semiconductor assembly claim 2 , comprising:singulating a first semiconductor assembly having a first die and a first bond-site at a periphery of the first assembly, the first assembly having a first footprint;singulating a second semiconductor assembly along a singulation line, the second semiconductor assembly having a second ...

Cu ALLOY CORE BONDING WIRE WITH Pd COATING FOR SEMICONDUCTOR DEVICE

A bonding wire for a semiconductor device includes a Cu alloy core material and a Pd coating layer formed on a surface thereof, and the boding wire contains one or more elements of As, Te, Sn, Sb, Bi and Se in a total amount of 0.1 to 100 ppm by mass. The bonding longevity of a ball bonded part can increase in a high-temperature and high-humidity environment, improving the bonding reliability. When the Cu alloy core material further contains one or more of Ni, Zn, Rh, In, Ir, Pt, Ga and Ge in an amount, for each, of 0.011 to 1.2% by mass, it is able to increase the reliability of a ball bonded part in a high-temperature environment of 170° C. or more. When an alloy skin layer containing Au and Pd is further formed on a surface of the Pd coating layer, wedge bondability improves. 1. A bonding wire for a semiconductor device comprising:a Cu alloy core material; anda Pd coating layer formed on a surface of the Cu alloy core material, whereinthe bonding wire contains at least one or more first elements selected from Sb, Bi and Se,a concentration of the first elements in total is 0.1 ppm by mass or more and 100 ppm by mass or less relative to the entire wire, andSb≤10 ppm by mass; and Bi≤1 ppm by mass, andthe bonding wire contains at least one or more second elements selected from Ni, Zn, Rh, In, Ir, Pt, Ga and Ge, anda concentration of each of the second elements is 0.011% by mass or more and 1.2% by mass or less relative to the entire wire.2. The bonding wire for a semiconductor device according to claim 1 , wherein the concentration of the at least one or more first elements selected from Sb claim 1 , Bi and Se in total is 1 ppm by mass or more and 100 ppm by mass or less relative to the entire wire.3. The bonding wire for a semiconductor device according to claim 1 , wherein a thickness of the Pd coating layer is 0.015 μm or more and 0.150 μm or less.4. The bonding wire for a semiconductor device according to claim 1 , further comprising an alloy skin layer ...

Light emitting device mount, light emitting apparatus including the same, and leadframe

A mount includes a terminal, and a resin portion. The terminal includes a first surface, a second surface, and an end surface having first and second recessed areas that are extend from the first and second surfaces, respectively. The resin portion is integrally formed with the terminal, and at least partially covers the end surface so that the first and second surfaces are at least partially exposed. The resin portion forms a recessed part to accommodate the light emitting device. The second recessed area includes a closest point that is positioned closest to the first surface, and an extension part that extends outward of the closest point and toward the second surface side. The extension part is formed at least on opposing end surfaces of the pair of positive and negative lead terminal. The first recessed area is arranged on the exterior side relative to the closest point.

Method of manufacturing semiconductor device

As one embodiment, a method of manufacturing a semiconductor device includes the following steps. That is, the method of manufacturing a semiconductor device includes a first step of applying ultrasonic waves to a ball portion of a first wire in contact with a first electrode of the semiconductor chip while pressing the ball portion with a first load. In addition, the method of manufacturing a semiconductor device includes a step of, after the first step, applying the ultrasonic waves to the ball portion while pressing the ball portion with a second load larger than the first load, thereby bonding the ball portion and the first electrode.

BONDING WIRE FOR SEMICONDUCTOR DEVICE

A bonding wire for a semiconductor device includes a Cu alloy core material and a Pd coating layer on a surface of the Cu alloy core material, and contains Ga and Ge of 0.011 to 1.2% by mass in total, which is able to increase bonding longevity of the ball bonded part in the high-temperature, high-humidity environment, and thus to improve the bonding reliability. The thickness of the Pd coating layer is preferably 0.015 to 0.150 μm. When the bonding wire further contains one or more elements of Ni, Ir, and Pt in an amount, for each element, of 0.011 to 1.2% by mass, it is able to improve the reliability of the ball bonded part in a high-temperature environment at 175° C. or more. When an alloy skin layer containing Au and Pd is further formed on a surface of the Pd coating layer, wedge bondability improves. 2. The bonding wire for a semiconductor device according to claim 1 , wherein a thickness of the Pd coating layer is 0.015 μm or more and 0.150 μm or less.3. The bonding wire for a semiconductor device according to claim 1 , further comprising an alloy skin layer containing Au and Pd on the Pd coating layer.4. The bonding wire for a semiconductor device according to claim 3 , wherein a thickness of the alloy skin layer containing Au and Pd is 0.0005 μm or more and 0.050 μm or less.5. The bonding wire for a semiconductor device according to claim 1 , whereinthe bonding wire further contains one or more elements selected from Ni, Ir, and Pt, anda concentration of each of the elements relative to the entire wire is 0.011% by mass or more and 1.2% by mass or less.6. The bonding wire for a semiconductor device according to claim 1 , whereinthe Cu alloy core material contains Pd, anda concentration of Pd contained in the Cu alloy core material is 0.05% by mass or more and 1.2% by mass or less.7. The bonding wire for a semiconductor device according to claim 1 , whereinthe bonding wire further contains at least one element selected from B, P, and Mg, anda concentration ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

According to one embodiment, semiconductor device includes a semiconductor layer, an electrode provided on the semiconductor layer, and a bonding wire connected to the electrode, wherein the electrode comprises a first metal layer containing copper, a second metal layer containing aluminum, provided between the first metal layer and the semiconductor layer, and a third metal layer provided between the first metal layer and the second metal layer, the third metal layer comprising a material different from those of the first metal layer and the second metal layer, and the thickness of the first metal layer is larger than the thickness of the second metal layer and larger than the thickness of the third metal layer. 1. A semiconductor device , comprising:a semiconductor layer;an electrode provided on the semiconductor layer; anda bonding wire connected to the electrode, whereinthe electrode comprises a first metal layer containing copper, a second metal layer containing aluminum and between the first metal layer and the semiconductor layer, and a third metal layer between the first metal layer and the second metal layer, the third metal layer comprising a material different from those of the first metal layer and the second metal layer, andthe thickness of the first metal layer is greater than the thickness of the second metal layer and greater than the thickness of the third metal layer.2. The semiconductor device according to claim 1 , wherein the third metal layer contains at least one metal element selected from the group consisting of titanium claim 1 , tungsten claim 1 , and tantalum.3. The semiconductor device according to claim 1 , wherein the third metal layer contains at least one material selected from the group consisting of titanium claim 1 , tungsten claim 1 , tantalum claim 1 , titanium nitride claim 1 , tungsten nitride claim 1 , tantalum nitride claim 1 , and a titanium/tungsten alloy.4. The semiconductor device according to claim 1 , wherein the ...

COATING LAYER FOR A CONDUCTIVE STRUCTURE

A coating layer for use in copper integrated circuit interconnect and other conductive structures hinders and decreases oxide growth on surfaces of such conductive structures. The coating layer includes an amorphous copper containing layer deposited on a crystalline copper substrate, such as utilized for a lead frame and a bonding wire. Additional amorphous layers may be interposed between the amorphous copper containing layer and the copper substrate, such as an amorphous tantalum nitride layer and an amorphous titanium nitride layer. 1. A conductive structure comprising:a crystalline copper substrate suitable for an electrically conductive structure; anda coating layer over the crystalline copper substrate, wherein the coating layer comprises acontinuous amorphous copper containing film.2. The conductive structure as recited in claim 1 , wherein the coating layer further comprises:an amorphous tantalum nitride layer between the crystalline copper substrate and an amorphous titanium nitride layer; andthe amorphous titanium nitride layer between, the amorphous tantalum, nitride layer and the amorphous copper containing film.3. The conductive structure as recited in claim 2 , wherein the amorphous copper containing film comprises an amorphous copper alloy.4. The conductive structure as recited in claim 3 , wherein the amorphous copper alloy is selected from the group consisting of an amorphous copper zirconium alloy and an amorphous copper hafnium alloy.5. The conductive structure as recited in claim 1 , wherein the amorphous copper containing film comprises an amorphous copper alloy.6. The conductive structure as recited in claim 1 , wherein the coating layer comprises an amorphous copper alloy layer interposed between the amorphous copper containing film and the crystalline copper substrate.7. The conductive structure as recited in claim 6 , wherein the amorphous copper alloy layer comprises an amorphous copper zirconium alloy.8. The conductive structure as recited ...

INTEGRATED CIRCUIT PACKAGING

An integrated circuit package and methods for packaging an integrated circuit. In one example, a method for packaging an integrated circuit includes connecting input/output pads of a first die to terminals of a lead frame via palladium coated copper wires. An oxygen plasma is applied to the first die and the palladium coated copper wires. The first die and the palladium coated copper wires are encapsulated in a mold compound after application of the oxygen plasma. 1. A method for packaging an integrated circuit , comprising:connecting input/output pads of a first die to terminals of a lead frame via palladium coated copper wires;applying an oxygen plasma to the first die and the palladium coated copper wires;encapsulating the first die and the palladium coated copper wires in a mold compound after application of the oxygen plasma.2. The method of claim 1 , further comprising applying an argon plasma to the first die prior to the connecting.3. The method of claim 1 , further comprising connecting the first die to a second die via gold bond wires prior to applying the oxygen plasma.4. The method of claim 3 , further comprising connecting a capacitor of the first die to a capacitor of the second die via one of the gold bond wires.5. The method of claim 1 , further comprising connecting the first die to a second die via palladium coated copper wires prior to applying the oxygen plasma.6. The method of claim 1 , further comprising connecting input/output pads of a second die to terminals of the lead frame via palladium coated copper wires.7. The method of claim 6 , wherein applying the oxygen plasma comprises applying the oxygen plasma to the second die and the palladium coated copper wires connecting the input/output pads of the second die to terminals of the lead frame.8. The method of claim 6 , wherein the encapsulating comprises encapsulating the second die and the palladium coated copper wires connecting the input/output pads of the second die to terminals of the ...

BONDING WIRE FOR SEMICONDUCTOR DEVICE

A bonding wire for a semiconductor device includes a Cu alloy core material and a Pd coating layer formed on a surface thereof. Containing an element that provides bonding reliability in a high-temperature environment improves the bonding reliability of the ball bonded part in high temperature. Furthermore, making an orientation proportion of a crystal orientation <100> angled at 15 degrees or less to a wire longitudinal direction among crystal orientations in the wire longitudinal direction 30% or more when measuring crystal orientations on a cross-section of the core material in a direction perpendicular to a wire axis of the bonding wire, and making an average crystal grain size in the cross-section of the core material in the direction perpendicular to the wire axis of the bonding wire 0.9 to 1.5 μm provides a strength ratio of 1.6 or less. 1. A bonding wire for a semiconductor device , the bonding wire comprising:a Cu alloy core material; anda Pd coating layer formed on a surface of the Cu alloy core material, whereinwhen measuring crystal orientations on a cross-section of the core material in a direction perpendicular to a wire axis of the bonding wire, a crystal orientation <100> angled at 15 degrees or less to a wire axis direction has a proportion of 30% or more among crystal orientations in the wire axis direction,an average crystal grain size in the cross-section of the core material in the direction perpendicular to the wire axis of the bonding wire is 0.9 μm or more and 1.5 μm or less, andthe bonding wire contains one or more elements selected from Ga and Ge, and a concentration of the elements in total is 0.011 to 1.5% by mass relative to the entire wire.2. The bonding wire for a semiconductor device according to claim 1 , wherein a strength ratio defined by the following Equation (1) is 1.1 or more and 1.6 or less:{'br': None, 'Strength ratio=ultimate strength/0.2% offset yield strength. \u2003\u2003(1)'}3. The bonding wire for a semiconductor device ...

Method of Manufacturing Semiconductor Device

A method of manufacturing a semiconductor device which improves the reliability of a semiconductor device. The method of manufacturing the semiconductor device includes the step of connecting a ball portion formed at the tip of a wire with a pad (electrode pad) of a semiconductor chip. The pad is comprised of an aluminum-based material and has a trench in its portion to be connected with the ball portion. The ball portion is comprised of a harder material than gold. The step of connecting the ball portion includes the step of applying ultrasonic waves to the ball portion. 1. A method of manufacturing semiconductor device comprising the steps of:(a) providing a semiconductor chip including a front surface, a protective film formed on the front surface, and a first electrode pad exposed from the protective film in an opening formed in the protective film; and(b) after the step (a), connecting a ball portion formed at a tip of a wire with the first electrode pad,wherein the first electrode pad is comprised of an aluminum-based material,wherein a trench is formed on a portion of the first electrode pad exposed from the protective film,wherein the ball portion is comprised of a harder material than gold, and (b1) contacting the ball portion with the first electrode pad such that the ball portion overlaps the trench of the first electrode pad,', '(b2) after the step (b1), applying a load to the ball portion, and pressing the ball portion in a thickness direction of the first electrode pad, and', '(b3) after the step (b2), applying ultrasonic waves to the ball portion., 'wherein the step (b) comprises the following steps2. The method of manufacturing of the semiconductor device according to claim 1 ,wherein at the step (b3), the ultrasonic waves which oscillate in a first direction along the front surface of the semiconductor chip are applied, andwherein the trench of the first electrode pad has a first portion extending along a second direction crossing the first ...

WIRE BALL BONDING IN SEMICONDUCTOR DEVICES

A method of interconnecting components of a semiconductor device using wire bonding is presented. The method includes creating a free air ball at a first end of an aluminum wire that has a coating surrounding the aluminum wire, wherein the coating comprises palladium, and wherein the free air ball is substantially free of the coating. The method further includes the step of bonding the free air ball to a bond pad on a semiconductor chip, the bond pad having an aluminum surface layer, wherein the resultant ball bond and the bond pad form a substantially homogenous, aluminum-to-aluminum bond. The method may further include bonding a second, opposing end of the coated-aluminum wire to a bond site separate from the semiconductor chip, the bond site having a palladium surface layer, wherein the second end of the coated-aluminum wire and the bond site form a substantially homogenous, palladium-to-palladium bond. 1. A method of interconnecting components of a semiconductor device using wire bonding , the method comprising:providing a coated-aluminum wire, the coated-aluminum wire having a coating that comprises palladium;forming a free air ball from a first end of the coated-aluminum wire, wherein during the formation of the free air ball, the coating is removed from at least a portion of the free air ball;bonding the free air ball to a bond pad on a semiconductor chip, the bond pad having an aluminum surface layer, wherein the free air ball and the aluminum surface layer of the bond pad form a substantially homogenous, aluminum-to-aluminum ball bond; andbonding a second, opposing end of the coated-aluminum wire to a lead on a lead frame, the lead having a palladium surface layer, wherein the second end of the coated-aluminum wire and the lead form a substantially homogenous, palladium-to-palladium bond.2. The method of claim 1 , wherein the coating prevents oxidation of the free air ball during formation of the free air ball.3. The method of claim 1 , wherein the ...

RECONSTITUTED INTERPOSER SEMICONDUCTOR PACKAGE

A reconstituted semiconductor package and a method of making a reconstituted semiconductor package are described. An array of die-attach substrates is formed onto a carrier. A semiconductor device is mounted onto a first surface of each of the die-attach substrates. An interposer substrate is mounted over each of the semiconductor devices. The interposer substrates are electrically connected to the first surface of the respective die-attach substrates. A molding compound is filled in open spaces within and between the interposer substrates mounted to their respective die-attach substrates to form an array of reconstituted semiconductor packages. Electrical connections are mounted to a second surface of the die-attach substrates. The array of reconstituted semiconductor packages is singulated through the molding compound between each of the die-attach substrates and respective mounted interposer substrates. 1. A reconstituted interposer package comprising:an interposer substrate electrically mounted to a first surface of a reconstituted die-attach substrate and straddling an integrated circuit mounted on the first surface of the reconstituted die-attach substrate;a molding compound filled within open spaces between the interposer substrate and the first surface of the reconstituted die-attach substrate, wherein singulated surfaces of the molding compound reside along edges of the interposer substrate and the reconstituted die-attach substrate; andexternal electrical connections formed in a grid array on a second surface of the reconstituted die-attach substrate.2. The reconstituted interposer package of claim 1 , wherein one or more of the reconstituted interposer packages are assembled into one of a baseband microprocessor claim 1 , a set-top-box microprocessor claim 1 , a server message block microprocessor claim 1 , or an encryption/security microprocessor.3. The reconstituted semiconductor package of claim 1 , wherein the molding compound covers side walls of the ...

Substrate-Less Stackable Package With Wire-Bond Interconnect

A method for making a microelectronic unit includes forming a plurality of wire bonds on a first surface in the form of a conductive bonding surface of a structure comprising a patternable metallic element. The wire bonds are formed having bases joined to the first surface and end surfaces remote from the first surface. The wire bonds have edge surfaces extending between the bases and the end surfaces. The method also includes forming a dielectric encapsulation layer over a portion of the first surface of the conductive layer and over portions of the wire bonds such that unencapsulated portions of the wire bonds are defined by end surfaces or portions of the edge surfaces that are unconvered by the encapsulation layer. The metallic element is patterned to form first conductive elements beneath the wire bonds and insulated from one another by portions of the encapsulation layer. 1. An apparatus , comprising:conductive elements of a conductive layer on a bottom side of a package;wire bond wires coupled to and extending from first upper surface portions of the conductive elements;a microelectronic element coupled to second upper surface portions of the conductive elements through conductive contact structures;a wire bond wire of the wire bond wires interconnected for electrical conductivity to a conductive contact structure of the conductive contact structures by a conductive element of the conductive elements for a redistribution on the bottom side of the package; anda dielectric layer contacting the wire bond wires and side portions of the microelectronic element to define at least one dimension of the package, the conductive layer at least partially defining the bottom side of the package.2. The apparatus according to claim 1 , wherein the redistribution is configured to provide contacts of the package for interconnects for electrical conductivity with a microelectronic structure.3. The apparatus according to claim 1 , wherein the redistribution is a lower ...

Image sensor device

An image sensor device, as well as methods therefor, is disclosed. This image sensor device includes a substrate having bond pads. The substrate has a through substrate channel defined therein extending between a front side surface and a back side surface thereof. The front side surface is associated with an optically-activatable surface. The bond pads are located at or proximal to the front side surface aligned for access via the through substrate channel. Wire bond wires are bonded to the bond pads at first ends thereof extending away from the bond pads with second ends of the wire bond wires located outside of an opening of the channel at the back side surface. A molding layer is disposed along the back side surface and in the through substrate channel. A redistribution layer is in contact with the molding layer and interconnected to the second ends of the wire bond wires.

PALLADIUM-COATED COPPER BONDING WIRE AND METHOD FOR MANUFACTURING SAME

There is provided a palladium-coated copper bonding wire that does not cause a shrinkage cavity during first bonding, has high bonding reliability, and is capable of maintaining excellent bonding reliability for a long period of time even in high-temperature and high-humidity environments. A palladium-coated copper bonding wire in which a concentration of palladium is 1.0 mass % or more and 4.0 mass % or less relative to the total of copper, palladium, and a sulfur group element, a total concentration of the sulfur group element is 50 mass ppm or less, and a concentration of sulfur is 5 mass ppm or more and 12 mass ppm or less, a concentration of selenium is 5 mass ppm or more and 20 mass ppm or less, or a concentration of tellurium is 15 mass ppm or more and 50 mass ppm or less, and the palladium-coated copper bonding wire including a palladium-concentrated region with the average concentration of palladium of 6.5 atom % or more and 30.0 atom % or less relative to the total of copper and palladium within a range from a surface of a tip portion of a free air ball formed at a tip of the wire to 5.0 nm or more and 100.0 nm or less. 1. A palladium-coated copper bonding wire containing 50 mass ppm or less of sulfur group element in total , the palladium-coated copper bonding wire comprising:a core material containing copper as a main component; anda palladium layer on the core material, wherein 5 mass ppm or more and 12 mass ppm or less of sulfur (S);', '5 mass ppm or more and 20 mass ppm or less of selenium (Se); and', '15 mass ppm or more and 50 mass ppm or less of tellurium (Te),, 'the sulfur group element includes at least one ofa concentration of palladium is 1.0 mass % or more and 4.0 mass % or less relative to the total of copper, palladium, and the sulfur group element of the palladium-coated copper bonding wire, and,the palladium-coated copper bonding wire includes a palladium-concentrated region with the average concentration of palladium of 6.5 atom % or more ...

PACKAGED SEMICONDUCTOR ASSEMBLIES AND METHODS FOR MANUFACTURING SUCH ASSEMBLIES

Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of a packaged semiconductor assembly includes a support member having a first bond-site and a die carried by the support member having a second bond-site. An interconnect structure is connected between the first and second bond-sites and includes a wire that is coupled to at least one of the first and second bond-sites. The interconnect structure also includes a third bond-site coupled to the wire between the first and second bond-sites. 1. A method of forming a semiconductor assembly , comprising:forming a conductive pedestal at a first bond-site of a support member, wherein the pedestal has a surface spaced apart from the support member;attaching the support member to a die having a second bond-site;disposing an encapsulant adjacent to the pedestal;removing at least a portion of the encapsulant to at least partially expose the surface of the pedestal; andforming a redistribution structure connected to the surface of the pedestal and the first bond-site and having a third bond-site between the first and second bond-sites and spaced apart from the die.2. The method of wherein removing at least a portion of the encapsulant comprises forming a via through the encapsulant that terminates at the surface of the pedestal.3. The method of claim 2 , further comprising disposing a conductive member in the via and coupling the conductive member to the surface of the pedestal with the conductive member exposed for an electrical connection external to the assembly.4. A method of forming a stacked semiconductor assembly claim 2 , comprising:singulating a first semiconductor assembly having a first die and a first bond-site at a periphery of the first assembly, the first assembly having a first footprint;singulating a second semiconductor assembly along a singulation line, the second semiconductor assembly having a second ...

INTEGRATED CIRCUIT PACKAGING

An integrated circuit and methods for packaging the integrated circuit. In one example, a method for packaging an integrated circuit includes connecting input/output pads of a first integrated circuit die to terminals of a lead frame via palladium coated copper wires. An oxygen plasma is applied to the first integrated circuit die and the palladium coated copper wires. The first integrated circuit die and the palladium coated copper wires are encapsulated in a mold compound after application of the oxygen plasma. 1. An integrated circuit package comprising:a first circuit die;a second circuit die;a portion of a lead frame;palladium coated copper bond wires that conductively couple the first circuit die and the second circuit die to the lead frame;gold bond wires that conductively couple the first circuit die to the second circuit die; andencapsulation material covering the first circuit die, the second circuit die, the lead frame, the palladium coated copper bond wires, and the gold bond wires.2. The integrated circuit package of claim 1 , wherein the first circuit die comprises a capacitor connected to one of the gold bond wires.3. The integrated circuit package of claim 1 , wherein the second circuit die comprises a capacitor connected to the one of the gold bond wires.4. The integrated circuit package of claim 1 , wherein an amount of palladium coating the palladium coated copper wires disposed within the encapsulation material is uniform over a surface of the palladium coated copper wires.5. The integrated circuit package of claim 1 , wherein an oxygen plasma is applied to the first integrated circuit die and the palladium coated copper wires.6. The integrated circuit package of claim 1 , wherein an argon plasma is applied to the first integrated circuit die.7. An integrated circuit package comprising:a first die attached to a first die attach pad;a second die attached to a second die attach pad;at least one gold wire connecting the first die and the second die; ...

Encapsulating resin composition, semiconductor device using the encapsulating resin composition, and method for manufacturing semiconductor device using the encapsulating resin composition

An encapsulating resin composition contains a thermosetting resin component, a curing accelerator, an inorganic filler, an ion trapping agent, and an aromatic monocarboxylic acid having one or more electron-withdrawing functional groups selected from a nitro group and a cyano group. The encapsulating resin composition is solid at 25° C., and has a sulfur content, measured by X-ray fluorescence analysis, of 0.1 mass % or less in terms of SO 3 .

Half Bridge Circuit, Method of Operating a Half Bridge Circuit and a Half Bridge Circuit Package

A half bridge circuit includes an input connection configured to supply an electric input, an output connection configured to supply an electric output to a load to be connected to the output connection, a switch and a diode arranged between the input connection and the output connection and a voltage limiting inductance arranged in series between the switch and the diode. The voltage limiting inductance is configured to limit, upon switching the switch, a maximum voltage across the switch to below a breakdown voltage of the switch. A corresponding method of operating the half bridge circuit and package are also described. 120-. (canceled)21. A half bridge circuit , comprising:an input connection configured to supply an electric input;an output connection configured to supply an electric output to a load to be connected to the output connection;a switch and a diode arranged between the input connection and the output connection; anda voltage limiting inductance arranged in series between the switch and the diode, the voltage limiting inductance configured to limit, upon switching the switch, a maximum voltage across the switch to below a breakdown voltage of the switch.22. The half bridge circuit of claim 21 , wherein the switch is a field effect transistor switch claim 21 , wherein the diode is a field effect transistor diode claim 21 , and wherein the voltage limiting inductance is arranged in series between a source of the field effect transistor switch and a drain of the field effect transistor diode.23. The half bridge circuit of claim 21 , wherein both the switch and the diode are connected within a loop between the input connection and the output connection claim 21 , and wherein the voltage limiting inductance has an inductance value in a range between 20% and 70% of a loop inductance of the loop.24. The half bridge circuit of claim 23 , wherein the voltage limiting inductance is distributed over the entire loop.25. The half bridge circuit of claim 21 , ...

STRUCTURES AND METHODS FOR REDUCING CORROSION IN WIRE BONDS

A semiconductor structure includes a bond pad and a wire bond coupled to the bond pad. The wire bond includes a bond in contact with the bond pad. The wire bond includes a coating on a surface of the wire bond, and a first exposed portion of the wire bond in a selected location. The wire bond is devoid of the coating over the selected location of the wire bond, and an area of the first exposed portion is at least one square micron. 1. A method comprising: the wire bond includes a coating, and', 'the wire bond is in contact with the bond pad; and, 'coupling a wire bond to a bond pad, wherein'}subsequent to the coupling the wire bond, removing a first portion of the coating on the wire bond in a selected location.2. The method of claim 1 , whereinthe wire bond includes one or more exposures in the coating, andthe one or more exposures are in proximity to the first portion.3. The method of claim 2 , whereinthe one or more exposures exist in the coating prior to the removing the first portion of the coating, andthe one or more exposures are localized within a contact area of the wire bond that has been in contact with a bonding tool during a wire bonding process.4. The method of claim 3 , wherein the selected location is located outside of the contact area.5. The method of claim 1 , wherein the removing the first portion of the coating utilizes one oflaser removal of the coating,mechanical removal of the coating, andchemical removal of the coating.6. The method of claim 1 , whereinthe wire bond includes one or more additional coatings, and 'removing a second portion of the one or more additional coatings.', 'the removing the first portion of the coating includes'}7. The method of claim 1 , whereinthe wire bond includes a bond in contact with the bond pad, andthe first portion includes a minimum width of one micron.8. The method of claim 1 , wherein copper,', 'silver, and', 'aluminum, and, 'the wire bond includes one of'} palladium-inclusive coating,', 'organic coating, ...

Binding wire and semiconductor package structure using the same

A semiconductor package structure includes a substrate, and a package preform. The substrate includes a plurality of conductive tracing wires. The package preform includes a semiconductor chip and a plurality of binding wires. The semiconductor chip includes a plurality of welding spots, and the welding spots are electrically connected with corresponding conductive tracing wires by the binding wires. Each binding wire comprises a carbon nanotube composite wire, the carbon nanotube composite wire includes a carbon nanotube wire and a metal layer. The carbon nanotube wire consists of a plurality of carbon nanotubes spirally arranged along an axial direction an axial direction of the carbon nanotube wire.

BONDING WIRE FOR SEMICONDUCTOR DEVICES

Provided is a bonding wire capable of reducing the occurrence of defective loops. The bonding wire includes: a core material which contains more than 50 mol % of a metal M; an intermediate layer which is formed over the surface of the core material and made of Ni, Pd, the metal M, and unavoidable impurities, and in which the concentration of the Ni is 15 to 80 mol %; and a coating layer formed over the intermediate layer and made of Ni, Pd and unavoidable impurities. The concentration of the Pd in the coating layer is 50 to 100 mol %. The metal M is Cu or Ag, and the concentration of Ni in the coating layer is lower than the concentration of Ni in the intermediate layer. 1. A bonding wire for a semiconductor device comprising:a core material containing more than 50 mol % of a metal M;an intermediate layer formed over a surface of the core material and made of Ni, Pd, the metal M, and unavoidable impurities, concentration of the Ni being 15 to 80 mol %; anda coating layer formed over the intermediate layer and made of Ni, Pd and unavoidable impurities, the concentration of the Pd being 50 to 100 mol %,wherein the metal M is Cu or Ag, and the concentration of the Ni in the coating layer is lower than the concentration of the Ni in the intermediate layer.2. The bonding wire according to claim 1 , wherein the thickness of the intermediate layer is 8 to 80 nm.3. The bonding wire according to claim 1 , whereinthe coating layer further contains Au, and the bonding wire further comprises a surface layer formed over the coating layer and made of an alloy containing Au and Pd, the concentration of the Au being 10 to 70 mol %, the sum total concentration of the Au and the Pd being 80 mol % or more,wherein the concentration of the Au in the coating layer is lower than the concentration of the Au in the surface layer.4. The bonding wire according to claim 3 , wherein the total thickness of the surface layer claim 3 , the coating layer claim 3 , and the intermediate layer is 25 ...

BONDING WIRE FOR SEMICONDUCTOR DEVICE

There is provided a Cu bonding wire having a Pd coating layer on a surface thereof, that improves bonding reliability of a ball bonded part in a high-temperature and high-humidity environment and is suitable for on-vehicle devices. 1. A bonding wire for a semiconductor device comprising:a Cu alloy core material; anda Pd coating layer formed on a surface of the Cu alloy core material, wherein the bonding wire contains In,a concentration of In is 0.031% by mass or more and 1.2% by mass or less relative to the entire wire, anda thickness of the Pd coating layer is 0.015 μm or more and 0.150 μm or less.2. The bonding wire for a semiconductor device according to claim 1 , whereinthe Cu alloy core material contains at least one element selected from Pt, Pd, Rh and Ni, anda concentration of each of the elements contained in the Cu alloy core material is 0.05% by mass or more and 1.2% by mass or less.3. The bonding wire for a semiconductor device according to claim 1 , further comprising an Au skin layer on the Pd coating layer.4. The bonding wire for a semiconductor device according to claim 3 , wherein a thickness of the Au skin layer is 0.0005 μm or more and 0.050 μm or less.5. The bonding wire for a semiconductor device according to claim 1 , whereinthe bonding wire further contains at least one element selected from B, P, Mg, Ga and Ge, anda concentration of each of the elements is 1 ppm by mass or more and 100 ppm by mass or less relative to the entire wire.6. The bonding wire for a semiconductor device according to claim 1 , wherein claim 1 , in a measurement result when measuring crystal orientations on a surface of the bonding wire claim 1 , a crystal orientation <111> angled at 15 degrees or less to a longitudinal direction of the bonding wire has a proportion of 30% or more and 100% or less among crystal orientations in the wire longitudinal direction. The present invention relates to a bonding wire for a semiconductor device used to connect electrodes on a ...

Package in Package (PiP) Electronic Device and Manufacturing Method thereof

A manufacturing method for Package in Package (PiP) electronic device based on multi-row Quad Flat No-lead (QFN) package is provided wherein the lower surface of plate metallic base material are half-etched to form grooves. Insulation filling material is filled in the half-etched grooves. The upper surface of plate metallic base material is half-etched to form chip pad and multi-row of leads. Encapsulating IC chip for wire bonding, adhesive material, metal wire, chip pad and a plurality of leads to form a multi-row QFN package as an inner package. Flip-chip bonding IC chip with solder bumps on the first metal material layer of leads. Encapsulating IC chip with solder bumps, the multi-row QFN package, adhesive material, and leads to form an array of PiP electronic devices. Sawing and separating the PiP electronic device array, forming PiP electronic device unit.

CHIP PACKAGE, METHOD OF FORMING A CHIP PACKAGE AND METHOD OF FORMING AN ELECTRICAL CONTACT

In various embodiments, a chip package is provided. The chip package may include a chip, a metal contact structure including a non-noble metal and electrically contacting the chip, a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure. 1. A chip package , comprising:a chip comprising a chip metal surface;a metal contact structure, the metal contact structure electrically contacting the chip metal surface;a packaging material; anda protective layer comprising or consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material; 'Ni, Co, Cr, Ti, V, Mn, Zn, Sn, Mo, Zr.', 'wherein the protective layer comprises or essentially consists of at least one material of a group of inorganic materials, the group consisting of'}2. A chip package , comprising:a chip comprising a chip metal surface;a metal contact structure, the metal contact structure electrically contacting the chip metal surface, wherein the metal contact structure comprises copper and/or silver;a packaging material; anda protective layer comprising or consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material;wherein the protective layer comprises or essentially consists of an azole and/or tetracyanoquinodimethane that is different from the packaging material.3. A leadframe based chip package , comprising:a chip;a metal contact structure comprising a non-noble metal and electrically contacting the chip;a packaging material; anda ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device includes a semiconductor substrate SB and a wiring structure formed on a main surface of the semiconductor substrate SB. The uppermost first wiring layer among a plurality of wiring layers included in the wiring structure includes a pad PD, and the pad PD has a first region for bonding a copper wire and a second region for bringing a probe into contact with the pad. A second wiring layer that is lower by one layer than the first wiring layer among the plurality of wiring layers included in the wiring structure includes a wiring line M arranged immediately below the pad PD, the wiring line M is arranged immediately below a region other than the first region of the pad PD, and no conductor pattern in the same layer as a layer of the wiring line M belong is formed immediately below the first region of the pad PD. 120-. (canceled)21. A semiconductor device comprising:a semiconductor chip having a pad;a copper wire electrically connected to the pad of the semiconductor chip; anda sealing resin portion sealing the semiconductor chip and the copper wire, a semiconductor substrate;', 'a plurality of semiconductor elements formed on a main surface of the semiconductor substrate; and', 'a wiring structure formed on the main surface of the semiconductor substrate, the wiring structure including a plurality of insulating films and a plurality of wiring layers,, 'wherein the semiconductor chip includes a first wiring layer; and', 'a second wiring layer,, 'wherein the plurality of wiring layers includeswherein the first wiring layer is an uppermost layer among the plurality of wiring layers,wherein the first wiring layer includes the pad, a first region for bonding the copper wire; and', 'a second region for bringing a probe into contact with the pad,, 'wherein the pad haswherein the second wiring layer is one layer below the first wiring layer,wherein the second wiring layer includes a first wiring line arranged immediately below the second region of the ...

COATED WIRE FOR BONDING APPLICATIONS

The invention is related to a bonding wire which contains a core having a surface and a coating layer which is at least partially superimposed over the surface of the core. The core contains a core main component selected from copper and silver. The coating layer contains a coating component selected from palladium, platinum, gold, rhodium, ruthenium, osmium and iridium in an amount of at least 10% and further contains the core main component in an amount of at least 10%. 121.-. (canceled)22. A bonding wire comprising a core having a surface and a coating layer which is at least partially superimposed over the surface of the core , wherein the core comprises a core main component selected from the group consisting of copper and silver; and wherein the coating layer comprises a coating component selected from the group consisting of palladium , platinum , gold , rhodium , ruthenium , osmium and iridium in an amount of at least 10% and further comprises the core main component in an amount of at least 10%.23. The wire according to claim 22 , wherein an outer range of the coating layer extends from a depth of 0.1% of a wire diameter to a depth of 0.25% of the wire diameter claim 22 , and wherein the amount of the core main component and the amount of the coating component are present in the outer range.24. The wire according to claim 23 , wherein the amount of the core main component in the outer range is between 30% and 70%.25. The wire according to claim 23 , wherein the amount of the coating component decreases within the outer range toward an inside of the wire.26. The wire according to claim 25 , wherein a difference of the amount of the coating component at a radially inner border of the outer range and the amount of the coating component at a radially outer border of the outer range is not more than 30%.27. The wire according to claim 22 , wherein a main component of the wire changes at least two times starting from an outside of the wire up to a depth of 0.25% ...

COATED WIRE

A wire comprising a wire core with a surface, the wire core having a coating layer superimposed on its surface, wherein the wire core includes: (a) pure silver consisting of silver and further components; or (b) doped silver consisting of silver, at least one doping element, and further components; or (c) a silver alloy consisting of silver, palladium and further components; or (d) a silver alloy consisting of silver, palladium, gold, and further components; or (e) a doped silver alloy consisting of silver, palladium, gold, at least one doping element, and further components, wherein the individual amount of any further component is less than 30 wt.-ppm and the individual amount of any doping element is at least 30 wt.-ppm, and the coating layer is a single-layer of gold or palladium or a double-layer comprised of an inner layer of nickel or palladium and an adjacent outer layer of gold. 1. A wire comprising a wire core with a surface , the wire core having a coating layer superimposed on its surface , wherein the wire core itself consists of:(a) pure silver consisting of (a1) silver in an amount in the range of from 99.99 to 100 wt.-% and (a2) further components in a total amount of from 0 to 100 wt.-ppm; or(b) doped silver consisting of (b1) silver in an amount in the range of from 99.69 to 99.987 wt.-%, (b2) at least one doping element selected from the group consisting of calcium, nickel, platinum, copper, rhodium and ruthenium, in a total amount of from 30 to 3000 wt.-ppm and (b3) further components in a total amount of from 0 to 100 wt.-ppm; or(c) a silver alloy consisting of (c1) silver in an amount in the range of from 95.99 to 99.49 wt.-%, (c2) palladium in an amount in the range of from 0.5 to 4 wt.-% and (c3) further components in a total amount of from 0 to 100 wt.-ppm; or(d) a silver alloy consisting of (d1) silver in an amount in the range of from 93.99 to 99.39 wt.-%, (d2) palladium in an amount in the range of from 0.5 to 4 wt.-%, (d3) gold in an ...

Bonding wire for semiconductor device

The present invention provides a bonding wire capable of simultaneously satisfying ball bonding reliability and wedge bondability required of bonding wires for memories, the bonding wire including a core material containing one or more of Ga, In, and Sn for a total of 0.1 to 3.0 at % with a balance being made up of Ag and incidental impurities; and a coating layer formed over a surface of the core material, containing one or more of Pd and Pt, or Ag and one or more of Pd and Pt, with a balance being made up of incidental impurities, wherein the coating layer is 0.005 to 0.070 μm in thickness.

Semiconductor device and manufacturing method thereof

A semiconductor device includes: a pad electrode 9 a formed in an uppermost layer of a plurality of wiring layers; a base insulating film 11 having an opening 11 a on the pad electrode 9 a ; a base metal film UM formed on the base insulating film 11 ; a redistribution line RM formed on the base metal film UM; and a cap metal film CM formed so as to cover an upper surface and a side surface of the redistribution line RM. In addition, in a region outside the redistribution line RM, the base metal film UM made of a material different from that of the redistribution line RM and the cap metal film CM made of a material different from the redistribution line RM are formed between the cap metal film CM formed on the side surface of the redistribution line RM and the base insulating film 11 , and the base metal film UM and the cap metal film CM are in direct contact with each other in the region outside the redistribution line RM.

BONDING WIRE FOR SEMICONDUCTOR DEVICE

A bonding wire for a semiconductor device, which is suitable for on-vehicle devices bonding wire, has excellent capillary wear resistance and surface flaw resistance while ensuring high bonding reliability and further satisfies overall performance including ball formability and wedge bondability, the bonding wire including: a Cu alloy core material; a Pd coating layer formed on a surface of the Cu alloy core material; and a Cu surface layer formed on a surface of the Pd coating layer, in which the bonding wire for semiconductor device contains Ni, a concentration of the Ni in the bonding wire is 0.1 to 1.2 wt. %, the Pd coating layer is 0.015 to 0.150 μm in thickness, and the Cu surface layer is 0.0005 to 0.0070 μm in thickness. 1. A bonding wire for a semiconductor device comprising: a Cu alloy core material; a Pd coating layer formed on a surface of the Cu alloy core material; and a Cu surface layer formed on a surface of the Pd coating layer , wherein the bonding wire contains Ni , a concentration of the Ni in the bonding wire is 0.1 to 1.2 wt. % , the Pd coating layer is 0.015 to 0.150 μm in thickness , and the Cu surface layer is 0.0005 to 0.0070 μm in thickness.2. The bonding wire according to claim 1 , further comprising an alloy coating layer between the Pd coating layer and the Cu surface layer claim 1 , the alloy coating layer containing Au and Pd claim 1 , wherein the alloy coating layer is 0.0005 to 0.0500 μm in thickness.3. The bonding wire according to claim 1 , wherein the Cu alloy core material further contains at least one or more elements selected from among Zn claim 1 , In claim 1 , Pt claim 1 , and Pd; and a concentration of the one or more elements in the Cu alloy core material is 0.05 to 0.50 wt. %.4. The bonding wire according to claim 1 , wherein the bonding wire further contains at least one or more elements selected from among B claim 1 , P claim 1 , Mg claim 1 , and Sn; and a concentration of the one or more elements in the bonding wire is ...

VERTICAL WIRE CONNECTIONS FOR INTEGRATED CIRCUIT PACKAGE

A method includes aligning a wire with a package body having a contact pad and moving the wire through the package body to form electrical contact with the contact pad. 125.-. (canceled)26. A method of forming wire connections comprising:aligning a wire with a package body having a contact pad; andmoving the wire through the package body to form electrical contact with the contact pad.27. The method of wherein moving the wire through the package body forms electrical contact with multiple contact pads at different levels of the package body.28. The method of wherein the package body comprises dielectric material.29. The method of wherein the package body comprises an adhesion layer coupled to the package body claim 28 , and wherein the wire is moved through the contact pad claim 28 , the dielectric layer claim 28 , and the adhesion layer to a rigid carrier supporting the package body.30. The method of and further comprising deforming a tip of the wire during moving the wire as the tip of the wire contacts the rigid carrier.31. The method of and further comprising curing the dielectric material following the formation of the electrical contact with the contact pad.32. The method of wherein the wire has a tip with a reduced cross section on a portion of the wire first contacting the body package as the wire is moved through the body package.33. The method of wherein multiple wires are aligned with respect to multiple contact pads and moved through the package to form electrical contact with respective contact pads.34. The method of wherein at least one of the respective contact pads is on a different level of the package body.35. The method of wherein the wire is moved by pressing the wire through the package body.36. The method of wherein the wire is moved by shooting the wire through the package body.37. A method of forming wire connections comprising:arranging wires in a stencil;aligning the stencil to position the wires above selected contact pads of a stack of ...

SEGMENTED SHIELDING USING WIREBONDS

The present disclosure relates to segmented shielding using wirebonds. In an exemplary aspect, a shield is formed from a series of wires (e.g., wirebonds) to create a wall and/or shielded compartment in an integrated circuit (IC) module. The wires can be located in any area within the IC module. The IC module may be overmolded with an insulating mold compound, and a top surface of the insulating mold can be ground or otherwise removed to expose ends of the wires to a shield layer which surrounds the insulating mold. Some examples may further laser ablate or otherwise form cavities around the ends of the wires to create stronger bonding between the wires of the shield and the shield layer. 1. A method for forming a shielded compartment in an integrated circuit (IC) module , comprising:providing a module substrate; placing a first series of wires to form a first wall separating the shielded compartment from a portion of the module substrate; and', 'bonding the first series of wires to a conductive plate in the module substrate;, 'forming an electromagnetic shield, comprisingdepositing an insulating mold over the module substrate; anddepositing a shield layer over the insulating mold, the shield layer contacting an exposed end of each of the first series of wires.2. The method of claim 1 , wherein bonding the first series of wires to the conductive plate further comprises bonding ends of a plurality of wire loops to the conductive plate.3. The method of claim 2 , wherein the ends of the plurality of wire loops are separated from nearby ends of the plurality of wire loops.4. The method of claim 1 , wherein the insulating mold surrounds each of the first series of wires.5. The method of claim 1 , further comprising removing a portion of the insulating mold to expose the exposed end of each of the first series of wires.6. The method of claim 5 , further comprising laser ablating a cavity in the insulating mold about each of the exposed ends of the first series of wires to ...

STACK PACKAGE AND METHODS OF MANUFACTURING THE SAME

A stack package and a method of manufacturing the stack package are provided. The method includes: attaching a first semiconductor device onto a first surface of a first package substrate; attaching a molding resin material layer onto a first surface of a second package substrate; arranging the first surface of the first package substrate and the first surface of the second package substrate to face each other; compressing the first package substrate and the second package substrate while reflowing the molding resin material layer; and hardening the reflowed molding resin material layer. 1. A stack package , comprising:a first package substrate including a first surface on which a first semiconductor device is mounted;a second package substrate provided on the first semiconductor device, the second package substrate including a first surface facing the first surface of the first package substrate;a connection terminal connecting the first semiconductor device and the first package substrate;a connector connecting a terminal on the first surface of the first package substrate and a terminal on the first surface of the second package substrate corresponding thereto; andmolding resin encircling the connector while filling a portion between the first package substrate and the second package substrate,wherein the molding resin contacts all side surfaces of the connector.2. The stack package of claim 1 ,wherein an upper portion and a lower portion of the connector are substantially symmetrical to each other, andwherein the cross sectional area of the connector in a horizontal direction between the first package substrate and the second package substrate is greater than the cross sectional area thereof at the terminal on the first package substrate.3. The stack package of claim 1 ,wherein a contact angle between the connector and the first package substrate is substantially identical to a contact angle between the connector and the second package substrate.4. The stack ...

Superconducting bonds for thin film devices

A method of bonding a superconductive ribbon lead to a superconducting bonding pad connected to superconducting circuitry. The thin ribbon is first coated with a fresh layer of the same material from which it is made and then a very thin layer of a noble metal is applied over that fresh layer. The bonding pad is also prepared with a very thin layer of the noble metal. Those coated surfaces are placed in facing contact and ultrasonically bonded.

Semiconductor package with drilled mold cavity

A semiconductor package includes a semiconductor die including terminals, a plurality of leads, at least some of the leads being electrically coupled to the terminals within the semiconductor package, a sensor on a surface of the semiconductor die, laser shielding forming a perimeter around the sensor on the surface of the semiconductor die, and a mold compound surrounding the semiconductor die except for an area inside the perimeter on the surface of the semiconductor die such that the sensor is exposed to an external environment.

광원 패키지 및 그를 포함하는 표시 장치

본 발명은 광원 패키지 및 그를 포함하는 표시 장치에 관한 것으로서, 기판; 상기 기판 위에 실장된 발광 소자; 상기 발광 소자의 표면에 인접하여 형성된 적색 형광체층; 및 상기 발광 소자 및 상기 적색 형광체층을 봉지하는 봉지층을 포함하고, 상기 적색 형광체층의 형광체가 불화물계 또는 황화물계 형광체인 것을 특징으로 하는 광원 패키지를 제공한다. 본 발명의 광원 패키지 및 그를 포함하는 표시 장치는 장시간이 흐른 뒤에도 표시되는 색상이 수분에 의하여 열화됨이 없이 우수한 색재현성을 가질 수 있다.

Semiconductor device and method for fabricating the same

본 발명은 구리 금속배선을 사용하는 반도체 소자에서, 스크라이브 레인 영역에서 구리 금속배선이 노출되는 것을 방지하여 반도체 소자의 수율 증가 및 신뢰성 향상을 확보할 수 있는 반도체 소자의 제조방법을 제공한다. The present invention provides a method of manufacturing a semiconductor device in which a semiconductor device using a copper metal wiring is prevented from exposing the copper metal wiring in a scribe lane region, thereby increasing yield and improving reliability of the semiconductor device. 본 발명에 따르면, 먼저 스크라이브 레인 영역에는 제1 금속으로 이루어진 제1 패드 및 연결배선을 형성하고, 칩 영역에는 제1 금속으로 이루어진 제2 패드를 형성한다. 다음에, 제1 패드, 연결배선 및 제2 패드 상에 식각정지막 및 제1 절연막을 순차로 형성한다. 그리고 식각정지막 및 제1 절연막을 패터닝하여 제1 및 제2 패드를 노출시키고, 제1 및 제2 패드 상에 제2 금속으로 이루어진 제3 및 제4 패드를 형성한다. 그런 후에 제3 및 제4 패드와 패터닝된 제1 절연막 상에 제2 및 제3 절연막을 순차적으로 형성하고, 제3 절연막 상에 형성되어 패터닝된 감광막을 이용하여 제3 및 제4 패드가 노출되도록 제1, 제2 및 제3 절연막을 식각한다. According to the present invention, first, a first pad made of a first metal and a connection wiring are formed in the scribe lane region, and a second pad made of the first metal is formed in the chip region. Next, an etch stop film and a first insulating film are sequentially formed on the first pad, the connection wiring, and the second pad. The etch stop layer and the first insulating layer are patterned to expose the first and second pads, and third and fourth pads made of a second metal are formed on the first and second pads. Thereafter, second and third insulating layers are sequentially formed on the third and fourth pads and the patterned first insulating layer, and the third and fourth pads are exposed on the third insulating layer by using the patterned photosensitive layer. The first, second and third insulating films are etched. 구리, 부식, 스크라이브 레인, 식각정지막 Copper, Corrosion, Scribe Lane, Etch Stop

Optical transmitting set packaging part and device and correlation technique with improved wire bonding

本发明公开了具有改进的引线接合的光发射器封装件和装置及相关方法。在一个实施例中，光发射器封装件可包括通过焊线电连接至电元件的至少一个发光二极管（LED）芯片。所述焊线可通过改进的引线接合参数，诸如约150℃或更低的温度、约100ms或更少的接合时间、约1700mW或更小的功率以及约100克力（gf）或更小的力或其组合来提供。

Semiconductor PiP (package in package) system structure and manufacturing method thereof

本发明公开了一种半导体封装中封装系统结构及制造方法。本半导体封装中封装系统结构包括引线框架、第一金属材料层、第二金属材料层、具有凸点的IC芯片、引线键合的IC芯片、绝缘填充材料、粘贴材料和塑封材料。引线框架包括芯片载体和多个围绕芯片载体呈多圈排列的引脚。第一金属材料层和第二金属材料层分别配置于引线框架上表面和下表面。绝缘填充材料配置于引线框架的台阶式结构下。引线键合的IC芯片配置于芯片载体上。具有凸点的IC芯片的凸点倒装焊接配置于多圈引脚的内引脚上，通过塑封材料包覆具有凸点的IC芯片、引线键合的IC芯片形成半导体封装中封装系统结构。本发明是基于QFN封装的高可靠性、低成本、高I/O密度的三维封装结构及其制造方法。

Bonding wires for semiconductor devices

An object of the present invention is to provide a high-performance bonding wire that is suitable for semiconductor mounting technology, such as stacked chip bonding, thinning, and fine pitch mounting, where wire lean (leaning) at an upright position of a ball and spring failure can be suppressed and loop linearity and loop height stability are excellent. This bonding wire for a semiconductor device includes a core material made of a conductive metal, and a skin layer formed on the core material and containing a metal different from the core material as a main component; wherein a relationship between an average size (a) of crystal grains in the skin layer on a wire surface along a wire circumferential direction and an average size (b) of crystal grains in the core material on a normal cross section, the normal cross section being a cross section normal to a wire axis, satisfies an inequality of a/b ‰¤ 0.7.

Semiconductor device packages including connecting elements

Described herein are wafer-level semiconductor device packages with stacking functionality and related stacked package assemblies and methods. In one embodiment, a semiconductor device package includes a set of connecting elements disposed adjacent to a periphery of a set of stacked semiconductor devices. At least one of the connecting elements is wire-bonded to an active surface of an upper one of the stacked semiconductor devices.

Substrate-less stackable package with wire-bond interconnect

A method for making a microelectronic unit includes forming a plurality of wire bonds on a first surface in the form of a conductive bonding surface of a structure comprising a patternable metallic element. The wire bonds are formed having bases joined to the first surface and end surfaces remote from the first surface. The wire bonds have edge surfaces extending between the bases and the end surfaces. The method also includes forming a dielectric encapsulation layer over a portion of the first surface of the conductive layer and over portions of the wire bonds such that unencapsulated portions of the wire bonds are defined by end surfaces or portions of the edge surfaces that are uncovered by the encapsulation layer. The metallic element is patterned to form first conductive elements beneath the wire bonds and insulated from one another by portions of the encapsulation layer.

BVA interposer

A method for making an interposer includes forming a plurality of wire bonds bonded to one or more first surfaces of a first element. A dielectric encapsulation is formed contacting an edge surface of the wire bonds which separates adjacent wire bonds from one another. Further processing comprises removing at least portions of the first element, wherein the interposer has first and second opposite sides separated from one another by at least the encapsulation, and the interposer having first contacts and second contacts at the first and second opposite sides, respectively, for electrical connection with first and second components, respectively, the first contacts being electrically connected with the second contacts through the wire bonds.

Ball bonding metal wire bond wires to metal pads

An apparatus, and methods therefor, relates generally to an integrated circuit package. In such an apparatus, a platform substrate has a copper pad. An integrated circuit die is coupled to the platform substrate. A wire bond wire couples a contact of the integrated circuit die and the copper pad. A first end of the wire bond wire is ball bonded with a ball bond for direct contact with an upper surface of the copper pad. A second end of the wire bond wire is stitch bonded with a stitch bond to the contact.

An apparatus and method for laser welding of ribbons for electrical connections

An apparatus and method are provided for using laser energy in an automated bonding machine to effect laser welding of ribbons and other connectors, particularly conductive ribbons in microelectronic circuits. The apparatus and method allow bonding and connection of microelectronic circuits with discrete heating avoiding heat damage to peripheral microelectronic components. The apparatus and method also allow bonding of flexible materials and low-resistance materials, and are less dependant on substrate and terminal stability in comparison to existing bonding methods. The bonding method leads to decreased apparatus wear in comparison to existing bonding methods.

Semiconductor device and manufacturing method thereof

A kind of corrosion-resistant method of modifying suitable for copper wire

本发明公开了一种适用于铜丝的耐腐蚀改性方法，该改性方法先从原料铜中提取高纯铜，清洗、烘干后与镍、镓、磷钨酸钾、纳米氮化钽共同置于熔炼装置中熔化，经在线除气、脱氧、搅拌，用牵引机组离合式真空上引无氧合金铜杆，随后采用连续挤压机组生产合金铜带坯料，随后经粗拔、镀钯、精拔得到镀钯合金铜丝。利用该方法制备而成的镀钯合金铜丝具有良好的耐腐蚀性能，并且成本较低，能够满足行业的要求，具有良好的应用前景。同时，本发明还公开了该方法所制得的铜丝在集成电路中的应用。

Bonding Wires for Semiconductor Devices

본 발명은 볼 직상부의 와이어 무너짐(리닝) 및 스프링 불량을 억제할 수 있고, 루프의 직선성, 루프 높이의 안정성 등에도 우수하여, 적층 칩 접속, 세선화, 협피치 실장 등의 반도체 실장 기술에도 적응하는 고기능의 본딩 와이어를 제공하는 것을 목적으로 한다. 도전성 금속으로 이루어지는 심재와, 이 심재 위에 심재와는 다른 금속을 주성분으로 하는 표피층을 가진 본딩 와이어로서, 이 표피층의 표면에 있어서의 결정립의 원주 방향의 평균 사이즈 a와, 와이어 축의 수직 단면에 있어서의 이 심재의 결정립의 평균 사이즈 b와의 관계에 대하여, a≤0.7인 반도체 장치용 본딩 와이어이다. INDUSTRIAL APPLICABILITY The present invention can suppress wire collapse (lining) and spring failure in the upper portion of a ball, and is excellent in linearity of loops, stability of loop height, and the like. It is an object of the present invention to provide a high-performance bonding wire that is adapted to. Bonding wire which has a core material which consists of an electroconductive metal, and the skin layer which has a metal other than a core material as a main component on this core material, Comprising: The average size a of the circumferential direction of the crystal grain in the surface of this skin layer, and the vertical cross section of a wire axis It is a bonding wire for semiconductor devices whose a <= 0.7 is about the relationship with the average size b of the crystal grain of this core material. 본딩 와이어, 리닝, 스프링 불량, 루프의 직진성 Bonding wires, linings, bad springs, straightness of loop

Electronic component of a high frequency current suppression type and bonding wire for the same

고주파에서 이용될 때에도 전자기 간섭이 발생하는 것을 방지하기 위하여 고주파 전류를 와전하게 억제할 수 있는 고주파 전류 억제형 전자 부품을 제공하기 위하여, 그리고 상기 전자 부품용 접합 와이어를 제공하기 위하여, 반도체 집적 회로 소자(IC)(17)는 고주파에서 이용시 고속으로 동작하고 소정 수의 단자(19)에는 단자들 자체를 통과하는 고주파 전류를 감쇠시키는 고주파 전류 억제기(21)가 제공된다. 이러한 고주파 전류 억제기(21)는 03 내지 20μm 두께를 가진 박막 필름 자기 물질이며 각각의 단자(19)의 전체 표면상에 배치되는데, 상기 단자의 전체 표면은 반도체 집적 회로 소자(IC)(17)를 장착하기 위한 인쇄회로기판(23)상에 장착될 장착 부분 및 인쇄회로기판(23)상에 배치된 도전성 패턴에 대한 접속 부분을 포함하는 에지를 커버한다. IC(17)를 인쇄회로기판(23)에 장착할 때 땜납(27)에 의하여 상부 단부가 도전성 패턴(17)과 연결될 때, 상기 장착 부분 근처는 몇십 MHz 이하인 사용 주파수 대역에서 전도성을 가진다.

Semiconductor device

Semiconductor device and method of manufacturing the same

本发明提供一种半导体装置及其制造方法，该半导体装置可以抑制在半导体封装体的表面形成电磁屏蔽时，在半导体封装体的外缘产生屏蔽材料的毛边，且抑制半导体封装体的背面的端子间的短路。本实施方式的半导体装置包括基板。半导体芯片配置于基板的第1面上。密封材料被覆半导体芯片。导电膜被覆密封材料的上表面及侧面。在基板的与第1面相反侧的第2面的外缘设置着阶差、斜面或槽。

Semiconductor device

Bonding wire for semiconductor device

본 발명은, 볼부의 형성성, 접합성을 개선하고, 루프 제어성도 양호하고, 웨지 접속의 접합 강도를 높이고, 공업 생산성도 확보하고, 금 와이어보다도 저렴한 구리를 주체로 하는 본딩 와이어를 제공하는 것이며, 구리를 주성분으로 하는 코어재와, 상기 코어재 상에 코어재와 다른 조성의 도전성 금속의 표피층을 갖는 본딩 와이어이며, 상기 표피층의 주성분이 금, 팔라듐, 백금, 로듐, 은 또는 니켈로부터 선택되는 2종 이상이고, 상기 표피층 내에 와이어 직경 방향으로 주성분 금속 또는 구리의 한쪽 또는 양쪽의 농도 구배를 갖는 영역이 존재하는 것을 특징으로 하는 반도체 장치용 본딩 와이어이다. SUMMARY OF THE INVENTION The present invention improves the formability and bonding properties of a ball part, improves loop controllability, improves bonding strength of wedge connection, secures industrial productivity, and provides a bonding wire mainly composed of copper, which is cheaper than gold wire. A bonding wire having a core material mainly composed of copper and a skin layer of a conductive metal having a composition different from that of the core material on the core material, wherein the main component of the skin layer is selected from gold, palladium, platinum, rhodium, silver or nickel. It is a bond wire for semiconductor devices characterized by the above-mentioned, and the area | region which has the density | concentration gradient of one or both of main component metal or copper in a wire diameter direction exists in the said skin layer. 코어재, 본딩 와이어, 볼, 네크부, 피복층 Core material, bonding wire, ball, neck part, coating layer

BVA interposer

一种用于制作中介结构的方法，包括形成键合到第一元件的一个或者多个第一表面的多个接线键合。形成与接线键合的边界表面接触的电介质包封体，该包封体使得相邻的接线键合相互分离。进一步处理包括去除第一元件的至少部分，其中中介结构具有至少通过包封体而相互分离的相对的第一侧和第二侧，并且中介结构具有分别在相对的第一侧和第二侧的分别用于与第一部件和第二部件电连接的第一接触和第二接触，第一接触通过接线键合而与第二接触电连接。

Bond wire for semiconductor device

Bonddraht für eine Halbleitervorrichtung, wobei der Bonddraht aufweist: ein Cu-Legierungskernmaterial; und eine Pd-Überzugschicht, die auf einer Oberfläche des Cu-Legierungskernmaterials ausgebildet ist, wobei der Bonddraht wenigstens ein Element enthält, das aus Ni, Zn, Rh, In, Ir und Pt ausgewählt ist, eine Konzentration der Elemente insgesamt relativ zu dem Gesamtdraht 0,03 Massen-% oder mehr und 2 Massen-% oder weniger beträgt, wenn Kristallorientierungen auf einem Querschnitt des Kernmaterials in einer Richtung senkrecht zu einer Drahtachse des Bonddrahts gemessen werden, eine Kristallorientierung <100> mit einem Winkel von 15 Grad oder weniger zu einer Drahtachsenrichtung einen Anteil von 50% oder mehr an Kristallorientierungen in der Drahtachsenrichtung hat, und eine mittlere Kristallkorngröße in dem Querschnitt des Kernmaterials in der Richtung senkrecht zu der Drahtachse des Bonddrahts 0,9 µm oder mehr und 1,3 µm oder weniger beträgt. Bond wire for a semiconductor device, the bond wire comprising: a Cu alloy core material; and a Pd plating layer formed on a surface of the Cu alloy core material, wherein the bonding wire contains at least one element selected from Ni, Zn, Rh, In, Ir and Pt, a total concentration of the elements relative to the total wire is 0.03 mass% or more and 2 mass% or less, when crystal orientations are measured on a cross section of the core material in a direction perpendicular to a wire axis of the bonding wire, a crystal orientation <100> at an angle of 15 degrees or less to a wire axis direction accounts for 50% or more of crystal orientations in the wire axis direction, and an average crystal grain size in the cross section of the core material in the direction perpendicular to the wire axis of the bonding wire is 0.9 µm or more and 1.3 µm or less.

Stacked package and method of manufacturing the same

본 발명은 적층 패키지 및 그의 제조 방법에 관한 것으로서, 제 1 패키지 기판의 제 1 표면 상에 제 1 반도체 장치를 부착하는 단계; 제 2 패키지 기판의 제 1 표면 상에 몰딩 수지 물질막을 부착하는 단계; 상기 제 1 패키지 기판의 제 1 표면과 상기 제 2 패키지 기판의 제 1 표면이 서로 마주하도록 배열하는 단계; 상기 몰딩 수지 물질막을 리플로우시키면서 상기 제 1 패키지 기판과 상기 제 2 패키지 기판을 압착하는 단계; 및 리플로우된 상기 몰딩 수지 물질막을 경화시키는 단계를 포함하는 적층 패키지의 제조 방법이 제공된다. 본 발명의 제조 방법을 이용하면 신뢰성이 우수한 적층 패키지를 간단하고 신속하게 적층 패키지를 제조할 수 있다.

Power semiconductor device, method for manufacturing same, and bonding wire

The present invention addresses the issue of providing: a power semiconductor device, which can be used without a problem even if heat stress is generated, and which is capable of reducing heat generated by a wire, and is capable of ensuring reliability of a bonding section even under high-temperature environments, at the time when the current capacity of the power semiconductor device is increased and the power semiconductor device is used under high-temperature environments; a method for manufacturing the power semiconductor device; and a bonding wire. In a power semiconductor device (1), a metal electrode (element electrode (3)) and the other metal electrode (connecting electrode (4)), which are on a power semiconductor element (2), are both wedge-connected by means of a metal wire (5). The metal wire (5) is an Ag wire or an Ag alloy wire having a diameter larger than 50 μm but equal to or smaller than 2 mm, and the element electrode (3) has, on the surface thereof, one or more metal layers or alloy layers, each of which has a thickness of 50 Å or more, said metal layers being composed of a metal selected from among Ni, Cr, Cu, Pd, V, Ti, Pt, Zn, Ag, Au, W, and Al, and said alloy layers being composed of metals selected from among such metals. Consequently, irrespective of the fact that the Ag wire is used, reliability of a bonding section to the electrode can be ensured, heat generated by the metal wire can be reduced when a large current is used, and heat resistance at a high temperature is improved.

A DEVICE AND METHOD FOR LASER WELDING OF TAPES FOR ELECTRICAL CONNECTIONS

Semiconductor device

Bonding wire for power module package and method of manufacturing the same

Method for forming stackable semiconductor device packages including openings with conductive bumps of specified geometries

In one embodiment, a manufacturing method includes: (1) applying a first electrically conductive material to an upper surface of a substrate to form first conductive bumps; (2) electrically connecting a semiconductor device to the upper surface of the substrate; (3) applying a molding material to form a molded structure covering the first conductive bumps and the semiconductor device, upper ends of the first conductive bumps being recessed below an upper surface of the molded structure; (4) forming openings adjacent to the upper surface of the molded structure, the openings exposing the upper ends of the first conductive bumps; (5) applying, through the openings, a second electrically conductive material to form second conductive bumps; and (6) forming cutting slits extending through the molded structure and the substrate.

Process for making composite conductors

Wire structure and semiconductor device having the same, and method of manufacturing the wire structure

개시된 와이어 구조체는, 와이어 형상을 가지는 제1 와이어 코어와, 상기 제1 와이어 코어를 둘러싸는 것으로 탄소를 포함하는 제1 카본 셸을 포함하는 제1 와이어; 및 상기 제1 와이어의 길이 방향으로 연장되는 제2 와이어를 포함한다. The disclosed wire structure includes: a first wire including a first wire core having a wire shape and a first carbon shell including carbon as surrounding the first wire core; And a second wire extending in a length direction of the first wire.

Bonding wire for semiconductor device

표면에 Pd 피복층을 갖는 Cu 본딩 와이어에 있어서, 고온 고습 환경에서의 볼 접합부의 접합 신뢰성을 개선하고, 차량 탑재용 디바이스에 적합한 본딩 와이어를 제공한다. Cu 합금 코어재와, 상기 Cu 합금 코어재의 표면에 형성된 Pd 피복층을 갖는 반도체 장치용 본딩 와이어에 있어서, 본딩 와이어가 In을 0.011∼1.2질량％ 포함하고, Pd 피복층의 두께가 0.015∼0.150㎛이다. 이에 의해, 고온 고습 환경하에서의 볼 접합부의 접합 수명을 향상시키고, 접합 신뢰성을 개선할 수 있다. Cu 합금 코어재가 Pt, Pd, Rh, Ni의 1종 이상을 각각 0.05∼1.2질량％ 함유하면, 175℃ 이상의 고온 환경에서의 볼 접합부 신뢰성을 향상시킬 수 있다. 또한, Pd 피복층의 표면에 Au 표피층을 더 형성하면 웨지 접합성이 개선된다. A Cu bonding wire having a Pd coating layer on its surface improves bonding reliability of a ball joint in a high temperature and high humidity environment and provides a bonding wire suitable for a vehicle mounting device. Cu alloy core material and a Pd coating layer formed on the surface of the Cu alloy core material, wherein the bonding wire contains 0.011 to 1.2 mass% of In and the thickness of the Pd coating layer is 0.015 to 0.150 占 퐉. This improves the bonding life of the ball joint in a high temperature and high humidity environment and improves bonding reliability. When the Cu alloy core material contains 0.05 to 1.2 mass% of at least one of Pt, Pd, Rh, and Ni, the reliability of the ball joint in a high temperature environment of 175 캜 or more can be improved. Further, when an Au skin layer is further formed on the surface of the Pd coating layer, the wedge bonding property is improved.

Connection structure of conductor, electronic equipment

The purpose of the present invention is to narrow the connection area on a base body such as a light-emitting device, display device and so forth, to allow for a narrow frame, and thereby to achieve smaller and thinner electronic equipment. Provided are a conductive section (3A) provided on a base body (1), a protective section (3B) to cover the conductive section (3A), and a conductor (5). The conductor (5) is connected to the conductive section (3A) through the protective section (3B) and the conductor (5) is formed of a material that is harder than gold.

Wire bonding structure and method for forming same

Provided is a bonding structure of a bonding wire and a method for forming the same which can solve problems of conventional technologies in practical application of a multilayer copper wire, improve the formability and bonding characteristic of a ball portion, improve the bonding strength of wedge connection, and have a superior industrial productivity. A bonding wire mainly composed of copper, and a concentrated layer where the concentration of a conductive metal other than copper is high is formed at a ball bonded portion. The concentrated layer is formed in the vicinity of the ball bonded portion or at the interface thereof. An area where the concentration of the conductive metal is 0.05 to 20 mol % has a thickness greater than or equal to 0.1 μm, and it is preferable that the concentration of the conductive metal in the concentrated layer should be five times as much as the average concentration of the conductive metal at the ball bonded portion other than the concentrated layer.