Verdrahtungssubstrat

Ein Verdrahtungssubstrat umfasst ein Substrat mit einem Verdrahtungsmuster und ein linienförmiges Isoliermuster, das auf dem Substrat derart gebildet ist, daß es das Verdrahtungsmuster schneidet und einen Teil des Verdrahtungsmusters für eine Anschlußbereichselektrode definiert. Das Isoliermuster umfasst eine Mehrzahl von linienförmigen Abschnitten, die miteinander verbunden sind, um eine rahmenartige Struktur zu bilden.

Flip-chip electronic device with carrier having heat dissipation elements free of solder mask

Flip-chip electronic device with carrier having heat dissipation elements free of solder mask

PROCEDURE FOR the VERSCHWEIßEN OF TWO PARTS WITH THE HELP OF a SOLDERING MATERIAL

Method of manufacturing semiconductor device and semiconductor device

METHOD OF ASSEMBLING A CHIP IN A FLEXIBLE SUBSTRATE.

Method for assembling e.g. two components in face to face manner, involves depositing volume of welding material on surface, where welding material comprises melting point, which is higher than that of another welding material

The method involves producing wetable surface (36) by a welding material on a face of a component (34), which is surrounded by a non-wetable surface by another welding material. Volume (40) of the latter welding material is deposited on the wetable surface, where the latter welding material comprises a melting point, which is higher than a melting point of the former welding material. A heating volume of latter welding material is applied to temperature greater than or equal to temperature at the melting point of latter welding material.

Method for forming the package structure

A method for forming the package structure is provided. The method includes forming a die structure over a first surface of a first substrate, and forming a plurality of electrical connectors below a second surface of the first substrate. The method also includes forming a first protruding structure below the second surface of the first substrate, and the electrical connectors are surrounded by the first protruding structure. The method further includes forming a second protruding structure over a second substrate, and bonding the first substrate to the second substrate. The electrical connectors are surrounded by the second protruding structure, and the first protruding structure does not overlap with the second protruding structure.

Film for flip chip type semiconductor back surface, and its use

Connection components with rows of lead bond sections

A connection component for a microelectronic element includes a sheet-like support structure having top and bottom surfaces which extend in horizontal directions. The support structure includes a central region and a periphery surrounding the central region with terminals mounted on the central region of the support structure and exposed at the top surface thereof. A plurality of leads extend on the support structure with each lead having a terminal section connected to one of the terminals and attached to the bottom surface, a bond region and a horizontally curved section between the bond region and the terminal region. The bond regions of the leads are disposed side-by-side in one or more rows adjacent the periphery of the support structure. After the bond regions of the leads have been bonded to contacts of a microelectronic element, the support structure of the connection component is moveable upwardly so as to bend the curved sections of the leads.

LOW COST PACKAGE WARPAGE SOLUTION

Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.

Using collapse limiter structures between elements to reduce solder bump bridging

Provided are an electronic assembly and method for forming the same, comprising a first element having a first surface and a second element having a second surface. Electrical connections are provided between the first and the second elements formed by heating solder bumps. At least one collapse limiter structure is coupled to at least one of the first and the second surfaces, wherein the at least one collapse limiter structure is between at least two of the electrical connections.

Method of welding two elements together by means of a brazing material

ГИБКО ОБОРАЧИВАЕМЫЙ КРИСТАЛЛ ИНТЕГРАЛЬНОЙ СХЕМЫ

Verfahren zur Herstellung einer integrierten Halbleitereinrichtung

Verfahren zur Herstellung einer integrierten Halbleitereinrichtung, welche einen aus einem ersten Wafer vereinzelten ersten Chip und einen aus einem zweiten Wafer vereinzelten zweiten Chip, deren aktive Flächen einander gegenüberliegen, und eine durch Waferbonden hergestellte elektrische und mechanische Verbindung zwischen den aktiven Flächen des ersten und zweiten Chips aufweist, wobei auf dem ersten und zweiten Wafer jeweils derart metallische Kontaktbereiche gebildet werden, dass diese bei einer geeignet gewählten Übereinander-Positionierung des ersten und zweiten Wafers mit einander zugewandten aktiven Flächen einander gegenüberliegen, der erste und zweite Wafer mit einander zugewandten aktiven Flächen in vorbestimmtem Abstand derart übereinander positioniert und fixiert werden, dass die Kontaktbereiche einander gegenüberliegen, wobei ein Abstandshalter-Muster auf dem ersten und/oder zweiten Wafer ausgebildet wird, und danach der erste und zweite Wafer im miteinander fixierten Zustand ...

METHOD FOR MANUFACTURING ELECTRONIC COMPONENT-MOUNTED BOARD

스택되는 다이들의 위치들을 제어하는 기술

... 조립 부품(100) 및 조립 부품을 이용하여 칩 패키지를 조립하는 기술이 설명된다. 이 칩 패키지는 수직 방향으로 스택 내에 배열되는 반도체 다이들(310-1 내지 310-N)의 세트를 포함하는데, 반도체 다이들은 수직 스택의 일 측에 계단형 테라스(112-1)를 정의하도록 수평 방향에서 서로 오프셋된다. 또한, 칩 패키지는 조립 부품(100)을 이용하여 조립될 수 있다. 특히, 조립 부품은 대략 칩 패키지의 계단형 테라스를 대략 미러링하는 계단형 테라스들(112-1, 112-2)의 쌍을 포함할 수 있고, 이 경사형 테라스들의 쌍은 칩 패키지의 조립 동안 수직 스택으로 반도체 다이들의 세트를 배치하는 조립 도구에 대해 수직 위치 레퍼런스를 제공한다.

3di solder cup

A substrate or semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a solder cup. The semiconductor device assembly includes a substrate disposed over another substrate. At least one solder cup extends from one substrate towards an under bump metal (UBM) on the other substrate. The barrier on the exterior of the solder cup may be a standoff to control a bond line between the substrates. The barrier may reduce solder bridging during the formation of a semiconductor device assembly. The barrier may help to align the solder cup with a UBM when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of substrates and/or semiconductor devices.

Chip package and method for forming the same

A chip package is provided. A first bonding structure is disposed on a first redistribution layer. A first chip includes a sensing region and a conductive pad that are adjacent to an active surface. The first chip is bonded onto the first redistribution layer through the first bonding structure. The first bonding structure is disposed between the conductive pad and the first redistribution layer. The molding layer covers the first redistribution layer and surrounds the first chip. A second redistribution layer is disposed on the molding layer and the first chip. The second redistribution layer is electrically connected to the first redistribution layer. The second chip is stacked on a non-active surface of the first chip. The second chip is electrically connected to the first chip through the second redistribution layer, the first redistribution layer and the first bonding structure. A method of forming the chip package is also provided.

OPTICAL CONNECTION THROUGH SINGLE ASSEMBLY OVERHANG FLIP CHIP OPTICS DIE WITH MICRO STRUCTURE ALIGNMENT

A system includes an optical transceiver assembly, including a flip chip connection of a semiconductor die with a photonic transceiver that overhangs a substrate to which it is to be connected. The assembly further includes an alignment pin that is held to the semiconductor die at a micro-engineered structure in the semiconductor die. The alignment pin provides passive alignment of the photonic transceiver with an optical lens that interfaces the photonic transceiver to one or more optical channels.

STACKING OF MULTIPLE DIES FOR FORMING THREE DIMENSIONAL INTEGRATED CIRCUIT (3DIC) STRUCTURE

Some embodiments of the present disclosure relate to a three dimensional integrated circuit (3DIC) structure. The 3DIC structure has a first die and a second die that is bonded to the first die by one or more bonding structures. The one or more bonding structures respectively have a first metal pad arranged on the first die and a second metal pad arranged on the second die. A first plurality of support structures are disposed between the first die and the second die. The first plurality of support structures include polymers and are laterally spaced apart from a closest one of the one or more bonding structures. The first plurality of support structures extend below an upper surface of the second metal pad.

Film for flip chip type semiconductor back surface and its use

The present invention relates to a film for flip chip type semiconductor back surface, which is to be disposed on a back surface of a semiconductor element flip chip-connected onto an adherend, the film for flip chip type semiconductor back surface including an adhesive layer and a protective layer laminated on the adhesive layer, in which the protective layer is constituted of a heat-resistant resin having a glass transition temperature of 200° C. or more or a metal.

RAMP-STACK CHIP PACKAGE WITH STATIC BENDS

ГИБКО ОБОРАЧИВАЕМЫЙ КРИСТАЛЛ ИНТЕГРАЛЬНОЙ СХЕМЫ

Использование: для создания интегральной схемы. Сущность изобретения заключается в том, что устройство на основе гибко оборачиваемого кристалла интегральной схемы содержит подложку и гибкий кристалл интегральной схемы, соединенный с подложкой по существу в вертикальной ориентации относительно поверхности подложки. Технический результат: обеспечение возможности улучшенного теплоотведения и сохранения компактности. 4 н. и 21 з.п. ф-лы, 8 ил. РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 2 642 170 C2 (51) МПК H01L 23/12 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ ИЗОБРЕТЕНИЯ К ПАТЕНТУ (52) СПК H01L 23/12 (2006.01) (21)(22) Заявка: 2016119458, 19.12.2013 (24) Дата начала отсчета срока действия патента: Дата регистрации: 24.01.2018 (73) Патентообладатель(и): ИНТЕЛ КОРПОРЕЙШН (US) (43) Дата публикации заявки: 23.11.2017 Бюл. № 33 (56) Список документов, цитированных в отчете о поиске: US 20110057284 A1, 10.03.2011. US (45) Опубликовано: 24.01.2018 Бюл. № 3 2011281407 A1, 17.11.2011. US 2010112774 A1, 06.05.2010. JP 2001284564 A, 12.10.2001. (85) Дата начала рассмотрения заявки PCT на национальной фазе: 19.05.2016 (86) Заявка PCT: 2 6 4 2 1 7 0 Приоритет(ы): (22) Дата подачи заявки: 19.12.2013 R U 19.12.2013 (72) Автор(ы): АЛЬБЕРС Свен (DE), СКИННЕР Майкл (US), БАРТ Ганс-Йоахим (DE), БАУМГАРТНЕР Петер (DE), ГОСНЕР Харальд (DE) WO 2015/094259 (25.06.2015) Адрес для переписки: 109012, Москва, ул. Ильинка, 5/2, ООО "Союзпатент" (54) ГИБКО ОБОРАЧИВАЕМЫЙ КРИСТАЛЛ ИНТЕГРАЛЬНОЙ СХЕМЫ (57) Реферат: Использование: для создания интегральной вертикальной ориентации относительно схемы. Сущность изобретения заключается в том, поверхности подложки. Технический результат: что устройство на основе гибко оборачиваемого обеспечение возможности улучшенного кристалла интегральной схемы содержит теплоотведения и сохранения компактности. 4 н. подложку и гибкий кристалл интегральной схемы, и 21 з.п. ф-лы, 8 ил. соединенный с подложкой по существу в R U 2 6 4 2 1 7 0 (87 ...

Semiconductor back is cut with integrated membrane

Method of bonding interposer and integrated circuit chip, and ultrasound probe using the method

제1 및 제2 구성요소들의 조립 후에 금속 커넥터를 도금함으로써 마이크로전자 조립체를 형성하는 방법 및 대응하는 장치

... 마이크로전자 조립체들 및 이의 제조 방법들이 본 명세서에 개시된다. 일 실시예에서, 마이크로전자 조립체의 형성 방법은 제1 및 제2 구성요소(102, 128)들의 제1 주 표면(104, 130)들이 서로 대면하고 사전결정된 간격만큼 서로 이격되도록 제1 및 제2 구성요소(102, 128)들을 조립하는 단계로서, 제1 구성요소(102)는 반대편을 향하는 제1 및 제2 주 표면(104, 106)들, 제1 주 표면(104)과 제2 주 표면(106) 사이에서 제1 방향으로 연장되는 제1 두께, 및 제1 주 표면(104)에 있는 복수의 제1 금속 접속 요소(112)들을 구비하고, 제2 구성요소(128)는 제2 구성요소(128)의 제1 주 표면(130)에 있는 복수의 제2 금속 접속 요소(132)들을 구비하는, 상기 제1 및 제2 구성요소들을 조립하는 단계; 및 이어서 각자의 제1 접속 요소(112)와 각자의 제1 접속 요소(112)의 반대편의 대응하는 제2 접속 요소(132) 사이에서 각각 제1 방향으로 연속적으로 연장되어 접속하는 복수의 금속 커넥터 영역(146)들을 도금(전기 도금 또 무전해 도금)하는 단계를 포함한다. 제1 및 제2 금속 접속 요소(112, 132)들은 구성요소(102, 128)들 내의 금속 비아(116, 134)들 또는 구성요소(102, 128)들의 표면에 있는 금속 패드(118)들을 포함할 수 있는데, 금속 비아(116, 134)들 또는 금속 패드(118)들은 도금 금속 영역(114)들에 의해 덮인다. 제1 시드 층(126)이 도금 공정 전에 제1 구성요소(102)의 주 표면 위에 놓이게 형성될 수 있는데, 여기서 금속 커넥터 영역(146)들을 도금한 후에 제1 시드 층(126)의 덮이지 않은 부분들이 제거된다. 유사하게, 제2 시드 층(144)이 제2 구성요소(128)의 주 표면 위에 놓이게 형성될 수 있다. 복수의 장벽 영역(152)들이 금속 커넥터 영역(146)들, 제1 도금 금속 영역(114)들 또는 제2 도금 금속 영역들 중 적어도 하나의 ...

Low cost package warpage solution

System and method for laser assisted bonding of semiconductor die

A system and method for laser assisted bonding of semiconductor die. As non-limiting examples, various aspects of this disclosure provide systems and methods that enhance or control laser irradiation of a semiconductor die, for example spatially and/or temporally, to improve bonding of the semiconductor die to a substrate.

Interposer, electronic substrate, and method for producing electronic substrate

An interposer is capable of efficiently reinforcing the connecting portion between an electronic component and a substrate. The interposer is used for mounting a first electronic component on a substrate and includes a sheet-shaped spacer having at least one through-hole and including a material that does not flow during reflow soldering and a resin portion that covers at least a part of the spacer and is flowable during reflow soldering, and the through-hole is configured to store a bump of the first electronic component.

MANUFACTURING OF FLIP-CHIP ELECTRONIC DEVICE WITH CARRIER HAVING HEAT DISSIPATION ELEMENTS FREE OF SOLDER MASK

Manufacturing of flip-chip type assemblies is provided, and includes forming one or more contact elements of electrically conductive material on a carrier surface of at least one chip carrier, providing a restrain structure around the contact elements, depositing solder material on the contact elements and/or on one or more terminals of electrically conductive material on a chip surface of at least one integrated circuit chip, and placing the chip with each terminal facing corresponding contact elements. Further, the method includes soldering each terminal to the corresponding contact element by a soldering material, the soldering material being restrained during a soldering of the terminals to the contact elements by the restrain structure, and forming one or more heat dissipation elements of thermally conductive material on the carrier surface for facing the chip surface displaced from the terminals, where the one or more heat dissipation elements are free of any solder mask.

PROTECTIVE LAYER FOR PROTECTING TSV TIPS DURING THERMO-COMPRESSIVE BONDING

A method of protecting through substrate via (TSV) die from bonding damage includes providing a substrate including a plurality of TSV die having a topside including active circuitry, a bottomside, and a plurality of TSVs that include an inner metal core that reaches from the topside to protruding TSV tips that extend out from the bottomside. A protective layer is formed on or applied to the bottomside of the TSV die including between and over the protruding TSV tips. The TSV die is bonded with its topside down onto a workpiece having a workpiece surface and its bottomside up and in contact with a bond head. The protective layer reduces damage from the bonding process including warpage of the TSV die by preventing the bond head from making direct contact to the protruding TSV tips.

Package-on-package semiconductor device

Some embodiments relate to a semiconductor device. The semiconductor device includes a substrate and a first die coupled to a top surface of the substrate. A second die is coupled to a bottom surface of the substrate. A thermal contact pad couples the second die to the bottom surface of the substrate. The thermal contact pad electrically isolates the first die from the second die. A molding compound resides over the substrate and surrounds the first and second dies and the thermal contact pad.

Eine Bondstützstruktur (und zugehöriger Prozess) für Waferstapeln

Bei einigen Ausführungsformen wird ein Verfahren zum Bonden von Halbleiterwafern bereitgestellt. Das Verfahren umfasst das Bilden einer ersten integrierten Schaltung (IC) über einer Zentralregion eines ersten Halbleiterwafers. Eine erste ringförmige Bondstützstruktur wird über einer ringförmigen Umfangsregion des ersten Halbleiterwafers gebildet, wobei die ringförmige Umfangsregion des ersten Halbleiterwafers die Zentralregion des ersten Halbleiterwafers umschließt. Ein zweiter Halbleiterwafer wird derart an den ersten Halbleiterwafer gebondet, dass eine auf dem zweiten Halbleiterwafer angeordnete zweite IC mit der ersten IC elektrisch gekoppelt wird.

Ball grid array solder attachment

Coated electrical assembly

Dicing tape-integrated film for semiconductor back surface

The present invention provides a dicing tape-integrated film for semiconductor back surface including: a dicing tape including a base material and a pressure-sensitive adhesive layer on the base material; and a film for flip chip type semiconductor back surface, which is provided on the pressure-sensitive adhesive layer, in which at least a part of the pressure-sensitive adhesive layer has been cured beforehand by irradiation with a radiation ray.

Method for manufacturing electronic component-mounted board

Adhesive film for a semiconductor device with a body and the back of the cut film for semiconductor

METHOD FOR TRANSFORMING AN ELECTRONIC DEVICE

La présente invention concerne un procédé de transformation d'un dispositif électronique à partir d'un état initial dans lequel le dispositif comprend un premier substrat (100) et un deuxième substrat (300), lesdits premier et deuxième substrats (100, 300) étant solidarisés au moyen d'une interface de collage (800) à partir de leurs premières faces (101, 301) respectives, état initial dans lequel le premier substrat (100) comprend au moins une cavité (120), réalisée à partir de la première face (101) du premier substrat (100), ladite cavité (120) étant bordée d'au moins une zone périphérique (110) et étant remplie au moins partiellement d'une couche tampon (200) dans le fond de la cavité (120), et dans lequel la première face (301) du deuxième substrat (300) est au moins en partie en regard de la cavité (120) du premier substrat (100). Le procédé comprend une étape de retrait du fond de la cavité (120) du premier substrat (100) à partir d'une deuxième face (102), opposée à la première face (101) du premier substrat (100). The present invention relates to a method of transforming an electronic device from an initial state in which the device comprises a first substrate (100) and a second substrate (300), said first and second substrates (100, 300) being secured by means of a bonding interface (800) from their respective first faces (101, 301), initial state in which the first substrate (100) comprises at least one cavity (120), made from the first face (101) of the first substrate (100), said cavity (120) being bordered by at least one peripheral zone (110) and being at least partially filled with a buffer layer (200) in the bottom of the cavity (120) ), and wherein the first face (301) of the second substrate (300) is at least partially facing the cavity (120) of the first substrate (100). The method includes a step of removing the bottom of the cavity (120) of the first substrate (100) from a second face (102), opposite to the first face ( ...

Semiconductor chip and semiconductor package having the same

무-범프 플립칩 인터커넥트 구조 제조용 반도체 소자 및 방법

... 반도체 소자는 접촉 패드를 갖는 기판을 포함한다. 기판 위에 마스크가 배치된다. 기판의 접촉 패드 위에 알루미늄-가용성 전도성 페이스트가 프린팅된다. 알루미늄-가용성 전도성 페이스트 위에 반도체 다이가 배치된다. 알루미늄-가용성 전도성 페이스트가 리플로되어, 상기 기판의 접촉 패드 위에 인터커넥트 구조를 형성한다. 접촉 패드는 알루미늄을 포함한다. 반도체 다이의 접촉 패드는 알루미늄-가용성 전도성 페이스트 위에 배치된다. 알루미늄-가용성 전도성 페이스트는 리플로되어, 반도체 다이의 접촉 패드와 기판의 접촉 패드 사이에 인터커넥트 구조를 형성한다. 인터커넥트 구조는 상기 반도체 다이와 기판의 접촉 패드 바로 위에 형성된다. 반도체 다이의 접촉 패드는 알루미늄-가용성 전도성 페이스트의 리플로에 앞서 식각된다. 에폭시 프리-도트(epoxy pre-dot)가 반도체 다이와 기판 사이의 분리 거리를 유지시킨다.

SEMICONDUCTOR PACKAGES HAVING THROUGH ELECTRODES AND METHODS FOR FABRICATING THE SAME

작은 간극 내의 상호접속 구조체의 국소화된 밀봉

... 장치는 일반적으로 마이크로전자 디바이스에 관한 것이다. 그러한 장치에서, 제1 기판이 제1 표면을 갖고, 제1 표면 상에 제1 상호접속부들이 위치되며, 제2 기판이 제1 표면으로부터 이격되는 제2 표면을 갖고, 제1 표면과 제2 표면 사이에 간극이 있다. 제2 상호접속부들이 제2 표면 상에 위치된다. 제1 상호접속부들의 하부 표면들과 제2 상호접속부들의 상부 표면들이 제1 기판과 제2 기판 사이의 전기 전도성을 위해 서로 결합된다. 전도성 칼라가 제1 및 제2 상호접속부들의 측벽들 주위에 있고, 유전체 층이 전도성 칼라 주위에 있다.

METHOD OF MANUFACTURING ELEMENT CHIP, METHOD OF MANUFACTURING ELECTRONIC COMPONENT-MOUNTED STRUCTURE, AND ELECTRONIC COMPONENT-MOUNTED STRUCTURE

In a plasma processing step that is used in the method of manufacturing the element chip for manufacturing a plurality of element chips by dividing a substrate which has a plurality of element regions and of which an element surface is covered by insulating film, the substrate is divided into element chips by exposing the substrate to a first plasma, element chips having first surface, second surface, and side surface are held spaced from each other on carrier, insulating film is in a state of being exposed, recessed portions are formed by retreating insulating film by exposing element chips to second plasma for ashing, and then recessed portions are covered by protection films by third plasma for formation of the protection film, thereby suppressing creep-up of the conductive material to side surface in the mounting step.

Method for Aligning Micro-Electronic Components

Alignment of a first micro-electronic component to a receiving surface of a second micro-electronic component is realized by a capillary force-induced self-alignment, combined with an electrostatic alignment. The latter is accomplished by providing at least one first electrical conductor line along the periphery of the first component, and at least one second electrical conductor along the periphery of the location on the receiving surface of the second component onto which the component is to be placed. The contact areas surrounded by the conductor lines are covered with a wetting layer. The electrical conductor lines may be embedded in a strip of anti-wetting material that runs along the peripheries to create a wettability contrast. The wettability contrast helps to maintain a drop of alignment liquid between the contact areas so as to obtain self-alignment by capillary force. By applying appropriate charges on the conductor lines, electrostatic self-alignment is realized, which improves the alignment obtained through capillary force and maintains the alignment during evaporation of the liquid. 1. An assembly of at least two components , comprising:a first component and a second component;wherein each of the first component and the second component comprises a contact area covered by a wetting layer;wherein each of the first component and the second component comprises means for containing a liquid on the respective wetting layer;wherein each of the first component and the second component comprises one or more conductor lines running along a circumference of the respective contact area, wherein the one or more conductor lines of the first component are arranged to face the one or more conductor lines of the second component;and wherein at least one of the first component or the second component is provided with means for applying an electrical charge to the respective one or more conductor lines.2. The assembly according to claim 1 , wherein on at least one of ...

Localized sealing of interconnect structures in small gaps

An apparatus relates generally to a microelectronic device. In such an apparatus, a first substrate has a first surface with first interconnects located on the first surface, and a second substrate has a second surface spaced apart from the first surface with a gap between the first surface and the second surface. Second interconnects are located on the second surface. Lower surfaces of the first interconnects and upper surfaces of the second interconnects are coupled to one another for electrical conductivity between the first substrate and the second substrate. A conductive collar is around sidewalls of the first and second interconnects, and a dielectric layer is around the conductive collar.

Low cost package warpage solution

Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.

Method of welding two elements together by means of a brazing material

Ce procédé de soudure ou d'hybridation de deux composants (1,2) entre eux au moyen d'un matériau de brasure, l'un (1) au moins desdits composants, dénommé premier composant, comportant une ou plusieurs pistes métalliques (4) électriquement conductrices, reliées à autant de plots de connexion externes (5), consiste : - à réaliser sur les surfaces en regard des composants à souder ou à hybrider une surface de mouillabilité (7,8) ; - à déposer sur l'une desdites surfaces de mouillabilité une quantité appropriée de matériau de brasure, propre à constituer un plot de soudure ou d'hybridation (6) ; - à déposer un flux de soudure ; - à mettre en contact la surface de mouillabilité (8) de l'autre composant (2) avec le matériau de brasure ainsi déposé ; - puis à élever la température de l'enceinte au sein de laquelle sont positionnés les composants à souder ou à hybrider jusqu'à atteindre au moins la température de fusion du matériau de brasure afin d'assurer la soudure ou l'hybridation effective ...

IMPROVED METHOD FOR PRODUCING A STRUCTURE FOR ASSEMBLING MICROELECTRONIC DEVICES

L'invention concerne la réalisation d'un dispositif microélectronique comprenant un substrat comportant au moins un plot conducteur ledit plot étant doté d'une face inférieure reposant sur le substrat et d'une face supérieure opposée à ladite face inférieure, ladite face supérieure dudit plot étant recouverte d'un empilement formé d'une couche conductrice et d'une couche de protection diélectrique comportant une ouverture dite première ouverture en regard dudit du plot et dévoilant ladite couche conductrice, au moins un bloc isolant (120a, 120b) étant agencé sur une zone périphérique de ladite face supérieure dudit plot, ledit bloc de isolant (120a, 120b) ayant une section transversale formant un contour fermé et comportant une ouverture dite deuxième ouverture, un pilier conducteur (130a, 130b) étant situé au centre dudit contour dans ladite deuxième ouverture. The invention relates to the production of a microelectronic device comprising a substrate comprising at least one conductive pad, said pad being provided with a lower face resting on the substrate and with an upper face opposite to said lower face, said upper face of said being covered with a stack formed of a conductive layer and a dielectric protection layer comprising an opening called the first opening facing said pad and revealing said conductive layer, at least one insulating block (120a, 120b) being arranged on a peripheral zone of said upper face of said pad, said insulating block (120a, 120b) having a cross section forming a closed contour and comprising an opening called a second opening, a conductive pillar (130a, 130b) being located at the center of said contour in said second opening.

ELECTRONIC-COMPONENT MOUNTED BODY, ELECTRONIC COMPONENT, AND CIRCUIT BOARD

METHOD FOR FORMING THE PACKAGE STRUCTURE

Semiconductor device and method for forming a semiconductor device

Technique for controlling positions of stacked dies

Bonded 3D integrated circuit (3DIC) structure

An embodiment bonded integrated circuit (IC) structure includes a first IC structure and a second IC structure bonded to the first IC structure. The first IC structure includes a first bonding layer and a connector. The second IC structure includes a second bonding layer bonded to and contacting the first bonding layer and a contact pad in the second bonding layer. The connector extends past an interface between the first bonding layer and the second bonding layer, and the contact pad contacts a lateral surface and a sidewall of the connector.

Flip-chip method

A flip-chip method includes providing a semiconductor chip and conductive connection pillars. Each of the conductive connection pillars has a first surface and a second surface opposite to the first surface. The flip-chip method also includes fixing the conductive connection pillars on a surface of the semiconductor chip. The first surfaces face the semiconductor chip. The flip-chip method also includes providing a carrier plate, forming solder pillars on the carrier plate, and forming a barrier layer on the carrier plate around the solder pillars. The flip-chip method further includes bringing the solder pillars into contact with the second surfaces of the conductive connection pillars. The conductive connection pillars are located above the solder pillars. The flip-chip method further includes performing a reflow-soldering process on the solder pillars, thereby forming solder layers from the solder pillars.

Electronic device and method of manufacturing electronic device

An electronic device includes: a first electronic component; first members that are provided on a first surface of the first electronic component and that include outside surfaces configured to face diagonally upward with respect to the first surface; a second electronic component provided above the first surface; second members that are provided corresponding to the first members on a second surface of the second electronic component which faces the first surface and that include inside surfaces configured to face diagonally downward with respect to the second surface and configured to face the outside surfaces; and solder that is provided between the first surface and the second surface and that electrically connects the first electronic component and the second electronic component.

METHOD OF FABRICATING A SEMICONDUCTOR DEVICE AND THE SEMICONDUCTOR DEVICE

The device and the method can provide higher productivity.

Halbleiterbauelemente mit einem Glassubstrat und Verfahren zu deren Herstellung

Ein Verfahren zum Herstellen von Halbleiterbauelementen beinhaltet das Bereitstellen eines Stapels mit einem Halbleiterwafer (300) und einem Glassubstrat (200) mit Öffnungen (205) und mindestens einem Graben (206), das an dem Halbleiterwafer (300) angebracht ist. Der Halbleiterwafer (300) weist mehrere Halbleiterbauelemente (310) auf. Die Öffnungen (205) des Glassubstrats (200) lassen jeweilige Bereiche der Halbleiterbauelemente (310) durch das Glassubstrat (200) unbedeckt, und der Graben (206) verbindet die Öffnungen (205). Eine Metallschicht wird mindestens an freiliegenden Wänden des Grabens (206) und den Öffnungen (205) und an den unbedeckten Bereichen der Halbleiterbauelemente (310) des Halbleiterwafers (300) ausgebildet. Ein Metallgebiet wird durch Galvanisieren von Metall in den Öffnungen (205) und dem Graben (206) und durch nachfolgendes Schleifen des Glassubstrats (200), um die Gräben (206) zu entfernen, ausgebildet. Der Stapel des Halbleiterwafers (300) und des angebrachten Glassubstrats ...

Wiring board e.g. for mobile communications device or computer, has insulating pattern formed on substrate, intersecting wiring pattern to define electrode

The wiring board includes a substrate (1) with a wiring pattern (4) and a insulating pattern (8) that is formed on the substrate in such a way that it intersects the wiring pattern and defines part of the wiring pattern as a connection region electrode (7). A further insulating pattern may be formed on the substrate, parallel to the first insulating pattern. Independent claims are included for a method of manufacturing a wiring board, a method of manufacturing a wiring pattern, and an electrical device provided with the wiring board.

Flip-chip electronic device with carrier having heat dissipation elements free of solder mask

TRANSFORMATION METHOD OF AN ELECTRONIC DEVICE

PROCESS OF WELDING OF TWO ELEMENTS BETWEEN THEM BY MEANS OF A MATERIAL OF BRAZING.

PROCESS Of ASSEMBLY Of a CHIP IN a FLEXIBLE SUBSTRATE.

Un substrat muni d'un fil (3) électriquement conducteur enrobé par un matériau électriquement isolant est imprégné par un matériau polymérisable (4). Une zone d'accueil (5) pour une puce (2) est formée sur une surface du substrat (1), par déformation. La zone d'accueil (5) est rigidifiée au moyen du matériau polymérisable (4). La puce (2) est disposée dans la zone d'accueil (5) et une zone (8) de connexion électrique de la puce (2) est connectée électriquement au fil (3) électriquement conducteur du substrat (1).

Method for forming chip package structure

A method for forming a chip package structure is provided. The method includes forming a first conductive bump and a first ring-like structure over a chip. The first ring-like structure surrounds the first conductive bump, the first ring-like structure and the first conductive bump are made of a same first material, the chip includes an interconnect structure, and the first ring-like structure is electrically insulated from the interconnect structure and the first conductive bump. The method includes bonding the chip to a substrate through the first conductive bump.

Stacked semiconductor package and method for making the same

The present invention relates to a stacked semiconductor package and method for making the same. The method includes the steps of: forming and curing a first protective layer to cover the first bumps of a first wafer; cutting the first wafer to form a plurality of first dice; forming and curing a second protective layer to cover the second bumps of a second wafer; sucking the first die through the first protective layer by a bonding head, and bonding the first die to the second wafer; removing the bonding head and removing part of the first protective layer; cutting the second wafer to form a plurality of second dice; forming a third protective layer on a substrate; and bonding the first die and the second die to the substrate. Whereby, the first protective layer can protect the first bumps, and the first protective layer can increase the total thickness and the flatness, which facilitate sucking the first die.

Technique for controlling positions of stacked dies

An assembly component and a technique for assembling a chip package using the assembly component are described. This chip package includes a set of semiconductor dies that are arranged in a stack in a vertical direction, which are offset from each other in a horizontal direction to define a stepped terrace at one side of the vertical stack. Moreover, the chip package may be assembled using the assembly component. In particular, the assembly component may include a pair of stepped terraces that approximately mirror the stepped terrace of the chip package and which provide vertical position references for an assembly tool that positions the set of semiconductor dies in the vertical stack during assembly of the chip package.

Methods for providing a flexible structure and flexible apparatuses

METHOD FOR ASSEMBLING A CHIP IN A FLEXIBLE SUBSTRATE

According to the invention, a substrate, provided with an electrically conductive wire (3) coated with an electrically insulating material, is impregnated with a polymerisable material (4). A reception area (5) for a chip (2) is formed on a surface of the substrate (1) by means of deformation. The reception area (5) is stiffened using the polymerisable material (4). The chip (2) is disposed in the reception area (5) and an electrical connection area (8) of the chip (2) is connected electrically to the electrically conductive wire of the substrate (1).

THREE DIMENSIONAL INTEGRATED CIRCUIT (3DIC) WITH SUPPORT STRUCTURES

The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure has a first conductive layer on a first substrate and a second conductive layer on a second substrate. A bonding structure is disposed between the first conductive layer and the second conductive layer. A support structure is disposed between the first substrate and the second substrate. A passivation layer covers a bottom surface of the first conductive layer and has a lower surface facing an uppermost surface of the support structure.

Chip stack with electrically insulating walls

A method of forming a chip stack is provided and includes arraying solder pads along a plane of a major surface of a substrate forming walls of electrically insulating material between adjacent ones of the solder pads.

Package on package bonding structure and method for forming the same

The described embodiments of mechanisms of forming a die package and package on package (PoP) structure involve forming a solder paste layer over metal balls of external connectors of a die package. The solder paste layer protects the metal balls from oxidation. In addition, the solder paste layer enables solder to solder bonding with another die package. Further, the solder paste layer moves an intermetallic compound (IMC) layer formed between the solder paste layer and the metal balls below a surface of a molding compound of the die package. Having the IMC layer below the surface strengthens the bonding structure between the two die packages.

Wiring substrate

A wiring substrate includes a first insulating layer including a cavity, an electronic component in the cavity, and a second insulating layer on the first insulating layer. The second insulating layer covers the electronic component. A recess having a predetermined volume distribution is formed in an outermost layer of the electronic component that defines a surface of the electronic component facing away from the bottom of the cavity. The width of the gap between the side surface of the electronic component and the inner wall surface of the cavity in a plan view is determined based on the predetermined volume distribution. The second insulating layer is in the recess and the gap.

Verfahren zur Herstellung von Halbleiterbauelementen mit einem Glassubstrat und Halbleiterbauelemente mit Glassubstrat

Verfahren zum Herstellen von Halbleiterbauelementen, wobei das Verfahren umfasst: Bereitstellen eines Stapels, der einen Halbleiterwafer (300) und ein an dem Halbleiterwafer (300) angebrachtes Glassubstrat (200) aufweist, wobei der Halbleiterwafer (300) mehrere Halbleiterbauelemente (310) aufweist, wobei das Glassubstrat (200) mehrere Öffnungen (205, 207) aufweist, die jeweils einen jeweiligen Bereich der Halbleiterbauelemente (310) durch das Glassubstrat (200) unbedeckt lassen, und mindestens einen Graben (206), der auf einer Seite (202) des Glassubstrats (200) ausgebildet ist, die von dem Halbleiterwafer (300) weg weist, und der die Öffnungen (205, 207) verbindet, wobei der mindestens eine Graben (206) eine Tiefe (d3) aufweist, die kleiner ist als eine Dicke (d1) des Glassubstrats (200); Ausbilden einer Metallschicht (410) mindestens auf freiliegenden Wänden des mindestens einen Grabens (206) und der Öffnungen (205, 207) und auf den unbedeckten Bereichen der Halbleiterbauelemente des ...

Ball grid array solder attachment

Reflow Grid Array (RGA) 220 implemented in an interposer device, where the interposer is placed between a motherboard 260 and a ball grid array (BGA) package 205 of an electrical component, the interposer provides a heat source to reflow solder between the interposer and the BGA package. In one embodiment flux is provided to the solder bumps before soldering an electrical component to the RGA (see Figure 11). The interposer may comprise a heater trace 245 which causes reflow of the solder and an electrical connection to an electrical component connected to the BGA. In one embodiment solder bumps are aligned with contacts on the component. The solder may be disposed in gaps in a contact mask on the interposer which correspond do interposer contacts. The solder may be applied using a solder film (see Figures 14A-14C).

Ball grid array solder attachment

Semiconductor device and semiconductor manufacturing process

라미네이팅 장치 및 그를 이용하는 반도체 패키지 제조 방법

... 라미네이팅 장치 및 그를 이용하는 반도체 패키지 제조 방법이 제공된다. 라미네이팅 장치는, 기판이 배치되는 기판 받침대, 기판 받침대 상에, 기판 받침대의 상면과 대향되는 볼록면을 포함하고, 팽창 가능한 가압부, 가압부와 연결되어 가압부에 공기를 주입하는 플레이트, 및 기판과 가압부 사이에 필름을 제공하는 필름 제공부를 포함하고, 가압부는 팽창하면서 기판 상에 필름을 부착시킨다.

FLIP CHIP TYPE SEMICONDUCTOR REAR SURFACE FILM FOR EFFECTIVELY SUPPRESSING BENDING OF A SEMICONDUCTOR DEVICE BEFORE PERFORMING A REFLOW PROCESS, A DICING TAPE INTEGRATED TYPE SEMICONDUCTOR REAR SURFACE FILM, A MANUFACTURING METHOD OF A SEMICONDUCTOR APPARATUS, AND A FLIP CHIP TYPE SEMICONDUCTOR APPARATUS

PURPOSE: A flip chip type semiconductor rear surface film, a dicing tape integrated type semiconductor rear surface film, a manufacturing method of a semiconductor apparatus, and a flip chip type semiconductor apparatus are provided to protect the rear surface of a semiconductor device using the semiconductor rear surface film, thereby preventing bending or damage of a semiconductor device. CONSTITUTION: A dicing tape(3) comprises an adhesive layer(32) arranged on a base material(31). A flip chip type semiconductor rear surface film(2) is arranged on the adhesive layer. The flip chip type semiconductor rear surface film has a film shape. The flip chip type semiconductor rear surface film is arranged only on a region(33) corresponding to a semiconductor wafer attached region. The surface of the semiconductor rear surface film is protected by a separator until the rear surface of a wafer is attached on the surface of the semiconductor rear surface film. COPYRIGHT KIPO 2012 ...

Film for flip chip type semiconductor back surface and its use

The present invention relates to a film for flip chip type semiconductor back surface, which is to be disposed on a back surface of a semiconductor element flip chip-connected onto an adherend, the film for flip chip type semiconductor back surface including an adhesive layer and a protective layer laminated on the adhesive layer, in which the protective layer is constituted of a heat-resistant resin having a glass transition temperature of 200 DEG C or more or a metal.

Reliable device assembly

Microelectronic assemblies and methods for making the same are disclosed herein. In one embodiment, a method of forming a microelectronic assembly comprises assembling first and second components to have first major surfaces of the first and second components facing one another and spaced apart from one another by a predetermined spacing, the first component having first and second oppositely facing major surfaces, a first thickness extending in a first direction between the first and second major surfaces, and a plurality of first metal connection elements at the first major surface, the second component having a plurality of second metal connection elements at the first major surface of the second component; and plating a plurality of metal connector regions each connecting and extending continuously between a respective first connection element and a corresponding second connection element opposite the respective first connection element in the first direction.

RAMP-STACK CHIP PACKAGE WITH STATIC BENDS

A ramp-stack chip package is described. This chip package includes a vertical stack of semiconductor dies or chips that are offset from each other in a horizontal direction, thereby defining a terrace with exposed pads. A high-bandwidth ramp component, which is positioned approximately parallel to the terrace, is electrically and mechanically coupled to the exposed pads. For example, the ramp component may be coupled to the semiconductor dies using: solder, microsprings and/or an anisotropic conducting film. Furthermore, each of the semiconductor dies includes a static bend so that an end segment of each of the semiconductor dies is parallel to the direction and is mechanically coupled to the ramp component. These end segments may facilitate high-bandwidth communication of signals between the chips and the ramp component, for example, via proximity communication.

RELIABLE DEVICE ASSEMBLY

Microelectronic assemblies and methods for making the same are disclosed herein. In one embodiment, a method of forming a microelectronic assembly comprises assembling first and second components to have first major surfaces of the first and second components facing one another and spaced apart from one another by a predetermined spacing, the first component having first and second oppositely-facing major surfaces, a first thickness extending in a first direction between the first and second major surfaces, and a plurality of first metal connection elements at the first major surface, the second component having a plurality of second metal connection elements at the first major surface of the second component; and plating a plurality of metal connector regions each connecting and extending continuously between a respective first connection element and a corresponding second connection element opposite the respective first connection element in the first direction.

Film for flip chip type semiconductor back surface, dicing tape-integrated film for semiconductor back surface, process for producing semiconductor device, and flip chip type semiconductor device

The present invention relates to a film for flip chip type semiconductor back surface to be formed on a back surface of a semiconductor element flip chip-connected onto an adherend, in which the film for flip chip type semiconductor back surface before thermal curing has, at the thermal curing thereof, a volume contraction ratio within a range of 23° C. to 165° C. of 100 ppm/° C. to 400 ppm/° C.

Metal-bump sidewall protection

A method includes forming a metal bump on a top surface of a first package component, forming a solder region on a top surface of the metal bump, forming a protection layer extending on a sidewall of the metal bump, reflowing the solder region to bond the first package component to a second package component, and dispensing an underfill between the first package component and the second package component. The underfill is in contact with the protection layer.

SURFACE-MOUNT COMPONENTS, METHODS OF MANUFACTURE THEREOF, AND MOUNTING METHODS EMPLOYING THE COMPONENTS

A surface-mount electronic component (20) comprises a substrate (2), a contact pad (8) on a first surface (2a) of the substrate (2), and a solder-stop frame (6) surrounding the contact pad (8). The solder-stop frame (6) delimits a solder-reception space (7) designed to receive solder material in contact with an accessible portion of the contact pad (8). During mounting of the surface-mount electronic component (20) on a mounting board (40), the contact pad of the surface-mount electronic component (20) becomes bonded to a landing pad (42) on the mounting board (40) using solder in the solder-reception space (7), whereby there is reduced tilt of the mounted component. The surface-mount component may be pre-bumped, that is, provided with a flat bonding bump in the solder-reception space (7). Methods of manufacture of the surface-mount components, and mounting methods using the surface-mount components are also described.

Flip-chip electronic device with carrier having heat dissipation elements free of solder mask

A solution relating to electronic devices of flip-chip type is proposed. Particularly, an electronic device (200,300;400;700;800) of flip-chip type comprises at least one chip carrier (110;805) having a carrier surface (135;835), the carrier comprising one or more contact elements (140s,140p;740s,740p;840s,840p) of electrically conductive material on the carrier surface, at least one integrated circuit chip (105;705) having a chip surface (120;720), the chip comprising one or more terminals (125s,125p;725s,725p) of electrically conductive material on the chip surface each one facing a corresponding contact element, solder material (150;750) soldering each terminal to the corresponding contact element, and restrain means (210s,210p,310;410sl,410sd,410p;790s,790p;890s,890p) around the contact elements for restraining the solder material during a soldering of the terminals to the contact elements, wherein the carrier comprises one or more heat dissipation elements (205s,205p;785s,785p;885s ...

PROCESS OF WELDING OF TWO ELEMENTS BETWEEN THEM BY MEANS OF A MATERIAL OF BRAZING.

Ce procédé de soudure ou d'hybridation de deux composants (1, 2) entre eux au moyen d'un matériau de brasure, l'un (1) au moins desdits composants, dénommé premier composant, comportant une ou plusieurs pistes métalliques (4) électriquement conductrices, reliées à autant de plots de connexion externes (5), consiste : - à réaliser sur les surfaces en regard des composants à souder ou à hybrider une surface de mouillabilité (7, 8) ; - à déposer sur l'une desdites surfaces de mouillabilité une quantité appropriée de matériau de brasure, propre à constituer un plot de soudure ou d'hybridation (6) ; - à mettre en contact la surface de mouillabilité (8) de l'autre composant (2) avec le matériau de brasure ainsi déposé ; - puis à élever la température de l'enceinte au sein de laquelle sont positionnés les composants à souder ou à hybrider jusqu'à atteindre au moins la température de fusion du matériau de brasure afin d'assurer la soudure ou l'hybridation effective des deux composants entre eux ...

IMPROVED PROCESS FOR PRODUCING A STRUCTURE FOR ASSEMBLING MICROELECTRONIC DEVICES

L'invention concerne la réalisation d'un dispositif microélectronique comprenant un substrat comportant au moins un plot conducteur ledit plot étant doté d'une face inférieure reposant sur le substrat et d'une face supérieure opposée à ladite face inférieure, ladite face supérieure dudit plot étant recouverte d'un empilement formé d'une couche conductrice et d'une couche de protection diélectrique comportant une ouverture dite première ouverture en regard dudit du plot et dévoilant ladite couche conductrice, au moins un bloc isolant (120a, 120b) étant agencé sur une zone périphérique de ladite face supérieure dudit plot, ledit bloc de isolant (120a, 120b) ayant une section transversale formant un contour fermé et comportant une ouverture dite deuxième ouverture, un pilier conducteur (130a, 130b) étant situé au centre dudit contour dans ladite deuxième ouverture.

DUMMY FLIP CHIP BUMPS FOR REDUCING STRESS

DICING TAPE-INTEGRATED FILM FOR A SEMICONDUCTOR BACK SURFACE, CAPABLE OF EFFICIENTLY SUPPRESSING DAMAGE TO A SEMICONDUCTOR CHIP AND CHIPPING AND WARPAGE THEREOF

PURPOSE: A dicing tape-integrated film for a semiconductor back surface is provided to effectively protect a semiconductor wafer or a semiconductor chip by attaching a film for a flip chip type semiconductor backside to the backside of semiconductor wafer or the backside of the semiconductor chip. CONSTITUTION: In a dicing tape-integrated film for a semiconductor back surface, a dicing tape(3) comprises a material(31) and an adhesive layer(32) which is formed on the materials. A film(2) for the flip chip type semiconductor backside is formed on the adhesive layer. The film for the flip chip type semiconductor backside has a laser marking property. A workpiece is attached on the film for the flip chip type semiconductor backside. COPYRIGHT KIPO 2011 ...

플렉시블하게-랩핑된 집적 회로 다이

... 플렉시블하게-랩핑된 집적 회로 다이 디바이스의 실시예들 및 플렉시블하게-랩핑된 집적 회로 다이를 기판에 장착시키는 방법의 실시예들이 개시된다. 플렉시블하게-랩핑된 집적 회로 다이 디바이스는 기판 및 상기 기판의 표면에 대해서 실질적으로 수직하게 배향되게 상기 기판에 연결된 플렉시블한 집적 회로 다이를 포함한다.

3D INTEGRATED CIRCUIT (3DIC) STRUCTURE AND METHOD OF MAKING SAME

The bonded integrated circuit (IC) structure of an embodiment includes a first IC structure and a second IC structure bonded to the first IC structure. The first IC structure includes a first bonding layer and a connector. The second IC structure includes a second bonding layer bonded to the first bonding layer, and a contact pad in the second bonding layer. A connector is extended by passing an interface between the first bonding layer and the second bonding layer. The contact pad touches a lateral surface and a sidewall of the connector. So, power consumption can be reduced. COPYRIGHT KIPO 2016 ...

WARPAGE CONTROL FOR FLEXIBLE SUBSTRATES

Plurality of bonded semiconductor wafers and bonding method thereof

Dicing tape-integrated film for semiconductor back surface

METHOD OF FORMING A MICROELECTRONIC ASSEMBLY BY PLATING METAL CONNECTORS AFTER ASSEMBLYING FIRST AND SECOND COMPONENTS AND CORRESPONDING DEVICE

Microelectronic assemblies and methods for making the same are disclosed herein. In one embodiment, a method of forming a microelectronic assembly comprises: assembling first and second components (102, 128) to have first major surfaces (104, 130) of the first and second components (102, 128) facing one another and spaced apart from one another by a predetermined spacing, the first component (102) having first and second oppositely-facing major surfaces (104, 106), a first thickness extending in a first direction between the first and second major surfaces (104, 106), and a plurality of first metal connection elements (112) at the first major surface (104), the second component (128) having a plurality of second metal connection elements (132) at the first major surface (130) of the second component (128); and then plating (electroplating or electroless plating) a plurality of metal connector regions (146) each connecting and extending continuously between a respective first connection ...

Interconnection of a carrier substrate and a semiconductor device

Solder interconnection for forming connections between an integrated semiconductor device and a carrier substrate is provided. Located on the carrier substrate are electrodes and located between the electrodes and integrated semiconductor device are solder connections that have a relatively low melting point such that when the device is in operation, the solder connection will liquify thereby permitting expansion compensation between the substrate and semiconductor device.

Electronic Device and Method for Manufacturing an Electronic Device

In an embodiment an electronic device includes a carrier board having an upper surface, an electronic chip mounted on the upper surface of the carrier board, the electronic chip having a mounting side facing the upper surface of the carrier board, a flexible mounting layer arranged between the upper surface of the carrier board and the mounting side of the electronic chip, the flexible mounting layer mounting the electronic chip to the carrier board, wherein the mounting side has at least one first region and a second region, and wherein the electronic chip has at least one chip contact element in the first region and at least one connection element arranged on the at least one first region and connecting the at least one chip contact element to the upper surface of the carrier board, wherein the flexible mounting layer separates the second region from the connection element.

Film for flip chip type semiconductor back surface, dicing tape-integrated film for semiconductor back surface, process for producing semiconductor device, and flip chip type semiconductor device

The present invention relates to a film for flip chip type semiconductor back surface to be formed on a back surface of a semiconductor element flip chip-connected onto an adherend, in which the film for flip chip type semiconductor back surface before thermal curing has, at the thermal curing thereof, a volume contraction ratio within a range of 23° C. to 165° C. of 100 ppm/° C. to 400 ppm/° C.

Semiconductor device and method of fabricating the semiconductor device

A semiconductor device includes a first device including a first substrate and a first external connection terminal for connecting outside the first device; a second device stacked on the first device, the second device including a second substrate and a second external connection terminal for connecting outside the second device; an adhesive pattern disposed between the first device and second device, the adhesive pattern disposed in locations other than locations where the first external connection terminal and second external connection terminal are disposed, and the adhesive pattern causing the first device and second device, when stacked, to be spaced apart by a predetermined distance; and a plated layer disposed between and electrically and physically connecting the first external connection terminal and the second external connection terminal.

Adhesive film for semiconductor device, film for backside of flip-chip semiconductor, and dicing tape-integrated film for backside of semiconductor

Provided is an adhesive film for a semiconductor device that is capable of having the same physical properties as these at the time of manufacture even after it is stored for a long time. The adhesive film for a semiconductor device of the present invention contains a thermosetting resin, and in which the amount of reaction heat generated in a temperature range of ±80° C. of a reaction heat peak temperature measured by a differential scanning calorimeter after the adhesive film is stored at 25° C. for 4 weeks is 0.8 to 1 time the amount of reaction heat generated before storage.

Bump Structure and Method of Forming Same

An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal bump on the under bump metallurgy feature, and a substrate trace on a substrate, the substrate trace coupled to the metal bump through a solder joint and intermetallic compounds, a ratio of a first cross sectional area of the intermetallic compounds to a second cross sectional area of the solder joint greater than forty percent.

Metal Bump and Method of Manufacturing Same

An embodiment bump structure includes a contact element formed on a substrate, a passivation layer overlying the substrate, the passivation layer having a passivation opening exposing the contact element a polyimide layer overlying the passivation layer, the polyimide layer having a polyimide opening exposing the contact element an under bump metallurgy (UMB) feature electrically coupled to the contact element, the under bump metallurgy feature having a UBM width, and a copper pillar on the under bump metallurgy feature, a distal end of the copper pillar having a pillar width, the UBM width greater than the pillar width.

Metal-Bump Sidewall Protection

A method includes forming a metal bump on a top surface of a first package component, forming a solder region on a top surface of the metal bump, forming a protection layer extending on a sidewall of the metal bump, reflowing the solder region to bond the first package component to a second package component, and dispensing an underfill between the first package component and the second package component. The underfill is in contact with the protection layer. 1. A package comprising: a dielectric layer;', 'a metal bump protruding beyond the dielectric layer;', 'a solder region over and contacting the metal bump; and', 'a protection layer contacting a sidewall of the metal bump and a surface of the dielectric layer, wherein the protection layer is formed of a dielectric material., 'a first package component comprising2. The package of claim 1 , wherein the protection layer is free from filler particles therein.3. The package of further comprising:a second package component bonded to the first package component; andan underfill contacting the protection layer, wherein the underfill comprises a portion lower than a bottom surface of the metal bump.4. The package of claim 1 , wherein the protection layer is lower than claim 1 , and is spaced apart from claim 1 , the solder region.5. The package of claim 1 , wherein the protection layer and the dielectric layer are formed of a same dielectric material claim 1 , and have a distinguishable interface therebetween.6. The package of claim 1 , wherein the protection layer comprises polyimide claim 1 , polybenzoxazole (PBO) claim 1 , or benzocyclobutene (BCB).7. The package of claim 1 , wherein the first package component comprises an edge claim 1 , and the protection layer is recessed laterally from the edge.8. The package of claim 1 , wherein the first package component further comprises an additional metal bump protruding beyond the dielectric layer claim 1 , and the protection layer comprises:a first portion contacting the ...

Bonding interposer and integrated circuit chip, and ultrasound probe using the same

The method of bonding an interposer and an integrated circuit chip includes preparing an interposer including an insulator and conductive lines each having one end exposed to a first surface of the insulator and another end exposed to a second surface opposite to the first surface; placing a bonding mask on the interposer; forming through-holes on the bonding mask before or after the placing of the bonding mask on the interposer; filling the plurality with a conductive material; and bonding an integrated circuit chip to the bonding mask.

Semiconductor Die Package and Method of Manufacture

In an embodiment, an interposer has a first side, a first integrated circuit device attached to the first side of the interposer with a first set of conductive connectors, each of the first set of conductive connectors having a first height, a first die package attached to the first side of the interposer with a second set of conductive connectors, the second set of conductive connectors including a first conductive connector and a second conductive connector, the first conductive connector having a second height, the second conductive connector having a third height, the third height being different than the second height, a first dummy conductive connector being between the first side of the interposer and the first die package, an underfill disposed beneath the first integrated circuit device and the first die package, and an encapsulant disposed around the first integrated circuit device and the first die package.

SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor package structure includes a first package, a second package over the first package, a plurality of connectors between the first package and the second package and a plurality of baffle structures between the first package and the second package. The second package includes a bonding region and a periphery region surrounding the bonding region. The connectors are disposed in the bonding region to provide electrical connections between the first package and the second package. The baffle structures are disposed in the periphery region and are separated from each other. 1. A semiconductor package structure comprising:a first package;a second package over the first package and comprising a bonding region and a periphery region surrounding the bonding region;a plurality of connectors between the first package and the second package in the bonding region, wherein the plurality of connectors provide electrical connections between the first package and the second package; anda plurality of baffle structures between the first package and the second package, wherein the plurality of baffle structures are in contact with both of the first package and the second package,wherein the plurality of baffle structures are disposed in the periphery region of the second package and are separated from each other.2. The semiconductor package structure of claim 1 , wherein the plurality of baffle structures comprise insulating materials.3. The semiconductor package structure of claim 2 , wherein at least one of the plurality of baffle structures is in contact with one of the plurality of connectors.4. The semiconductor package structure of claim 2 , further comprising an underfill between the first package claim 2 , the second package claim 2 , adjacent connectors claim 2 , and adjacent baffle structures.5. The semiconductor package structure of claim 1 , wherein the plurality of baffle structures comprise conductive materials.6. The semiconductor package structure of ...

CHIP PACKAGE FABRICATION KIT AND CHIP PACKAGE FABRICATING METHOD THEREOF

A chip package fabricating kit includes a metal cover, at least one screw, and at least one screw cap. The metal cover includes a cap portion and at least one leg. The cap portion substantially presses against the BGA package. The leg substantially presses a PCB board that loads the BGA package. The leg forms a concave space with the metal cover for substantially encompassing the BGA package. Each the screw screws through a corresponding leg from top to bottom. Each the screw screws the PCB board at a first side. The screw cap respectively corresponds to the screw and one leg. The screw cap caps and fixes a tail of its corresponding screw for affixing the PCB board. A height of the concave space is dynamically adjusted by adjusting a degree that the screw screws with the screw cap. Such that the concave space substantially clamps the BGA package. 1. A chip package fabricating kit , comprising:a metal cover, comprising:a cap portion, configured to substantially press against at least one ball grid array (BGA) package; andat least one leg, configured to substantially press a printed circuit board (PCB) board that loads the BGA package, and configured to form a concave space with the metal cover for substantially encompassing the at least one BGA package;at least one screw, each of which is configured to screw through a corresponding leg of the metal cover from top to bottom and to screw the PCB board at a first side of said PCB board; andat least one screw cap respectively corresponding to one of the at least one screw and one of the at least one leg of the metal cover, configured to cap and fix a tail of its corresponding screw for affixing the PCB board;wherein a height of the concave space is dynamically adjusted by adjusting a degree that the at least one screw screws with the at least one screw cap, such that the concave space substantially clamps the BGA package.2. The chip package fabricating kit of claim 1 , further comprising:at least one buffer pad ...

FLIP-CHIP ELECTRONIC DEVICE WITH CARRIER HAVING HEAT DISSIPATION ELEMENTS FREE OF SOLDER MASK

A solution relating to electronic devices of flip-chip type is provided, which includes at least one chip carrier having a carrier surface, the carrier(s) including one or more contact elements of electrically conductive material on the carrier surface, at least one integrated circuit chip having a chip surface, the chip(s) including one or more terminals of electrically conductive material on the chip surface each one facing a corresponding contact element, solder material soldering each terminal to the corresponding contact element, and a restrain structure around the contact elements for restraining the solder material during a soldering of the terminals to the contact elements. The carrier includes one or more heat dissipation elements of thermally conductive material on the carrier surface facing the chip surface displaced from the terminals, the dissipation elements being free of any solder mask. 1. An electronic device of a flip-chip type comprising:at least one chip carrier having a carrier surface, the at least one chip carrier comprising one or more contact elements of electrically conductive material on the carrier surface;at least one integrated circuit chip having a chip surface, the at least one integrated circuit chip comprising one or more terminals of electrically conductive material on the chip surface each one facing a corresponding contact element;solder material soldering each terminal to the corresponding contact element, and a restrain structure around the contact elements for restraining the solder material during a soldering of the terminals to the contact elements; andwherein the at least one chip carrier comprises one or more heat dissipation elements of thermally conductive material on the carrier surface facing the chip surface displaced from the terminals, the dissipation elements being free of any solder mask.2. The electronic device according to claim 1 , wherein the contact elements and the dissipation elements are portions of a ...

Apparatus and methods for creating environmentally protective coating for integrated circuit assemblies

Example methods, apparatus, and products for creating an environmentally protective coating for integrated circuit assemblies are described herein. A preform plastic sheet is places over components of an integrated circuit such that during a reflow process, the preform plastic sheet melts to form a conformal coating over components of the integrated circuit assembly.

Method of fabricating a semiconductor device

A semiconductor device and a semiconductor package, the device including a first buffer dielectric layer on a first dielectric layer; a second dielectric layer and a second buffer dielectric layer sequentially disposed on the first buffer dielectric layer, the second buffer dielectric layer being in contact with the first buffer dielectric layer; and a pad interconnection structure that penetrates the first buffer dielectric layer and the second buffer dielectric layer, wherein the pad interconnection structure includes copper and tin.

Warpage Control for Flexible Substrates

A flexible substrate may be provided having a first side and a second side. A device may be electrically coupled to the first side of the flexible substrate through one or more electrical connections. A warpage control device may be attached to the second side flexible substrate. The warpage control device may include an adhesive layer and a rigid layer. The warpage control device may be formed in an area of the second side of the flexible substrate that may be opposite the one or more electrical connections on the first side of the flexible substrate.

Packaging Devices, Packaged Semiconductor Devices, and Packaging Methods

Packaging devices, packaged semiconductor devices, and packaging methods are disclosed. In some embodiments, a packaging device includes a substrate having an integrated circuit die mounting region disposed thereon. Microstructures are disposed proximate a side of the integrated circuit die mounting region of the substrate.

LIGHT-EMITTING ASSEMBLY

A light emitting assembly includes a substrate, an adhesive layer on the substrate, and a plurality of light emitting units on the adhesive layer. Each of the light emitting units includes a first-type semiconductor layer, a second-type semiconductor layer, an active layer disposed between the first-type and second-type semiconductor layers, a first electrode electrically connected to the first-type semiconductor layer, and a second electrode electrically connected to the second-type semiconductor layer. A light emitting apparatus including the light emitting assembly is provided. Methods for making the light emitting assembly and the light emitting apparatus are provided. 1. A light emitting assembly , comprising:a substrate;an adhesive layer disposed on said substrate in a first direction; anda plurality of light emitting units that are disposed on said adhesive layer opposite to said substrate in the first direction, each of said light emitting units including a first-type semiconductor layer, a second-type semiconductor layer, an active layer that is disposed between said first-type and second-type semiconductor layers, a first electrode that is electrically connected to said first-type semiconductor layer, and a second electrode that is electrically connected to said second-type semiconductor layer.2. The light emitting assembly as claimed in claim 1 , wherein said adhesive layer has a thickness that ranges from 5 μm to 500 μm in the first direction.3. The light emitting assembly as claimed in claim 1 , wherein:said adhesive layer has a base portion and a plurality of protrusions that are disposed on said base portion and that are spaced apart from each other; andsaid light emitting units are respectively disposed on said protrusions.4. The light emitting assembly as claimed in claim 3 , wherein:each of said protrusions is a platform having an upper surface; andeach of said light emitting units is in direct contact with said upper surface of a respective one of ...

Bonded assembly and display device including the same

A bonded assembly including: a first electronic component including a first substrate and a plurality of first electrodes disposed in a pressed area at a first height from a surface of the first substrate; a second electronic component including a second substrate and a plurality of second electrodes disposed at a second height from a surface of the second substrate, a second electrode overlapping with a corresponding first electrode to face the first electrode; a conductive bonding layer disposed between the first electrode and the second electrode overlapped with each other to bond the first electrode and the second electrode; and at least one spacer disposed between the first substrate and the second substrate to overlap the pressed area, the at least one spacer having a thickness that is greater than a value obtained by summing the first height and the second height.

MICRO-SELECTIVE SINTERING LASER SYSTEMS AND METHODS THEREOF

A microscale selective laser sintering (μ-SLS) that improves the minimum feature-size resolution of metal additively manufactured parts by up to two orders of magnitude, while still maintaining the throughput of traditional additive manufacturing processes. The microscale selective laser sintering includes, in some embodiments, ultra-fast lasers, a micro-mirror based optical system, nanoscale powders, and a precision spreader mechanism. The micro-SLS system is capable of achieving build rates of at least 1 cm/hr while achieving a feature-size resolution of approximately 1 μm. In some embodiments, the exemplified systems and methods facilitate a direct write, microscale selective laser sintering μ-SLS system that is configured to write 3D metal structures having features sizes down to approximately 1 μm scale on rigid or flexible substrates. The exemplified systems and methods may operate on a variety of material including, for example, polymers, dielectrics, semiconductors, and metals. 1. A system for additively producing a three-dimensional workpiece , the system comprising:an electromagnetic radiation source configured to coherently and intermittently emit an electromagnetic radiation beam; anda lens assembly having a plurality of micro-mirrors, collectively, forming a matrixed mirror array, each micro-mirror being configured to selectively direct the emitted electromagnetic radiation beam to a focus point on a sintering plane comprising a layer of particles to form one or a plurality of sintered layers, wherein each sintered layer is successively produced, in a layer-by-layer manner, to form the three-dimensional workpiece.2. The system of claim 1 , wherein the plurality of micro-mirrors direct the plurality of emitted electromagnetic radiation beams onto an area spanning a maximum cross-sectional profile of the three-dimensional workpiece.3. The system of claim 1 , comprising:a slot die coater, the slot die coater being configured to dispense a solvent having ...

FLEXIBLE DISPLAY PANEL AND PREPARATION METHOD THEREOF, FLEXIBLE DISPLAY DEVICE

A flexible display panel, a preparation method thereof and a flexible display device are provided. The flexible display panel includes a flexible substrate; a back protective film arranged on a back surface of the flexible substrate; an adhesive layer arranged between the flexible substrate and the back protective film; and a support structure arranged in the adhesive layer between the flexible substrate and the back protective film and in a position corresponding to each of integrated circuit bumps, the support structure being configured to support the integrated circuit bumps in the adhesive layer. 1. A flexible display panel , comprising a flexible substrate;a back protective film arranged on a back surface of the flexible substrate;an adhesive layer between the flexible substrate and the back protective film;a support structure arranged in the adhesive layer between the flexible substrate and the back protective film and in a position corresponding to each of integrated circuit bumps, the support structure being configured to support the integrated circuit bump in the adhesive layer.2. The flexible display panel according to claim 1 , wherein the support structure is a supporting bar.3. The flexible display panel according to claim 2 , wherein a plurality of the supporting bars are arranged corresponding to each of the integrated circuit bumps claim 2 , the plurality of the supporting bars being arranged in parallel substantially.4. The flexible display panel according to claim 2 , wherein a plurality of the supporting bars are arranged corresponding to each of the integrated circuit bumps claim 2 , the plurality of the supporting bars being intersected with each other to form a grid structure.5. The flexible display panel according to claim 2 , wherein a plurality of the integrated circuit bumps are arranged along a pattern separately claim 2 , and the supporting bars are arranged along the pattern.6. The flexible display panel according to claim 5 , wherein ...

Crystal controlled oscillator

A crystal controlled oscillator is provided and includes a ceramic package, a plurality of metal patterns on the substrate, an IC chip, and an alumina coating portion. The ceramic package includes a substrate therein. The metal pattern includes a pad region and a wiring region. The IC chip oscillates a crystal resonator. The alumina coating portion covers the pad regions of the plurality of metal patterns. The alumina coating portion includes openings for mounting solders corresponding to the pad regions. The opening of the alumina coating portion is formed in a shape having a size to be placed within the pad region, even if a print displacement of the metal pattern occurs.

CONDUCTIVE CONTACTS HAVING VARYING WIDTHS AND METHOD OF MANUFACTURING SAME

A bump structure includes a contact element formed on a substrate and a passivation layer overlying the substrate. The passivation layer includes a passivation opening exposing the contact element. The bump structure also includes a polyimide layer overlying the passivation layer and an under bump metallurgy (UBM) feature electrically coupled to the contact element. The polyimide layer has a polyimide opening exposing the contact element, and the under bump metallurgy feature has a UBM width. The bump structure further includes a copper pillar on the under bump metallurgy feature. A distal end of the copper pillar has a pillar width, and the UBM width is greater than the pillar width. 1. A method comprising:forming a contact element over a substrate;forming one or more insulating layers over the contact element;patterning an opening in the one or more insulating layers to expose the contact element;electrically coupling an under bump metallurgy (UBM) feature with the contact element; andforming a conductive pillar on an opposing side of the UBM feature as the contact element, wherein the conductive pillar continuously decreases in diameter from a top surface of the UBM feature to a top surface of the conductive pillar, and wherein sidewalls of the conductive pillar are non-perpendicular to a major surface of the substrate.2. The method of further comprising disposing a solder joint on the top surface of the conductive pillar.3. The method of further comprising bonding the solder joint to a substrate trace of a semiconductor device.4. The method of claim 2 , wherein a distance between the conductive pillar and an adjacent conductive pillar measured at the UBM feature is less than a distance between the conductive pillar and the adjacent conductive pillar measured at a surface of the conductive pillar distal to the UBM feature.5. The method of claim 1 , wherein electrically coupling the UBM feature comprises disposing at least a portion of the UBM feature in the ...

3DI Solder Cup

A substrate or semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a solder cup. The semiconductor device assembly includes a substrate disposed over another substrate. At least one solder cup extends from one substrate towards an under bump metal (UBM) on the other substrate. The barrier on the exterior of the solder cup may be a standoff to control a bond line between the substrates. The barrier may reduce solder bridging during the formation of a semiconductor device assembly. The barrier may help to align the solder cup with a UBM when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of substrates and/or semiconductor devices. 1. A device comprising:a substrate;an electrical interconnect within the substrate;a barrier structure electrically connected to the electrical interconnect, the barrier structure having a funnel-shaped recess defined therein; andsolder positioned within the funnel-shaped recess of the barrier structure.2. The device of claim 1 , further comprising:a copper structure positioned within the funnel-shaped recess of the barrier structure; anda nickel structure positioned within the funnel-shaped recess of the barrier structure.3. The device of claim 1 , wherein the barrier structure comprises tantalum claim 1 , tungsten claim 1 , titanium nitride claim 1 , or combinations thereof.4. The device of claim 1 , further comprising:a semiconductor device having a via and an under bump metal (UBM) electrically connected to the via, and wherein the UBM is encased in the solder within the funnel-shaped recess of the barrier structure.5. The device of claim 4 , wherein the UBM includes angled sidewalls.6. The device of claim 5 , wherein the angled sidewalls of the UBM are configured to produce a wetting force between the substrate and the semiconductor device during thermal compression bonding.7. The device of claim 4 , wherein the ...

Dicing tape-integrated film for semiconductor back surface

The present invention provides a dicing tape-integrated film for semiconductor back surface, which includes: a dicing tape including a base material and a pressure-sensitive adhesive layer provided on the base material; and a film for flip chip type semiconductor back surface provided on the pressure-sensitive adhesive layer, in which a peel force (temperature: 23° C., peeling angle: 180°, tensile rate: 300 mm/min) between the pressure-sensitive adhesive layer of the dicing tape and the film for flip chip type semiconductor back surface is from 0.05 N/20 mm to 1.5 N/20 mm.

Semiconductor package assembly

The invention provides a semiconductor package assembly. The semiconductor package assembly includes a core substrate formed of a first material having a device-attach surface and a solder-bump-attach surface opposite to the die-attach surface. A bump pad is disposed on the bump-attach surface. A first solder mask layer formed of the first material covers the bump-attach surface of the core substrate and a portion of the bump pad. A second solder mask layer covers the device-attach surface of the core substrate, wherein the second solder mask layer is formed of a second material.

Method for Bonding of Group III-Nitride Device-on-Silicon and Devices Obtained Thereof

A method for flip chip bonding a GaN device formed on a silicon substrate is described. The method includes providing a silicon substrate having a GaN device thereon, the GaN device comprising at least one gallium-nitride layer near the silicon substrate and remote from the silicon substrate a dielectric layer comprising at least one via configured to electrically contact the at least one gallium-nitride layer, forming a stiffener layer over the GaN device leaving the at least one via exposed, flip chip bonding the GaN device to a submount, wherein the stiffener layer physically contacts the submount and the submount is electrically connected to the at least gallium-nitride layer through the via, and completely removing the silicon substrate exposing the GaN device. Preferably, the material of the stiffener layer comprises silicon, such as silicon, silicon-germanium, or silicon-carbide.

METHOD OF MANUFACTURING SUBSTRATE STRUCTURE WITH FILLING MATERIAL FORMED IN CONCAVE PORTION

Provided is a substrate structure including a substrate body, electrical contact pads and an insulating protection layer disposed on the substrate body, wherein the insulating protection layer has openings exposing the electrical contact pads, and at least one of the electrical contact pads has at least a concave portion filled with a filling material to prevent solder material from permeating along surfaces of the insulating protection layer and the electric contact pads, thereby eliminating the phenomenon of solder extrusion. Thus, bridging in the substrate structure can be eliminated even when the bump pitch between two adjacent electrical contact pads is small. As a result, short circuits can be prevented, and production yield can be increased. 113-. (canceled)14: A method for manufacturing a substrate structure , comprising:providing a substrate body including a plurality of electrical contact pads;forming an insulating protection layer on the substrate body and the electrical contact pads, wherein the insulating protection layer includes a plurality of openings exposing the electrical contact pads;forming at least one hole on the insulating protection layer, the hole extending into at least one of the electrical contact pads to form at least one concave portion on the electrical contact pad; andforming a filling material in the concave portion.15: The method of claim 14 , wherein the filling material is further formed in the concave portion.16: A method for manufacturing a substrate structure claim 14 , comprising:providing a substrate body including a plurality of electrical contact pads, wherein at least one of the electrical contact pads includes at least one concave portion; andforming an insulating protection layer on the substrate body, and forming a filling material in the concave portion, wherein the insulating protection layer includes a plurality of openings exposing the electrical contact pads.17: The method of claim 16 , wherein the concave portion ...

Semiconductor packages

A semiconductor package includes a first substrate, a first flow channel and a second flow channel. The first flow channel is on the first substrate. The second flow channel is on the first substrate and in fluid communication with the first flow channel. The second flow channel is spaced from an inlet and an outlet of the first flow channel. The first flow channel and the second flow channel constitute a bonding region of the first substrate.

Semiconductor device and semiconductor package including the same

A semiconductor device and a semiconductor package, the device including a first buffer dielectric layer on a first dielectric layer; a second dielectric layer and a second buffer dielectric layer sequentially disposed on the first buffer dielectric layer, the second buffer dielectric layer being in contact with the first buffer dielectric layer; and a pad interconnection structure that penetrates the first buffer dielectric layer and the second buffer dielectric layer, wherein the pad interconnection structure includes copper and tin.

SEMICONDUCTOR CHIP, ELECTRONIC DEVICE HAVING THE SAME AND METHOD OF CONNECTING SEMICONDUCTOR CHIP TO ELECTRONIC DEVICE

Provided herein may be an electronic device. The electronic device may include a substrate provided with a plurality of connecting pads including a first metal, a semiconductor chip on an area of the substrate, facing the connecting pads, and including a base substrate including a first surface facing the substrate, and a second surface opposite the first surface, a plurality of connecting terminals on the first surface, facing the connecting pads, and including a second metal, and a non-adhesive polymer layer on the second surface, and a conductive joining layer electrically connecting, and interposed between, respective ones of the connecting pads to the connecting terminals, and including a diffusion layer in which the first metal and the second metal are mixed. 1. An electronic device comprising:a substrate provided with a plurality of connecting pads comprising a first metal; a base substrate comprising a first surface facing the substrate, and a second surface opposite the first surface;', 'a plurality of connecting terminals on the first surface, facing the connecting pads, and comprising a second metal; and', 'a non-adhesive polymer layer on the second surface; and, 'a semiconductor chip on an area of the substrate, facing the connecting pads, and comprisinga conductive joining layer electrically connecting, and interposed between, respective ones of the connecting pads to the connecting terminals, and comprising a diffusion layer in which the first metal and the second metal are mixed.2. The electronic device of claim 1 , wherein the polymer layer comprises at least one of silicon sealant claim 1 , photocurable resin claim 1 , polydimethylsiloxane and polyurethane.3. The electronic device of claim 1 , wherein the polymer layer comprises insulating material that is softer than material of the base substrate.4. The electronic device of provided with a display panel comprising the substrate.5. The electronic device of claim 4 , wherein the polymer layer ...

Chip stack with electrically insulating walls

A chip stack is provided and includes two or more chips, a solder joint operably disposed between adjacent ones of the two or more chips, the solder joint occupying about 25-30% or more of an area of the chip stack and insulating walls disposed on at least one of the two or more chips to separate the solder joint from an adjacent solder joint.

PRINTING MODULE, PRINTING METHOD AND SYSTEM OF FORMING A PRINTED STRUCTURE

A printing module, printing method and system of forming a printed structure are provided. The printing module includes a first printing dispenser operable to dispense a first material, a second printing dispenser operable to dispense a second material, a first curing unit, a second curing unit and a third curing unit. The first, the second and the third curing units each is operable to irradiate a light capable of curing the first and second materials and are alternately arranged with the first and second printing dispensers along a line. The first and second printing dispensers and the first, second and third curing units are simultaneously movable along the line. During the second curing unit and one of the first curing unit and the third curing unit are operable to irradiate the light, the other of the first curing unit and the third curing unit is off. 1. A printing module , comprising:a first printing dispenser operable to dispense a first material;a second printing dispenser operable to dispense a second material; anda first curing unit, a second curing unit and a third curing unit each being operable to irradiate a light capable of curing the first and second materials, wherein the first, second and third curing units are alternately arranged with the first and second printing dispensers along a line, the first printing dispenser is sandwiched between the first and second curing units, and the second printing dispenser is sandwiched between the second and third curing units,wherein the first and second printing dispensers and the first, second and third curing units are simultaneously movable along the line, andwherein during the second curing unit and one of the first curing unit and the third curing unit are operable to irradiate the light, the other of the first curing unit and the third curing unit is off.2. The printing module of claim 1 , wherein when the printing module moves in a first direction along the line claim 1 , the first curing unit is off ...

DISPLAY DEVICE AND METHOD FOR MANUFACTURING DISPLAY DEVICE

A display panel comprising a display substrate having a display area and a pad area disposed around the display area. A connection wire is disposed on the pad area of the display substrate. A signal wire is disposed on the connection wire. A supporter is disposed between the display substrate and the connection wire. The connection wire directly contacts the supporter. 1. A display panel comprising:a display substrate having a display area and a pad area disposed around the display area;a connection wire disposed on the pad area of the display substrate;a signal wire disposed on the connection wire; anda supporter disposed between the display substrate and the connection wire,wherein the connection wire directly contacts the supporter.2. The display panel of claim 1 , wherein:a planar size of the connection wire is greater than a planar size of the supporter; andthe connection wire covers the supporter.3. The display panel of claim 2 , wherein:a planar size of the signal wire is greater than the planar size of the connection wire; andthe signal wire directly contacts the connection wire.4. The display panel of claim 1 , further comprising an insulating layer disposed between the display substrate and the signal wire claim 1 ,wherein the insulating layer covers a side surface of the connection wire and exposes an upper surface thereof.5. The display panel of claim 4 , wherein the signal wire directly contacts an upper surface of the insulating layer.6. The display panel of claim 1 , wherein a cross-sectional shape of the supporter includes a trapezoidal shape claim 1 , a triangular shape claim 1 , a pentagonal shape claim 1 , a semicircular shape claim 1 , a semi-elliptical shape claim 1 , and/or a quadrangular shape.7. The display panel of claim 1 , wherein the supporter includes a plurality of patterns extending along a long-side direction of the signal wire andspaced apart from each other along a short-side direction of the signal wire.8. The display panel of ...

3DI Solder Cup

A substrate or semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a solder cup. The semiconductor device assembly includes a substrate disposed over another substrate. At least one solder cup extends from one substrate towards an under bump metal (UBM) on the other substrate. The barrier on the exterior of the solder cup may be a standoff to control a bond line between the substrates. The barrier may reduce solder bridging during the formation of a semiconductor device assembly. The barrier may help to align the solder cup with a UBM when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of substrates and/or semiconductor devices. 1. (canceled)2. The assembly of claim 8 , wherein the solder cup and UBM form an interconnect that electrically connects the first substrate and the second substrate.3. The assembly of claim 2 , wherein the first substrate further comprises a first semiconductor device and the second substrate further comprises a second semiconductor device.4. The assembly of claim 3 , wherein the second end of the barrier engages the first surface of the first semiconductor device and supports the second semiconductor device.5. (canceled)6. The assembly of claim 8 , wherein the second end of the barrier surrounds the UBM.7. (canceled)8. A semiconductor device assembly comprising:a first substrate having a first surface and a second surface opposite the first surface, the first surface having at least one under bump metal (UBM) disposed thereon;a second substrate having a first surface and a second surface opposite the first surface, the second substrate disposed over the first substrate, the second substrate having at least one solder cup on the second surface, the at least one solder cup comprising a barrier having a first end proximal to the second surface of the second substrate and a second end distal to the second surface of ...

Method for 3D Ink Jet TCB Interconnect Control

A semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a pillar. The semiconductor device assembly includes a semiconductor device disposed over another semiconductor device. At least one pillar extends from one semiconductor device towards a pad on the other semiconductor device. The barrier on the exterior of the pillar may be a standoff to control a bond line between the semiconductor devices. The barrier may reduce solder bridging and may prevent reliability and electromigration issues that can result from the IMC formation between the solder and copper portions of a pillar. The barrier may help align the pillar with a pad when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of the semiconductor devices. Windows or slots in the barrier may permit the expansion of solder in predetermined directions while preventing bridging in other directions. 2. (canceled)3. The semiconductor device assembly of claim 1 , wherein the at least one pillar extends towards a pad positioned over a trace on the first substrate.4. The semiconductor device assembly of claim 1 , wherein the first end of the barrier is positioned adjacent to the second substrate and the second end of the barrier is located a first distance from the second substrate and wherein a plurality of slots of the castellated second end of the barrier are located a second distance from the second substrate claim 1 , the second distance being less than the first distance.5. The semiconductor device assembly of claim 4 , wherein the plurality of slots are configured to permit expansion of solder in a first plurality of directions.6. The semiconductor device assembly of claim 5 , wherein the barrier is configured to prevent expansion of solder in a second plurality of directions.7. The semiconductor device assembly of claim 1 , wherein at least a portion of the barrier extends from a second ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor chip includes a chip body and a plurality of solder-including electrodes provided on an element-formation surface of the chip body. A packaging substrate includes a substrate body, and one or more conductive layers and a solder resist layer that are provided on a front surface of the substrate body. The solder resist layer is provided as a continuous layer on the front surface of the substrate body and the one or more conductive layers, and has one or more apertures on each of the one or more conductive layers. The plurality of solder-including electrodes include two or more first electrodes having a same function other than a function of power supply. The one or more conductive layers include a continuous first conductive layer. The two or more first electrodes are connected to the continuous first conductive layer. The one or more apertures are confronted with the respective two or more first electrodes. 1. A semiconductor device , comprising:a semiconductor chip; anda packaging substrate on which the semiconductor chip is mounted,wherein the semiconductor chip includes a chip body and a plurality of solder-including electrodes provided on an element-formation surface of the chip body,the packaging substrate includes a substrate body, one or more conductive layers, and a solder resist layer, the one or more conductive layers and the solder resist layer being provided on a front surface of the substrate body,the solder resist layer is provided as a continuous layer on the front surface of the substrate body and the one or more conductive layers, and has one or more apertures on each of the one or more conductive layers,the plurality of solder-including electrodes include two or more first electrodes having a same function other than a function of power supply,the one or more conductive layers include a continuous first conductive layer,the two or more first electrodes are connected to the continuous first conductive layer, andthe one or more ...

DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME

A display device includes a drive circuit on an insulating substrate; a connecting electrode electrically connected to the drive circuit; an LED element electrically connected to the drive circuit via the connecting electrode, and a first light reflecting layer overlapping the LED element and having an inclined surface. The inclined surface reflects light incident on the inclined surface through the LED element toward the connecting electrode. The first light reflecting layer may have a reflectance of 90 percent or more for light at a wavelength of 1.0 μm or more to 1.5 μm or less. 1. A display device comprising:a drive circuit on an insulating substrate;a connecting electrode electrically connected to the drive circuit;an LED element electrically connected to the drive circuit via the connecting electrode, anda first light reflecting layer overlapping the LED element and having an inclined surface.2. The display device according to claim 1 , whereinthe inclined surface reflects light incident on the inclined surface through the LED element toward the connecting electrode.3. The display device according to claim 1 , whereinthe first light reflecting layer has a reflectance of 90 percent or more for light at a wavelength of 1.0 μm or more to 1.5 μm or less.4. The display device according to claim 1 , whereinthe first light reflecting layer has a metal layer containing gold, silver, copper, or aluminum.5. The display device according to claim 4 , whereinthe first light reflecting layer has a first metal layer and a second metal layer covering the first metal layer, andthe second metal layer is a metal layer containing gold, silver, copper, or aluminum.6. The display device according to claim 1 , further comprising:A second light reflecting layer located at a distance from the first light reflecting layer, whereinthe connecting electrode is located between the first light reflecting layer and the second light reflecting layer in a plan view.7. The display device ...

LOW PROFILE REINFORCED PACKAGE-ON-PACKAGE SEMICONDUCTOR DEVICE

The present disclosure provides semiconductor packages and methods for fabricating PoP semiconductor packages. The PoP semiconductor package may comprise a first semiconductor package, the first semiconductor package comprising an anodized metal lid structure comprising (i) a central cavity having a central cavity opening direction and (ii) at least one perimeter cavity having a perimeter cavity opening direction facing in an opposite direction of the central cavity opening direction, a first semiconductor device arranged in the central cavity of the anodized metal lid structure, a redistribution layer electrically coupled to the first semiconductor device, wherein a conductive trace formed in the redistribution layer is exposed to the at least one perimeter cavity, and solder material arranged in the at least one perimeter cavity, and a second semiconductor package, the second semiconductor package comprising at least one conductive post, wherein the at least one conductive post is electrically coupled to the solder material arranged in the at least one perimeter cavity. 1. A package-on-package (PoP) semiconductor device , comprising: an anodized metal lid structure comprising (i) a central cavity having a central cavity opening direction and (ii) at least one perimeter cavity having a perimeter cavity opening direction facing in an opposite direction of the central cavity opening direction;', 'a first semiconductor device arranged in the central cavity of the anodized metal lid structure;', 'a redistribution layer electrically coupled to the first semiconductor device, wherein a conductive trace formed in the redistribution layer is exposed to the at least one perimeter cavity; and', 'solder material arranged in the at least one perimeter cavity; and, 'a first semiconductor package, the first semiconductor package comprisinga second semiconductor package, the second semiconductor package comprising at least one conductive post, wherein the at least one conductive ...

Stacked device and method of manufacturing the same

A stacked device encompasses a lower chip including a plurality of wiring lands and a plurality of wall-block patterns, each of the wall-block patterns is allocated at a position except locations where the wiring lands are disposed, each of the wall-block patterns has a inclined plane, a height of each of the wall-block patterns measured from a reference plane of the array of the wiring lands is higher than the wiring lands, and an upper chip including a plurality of wiring bumps assigned correspondingly to the positions of the wiring lands, respectively, and a plurality of cone bumps assigned correspondingly to the positions of the wall-block patterns, respectively.

Method for manufacturing electronic component

A manufacturing method comprises preparing a bonding substrate having bumps thereon; preparing a mounted member having external conductive members; applying a fixing material to the surface of the bonding substrate and/or to a surface of the mounted member; and fixing the bonding substrate and the mounted member with the fixing material such that the bumps contact the external conductive members. The fixing material is prepared to contain a first compound and a second compound, each having respective viscosities which change depending on their respective temperature profiles; and applying the fixing material to the bonding substrate and/or the mounted member at a temperature lower than a first temperature, and the fixing comprises pressing the bonding substrate against the mounted member when the fixing material has a temperature lower than the first temperature; and heating the fixing material to a temperature higher than the second temperature and curing the fixed material.

3DI Solder Cup

A substrate or semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a solder cup. The semiconductor device assembly includes a substrate disposed over another substrate. At least one solder cup extends from one substrate towards an under bump metal (UBM) on the other substrate. The barrier on the exterior of the solder cup may be a standoff to control a bond line between the substrates. The barrier may reduce solder bridging during the formation of a semiconductor device assembly. The barrier may help to align the solder cup with a UBM when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of substrates and/or semiconductor devices.

ELECTRONIC-PART-REINFORCING THERMOSETTING RESIN COMPOSITION, SEMICONDUCTOR DEVICE, AND METHOD FOR FABRICATING THE SEMICONDUCTOR DEVICE

An electronic-part-reinforcing thermosetting resin composition has: a viscosity of 5 Pa·s or less at 140° C.; a temperature of 150° C. to 170° C. as a temperature corresponding to a maximum peak of an exothermic curve representing a curing reaction; and a difference of 20° C. or less between the temperature corresponding to the maximum peak and a temperature corresponding to one half of the height of the maximum peak in a temperature rising range of the exothermic curve. 1. An electronic-part-reinforcing thermosetting resin composition having:a viscosity of 5 Pa·s or less at 140° C.;a temperature of 150° C. to 170° C. as a temperature corresponding to a maximum peak of an exothermic curve representing a curing reaction; anda difference of 20° C. or less between the temperature corresponding to the maximum peak and a temperature corresponding to one half of the height of the maximum peak in a temperature rising range of the exothermic curve.2. The electronic-part-reinforcing thermosetting resin composition of claim 1 , whereinthe temperature corresponding to one half of the height of the maximum peak in the temperature rising range of the exothermic curve falls within a range from 140° C. to 168° C.3. The electronic-part-reinforcing thermosetting resin composition of claim 1 , whereinthe resin composition turns into a cured product having a curing rate of 60% or more when subjected to a heating treatment under at least one condition that the highest heating temperature falls within a range from 160° C. to 200° C. and a total of time periods in which a heating temperature is equal to or higher than 160° C. is within a range from 40 seconds to 10 minutes.4. The electronic-part-reinforcing thermosetting resin composition of claim 1 , containinga bisphenol type epoxy resin exhibiting a liquid phase at 25° C.; andat least one compound selected from the group consisting of: 2-phenyl-4-hydroxymethyl-5-methylimidazole, 2-phenyl-4,5-dihydroxymethylimidazole, and 2,4-diamino-6 ...

BALL GRID ARRAY SOLDER ATTACHMENT

Reflow Grid Array (RGA) technology may be implemented on an interposer device, where the interposer is placed between a motherboard and a ball grid array (BGA) package. The interposer may provide a controlled heat source to reflow solder between the interposer and the BGA package. A technical problem faced by an interposer using RGA technology is application of solder to the RGA interposer. Technical solutions described herein provide processes and equipment for application of solder and formation of solder balls to connect an RGA interposer to a BGA package. 1. A method comprising:disposing solder on each of a plurality of interposer contacts on a reflow grid array (RGA) interposer; andreflowing the solder to form solid solder bumps, the solid solder bumps configured to be reflowed by the RGA interposer to solder an electrical component to the RGA interposer.21. The method of , wherein reflowing the solder includes heating an interposer heater trace.3. The method of claim 1 , further including soldering the electrical component to the RGA interposer.4. The method of claim 3 , wherein soldering the electrical component includes applying flux to the solid solder bumps.5. The method of claim 4 , wherein soldering the electrical component includes aligning the solid solder bumps with a plurality of component contacts on the electrical component.6. The method of claim 5 , wherein aligning the solid solder bumps includes disposing an alignment fixture on the RGA interposer and disposing the electrical component within the alignment fixture.7. The method of claim 3 , wherein soldering the electrical component includes reflowing the solid solder bumps.8. The method of claim 7 , wherein soldering the electrical component includes reflowing a plurality of electrical component solder bumps on the electrical component to form electrical contacts between the plurality of electrical component solder bumps and the solid solder bumps.9. The method of claim 1 , wherein disposing ...

Package on Package Bonding Structure and Method for Forming the Same

The described embodiments of mechanisms of forming a die package and package on package (PoP) structure involve forming a solder paste layer over metal balls of external connectors of a die package. The solder paste layer protects the metal balls from oxidation. In addition, the solder paste layer enables solder to solder bonding with another die package. Further, the solder paste layer moves an intermetallic compound (IMC) layer formed between the solder paste layer and the metal balls below a surface of a molding compound of the die package. Having the IMC layer below the surface strengthens the bonding structure between the two die packages. 1. A die package comprising:a semiconductor die attached to a substrate having interconnect structures, wherein the semiconductor die is electrically connected to the interconnect structures; and a first contact pad,', 'a metal ball with a convex surface, wherein the metal ball is bonded to the first contact pad, and', 'a solder paste layer over an upper surface of the metal ball, wherein an upper surface of the solder paste layer substantially conforms to the upper surface of the metal ball, and wherein the solder paste layer has a first portion above an upper surface of the molding compound and a second portion extending lower than the upper surface of the molding compound, wherein the second portion surrounds the first portion., 'a first external connector adjacent to the semiconductor die, wherein the first external connector is electrically connected to the interconnect structures, wherein the first external connector is embedded in a molding compound interposed between the semiconductor die and the first external connector, wherein the first external connector comprises2. The die package of claim 1 , wherein the molding compound is a molded underfill (MUF) interposed between the semiconductor die and the first external connector claim 1 , and wherein the MUF extends into a gap between the semiconductor die and the ...

3D INTEGRATED CIRCUIT (3DIC) STRUCTURE AND METHOD OF MAKING SAME

An embodiment bonded integrated circuit (IC) structure includes a first IC structure and a second IC structure bonded to the first IC structure. The first IC structure includes a first bonding layer and a connector. The second IC structure includes a second bonding layer bonded to and contacting the first bonding layer and a contact pad in the second bonding layer. The connector extends past an interface between the first bonding layer and the second bonding layer, and the contact pad contacts a lateral surface and a sidewall of the connector. 1. A bonded integrated circuit (IC) structure comprising:a first IC structure comprising a first bonding layer and a connector; and a second bonding layer over an interconnect layer, the second bonding layer bonded to and contacting the first bonding layer, wherein the connector extends past an interface between the first bonding layer and the second bonding layer; and', 'a contact pad in the second bonding layer, wherein the contact pad contacts a lateral surface and a sidewall of the connector, wherein the connector is electrically connected to the interconnect layer through the contact pad., 'a second IC structure bonded to the first IC structure, wherein the second IC structure comprises2. The bonded IC structure of claim 1 , wherein the contact pad extends from the interface between the first bonding layer and the second bonding layer to an opposing surface of the second bonding layer from the first bonding layer.3. The bonded IC structure of claim 2 , wherein a lateral surface of the contact pad is substantially level with the opposing surface of the second bonding layer.4. The bonded IC structure of claim 1 , further comprising an air gap between the contact pad and the first bonding layer.5. The bonded IC structure of claim 1 , wherein the connector comprises solder claim 1 , copper claim 1 , or a combination thereof.6. The bonded IC structure of claim 1 , wherein the first bonding layer and the second bonding layer ...

Low cost package warpage solution

Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.

Substrate structure and method of manufacturing the same

Provided is a substrate structure including a substrate body, electrical contact pads and an insulating protection layer disposed on the substrate body, wherein the insulating protection layer has openings exposing the electrical contact pads, and at least one of the electrical contact pads has at least a concave portion filled with a filling material to prevent solder material from permeating along surfaces of the insulating protection layer and the electric contact pads, thereby eliminating the phenomenon of solder extrusion. Thus, bridging in the substrate structure can be eliminated even when the bump pitch between two adjacent electrical contact pads is small. As a result, short circuits can be prevented, and production yield can be increased.

Packaging through Pre-Formed Metal Pins

A package includes first package component and a second package component. The first package component includes a first electrical connector at a surface of the first package component, and a first solder region on a surface of the first electrical connector. The second package component includes a second electrical connector at a surface of the second package component, and a second solder region on a surface of the second electrical connector. A metal pin has a first end bonded to the first solder region, and a second end bonded to the second solder region. 1. A package comprising: a first electrical connector at a surface of the first package component; and', 'a first solder region on a surface of the first electrical connector;, 'a first package component comprising a second electrical connector at a surface of the second package component; and', 'a second solder region on a surface of the second electrical connector; and, 'a second package component comprising a first end bonded to the first solder region, wherein the first end has a T-shaped cross-sectional view; and', 'a second end bonded to the second solder region., 'a metal pin formed of a non-solder metallic material, the metal pin comprising2. The package of claim 1 , wherein the first solder region is separated from the second solder region.3. The package of claim 1 , wherein the first end of the metal pin is spaced apart from the first electrical connector by a portion of the first solder region.4. The package of claim 3 , wherein the second end of the metal pin is spaced apart from the second electrical connector by a portion of the second solder region.5. The package of claim 1 , wherein the first end is in physical contact with the first electrical connector claim 1 , with no metal-to-metal direct bonding formed between the first end of the metal pin and the first electrical connector.6. The package of claim 5 , wherein the metal pin is bonded to the first electrical connector by the first solder ...

Integrated Circuit Package and Methods of Forming Same

A method for forming integrated circuit packages is presented. A first plurality of first tier stacks are mounted to the substrate, wherein the substrate has one or more contact pads corresponding to each of the first tier stacks and has one or more probing pads associated with each of the first tier stacks. Each of the first tier stacks is electrically tested to identify known good first tier stacks and known bad first tier stacks. A first plurality of stacking substrates are mounted to the known good first tier stacks, thereby forming a plurality of second tier stacks. Each of the second tier stacks is electrically tested to identify known good second tier stacks and known bad second tier stacks. 1. A method for forming integrated circuit packages , the method comprising:providing a substrate;mounting a plurality of first tier stacks to the substrate, wherein the substrate has one or more contact pads corresponding to each of the first tier stacks and has one or more probing pads associated with each of the first tier stacks;electrically testing each of the first tier stacks and identifying known good first tier stacks and known bad first tier stacks;mounting a first plurality of stacking substrates to the known good first tier stacks, thereby forming a plurality of second tier stacks; andelectrically testing each of the second tier stacks, and identifying known good second tier stacks and known bad second tier stacks.2. The method of claim 1 , wherein the plurality of first tier stacks is a plurality of integrated circuit dies.3. The method of claim 1 , wherein the plurality of first tier stacks is a plurality of interposers.4. The method of claim 1 , further comprising mounting a plurality of dummy substrates to the known bad first tier stacks.5. The method of claim 1 , wherein electrically testing each of the first tier stacks comprises testing functionality of each of the first tier stacks.6. The method of claim 1 , further comprising:mounting a second ...

SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME

Present disclosure provides a semiconductor package, including a first substrate having a first active surface and a first trench recessed from the first active surface, a second substrate having a second trench facing the first trench, and a pathway cavity defined by the first trench and the second trench. The first trench comprises a first metal protrusion and a first insulating protrusion. A method for manufacturing the semiconductor package described herein is also disclosed. 1. A semiconductor package , comprising:a first substrate having a first active surface and a first trench recessed from the first active surface;a second substrate having a second trench facing the first trench; anda pathway cavity defined by the first trench and the second trench;wherein the first trench comprises a first metal protrusion and a first insulating protrusion.2. The semiconductor package of claim 1 , wherein the pathway cavity comprises a narrower width at an edge of the first substrate and a wider width at a center of the first substrate.3. The semiconductor package of claim 1 , wherein the second trench further comprising:a second metal protrusion electrically coupling to the first metal protrusion; anda second insulating protrusion connected to the first insulating protrusion.4. The semiconductor package of claim 3 , further comprising an electroless-plated portion between the first metal protrusion and the second metal protrusion.5. The semiconductor package of claim 3 , further comprising a boundary between the first insulating protrusion and the second insulating protrusion claim 3 , the boundary being at a level higher than a top surface of the first metal protrusion.6. The semiconductor package of claim 1 , wherein the first trench further comprises a plurality of metal protrusions and a plurality of insulating protrusions claim 1 , each of the metal protrusions being staggerly disposed with respect to each of the insulating protrusions.7. The semiconductor package of ...

PASTE THERMOSETTING RESIN COMPOSITION, SEMICONDUCTOR COMPONENT, SEMICONDUCTOR MOUNTED ARTICLE, METHOD FOR MANUFACTURING SEMICONDUCTOR COMPONENT, AND METHOD FOR MANUFACTURING SEMICONDUCTOR MOUNTED ARTICLE

Provided is a paste thermosetting resin composition containing solder powder, a thermosetting resin binder, an activator, and a thixotropy imparting agent. The solder powder has a melting point ranging from 100° C. to 240° C., inclusive. The thermosetting resin binder contains a main agent and a curing agent. The main agent contains a di- or higher functional oxetane compound. 1. A paste thermosetting resin composition comprising:solder powder;a thermosetting resin binder;an activator; anda thixotropy imparting agent,the solder powder having a melting point ranging from 100° C. to 240° C., inclusive,the thermosetting resin binder containing a main agent and a curing agent, andthe main agent containing a di- or higher functional oxetane compound.3. The paste thermosetting resin composition according to claim 1 ,wherein the oxetane compound is 50% by mass or more relative to a total mass of the main agent.4. The paste thermosetting resin composition according to claim 1 ,wherein the curing agent contains a benzoxazine compound having two or more oxazine rings.5. The paste thermosetting resin composition according to claim 1 ,wherein the solder powder is powder of Sn—Ag—Cu solder.6. The paste thermosetting resin composition according to claim 1 ,wherein the solder powder is powder of Sn—Bi solder.7. The paste thermosetting resin composition according to claim 1 ,wherein the solder powder has an average particle size ranging from 3 μm to 30 μm, inclusive.8. The paste thermosetting resin composition according to claim 1 ,wherein the main agent contains a di- or higher functional epoxy compound.9. The paste thermosetting resin composition according to claim 1 ,wherein the activator contains one or more compounds selected from the group consisting of glutaric acid and triethanolamine.10. The paste thermosetting resin composition according to claim 1 ,wherein the thixotropy imparting agent contains amide wax.11. A paste thermosetting resin composition comprising:solder ...

Localized sealing of interconnect structures in small gaps

An apparatus relates generally to a microelectronic device. In such an apparatus, a first substrate has a first surface with first interconnects located on the first surface, and a second substrate has a second surface spaced apart from the first surface with a gap between the first surface and the second surface. Second interconnects are located on the second surface. Lower surfaces of the first interconnects and upper surfaces of the second interconnects are coupled to one another for electrical conductivity between the first substrate and the second substrate. A conductive collar is around sidewalls of the first and second interconnects, and a dielectric layer is around the conductive collar. 1. A microelectronic device , comprising:a conductive collar around sidewalls of first interconnects and second interconnects;the conductive collar configured from phase separated self-assembly matrix material;a dielectric layer around the conductive collar; andthe dielectric layer configured from the phase separated self-assembly matrix material.2. The microelectronic device according to claim 1 , wherein:the first and second interconnects respectively include metallization structures.3. The microelectronic device according to claim 1 , wherein:the first and second interconnects are respectively of first and second substrates;the first and second interconnects respectively include metallization structures;a gap between the first and second substrates is equal to or less than a pitch between the sidewalls of two adjacent ones of the first interconnects; andthe first and second interconnects are coupled to one another for electrical conductivity between the first substrate and the second substrate.4. The microelectronic device according to claim 1 , wherein:the first and second interconnects are respectively of first and second substrates;the first and second interconnects respectively include metallization structures;a gap between the first and second substrates is equal to ...

Semiconductor Devices Having a Glass Substrate, and Method for Manufacturing Thereof

A method for manufacturing semiconductor devices includes providing a stack having a semiconductor wafer and a glass substrate with openings and at least one trench attached to the semiconductor wafer. The semiconductor wafer includes a plurality of semiconductor devices. The openings of the glass substrate leave respective areas of the semiconductor devices uncovered by the glass substrate and the trench connects the openings. A metal layer is formed at least on exposed walls of the trench and the openings and on the uncovered areas of the semiconductor devices of the semiconductor wafer. A metal region is formed by electroplating metal in the openings and the trench and by subsequently grinding the glass substrate to remove the trenches. The stack of the semiconductor wafer and the attached glass substrate is cut to separate the semiconductor devices.

Dummy Flip Chip Bumps for Reducing Stress

A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A dummy bump is over the polymer layer, wherein the dummy bump is electrically insulated from conductive features underlying the polymer layer. 1. A method comprising: bonding a first solder region to be between and joining to both of an electrical connector of the device die and a metal trace of the package component, wherein the first solder region contacts a bottom surface and sidewalls of the metal trace, and the metal trace is in a surface dielectric layer of the package component; and', 'contacting a second solder region to a bottom surface of the surface dielectric layer or a bond pad of the package component, wherein the bond pad is in the surface dielectric layer, and wherein the second solder region is joined to a dummy bump of the device die., 'bonding a package component to a device die, wherein the bonding comprises2. The method of further comprising forming the device die comprising:forming an additional dielectric layer; andforming the dummy bump over the additional dielectric layer, with an entirety of a bottom surface of the dummy bump contacting a top surface of the additional dielectric layer.3. The method of claim 2 , wherein the dummy bump is electrically disconnected from all conductive components that are lower than the top surface of the additional dielectric layer.4. The method of claim 1 , wherein after the bonding claim 1 , the dummy bump is electrically floating.5. The method of claim 1 , wherein the first solder region extends into an opening in the surface dielectric layer of the package component.6. The method of further comprising claim 5 , after the package component is bonded to the device die claim 5 , dispensing an underfill between ...

PACKAGE-ON-PACKAGE SEMICONDUCTOR DEVICE

Some embodiments relate to a semiconductor device. The semiconductor device includes a substrate. A first die is coupled beneath a lower surface of the substrate. A second die is coupled beneath the lower surface of the substrate and is disposed over the first die. A thermal contact pad is arranged beneath a lower surface of the second die and an upper surface of the first die. The thermal contact pad thermally isolates the first die from the second die. 1. A semiconductor device comprising:a substrate;a first die coupled beneath a lower surface of the substrate;a second die coupled beneath the lower surface of the substrate and disposed over the first die; anda thermal contact pad arranged beneath a lower surface of the second die and an upper surface of the first die, wherein the thermal contact pad thermally isolates the first die from the second die.2. The semiconductor device of claim 1 , wherein the thermal contact pad has outer sidewalls which are aligned with corresponding outer sidewalls of the second die.3. The semiconductor device of claim 1 , wherein the first die has a first width as measured between outer sidewalls of the first die claim 1 , and wherein the second die has a second width claim 1 , which is less than the first width claim 1 , as measured between outer sidewalls of the second die claim 1 , and wherein the thermal contact pad has a third width as measured between outer sidewalls of the thermal contact pad claim 1 , the third width being equal to the second width.4. The semiconductor device of claim 1 , further comprising:conductive elements extending through the substrate and coupled to the first die and the second die.5. The semiconductor device of claim 1 , further comprising:a molding compound separating the upper surface of the first die from the lower surface of the substrate and separating the upper surface of the second die from the lower surface of the substrate.6. The semiconductor device of claim 5 , further comprising:conductive ...

Ball Height Control in Bonding Process

A package includes a first package component, a second package component over the first package component, and a solder region bonding the first package component to the second package component. At least one ball-height control stud separates the first package component and the second package component from each other, and defines a standoff distance between the first package component and the second package component.

Printed circuit board, semiconductor device connection structure, and method of manufacturing a printed circuit board

First electrode pads formed on one semiconductor package surface include a first reinforcing electrode pad having a surface area larger than that of other first electrode pads. Second electrode pads formed on a printed wiring board on which the semiconductor package is mounted include at least one second reinforcing electrode pad. The second reinforcing electrode pad opposes the first reinforcing electrode pad, and has a surface area greater than that of the other second electrode pads. The first and second electrode pads are connected by solder connection parts. A cylindrical enclosing member encloses an outer perimeter of a solder connection part connecting the first and second reinforcing electrode pads. Increases in the amount of warping of semiconductor devices such as the package substrate and the printed wiring board are suppressed, and the development of solder bridges with respect to adjacent solder connecting parts or adjacent components is reduced.

SYSTEM AND METHOD FOR LASER ASSISTED BONDING OF AN ELECTRONIC DEVICE

A system and method for laser assisted bonding of semiconductor die. As non-limiting examples, various aspects of this disclosure provide systems and methods that enhance or control laser irradiation of a semiconductor die, for example spatially and/or temporally, to improve bonding of the semiconductor die to a substrate. 120-. (canceled)21. A method of manufacturing an electronic device , the method comprising:receiving a first electronic component having a laser assisted bonding (LAB) material thereon;receiving a second electronic component;positioning the first and second electronic components such that a plurality of interconnection structures are positioned between the first and second electronic components; andlaser-irradiating at least a portion of the LAB material while reflowing the interconnection structures.22. The method of claim 21 , wherein said laser-irradiating comprises laser-irradiating at least a portion of the second electronic component.23. The method of claim 21 , wherein the first electronic component comprises a laminate structure.24. The method of claim 21 , wherein the LAB material alters reflectiveness of the first electronic component.25. The method of claim 21 , wherein the LAB material is a laser absorbing material.26. The method of claim 21 , wherein:one of the first electronic component and the second electronic component comprises a functional die; andanother of the first electronic component and the second electronic component comprises a substrate.27. The method of claim 21 , wherein:the first electronic component comprises a plurality of first component lateral sides;the LAB material comprises a plurality of LAB lateral sides; andeach of the plurality of LAB lateral sides is coplanar with a respective one of the plurality of first component lateral sides.28. The method of claim 21 , wherein the LAB material vertically covers only a portion of the first electronic component.29. The method of claim 21 , comprising forming an ...

FLIP-CHIP ELECTRONIC DEVICE WITH CARRIER HAVING HEAT DISSIPATION ELEMENTS FREE OF SOLDER MASK

A solution relating to electronic devices of flip-chip type is proposed. Particularly, an electronic device () of flip-chip type comprises at least one chip carrier () having a carrier surface (), the carrier comprising one or more contact elements () of electrically conductive material on the carrier surface, at least one integrated circuit chip () having a chip surface (), the chip comprising one or more terminals () of electrically conductive material on the chip surface each one facing a corresponding contact element, solder material () soldering each terminal to the corresponding contact element, and restrain means () around the contact elements for restraining the solder material during a soldering of the terminals to the contact elements, wherein the carrier comprises one or more heat dissipation elements () of thermally conductive material on the carrier surface facing the chip surface displaced from the terminals, the dissipation elements being free of any solder mask. 1. An electronic device of a flip-chip type comprising:at least one chip carrier having a carrier surface, the at least one chip carrier comprising one or more contact elements of electrically conductive material on the carrier surface;at least one integrated circuit chip having a chip surface, the at least one integrated circuit chip comprising one or more terminals of electrically conductive material on the chip surface each one facing a corresponding contact element;solder material soldering each terminal to the corresponding contact element, and a restrain structure around the contact elements for restraining the solder material during a soldering of the terminals to the contact elements; andwherein the at least one chip carrier comprises one or more heat dissipation elements of thermally conductive material on the carrier surface facing the chip surface displaced from the terminals, the dissipation elements being free of any solder mask.2. The electronic device according to claim 1 , ...

Solderless Interconnection Structure and Method of Forming Same

An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion. 1. A device comprising:a substrate trace extending along a first substrate, the substrate trace having a first shape in a plan view; anda metal ladder bump extending from an integrated circuit, the metal ladder bump having a second shape in the plan view, the second shape being different from the first shape,wherein the metal ladder bump and the substrate trace are physically and electrically coupled together through direct metal-to-metal bonds, an interface between the metal ladder bump and the substrate trace being free from solder.2. The device of claim 1 , wherein the substrate trace has a first length claim 1 , the metal ladder bump has a second length claim 1 , and the first length is greater than the second length claim 1 , the first length and the second length each being measured in a direction parallel to a longitudinal axis of the substrate trace.3. The device of claim 1 , wherein the second shape is a quadrilateral.4. The device of claim 1 , wherein the second shape is a circle.5. The device of claim 1 , wherein the metal ladder bump and the substrate trace are copper claim 1 , and wherein the interface between the metal ladder bump and the substrate trace is free from intermetallic compounds.6. The device of claim 1 , wherein the substrate trace has a first end proximate the first substrate and a second end distal the first substrate claim 1 , the first end having a greater width than the second end. ...

3D INTEGRATED CIRCUIT (3DIC) STRUCTURE AND METHOD OF MAKING SAME

An embodiment bonded integrated circuit (IC) structure includes a first IC structure and a second IC structure bonded to the first IC structure. The first IC structure includes a first bonding layer and a connector. The second IC structure includes a second bonding layer bonded to and contacting the first bonding layer and a contact pad in the second bonding layer. The connector extends past an interface between the first bonding layer and the second bonding layer, and the contact pad contacts a lateral surface and a sidewall of the connector. 1. A bonded integrated circuit (IC) structure comprising:a first IC structure comprising a first bonding layer and a connector; and a second bonding layer bonded to and contacting the first bonding layer, wherein the connector extends past an interface between the first bonding layer and the second bonding layer; and', 'a contact pad in the second bonding layer, wherein the contact pad contacts a lateral surface and a sidewall of the connector., 'a second IC structure bonded to the first IC structure, wherein the second IC structure comprises2. The bonded IC structure of claim 1 , wherein the contact pad extends from the interface between the first bonding layer and the second bonding layer to an opposing surface of the second bonding layer from the first bonding layer.3. The bonded IC structure of claim 2 , wherein a lateral surface of the contact pad is substantially level with the opposing surface of the second bonding layer.4. The bonded IC structure of claim 1 , further comprising an air gap between the contact pad and the first bonding layer.5. The bonded IC structure of claim 1 , wherein the connector comprises solder claim 1 , copper claim 1 , or a combination thereof.6. The bonded IC structure of claim 1 , wherein the first bonding layer and the second bonding layer each comprise an oxide.7. The bonded IC structure of claim 1 , wherein the connector is partially disposed in the first bonding layer.8. The bonded IC ...

Dummy Flip Chip Bumps for Reducing Stress

A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A dummy bump is over the polymer layer, wherein the dummy bump is electrically insulated from conductive features underlying the polymer layer. 1. A device comprising:a substrate;a metal pad over the substrate;a passivation layer comprising a portion over the metal pad;a post-passivation interconnect (PPI) electrically coupling to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer;a polymer layer over the PPI; a first portion extending into the polymer layer to electrically couple to the metal pad; and', 'a second portion having a bottom surface contacting a top surface of the polymer layer; and, 'a non-solder electrical connector comprisinga dummy bump having a bottom surface contacting the top surface of the polymer layer.2. The device of claim 1 , wherein the dummy bump comprises:a non-solder bump and a solder cap over the non-solder bump.3. The device of further comprising a device over the non-solder electrical connector and the dummy bump claim 1 , wherein the device comprises a dielectric layer claim 1 , and a bottom surface of the dielectric layer in the device is in contact with a top surface of the dummy bump.4. The device of claim 3 , wherein the dummy bump comprises a solder region claim 3 , and the bottom surface of the dielectric layer is in contact with the top surface of the dummy bump.5. The device of claim 4 , wherein the dummy bump further comprises a non-solder portion underlying the solder region.6. The device of claim 1 , wherein the polymer layer is a polyimide layer claim 1 , and wherein the dummy bump comprises a copper-containing material.7. The device of claim 1 , wherein the dummy bump is ...

SEMICONDCUTOR PACKAGE

A semiconductor package, a manufacturing method for the semiconductor package and a printing module used thereof are provided. The semiconductor package has a redistribution layer, at least one die over the redistribution layer, through interlayer vias on the redistribution layer and aside the die and a molding compound encapsulating the die and the through interlayer vias disposed on the redistribution layer. The semiconductor package has connectors connected to the through interlayer vias, a polymeric cover film covering the molding compound and the die and polymeric dam structures disposed aside the connectors. The polymeric cover film and the polymeric dam structures are formed by printing. 1. A semiconductor package comprising:at least one die;a molding compound encapsulating the at least one die;through interlayer vias (TIVs), penetrating the molding compound and arranged beside the at least one die, wherein at least one of the through interlayer vias is electrically connected with the at least one die;a polymeric cover film, disposed on the molding compound and on the at least one die;connectors, disposed on the through interlayer vias; andpolymeric dam structures, disposed on the molding compound and located beside and between the connectors, wherein the polymeric dam structures are block structures arranged around the connectors and between the connectors in a region where the TIVs are located, tops of the polymeric dam structures are higher than tops of the connectors, and the polymeric cover film is made of a material different from that of the polymeric dam structures.2. The semiconductor package as claimed in claim 1 , wherein a height of the connectors is larger than a thickness of the polymeric cover film and is smaller than a height of the polymeric dam structures.3. The semiconductor package as claimed in claim 2 , wherein a ratio of the height of the polymeric dam structures to the height of the connectors is greater than 1.0 and less than about 2. ...

Bump Structure and Method of Forming Same

An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal bump on the under bump metallurgy feature, and a substrate trace on a substrate, the substrate trace coupled to the metal bump through a solder joint and intermetallic compounds, a ratio of a first cross sectional area of the intermetallic compounds to a second cross sectional area of the solder joint greater than forty percent. 1. A device comprising:a first substrate;a conductive pillar extending from a first surface of the first substrate;a second substrate;a conductive trace extending along a second surface of the second substrate, the conductive trace having a uniform width, the conductive trace extending past a periphery of the conductive pillar in a plan view; anda solder joint electrically coupling the conductive pillar to the conductive trace, the solder joint being separated from the conductive trace and the conductive pillar by intermetallic compounds, a ratio of a first cross sectional area of the intermetallic compounds to a second cross sectional area of the solder joint greater than forty percent.2. The device of claim 1 , further comprising an additional metal interposed between the conductive pillar and the solder joint.3. The device of claim 2 , wherein the additional metal comprises nickel.4. The device of claim 1 , wherein the conductive pillar has a tapering profile.5. The device of claim 1 , wherein a ratio of a top width of the conductive pillar to a bottom width of the conductive pillar is between about 0.5 to about 0.89.6. The device of claim 1 , wherein sidewalls of the conductive pillar are coated with a metal oxide.7. The device of claim 1 , wherein the conductive trace is provided with a surface treatment.8. The device of claim 7 , wherein the surface treatment comprises organic solderability preservatives (OSP).9. The device of claim 7 , ...

Package-on-package semiconductor device

Exemplary methods of forming the semiconductor device, encompasses forming a first package with at least one first die on a packaging substrate that is removably coupled to a carrier. Forming a thermal contact pad on the first die package, with or without a surrounding seal ring, and bonding a second die package to the first die package where the thermal contact pad is between the two packages. Electrically coupling the first die package to the second die package with a set of conductive elements and removing the carrier from the first package.

Low cost package warpage solution

Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.

BALL GRID ARRAY SOLDER ATTACHMENT

Reflow Grid Array (RGA) technology may be implemented on an interposer device, where the interposer is placed between a motherboard and a ball grid array (BGA) package. The interposer may provide a controlled heat source to reflow solder between the interposer and the BGA package. A technical problem faced by an interposer using RGA technology is application of solder to the RGA interposer. Technical solutions described herein provide processes and equipment for application of solder and formation of solder balls to connect an RGA interposer to a BGA package. 1. An apparatus comprising:an interposer;a plurality of electrical component interposer contacts on a first surface of the interposer; anda heater trace within the interposer proximate to one or more of the plurality of electrical component interposer contacts.2. The apparatus of claim 1 , further including a plurality of conductive through-holes within the interposer and proximate to the heater trace claim 1 , each of the conductive through-holes electrically connected to each of the plurality of electrical component interposer contacts.3. The apparatus of claim 1 , further including a plurality of motherboard interposer contacts on a second surface of the interposer claim 1 , the second surface of the interposer opposite from the first surface of the interposer claim 1 , each of the conductive through-holes electrically connecting each of the plurality of electrical component interposer contacts and each of the plurality of motherboard interposer contacts.4. The apparatus of claim 1 , further including a thermal sensor trace within the interposer to generate temperature sensor data.5. The apparatus of claim 4 , further including a controller to receive temperature sensor data from the thermal sensor trace and control a heater current applied to the heater trace.6. The apparatus of claim 1 , further including:a second plurality of electrical component interposer contacts within a second zone on the first ...

LOW COST PACKAGE WARPAGE SOLUTION

Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer. 1. (canceled)2. An electronic device comprising:a package substrate having one or more conductive traces over a first surface of the package substrate;solder resist material over the one or more conductive traces;one or more conductive through vias from the first surface of the package substrate to a second surface of the package substrate that is opposite from the first surface of the package substrate, wherein one or more of the conductive vias are electrically coupled to a conductive trace of the one or more conductive traces;a reinforcement layer over the package substrate, wherein the reinforcement layer has at least one opening;a device die electrically coupled to the one or more conductive traces by one or more solder bumps, wherein the device die is positioned in the opening of the reinforcement layer; andwherein a first gap between a first edge of the device die and a first sidewall of the opening is larger than a second gap between a second edge of the device die and a second sidewall of the opening.3. The device of claim 2 , further comprising adhesive material between the reinforcement layer and the first surface of the package substrate.4. The device of claim 3 , wherein the adhesive material comprises an epoxy claim 3 , a polyester claim 3 , or an acrylic material.5. The device of ...

METHOD AND SYSTEM FOR POSITIONING USING NEAR FIELD TRANSDUCERS, PARTICULARLY SUITED FOR POSITIONING ELECTRONIC CHIPS USING INTERPOSERS

Method for positioning and orienting a first object relative to a second object. Method includes positioning a near field transducer having an aperture on the first object, and directing a laser light toward the aperture of the near field transducer on the first object to create an effervescent wave on the other side of the aperture. Positioning a sensor on the second object for detecting the effervescent wave from the near field transducer. Providing an algorithm, and using information obtained from the sensor on the second object in the algorithm to control a nanopositioning system to position one of the first and second objects in a desired position and orientation relative to the other one of the first and second objects. One or both of the first and second objects may be an interposer, such as a silicon or glass interposer. 1. A method for positioning and orienting a first object relative to a second object , the method comprising:a) positioning a near field transducer having an aperture on the first object;b) directing a laser light toward the aperture of the near field transducer on the first object to create an effervescent wave on the other side of the aperture;c) positioning a sensor on the second object for detecting the effervescent wave from the near field transducer;d) the first object being an interposer; ande) providing an algorithm, using information obtained from the sensor on the second object in the algorithm to control a nanopositioning system to position one of the first object and the second object in a desired position and orientation relative to the other one of the first object and the second object.2. The method for positioning and orienting a first object relative to a second object as in claim 1 , wherein:a) the sensor is one of an optical sensor, a thermal sensor, and a single metal thermocouple with a constriction.3. The method for positioning and orienting a first object relative to a second object as in claim 1 , wherein:a) the laser ...

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE THEREOF

Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a device includes coupling a first semiconductor device to a second semiconductor device by spacers. The first semiconductor device has first contact pads disposed thereon, and the second semiconductor device has second contact pads disposed thereon. The method includes forming an immersion interconnection between the first contact pads of the first semiconductor device and the second contact pads of the second semiconductor device. 1. A method of manufacturing a device , the method comprising:coupling a first semiconductor device to a second semiconductor device by a plurality of spacers, the first semiconductor device having a plurality of first contact pads disposed thereon, the second semiconductor device having a plurality of second contact pads disposed thereon; andforming an immersion interconnection between each of the plurality of first contact pads of the first semiconductor device and one of the plurality of second contact pads of the second semiconductor device.2. The method according to claim 1 , wherein coupling the first semiconductor device to the second semiconductor device comprises coupling a first semiconductor device comprising a wafer claim 1 , an integrated circuit die claim 1 , or a plurality of integrated circuit dies to the second semiconductor device.3. The method according to claim 1 , wherein coupling the first semiconductor device to the second semiconductor device comprises coupling the first semiconductor device to a second semiconductor device comprising a wafer claim 1 , an integrated circuit die claim 1 , or a plurality of integrated circuit dies.4. The method according to claim 1 , wherein the plurality of first contact pads or the plurality of second contact pads comprise a conductive pillar coupled thereto claim 1 , and wherein forming the immersion interconnection further comprises forming the immersion ...

SUBSTRATE, ELECTRONIC SUBSTRATE, AND METHOD FOR PRODUCING ELECTRONIC SUBSTRATE

A substrate is capable of effectively reinforcing a connecting portion between an electronic component and the substrate. The substrate is a substrate on which a first electronic component having a plurality of bumps is to be mounted, and includes a base portion including an insulator and having, on the upper face thereof, at least one groove portion configured to store a tip portion of at least one of the bumps, and includes an electrode formed on at least the bottom face of the groove portion. 1. A substrate on which a first electronic component having a plurality of bumps is to be mounted , the substrate comprising:a base portion including an insulator and having, on an upper face thereof, at least one groove portion configured to receive a tip portion of at least one of the bumps of the first electronic component; andan electrode on at least a bottom face of the groove portion.2. The substrate according to claim 1 , wherein the electrode is on the bottom face and a side face of the groove portion.3. The electronic substrate according to claim 1 , wherein a respective groove portion corresponds to each bump.4. The substrate according to claim 1 , wherein a plurality of the groove portions are on the upper face in a grid pattern.5. The substrate according to claim 4 , wherein the groove portions include first groove portions in four corner areas on the base portion and include second groove portions having a smaller diameter than that of the first groove portions and are located in an area other than the four corner areas on the base portion.6. The substrate according to claim 1 , wherein:the plurality of groove portions are located in an outer peripheral area on the base portion,an upper face of an inside area from the outer peripheral area with the groove portions is a recessed portion that is recessed from an upper face of the outer peripheral area, and an upper face of the recessed portion has at least electrode configured to be connected to at least one of ...

INTERPOSER, ELECTRONIC SUBSTRATE, AND METHOD FOR PRODUCING ELECTRONIC SUBSTRATE

An interposer is capable of efficiently reinforcing the connecting portion between an electronic component and a substrate. The interposer is used for mounting a first electronic component on a substrate and includes a sheet-shaped spacer having at least one through-hole and including a material that does not flow during reflow soldering and a resin portion that covers at least a part of the spacer and is flowable during reflow soldering, and the through-hole is configured to store a bump of the first electronic component. 1. An interposer used for mounting a first electronic component on a substrate , the interposer comprising:a sheet-shaped spacer having at least one through-hole and including a material that is non-flowable during reflow soldering; anda resin portion that covers at least a part of the spacer and is flowable during reflow soldering, wherein:the through-hole is configured to receive a bump of the first electronic component.2. The interposer according to claim 1 , wherein:the spacer includes an insulating material having a smaller thermal expansion coefficient than that of the resin portion, andthe resin portion covers an upper face and an lower face of the spacer.3. The interposer according to claim 1 , wherein the resin portion covers an upper face and a lower face of the spacer and a surface of the through-hole.4. The interposer according to claim 2 , wherein an inner surface of the through-hole is covered with a metal coating.5. The interposer according to claim 1 , wherein the spacer has a plurality of the through-holes arranged in a grid pattern.6. The interposer according to claim 1 , wherein:the through-hole is located in an outer peripheral area of the spacer, andthe spacer has a void in an inner area from the outer peripheral area with the through-hole.7. An electronic substrate comprising:a substrate;a first electronic component having a bump mounted on the substrate; andan interposer including a sheet-shaped spacer having at least one ...

FLIP-CHIP METHOD

A flip-chip method includes providing a semiconductor chip and conductive connection pillars. Each of the conductive connection pillars has a first surface and a second surface opposite to the first surface. The flip-chip method also includes fixing the conductive connection pillars on a surface of the semiconductor chip. The first surfaces face the semiconductor chip. The flip-chip method also includes providing a carrier plate, forming solder pillars on the carrier plate, and forming a barrier layer on the carrier plate around the solder pillars. The flip-chip method further includes bringing the solder pillars into contact with the second surfaces of the conductive connection pillars. The conductive connection pillars are located above the solder pillars. The flip-chip method further includes performing a reflow-soldering process on the solder pillars, thereby forming solder layers from the solder pillars. 1. A flip-chip method , comprising:providing a semiconductor chip and conductive connection pillars, wherein each of the conductive connection pillars has a first surface and a second surface opposite to the first surface;fixing the conductive connection pillars on a surface of the semiconductor chip, wherein the first surfaces face the semiconductor chip;providing a carrier plate;forming solder pillars on the carrier plate;forming a barrier layer on the carrier plate around the solder pillars;bringing the solder pillars into contact with the second surfaces of the conductive connection pillars, wherein the conductive connection pillars are located above the solder pillars; andperforming a reflow-soldering process on the solder pillars, thereby forming solder layers from the solder pillars.2. The flip-chip method according to claim 1 , further including: 'the barrier layer is made of a material including an insulation glue and formed by a brushing process.', 'forming the barrier layer after the solder pillars are formed, wherein3. The flip-chip method according ...

Metal-Bump Sidewall Protection

A method includes forming a metal bump on a top surface of a first package component, forming a solder region on a top surface of the metal bump, forming a protection layer extending on a sidewall of the metal bump, reflowing the solder region to bond the first package component to a second package component, and dispensing an underfill between the first package component and the second package component. The underfill is in contact with the protection layer.

반도체 장치 및 이를 포함하는 반도체 패키지

본 발명의 실시예에 따른 반도체 장치는 제 1 절연막 상에 배치된 제 1 버퍼 절연막, 상기 제 1 버퍼 절연막 상에 차례로 배치된 제 2 절연막 및 제 2 버퍼 절연막, 상기 제 2 버퍼 절연막과 상기 제 1 버퍼 절연막은 서로 접촉하고, 및 상기 상기 제 1 버퍼 절연막 및 상기 제 2 버퍼 절연막을 관통하는 패드 연결 구조체를 포함하되, 상기 패드 연결 구조체는 구리 및 주석을 포함할 수 있다.

柔性显示面板及其制备方法、柔性显示装置

本发明提供一种柔性显示面板，包括柔性基板；在所述柔性基板的背面形成有背面保护膜；在所述柔性基板和所述背面保护膜之间还设置有胶材；在所述柔性基板和所述背面保护膜之间且对应每个IC Bump位置处设置有支撑体；所述支撑体用于在所述胶材内支撑所述IC Bump。本发明还提供一种柔性显示面板的制备方法和柔性显示装置。本发明可以提高IC bonding后的平坦度，从而能够降低IC边缘处断线和压接不良等问题的产生。

半导体装置和包括其的半导体封装件

本公开提供了半导体装置和包括其的半导体封装件。半导体装置包括第一电介质层上的第一缓冲电介质层；按次序布置在第一缓冲电介质层上的第二电介质层和第二缓冲电介质层，第二缓冲电介质层与第一缓冲电介质层接触；以及焊盘互连结构，其穿过第一缓冲电介质层和第二缓冲电介质层，其中焊盘互连结构包括铜和锡。

Semiconductor device and method for manufacturing the same

반도체 장치 및 그 제조 방법이 제공된다. 반도체 장치는, 내부 기판; 상기 내부 기판을 수직으로 관통하도록 형성되고, 상기 내부 기판의 상면으로부터 돌출된 TSV(Through Silicon Via); 상기 돌출된 TSV의 측면을 둘러싸도록 상기 내부 기판의 상면 상에 형성된 보호층; 상기 돌출된 TSV의 상면 상에 형성되고, 상기 보호층의 일부와 오버랩되는 접촉 패드; 및 상기 접촉 패드와 동일한 높이로 상기 보호층 상에 형성되는 더미 패드를 포함한다. A semiconductor device and a method for manufacturing the same are provided. A semiconductor device comprising: an internal substrate; a through silicon via (TSV) formed to vertically penetrate the inner substrate and protruding from a top surface of the inner substrate; a protective layer formed on an upper surface of the inner substrate to surround a side surface of the protruding TSV; a contact pad formed on an upper surface of the protruding TSV and overlapping a portion of the protective layer; and a dummy pad formed on the passivation layer at the same height as the contact pad.

Film for flip chip type semiconductor back surface and its use

本发明涉及倒装芯片型半导体背面用膜及其用途。本发明涉及倒装芯片型半导体背面用膜，其要设置于倒装芯片连接至被粘物上的半导体元件背面上，所述倒装芯片型半导体背面用膜包括粘合剂层和层压于粘合剂层上的保护层，其中保护层由具有玻璃化转变温度为200℃以上的耐热性树脂构成或由金属构成。

Laminating device and method for fabricating semiconductor package using the same

라미네이팅 장치 및 그를 이용하는 반도체 패키지 제조 방법이 제공된다. 라미네이팅 장치는, 기판이 배치되는 기판 받침대, 기판 받침대 상에, 기판 받침대의 상면과 대향되는 볼록면을 포함하고, 팽창 가능한 가압부, 가압부와 연결되어 가압부에 공기를 주입하는 플레이트, 및 기판과 가압부 사이에 필름을 제공하는 필름 제공부를 포함하고, 가압부는 팽창하면서 기판 상에 필름을 부착시킨다. A laminating apparatus and a semiconductor package manufacturing method using the same are provided. The laminating apparatus includes a substrate pedestal on which a substrate is disposed, a convex surface opposite to an upper surface of the substrate pedestal on the substrate pedestal, and an expandable pressing unit, a plate connected to the pressing unit to inject air into the pressing unit, and a substrate; and a film providing part providing a film between the pressing part, and the pressing part attaching the film on the substrate while expanding.

The crystal covered chip encapsulating products and its manufacture craft of a kind of unused conducting resinl

一种未使用导电胶的覆晶芯片封装产品及其制作工艺，属于RFID技术领域。本发明用于芯片与基板的覆晶接合结构上,在基板上预长金属粒子（金属珠）做为IC芯片凸块接点或厚垫接点（即Bump或PAD），与基板接点形成电气导通的材料，取代以往使用的ACP(或ACF)内的导电粒子做为芯片与基板电气导通的材料；再使用一般不导电的结构胶（不含导电粒子,不导电材料,加热固化型的胶或UV固化的胶），取代以往使用的异方性导电胶(ACP or ACF)；在工艺上,使用Flip chip bonding(覆晶封装),在热压时使用140℃‑360℃的温度。

Film for flip chip type semiconductor back surface and its use

본 발명은, 피착체 상에 플립 칩 접속되는 반도체 소자의 이면에 설치되는 플립 칩형 반도체 이면용 필름으로서, 접착제층과, 이 접착제층 상에 적층된 보호층을 구비하고, 상기 보호층은, 유리전이온도가 200℃ 이상인 내열성 수지 또는 금속으로 구성되어 있는 플립 칩형 반도체 이면용 필름에 관한 것이다. A flip chip type semiconductor backing film provided on a back surface of a semiconductor element which is flip-chip connected on an adherend, comprising: an adhesive layer; and a protective layer laminated on the adhesive layer, And a flip chip type semiconductor backside film composed of a heat resistant resin or metal having a transition temperature of 200 DEG C or higher.

Film for flip chip type semiconductor back surface and application thereof

本发明涉及倒装芯片型半导体背面用膜及其用途。本发明涉及倒装芯片型半导体背面用膜，其要设置于倒装芯片连接至被粘物上的半导体元件背面上，所述倒装芯片型半导体背面用膜包括粘合剂层和层压于粘合剂层上的保护层，其中保护层由具有玻璃化转变温度为200℃以上的耐热性树脂构成或由金属构成，其中所述倒装芯片型半导体背面用膜为卷绕成卷形物的形式。

Film for semiconductor back surface,dicing tape-integrated film for semiconductor back surface, method for producing semiconductor device, and semiconductor device

本发明涉及倒装芯片型半导体背面用膜、半导体背面用切割带集成膜、用于生产半导体器件的方法和倒装芯片型半导体器件。本发明涉及一种倒装芯片型半导体背面用膜，其在倒装芯片连接至被粘物上的半导体元件背面上形成，其中热固化前的倒装芯片型半导体背面用膜在其热固化时，在23℃-165℃范围内的体积收缩率为100ppm/℃-400ppm/℃。

Electronic component mounting body, electronic component, board

Packaging through pre-formed metal pins

一种封装件包括第一封装组件和第二封装组件。第一封装组件包括位于第一封装组件的表面处的第一电连接件以及位于第一电连接件的表面上的第一焊料区域。第二封装组件包括位于第二封装组件的表面处的第二电连接件以及位于第二电连接件的表面上的第二焊料区域。金属引脚具有接合至第一焊料区域的第一末端和接合至第二焊料区域的第二末端。本发明的也提供了通过预形成的金属引脚的封装。

Dicing tape integrated adhesive sheet, manufacturing method of semiconductor device using dicing tape integrated adhesive sheet, and semiconductor device

본 발명의 과제는 반도체 장치의 제조 공정에 있어서, 반도체 칩 위의 회로가 파괴되어버리는 것을 방지하는 것이 가능한 다이싱 테이프 일체형 접착 시트를 제공하는 것이다. 상기 과제를 해결하기 위해서, 기재 위에 점착제층이 적층된 다이싱 테이프와, 점착제층 위에 형성된 접착 시트를 갖는 다이싱 테이프 일체형 접착 시트이며, 박리 속도 10m/분, 박리 각도 150°에서의 박리 시험에 있어서의, 점착제층과 접착 시트의 박리력이 0.02 내지 0.5N/20㎜이며, 박리 시험에 의한 조건에 따라 점착제층과 접착 시트를 박리하였을 때의 박리 대전압의 절댓값이 0.5㎸ 이하인 다이싱 테이프 일체형 접착 시트를 제공한다. An object of the present invention is to provide a dicing tape-integrated adhesive sheet capable of preventing a circuit on a semiconductor chip from being destroyed in the manufacturing process of a semiconductor device. In order to solve the above problem, a dicing tape having a pressure-sensitive adhesive layer laminated on a substrate and a dicing tape-integrated adhesive sheet having an adhesive sheet formed on the pressure-sensitive adhesive layer, in a peeling test at a peeling speed of 10 m / min and a peeling angle of 150 °. The dicing tape in which the peeling force between the pressure-sensitive adhesive layer and the adhesive sheet is 0.02 to 0.5 N / 20 mm, and the absolute value of the peeling voltage when peeling the pressure-sensitive adhesive layer and the adhesive sheet according to the conditions of the peeling test is 0.5 MPa or less. An integral adhesive sheet is provided.

Manufacturing method of semiconductor device

Manufacturing method of semiconductor device

Adhesive film for semiconductor device, film for back surface of flip-chip semiconductor and dicing-tape-integrated film for back surface of flip-chip semiconductor

본 발명은 장기간 보존된 후에 있어서도, 제조 시와 마찬가지의 물성을 갖는 것이 가능한 반도체 장치용 접착 필름을 제공한다. 이를 해결하기 위하여, 열경화성 수지를 함유하고, 시차 주사 열량계에 의해 측정되는 반응 발열 피크 온도의 ±80℃의 온도 범위에서의 반응 발열량이, 25℃의 조건 하에서 4주일 보존한 후에 있어서, 보존 전의 반응 발열량에 대하여 0.8 내지 1배의 범위인 반도체 장치용 접착 필름을 제공한다. The present invention provides an adhesive film for a semiconductor device capable of having the same physical properties as those at the time of production even after long-term storage. In order to solve this problem, after the reaction calorific value of the reaction exothermic peak temperature measured by the differential scanning calorimeter and including the thermosetting resin in the temperature range of 占 80 占 폚 was stored for 4 weeks under the condition of 25 占 폚, And an adhesive film for a semiconductor device in the range of 0.8 to 1 times the amount of heat generated.

Film for flip chip type semiconductor back surface, and its use

본 발명은 피착체 상에 플립칩 접속되는 반도체 소자의 이면에 배치되는 플립칩형 반도체 이면용 필름으로서, 수지 및 열전도성 충전재를 포함하고, 상기 열전도성 충전재의 함유량이 상기 필름의 50 체적% 이상이며, 상기 필름의 두께에 대하여, 상기 열전도성 충전재의 평균 입경이 30% 이하의 값이고, 또한 최대 입경이 80% 이하의 값인 플립칩형 반도체 이면용 필름을 제공한다.

Method for manufacturing element chip and method for manufacturing electronic component mounting structure

本发明提供一种元件芯片的制造方法和电子部件安装结构体的制造方法。在将在元件区域形成了元件电极露出的凸部的基板进行分割来制造多个元件芯片(10)的元件芯片的制造方法中，通过蚀刻将基板进行分割后，使元件芯片(10)暴露于第2等离子体(P2)，由此在元件芯片(10)的第2面(10b)、侧面(10c)、空隙部(S)的第1面(10a)，形成由氟碳膜构成的保护膜，接下来使元件芯片(10)暴露于第3等离子体(P3)，由此使形成于空隙部(S)的保护膜的至少一部分残留，去除形成在元件芯片(10)的第2面(10b)、侧面(10c)的保护膜。由此，通过残留的保护膜来抑制安装过程中的导电性材料的爬升。

Flip chip packaging product without conductive adhesive and manufacturing process thereof

一种未使用导电胶的覆晶芯片封装产品及其制作工艺，属于RFID技术领域。本发明用于芯片与基板的覆晶接合结构上,在基板上预长金属粒子（金属珠）做为IC芯片凸块接点或厚垫接点（即Bump或PAD），与基板接点形成电气导通的材料，取代以往使用的ACP(或ACF)内的导电粒子做为芯片与基板电气导通的材料；再使用一般不导电的结构胶（不含导电粒子,不导电材料,加热固化型的胶或UV固化的胶），取代以往使用的的异方性导电胶(ACP or ACF)；在工艺上,使用Flip chip bonding(覆晶封装),在热压时使用140℃‑360℃的温度。