Kontaktsystem mit einem Verbindungsmittel und Verfahren

Die Erfindung betrifft ein Kontaktsystem. Das Kontaktsystem umfasst wenigstens ein insbesondere elektronisches Bauelement. Das Bauelement weist wenigstens einen elektrischen Anschluss auf. Das Kontaktsystem weist wenigstens eine elektrisch leitfähige Schicht auf. Der Anschluss des Bauelements und die elektrisch leitfähige Schicht sind mittels eines elektrisch leitfähigen Verbindungsmittels miteinander verbunden. Erfindungsgemäß ist das elektrisch leitfähige Verbindungsmittel zum Teil mittels eines thermischen Spritzverfahrens und zum Teil mittels Galvanisieren erzeugt.

Package-Struktur und Verfahren

In einer Ausführungsform umfasst eine Vorrichtung: ein Substrat mit einer ersten Seite und einer zweiten Seite gegenüber der ersten Seite; eine Verbindungsstruktur benachbart zu der ersten Seite des Substrats; und eine IC-Vorrichtung, welche an der Verbindungsstruktur befestigt ist; eine Durchkontaktierung, welche sich von der ersten Seite des Substrats bis zu der zweiten Seite des Substrats erstreckt, wobei die Durchkontaktierung mit der IC-Vorrichtung elektrisch verbunden ist; eine Under-Bump-Metallurgie (UBM) benachbart zu der zweiten Seite des Substrats und die Durchkontaktierung kontaktierend; einen leitfähigen Höcker auf der UBM, wobei es sich bei dem leitfähigen Höcker und der UBM um ein durchgängiges leitfähiges Material handelt, wobei der leitfähige Höcker von der Durchkontaktierung seitlich versetzt ist; und eine Unterfüllung, welche die UBM und den leitfähigen Höcker umgibt.

Substrat-Bondingstruktur und Substrat-Bondingverfahren

Eine Vorrichtung (2) ist auf einer Hauptoberfläche eines Substrats (1) ausgebildet. Die Hauptoberfläche des Substrats (1) ist über das Bonding-Bauteil (11, 12, 13) in einem hohlen Zustand an die Unterseite des Gegensubstrats (14) gebondet. Eine Schaltung (17) und eine Höckerstruktur (26) sind auf der Oberseite des Gegensubstrats (14) ausgebildet. Die Höckerstruktur (26) ist in einem Bereich positioniert, der zumindest dem Bonding-Bauteil (11, 12, 13) entspricht, und weist eine größere Höhe als diejenige der Schaltungsstruktur (17) auf.

Leistungshalbleiterchip mit zwei Metallschichten auf einer Fläche

Ein Halbleiterchip beinhaltet eine Leistungstransistorschaltung mit mehreren aktiven Transistorzellen. Eine erste Lastelektrode und eine Steuerelektrode sind auf einer ersten Fläche des Halbleiterchips angeordnet, wobei die erste Lastelektrode eine erste Metallschicht beinhaltet. Eine zweite Lastelektrode ist auf einer zweiten Fläche des Halbleiterchips angeordnet. Eine zweite Metallschicht ist über der ersten Metallschicht angeordnet, wobei die zweite Metallschicht elektrisch gegenüber der Leistungstransistorschaltung isoliert ist und die zweite Metallschicht über einen Bereich der Leistungstransistorschaltung angeordnet ist, der mindestens eine der mehreren aktiven Transistorzellen umfasst.

Method for manufacturing DCB substrate for e.g. power semiconductor component in power converter, involves electroplating metal film on metallization layer and around cover so as to form pocket at desired position of power component

The method involves providing an electrically non-conductive insulating material body (1). A structured electrically conductive metallization layer (2a) is applied on a side (15a) of the body. An electrically non-conductive cover (3) is applied on the metallization layer at a desired position of a power semiconductor component. A metal film is electroplated on the metallization layer and around the cover so as to form a pocket at a desired position of the semiconductor component. The cover is removed. Independent claims are also included for the following: (1) a substrate for a power semiconductor component (2) a power semiconductor module.

Anordnung mit drei Halbleiterchips und Herstellung einer solchen Anordnung

Anordnung, umfassend:einen ersten Halbleiterchip, der eine erste Kontaktstelle auf einer ersten Seite umfasst;einen zweiten Halbleiterchip, der eine erste Kontaktstelle auf einer ersten Seite umfasst, wobei der zweite Halbleiterchip über dem ersten Halbleiterchip platziert ist und die erste Seite des ersten Halbleiterchips der ersten Seite des zweiten Halbleiterchips zugewandt ist; genau eine Schicht aus einem elektrisch leitfähigen Material, die zwischen dem ersten Halbleiterchip und dem zweiten Halbleiterchip angeordnet ist, wobei die genau eine Schicht aus einem elektrisch leitfähigen Material die erste Kontaktstelle des ersten Halbleiterchips elektrisch mit der ersten Kontaktstelle des zweiten Halbleiterchips koppelt;eine Passivierungsschicht, die einen Teil der ersten Seite des ersten Halbleiterchips außerhalb der ersten Kontaktstelle überdeckt; undeinen auf der Passivierungsschicht angebrachten dritten Halbleiterchip,wobei der erste und der zweite Halbleiterchip jeweils Leistungs-Halbleiterchips ...

Dreidimensionale integrierte Schaltungsstruktur und Verfahren zu deren Herstellung

Es wird eine dreidimensionale integrierte Schaltungsstruktur bereitgestellt, die ein erstes Dia, eine Trägerschichtdurchkontaktierung und ein Verbindungselement enthält. Das erste Die ist an ein zweites Die mit einer ersten dielektrischen Schicht des ersten Dies und einer zweiten dielektrischen Schicht des zweiten Dies gebunden, wobei eine erste Passivierungsschicht zwischen der ersten dielektrischen Schicht und einer ersten Trägerschicht des ersten Dies liegt und ein erstes Testpad in der ersten Passivierungsschicht eingebettet ist. Die Trägerschichtdurchkontaktierung durchdringt das erste Die und ist elektrisch mit dem zweiten Die verbunden. Das Verbindungselement ist elektrisch mit dem ersten Die und dem zweiten Die durch die Trägerschichtdurchkontaktierung verbunden.

INTEGRIERTES SCHALTUNGSPACKAGE UND VERFAHREN

In einer Ausführungsform weist eine Struktur Folgendes auf: einen ersten integrierten Schaltungsdie, der erste Die-Anschlüsse aufweist; eine erste Dielektrikumsschicht auf den ersten Die-Anschlüssen; erste leitfähige Durchkontaktierungen, die sich durch die erste Dielektrikumsschicht hindurch erstrecken, wobei die ersten leitfähigen Durchkontaktierungen an eine erste Untergruppe der ersten Die-Anschlüsse angeschlossen sind; einen zweiten integrierten Schaltungsdie, der an eine zweite Untergruppe der ersten Die-Anschlüsse mit ersten aufschmelzbaren Anschlüssen gebondet ist; ein erstes Verkapselungsmaterial, das den zweiten integrierten Schaltungsdie und die ersten leitfähigen Durchkontaktierungen umgibt, wobei das erste Verkapselungsmaterial und der erste integrierte Schaltungsdie seitlich angrenzend sind; zweite leitfähige Durchkontaktierungen benachbart zu dem ersten integrierten Schaltungsdie; ein zweites Verkapselungsmaterial, das die zweiten leitfähigen Durchkontaktierungen, das erste ...

HALBLEITERVORRICHTUNG

In einer Halbleitervorrichtung (100), ist eine Wärmeabführungsplatte (2) innerhalb eines Dichtungsharzes (8) eingeschlossen und abgedichtet. Ein Isolierflächenkörper (3) ist derart montiert, dass er in Kontakt mit einer Hauptfläche der Wärmeabführungsplatte (2) innerhalb des Dichtungsharzes (8) steht. Ein Leiterrahmen (4) erstreckt sich von dem Inneren des Dichtungsharzes (8) zu der Außenseite bzw. der äußeren Umgebung des Dichtungsharzes (8), und ist derart angeordnet, dass er in Kontakt mit einer Hauptfläche des Isolierflächenkörpers (3) steht, die der Wärmeabführungsplatte (2) gegenüberliegt. Ein Halbleiterelement (1) ist mit zumindest einem Bereich einer Hauptfläche des Leiterrahmens (4) verbunden, die dem Isolierflächenkörper (3) innerhalb des Dichtungsharzes (8) gegenüberliegt. Die Fläche des Isolierflächenkörpers (3), die in Kontakt mit dem Leiterrahmen (4) steht, ist geneigt und derart abgesenkt, dass sie sich weg von dem Leiterrahmen (4) in einer Endregion erstreckt, die zumindest ...

Packung mit aufgerauter verkapselter Oberfläche zur Förderung einer Haftung

Eine Packung (100), die mindestens einen elektronischen Chip (102), einen ersten wärmeabführenden Körper (104), der thermisch mit einer Hauptoberfläche des mindestens einen elektronischen Chips (102) gekoppelt ist und dafür ausgelegt ist, Wärmeenergie von dem mindestens einen elektronischen Chip (102) abzuführen, ein Kapselungsmittel (108), das mindestens einen Teil des mindestens einen elektronischen Chips (102) und einen Teil des ersten wärmeabführenden Körpers (104) verkapselt, wobei mindestens ein Teil einer Oberfläche des ersten wärmeabführenden Körpers (104) aufgeraut ist.

Leitungsintegrierter Schalter und Verfahren zum Herstellen eines leitungsintegrierten Schalters

Leitungsintegrierter Schalter mit zumindest einem ersten metallischen Flachteil 2, zumindest einen zweiten metallischen Flachteil 8, wobei die Flachteile in einem Überlappungsbereich mit ihren breiten Seiten übereinander angeordnet sind und in dem Überlappungsbereich ein Halbleiterschalter 18 zwischen den Flachteilen 2, 8, die Flachteile 2, 8 schaltend miteinander verbindend, angeordnet ist. Ein einfacher Aufbau ist dadurch möglich, dass zumindest im Überlappungsbereich ein erstes der Flachteile 2 auf einer dem zweiten der Flachteile 8 zugewandten Seite zumindest teilweise mit einer Isolation beschichtet ist, wobei in der Isolation in einem Kontaktbereich 10 eine Ausnehmung vorgesehen ist und der Halbleiterschalter 18 in dem Kontaktbereich 10 mit dem Flachteil 8 elektrisch kontaktiert ist.

Gehäuse eines integrierten Schaltkreises und Verfahren zum Bilden desselben

Eine Ausführungsform einer Gehäuse-auf-Gehäuse(PoP)-Vorrichtung umfasst eine Gehäusestruktur, einen Gehäuseträger und eine Vielzahl von Anschlüssen, die die Gehäusestruktur mit dem Gehäuseträger verbinden. Die Gehäusestruktur umfasst einen Logikchip, der mit einem Speicherchip verbunden ist, eine Formmasse, die den Speicherchip umschließt und eine Vielzahl leitfähiger Stifte, die sich durch die Formmasse hindurch erstrecken. Die Vielzahl der leitfähigen Stifte ist an Kontaktpolstern auf dem Logikchip befestigt.

Leistungshalbleitermodul und Verfahren zur Herstellung eines Leistungshalbleitermoduls

Ein Leistungshalbleitermodul kann einen Träger, einen Leistungshalbleiterchip, der so über dem Träger angeordnet ist, dass eine erste Hauptseite des Leistungshalbleiterchips dem Träger zugewandt ist, einen Kontaktclip, der so über dem Leistungshalbleiterchip angeordnet ist, dass eine zweite, der ersten Hauptseite gegenüberliegende Hauptseite des Leistungshalbleiterchips; dem Kontaktclip zugewandt ist, und ein zwischen der zweiten Hauptseite und dem Kontaktclip angeordnetes Abstandshalterelement umfassen, wobei eine erste Lötverbindung die zweite Hauptseite und das Abstandshalterelement verbindet und wobei eine zweite Lötverbindung das Abstandshalterelement und den Kontaktclip verbindet.

Devices and methods related to radio-frequency filters on silicon-on-insulator substrate

Substrate composite, method and apparatus for bonding substrates

Die Erfindung betrifft ein Verfahren zum Bonden eines ersten Substrats (1) mit einem zweiten Substrat (7) mit folgenden Schritten, insbesondere folgendem Ablauf: - Kontaktierung einer ersten Kontaktfläche (lk) des ersten Substrats (1) mit einer parallel zur ersten Kontaktfläche (lk) ausgerichteten zweiten Kontaktfläche (18k) des zweiten Substrats (7), wodurch eine gemeinsame Kontaktfläche (22) gebildet wird, - Herstellung einer punktuellen, stoffschlüssigen Verbindung zwischen dem ersten Substrat (1) und dem zweiten Substrat (7) außerhalb der gemeinsamen Kontaktfläche (22). Weiterhin betrifft die Erfindung eine korrespondierende Vorrichtung und einen Substratverbund aus einem ersten Substrat (1) und einem zweiten Substrat (7), bei dem eine erste Kontaktfläche (lk) des ersten Substrats (1) mit einer parallel zur ersten Kontaktfläche (lk) ausgerichteten zweiten Kontaktfläche (18k) des zweiten Substrats (7) eine gemeinsame Kontaktfläche (22) bildet, wobei außerhalb der gemeinsamen Kontaktfläche ...

Method for stapling with contact element on a chip with a functional layer with openings for the chip substrate provided contact elements

Die vorliegende Erfindung betrifft ein Verfahren zum Heften von Chips (4) auf ein Substrat (1) an auf einer Oberfläche (1o) des Substrats (1) verteilten Chippositionen (1c) mit folgenden Schritten, insbesondere folgendem Ablauf: -Ausbildung oder Aufbringung einer a) an den Chippositionen (1c) zumindest im Bereich von Kontakten (2) durch Strukturierung freigelegten oder b) durch Freilegung von an der Oberfläche (1o) jeweils an den Chippositionen (1c) zumindest im Bereich der Kontakte (2) nach Ausbildung oder Aufbringung der Funktionsschicht (7) freigelegten Funktionsschicht (7) auf das Substrat (1), -Heften von Chips (4) auf eine Chipkontaktseite (7o) der Funktionsschicht (7) an den Chippositionen (1c) und Kontaktierung der Kontakte (2) über Kontaktelemente (3).

Method for stapling with contact element on a chip with a functional layer with openings for the chip substrate provided contact elements

Die vorliegende Erfindung betrifft ein Verfahren zum Heften von Chips (4) auf ein Substrat (1) an auf einer Oberfläche (1o) des Substrats (1) verteilten Chippositionen ( 1 c) mit folgenden Schritten, insbesondere folgendem Ablauf: Ausbildung oder Aufbringung einer a) an den Chippositionen (lc) zumindest im Bereich von Kontakten (2) durch Strukturierung freigelegten oder b) durch Freilegung von an der Oberfläche (lo) jeweils an den Chippositionen (1c) zumindest im Bereich der Kontakte (2) nach Ausbildung oder Aufbringung der Funktionsschicht (7) freigelegten Funktionsschicht (7) auf das Substrat ( 1 ), Heften von Chips (4) auf eine Chipkontaktseite (7o) der Funktionsschicht (7) an den Chippositionen (1 c) und Kontaktierung der Kontakte (2) über Kontaktelemente (3).

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND ADHESIVE FOR MOUNTING FLIP CHIP

A purpose of the present invention is to provide a method for manufacturing a semiconductor device that can suppress voids and achieve high reliability. An additional purpose of the present invention is to provide an adhesive which is for mounting a flip chip and is used in the method for manufacturing the semiconductor device. The method for manufacturing the semiconductor devices has: a step 1 for positioning a semiconductor chip, having formed thereon a protruding electrode having a tip part formed from solder, on a substrate via an adhesive; a step 2 for heating the semiconductor chip to a temperature at or above the solder melting point, fusion bonding the protruding electrode of the semiconductor chip and an electrode part of the substrate, and also temporarily bonding with the adhesive; and a step 3 for eliminating voids by heating the adhesive in a pressurized atmosphere. The adhesive has an activation energy ?E found by differential scanning calorimetry and the Ozawa method of ...

Redresseur électrique à cristal

Redresseur électrique à cristal

The anisotropic conductive film and connection structure

Wafer level system packaging method and packaging structure

Thermal interface material layer and includes a thermal interface material layer of the stacked package device

Method of manufacturing semiconductor device and semiconductor device

Integrated circuit device and method of producing the same

Semiconductor package and method of manufacturing thereof

Electronic package and fabrication method thereof

Method and system for extending die size and packaged semiconductor devices incorporating the die

Curable flux composition and method of soldering

Multilayer substrate

METHOD OF ASSEMBLING A CHIP IN A FLEXIBLE SUBSTRATE.

A METHOD OF JOINING TWO ELECTRONIC COMPONENTS, FLIP-BY ANNEALING THE UV, OBTAINED ASSEMBLY

A METHOD OF JOINING TWO ELECTRONIC COMPONENTS, FLIP UV BY ANNEALING, RESULTING ASSEMBLY

L'invention concerne un procédé d'assemblage de type Flip-Chip, entre un premier (1) et un deuxième (2) composants comportant chacun des plots de connexion (11, 21) sur une de leurs faces, dites faces d'assemblage, selon lequel on reporte les composants l'un sur l'autre par leurs faces d'assemblage de sorte à réaliser des interconnexions électriques entre les plots du premier et ceux du deuxième composant. Selon l'invention, on réalise une transformation de l'oxyde de cuivre en cuivre par recuit UV, très localement dans l'espacement entre composants au moins autour des zones au droit des plots de connexion. Le procédé selon l'invention peut être utilisé pour n'importe quel composant transparent aux UV, y compris pour des substrats en matière plastique tels que des substrats en PEN ou en PET.

METHOD FOR REALIZATION Of ELEMENTS CHIP HAS PROVIDED WITH GROOVES Of INSERTION OF WIRE

L'invention concerne un procédé de réalisation d'éléments à puce (10) munis d'une rainure (14), comprenant les étapes suivantes : prévoir, sur un substrat d'interconnexion (22), une piste conductrice (26) agencée pour relier une plage de contact d'une face active d'une puce (20) à une zone correspondant à une première paroi de la rainure ; faire croître par électrodéposition un plot de contact (16) sur la piste conductrice au niveau de la zone correspondant à la première paroi de la rainure ; assembler la puce (20) sur le substrat par sa face active de manière qu'une paroi latérale de la puce forme le fond de la rainure ; usiner la puce par sa face arrière parallèlement au substrat en mesurant la distance entre la face arrière de la puce et le plot de contact ; arrêter l'usinage lorsque la distance mesurée atteint une valeur souhaitée ; et assembler par collage une plaque (24) sur la face arrière de la puce de manière à former une deuxième paroi de la rainure.

반도체 패키지 및 그 형성 방법

... 본 발명의 실시예들은 반도체 패키지 및 그 형성 방법을 포함한다. 일실시예는, 제1 다이, 제1 전기 연결부, 및 제1 다이와 제1 전기 연결부에 연결된 제1 재배선층을 포함하는 제1 다이 패키지를 형성하는 단계, 제1 다이 패키지 위에 언더필을 형성하는 단계, 제1 전기 연결부의 일부분을 노출시키기 위해 개구부를 갖도록 언더필을 패터닝하는 단계, 상기 언더필의 개구부 내에서 제1 전기 연결부에 연결된 접합 구조체에 의해 제1 다이 패키지에 제2 다이 패키지를 접합하는 단계를 포함하는 방법이다.

마주보는（ＦＡＣＥ­ＴＯ­ＦＡＣＥ, Ｆ2Ｆ） 하이브리드 구조를 갖는 집적 회로(ＩＣ), ＩＣ 조립체, ＩＣ 제품 및 이들을 제조하는 방법, 그리고 이를 위한 컴퓨터-판독가능 매체

... 재분배 층(RDL)을 포함하는 집적 회로(IC) 제품이 제공되며, 재분배 층(RDL)은 IC 내에서 전기적 정보를 하나의 위치로부터 또 하나의 위치로 분배하도록 구성된 적어도 하나의 전도성 층을 갖는다. RDL은 또한 복수의 와이어 본드 패드들 및 복수의 솔더 패드들을 포함한다. 복수의 솔더 패드들 각각은 RDL과 직접적으로 전기적 통신을 하는 솔더 가용성 물질을 포함한다.

핫 스팟 열 관리 특징부를 갖춘 3ＤＩＣ 패키징

... 패키지는 전도성 층을 갖는 기판을 포함하며, 전도성 층은 노출된 부분을 포함한다. 다이 스택은 기판 위에 배치되며, 전도성 층에 전기적으로 접속된다. 고 열전도성 재료가 기판 위에 배치되며 전도성 층의 노출된 부분과 접촉한다. 패키지는 또한, 고 열전도성 재료 위에 있고 고 열전도성 재료와 접촉하는 콘투어 링을 포함한다.

디바이스 다이의 링 구조물

... 다이는 금속 패드, 금속 패드 위에 패시베이션 층 및 패시베이션 층 위에 폴리머 층을 포함한다. 금속 필라가 전기적으로 금속 패드에 위에서 연결된다. 금속 링은 상기 금속 필라와 동일 평면 상에 있다. 상기 폴리머 층은 금속 필라 및 금속 링과 동일 평면 상의 부분을 포함한다.

Substrate of Semiconductor Package, Semiconductor Package including the same and Stack Package using the same

개선된 인터커넥트 대역폭을 갖는 적층된 반도체 디바이스 패키지

... 본 개시는 적층된 반도체 디바이스 패키지 및 연관 기술들 및 구성들의 실시예들을 설명한다. 패키지는, 인터커넥트들, 및 일 측면에 부착되는 제 1 반도체 디바이스 및 대향 측면에 부착되는 제 2 반도체 디바이스를 갖는 패키징 기판을 포함할 수 있다. 디바이스들은, 패드 측면들이 기판의 대향하는 측면들 상에서 서로를 향하는 플립 칩 구성으로 부착될 수 있다. 디바이스들은 인터커넥트들에 의해 전기적으로 커플링될 수 있다. 디바이스들은 기판 상의 팬아웃 패드들에 전기적으로 커플링될 수 있다. 유전체 층은 기판의 제 2 측면에 커플링되고 제 2 디바이스를 캡슐화할 수 있다. 비아들은 전기 신호들을, 유전체 층을 통해 팬아웃 영역으로부터 그리고 유전체 층에 커플링된 재분배 층으로 라우팅할 수 있다. 다른 실시예들이 설명 및/또는 주장될 수 있다.

PROCESS TO ALLOW ELECTRICAL AND MECHANICAL CONNECTION OF AN ELECTRICAL DEVICE WITH A FACE EQUIPPED WITH CONTACT PADS

A method of manufacturing an electrical device that is electrically and mechanically connectable to another electrical device, the electrical device having a face equipped with contact pads, the method being characterised in that it includes:- a layer-application step in which an adhesive layer is applied on the face equipped with contact pads, the adhesive layer being composed of a substance with adhesive properties; - an opening-creation step in which an opening is created through the adhesive layer at the level of a contact pad; - an opening-filing step in which the opening is filled with a conductive material so that the opening is substantially filled with the conductive material so as to form a conductive path the volume of which is defined by the opening. © KIPO & WIPO 2007 ...

SEMICONDUCTOR DEVICE WITH A SOLDER BUMP AND METHODS FOR MANUFACTURING THE SEMICONDUCTOR DEVICE AND A WIRING SUBSTRATE

PURPOSE: A semiconductor device and methods for manufacturing the same and a wiring substrate are provided to precisely form a solder layer on a desirable area of a wiring pad by forming the solder layer using a patterned photoresist layer. CONSTITUTION: An electrode pad(9) is formed on a semiconductor substrate(5). A passivation film(6) covers the semiconductor substrate and the periphery of the electrode pad. A contact layer(7) and a seed metal layer(8) are formed on the electrode pad in order. A barrier metal layer(2) and a solder layer(3) are formed on the seed metal layer in order. A stopper film(4) is formed on the upper part of the barrier metal layer. COPYRIGHT KIPO 2013 ...

이방 도전성 필름 및 접속 구조체

... 이방 도전성 필름 (1A, 1B) 이, 절연 접착제층 (10) 과 그 절연 접착제층 (10) 에 격자상으로 배치된 도전 입자 (P) 를 포함한다. 임의의 도전 입자 (P0) 와 그 도전 입자 (P0) 에 인접하는 도전 입자의 중심간 거리에 대해, 도전 입자 (P0) 와 가장 짧은 거리를 제 1 중심간 거리 (d1) 로 하고, 그 다음으로 짧은 거리를 제 2 중심간 거리 (d2) 로 한 경우에, 이들 중심간 거리 (d1, d2) 가, 각각 도전 입자의 입자경의 1.5 ∼ 5 배이고, 임의의 도전 입자 (P0) 와, 그 도전 입자 (P0) 와 제 1 중심간 거리에 있는 도전 입자 (P1) 와, 그 도전 입자 (P0) 와 제 1 중심간 거리 (d1) 또는 제 2 중심간 거리 (d2) 에 있는 도전 입자 (P2) 로 형성되는 예각 삼각형에 대해서, 도전 입자 (P0, P1) 를 통과하는 제 1 배열 방향 (L1) 에 대하여 직교하는 직선 (L0) 과, 도전 입자 (P1, P2) 를 통과하는 제 2 배열 방향 (L2) 이 이루는 예각의 각도 (α) 가 18 ∼ 35°이다. 이 이방 도전성 필름 (1A, 1B) 은, COG 접속에 있어서도 안정된 접속 신뢰성을 갖는다.

리세싱된 엣지들을 갖는 반도체 디바이스 및 그 제조방법

... 패키지 엣지를 따라 리세싱된 영역들을 활용하는 디바이스 및 제조 방법이 제공된다. 예를 들어, 집적형 팬 아웃 패키지에 있어서, 단품화 이후 유전체층들이 다이의 엣지들로부터 리세싱 백(recessed back)되도록, 유전체층들, 예컨대 재분배층들의 폴리머층들은 스크라이브 라인을 따라 제거된다. 모서리 영역들은 더욱 리세싱될 수 있다. 리세싱된 영역들은 삼각형, 둥근형, 또는 이와 다른 형상일 수 있다. 몇몇의 실시예들에서, 하나 이상의 모서리 영역들은 남아있는 모서리 영역들에 비해 더욱 리세싱될 수 있다. 재분배층들은 전측면 재분배층들과 후측면 재분배층들 중 하나 또는 이 둘 모두를 따라 리세싱될 수 있다.

SEMICONDUCTOR PACKAGE CAPABLE OF PREVENTING A DEFLECTION PHENOMENON DUE TO VOLUME EXPANSION AND CONTRACTION OF A SEMICONDUCTOR CHIP AND A METHOD FOR MANUFACTURING THE SAME

PURPOSE: A semiconductor package and a method for manufacturing the same are provided to improve mounting reliability by improving bonding power between a substrate and semiconductor chips. CONSTITUTION: A substrate(100) comprises a connection terminal(102) having a groove(H) on the surface. Nano-powder(104) is arranged at the bottom of the connection terminal. The nano-powder comprises either copper or silver. A semiconductor chip(110) is flip-chip-bonded on the substrate by the medium of a connection member. The connection member comprises a bonding pad(112) and a bump(114) arranged on the bonding pad. Filler(108) is placed between the substrate and the semiconductor chip. The connection member is inserted in an opening of the filler. COPYRIGHT KIPO 2012 ...

DIE BOND FILM AND THE USE CAPABLE OF IMPROVING WORKABILITY IN WIRE BONDING PROCESS OR SEALING PROCESS AND DISPLAYING ENOUGH SHEAR BOND STRENGTH IN POST-CURE AT HIGH TEMPERATURE

PURPOSE: A die bond film and the use are provided to prevent voids formation at the border of the die bond film and adherent. CONSTITUTION: A die bond film(3) includes glycidyl group contained acrylic copolymer having an average molecular weight of 500,000 and phenol resin. The weight ratio of phenol resin having the content of the glycidyl group contained acrylic copolymer to the phenol resin is 5-30. The die bond film does not include epoxy resins having the average molecular weight of 5000 or less. The die bond film has the epoxy value of 0.15-0.65 e.q.kg based on the glycidyl group-contained acrylic copolymer and the glass transition point of (-15)-40 deg. Celsius. Moreover, the storage modulus of the die bond film at 150 deg. Celsius is 0.1 MPa or greater. COPYRIGHT KIPO 2013 ...

MULTI-CHIP SEMICONDUCTOR PACKAGE AND A METHOD FOR FORMING THE SAME CAPABLE OF IMPROVING PRODUCTION EFFICIENCY

PURPOSE: A multi-chip semiconductor package and a method for forming the same are provided to reduce a chip crack by using an insulating layer, a protrusion electrode, and an interconnection. CONSTITUTION: A first semiconductor chip(11) having a first protrusion electrode(17) is formed on the upper surface. A second semiconductor chip(21) having a second protrusion electrode(27) is formed on the first semiconductor chip. An insulating layer(8) is formed between the first protrusion electrode and the second protrusion electrode. A groove is formed on the insulating layer. The first protrusion electrode is interconnected with the second protrusion electrode by filling the groove. COPYRIGHT KIPO 2013 ...

저온 부착을 위한 하이브리드 인터커넥트

... 증가된 z 높이 및 감소된 리플로우 온도를 갖는 인터커넥트에 관한 장치, 프로세스 및 시스템이 본 명세서에 기술되어 있다. 실시예들에서, 인터커넥트는 솔더 볼을 기판에 접속하기 위해 솔더 볼 및 솔더 페이스트를 포함할 수 있다. 솔더 볼 및/또는 솔더 페이스트는 상대적으로 낮은 용융점을 갖는 합금 및 상대적으로 높은 용융점을 갖는 합금으로 구성될 수 있다.

Preparation method of semiconductor device, and semiconductor device

Chip package structure and manufacturing method thereof

"chip semicondutor módulo de cristal líquido e estrutura de montagem do chip semicondutor"

Heterogeneous chip integration with low loss interconnection through adaptive patterning

Integrating a semiconductor component with a substrate through a low loss interconnection formed through adaptive patterning includes forming a cavity in the substrate, placing the semiconductor component therein, filling a gap between the semiconductor component and substrate with a fill of same or similar dielectric constant as that of the substrate and adaptively patterning a low loss interconnection on the fill and extending between the contacts of the semiconductor component and the electrical traces on the substrate. The contacts and leads are located and adjoined using an adaptive patterning technique that places and forms a low loss radio frequency transmission line that compensates for any misalignment between the semiconductor component contacts and the substrate leads.

Packaging structure for thinned wafer and method for manufacturing the same

A packaging structure for thin die is provided. The packaging structure have a substrate, a thin die, a strengthen layer and an encapsulation body. The thin die is disposed on and electrically connected with the substrate; the strengthen layer is disposed on the thin die; the encapsulation body is formed on the substrate and covers both the thin die and the strengthen layer. The strengthen layer can bear the pressure or stress during the formation of the encapsulation body to protect the thin die. A method for manufacturing a packaging structure for thin die is further provided to manufacture the above packaging structure for thin die.

Semiconductor packages

Semiconductor packages are provided. One of the semiconductor packages includes a first chip, a second chip and a molding compound. The first chip has at least one first via and a protection layer thereon, and the at least one first via is formed in the protection layer. The second chip has at least one second via thereon. The molding layer encapsulates the first and second chips. The at least one second via is disposed in and contact with the molding layer, and top surfaces of the protection layer, the at least one first via and the at least one second via are substantially coplanar with a top surface of the molding layer.

Chip package and method for forming the same

An embodiment of the invention provides a chip package which includes: a first substrate; a second substrate disposed on the first substrate, wherein the second substrate includes a lower semiconductor layer, an upper semiconductor layer, and an insulating layer therebetween, and a portion of the lower semiconductor layer electrically contacts with at least one pad on the first substrate; a conducting layer disposed on the upper semiconductor layer of the second substrate and electrically connected to the portion of the lower semiconductor layer electrically contacting with the at least one pad; an opening extending from the upper semiconductor layer towards the lower semiconductor layer and extending into the lower semiconductor layer; and a protection layer disposed on the upper semiconductor layer and the conducting layer, wherein the protection layer extends onto a portion of a sidewall of the opening, and does not cover the lower semiconductor layer in the opening.

Thermosetting adhesive film, adhesive film with dicing film, and method for fabricating semiconductor device using said thermosetting adhesive film or said adhesive film with dicing film

Provided is a thermosetting adhesive film whose constitution contains no filler substantially, and the thermosetting adhesive film is capable of preventing damage of a semiconductor chip caused by pressure during die bonding. The thermosetting adhesive film also can prevent reduction of tensile elastic modulus, and simultaneously avoid warpage resulting from thermal contraction during thermosetting, thereby enhancing packaging reliability. The thermosetting adhesive film is utilized during the fabrication of a semiconductor device, wherein a tensile storage elastic modulus at 260 DEG C after thermosetting is 2*105Pa to 5*107Pa, a content of the filler is less than or equal to 0.1 wt% as compared with entirety of the thermosetting adhesive film, and a thickness is 1 m to 10 m.

Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate

A microelectronic package 100 includes a microelectronic element 101 having a memory storage array. Terminals 104 on a surface 110 of a substrate 102 are configured for connection to an external component. Substrate contacts 121 exposed at an opposite surface 108 of the substrate 102 face and are joined to element contacts 111 of the microelectronic element 101. The terminals can include first terminals 104 arranged at positions within first and second sets 114, 124 thereof disposed on respective opposite sides of a theoretical axis 132. Each set of first terminals 104 can be configured to carry address information usable by circuitry within the microelectronic package 100 to determine an addressable memory location in the memory storage array. The signal assignments of the first terminals 104 in the first set 114 can be a mirror image of the signal assignments of the first terminals in the second set 124.

Semiconductor device and method of manufacturing semiconductor device

A semiconductor device includes a semiconductor element; a pad electrode that is formed on the semiconductor element; an alignment mark that is formed on the semiconductor element; a connection electrode that is formed on the pad electrode; and an underfill resin that is formed to cover the connection electrode. The height of the alignment mark from the semiconductor element is greater than that of the connection electrode.

Microelectronic assemblies with cavities, and methods of fabrication

Die (110) are attached to an interposer (420), and the interposer/die assembly is placed into a lid cavity (510). The lid (210) is attached to the top of the assembly, possibly to the encapsulant (474) at the top. The lid's legs (520) surround the cavity and extend down below the top surface of the interposer's substrate (420S), possibly to the level of the bottom surface of the substrate or lower. The legs (520) may or may not be attached to the interposer/die assembly. In fabrication, the interposer wafer (420SW) has trenches (478) which receive the lid's legs during the lid placement. The interposer wafer is later thinned to remove the interposer wafer portion below the legs and to dice the interposer wafer. The thinning process also exposes, on the bottom, conductive vias (450) passing through the interposer substrate. Other features are also provided.

Die encapsulation in oxide bonded wafer stack

Structures and methods of fabricating semiconductor wafer assemblies that encapsulate one or die in a cavity etched into an oxide bonded semiconductor wafer stack. The methods generally include the steps of positioning the die in the cavity, mechanically and electrically mounting the die to the wafer stack, and encapsulating the die within the cavity by bonding a lid wafer to the wafer stack in one of multiple ways. Semiconductor processing steps are applied to construct the assemblies (e.g., deposition, annealing, chemical and mechanical polishing, etching, etc.) and connecting the die (e.g., bump bonding, wire interconnecting, ultrasonic bonding, oxide bonding, etc.) according to the embodiments described above.

Integrated fan-out package

An integrated fan-out package including a die attach film, an integrated circuit component, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit component is disposed on the die attach film and includes a plurality of conductive terminals. The die attach film includes an uplifted edge which raises toward sidewalls of the integrated circuit component. The insulating encapsulation encapsulates the uplifted edge and the integrated circuit component. The redistribution circuit structure is disposed on the integrated circuit component and the insulating encapsulation, and the redistribution circuit structure is electrically connected to the conductive terminals of the integrated circuit component. A method of fabricating the integrated fan-out package is also provided.

Package substrate and its fabrication method

This disclosure provides a package substrate and its fabrication method. The package substrate includes: a molding compound body; a first circuit device having a plurality of first terminals on its top surface and disposed in the molding compound body; a plurality of first conductive vias formed in the molding compound body and connected to the first terminals; a second circuit device having a plurality of second terminals on its top surface and disposed in the molding compound body; a plurality of second conductive vias formed in the molding compound body and connected to the second terminals; and a redistribution layer formed on the molding compound body and having at least one conductive wire which connects the first conductive vias and the second conductive vias; wherein the first terminals have a first depth in the molding compound body, the second terminals have a second depth in the molding compound body, and the first depth is not equal to the second depth.

Method of forming semiconductor structure

Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.

Method for forming the package structure

A method for forming the package structure is provided. The method includes forming a die structure over a first surface of a first substrate, and forming a plurality of electrical connectors below a second surface of the first substrate. The method also includes forming a first protruding structure below the second surface of the first substrate, and the electrical connectors are surrounded by the first protruding structure. The method further includes forming a second protruding structure over a second substrate, and bonding the first substrate to the second substrate. The electrical connectors are surrounded by the second protruding structure, and the first protruding structure does not overlap with the second protruding structure.

Integrated circuit package and method of forming the same

In an embodiment, a device includes: a processor die including circuit blocks, the circuit blocks including active devices of a first technology node; a power gating die including power semiconductor devices of a second technology node, the second technology node larger than the first technology node; and a first redistribution structure including first metallization patterns, the first metallization patterns including power supply source lines and power supply ground lines, where a first subset of the circuit blocks is electrically coupled to the power supply source lines and the power supply ground lines through the power semiconductor devices, and a second subset of the circuit blocks is permanently electrically coupled to the power supply source lines and the power supply ground lines.

Pad structure for enhanced bondability and method of forming the same

Pad structure for enhanced bondability

Various embodiments of the present application are directed towards a pad with high strength and bondability. In some embodiments, an integrated chip comprises a substrate, an interconnect structure, a pad, and a conductive structure. The interconnect structure adjoins the substrate and comprises wires and vias. The wires and the vias are stacked between the pad and the substrate. The conductive structure (e.g., a wire bond) extends through the substrate to the pad. By arranging the wires and the vias between the pad and the substrate, the pad may be inset into a passivation layer of the interconnect structure and the passivation layer may absorb stress on the pad. Further, the pad may contact the wires and the vias at a top wire level. A thickness of the top wire level may exceed a thickness of other wire levels, whereby the top wire level may be more tolerant to stress.

Package and package method thereof

A method includes bonding an antenna substrate to a redistribution structure. The antenna substrate has a first part of a first antenna, and the redistribution structure has a second part of the first antenna. The method further includes encapsulating the antenna substrate in an encapsulant, and bonding a package component to the redistribution structure. The redistribution structure includes a third part of a second antenna, and the package component includes a fourth part of the second antenna.

Manufacturing method of package-on-package structure

Power overlay structure and method of making same

CHIP SCALE PACKAGE AND METHOD OF ASSEMBLING THE SAME

A method of producing a chip scale package is disclosed. The method includes dicing a wafer into a plurality of chip arrays, each array including two or more integrated circuit chips. The method further includes mounting each array on a substrate and dicing each array, attached to the substrate, into individual chip scale packages, each individual chip scale package including only one integrated circuit chip.

Semiconductor device and method of manufacture

METHOD OF FORMING SEMICONDUCTOR DEVICE

Semiconductor device and method of forming an embedded sop fan-out package

Semiconductor package

Package structure and method for manufacturing same

Semiconductor device, method of manufacturing the same, and method of manufacturing wiring board

STACKABLE MOLDED MICROELECTRONIC PACKAGES WITH AREA ARRAY UNIT CONNECTORS

A microelectronic package (290) having a (substrate 230), a microelectronic element (170), e.g., a chip, and terminals (240) can have conductive elements (238) electrically connected with element contacts of the chip and contacts of the substrate. Conductive elements can be electrically insulated from one another for simultaneously carrying different electric potentials. An encapsulant (201) can overlie the first surface (136) of the substrate and at least a portion of a face (672) of the microelectronic element remote from the substrate, and may have a major surface (200) above the microelectronic element. A plurality of package contacts (120, 220, 408, 410, 427) can overlie a face (672) of the microelectronic element remote from the substrate. The package contacts, e.g., conductive masses (410), substantially rigid posts (120, 220), can be electrically interconnected with terminals (240) of the substrate (230), such as through the conductive elements. The package contacts can have top ...

CHIP SUPPORT SUBSTRATE, METHOD FOR SUPPORTING CHIP, THREE-DIMENSIONAL INTEGRATED CIRCUIT, ASSEMBLY DEVICE, AND METHOD FOR MANUFACTURING THREE-DIMENSIONAL INTEGRATED CIRCUIT

The present invention is a chip support substrate provided with a lyophilic region (4) formed on the substrate and holding a chip (3A) using suction, and an electrode (6) formed within the lyophilic region on the substrate, and used for generating electrostatic force on the chip. The present invention is also a method for supporting a chip including: a step for positioning the chip in a lyophilic region of a chip support substrate provided with the lyophilic region, which is formed on the substrate, and an electrode formed within the lyophilic region on the substrate, a fluid (15) being interposed between the chip and the lyophilic region; and a step for generating an electrostatic force on the chip corresponding to the electrode by applying voltage to the electrode.

SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR

Provided is a production method for a semiconductor device in which the respective connecting sections of a semiconductor chip and a wiring circuit board are electrically connected to each other, or for a semiconductor device in which the respective connecting sections of a plurality of semiconductor chips are electrically connected to each other. The production method for a semiconductor comprises a step in which at least one portion of the connecting section is sealed using an adhesive for semiconductors that contains a compound comprising the group represented by formula (1). [In formula (1), R1 indicates an electron-donating group.] ...

METHOD FOR FASTENING CHIPS WITH A CONTACT ELEMENT ONTO A SUBSTRATE PROVIDED WITH A FUNCTIONAL LAYER HAVING OPENINGS FOR THE CHIP CONTACT ELEMENTS

A method for tacking of chips onto a substrate at chip positions which are distributed on a surface of the substrate. The method includes the following steps: formation or application of a function layer onto the substrate, removing the function layer from the substrate at the chip positions at least in the region of contacts to uncover the contacts, tacking chips onto one chip contact side of the function layer at the chip positions and contacting the chips with the contacts via contact elements.

Electronic device, method for manufacturing the electronic device, and electronic apparatus

An electronic device includes: a first circuit board; a second circuit board located above a first region of the first circuit board; a first semiconductor element located above a second region of the first circuit board, which is different from the first region, and above a third region of the second circuit board; a first connection interposed between the first semiconductor element and the second region so as to electrically interconnect the first semiconductor element and the first circuit board; and a second connection interposed between the first semiconductor element and the third region so as to electrically interconnect the first semiconductor element and the second circuit board.

SEMICONDUCTOR DEVICE INCLUDING CONTACT FINGERS ON OPPOSED SURFACES

A land grid array semiconductor device is disclosed which is configured for removable insertion to and from a host device. The land grid array semiconductor device may include a first set of one or more contact fingers on the first surface of the land grid array semiconductor device, and a second set of one or more contact fingers on the second surface of the land grid array semiconductor device. In order to electrically couple the second set of one or more contact fingers, one or more electrical connectors may be provided physically extending between the second set of one or more contact fingers and at least one of the substrate and the at least one semiconductor die.

Package apparatus and manufacturing method thereof

A package apparatus comprises a first conductive wiring layer, a first conductive pillar layer, a first conductive glue layer, an internal component, a second conductive pillar layer, a first molding compound layer and a second conductive wiring layer. The first conductive pillar layer is disposed on the first conductive wiring layer. The first conductive glue layer is disposed on the first conductive wiring layer. The internal component has a first electrode layer and a second electrode layer, wherein the first electrode layer is disposed and electrical connected to the first conductive glue layer. The second conductive pillar layer is disposed on the second electrode layer. Wherein the first conductive wiring layer, the first conductive pillar layer, the first conductive glue layer, the internal component and the second conductive pillar layer are disposed inside the first molding compound layer.

Semiconductor device and manufacturing method of the same

Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes: a bottom package; wherein an area of a contact surface between the conductor and the through via substantially equals a cross-sectional area of the through via, and the bottom package includes: a molding compound; a through via penetrating through the molding compound; a die molded in the molding compound; and a conductor on the through via. An associated method of manufacturing the semiconductor device is also disclosed.

NEW DUAL-GATE TRENCH IGBT WITH BURIED FLOATING P-TYPE SHIELD

A method of manufacturing an insulated gate bipolar transistor (IGBT) device comprising 1) preparing a semiconductor substrate with an epitaxial layer of a first conductivity type supported on the semiconductor substrate of a second conductivity type; 2) applying a gate trench mask to open a first trench and second trench followed by forming a gate insulation layer to pad the trench and filling the trench with a polysilicon layer to form the first trench gate and the second trench gate; 3) implanting dopants of the first conductivity type to form an upper heavily doped region in the epitaxial layer; and 4) forming a planar gate on top of the first trench gate and apply implanting masks to implant body dopants and source dopants to form a body region and a source region near a top surface of the semiconductor substrate.

Semiconductor Bonding Structures and Methods

A system and method for applying an underfill is provided. An embodiment comprises applying an underfill to a substrate and patterning the underfill. Once patterned other semiconductor devices, such as semiconductor dies or semiconductor packages may then be attached to the substrate through the underfill, with electrical connections from the other semiconductor devices extending into the pattern of the underfill.

Simultaneous wafer bonding and interconnect joining

Disclosed are a microelectronic assembly of two elements and a method of forming same. A microelectronic element includes a major surface, and a dielectric layer and at least one bond pad exposed at the major surface. The microelectronic element may contain a plurality of active circuit elements. A first metal layer is deposited overlying the at least one bond pad and the dielectric layer. A second element having a second metal layer deposited thereon is provided, and the first metal layer is joined with the second metal layer. The assembly may be severed along dicing lanes into individual units each including a chip.

LOW COST PACKAGE WARPAGE SOLUTION

Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.

Connection pad for embedded components in PCB packaging

Described herein are printed circuit boards (PCBs), PCB assemblies, and methods of manufacture thereof, which allow free placement of electrical components. The PCBs may have electrical pads that may couple to components through via-based connections and without the use of solder. The electrical components may be physically attached to the PCBs through tight fitting, lamination, and/or the use of adhesives. The distance between adjacent vias may be reduced, as accidental short-circuit risks due to solder bridging and similar effects are mitigated when the soldering process is bypassed. The PCB design and component placement may be flexible as to allow the use of electrical components with custom shape and/or customized terminal placement.

Active energy ray-curable pressure-sensitive adhesive for re-release and dicing die-bonding film

Provided is an active energy ray-curable pressure-sensitive adhesive for re-release, which has a small influence on an environment or a human body, can be easily handled, can largely change its pressure-sensitive adhesiveness before and after irradiation with an active energy ray, and can express high pressure-sensitive adhesiveness before the irradiation with the active energy ray and express high releasability after the irradiation with the active energy ray. The active energy ray-curable pressure-sensitive adhesive for re-release includes an active energy ray-curable polymer (P), in which the polymer (P) includes one of a polymer obtained by causing a carboxyl group-containing polymer (P3) and an oxazoline group-containing monomer (m3) to react with each other, and a polymer obtained by causing an oxazoline group-containing polymer (P4) and a carboxyl group-containing monomer (m2) to react with each other.

Laminated semiconductor substrate, laminated chip package and method of manufacturing the same

In a laminated semiconductor substrate, a plurality of semiconductor substrates are laminated. Each of the semiconductor substrate has a plurality of scribe-groove parts formed along scribe lines. Further, each of the semiconductor substrate has a plurality of device regions insulated from each other and has a semiconductor device formed therein. Further, an uppermost substrate and a lowermost substrate have an electromagnetic shielding layer formed using a ferromagnetic body. The electromagnetic shielding layer is formed in a shielding region except the extending zone. The extending zone is set a part which the wiring electrode crosses, in a peripheral edge part of the device region.

Stitch bump stacking design for overall package size reduction for multiple stack

A method for die stacking is disclosed. In one embodiment a first die is formed overlying a substrate. A first wire is bonded to the first die and to a bond finger of the substrate, wherein the first wire is bonded to the bond finger with a first bond. A first stitch bump is formed overlying the first stitch bond, wherein the first stitch bump is formed from a molten ball of conductive material. A second die is formed overlying the first die. A second wire is bonded to the second die and to the first stitch bump, wherein the second wire is bonded to the first stitch bump with a second bond.

Process for assembling two parts of a circuit

A three-dimensional integrated structure is fabricated by assembling at least two parts together, wherein each part contains at least one metallic line covered with a covering region and having a free side. A cavity is formed in the covering region of each part, that cavity opening onto the metallic line. The two parts are joined together with the free sides facing each other and the cavities in each covering region aligned with each other. The metallic lines are then electrically joined to each other through an electromigration of the metal within at least one of the metallic lines, the electromigrated material filling the aligned cavities.

Multi-chip package with offset die stacking

A semiconductor device has a plurality of stacked semiconductor dice mounted on a substrate. Each die has similar dimensions. Each die has a first plurality of bonding pads arranged along a bonding edge of the die. A first group of the dice are mounted to the substrate with the bonding edge oriented in a first direction. A second group of the dice are mounted to the substrate with the bonding edge oriented in a second direction opposite the first direction. Each die is laterally offset in the second direction relative to the remaining dice by a respective lateral offset distance such that the bonding pads of each die are not disposed between the substrate and any portion of the remaining dice in a direction perpendicular to the substrate. A plurality of bonding wires connects the bonding pads to the substrate. A method of manufacturing a semiconductor device is also disclosed.

Integrated circuit packaging system with stack interconnect and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: forming a connection carrier having base device pads and base interconnect pads on a carrier top side of the connection carrier; connecting a base integrated circuit to the base device pads and mounted over the carrier top side; mounting base vertical interconnects directly on the base interconnect pads; attaching a base package substrate to the base integrated circuit and directly on the base vertical interconnects; forming a base encapsulation on the base package substrate, the base device pads, and the base interconnect pads; and removing a portion of the connection carrier with the base device pads and the base interconnect pads partially exposed opposite the base package substrate.

Integrated circuit packaging system with active surface heat removal and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing an interconnect structure having a structure bottom side, a structure top side, and a cavity, the structure bottom side electrically connected to the structure top side; mounting an integrated circuit entirely within the cavity, the integrated circuit having an active side coplanar with the structure top side; forming an encapsulation partially covering the interconnect structure and the integrated circuit, the encapsulation having an encapsulation top side coplanar with the structure top side and the active side; forming a top re-passivation layer over the structure top side and the encapsulation; and mounting a heat sink over the top re-passivation layer for removing heat from the active side.

Integrated circuit packaging system with warpage control and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit device having chip interconnects; applying an attachment layer directly on the integrated circuit device; attaching a device stiffener to the integrated circuit device with the attachment layer; attaching a chip carrier to the chip interconnects with the device stiffener attached to the integrated circuit device for controlling warpage of the integrated circuit device to prevent the warpage from causing some of the chip interconnects to separate from the chip carrier during attachment of the chip interconnects to the chip carrier; and applying an underfill between the chip carrier and the integrated circuit device for controlling connectivity of all the chip interconnects to the chip carrier.

Flexible underfill compositions for enhanced reliability

Underfill materials for fabricating electronic devices are described. One embodiment includes an underfill composition including an epoxy mixture, an amine hardener component, and a filler. The epoxy mixture may include a first epoxy comprising a bisphenol epoxy, a second epoxy comprising a multifunctional epoxy, and a third epoxy comprising an aliphatic epoxy, the aliphatic epoxy comprising a silicone epoxy. The first, second, and third epoxies each have a different chemical structure. Other embodiments are described and claimed.

Semiconductor package device with a heat dissipation structure and the packaging method thereof

The present invention provide a heat dissipation structure on the active surface of the die to increase the performance of the heat conduction in longitude direction of the semiconductor package device, so that the heat dissipating performance can be improved when the semiconductor package device is associated with the exterior heat dissipation mechanism.

Chip-on-chip structure and manufacturing method therof

According to an embodiment, a chip-on-chip structure includes a first chip, a second chip, the first chip and the second chip being opposite to each other, a first electrode terminal, a second electrode terminal, a bump and a protecting material. The first electrode terminal is provided on the surface of the first chip at the side of the second chip. The second electrode terminal is provided on the surface of the second chip at the side of the first chip. The bump electrically connects the first electrode terminal and the second electrode terminal. The protecting material is formed around the bump between the first chip and the second chip. The protecting material includes a layer made of a material having heat-sensitive adhesive property.

Electronic element unit and reinforcing adhesive agent

It is an object of the present invention to provide an electronic element unit and a reinforcing adhesive agent in which a bonding strength can be improved between an electronic element and a circuit board and a repairing work can be carried out without giving a thermal damage to the electronic element or the circuit board. In an electronic element unit ( 1 ) including an electronic element ( 2 ) having a plurality of connecting terminals ( 12 ) on a lower surface thereof, a circuit board ( 3 ) having a plurality of electrodes ( 22 ) corresponding to the connecting terminals ( 12 ) on an upper surface thereof. The connecting terminals ( 12 ) and the electrodes ( 22 ) are connected by solder bumps ( 23 ), and the electronic element ( 2 ) and the circuit board ( 3 ) are partly bond by a resin bond part ( 24 ) made of a thermosetting material of a thermosetting resin, and a metal powder ( 25 ) is included in the resin bond parts ( 24 ) in a dispersed state. The metal powder ( 25 ) has a melting point lower than a temperature at which the resin bond parts ( 24 ) are heated when a work (a repairing work) is carried out for removing the electronic element ( 2 ) from the circuit board ( 3 ).

Method for Manufacturing Heat Dissipation Bulk of Semiconductor Device

A method for manufacturing a heat dissipation bulk of a semiconductor device including the following steps is described. An electrically conductive layer is formed to cover a surface of a temporary substrate. At least one semiconductor chip is connected to the electrically conductive layer by at least one metal bump, wherein the at least one metal bump is located between the at least one semiconductor chip and the electrically conductive layer. A metal substrate is formed on the electrically conductive layer, wherein the metal substrate fills up a gap between the at least one semiconductor chip and the electrically conductive layer. The temporary substrate is removed.

Tsv for 3d packaging of semiconductor device and fabrication method thereof

The present invention relates to a through silicon via (TSV) for 3D packaging to integrate a semiconductor device and a method for manufacturing the same, and more particularly, to a through silicon via (TSV) for 3D packaging of a semiconductor device that is capable of improving production efficiency, having very high electric conductivity, and minimizing electrical signal delay, without using a carrier wafer by self-aligning substrates in a low temperature state and sequentially bonding a plurality of semiconductor dies (or semiconductor chips), and a method of manufacturing the same.

Semiconductor device and assembling method thereof

A semiconductor device and an assembling method thereof are provided. The semiconductor device includes a chip, a carrier, a plurality of first conductive elements and a plurality of second conductive elements. The chip has a plurality of first pads. The carrier has a plurality of second pads. The second pads correspond to the first pads. Each first conductive element is disposed between one of the first pads and one of the second pads. Each second conductive element is disposed between one of the first pads and one of the second pads. A volume ratio of intermetallic compound of the second conductive elements is greater than a volume ratio of intermetallic compound of the first conductive elements.

Low cost thermally enhanced hybrid bga and method of manufacturing the same

A semiconductor package is formed having a substrate juxtaposed on at least two sides of a semiconductor die. Both the substrate and the semiconductor die are affixed to a conductive layer that draws heat generated during use of the semiconductor package away from the semiconductor die and the substrate. There are also electrical contacts affixed to the substrate and the semiconductor die. The electrical contacts facilitate electrical connection between the semiconductor die, the substrate, and any external devices or components making use of the semiconductor die. The substrate, semiconductor die, and at least a portion of some of the electrical contacts are enclosed by an encapsulating layer insulating the components. Portions of the electrical contacts not enclosed by the encapsulating layer are affixed to an outside device, such as a printed circuit board.

Alignment marks to enable 3d integration

Disclosed are a structure including alignment marks and a method of forming alignment marks in three dimensional (3D) structures. The method includes forming apertures in a first surface of a first semiconductor substrate; joining the first surface of the first semiconductor substrate to a first surface of a second semiconductor substrate; thinning the first semiconductor on a second surface of the first semiconductor substrate to provide optical contrast between the apertures and the first semiconductor substrate; and aligning a feature on the second surface of the first semiconductor substrate using the apertures as at least one alignment mark.

Semiconductor device and method of fabricating the semiconductor device

A semiconductor device includes a first device including a first substrate and a first external connection terminal for connecting outside the first device; a second device stacked on the first device, the second device including a second substrate and a second external connection terminal for connecting outside the second device; an adhesive pattern disposed between the first device and second device, the adhesive pattern disposed in locations other than locations where the first external connection terminal and second external connection terminal are disposed, and the adhesive pattern causing the first device and second device, when stacked, to be spaced apart by a predetermined distance; and a plated layer disposed between and electrically and physically connecting the first external connection terminal and the second external connection terminal.

Semiconductor apparatus, method for manufacturing the same and electric device

A semiconductor apparatus includes: a semiconductor device including a first electrode; a substrate including a second electrode and a recess; and a heat-dissipating adhesive material to set the semiconductor device in the recess so as to arrange the first electrode close to the second electrode, wherein the first electrode is coupled to the second electrode and the heat-dissipating adhesive material covers a bottom surface and at least part of a side surface of the semiconductor device.

Semiconductor device and manufacturing method of the same

A semiconductor device, includes: a wiring substrate, a stacked body mounted on the wiring substrate, an underfill layer filled into gaps between respective semiconductor chips of the stacked body; and a molding body made up of a molding resin covered and formed at outside of the stacked body and so on. The underfill layer is made up of a cured product of a resin material containing an amine-based curing agent, and the cured product has a Tg of 65° C. or more and 100° C. or less.

Method of manufacturing film for semiconductor device

The present invention aims to provides a method of manufacturing a film for a semiconductor device in which a dicing film, a die bond film, and a protecting film are laminated in this order, including the steps of: irradiating the die bond film with a light ray having a wavelength of 400 to 800 nm to detect the position of the die bond film based on the obtained light transmittance and punching the dicing film out based on the detected position of the die bond film, and in which T 2 /T 1 is 0.04 or more, wherein T 1 is the light transmittance of the portion where the dicing film and the protecting film are laminated and T 2 is the light transmittance of the portion where the dicing film, the die bond film, and the protecting film are laminated.

Integrated circuit package system with removable backing element having plated terminal leads and method of manufacture thereof

A method of manufacture of an integrated circuit package system includes: attaching a first die to a first die pad; connecting electrically a second die to the first die through a die interconnect positioned between the first die and the second die; connecting a first lead adjacent the first die pad to the first die; connecting a second lead to the second die, the second lead opposing the first lead and adjacent the second die; and providing a molding material around the first die, the second die, the die interconnect, the first lead and the second lead, with a portion of the first lead exposed.

Semiconductor Device and Method of Making a Semiconductor Device

A semiconductor device and a method of manufacturing a semiconductor device are disclosed. An embodiment comprises forming a bump on a die, the bump having a solder top, melting the solder top by pressing the solder top directly on a contact pad of a support substrate, and forming a contact between the die and the support substrate.

Semiconductor Device and Method of Embedding TSV Semiconductor Die Within Substrate for Vertical Interconnect in POP

A semiconductor device has a substrate with a first conductive layer over a surface of the substrate and a plurality of cavities exposing the first conductive layer. A first semiconductor die having conductive TSV is mounted into the cavities of the substrate. A first insulating layer is formed over the substrate and first semiconductor die and extends into the cavities to embed the first semiconductor die within the substrate. A portion of the first insulating layer is removed to expose the conductive TSV. A second conductive layer is formed over the conductive TSV. A portion of the first conductive layer is removed to form electrically common or electrically isolated conductive segments of the first conductive layer. A second insulating layer is formed over the substrate and conductive segments of the first conductive layer. A second semiconductor die is mounted over the substrate electrically connected to the second conductive layer.

Method of manufacturing chip-stacked semiconductor package

A method of manufacturing a chip-stacked semiconductor package, the method including preparing a base wafer including a plurality of first chips each having a through-silicon via (TSV); bonding the base wafer including the plurality of first chips to a supporting carrier; preparing a plurality of second chips; forming stacked chips by bonding the plurality of second chips to the plurality of first chips; sealing the stacked chips with a sealing portion; and separating the stacked chips from each other.

Layered chip package and method of manufacturing same

A layered chip package includes a main body and wiring. The main body includes: a main part having a top surface and a bottom surface and including three or more layer portions stacked on one another; a plurality of first terminals disposed on the top surface of the main part; and a plurality of second terminals disposed on the bottom surface of the main part. Each layer portion includes a semiconductor chip having first and second surfaces, and a plurality of electrodes electrically connected to the wiring. The plurality of electrodes are disposed on a side of the first surface of the semiconductor chip. A first layer portion located closest to the top surface of the main part and a second layer portion located closest to the bottom surface of the main part are arranged so that the second surfaces of their respective semiconductor chips face toward each other. The plurality of first terminals are formed by using the plurality of electrodes of the first layer portion. The plurality of second terminals are formed by using the plurality of electrodes of the second layer portion.

Semiconductor package

A semiconductor package includes a plurality of connection pads, which are electrically connected to connection terminals of a mounted component that is mounted on the semiconductor package, and recognition marks. The recognition marks are formed respectively within the area of each of at least two of the connection pads. Each recognition mark has an area that is smaller than the area of the connection mark in which it is formed.

Semiconductor device and method for manufacturing same

A dug portion ( 50 ) in which a die-bonding material is filled is provided to a lower surface of a stamping nozzle ( 42 ) used in a step of applying the die-bonding material onto a chip mounting portion of a wiring board. Planar dimensions of the dug portion ( 50 ) are smaller than external dimensions of a chip to be mounted on the chip mounting portion. In addition, a depth of the dug portion ( 50 ) is smaller than a thickness of the chip. When the thickness of the chip is 100 μm or smaller, a problem of crawling up of the die-bonding material to an upper surface of the chip is avoided by applying the die-bonding material onto the chip mounting portion using the stamping nozzle ( 42 ).

Package-on-package structures

Embodiments of the present disclosure provide a package on package arrangement comprising a bottom package and a second package. The first package includes a substrate layer including (i) a top side and (ii) a bottom side that is opposite to the top side. Further, the top side defines a substantially flat surface. The first package also includes a die coupled to the bottom side of the substrate layer. The second package includes a plurality of rows of solder balls, and the second package is attached to the substantially flat surface of the substrate layer via the plurality of rows of solder balls.

Semiconductor Device and Method of Forming Stacked Vias Within Interconnect Structure for FO-WLCSP

A semiconductor device has a semiconductor die mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A first insulating layer is formed over the encapsulant and semiconductor die. First vias are formed through the first insulating layer to expose contact pads of the semiconductor die. A first conductive layer is formed over the first insulating layer and into the first vias to electrically connect to the contact pads of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. Second vias are formed through the second insulating layer by laser direct ablation and aligned or offset with the first vias to expose the first conductive layer. A second conductive layer is formed over the second insulating layer and into the second vias. Conductive vias can be formed through the encapsulant.

Multi-chip semiconductor package and method of fabricating the same

A first semiconductor chip having a first projection electrode formed on an upper surface thereof is prepared. A second semiconductor chip having a second projection electrode is mounted on the first semiconductor chip to expose the first projection electrode. An insulating film is formed between the first projection electrode and the second projection electrode. A groove is formed in the insulating film. An interconnection configured to fill an inside of the groove and connected to the first projection electrode and the second projection electrode is formed.

Curable Amine, Carboxylic Acid Flux Composition And Method Of Soldering

A curable flux composition is provided, comprising, as initial components: a resin component having at least two oxirane groups per molecule; a carboxylic acid; and, an amine fluxing agent represented by formula I: and, optionally, a curing agent. Also provided is a method of soldering an electrical contact using the curable flux composition.

Method Of Manufacturing Package-On-Package (Pop)

A method of manufacturing package-on-packages (POPs) includes: forming a plurality of internal connection members that are separated from each other on a first circuit substrate; forming a first package by attaching a plurality of first chips between the internal connection members on the first circuit substrate; forming a second package by attaching a plurality of second chips that are separated from each other on a second circuit substrate; electrically connecting the first circuit substrate and the second circuit substrate by stacking the internal connection members onto the second circuit substrate; forming an encapsulant to encapsulate the first package and the second package; and forming the POPs in which the first chips and the second chips are respectively formed by cutting the first circuit substrate, the second circuit substrate, and the encapsulant.

System in package process flow

A method comprises connecting a substrate having a plurality of integrated circuit (IC) dies to a package substrate, so that the package substrate extends beyond at least two edges of the substrate, leaving first and second edge portions of the package substrate having exposed contacts. The first and second edge portions meet at a first corner of the package substrate. At least a first upper die package is placed over the substrate, so that first and second edge portions of the first upper die package extend beyond the at least two edges of the substrate. Pads on the first and second edge portions of the first upper die package are connected to the contacts of the first and second edge portions of the package substrate.

Embedded Electrical Component Surface Interconnect

An electrical component package is disclosed comprising: an electrical component having an embedded surface, a structure attached to the electrical component opposite the embedded surface, a conductive adhesive directly attached to the embedded surface, where the conductive adhesive is shaped to taper away from the embedded surface, and an encapsulation material covering the conductive adhesive and the electrical component. In various embodiments, the tapered conductive adhesive facilitates the securing of the conductive adhesive to the electrical component by the encapsulation material. Also disclosed are various methods of forming an electrical component package having a single interface conductive interconnection on the embedded surface. The conductive interconnection is configured to maintain an interconnection while under stress forces. Further disclosed in a method of applied a conductive adhesive that enables design flexibility regarding the shape and depth of the conductive interconnection.

Flip-chip packaging techniques and configurations

Embodiments of the present disclosure flip-chip packaging techniques and configurations. An apparatus may include a package substrate having a plurality of pads formed on the package substrate, the plurality of pads being configured to receive a corresponding plurality of interconnect structures formed on a die and a fluxing underfill material disposed on the package substrate, the fluxing underfill material comprising a fluxing agent configured to facilitate formation of solder bonds between individual interconnect structures of the plurality of interconnect structures and individual pads of the plurality of pads and an epoxy material configured to harden during formation of the solder bonds to mechanically strengthen the solder bonds. Other embodiments may also be described and/or claimed.

Fully molded fan-out

A method for manufacturing a device package may include constructing a spacer element coupled with a surface of a semiconductor die unit, where the spacer element is configured to create a gap between the semiconductor die unit and a surface of a carrier, and encapsulating the semiconductor die unit within a mold compound, where the encapsulating includes introducing the mold compound into the gap.

Probing Chips during Package Formation

A method includes bonding a first package component on a first surface of a second package component, and probing the first package component and the second package component from a second surface of the second package component. The step of probing is performed by probing through connectors on the second surface of the second package component. The connectors are coupled to the first package component. After the step of probing, a third package component is bonded on the first surface of the second package component.

Bonded processed semiconductor structures and carriers

Methods of fabricating semiconductor structures include implanting atom species into a carrier die or wafer to form a weakened region within the carrier die or wafer, and bonding the carrier die or wafer to a semiconductor structure. The semiconductor structure may be processed while using the carrier die or wafer to handle the semiconductor structure. The semiconductor structure may be bonded to another semiconductor structure, and the carrier die or wafer may be divided along the weakened region therein. Bonded semiconductor structures are fabricated using such methods.

Semiconductor chip stack package and manufacturing method thereof

The present invention relates to a semiconductor chip stack package and a manufacturing method thereof, and more particularly, to a semiconductor chip stack package and a manufacturing method thereof in which a plurality of chips can be rapidly arranged and bonded without a precise device or operation so as to improve productivity

Monolithic Power Converter Package

According to an exemplary embodiment, a monolithic power converter package includes a monolithic die over a substrate, the monolithic die integrating a driver integrated circuit (IC) with a control power transistor and a sync power transistor connected in a half-bridge. A high side power input, a low side power input, and a power output of the half-bridge are each disposed on a top surface of the monolithic die. The high side power input is electrically and mechanically coupled to the substrate by a high side power strip. Also, the low side power input is electrically and mechanically coupled to the substrate by a low side power strip. Furthermore, the power output is electrically and mechanically coupled to the substrate by a power output strip.

Circuit device

A circuit device having superior voltage resistance is provided. A structure is achieved that omits the resin layer that is normally provided to the top surface of a circuit board. Specifically, a ceramic substrate ( 22 ) is disposed on the top surface of a circuit board ( 12 ) comprising a metal, and a transistor ( 34 ) such as an IGBT is mounted to the top surface of the ceramic substrate ( 22 ). As a result, the transistor ( 34 ) and the circuit board ( 12 ) are insulated from each other by the ceramic substrate ( 22 ). The ceramic substrate ( 22 ), which comprises an inorganic material, has an extremely high voltage resistance compared to the conventionally used insulating layer comprising resin, and so even if a high voltage on the order of 1000V is applied to the transistor ( 34 ), short circuiting between the transistor ( 34 ) and the circuit board ( 12 ) is prevented.

Production method for polyamide acid particles, production method for polyimide particles, polyimide particles and bonding material for electronic component

An object of the present invention is to provide a method for producing polyamide acid particles which is used as a raw material for polyimide particles with a small average particle diameter having high heat resistance. Other objects of the present invention are to provide a method for producing polyimide particles using the method for producing polyamide acid particles, and polyimide particles produced by the method for producing polyimide particles. Yet another object of the present invention is to provide a bonding material for an electronic component, which has a low linear expansion coefficient and a low elastic modulus after being cured in the temperature range equal to or less than the glass transition temperature, so that a joined body with high reliability can be produced. The present invention is a method for producing polyamide acid particles having a step of preparing a solution having a diamine compound dissolved, and a step of precipitating polyamide acid particles by adding a tetracarboxylic anhydride in a non-solution state to the solution having a diamine compound dissolved while applying a physical impact thereto.

Simultaneous wafer bonding and interconnect joining

Disclosed are a microelectronic assembly of two elements and a method of forming same. A microelectronic element includes a major surface, and a dielectric layer and at least one bond pad exposed at the major surface. The microelectronic element may contain a plurality of active circuit elements. A first metal layer is deposited overlying the at least one bond pad and the dielectric layer. A second element having a second metal layer deposited thereon is provided, and the first metal layer is joined with the second metal layer. The assembly may be severed along dicing lanes into individual units each including a chip.

Electrical module for being received by automatic placement machines by means of generating a vacuum

The invention relates to an electrical module ( 100 ) for being received by automatic placement machines by means of generating a vacuum, comprising a carrier substrate ( 10 ), at least one component ( 20, 21 ) disposed on the carrier substrate ( 10 ), and a cover element ( 30 ) disposed above the at least one component ( 20, 21 ). A fixing component ( 40 ) by which the cover element ( 30 ) is attached to the at least one component ( 21 ) is disposed between the cover element ( 30 ) and the at least one component ( 21 ). The cover element can be implemented as a dimensionally stable, flat film by means of which it is possible to suction the module by means of vacuum for a placement method, and to place said module at a position on a circuit board.

Method of fabricating wafer level package

A method of fabricating a wafer level package includes preparing a wafer including a plurality of first semiconductor chips, mounting a plurality of second semiconductor chips on the wafer, disposing the wafer on a lower mold and disposing an upper mold so as to surround edges of a top surface of the wafer, dispensing a molding member on the wafer, and pressurizing the molding member by using a plunger so as to fabricate a wafer level package in which a top surface of each of the plurality of second semiconductor chips is exposed.

Heatsink attachment module

An assembly process for a heatsink attachment module for a chip packaging apparatus is provided and includes attaching a semiconductor chip to a substrate to form a module subassembly, placing a load frame and shim in a fixture, dispensing adhesive to the load frame and loadably placing the module subassembly chip face down in the fixture.

Wafer-level device packaging

The present invention relates to a semiconductor device packaged at the wafer level such that an entire packaged device is formed prior to separation of individual devices. The semiconductor device package includes a semiconductor chip having one or more bonding pads associated with the chip and a protective layer bonded over the semiconductor chip. An insulation layer is positioned on at least side edges and a lower surface of the semiconductor chip. Interconnection/bump metallization is positioned adjacent one or more side edges of the semiconductor chip and is electrically connected to at least one bonding pad. A compact image sensor package can be formed that is vertically integrated with a digital signal processor and memory chip along with lenses and a protective cover.

Embedded integrated circuit package and method for manufacturing an embedded integrated circuit package

A embedded integrated circuit package is provided, the embedded integrated circuit package including: at least one chip arranged over a chip carrier, the at least one chip including a plurality of chip contact pads; encapsulation material formed over the chip carrier and at least partially surrounding the at least one chip; a plurality of electrical interconnects formed through the encapsulation material, wherein each electrical interconnect is electrically connected to a chip contact pad; and a structure formed between the electrical interconnects of the embedded integrated circuit package, wherein the structure increases the creepage resistance between the electrical interconnects.

Power MOSFET Having Selectively Silvered Pads for Clip and Bond Wire Attach

A packaged power field effect transistor device includes a power field effect transistor die, a DBA substrate, a clip, a wire bond, leads, and an amount of plastic encapsulant. The top of the DBA has a plurality of metal plate islands. A sintered silver feature is disposed on one of the islands. A silvered backside of the die is directly bonded to the sintered silver structure of the DBA. The upper surface of the die includes a first aluminum pad (a source pad) and a second aluminum pad (a gate pad). A sintered silver structure is disposed on the first aluminum pad, but there is no sintered silver structure disposed on the second aluminum pad. A high current clip is attached via soft solder to the sintered silver structure on the first aluminum pad (the source pad). A bond wire is ultrasonically welded to the second aluminum pad (gate pad).

Method of manufacturing semiconductor device

In a semiconductor device formed by mounting a chip laminate including a semiconductor chip having a small diameter and a semiconductor chip having a large diameter over the top surface of a substrate, an excessive stress is prevented from being added to a joint of the two semiconductor chips. By mounting a first semiconductor chip having a large diameter over a support substrate and thereafter mounting a second semiconductor chip having a small diameter over the first semiconductor chip, it is possible to: suppress the inclination and unsteadiness of the second semiconductor chip mounted over the first semiconductor chip; and hence inhibit an excessive stress from being added to a joint of the first semiconductor chip and the second semiconductor chip.

Semiconductor package and method of manufacturing the same

Disclosed herein are a semiconductor package and a method of manufacturing the same, the semiconductor package including: a molding member having a cavity formed therein; a device mounted in the cavity; an insulating member formed inside the cavity and on and/or beneath the molding member and the device; a circuit layer formed on the insulating member, and including vias and connection pads electrically connected with the device; a solder resist layer formed on the circuit layer, and having openings exposing upper portions of the connection pads; and solder balls formed in the openings.

Die connections using different underfill types for different regions

Die connections are described using different underfill types for different regions. In one example, a first electrically-non-conductive underfill paste (NCP) type is applied to an I/O region of a first die. A second NCP type is applied outside the I/O region of the first die, the second NCP type having more filler than the first NCP type, and the second die is bonded to a first die using the NCP.

SEMICONDUCTOR DEVICE PACKAGES AND METHODS OF MANUFACTURING THE SAME

A semiconductor device package includes a semiconductor device, a non-semiconductor substrate over the semiconductor device, and a first connection element extending from the semiconductor device to the non-semiconductor substrate and electrically connecting the semiconductor device to the non-semiconductor substrate. 1. A semiconductor device package , comprising:a semiconductor device;a non-semiconductor substrate over the semiconductor device; anda first connection element extending from the semiconductor device to the non-semiconductor substrate and electrically connecting the semiconductor device to the non-semiconductor substrate.2. The semiconductor device package of claim 1 , further comprising a patterned insulation layer between the semiconductor device and the non-semiconductor substrate.3. The semiconductor device package of claim 2 , wherein the non-semiconductor substrate comprises a through hole claim 2 , the first connection element extending from the semiconductor device into the through hole.4. The semiconductor device package of claim 3 , further comprising a second connection element in the through hole of the non-semiconductor substrate and surrounding the first connection element.5. The semiconductor device package of claim 4 , wherein the second connection element at least partially fills the through hole thereby forming a space between the semiconductor device claim 4 , the patterned insulation layer claim 4 , and the non-semiconductor substrate.6. The semiconductor device package of claim 2 , wherein the first connection element comprises solder material.7. The semiconductor device package of claim 1 , wherein the non-semiconductor substrate further comprises a patterned conductive layer on a surface away from the semiconductor device.8. The semiconductor device package of claim 1 , wherein the non-semiconductor substrate is narrower than the semiconductor device claim 1 , the first connection element extending from the semiconductor device ...

Flat No-Leads Package With Improved Contact Pins

According to an embodiment of the present disclosure, a leadframe for an integrated circuit (IC) device may comprise a center support structure for mounting an IC chip, a plurality of pins extending from the center support structure, and a bar connecting the plurality of pins remote from the center support structure. Each pin of the plurality of pins may include a dimple. 19-. (canceled)10. A method for manufacturing an integrated circuit (IC) device in a flat no-leads package , the method comprising:mounting an IC chip onto a center support structure of a leadframe, the leadframe including:the center support structure;a plurality of pins extending from the center support structure; anda bar connecting the plurality of pins remote from the center support structure;wherein each pin of the plurality of pins includes a dimple;bonding the IC chip to at least some of the plurality of pins;encapsulating the leadframe and bonded IC chip creating an IC package; andcutting the IC package free from the bar by sawing through the encapsulated lead frame at a set of cutting lines intersecting the dimples of the plurality of pins, exposing an end face of each of the plurality of pins and leaving a portion of the dimples that extends from the bottom surface of the IC package to a side surface with the exposed end faces of the pins.11. A method according to claim 10 , further comprising:performing an isolation cut to isolate individual pins of the IC package without separating the IC package from the lead frame; andperforming a circuit test of the isolated individual pins after the isolation cut.12. A method according to claim 10 , further comprising bonding the IC chip to at least some of the plurality of pins using wire bonding.13. A method according to claim 10 , further comprising plating the exposed portion of the plurality of pins claim 10 , including the dimples claim 10 , on a bottom surface of the IC package before cutting the IC package free from the bar.14. A method for ...

NEGATIVE FILLET FOR MOUNTING AN INTEGRATED DEVICE DIE TO A CARRIER

An electronic module is disclosed. The electronic module can include a package substrate, an integrated device die, a dam structure, and a mounting compound. The integrated device die can have an upper side, a lower side, and an outer side edge. The dam structure can have a first sidewall and a second sidewall opposite the first sidewall. The second sidewall can be nearer to the outer side edge than the first sidewall. The first sidewall can be laterally positioned between a center of the lower side of the integrated device die and the outer side edge. The dam structure can be disposed between a portion of the package substrate and a portion of the lower side of the integrated device die. The mounting compound can be disposed between the lower side of the integrated device die and the package substrate. The dam structure can be positioned between the mounting compound and the outer side edge of the integrated device die 1. An electronic module comprising:a package substrate;an integrated device die having an upper side, a lower side, and an outer side edge;a dam structure having a first sidewall and a second sidewall opposite the first sidewall, the second sidewall being nearer to the outer side edge than the first sidewall, the first sidewall being laterally positioned between a center of the lower side of the integrated device die and the outer side edge, the dam structure disposed between a portion of the package substrate and a portion of the lower side of the integrated device die; anda mounting compound disposed between the lower side of the integrated device die and the package substrate, the dam structure positioned between the mounting compound and the outer side edge of the integrated device die.2. The electronic module of claim 1 , wherein the dam structure comprises a non-conductive epoxy.3. The electronic module of claim 1 , wherein the dam structure comprises an hour glass shape.4. The electronic module of claim 1 , wherein the integrated device die ...

Display panel and manufacturing method for same

A display panel having a display region and a non-display region, the display panel includes: a substrate having at least one first opening; an electronic component disposed on the substrate; a plurality of pads disposed in the non-display region and including a first pad and a second pad are spaced apart from each other in a first direction with the at least one first opening therebetween; and an adhesive layer disposed between the substrate and the electronic component and overlapping the at least one first opening.

SEMICONDUCTOR DEVICE AND METHOD FOR MAKING SEMICONDUCTOR DEVICE

A semiconductor device includes: a substrate including a base member having a main surface and a back surface facing opposite in a thickness direction; a semiconductor element mounted on the main surface of the substrate and having at least one element pad; a wire having a bonding portion bonded to the element pad; and a sealing resin formed on the main surface of the substrate for covering the wire and at least a portion of the semiconductor element. The semiconductor element has an element exposed side surface that faces in a direction crossing the thickness direction of the substrate and is exposed from the sealing resin. 1. A semiconductor device comprising:a substrate including a base member having a main surface and a back surface facing opposite in a thickness direction;a semiconductor element having at least one element pad and mounted on the main surface of the substrate;a wire having a bonding portion bonded to the element pad; anda sealing resin formed on the main surface of the substrate, and covering the wire and at least a portion of the semiconductor element,wherein the semiconductor element includes an element exposed surface that faces in a direction crossing the thickness direction of the substrate and is exposed from the sealing resin.2. The semiconductor device according to claim 1 , wherein the base member includes a substrate outer side surface that connects the main surface and the back surface to each other and is flush with the element exposed side surface of the semiconductor element.3. The semiconductor device according to claim 2 , wherein the sealing resin has a sealing resin outer surface flush with both the element exposed side surface of the semiconductor element and the substrate outer side surface of the base member.4. The semiconductor device according to claim 1 , wherein the element exposed side surface of the semiconductor element is perpendicular to the thickness direction of the substrate.5. The semiconductor device according ...

Integrated circuit packages and methods of forming same

An integrated circuit package and a method of forming the same are provided. A method includes forming a conductive column over a carrier. An integrated circuit die is attached to the carrier, the integrated circuit die being disposed adjacent the conductive column. An encapsulant is formed around the conductive column and the integrated circuit die. The carrier is removed to expose a first surface of the conductive column and a second surface of the encapsulant. A polymer material is formed over the first surface and the second surface. The polymer material is cured to form an annular-shaped structure. An inner edge of the annular-shaped structure overlaps the first surface in a plan view. An outer edge of the annular-shaped structure overlaps the second surface in the plan view.

Repackaged integrated circuit assembly method

A method is provided. The method includes one or more of extracting a die from an original packaged integrated circuit, modifying the extracted die, reconditioning the modified extracted die, placing the reconditioned die into a cavity of a hermetic package base, bonding a plurality of bond wires between reconditioned die pads of the reconditioned die to leads of the hermetic package base or downbonds to create an assembled hermetic package base, and sealing a hermetic package lid to the assembled hermetic package base to create a new packaged integrated circuit. Modifying the extracted die includes removing the one or more ball bonds on the one or more die pads. Reconditioning the modified extracted die includes adding a sequence of metallic layers to bare die pads of the modified extracted die. The extracted die is a fully functional semiconductor die with one or more ball bonds on one or more die pads of the extracted die. 1. A method , comprising:extracting a die from an original packaged integrated circuit, wherein the extracted die is a fully functional semiconductor die with one or more ball bonds on one or more die pads of the extracted die;modifying the extracted die, comprising removing the one or more ball bonds on the one or more die pads; 'adding a sequence of metallic layers to bare die pads of the modified extracted die;', 'reconditioning the modified extracted die, comprisingplacing the reconditioned die into a cavity of a hermetic package base;bonding a plurality of bond wires between reconditioned die pads of the reconditioned die to leads of the hermetic package base or downbonds to create an assembled hermetic package base; andsealing a hermetic package lid to the assembled hermetic package base to create a new packaged integrated circuit.2. The method as recited in claim 1 , wherein bare die pads of the modified extracted die comprises all metallic and chemical residue claim 1 , all ball bonds claim 1 , and all bond wires removed from all die ...

Semiconductor backmetal (bm) and over pad metallization (opm) structures and related methods

A method of forming semiconductor devices includes providing a wafer having a first side and second side, electrically conductive pads at the second side, and an electrically insulative layer at the second side with openings to the pads. The first side of the wafer is background to a desired thickness and an electrically conductive layer is deposited thereon. Nickel layers are simultaneously electrolessly deposited over the electrically conductive layer and over the pads, and diffusion barrier layers are then simultaneously deposited over the nickel layers. Another method of forming semiconductor devices includes depositing backmetal (BM) layers on the electrically conductive layer including a titanium layer, a nickel layer, and/or a silver layer. The BM layers are covered with a protective coating and a nickel layer is electrolessly deposited over the pads. A diffusion barrier layer is deposited over the nickel layer over the pads, and the protective coating is removed.

Semiconductor assemblies including vertically integrated circuits and methods of manufacturing the same

Semiconductor assemblies including thermal management configurations for reducing heat transfer between vertically stacked devices and associated systems and methods are disclosed herein. In some embodiments, the semiconductor assemblies comprise at least one memory device mounted over a logic device with a thermally conductive layer, a thermal-insulator interposer, or a combination thereof disposed between the memory device and the logic device. The thermally conductive layer includes a structure configured to transfer the thermal energy across a horizontal plane. The thermal-insulator interposer includes a structure configured to reduce heat transfer between the logic device and the memory device.

SCALABLE PACKAGE ARCHITECTURE AND ASSOCIATED TECHNIQUES AND CONFIGURATIONS

Embodiments of the present disclosure describe scalable package architecture of an integrated circuit (IC) assembly and associated techniques and configurations. In one embodiment, an integrated circuit (IC) assembly includes a package substrate having a first side and a second side disposed opposite to the first side, a first die having an active side coupled with the first side of the package substrate and an inactive side disposed opposite to the active side, the first die having one or more through-silicon vias (TSVs) configured to route electrical signals between the first die and a second die, and a mold compound disposed on the first side of the package substrate, wherein the mold compound is in direct contact with a sidewall of the first die between the active side and the inactive side and wherein a distance between the first side and a terminating edge of the mold compound that is farthest from the first side is equal to or less than a distance between the inactive side of the first die and the first side. Other embodiments may be described and/or claimed. 111-. (canceled)12. A method for fabricating an integrated circuit (IC) assembly , comprising:providing a package substrate having a first side and a second side disposed opposite to the first side;coupling an active side of a first die with the first side of the package substrate, the first die including an inactive side disposed opposite to the active side and one or more through-silicon vias (TSVs) configured to route electrical signals between the first die and a second die; andforming a mold compound on the first side of the package substrate, wherein the mold compound is in direct contact with a sidewall of the first die between the active side and the inactive side and wherein a distance between the first side and a terminating edge of the mold compound that is farthest from the first side is equal to or less than a distance between the inactive side of the first die and the first side;mounting ...

Semiconductor Package and Method

In an embodiment, a device includes: a back-side redistribution structure including: a metallization pattern on a first dielectric layer; and a second dielectric layer on the metallization pattern; a through via extending through the first dielectric layer to contact the metallization pattern; an integrated circuit die adjacent the through via on the first dielectric layer; a molding compound on the first dielectric layer, the molding compound encapsulating the through via and the integrated circuit die; a conductive connector extending through the second dielectric layer to contact the metallization pattern, the conductive connector being electrically connected to the through via; and an intermetallic compound at the interface of the conductive connector and the metallization pattern, the intermetallic compound extending only partially into the metallization pattern.

Multi-Stacked Package-on-Package Structures

A multi-stacked package-on-package structure includes a method. The method includes: adhering a first die and a plurality of second dies to a substrate, the first die having a different function from each of the plurality of second dies; attaching a passive device over the first die; encapsulating the first die, the plurality of second dies, and the passive device; and forming a first redistribution structure over the passive device, the first die, and the plurality of second dies, the passive device connecting the first die to the first redistribution structure.

Metal-Bump Sidewall Protection

A method includes forming a metal bump on a top surface of a first package component, forming a solder region on a top surface of the metal bump, forming a protection layer extending on a sidewall of the metal bump, reflowing the solder region to bond the first package component to a second package component, and dispensing an underfill between the first package component and the second package component. The underfill is in contact with the protection layer. 1. A package comprising: a dielectric layer;', 'a metal bump protruding beyond the dielectric layer;', 'a solder region over and contacting the metal bump; and', 'a protection layer contacting a sidewall of the metal bump and a surface of the dielectric layer, wherein the protection layer is formed of a dielectric material., 'a first package component comprising2. The package of claim 1 , wherein the protection layer is free from filler particles therein.3. The package of further comprising:a second package component bonded to the first package component; andan underfill contacting the protection layer, wherein the underfill comprises a portion lower than a bottom surface of the metal bump.4. The package of claim 1 , wherein the protection layer is lower than claim 1 , and is spaced apart from claim 1 , the solder region.5. The package of claim 1 , wherein the protection layer and the dielectric layer are formed of a same dielectric material claim 1 , and have a distinguishable interface therebetween.6. The package of claim 1 , wherein the protection layer comprises polyimide claim 1 , polybenzoxazole (PBO) claim 1 , or benzocyclobutene (BCB).7. The package of claim 1 , wherein the first package component comprises an edge claim 1 , and the protection layer is recessed laterally from the edge.8. The package of claim 1 , wherein the first package component further comprises an additional metal bump protruding beyond the dielectric layer claim 1 , and the protection layer comprises:a first portion contacting the ...

Semiconductor device

A semiconductor device includes a protective layer, a redistribution pattern, a pad pattern and an insulating polymer layer. The protective layer may be formed on a substrate. The redistribution pattern may be formed on the protective layer. An upper surface of the redistribution may be substantially flat. The pad pattern may be formed directly on the redistribution pattern. An upper surface of the pad pattern may be substantially flat. The insulating polymer layer may be formed on the redistribution pattern and the pad pattern. An upper surface of the insulating polymer layer may be lower than the upper surface of the pad pattern. The semiconductor device may have a high reliability.

GANG CLIP

An integrated circuit (IC) package includes a lead frame and a first die attached to the lead frame. The IC package also includes a first clip attached to first die and the lead frame. The IC package further includes a second die attached to first clip and the lead frame. The IC package still further includes a second clip with a clip foot adhered to the lead frame on a first side of the second clip, the second clip extending to and contacting a side of the second die via a layer of solder paste. The second clip includes a sawn or lased edge at a second side of the second clip opposing the first side of the second clip. 1. An integrated circuit (IC) package comprising:a lead frame;a first die adhered to the lead frame on a first side of the first die;a first clip having a clip foot adhered to the lead frame, the first clip extending from the lead frame and contacting a second side of the first die on a first side of the first clip via a first layer of solder paste wherein the second side of the first die opposes the first side of the first die;a second die with a first side adhered to a second side of the first clip via a second layer of solder paste, wherein the second side of the first clip opposes the first side of the first clip; anda second clip having a clip foot adhered to the lead frame on a first side of the second clip, the second clip extending from the lead frame to a second side of the second die via a third layer of solder paste, the second side of the second die opposing the first side of the second die, wherein the second clip has an sawn or lased edge on a second side of the second clip, wherein the second side of the second clip opposes the first side of the second clip.2. The IC package of claim 1 , wherein the sawn or lased edge is parallel to an edge of the lead frame.3. The IC package of claim 1 , wherein the second clip comprises a high side that includes the sawn or lased edge claim 1 , and wherein a surface of the high side that is ...

Process Control for Package Formation

A method includes bonding a first and a second device die to a third device die, forming a plurality of gap-filling layers extending between the first and the second device dies, and performing a first etching process to etch a first dielectric layer in the plurality of gap-filling layers to form an opening. A first etch stop layer in the plurality of gap-filling layers is used to stop the first etching process. The opening is then extended through the first etch stop layer. A second etching process is performed to extend the opening through a second dielectric layer underlying the first etch stop layer. The second etching process stops on a second etch stop layer in the plurality of gap-filling layers. The method further includes extending the opening through the second etch stop layer, and filling the opening with a conductive material to form a through-via.

Semiconductor Device Package and Method

In an embodiment, a method includes: stacking a plurality of first dies to form a device stack; revealing testing pads of a topmost die of the device stack; testing the device stack using the testing pads of the topmost die; and after testing the device stack, forming bonding pads in the topmost die, the bonding pads being different from the testing pads.

Multi-Chip Structure and Method of Forming Same

A device includes a first chip is embedded in a molding compound layer, wherein the first chip is shifted toward a first direction, a second chip over the first chip and embedded in the molding compound layer, wherein the second chip is shifted toward a second direction opposite to the first direction and a plurality of bumps between the first chip and the second chip. 1. A device comprising:a first chip is embedded in a molding compound layer, wherein the first chip is shifted toward a first direction;a second chip over the first chip and embedded in the molding compound layer, wherein the second chip is shifted toward a second direction opposite to the first direction; anda plurality of bumps between the first chip and the second chip.2. The device of claim 1 , further comprising:a redistribution layer over the molding compound layer;a dielectric layer over the redistribution layer;an under bump metallization structure over the dielectric layer; anda solder ball over the under bump metallization structure.3. The device of claim 2 , wherein:the first chip comprises a plurality of logic circuits, wherein the first chip comprise a plurality of through vias connected to the redistribution layer; andthe second chip comprises a plurality of memory dies stacked together, wherein the second chip is electrically connected to the first chip through the plurality of bumps.4. The device of claim 2 , wherein:the redistribution layer extends beyond at least one outmost edge of the first chip.5. The device of claim 2 , wherein:the second chip and the redistribution layer are separated by the molding compound layer.6. The device of claim 1 , wherein:a top surface of the second chip is exposed outside the molding compound layer.7. The device of claim 1 , wherein:a first sidewall of the first chip is exposed outside the molding compound layer;a second sidewall of the first chip is covered by the molding compound layer and underneath the second chip;a first sidewall of the second ...

Fan-Out Package with Cavity Substrate

Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.

Semiconductor Package, and a Method for Forming a Semiconductor Package

A semiconductor package includes a semiconductor die arranged on a substrate. The semiconductor package includes a stiffener structure arranged on the substrate. The stiffener structure is spaced at a distance from the semiconductor die. The stiffener structure includes a molding compound material.

3D Packaging Method for Semiconductor Components

The present disclosure relates to a method for bonding semiconductor components. A semiconductor component comprising microbumps on a planar bonding surface is prepared for bonding by applying a photosensitive polymer layer on the bonding surface. The average thickness of the initial polymer layer in between the microbumps is similar to the average height of the microbumps. In a lithography process, the polymer is removed from the upper surface of the microbumps and from areas around the microbumps. The polymer is heated to a temperature at which the polymer flows, resulting in a polymer layer that closely adjoins the microbumps, without exceeding the microbump height. The closely adjoining polymer layer may have a degree of planarity substantially similar to a planarized layer.

Semiconductor package and method for manufacturing a semiconductor package

A semiconductor package includes at least one semiconductor element, an encapsulant, a first circuitry, a second circuitry and at least one first stud bump. The encapsulant covers at least a portion of the semiconductor element. The encapsulant has a first surface and a second surface opposite to the first surface. The first circuitry is disposed adjacent to the first surface of the encapsulant. The second circuitry is disposed adjacent to the second surface of the encapsulant. The first stud bump is disposed in the encapsulant, and electrically connects the first circuitry and the second circuitry. The first stud bump contacts the second circuitry directly.

Array substrate, method for manufacturing the same and display panel

An array substrate, a method for manufacturing the same and a display panel are provided. The array substrate comprises: a substrate; a bare chip fixed on the substrate, the bare chip comprising pins; a buffer layer and a first metallic layer disposed sequentially on the bare chip, the first metallic layer comprising outer leads in one-to-one correspondence with the pins of the bare chip, the outer leads being connected electrically to the pins corresponding thereto of the bare chip, and the outer leads being electrically insulated from each other; a thin film transistor; and a first signal wire and a first connecting wire disposed in a same layer as a gate electrode of the thin film transistor, and a second signal wire and a second connecting wire disposed in a same layer as a source electrode and a drain electrode of the thin film transistor.

METHOD FOR MANUFACTURING FLEXIBLE MOUNTING MODULE BODY

An adhesive film including a substrate film and an adhesive agent layer formed thereon is adhered to the back surface side of a mounting region of a flexible substrate, and an electronic component is mounted on the front surface side. An adhesive agent in the adhesive agent layer contains silica fine particles having a primary particle diameter of less than 100 nm, and the adhesive agent layer has a shear storage elastic modulus at 160° C. of 0.15 MPa or more. When the anisotropic conductive film is disposed on the mounting region and the electronic component is mounted on the anisotropic conductive film by heating and pressing, the adhesive agent is not pushed out to a large extent, and conductive particles sandwiched between a bump on the electronic component and the electrode are pressed and squashed, improving an electrical connection between the electronic component and the electrode. 1. A manufacturing method of a flexible mounting module body , the method comprising:an anisotropic conductive film disposing step including disposing a thermosetting anisotropic conductive film including conductive particles in a mounting region provided on a disposition surface that is one surface of a flexible substrate, the flexible substrate further including a second surface that is opposite the one surface;an electronic component disposing step including disposing an electronic component on the anisotropic conductive film disposed on the mounting region:an adhesive film adhering step including adhering an adhesive film to at least a portion of the second surface that is located directly opposite the mounting region, the adhesive film comprising an adhesive agent layer that (i) contains an adhesive agent and a. substrate film that are laminated, (ii) includes silica fine particles having a primary particle, diameter of less than 100 nm, and (iii) has a shear storage elastic modulus at 160° C. of 0.15 MPa or more; andafter the adhesive film adhering step, performing a ...

Semiconductor chip and stacked type semiconductor package having the same

The disclosure relates to a semiconductor chip and a stacked type semiconductor package having the same. The semiconductor chip includes: a semiconductor chip body having a first surface formed with a plurality of bonding pads and a second surface which is opposite to the first surface, a plurality of first and second through electrodes that pass through the semiconductor chip body and one ends thereof are electrically connected to the bonding pads, an insulating layer formed over the second surface of the semiconductor chip body such that the other ends of the first and second through electrodes are not covered by the insulating layer, and a first heat spreading layer formed over the insulating layer.

SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME

Disclosed is a semiconductor package comprising a lower substrate including a conductive line; a first semiconductor chip on the lower substrate; an under-fill layer between the first semiconductor chip and the lower substrate, the under-fill layer including a central part below the first semiconductor chip and an edge part isolated from direct contact with the central part in a first direction parallel to a top surface of the lower substrate, and a recess region between the central part and the edge part. The recess region may be defined by a sidewall of the central part, a sidewall of the edge part, and a top surface of the conductive line in the lower substrate. 110.-. (canceled)11. A semiconductor package , comprising:a lower substrate including a conductive line;a first semiconductor chip on the lower substrate; a central part below the first semiconductor chip, and', 'an edge part isolated from direct contact with the central part in a first direction parallel to a top surface of the lower substrate; and, 'an under-fill layer between the first semiconductor chip and the lower substrate, the under-fill layer including'}a recess region between the central part and the edge part, the recess region defined by a sidewall of the central part, a sidewall of the edge part, and a portion of a top surface of the conductive line.12. The semiconductor package of claim 11 , whereinthe central part of the under-fill layer fills a space between the lower substrate and the first semiconductor chip, andthe recess region of the under-fill layer is adjacent to a side of the first semiconductor chip.13. The semiconductor package of claim 11 , wherein a width in the first direction of the recess region is less than a width in the first direction of the conductive line.14. The semiconductor package of claim 11 , wherein a width in the first direction of the recess region is in a range of 10 μm to 500 μm.15. The semiconductor package of claim 11 , whereina height of the sidewall of ...

Four D Device Process and Structure

A 4D device comprises a 2D multi-core logic and a 3D memory stack connected through the memory stack sidewall using a fine pitch T&J connection. The 3D memory in the stack is thinned from the original wafer thickness to no remaining Si. A tongue and groove device at the memory wafer top and bottom surfaces allows an accurate stack alignment. The memory stack also has micro-channels on the backside to allow fluid cooling. The memory stack is further diced at the fixed clock-cycle distance and is flipped on its side and re-assembled on to a template into a pseudo-wafer format. The top side wall of the assembly is polished and built with BEOL to fan-out and use the T&J fine pitch connection to join to the 2D logic wafer. The other side of the memory stack is polished, fanned-out, and bumped with C4 solder. The invention also comprises a process for manufacturing the device. In another aspect, the invention comprises a 4D process and device for over 50× greater than 2D memory density per die and an ultra high density memory. 184-. (canceled)85. A 4D device which includes a structure comprising a 2D planar multi-core logic wafer and a vertically stacked 3D memory stack comprising a tier-1 region and a tier-2 region wherein both of said tier-1 region and said tier-2 region are for secondary 3D stacking (4D) , said tier-1 region produced by tier-1 bonding , said tier-1 region having a tier-1 dicing area and wherein said 3D memory stack comprises memory wafers or any of the device combination in said 3D memory stack comprising 2D-in-4D , 3D-in-4D , 2D/3D-in-4D , having a top surface and back surface , and at least one of tongue/groove or lock/key features in said tier-1 region at said top surface and back surface , so that said memory wafers or vertically stacked 3D memory stack in said 3D memory stack are stacked in alignment with each other during said tier-1 bonding , and said tongue/groove , lock/key features define x and y locations in said tier-1 and tier-2 devices , ...

Method for forming Board Assembly with Chemical Vapor Deposition Diamond (CVDD) Windows for Thermal Transport

A method for forming a board assembly includes identifying a location of a hot-spot on a semiconductor die and cutting an opening in a circuit board corresponding to the location of the identified hot-spot. A Chemical Vapor Deposition Diamond (CVDD) window is inserted into the opening. A layer of thermally conductive paste is applied over the CVDD window. The semiconductor die is placed over the layer of thermally conductive paste such that the CVDD window underlies the hot-spot and such that a surface of the semiconductor die is in direct contact with the layer of thermally conductive paste. 1. A method for forming a board assembly comprising:identifying a location of a hot-spot on a semiconductor die;cutting an opening in a circuit board corresponding to the location of the identified hot-spot;inserting a Chemical Vapor Deposition Diamond (CVDD) window into the opening;applying a layer of thermally conductive paste over the CVDD window; andplacing the semiconductor die over the layer of thermally conductive paste such that the CVDD window underlies the hot-spot and such that a surface of the semiconductor die is in direct contact with the layer of thermally conductive paste.2. The method of further comprising: attaching leads to the semiconductor die and the circuit board to electrically couple the die to the first circuit board.3. The method of further comprising: forming a dam around the semiconductor die and attaching an additional circuit board to the dam so as to enclose the semiconductor die within the dam and between the circuit board and the additional circuit board.4. The method of further comprising: dispensing filler material within the enclosure.5. The method of claim 4 , wherein the filler material comprises diamond paste.6. The method of claim 1 , wherein the CVDD window has a thickness that is the same as the thickness of the circuit board.7. The method of claim 1 , wherein the CVDD window has a thickness that is greater than a thickness of the ...

Multichip package manufacturing process

Multichip package manufacturing process is disclosed to form external pins at one side or each side of die-bonding area of package carrier board and to bond first IC and second IC to die-bonding area in stack. First IC and second IC each comprise transistor layer with core circuits, plurality of metal layers, plurality of VIA layers and solder pad layer. During production of first IC, design of at least one metal layer, VIA layer and dummy pads can be modified according to change of design of second IC. After chip probing, die sawing and bonding, wire bonding, packaging and final test are performed to package the package carrier board, first IC and second IC into automotive multichip package, achieving purpose of first IC only need to modify at least one layer or more than one layer to cooperate with second IC design change to carry out multichip packaging process.

ACRYLIC COMPOSITION FOR ENCAPSULATION, SHEET MATERIAL, LAMINATED SHEET, CURED OBJECT, SEMICONDUCTOR DEVICE, AND PROCESS FOR PRODUCING SEMICONDUCTOR DEVICE

The acrylic composition for sealing contains an acrylic compound, a polyphenylene ether resin including a radical-polymerizable substituent at a terminal, an inorganic filler, and a thermal radical polymerization initiator. 1. An acrylic composition for sealing , the acrylic composition comprising:an acrylic compound;a polyphenylene ether resin including a radical-polymerizable substituent at a terminal;an inorganic filler; anda thermal radical polymerization initiator.2. The acrylic composition for sealing according to claim 1 , further comprising a nitroxide compound.3. The acrylic composition for sealing according to claim 1 , wherein the radical-polymerizable substituent includes a carbon-carbon double bond.5. A sheet material that is a dried product or a half-cured product of the acrylic composition for sealing according to .6. The sheet material according to claim 5 , having a minimum melt viscosity less than or equal to 200 Pa·s.7. A multilayer sheet comprising:{'claim-ref': {'@idref': 'CLM-00005', 'claim 5'}, 'the sheet material according to ; and'}a support sheet that supports the sheet material.8. A cured product that is a thermally cured product of the acrylic composition for sealing according to .9. The cured product according to claim 8 , having a glass transition temperature more than or equal to 170° C.10. A semiconductor device comprising:a substrate;a semiconductor chip mounted face-down on the substrate; anda sealing material that seals a gap between the substrate and the semiconductor chip,wherein the sealing material is made of the cured product according to claim11. A method for manufacturing a semiconductor device claim 8 , the method comprising:{'claim-ref': {'@idref': 'CLM-00005', 'claim 5'}, 'overlaying the sheet material according to on a surface of a semiconductor wafer including a bump electrode, the surface including the bump electrode;'}cutting the semiconductor wafer together with the sheet material to produce a member, the member ...

Package assembly

In some embodiments, the present disclosure relates to a package assembly having a bump on a first substrate. A molding compound is on the first substrate and contacts sidewalls of the bump. A no-flow underfill layer is on a conductive region of a second substrate. The no-flow underfill layer and the conductive region contact the bump. A mask layer is arranged on the second substrate and laterally surrounds the no-flow underfill layer. The no-flow underfill layer contacts the substrate between the conductive region and the mask layer.

METHODS OF FORMING BONDED SEMICONDUCTOR STRUCTURES, AND SEMICONDUCTOR STRUCTURES FORMED BY SUCH METHODS

Methods of forming bonded semiconductor structures include providing a first semiconductor structure including a device structure, bonding a second semiconductor structure to the first semiconductor structure below about 400° C., forming a through wafer interconnect through the second semiconductor structure and into the first semiconductor structure, and bonding a third semiconductor structure to the second semiconductor structure on a side thereof opposite the first semiconductor structure. In additional embodiments, a first semiconductor structure is provided. Ions are implanted into a second semiconductor structure. The second semiconductor structure is bonded to the first semiconductor structure. The second semiconductor structure is fractured along an ion implant plane, a through wafer interconnect is formed at least partially through the first and second semiconductor structures, and a third semiconductor structure is bonded to the second semiconductor structure on a side thereof opposite the first semiconductor structure. Bonded semiconductor structures are formed using such methods. 1. A method of forming a bonded semiconductor structure , comprising: providing a first semiconductor structure comprising at least one device structure;bonding a second semiconductor structure to the first semiconductor structure at a temperature or temperatures below about 400° C.;forming at least one through wafer interconnect through the second semiconductor structure and into the first semiconductor structure to the at least one device structure; andbonding the second semiconductor structure on a side thereof opposite the first semiconductor structure to a third semiconductor structure.2. The method of claim 1 , wherein bonding the second semiconductor structure to the first semiconductor structure comprises:bonding a relatively thicker semiconductor structure to the first semiconductor structure; andthinning the relatively thicker semiconductor structure to form the second ...

Electronic component device

An electronic component device includes a first lead frame having a first connection terminal and an electronic component. The first connection terminal includes a first metal electrode, a first pad part formed on an upper surface of the first metal electrode and formed by a metal plated layer, and a first metal oxide layer formed on an upper surface of the first metal electrode in a surrounding region of the first pad part so as to surround an outer periphery of the first pad part. The electronic component has a first terminal part provided on its lower surface. The first terminal part of the electronic component is connected to the first pad part of the first connection terminal via a metal joining material.

Semiconductor package with dual sides of metal routing

A method includes forming a redistribution structure over a carrier, the redistribution structure having conductive features on a surface of the redistribution structure distal the carrier; forming a conductive pillar over the surface of the redistribution structure; attaching a die to the surface of the redistribution structure adjacent to the conductive pillar, where die connectors of the die are electrically coupled to the conductive features of the redistribution structure; and attaching a pre-made substrate to the conductive pillar through a conductive joint, where the conductive joint is on the conductive pillar and comprises a different material from the conductive pillar, where the conductive joint and the conductive pillar electrically couple the redistribution structure to the pre-made substrate.

THREE-DIMENSIONAL MEMORY DEVICES WITH DEEP ISOLATION STRUCTURES

A method for forming a three-dimensional memory device includes forming, on a first side of a first substrate, a peripheral circuitry including first and second peripheral devices, a first interconnect layer, and a shallow trench isolation (STI) structure between the first and second peripheral devices, and forming, on a second substrate, a memory array including a plurality of memory cells and a second interconnect layer. The method includes bonding the first and second interconnect layers and forming an isolation trench through the first substrate and exposing a portion of the STI structure. The isolation trench is formed through a second side of the first substrate that is opposite to the first side. The method includes disposing an isolation material to form an isolation structure in the isolation trench and performing a planarization process to remove portions of the isolation material disposed on the second side of the first substrate. 1. A method for forming a three-dimensional memory device , comprising:forming, on a first side of a first substrate, a peripheral circuitry comprising first and second peripheral devices, a first interconnect layer, and a shallow trench isolation (STI) structure between the first and second peripheral devices;forming, on a second substrate, a memory array comprising a plurality of memory cells and a second interconnect layer;bonding the first and second interconnect layers;forming an isolation trench through the first substrate and exposing a portion of the STI structure, wherein the isolation trench is formed through a second side of the first substrate that is opposite to the first side;disposing an isolation material to form an isolation structure in the isolation trench; andperforming a planarization process to remove portions of the isolation material disposed on the second side of the first substrate.2. The method of claim 1 , further comprising thinning the first substrate through the second side after bonding the first ...

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES, CORRESPONDING DEVICE AND CIRCUIT

A method of manufacturing semiconductor devices such as integrated circuits comprises: providing one or more semiconductor chips having first and second opposed surfaces, coupling the semiconductor chip or chips with a support substrate with the second surface towards the support substrate, embedding the semiconductor chip or chips coupled with the support substrate in electrically-insulating packaging material by providing in the packaging material electrically-conductive passageways. The electrically-conductive passageways comprise: electrically-conductive chip passageways towards the first surface of the at least one semiconductor chip, and/or electrically-conductive substrate passageways towards the support substrate. 1. A method , comprising:coupling a semiconductor chip to a support;molding a first layer of LDS material over the semiconductor chip and the support substrate;using a laser, forming first and second through openings in the first layer of LDS material, wherein the first through opening is at a bond pad of the semiconductor chip and the second through opening is at a contact of the support;filling the first and second through openings with conductive material;forming a conductive line on a surface of the first layer of LDS material, the conductive line being coupled to the conductive material in the first and second through openings; andmolding a second layer of LDS material over the conductive material in the first and second through openings and the conductive line.2. The method of claim 1 , wherein the conductive line is sloped.3. The method of claim 1 , further comprising using the laser to form a third through opening in the second layer of LDS material claim 1 , filling the third through opening with a conductive material claim 1 , the conductive material in the third through opening is coupled to the conductive line.4. The method of claim 1 , wherein the semiconductor chip is a first semiconductor chip claim 1 , the method further comprising ...

Multi-metal package stiffener

A semiconductor package system includes a semiconductor package including at least one semiconductor device having a first side and a second side and a substrate having a first side and a second side. The second side of the at least one semiconductor device is positioned on the first side of the substrate. At least one stiffener element is provided on the semiconductor package. The at least one stiffener element includes at least two metal elements having different coefficients of thermal expansion joined together.

Positional relationship among components of semiconductor device

A QFP has a die pad on which a semiconductor chip is mounted, a plurality of inner parts disposed around the die pad, a plurality of outer parts respectively connected with the plurality of inner parts, a plurality of wires electrically connect the bonding pads of the semiconductor chip and the plurality of inner parts, and a sealing body that seals the semiconductor chip. Moreover, the thickness of the semiconductor chip is larger than a thickness from a lower surface of the die pad to a lower surface of the sealing body, and a distance from the lower surface of the sealing body to a tip portion of each of the plurality of outer parts is larger than a thickness of the sealing body from a main surface of the semiconductor chip to an upper surface of the sealing body.

Semiconductor device with thin redistribution layers

A semiconductor device with thin redistribution layers is disclosed and may include forming a first redistribution layer on a dummy substrate, electrically coupling a semiconductor die to the first redistribution layer, and forming a first encapsulant layer on the redistribution layer and around the semiconductor die. The dummy substrate may be removed thereby exposing a second surface of the first redistribution layer. A dummy film may be temporarily affixed to the exposed second surface of the redistribution layer and a second encapsulant layer may be formed on the exposed top surface of the semiconductor die, a top surface and side edges of the first encapsulant layer, and side edges of the first redistribution layer. The dummy film may be removed to again expose the second surface of the first redistribution layer, and a second redistribution layer may be formed on the first redistribution layer and on the second encapsulant layer.

Semiconductor Device and Method

In an embodiment, a device includes: a first reflective structure including first doped layers of a semiconductive material, alternating ones of the first doped layers being doped with a p-type dopant; a second reflective structure including second doped layers of the semiconductive material, alternating ones of the second doped layers being doped with a n-type dopant; an emitting semiconductor region disposed between the first reflective structure and the second reflective structure; a contact pad on the second reflective structure, a work function of the contact pad being less than a work function of the second reflective structure; a bonding layer on the contact pad, a work function of the bonding layer being greater than the work function of the second reflective structure; and a conductive connector on the bonding layer.

Fingerprint identification module and method for manufacturing the same

The present disclosure discloses a fingerprint identification module and a method for manufacturing the same, and relates to the field of fingerprint identification technologies. The fingerprint identification module is obtained by dicing a board-level module, and includes a fingerprint identification chip, a filling material, a color coating and a cover. The color coating is disposed between the filling material and the cover, and the fingerprint identification chip is inversely attached in a hollow area of the filling material in a vacuum environment. The fingerprint identification module has a simple structure and is easy to manufacture. By using the method, the bubbles between the fingerprint identification chip and the cover are effectively eliminated, and the manufacture efficiency of the fingerprint identification module is improved.

BOTTOM PACKAGE EXPOSED DIE MEMS PRESSURE SENSOR INTEGRATED CIRCUIT PACKAGE DESIGN

A MEMS pressure sensor packaged with a molding compound. The MEMS pressure sensor features a lead frame, a MEMS semiconductor die, a second semiconductor die, multiple pluralities of bonding wires, and a molding compound. The MEMS semiconductor die has an internal chamber, a sensing component, and apertures. The MEMS semiconductor die and the apertures are exposed to an ambient atmosphere. A method is desired to form a MEMS pressure sensor package that reduces defects caused by mold flashing and die cracking. Fabrication of the MEMS pressure sensor package comprises placing a lead frame on a lead frame tape; placing a MEMS semiconductor die adjacent to the lead frame and on the lead frame tape with the apertures facing the tape and being sealed thereby; attaching a second semiconductor die to the MEMS semiconductor die; attaching pluralities of bonding wires to form electrical connections between the MEMS semiconductor die, the second semiconductor die, and the lead frame; and forming a molding compound. 19.-. (canceled)10. A package containing a MEMS sensor circuit , comprising:a lead frame having an open region in a middle of the lead frame and a first surface exposed to an ambient atmosphere;a MEMS semiconductor die being laterally adjacent to the lead frame, the MEMS semiconductor die having an exposed outer surface thereof exposed to the ambient atmosphere, the exposed outer surface having a plurality of apertures, the plurality of apertures exposing an internal chamber of the MEMS semiconductor die to the ambient atmosphere;a second semiconductor die attached to the MEMS semiconductor die;a first plurality of bonding wires connected between the lead frame and the second semiconductor die;a second plurality of bonding wires connected at least between one of the lead frame and the MEMS semiconductor die or the MEMS semiconductor die and the second semiconductor die; anda molding compound partially covering the MEMS semiconductor die and the lead frame and ...

ELECTRICALLY CONDUCTIVE ADHESIVE FILM AND DICING-DIE BONDING FILM USING THE SAME

The electrically conductive adhesive film comprises a metal particle (P), a resin (M) and a prescribed sulfide compound (A), the resin (M) comprises a thermosetting resin (M1), and the metal particle (P) has an average particle size (d50) of 20 μm or less and comprises 10% by mass or more of a first metal particle (P1) having a fractal dimension of 1.1 or more when viewed in a projection drawing in a primary particle state. 2. The electrically conductive adhesive film according to claim 1 , wherein the first metal particle (P1) is a dendritic metal powder.3. The electrically conductive adhesive film according to claim 1 , wherein claim 1 , in the general formula (1) claim 1 , each K independently includes claim 1 , in its moiety claim 1 , one or more group selected from a vinyl group claim 1 , an acrylic group claim 1 , a methacrylic group claim 1 , a maleic acid ester group claim 1 , a maleic acid amide group claim 1 , a maleic acid imide group claim 1 , a primary amino group claim 1 , a secondary amino group claim 1 , a thiol group claim 1 , a hydrosilyl group claim 1 , a hydroboron group claim 1 , a phenolic hydroxyl group and an epoxy group.4. The electrically conductive adhesive film according to claim 1 , wherein the metal particle (P) further comprises a second metal particle (P2) made of a spherical metal powder.5. The electrically conductive adhesive film according to claim 4 , wherein the second metal particle (P2) has an average particle size (d50) of less than 7 μm.6. The electrically conductive adhesive film according to claim 4 , wherein the second metal particle (P2) comprises a metal particle made of tin or a tin-containing alloy.7. The electrically conductive adhesive film according to claim 1 , wherein a loss tangent (tan δ) defined by a ratio (G″/G′) of a loss elastic modulus (G″) to a storage elastic modulus (G′) at 60° C. and 1 Hz in a B-stage state is 1.4 or higher.8. The electrically conductive adhesive film according to claim 1 , wherein the ...

ELECTRICALLY CONDUCTIVE ADHESIVE FILM AND DICING-DIE BONDING FILM USING THE SAME

The electrically conductive adhesive film comprises a metal particle (Q), a resin (M), and a prescribed organophosphorus compound (A), the resin (M) comprises a thermosetting resin (M1), and the metal particle (Q) has an average particle size (d50) of 20 μm or less and comprise 10% by mass or more of a first metal particle (Q1) having a fractal dimension of 1.1 or more when viewed in a projection drawing in a primary particle state. 2. The electrically conductive adhesive film according to claim 1 , wherein the first metal particle (Q1) is a dendritic metal powder.3. The electrically conductive adhesive film according to claim 1 , wherein the organophosphorus compound (A) is at least one compound selected from alkyl phosphine claim 1 , aryl phosphine and organic phosphorous acid ester.4. The electrically conductive adhesive film according to claim 1 , wherein claim 1 , in the general formula (1) claim 1 , each R independently includes claim 1 , in its moiety claim 1 , one or more group selected from a vinyl group claim 1 , an acrylic group claim 1 , a methacrylic group claim 1 , a maleic acid ester group claim 1 , a maleic acid amide group claim 1 , a maleic acid imide group claim 1 , a primary amino group claim 1 , a secondary amino group claim 1 , a thiol group claim 1 , a hydrosilyl group claim 1 , a hydroboron group claim 1 , a phenolic hydroxyl group and an epoxy group.5. The electrically conductive adhesive film according to claim 1 , wherein the metal particle (Q) further comprises a second metal particle (Q2) made of a spherical metal powder.6. The electrically conductive adhesive film according to claim 5 , wherein the second metal particle (Q2) has an average particle size (d50) of less than 7 μm.7. The electrically conductive adhesive film according to claim 5 , wherein the second metal particle (Q2) comprises a metal particle made of tin or a tin-containing alloy.8. The electrically conductive adhesive film according to claim 1 , wherein a loss tangent ( ...

Anti-fuse on and/or in Package

A package structure includes an integrated circuit die, a redistribution structure, an anti-fuse, and external connectors. The integrated circuit die is embedded in an encapsulant. The redistribution structure is on the encapsulant and is electrically coupled to the integrated circuit die. The anti-fuse is external to the integrated circuit die and the redistribution structure. The anti-fuse is mechanically and electrically coupled to the redistribution structure. The external connectors are on the redistribution structure, and the redistribution structure is disposed between the external connectors and the encapsulant.

Radio frequency shielding cavity package

A radio-frequency shielding cavity package is set forth along with a method of manufacturing thereof. According to one embodiment, the radio-frequency shielding cavity package comprises a metallic leadframe and plastic molded body. The leadframe has a plurality of contact pads extending from top to bottom surfaces thereof, at least one contact pad on the top surface being surrounded by metal for shielding the contact pad from external electric fields. A plated inner ring surrounds a die attach pad on the leadframe. The die attach pad receives a semiconductor die adapted to be wire bonded to the inner ring and plurality of contact pads. A plated outer ring defines a ground plane circumscribing the perimeter of the leadframe. A cap is connected to the ground plane for enclosing and protecting the wire bonded semiconductor device die and providing electrical grounding thereof.

Functional Spacer for SIP and Methods for Forming the Same

A device includes a spacer, which includes a recess extending from a top surface of the spacer into the spacer, and a conductive feature including a first portion and a second portion continuously connected to the first portion. The first portion extends into the recess. The second portion is on the top surface of the spacer. A die is attached to the spacer, and a lower portion of the first die extends into the recess.