Method for stapling with contact element on a chip with a functional layer with openings for the chip substrate provided contact elements

Die vorliegende Erfindung betrifft ein Verfahren zum Heften von Chips (4) auf ein Substrat (1) an auf einer Oberfläche (1o) des Substrats (1) verteilten Chippositionen (1c) mit folgenden Schritten, insbesondere folgendem Ablauf: -Ausbildung oder Aufbringung einer a) an den Chippositionen (1c) zumindest im Bereich von Kontakten (2) durch Strukturierung freigelegten oder b) durch Freilegung von an der Oberfläche (1o) jeweils an den Chippositionen (1c) zumindest im Bereich der Kontakte (2) nach Ausbildung oder Aufbringung der Funktionsschicht (7) freigelegten Funktionsschicht (7) auf das Substrat (1), -Heften von Chips (4) auf eine Chipkontaktseite (7o) der Funktionsschicht (7) an den Chippositionen (1c) und Kontaktierung der Kontakte (2) über Kontaktelemente (3).

Method for stapling with contact element on a chip with a functional layer with openings for the chip substrate provided contact elements

Die vorliegende Erfindung betrifft ein Verfahren zum Heften von Chips (4) auf ein Substrat (1) an auf einer Oberfläche (1o) des Substrats (1) verteilten Chippositionen ( 1 c) mit folgenden Schritten, insbesondere folgendem Ablauf: Ausbildung oder Aufbringung einer a) an den Chippositionen (lc) zumindest im Bereich von Kontakten (2) durch Strukturierung freigelegten oder b) durch Freilegung von an der Oberfläche (lo) jeweils an den Chippositionen (1c) zumindest im Bereich der Kontakte (2) nach Ausbildung oder Aufbringung der Funktionsschicht (7) freigelegten Funktionsschicht (7) auf das Substrat ( 1 ), Heften von Chips (4) auf eine Chipkontaktseite (7o) der Funktionsschicht (7) an den Chippositionen (1 c) und Kontaktierung der Kontakte (2) über Kontaktelemente (3).

System and method for sub-column parallel digitizers for hybrid stacked image sensor using vertical interconnects

Embodiments of a hybrid imaging sensor and methods for pixel sub-column data are read from within a pixel array. The hybrid imaging sensor and methods optimize the pixel array area and use a stacking scheme for a hybrid image sensor with minimal vertical interconnects between substrates.

System and method for sub-column parallel digitizers for hybrid stacked image sensor using vertical interconnects

Embodiments of a hybrid imaging sensor and methods for pixel sub-column data are read from within a pixel array. The hybrid imaging sensor and methods optimize the pixel array area and use a stacking scheme for a hybrid image sensor with minimal vertical interconnects between substrates.

Semiconductor device manufacturing method and semiconductor device

In a state wherein a plurality of protruding electrodes (4) on a semiconductor chip (1) abut a plurality of electrodes (13), which are formed on a semiconductor substrate (11), with a plurality of solder sections therebetween, the solder sections are melted, and a plurality of solder bonding sections (7), which are bonded to the protruding electrodes (4) of the semiconductor chip (1) and the electrodes (13) of the semiconductor substrate (11), are formed. Then, the interval (A) between a part of the semiconductor chip (1) and the semiconductor substrate (11) is made larger than the interval (B) between another part of the semiconductor chip (1) and the semiconductor substrate (11), and at least some solder bonding sections among the solder bonding sections (7) are stretched. Consequently, variance in the height of the solder bonding sections (7) is generated. Then, a hole (8) is formed in at least the solder bonding section (7a) having the maximum height among the solder bonding sections ...

METHOD FOR MAKING AN ELECTRICAL INTERCONNECT LEVEL

Hybridization method of electronic component e.g. x-ray or infrared radiation sensors, involves forming protrusions of larger size on pads of electronic component

Ce procédé d'hybridation consiste : - à munir un premier composant 1 de premiers plots 3 de réception de protubérances, - à munir un deuxième composant 2 de deuxièmes plots 5 de réception de protubérances, - les premiers 3 et deuxièmes 5 plots étant respectivement destinés à être associés deux à deux pour former des paires de plots, - puis, à munir les premiers plots et/ou les deuxièmes plots de protubérances 4 réalisées en un matériau fusible, - puis à reporter l'un sur l'autre les premier et deuxième composants, - puis à porter l'ensemble des premier et deuxième composants et corollairement les protubérances de soudure à une température de soudure pour interconnecter les premiers et deuxièmes plots de chaque paire de plots par soudage des protubérances sur ces plots, - et enfin, à faire refroidir la soudure ainsi obtenue. Parmi les protubérances 4 de matériau fusible équipant les premiers 3 et/ou les deuxièmes 5 plots, sont réalisées au moins trois protubérances 6 de plus grandes dimensions ...

이방성 도전 필름, 이방성 도전 필름의 제조 방법, 접속체의 제조 방법 및 접속 방법

... 본 발명은 이방성 도전 필름을 사용한 접속에 있어서, 접속 후의 기판 휨의 저감을 도모하는 것을 목적으로 한다. 이방성 도전 필름(23)은 제1 절연성 접착제층(30)과, 제2 절연성 접착제층(31)과, 제1 절연성 접착제층(30) 및 제2 절연성 접착제층(31)에 끼움 지지되고, 도전성 입자(32)가 절연성 접착제(33)에 함유된 도전성 입자 함유층(34)을 갖고, 도전성 입자 함유층(34)과 제1 절연성 접착제층(30) 사이에 기포(41)가 함유되고, 도전성 입자 함유층(34)은 제2 절연성 접착제층(31)과 접하는, 도전성 입자(32)의 하부의 경화도가 다른 부위의 경화도보다도 낮은 것이다.

이방성 도전 필름, 이방성 도전 필름의 제조 방법, 접속체의 제조 방법 및 접속 방법

... 본 발명은 이방성 도전 필름을 사용한 접속에 있어서, 접속 후의 기판 휨의 저감을 도모하는 것을 목적으로 한다. 이방성 도전 필름(23)은 제1 절연성 접착제층(30)과, 제2 절연성 접착제층(31)과, 제1 절연성 접착제층(30) 및 제2 절연성 접착제층(31)에 끼움 지지되고, 도전성 입자(32)가 절연성 접착제(33)에 함유된 도전성 입자 함유층(34)을 갖고, 도전성 입자 함유층(34)과 제1 절연성 접착제층(30) 사이에 기포(41)가 함유되고, 도전성 입자 함유층(34)은 제2 절연성 접착제층(31)과 접하는, 도전성 입자(32)의 하부의 경화도가 다른 부위의 경화도보다도 낮은 것이다.

FLIP CHIP MOUNTING METHOD AND BUMP FORMING METHOD

A solder resin composition (6) including a solder powder (5a) and a resin (4) is placed on a first electronic component (2), and a connecting terminal (3) of the first electronic component (2) and an electrode terminal (7) of a second electronic component (8) are arranged to face each other. The first electronic component (2) and the solder resin composition are heated to have a gas spouted from a gas generating source (1) included in the first electronic component (2), and the gas (9a) is permitted to flow in a convective manner in the solder resin composition (6). Thus, the solder powder (5a) is flowed in the solder resin composition (6), self-collected on the connecting terminal (3) and the electrode terminal (7), and the connecting terminal (3) and the electrode terminal (7) are electrically connected. The flip chip mounting method by which the electrode terminal of the semiconductor chip wired at a narrow pitch and the connecting terminal of the circuit board can be connected with ...

SYSTEM AND METHOD FOR SUB-COLUMN PARALLEL DIGITIZERS FOR HYBRID STACKED IMAGE SENSOR USING VERTICAL INTERCONNECTS

"chip semicondutor módulo de cristal líquido e estrutura de montagem do chip semicondutor"

Method and system for packing optimization of semiconductor devices

Provided is a disclosure for optimizing the number of semiconductor devices on a wafer/substrate. The optimization comprises laying out, cutting, and packaging the devices efficiently.

Package structure of semiconductor device

A package structure of semiconductor device includes a first substrate, a second substrate and a bonding layer. The bonding layer bonds the first substrate and the second substrate. The bonding layer includes an inner bonding pad pattern and an outer bonding pad pattern formed in a dielectric layer. The outer bonding pad pattern surrounds the first inner bonding pad pattern. A first bonding-pad density of the outer bonding pad pattern is larger than a second bonding-pad density of the inner bonding pad pattern.

Trace design for bump-on-trace (bot) assembly

METHOD FOR FASTENING CHIPS WITH A CONTACT ELEMENT ONTO A SUBSTRATE PROVIDED WITH A FUNCTIONAL LAYER HAVING OPENINGS FOR THE CHIP CONTACT ELEMENTS

A method for tacking of chips onto a substrate at chip positions which are distributed on a surface of the substrate. The method includes the following steps: formation or application of a function layer onto the substrate, removing the function layer from the substrate at the chip positions at least in the region of contacts to uncover the contacts, tacking chips onto one chip contact side of the function layer at the chip positions and contacting the chips with the contacts via contact elements.

Connection body

Even in case of conductive particles being clamped between stepped sections of substrate electrodes and electrode terminals, conductive particles sandwiched between each main surface of the substrate electrodes and electrode terminals are sufficiently compressed, ensuring electrical conduction. An electronic component is connected to a circuit substrate via an anisotropic conductive adhesive agent, on respective edge-side areas of substrate electrodes of the circuit substrate and electrode terminals of the electronic component, stepped sections are formed and abutted, conductive particles are sandwiched between each main surface and stepped sections of the substrate electrodes and electrode terminals; the conductive particles and stepped sections satisfy formula, a+b+c≦0.8 D (1), wherein a is height of the stepped section of the electrode terminals, b is height of the stepped section of the substrate electrodes, c is gap distance between each stepped sections and D is diameter of conductive ...

Intermetallic compound layer on a pillar between a chip and substrate

A semiconductor package includes a wiring substrate that includes a first conductive member; a semiconductor chip that is mounted on the wiring substrate and includes a second conductive member, the first conductive member and the second conductive member being positioned to face each other; and a bonding member that bonds and electrically connects the first conductive member and the second conductive member, at least one of the first conductive member and the second conductive member being a pillar-shaped terminal, the bonding member being bonded to an end surface of the pillar-shaped terminal and a portion of a side surface of the pillar-shaped terminal, an intermetallic compound layer being formed at an interface of the bonding member and the pillar-shaped terminal.

Semiconductor package and fabrication method thereof

A semiconductor package is provided, which includes: a first semiconductor device having a first top surface and a first bottom surface opposite to the first top surface; a plurality of conductive balls formed on the first top surface of the first semiconductor device; a second semiconductor device having a second top surface and a second bottom surface opposite to the second top surface; and a plurality of conductive posts formed on the second bottom surface of the second semiconductor device and correspondingly bonded to the conductive balls for electrically connecting the first semiconductor device and the second semiconductor device, wherein the conductive posts have a height less than 300 um. Therefore, the present invention can easily control the height of the semiconductor package and is applicable to semiconductor packages having fine-pitch conductive balls.

Method of Enhancing Fatigue Life of Grid Arrays

A method is presented that improves reliability for the mechanical electrical connection formed between a grid array device, such as a pin grid array device (PGA) or a column grid array device (CGA), and a substrate such as a printed circuit board (PCB). Between adjacent PCB pads, the method increases a spacing pattern toward the periphery of the CGA, creating a misalignment between pads and columns. As part of the method, columns align with the pads, resulting in column tilt that increases from the center to the periphery of the CGA. An advantage of the method is that the column tilt reduces the amount of contractions and expansions of columns during thermal cycling, thereby increasing the projected life of CGA. Another advantage of the method is that it reduces shear stress, further increasing the projected life of the CGA.

High density ball grid array (BGA) package capacitor design

A circuit package is provided that includes a substrate having a first side and a second side, an integrated circuit component coupled to the second side of the substrate, and a ball grid array formed on the first side of the substrate, the ball grid array including multiple contact balls arranged in a pattern. Each of a first subset of the contact balls is electrically coupled to a first voltage input of an integrated circuit component, and each of a second subset of the contact balls is electrically coupled to a second voltage input of the integrated circuit component. The package also includes a capacitor mounted to the first side and having a first terminal coupled to a first contact ball in the first subset of the contact balls and a second terminal coupled to a second contact ball in the second subset of the contact balls.

ANISOTROPIC CONDUCTIVE FILM AND PRODUCTION METHOD OF THE SAME

An anisotropic conductive film that can be produced in high productivity and can reduce a short circuit occurrence ratio has a first conductive particle layer in which conductive particles are dispersed at a predetermined depth in a film thickness direction, and a second conductive particle layer in which conductive particles are dispersed at a depth different from that in the first conductive particle layer. In the respective conductive particle layers, the closest distances between the adjacent conductive particles are 2 times or more the average particle diameters of the conductive particles.

FLIP CHIP MOUNTING METHOD AND METHOD FOR CONNECTING SUBSTRATES

A flip chip mounting method which is applicable to the flip chip mounting of a next-generation LSI and high in productivity and reliability as well as a method for connecting substrates are provided. A circuit board 10 having a plurality of connecting terminals 11 and a semiconductor chip 20 having a plurality of electrode terminals 21 are disposed in mutually facing relation and a resin 13 containing conductive particles 12 and a gas bubble generating agent is supplied into the space therebetween. In this state, the resin 13 is heated to generate gas bubbles 30 from the gas bubble generating agent contained in the resin 13. The resin 13 is pushed toward the outside of the generated gas bubbles 30 by the growth thereof. The resin 13 pushed to the outside is self-assembled in the form of columns between the respective terminals of the circuit board 10 and the semiconductor chip 20. In this state, by pressing the semiconductor chip 20 against the circuit board 10, the conductive particles ...

HALBLEITERCHIP MIT EINER DICHTEN ANORDNUNG VON KONTAKTANSCHLÜSSEN

Ein Halbleiterchip enthält einen Halbleiterkörper mit einem aktiven Bauelementgebiet, eine oder mehrere Metallisierungsschichten, von dem Halbleiterkörper isoliert und konfiguriert zum Führen eines oder mehrerer von Masse, Strom und Signalen zu dem aktiven Bauelementgebiet und mehrere Kontaktanschlüsse, in einer äußersten der Metallisierungsschichten ausgebildet oder darauf angeordnet und konfiguriert zum Bereitstellen von externem elektrischem Zugang zum Halbleiterchip. Ein Mindestabstand zwischen benachbarten der Kontaktanschlüsse ist für den Halbleiterchip definiert. Eine oder mehrere Gruppen von benachbarten der Kontaktanschlüsse besitzen eine elektrische oder funktionale Gemeinsamkeit und einen unter dem definierten Mindestabstand liegenden Pitch. Eine einzelne gemeinsame Lötverbindung kann zwei oder mehrere der Kontaktanschlüsse des Halbleiterchips mit einem oder mehreren Kontaktanschlüssen eines Substrats wie etwa einer Leiterplatte, eines Interposers oder eines anderen Halbleiterchips ...

IMPROVED IMAGE SENSOR FOR ENDOSCOPIC USE

An endoscopic device having embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed. Embodiments of the above may include systems, methods and processes for staggering ADC or column circuit bumps in a column or sub-column hybrid image sensor using vertical interconnects are also disclosed.

Power management applications of interconnect substrates

Various applications of interconnect substrates in power management systems are described.

Through electrode substrate and semiconductor device using the through electrode substrate

LEAD STRUCTURE OF CIRCUIT

PROCESS Of HYBRIDIZATION BY PROTUBERANCES OF WELDING OF SIZES DIFFERENT FROM TWO COMPONENTS BETWEEN THEM AND DEVICE IMPLEMENTING TWO HYBRID COMPONENTS BETWEEN THEM ACCORDING TO THIS PROCESS

ATTACHMENT OF CIRCUIT DEVICES TO A SUBSTRATE

3D STACK ELECTRONIC CHIPS

Centripetal arrangement of bosses and method

A METHOD OF JOINING TWO ELECTRONIC COMPONENT, FLIP-CHIP TYPE, OBTAINED BY THE ASSEMBLY METHOD.

L'invention concerne un procédé d'assemblage de deux composants électroniques l'un à l'autre, lesdits composants comportant chacun une face d'assemblage, selon lequel on rapproche les deux faces d'assemblage l'une de l'autre selon une direction X dite d'assemblage et on applique une force donnée F à l'un et/ou l'autre des composants, l'une et/ou l'autre face(s) d'assemblage comportant: - des inserts de connexion en matériau rigide présentant une forme longitudinale allongée selon la direction X d'assemblage; - des pistes de connexion en matériau de dureté inférieure à celle des inserts et de forme longitudinale allongée transversalement à la direction X d'assemblage. procédé selon lequel: - on aligne les inserts en regard des pistes correspondantes de manière à ce que les inserts et les pistes forment deux à deux, après assemblage, au moins une intersection sensiblement transversale, - on applique la force F pour faire pénétrer les inserts dans les pistes jusqu'à obtenir l'assemblage.

ASSEMBLY COMPRISING MEANS MIXED INTERCONNECT INTERCONNECT COMPRISING AN INTERMEDIATE ELEMENT AND SEALS OF A HYDRODYNAMIC BRAKE FRITS

L'invention a pour objet un assemblage comprenant : - au moins un premier élément (100) comprenant au moins un premier plot de connexion électrique (12) ; - au moins un second élément (200) comprenant au moins un second plot de connexion électrique (21) ; - des moyens d'interconnexion électrique et mécanique, caractérisé en ce que lesdits moyens d'interconnexion électrique et mécanique comprennent au moins : - au moins un premier élément intermédiaire métallique d'interconnexion (13), à la surface d'au moins le premier plot de connexion électrique ; - au moins un joint fritté de microparticules ou de nanoparticules métalliques empilé avec ledit premier élément intermédiaire d'interconnexion ; - la température de fusion dudit premier élément intermédiaire d'interconnexion étant supérieure à la température de frittage desdites microparticules ou de nanoparticules métalliques. L'invention a aussi pour objet un procédé de fabrication d'un assemblage de l'invention ...

INTERCONNECT STRUCTURE COMPRISING FINE PITCH BACKSIDE METAL REDISTRIBUTION LINES COMBINED WITH VIAS

반도체 디바이스 패키지 제조 방법

... 반도체 소자 패키지 및 개선된 땜납 접합부 구조를 사용하여 이 패키지를 제조하는 방법이 개시되어 있다. 상기 패키지는 상부 부분보다 얇은 저부 부분을 갖는 땜납 접합부를 포함한다. 저부 부분은 몰딩 화합물에 의해 둘러싸이고, 상부 부분은 몰딩 화합물에 의해 둘러싸이지 않는다. 상기 방법은 이형 필름을 사용하여 중간 땜납 접합부 주위에 액체 몰딩 화합물을 증착 및 형성하는 것과, 그 다음에 몰딩 화합물을 감소된 높이로 에칭하는 것을 포함한다. 결과적인 땜납 접합부는 몰딩 화합물과 땜납 접합부의 인터페이스에서 웨이스트(waist)를 갖지 않는다. 몰딩 화합물을 에칭 후에, 형성 직후의 몰딩 화합물보다 약 3 미크론 더 큰 거칠기를 갖는다.

FLIP CHIP MOUNTING METHOD AND METHOD FOR CONNECTING SUBSTRATES

A flip chip mounting method and a method for connecting substrates, which are applicable to next generation LSI flip chip mounting and have high productivity and reliability. A circuit board (21) having a plurality of connecting terminals (11) and a semiconductor chip (20) having a plurality of electrode terminals (12) are arranged to face each other, and a resin (13) containing conductive particles (12) and an air bubble generating agent is supplied to a space between the circuit board and the semiconductor chip. In such state, the resin (13) is heated, air bubbles (30) are generated from the air bubble generating agent contained in the resin (13), and the resin (13) is pushed to the outside of the air bubbles (30) by growth of the generated air bubbles (30). The pushed out resin (13) are self-collected between the circuit board (10) and the terminals of the semiconductor chip (20) in a column shape. In such state, by pressing the semiconductor chip (20) to the circuit board (10), the ...

Semiconductor device and manufacturing method thereof

A semiconductor device includes a substrate including a surface, a plurality of pads disposing on the surface of the substrate, the plurality of pads includes a non-solder mask defined (NSMD) pad and a solder mask defined (SMD) pad, and the NSMD pad is arranged at a predetermined location. Further, a method of manufacturing a semiconductor device includes providing a substrate, disposing a plurality of pads on a surface of the substrate, disposing a solder mask over the surface of the substrate and the plurality of pads, forming a first recess in the solder mask to surround one of the plurality of pads, and forming a second recess in the solder mask and above one of the plurality of pads.

METHOD FOR MANUFACTURING AN ELECTRONIC DEVICE BY CONNECTING AN INTEGRATED CIRCUIT TO A SUBSTRATE USING A LIQUID CRYSTAL POLYMER LAYER WITH OPENINGS AND A CORRESPONDING DEVICE

A method of making an electronic device (10) includes forming an electrically conductive pattern (12) on a substrate (11), forming a cover layer (e.g. a liquid crystal polymer (LCP) cover layer) (13) on the substrate (11) and the electrically conductive pattern (12), forming openings (16a, 16b, 16c) in the cover layer (13) and being aligned with the electrically conductive pattern (12), positioning an integrated circuit (IC) (17) on the cover layer (13) so that bond pads (18a, 18b, 18c) of the IC (17) are aligned with the openings (16a, 16b, 16c) and heating under pressure the cover layer (13) to both mechanically secure and electrically interconnect the IC (17) to the substrate (11). An electrically conductive material (14) (solder paste, conductive epoxy, gold stud bump or solder-capped copper pillar) may be filled in the openings (16a, 16b, 16c) before the positioning of the IC (17). The substrate (11) may be a liquid crystal polymer substrate.

CIRCUIT BOARD AND METHOD FOR PRODUCING SAME

Provided is a circuit board which exhibits excellent connection reliability with a semiconductor chip, and definitively protects a wiring conductive material using fine and rigid dam parts formed in the outermost surface layer of a layered body. The layered body (31) configuring the circuit board (10) includes a plurality of connection terminal parts (41) and a wiring conductive material (62) as the conductive layer (24) of the outermost surface layer. The wiring conductive material (62) is positioned so as to pass between the plurality of connection terminal parts (41) for flip-chip-mounting a semiconductor chip (51). A resin-insulating layer (23) in the outermost surface layer of the layered body has dam parts (63) and reinforcing parts (64). The dam parts (63) cover the wiring conductive material (62). The reinforcing parts (64) are formed so as to be shorter in the interval between connection terminal parts (41) adjacent to the wiring conductive material (62) than the height (H3) of ...

METHODS AND STRUCTURES FOR A VERTICAL PILLAR INTERCONNECT

In wafer-level chip-scale packaging and flip-chip packaging and assemblies, a solder cap is formed on a vertical pillar. In one embodiment, the vertical pillar overlies a semiconductor substrate. A solder paste, which may be doped with at least one trace element, is applied on a top surface of the pillar structure. A reflow process is performed after applying the solder paste to provide the solder cap.

Semiconductor device and method of forming base substrate with cavities formed through etch-resistant conductive layer for bump locking

A semiconductor device has a base substrate with first and second etch-resistant conductive layers formed over opposing surfaces of the base substrate. First cavities are etched in the base substrate through an opening in the first conductive layer. The first cavities have a width greater than a width of the opening in the first conductive layer. Second cavities are etched in the base substrate between portions of the first or second conductive layer. A semiconductor die is mounted over the base substrate with bumps disposed over the first conductive layer. The bumps are reflowed to electrically connect to the first conductive layer and cause bump material to flow into the first cavities. An encapsulant is deposited over the die and base substrate. A portion of the base substrate is removed down to the second cavities to form electrically isolated base leads between the first and second conductive layers.

150 degree bump placement layout for an integrated circuit power grid

A 150 degree bump placement layout for an integrated circuit power grid is provided. This layout improves integrated circuit performance and reliability and gives an integrated circuit designer added flexibility and uniformity in designing the integrated circuit. Further, a patterned bump array for a top metal layer of an integrated circuit having a plurality of 150 degree bump placement structures is provided.

Semiconductor Device and Method of Forming Base Substrate with Recesses for Capturing Bumped Semiconductor Die

A semiconductor device has a base substrate with recesses formed in a first surface of the base substrate. A first conductive layer is formed over the first surface and into the recesses. A second conductive layer is formed over a second surface of the base substrate. A first semiconductor die is mounted to the base substrate with bumps partially disposed within the recesses over the first conductive layer. A second semiconductor die is mounted to the first semiconductor die. Bond wires are formed between the second semiconductor die and the first conductive layer over the first surface of the base substrate. An encapsulant is deposited over the first and second semiconductor die and base substrate. A portion of the base substrate is removed from the second surface between the second conductive layer down to the recesses to form electrically isolated base leads for the bumps and bond wires.

3D-JOINING OF MICROELECTRONIC COMPONENTS WITH CONDUCTIVELY SELF-ADJUSTING ANISOTROPIC MATRIX

... 3D joining of microelectronic components and a conductively self-adjusting anisotropic matrix are provided. In an implementation, an adhesive matrix automatically makes electrical connections between two surfaces that have electrical contacts, and bonds the two surfaces together. Conductive members in the adhesive matrix are aligned to automatically establish electrical connections between at least partially aligned contacts on each of the two surfaces while providing nonconductive adhesion between parts of the two surfaces lacking aligned contacts. An example method includes forming an adhesive matrix between two surfaces to be joined, including conductive members anisotropically aligned in an adhesive medium, then pressing the two surfaces together to automatically connect corresponding electrical contacts that are at least partially aligned on the two surfaces. The adhesive medium in the matrix secures the two surfaces together.

Tall and fine pitch interconnects

Representative implementations of devices and techniques provide interconnect structures and components for coupling various carriers, printed circuit board (PCB) components, integrated circuit (IC) dice, and the like, using tall and/or fine pitch physical connections. Multiple layers of conductive structures or materials are arranged to form the interconnect structures and components. Nonwettable barriers may be used with one or more of the layers to form a shape, including a pitch of one or more of the layers.

Fan-out semiconductor package

A fan-out semiconductor package may include a support member having a through-hole, a semiconductor chip disposed in the through-hole, a component embedded structure disposed adjacent to and spaced apart from the semiconductor chip in the through-hole by a predetermined distance, an encapsulant, and a connection member. The semiconductor chip has an active surface having connection pads disposed thereon and an inactive surface opposing the active surface. The component embedded structure has a plurality of passive components embedded therein. The encapsulant encapsulates at least portions of the support member, the component embedded structure, and the semiconductor chip. The connection member is disposed on the support member, the component embedded structure, and the active surface of the semiconductor chip. The connection member includes redistribution layers and vias electrically connecting the redistribution layers to the plurality of passive components and the connection pads of the ...

3D-joining of microelectronic components with conductively self-adjusting anisotropic matrix

... 3D joining of microelectronic components and a conductively self-adjusting anisotropic matrix are provided. In an implementation, an adhesive matrix automatically makes electrical connections between two surfaces that have electrical contacts, and bonds the two surfaces together. Conductive members in the adhesive matrix are aligned to automatically establish electrical connections between at least partially aligned contacts on each of the two surfaces while providing nonconductive adhesion between parts of the two surfaces lacking aligned contacts. An example method includes forming an adhesive matrix between two surfaces to be joined, including conductive members anisotropically aligned in an adhesive medium, then pressing the two surfaces together to automatically connect corresponding electrical contacts that are at least partially aligned on the two surfaces. The adhesive medium in the matrix secures the two surfaces together.

SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device package includes an electronic component, a first set of conductive wires electrically connected to the electronic component, and an insulation layer surrounding the first set of conductive wires. The insulation layer exposes a portion of the first set of the conductive wires. The insulation layer is devoid of a filler. 1. A semiconductor device package , comprising:an electronic component;a first set of conductive wires electrically connected to the electronic component; andan insulation layer having a top surface and surrounding the first set of conductive wires, the top surface of the insulation layer exposing a portion of the first set of the conductive wires,wherein the insulation layer is devoid of a filler.2. The semiconductor device package of claim 1 , further comprising an encapsulant encapsulating the electronic component and the insulation layer.3. The semiconductor device package of claim 1 , further comprising a first patterned conductive layer disposed over the insulation layer and including a plurality of conductive pads claim 1 , wherein the conductive pads of the first patterned conductive layer are respectively electrically connected to the exposed portion of the first set of conductive wires.4. The semiconductor device package of claim 3 , whereinthe electronic component comprises a plurality of conductive contacts electrically connected to the first set of the conductive wires; anda pitch between at least two adjacent conductive contacts of the electronic component is less than a pitch between at least two adjacent conductive pads of the first patterned conductive layer.5. The semiconductor device package of claim 1 , further comprising a second set of conductive wires disposed on the insulation layer and electrically connected to the exposed portion of the first set of the conductive wires.6. The semiconductor device package of claim 5 , further comprising an encapsulant covering the electronic component claim 5 , the ...

Tall and fine pitch interconnects

Representative implementations of devices and techniques provide interconnect structures and components for coupling various carriers, printed circuit board (PCB) components, integrated circuit (IC) dice, and the like, using tall and/or fine pitch physical connections. Multiple layers of conductive structures or materials are arranged to form the interconnect structures and components. Nonwettable barriers may be used with one or more of the layers to form a shape, including a pitch of one or more of the layers.

Increased contact alignment tolerance for direct bonding

A bonded device structure including a first substrate having a first set of conductive contact structures, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the contact structures on the first substrate, a second substrate having a second set of conductive contact structures, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the contact structures on the second substrate, and a contact-bonded interface between the first and second set of contact structures formed by contact bonding of the first non-metallic region to the second non-metallic region. The contact structures include elongated contact features, such as individual lines or lines connected in a grid, that are non-parallel on the two substrates, making contact at intersections. Alignment tolerances are thus improved while minimizing dishing and parasitic capacitance.

Semiconductor device reducing risks of a wire short-circuit and a wire flow

A semiconductor device includes a wiring substrate having first and second connection pads on a main surface thereof, a first semiconductor chip having first electrode pads, a second semiconductor chip having second electrode pads each of which has a size smaller than that of each of the first electrode pads, first wires connecting the first electrode pads with the first connection pads, and second wires connecting the second electrode pads with the second connection pads. The second wires have wide width parts at first ends. The first electrode pads are larger than the wide width parts while the second electrode pads are smaller than the wide width parts. The wide width parts are connected the second connection pads and the second wires have second ends connected to the second electrode pads via bump electrodes which are smaller than the second electrode pads.

QUASI-MONOLITHIC DIE ARCHITECTURES

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a dielectric layer having one or more conductive traces and a surface; a microelectronic subassembly on the surface of the dielectric layer, the microelectronic subassembly including a first die and a through-dielectric via (TDV) surrounded by a dielectric material, wherein the first die is at the surface of the dielectric layer; a second die and a third die on the first die and electrically coupled to the first die by interconnects having a pitch of less than 10 microns, and wherein the TDV is electrically coupled at a first end to the dielectric layer and at an opposing second end to the second die; and a substrate on and coupled to the second and third dies; and an insulating material on the surface of the dielectric layer and around the microelectronic subassembly.

Image sensor with tolerance optimizing interconnects

Embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed. Embodiments of the above may include systems, methods and processes for staggering ADC or column circuit bumps in a column or sub-column hybrid image sensor using vertical interconnects are also disclosed.

Semiconductor device and manufacturing method

Radiation sensing device, the sensing elements to abutted, and method of making the device.

ATTACHMENT OF CIRCUIT DEVICES TO A SUBSTRATE

Semiconductor Packages and Methods of Fabricating the Same

Substrate, semiconductor chip, and semiconductor package having bump, and methods of fabricating the same

Semiconductor device package and method for forming the same

OFFSET INTEGRATED CIRCUIT PACKAGING INTERCONNECTS

One embodiment of the present invention sets forth an integrated circuit package including a substrate, an integrated circuit die, and a plurality of solder bump structures. The substrate includes a first plurality of interconnects disposed on a first surface of the substrate. The integrated circuit die includes a second plurality of interconnects disposed on a first surface of the integrated circuit die. The plurality of solder bump structures couple the first plurality of interconnects to the second plurality of interconnects. The first plurality of interconnects are configured to be substantially aligned with the second plurality of interconnects when the integrated circuit package is at a first temperature within a range of about 0° C. to about 100° C. The first plurality of interconnects are configured to be offset from the second plurality of interconnects when the integrated circuit package is at a temperature above the first temperature.

Integrated circuit packaging system with substrate and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; mounting a stack substrate over the base substrate with an inter-substrate connector directly on the stack substrate and the base substrate, the inter-substrate connector having an inter-substrate connector pitch; mounting an integrated circuit over the stack substrate, the integrated circuit having an internal connector directly on the stack substrate; and attaching an external connector directly on the base substrate, the external connector having an external connector pitch greater than the inter-substrate connector pitch.

Connection body, method for manufacturing a connection body, connecting method and anisotropic conductive adhesive agent

Ensure conduction between an electronic component and a circuit substrate having reduced pitches in wiring of the circuit substrate or electrodes of the electronic component and prevent short circuits between electrode terminals of the electronic component. A connection body including an electronic component connected to a circuit substrate via an anisotropic conductive adhesive agent containing conductive particles; wherein the conductive particles are regularly arranged; and wherein the conductive particles have a particle diameter that is ½ or less than a height of a connecting electrode of the electronic component.

SEMICONDUCTOR DEVICE HAVING A PASSIVATION LAYER

A semiconductor device includes a conductive pad over an interconnect structure, wherein the conductive pad is electrically connected to an active device. The semiconductor device includes a dielectric layer over the conductive pad, wherein the dielectric layer comprises silicon oxide. The semiconductor device includes a first passivation layer directly over the dielectric layer, wherein the first passivation layer comprises silicon oxide. The semiconductor device includes a second passivation layer directly over the first passivation layer, wherein the second passivation layer comprises silicon nitride.

CONDUCTIVE PILLAR SHAPED FOR SOLDER CONFINEMENT

Pillar-type connections and methods for fabricating a pillar-type connection. A conductive layer is formed on a bond pad. A second conductive layer is formed on the first conductive layer to define a conductive pillar. The conductive pillar includes a non-planar top surface defining a recess. The recess may receive a portion of a solder body used to connect the conductive pillar with a package.

Pillar on pad interconnect structures, semiconductor dice and die assemblies including such interconnect structures, and related methods

Methods of fabricating interconnect structures for semiconductor dice comprise forming conductive elements in contact with bond pads on an active surface over a full pillar diameter of the conductive elements, followed by application of a photodefinable material comprising a photoresist to the active surface and over the conductive elements. The polyimide material is selectively exposed and developed to remove photodefinable material covering at least tops of the conductive elements. Semiconductor dice and semiconductor die assemblies are also disclosed.

Semiconductor device having a passivation layer

A semiconductor device includes a conductive pad over an interconnect structure, wherein the conductive pad is electrically connected to an active device. The semiconductor device includes a dielectric layer over the conductive pad, wherein the dielectric layer comprises silicon oxide. The semiconductor device includes a first passivation layer directly over the dielectric layer, wherein the first passivation layer comprises silicon oxide. The semiconductor device includes a second passivation layer directly over the first passivation layer, wherein the second passivation layer comprises silicon nitride.

Method for manufacturing semiconductor apparatus, method for manufacturing flip-chip type semiconductor apparatus, semiconductor apparatus, and flip-chip type semiconductor apparatus

A method for manufacturing a semiconductor apparatus, including preparing a first substrate provided with a pad optionally having a plug and a second substrate or device provided with a plug, forming a solder ball on at least one of the pad or plug of first substrate and the plug of second substrate or device, covering at least one of a pad-forming surface of first substrate and a plug-forming surface of second substrate or device with a photosensitive insulating layer, forming an opening on the pad or plug of the substrate or device that has been covered with photosensitive insulating layer by lithography, pressure-bonding the second substrate or device's plug to the pad or plug of first substrate with the solder ball through the opening, electrically connecting pad or plug of first substrate to second substrate or device's plug by baking, and curing photosensitive insulating layer by baking.

Method and system for packing optimization of semiconductor devices

Provided is a disclosure for optimizing the number of semiconductor devices on a wafer/substrate. The optimization comprises laying out, cutting, and packaging the devices efficiently.

Through-hole electrode substrate

A through-hole electrode substrate includes a substrate including a through-hole extending from a first aperture of a first surface to a second aperture of a second surface, an area of the second aperture being larger than that of the first aperture, the through-hole having a minimum aperture part between the first aperture and the second aperture, wherein an area of the minimum aperture part in a planer view is smallest among a plurality of areas of the through-hole in a planer view, a filler arranged within the through-hole, and at least one gas discharge member contacting the filler exposed to one of the first surface and the second surface.

UNDER BUMP METALLIZATIONS, SOLDER COMPOSITIONS, AND STRUCTURES FOR DIE INTERCONNECTS ON INTEGRATED CIRCUIT PACKAGING

An electronic package comprises a first die having at least one first interconnect with solder over or under a first metal feature. A second die has at least one second interconnect to the first die, each second interconnect comprising a second metal feature comprising copper, solder over or under the second metal feature, and a layer between the solder and the second metal feature, wherein the layer comprises iron and has a different material than material of the first interconnect.

HYBRIDE HALBLEITERANORDNUNG

Improved image sensor for endoscopic use

An endoscopic device having embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed. Embodiments of the above may include systems, methods and processes for staggering ADC or column circuit bumps in a column or sub-column hybrid image sensor using vertical interconnects are also disclosed.

Hybrid semiconductor component.

MANUFACTURING METHOD OF PACKAGE BOARD AND MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE TO IMPROVE THE JUNCTION RELIABILITY BETWEEN THE CHIP BUMP AND SOLDER BUMP OF THE PACKAGE SUBSTRATE

PURPOSE: A manufacturing method of package board and manufacturing method of semiconductor package are provided to enhance the bond strength by changing the chip bump of the semiconductor chip. CONSTITUTION: Provided is the circuit board(12) in which the electrode pad(16) is formed. The solder bump(18) is formed in the electrode pad. The mask having the opening corresponding to the solder bump is settled in the circuit board. The mask is removed. The solder paste is reflowed. The solder bump is hardened. © KIPO 2009 ...

Chip package and bump connecting structure thereof

A chip package including a die, a carrier, and at least a bump connecting structure is provided. The die is connected to the carrier through the bump connecting structure. The bump connecting structure includes a first metal bump, a second metal bump, and a middle metal layer disposed between the said two. The first metal bump is disposed on a die pad of the die and has a first height relative to a passivation layer thereof. The second metal bump is disposed on a carrier pad of the carrier and has a second height relative to a solder mask layer thereof. The sum of the minimum distance between the first metal bump and the second metal bump, the first height of the first metal bump, and the second height of the second metal bump is less than 60 micrometers. The melting point of the middle metal layer is less than those of the first metal bump and the second metal bump.

Semiconductor package structure and manufacturing method thereof

System in package and method for manufacturing the same

Disclosed herein is a system in package and a method of manufacturing the same. The system in package includes a first semiconductor die including a plurality of bond pads, a lead frame disposed around the first semiconductor die and provided with a plurality of signal leads, a second semiconductor die disposed in an upper side of the first semiconductor die and connected to the lead frame by wire bonding, and a fan out metal pattern disposed in a lower side of the first semiconductor die and the lead frame to connect the bond pads and the signal leads electrically and provided with a plurality of metal pads.

SEMICONDUCTOR DEVICE

This semiconductor device has a laminated chip resulting from joining a first semiconductor chip (100) and a second semiconductor chip (200). On the primary surface of the first semiconductor chip are formed a first electrode pad (110) and a first bump (120) formed on the first electrode pad. On the primary surface of the second semiconductor chip (200) is formed a second bump (220) for joining to the first bump. The first electrode pad (110) has an aperture such that the central portion has a stepped shape. The first bump (120) has a concavity of which the central portion is depressed formed in a manner so as to straddle the stepped shape of the aperture and peripheral section of the first electrode pad (110).

FLIP CHIP MOUNTING METHOD AND BUMP FORMING METHOD

A flip chip mounting method and a bump forming method which are applicable to next generation LSI flip chip mounting and have high productivity and reliability. A resin (14) containing a solder powder (16) and an air bubble generating agent is supplied to a space between a circuit board (21) having a plurality of connecting terminals (11) and a semiconductor chip (20) having a plurality of electrode terminals (12). Then, the resin (14) is heated and air bubbles (30) are generated from the air bubble generating agent contained in the resin (14). The resin (14) is pushed to the outside of the air bubbles by growth of the generated air bubbles (30), and are self-collected between the connecting terminals (11) and the electrode terminals (12). Furthermore, by heating the resin (14) and melting the solder powder (16) contained in the self-collected resin (14) between the terminals, a connector is formed between the terminals and a flip chip mounting body is completed.

Terminations

An electronic support structure comprising one or more layers of copper features such as copper routing layers, laminated within a dielectric material comprising continuous glass fibers in a polymer matrix wherein pairs of adjacent layers of copper features are coupled by a via layer, and where terminations on at least one side of the electronic support structure comprise a modified bond-on-trace attachment sites comprising selectively exposed top and partial side surfaces of copper features in an outer layer of copper features for conductive coupling solder.

High density interconnect device and method

Embodiments that allow both high density and low density interconnection between microelectronic die and motherboard via Direct Chip Attach (DCA) are described. In some embodiments, microelectronic die have a high density interconnect with a small bump pitch located along one edge and a lower density connection region with a larger bump pitch located in other regions of the die. The high density interconnect regions between die are interconnected using an interconnecting bridge made out of a material that can support high density interconnect manufactured into it, such as silicon. The lower density connection regions are used to attach interconnected die directly to a board using DCA. The high density interconnect can utilize current Controlled Collapsed Chip Connection (C4) spacing when interconnecting die with an interconnecting bridge, while allowing much larger spacing on circuit boards.

Semiconductor package structure

A semiconductor package structure includes a redistribution structure, a chip, an upper dielectric layer, a plurality of conductive members and an encapsulation layer. The redistribution structure includes a redistribution layer and a first dielectric layer disposed on the redistribution layer. The upper dielectric layer is disposed between the chip and the first dielectric layer of the redistribution structure, wherein the upper dielectric layer and the first dielectric layer are organic materials. A plurality of conductive members is disposed between the redistribution layer and the chip. Each conductive member has a first end adjacent to the chip and a second end adjacent to the redistribution structure, wherein the first end of said each conductive member contacts with the upper dielectric layer and the second end of said each conductive member contacts with the first dielectric layer.

SEMICONDUCTOR DEVICE

A semiconductor device includes a substrate, a plurality of pads disposed over the substrate, and a solder mask disposed over the substrate. The substrate includes a pair of first edges parallel to each other, a pair of second edges orthogonal to the pair of first edges, and a center point. The solder mask includes four recess portions exposing an entire top surface and sidewalls of four of the pads in four corners of the regular array, and a plurality of second recess portions exposing a portion of a top surface of other pads in the regular array. A pad size of the four pads in the four corners of the regular array exposed through the first recess portions and a pad size of the other pads exposed through the second recess portions are the same. 2. The semiconductor device of claim 1 , wherein the plurality of pads comprise four non-solder mask defined (NSMD) pads in the four corners of the regular array and a plurality of solder mask defined (SMD) pads disposed away from the four corners of the regular array.3. The semiconductor of claim 2 , wherein each of the four NSMD pads is adjacent to one of the SMD pads in a same horizontal row and another one of the SMD pads in a same vertical column.4. The semiconductor device of claim 1 , wherein the first vertical distances are similar to the second vertical distances.5. The semiconductor device of claim 1 , wherein the first vertical distances are different from the second vertical distances.6. The semiconductor device of claim 1 , wherein a first distance is defined as a distance between the center point and each of the four first recess portions claim 1 , and the first distance is greater than at least one of the first vertical distance and the second vertical distance.7. The semiconductor device of claim 6 , wherein a second distance is defined as a distance between the center point and each of the second recess portions claim 6 , and the second distance is less than the first vertical distance and the second ...

Method for bonding bare chip dies

A method is provided for assembly of a micro-electronic component, in which a conductive die bonding material is used. This material includes a conductive thermosettable resin material or flux based solder and a dynamic release layer adjacent to the conductive thermoplastic material die bonding material layer A laser beam is impinged on the dynamic release layer, adjacent to the die bonding material layer, in such a way that the dynamic release layer is activated to direct conductive die bonding material matter towards the pad structure to be treated, to cover a selected part of the pad structure with a transferred conductive die bonding material. The laser beam is restricted in timing and energy, in such a way that the die bonding material matter remains thermosetting. Accordingly, adhesive matter can be transferred while preventing that the adhesive is rendered ineffective by thermal overexposure in the transferring process.

Multiple bond via arrays of different wire heights on a same substrate

An apparatus relating generally to a substrate is disclosed. In such an apparatus, a first bond via array has first wires extending from a surface of the substrate. A second bond via array has second wires extending from the surface of the substrate. The first bond via array is disposed at least partially within the second bond via array. The first wires of the first bond via array are of a first height. The second wires of the second bond via array are of a second height greater than the first height for coupling of at least one die to the first bond via array at least partially disposed within the second bond via array. 1. A method , comprising:obtaining a substrate;forming a first bond via array of first wire bond wires (“first wires”) extending from a surface of the substrate;forming a second bond via array of second wire bond wires (“second wires”) extending from the surface of the substrate;wherein the first bond via array and the second bond via array are external to the substrate;wherein the first bond via array is disposed within a region of the second bond via array;wherein the first wires of the first bond via array are of a first height; andwherein the second wires of the second bond via array are of a second height greater than the first height for a package-on-package configuration.2. The method according to claim 1 , further comprising:coupling a first die to the first bond via array; andcoupling a second die to the second bond via array disposed over the first die.3. The method according to claim 2 , wherein the first die and at least a portion of the second die are located within a perimeter of the second bond via array.4. The method according to claim 2 , further comprising coupling opposing surfaces of the first die and the second die to one another.5. The method according to claim 2 , further comprising attaching the first wires of the first bond via array and the second wires of the second bond via array by fusion bonding to the surface of the ...

TUNED SEMICONDUCTOR AMPLIFIER

Methods and structures for improving the performance of integrated semiconductor transistors operating at high frequency and/or high power are described. Two capacitors may be connected to an input of a semiconductor transistor and tuned to suppress second-harmonic generation and to transform and match the input impedance of the device. A two-stage tuning procedure is described. The transistor may comprise gallium nitride and may be configured as a power transistor capable of handling up to 1000 W of power. A tuned transistor may operate at frequencies up to 6 GHz with a peak drain efficiency greater than 60%.

Semiconductor device for use in flip-chip bonding, which reduces lateral displacement

A semiconductor device includes multilayer chips in which a first semiconductor chip and a second semiconductor chip are bonded together. A first electrode pad is formed on a principal surface of the first semiconductor chip, and a first bump is formed on the first electrode pad. A second bump is formed on the principal surface of the second semiconductor chip such that the second bump is bonded to the first bump. The first electrode pad has an opening, and the opening and an entire peripheral portion of the opening form a stepped shape form a stepped shape. The first bump has a recessed shape that is recessed at a center thereof and covers the stepped shape.

THROUGH-HOLE ELECTRODE SUBSTRATE

A through-hole electrode substrate includes a substrate including a through-hole extending from a first aperture of a first surface to a second aperture of a second surface, an area of the second aperture being larger than that of the first aperture, the through-hole having a minimum aperture part between the first aperture and the second aperture, wherein an area of the minimum aperture part in a planer view is smallest among a plurality of areas of the through-hole in a planer view, a filler arranged within the through-hole, and at least one gas discharge member contacting the filler exposed to one of the first surface and the second surface.

Method for making electronic device with cover layer with openings and related devices

A method of making an electronic device includes forming an electrically conductive pattern on a substrate, forming a cover layer on the substrate and the electrically conductive pattern, and forming openings in the cover layer and being aligned with the electrically conductive pattern. The method also includes positioning an IC on the cover layer so that bond pads of the IC are aligned with the openings, and heating under pressure the cover layer to both mechanically secure and electrically interconnect the IC.

SEMICONDUCTOR DEVICE AND BUMP ARRANGEMENT METHOD

This invention provides a placement area with an enlarged bump pitch while avoiding the risk of underfill void generation in the bump process. The number of bumps is not changed, but the bump pitch at the center is arranged in parallel with the drying direction of the flip-chip process in the drying direction, and an arrangement area in which n rows are enlarged by +b(μm) bump pitch is made, and the chip area is finely adjusted. According to the invention, with respect to the dry air direction after flux cleaning, the power of the dry air does not change for creating a minute bump enlarged area parallel to the air in the central portion.

CONNECTION STRUCTURAL BODY AND SEMICONDUCTOR DEVICE

A connection structural body includes a first connection terminal, a second connection terminal facing the first connection terminal, and a bonding member bonding the first connection terminal and the second connection terminal. The bonding member includes an intermetallic compound layer that is formed by a roughened-surface metal film, structured by deposits of metal piled over one another such that a large number of pores are formed, and a solder layer that is disposed in the pores.

Semiconductor device

In a structure for connecting a semiconductor element having a fine pitch electrode at 50 µm pitch or less and a pad or wirings on a substrate, for preventing inter-bump short-circuit or fracture of a connected portion due to high strain generated upon heating or application of load during connection, the substrate and the semiconductor element are connected by way of a bump having a longitudinal elastic modulus (Young's modulus) of 65 GPa or more and 600 GPa or less and a buffer layer including one of tin, aluminum, indium, or lead as a main ingredient and, further, protrusions are formed to at least one of opposing surfaces of the bump and the pad or the wirings on the substrate to each other, and the surfaces are connected by ultrasonic waves.

Halbleiter und seine Herstellung

Pixel array area optimization using stacking scheme for hybrid image sensor with minimal vertical interconnects

Embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed. Embodiments of the above may include systems, methods and processes for staggering ADC or column circuit bumps in a column or sub-column hybrid image sensor using vertical interconnects are also disclosed.

Improved image sensor for endoscopic use

An endoscopic device having embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed. Embodiments of the above may include systems, methods and processes for staggering ADC or column circuit bumps in a column or sub-column hybrid image sensor using vertical interconnects are also disclosed.

Semiconductor Device and Method of Forming RDL Wider than Contact Pad along First Axis and Narrower than Contact Pad Along Second Axis

A semiconductor device has a semiconductor die and first conductive layer formed over a surface of the semiconductor die. A first insulating layer is formed over the surface of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. An opening is formed in the second insulating layer over the first conductive layer. A second conductive layer is formed in the opening over the first conductive layer and second insulating layer. The second conductive layer has a width that is less than a width of the first conductive layer along a first axis. The second conductive layer has a width that is greater than a width of the first conductive layer along a second axis perpendicular to the first axis. A third insulating layer is formed over the second conductive layer and first insulating layer.

Enhanced Bump Pitch Scaling

An integrated circuit (IC) device is provided. In an embodiment the IC device includes an IC die configured to be bonded onto an IC routing member and a first plurality of pads that is located on a surface of the IC die, each pad being configured to be coupled to a respective pad of a second plurality of pads that is located on a surface of the IC routing member. A pad of the first plurality of pads is offset relative to a respective pad of the second plurality of pads such that the pad of the first plurality of pads is substantially aligned with the respective pad of the second plurality of pads after the IC die is bonded to the IC routing member.

Power management applications of interconnect substrates

Various applications of interconnect substrates in power management systems are described.

Bump-on-Trace Interconnect

Disclosed herein is a bump-on-trace interconnect with a wetted trace sidewall and a method for fabricating the same. A first substrate having conductive bump with solder applied is mounted to a second substrate with a trace disposed thereon by reflowing the solder on the bump so that the solder wets at least one sidewall of the trace, with the solder optionally wetting between at least half and all of the height of the trace sidewall. A plurality of traces and bumps may also be disposed on the first substrate and second substrate with a bump pitch of less than about 100 μm, and volume of solder for application to the bump calculated based on at least one of a joint gap distance, desired solder joint width, predetermined solder joint separation, bump geometry, trace geometry, minimum trace sidewall wetting region height and trace separation distance.

Pixel array area optimization using stacking scheme for hybrid image sensor with minimal vertical interconnects

Embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed.

IMAGE SENSOR WITH TOLERANCE OPTIMIZING INTERCONNECTS

Embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed. Embodiments of the above may include systems, methods and processes for staggering ADC or column circuit bumps in a column or sub-column hybrid image sensor using vertical interconnects are also disclosed. 166-. (canceled)67. An imaging sensor comprising:a plurality of substrates comprising a first substrate and a second substrate;a pixel array comprising a plurality of pixel groups on the first substrate;supporting circuitry for the plurality of pixel groups comprising a plurality of supporting circuitry groups on the second substrate;a plurality of interconnects that connect the plurality of pixel groups to the supporting circuitry; anda first interconnect that connects a first pixel read bus of a first pixel group to a first circuit read bus of a first supporting circuitry group and a second interconnect that connects a second pixel read bus of a second pixel group to a second circuit read bus of a second supporting circuitry group;wherein the first pixel group and the second pixel group are adjacent to each other on the first substrate; andwherein the first supporting circuitry group and the second supporting circuitry group are not adjacent to each other on the second substrate.68. The imaging sensor of claim 67 , wherein the first interconnect connects the first pixel read bus on the first substrate to the first circuit read bus on the second substrate at a point along a physical path where the first pixel read bus on the first ...

Tall and fine pitch interconnects

Representative implementations of devices and techniques provide interconnect structures and components for coupling various carriers, printed circuit board (PCB) components, integrated circuit (IC) dice, and the like, using tall and/or fine pitch physical connections. Multiple layers of conductive structures or materials are arranged to form the interconnect structures and components. Nonwettable barriers may be used with one or more of the layers to form a shape, including a pitch of one or more of the layers.

CONDUCTIVE CONNECTIONS, STRUCTURES WITH SUCH CONNECTIONS, AND METHODS OF MANUFACTURE

A solder connection may be surrounded by a solder locking layer () and may be recessed in a hole () in that layer. The recess may be obtained by evaporating a vaporizable portion () of the solder connection. Other features are also provided. 1. A manufacturing method comprising: one or more first components each of which comprises solder and a material sublimatable or vaporizable when the solder is melted; and', 'a first layer comprising a top surface and one or more holes in the top surface, each hole containing at least a segment of a corresponding first component;, 'obtaining a first structure comprisingheating each first component to sublimate or vaporize at least part of each sublimatable or vaporizable material and provide an electrically conductive connection at a location of each first component;wherein in the heating operation at least part of each first component recedes down from the top surface to provide or increase a recess in each hole at the top surface.2. The method of wherein each hole is a through-hole.3. The method of wherein each hole's sidewall is a dielectric sidewall.4. The method of wherein the first layer is dielectric.5. The method of wherein the first layer is formed by molding.6. The method of further comprising:obtaining a second structure with one or more protruding conductive posts; andinserting each conductive post into a corresponding recess provided or increased in the heating operation, and forming a solder bond in each recess between the corresponding conductive post and the corresponding electrically conductive connection.7. The method of wherein before the heating operation claim 1 , at least a segment of each first component either:comprises of a solder core coated with the sublimatable or vaporizable material; orconsists of the sublimatable or vaporizable material.8. The method of wherein in obtaining the first structure claim 7 , the one or more first components are formed before the first layer.9. The method of wherein in ...

CORNER GUARD FOR IMPROVED ELECTROPLATED FIRST LEVEL INTERCONNECT BUMP HEIGHT RANGE

Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment an electronic package comprises a package substrate, and a first level interconnect (FLI) bump region on the package substrate. In an embodiment, the FLI bump region comprises a plurality of pads, and a plurality of bumps, where each bump is over a different one of the plurality of pads. In an embodiment, the electronic package further comprises a guard feature adjacent to the FLI bump region. In an embodiment, the guard feature comprises, a guard pad, and a guard bump over the guard pad, wherein the guard feature is electrically isolated from circuitry of the electronic package. 1. An electronic package , comprising:a package substrate; a plurality of pads; and', 'a plurality of bumps, wherein each bump is over a different one of the plurality of pads; and, 'a first level interconnect (FLI) bump region on the package substrate, wherein the FLI bump region comprises a guard pad; and', 'a guard bump over the guard pad, wherein the guard feature is electrically isolated from circuitry of the electronic package., 'a guard feature adjacent to the FLI bump region, wherein the guard feature comprises2. The electronic package of claim 1 , wherein the guard feature is proximate to a corner of the FLI bump region.3. The electronic package of claim 2 , wherein the guard feature is substantially L-shaped claim 2 , and wherein the guard feature wraps around the corner of the FLI bump region.4. The electronic package of claim 3 , wherein a first arm of the guard feature and a second arm of the guard feature have lengths that are approximately 15 mm or less.5. The electronic package of claim 1 , further comprising:a plurality of guard features, wherein the plurality of guard features are positioned around a perimeter of the FLI bump region.6. The electronic package of claim 1 , wherein the plurality of guard features are positioned proximate to two or more corners of ...

Bump structural designs to minimize package defects

A method of forming a chip package includes providing a chip with a plurality of first bumps, wherein the plurality of first bumps has a first height. The method further includes providing a substrate with a plurality of second bumps, wherein the plurality of second bumps has a second height. The method further includes bonding the plurality of first bumps to the plurality of second bumps to form a first bump structure of the chip package, wherein the first bump structure has a standoff, wherein a ratio of a sum of the first height and the second height to the standoff is equal to or greater than about 0.6 and less than 1.

STRUCTURES AND METHODS FOR PROVIDING ELECTRICAL ISOLATION IN SEMICONDUCTOR DEVICES

Semiconductor package structures and methods of forming the same are provided. An interposer is bonded to a printed circuit board (PCB) or package substrate through first solder bumps disposed on a first side of the interposer. The first solder bumps have a first pitch. A plurality of semiconductor chips are formed, and each of the semiconductor chips is bonded to a second side of the interposer through second solder bumps. The second solder bumps have a second pitch that is less than the first pitch. Each of the semiconductor chips includes a substrate with one or more transistors or integrated circuits formed thereon. 17-. (canceled)8. A method of forming a semiconductor structure , the method comprising:forming a plurality of semiconductor chips, each of the semiconductor chips comprising a substrate with one or more transistors or integrated circuits formed thereon;forming, on a top surface of each of the plurality of semiconductor chips, first solder bumps having a first pitch;flipping the plurality of semiconductor chips having the first solder bumps formed thereon;bonding the flipped plurality of semiconductor chips to a first side of an interposer through the first solder bumps; andbonding the interposer to a printed circuit board (PCB) or package substrate through second solder bumps disposed on a second side of the interposer, the second solder bumps having a second pitch that is greater than the first pitch.9. The method of claim 8 , wherein the flip-chip bonding of the semiconductor chips to the first side of the interposer comprises:bonding the plurality of semiconductor chips to the first side of the interposer in an arrangement that includes air gaps or insulating passivation material separating adjacent semiconductor chips, the air gaps or insulating passivation material providing electrical isolation between the adjacent chips.10. The method of claim 8 , wherein the flip-chip bonding of the semiconductor chips to the first side of the interposer ...

Wire Bonding For Semiconductor Devices

A semiconductor device includes an integrated circuit die having bond pads and a bond wires. The bond wires are connected to respective ones of the bond pads by a ball bond. An area of contact between the ball bond and the bond pad has a predetermined shape that is non-circular and includes at least one axis of symmetry. A ratio of the ball bond length to the ball bond width may be equal to a ratio of the bond pad length to the bond pad width. 1. A semiconductor device comprising:an integrated circuit die having a plurality of bond pads; anda plurality of bond wires, each of the plurality of bond wires being physically connected to a respective one of the plurality of bond pads by a ball bond,wherein an area of contact between each ball bond and the respective bond pad has a shape that is non-circular and includes a first axis of symmetry.2. The semiconductor device of claim 1 , wherein the shape of the area of contact includes a second axis of symmetry claim 1 , wherein the second axis of symmetry is perpendicular to the first axis of symmetry.3. The semiconductor device of claim 2 , wherein the shape of the area of contact includes no more than two axes of symmetry.4. The semiconductor device of claim 1 , wherein each ball bond includes a ball bond width and a ball bond length claim 1 , and wherein a ratio of the ball bond length to the ball bond width is greater than 1.1.5. The semiconductor device of claim 4 , wherein the ratio of the ball bond length to the ball bond width is equal to or greater than 2.0.6. The semiconductor device of claim 4 , wherein the ball bond length is the largest dimension of the shape of the area of contact along the first axis of symmetry.7. The semiconductor device of claim 4 , wherein each of the bond pads includes a bond pad width and a bond pad length claim 4 , and wherein the ratio of the ball bond length to the ball bond width is equal to a ratio of the bond pad length to the bond pad width±10%.8. The semiconductor device of ...

SYSTEM AND METHOD FOR SUB-COLUMN PARALLEL DIGITIZERS FOR HYBRID STACKED IMAGE SENSOR USING VERTICAL INTERCONNECTS

Embodiments of a hybrid imaging sensor and methods for pixel sub-column data read from the within a pixel array. 127-. (canceled)28. An imaging sensor comprising:a pixel array comprising a plurality of pixel columns disposed on a first substrate, wherein each of the plurality of pixel columns is divided into a plurality of pixel sub-columns;a plurality of supporting circuits disposed on one or more additional substrates, the plurality of supporting circuits comprising a plurality of circuit columns, wherein each of the plurality of circuit columns is divided into a plurality of circuit sub-columns; anda plurality of interconnects for electrically connecting each pixel sub-column to one of the plurality of circuit sub-columns;wherein each of the plurality of circuit sub-columns has an area, a size, and an aspect ratio, and each of the plurality of pixel sub-columns that corresponds to each one of the circuit sub-columns has an area, a size, and an aspect ratio; andwherein the aspect ratio of at least one of the circuit sub-columns has a width equal to “N” times the width of the aspect ratio of one of said pixel sub-columns and a length equal to 1/“N” times the length of the aspect ratio of one of said pixel sub-columns.29. The imaging sensor of claim 28 , wherein the one or more additional substrates are disposed remotely relative to the first substrate;30. The imaging sensor of claim 28 , further comprising a pixel sub-column bus for each of the plurality of pixel sub-columns on the first substrate and a circuit sub-column bus for each of the plurality of circuit sub-columns on the one or more additional substrates.31. The imaging sensor of claim 30 , wherein each pixel sub-column bus on the first substrate is at least partially superimposed relative to a corresponding circuit sub-column bus on the one or more additional substrates claim 30 , wherein the first substrate and the one or more additional substrates are in a stacked configuration.32. The imaging sensor ...

PACKAGE METHOD FOR GENERATING PACKAGE STRUCTURE WITH FAN-OUT INTERFACES

A semiconductor package structure includes an encapsulant, a chip module, at least one auxiliary conduction block, and a redistribution layer. The chip module is encapsulated by the encapsulant. The chip module has a chip. Each of the at least one auxiliary conduction block has a plurality of auxiliary conductive bumps and a mold layer encapsulating the plurality of auxiliary conductive bumps. The redistribution layer is disposed on the encapsulant. The redistribution layer is used to electrically connect the chip of the chip module and the at least one auxiliary conduction block. 1. A semiconductor package structure , comprising:a chip module having a chip, the chip encapsulated by a first mold layer;at least one auxiliary conduction block, each of the at least one auxiliary conduction block having a plurality of auxiliary conductive pillars and a second mold layer encapsulating the plurality of auxiliary conductive pillars;an encapsulant encapsulating the first mold layer and the second mold layer; anda redistribution layer disposed on the encapsulant, the redistribution layer being configured to electrically connect the chip of the chip module and the at least one auxiliary conduction block,wherein the chip module, the at least one auxiliary conduction block, and the encapsulant are coplanar to each other.2. The semiconductor package of claim 1 , further comprising:a plurality of conduction bumps correspondingly disposed on the chip module and the at least one auxiliary conduction block and configured to electrically connect the chip of the chip module and the at least one auxiliary conduction block to the redistribution layer.3. The semiconductor package of claim 1 , whereineach of the at least one auxiliary conduction block further having a conductive layer disposed on the second mold layer, the conductive layer being patterned to form electrical connection among the plurality of auxiliary conductive pillars.4. The semiconductor package of claim 1 , wherein the ...

Design Scheme for Connector Site Spacing and Resulting Structures

A system and method for preventing cracks in a passivation layer is provided. In an embodiment a contact pad has a first diameter and an opening through the passivation layer has a second diameter, wherein the first diameter is greater than the second diameter by a first distance of about 10 μm. In another embodiment, an underbump metallization is formed through the opening, and the underbump metallization has a third diameter that is greater than the first diameter by a second distance of about 5 μm. In yet another embodiment, a sum of the first distance and the second distance is greater than about 15 μm. In another embodiment the underbump metallization has a first dimension that is less than a dimension of the contact pad and a second dimension that is greater than a dimension of the contact pad. 1. A device comprising:a first contact pad on a first substrate, the first contact pad having a first line of symmetry and a second line of symmetry, the first line of symmetry being perpendicular to the second line of symmetry, the first contact pad having a first width along the first line of symmetry, the first contact pad having a second width along the second line of symmetry;a first underbump metallization on the first contact pad; anda first conductive bump on the first underbump metallization, the first conductive bump, having a third line of symmetry and a fourth line of symmetry, the third line of symmetry being perpendicular to the fourth line of symmetry, the first conductive bump having a third width along the third line of symmetry, the first conductive bump having a fourth width along the fourth line of symmetry, the third width being greater than the first width, the fourth width being less than the second width.2. The device of claim 1 , wherein the first width is equal to the second width.3. The device of claim 1 , wherein the first width is different from the second width.4. The device of further comprising:a second contact pad on the first substrate; ...

Copper pillar bump and flip chip package using same

Electrically conductive pillars with a solder cap are formed on a substrate with an electroplating process. A flip-chip die having solder wettable pads is attached to the substrate with the conductive pillars contacting the solder wettable pads.

Structures for Providing Electrical Isolation in Semiconductor Devices

Semiconductor package structures are provided. An interposer is bonded to a printed circuit board (PCB) or package substrate through first solder bumps disposed on a first side of the interposer. The first solder bumps have a first pitch. A plurality of semiconductor chips are formed, and each of the semiconductor chips is bonded to a second side of the interposer through second solder bumps. The second solder bumps have a second pitch that is less than the first pitch. Each of the semiconductor chips includes a substrate with one or more transistors or integrated circuits formed thereon. 1. A semiconductor package structure comprising:a printed circuit board (PCB) or package substrate;an interposer bonded to the PCB or package substrate through first solder bumps disposed on a first side of the interposer, the first solder bumps having a first pitch; anda plurality of semiconductor chips, each of the semiconductor chips (i) being bonded to a second side of the interposer through second solder bumps having a second pitch that is less than the first pitch, and (ii) comprising a substrate with one or more transistors or integrated circuits formed thereon.2. The semiconductor package structure of claim 1 , wherein adjacent semiconductor chips bonded to the interposer are separated by air gaps or insulating passivation material claim 1 , the air gaps or insulating passivation material providing electrical isolation between the adjacent chips.3. The semiconductor package structure of claim 1 , wherein the semiconductor chips are bonded to the second side of the interposer in an arrangement that minimizes distances between adjacent semiconductor chips bonded to the interposer.4. The semiconductor package structure of claim 1 , wherein diameters of the first solder bumps are greater than diameters of the second solder bumps.5. The semiconductor package structure of claim 1 , wherein the interposer comprises silicon material and conductive lines and conductive vias formed ...

Bump-on-Trace Interconnect

Disclosed herein is a bump-on-trace interconnect with a wetted trace sidewall and a method for fabricating the same. A first substrate having conductive bump with solder applied is mounted to a second substrate with a trace disposed thereon by reflowing the solder on the bump so that the solder wets at least one sidewall of the trace, with the solder optionally wetting between at least half and all of the height of the trace sidewall. A plurality of traces and bumps may also be disposed on the first substrate and second substrate with a bump pitch of less than about 100 μm, and volume of solder for application to the bump calculated based on at least one of a joint gap distance, desired solder joint width, predetermined solder joint separation, bump geometry, trace geometry, minimum trace sidewall wetting region height and trace separation distance.

SEMICONDUCTOR DEVICE PACKAGES AND METHODS OF MANUFACTURING THE SAME

A semiconductor device package includes a first conductive layer, a second conductive layer and a third conductive layer. The first conductive layer has a first pitch. The second conductive layer has a second pitch and is arranged at two different sides of the first conductive layer. The third conductive layer has a third pitch and is disposed above the first conductive layer and the second conductive layer. The third conductive layer is electrically connected to the first conductive layer. The first pitch is smaller than the third pitch, and the third pitch is smaller than the second pitch. 1. A semiconductor device package , comprising:a first conductive layer having a first pitch,a second conductive layer having a second pitch and arranged at two different sides of the first conductive layer;a third conductive layer having a third pitch and disposed above the first conductive layer and the second conductive layer, the third conductive layer electrically connected to the first conductive layer, wherein the first pitch is smaller than the third pitch, and the third pitch is smaller than the second pitch;a first dielectric layer surrounding the first conductive layer; anda second dielectric layer surrounding the first dielectric layer, the second conductive layer and a portion of the third conductive layer.2. The semiconductor device package as claimed in claim 1 , further comprising:a first die disposed on the third conductive layer; anda second die disposed adjacent to the first die and on the third conductive layer, wherein the first die is electrically connected to the second die through the first conductive layer.3. The semiconductor device package as claimed in claim 2 , whereinthe first die is disposed over a first portion of the first conductive layer and a first portion of the second conductive layer adjacent to the first portion of the first conductive layer; andthe second die is disposed over a second portion of the first conductive layer and a second ...

Semiconductor package structure

The present disclosure relates to a semiconductor package structure, including a die and a package substrate. The die includes a semiconductor substrate, multiple interconnect metal layers, and at least one inter-level dielectric disposed between ones of the interconnect metal layers. Each inter-level dielectric is formed of a low k material. An outermost interconnect metal layer has multiple first conductive segments exposed from a surface of the inter-level dielectric. The package substrate includes a substrate body and multiple second conductive segments exposed from a surface of the substrate body. The second conductive segments are electrically connected to the first conductive segments.

BVA INTERPOSER

A method for making an interposer includes forming a plurality of wire bonds bonded to one or more first surfaces of a first element. A dielectric encapsulation is formed contacting an edge surface of the wire bonds which separates adjacent wire bonds from one another. Further processing comprises removing at least portions of the first element, wherein the interposer has first and second opposite sides separated from one another by at least the encapsulation, and the interposer having first contacts and second contacts at the first and second opposite sides, respectively, for electrical connection with first and second components, respectively, the first contacts being electrically connected with the second contacts through the wire bonds. 1. (canceled)2. A microelectronic package comprising:a dielectric encapsulation having first and second oppositely-facing surfaces;a plurality of wire bonds extending between the first and second surfaces, each wire bond having first and second opposite ends at the respective first and second surfaces, and an edge surface between the first and second ends contacted by the encapsulation and separated from the edge surfaces of adjacent wire bonds by the encapsulation;a redistribution structure having one or more layers overlying the first or second surface of the encapsulation and including a plurality of electrically conductive traces extending in one or more lateral directions substantially parallel to the first surface, the traces electrically connected to the first or second ends of at least some of the wire bonds;a microelectronic element having a front surface having element contacts thereat electrically connected with at least some of the electrically conductive traces, a rear surface opposite the front surface, and edge surfaces extending between the front and rear surfaces, the microelectronic element disposed at least partially within the dielectric encapsulation, with the edge surfaces at least partially covered by the ...

Electronic package and method for fabricating the same

An electronic package includes a circuit structure having a first electronic component disposed on one side thereof, and a second electronic component and conductive pillars disposed on the other side thereof. The second electronic component and the conductive pillars are encapsulated by an encapsulant, and end faces of the conductive pillars are exposed from the encapsulant, allowing the exposed end faces to be connected to an external circuit board. As the end faces of the conductive pillars are used as contact structures, fine-pitch electronic packages can be achieved. Also, by providing sufficient space attributed to the tall columnar structures of the conductive pillars, the second electronic component of an appropriate thickness can be obtained, allowing the electronic package to be suitable for applications requiring high voltages and/or high currents. A method for fabricating an electronic package is further provided.

Advanced Device Assembly Structures And Methods

A microelectronic assembly includes a first substrate having a surface and a first conductive element and a second substrate having a surface and a second conductive element. The assembly further includes an electrically conductive alloy mass joined to the first and second conductive elements. First and second materials of the alloy mass each have a melting point lower than a melting point of the alloy. A concentration of the first material varies in concentration from a relatively higher amount at a location disposed toward the first conductive element to a relatively lower amount toward the second conductive element, and a concentration of the second material varies in concentration from a relatively higher amount at a location disposed toward the second conductive element to a relatively lower amount toward the first conductive element. 1. A microelectronic assembly , comprising:a first substrate having a first surface and first conductive elements;a second substrate having a second surface and second conductive elements; anda plurality of electrically conductive masses, each mass joined to a respective pair of the first and second conductive elements,wherein each electrically conductive mass includes a first material, a second material, and a third material, the third material selected to increase the melting point of an alloy including the third material and at least one of the first material or the second material,wherein a concentration of the first material varies from a relatively higher amount at a location disposed toward the respective first conductive element to a relatively lower amount toward the respective second conductive element,wherein a concentration of the second material varies in concentration from a relatively higher amount at a location disposed toward the respective second conductive element to a relatively lower amount toward the respective first conductive element, andwherein the third material has a highest concentration at a location ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a substrate including a surface, a plurality of pads disposing on the surface of the substrate, the plurality of pads includes a non-solder mask defined (NSMD) pad and a solder mask defined (SMD) pad, and the NSMD pad is arranged at a predetermined location. Further, a method of manufacturing a semiconductor device includes providing a substrate, disposing a plurality of pads on a surface of the substrate, disposing a solder mask over the surface of the substrate and the plurality of pads, forming a first recess in the solder mask to surround one of the plurality of pads, and forming a second recess in the solder mask and above one of the plurality of pads. 2. The semiconductor device of claim 1 , wherein the plurality of pads are arranged in a regular array including a plurality of horizontal rows and a plurality of vertical columns.3. The semiconductor device of claim 1 , wherein the plurality of pads comprise a plurality of non-solder mask defined (NSMD) pads and a plurality of solder mask defined (SMD) pads.4. The semiconductor of claim 3 , wherein the first recess portion entirely exposes one of the NSMD pads claim 3 , and the second recess portion partially exposes one of the SMD pads.5. The semiconductor device of claim 1 , wherein first recess portion is disposed on a corner of the semiconductor device and the second recess portion is disposed away from the corner of the semiconductor device.6. The semiconductor device of claim 1 , wherein the first distance between the central point and the first edge is greater than a fourth distance between the central point and the second recess portion claim 1 , and the second distance between the central point and the second edge is greater than the fourth distance between the central point and the second recess portion.7. A semiconductor device claim 1 , comprising:a substrate comprising a pair of first edges parallel to each other, a pair of second edges orthogonal to the first edge, ...

CONDUCTIVE PILLAR SHAPED FOR SOLDER CONFINEMENT

A pillar-type connection includes a first conductive layer that includes a hollow core. A second conductive layer is connected to the first conductive layer defining a conductive pillar that includes a top surface defining a recess aligned with the hollow core. 1. A pillar-type connection comprising:a first conductive layer that includes a hollow core; anda second conductive layer coupled to the first conductive layer defining a conductive pillar that includes a top surface defining a recess aligned with the hollow core.2. The pillar-type connection of claim 1 , further comprising:a conductive via that terminates at a top surface of the first conductive layer; anda plating mask that includes an opening aligned with the conductive via.3. The pillar-type connection of claim 2 , further comprising:a sacrificial plug disposed within the opening;wherein the top surface of the conductive pillar is adjusted using factors comprising at least one of dimensions of the sacrificial plug and height of the hollow core before removing the sacrificial plug.4. The pillar-type connection of claim 3 , further comprising:vertical surfaces aligned parallel to sidewalls of the opening in the plating mask and inclined surfaces connecting a horizontal surface and a vertical surface to define a cavity, wherein the sacrificial plug has a top surface, and the first conductive layer is formed inside the opening by depositing the first conductive layer such that the top surface of the first conductive layer is recessed relative to the top surface of the sacrificial plug.5. The pillar-type connection of claim 2 , wherein the sacrificial plug is formed as part of a different plating mask.6. The pillar-type connection of claim 3 , further comprising:a feature on a package, the feature attached to the conductive pillar using a solder body, wherein the recess is dimensioned to receive the feature so that the feature is self-aligned with the conductive pillar during assembly.7. The pillar-type ...

ELECTRONIC DEVICE AND SEMICONDUCTOR DEVICE

The electronic device includes a first semiconductor device having a logic circuit, a second semiconductor device having a memory circuit, and a wiring substrate to which the first and second semiconductor devices are mounted. The first semiconductor device has a plurality of terminals arranged on a main surface. The plurality of terminals includes a plurality of differential pair terminals electrically connected to the second semiconductor device and to which differential signals are transmitted. The plurality of differential pair terminals is arranged along a side of the main surface, that is extending in an X direction, and includes a first differential pair terminal constituted by a pair of terminals arranged along a Y direction orthogonal to the X direction, and a second differential pair terminal constituted by a pair of terminals arranged along the Y direction. The first and second differential pair terminals are arranged along the Y direction.

INTERCONNECT STRUCTURES FOR FINE PITCH ASSEMBLY OF SEMICONDUCTOR STRUCTURES

A semiconductor structure includes a substrate having first and second opposing surfaces and a plurality of electrical connections extending between the first and second surfaces. The semiconductor structure also includes one or more interconnect pads having first and second opposing surfaces and one or more sides. The first surface of each one of the interconnect pads is disposed over or beneath select portions of at least the second surface of the substrate and is electrically coupled to select ones of the plurality of electrical connections. The semiconductor structure additionally includes an isolating layer having first and second opposing surfaces and openings formed in select portions of the isolating layer extending between the second surface of the isolating layer and the second surfaces of the interconnect pads. A corresponding method for fabricating a semiconductor structure is also provided. 1. A method for fabricating a semiconductor structure , comprising:providing a substrate having first and second opposing surfaces and a plurality of electrical connections extending between the first and second surfaces;providing one or more interconnect pads having first and second opposing surfaces and one or more sides, wherein the first surface of each one of the interconnect pads is disposed over or beneath select portions of at least the second surface of the substrate and is electrically coupled to select ones of the plurality of electrical connections;applying an isolating layer having first and second opposing surfaces, wherein the first surface of the isolating layer is disposed over the second surface of the substrate and the second surfaces and one or more sides of the interconnect pads;forming openings having a predetermined shape in select portions of the isolating layer extending between the second surface of the isolating layer and the first surface of the isolating layer;providing one or more pad interconnects having a pad portion and an ...

PACKAGE ON PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME

The described embodiments of mechanisms of forming a package on package (PoP) structure involve bonding with connectors with non-solder metal balls to a packaging substrate. The non-solder metal balls may include a solder coating layer. The connectors with non-solder metal balls can maintain substantially the shape of the connectors and control the height of the bonding structures between upper and lower packages. The connectors with non-solder metal balls are also less likely to result in bridging between connectors or disconnection (or cold joint) of bonded connectors. As a result, the pitch of the connectors with non-solder metal balls can be kept small. 1. A semiconductor device package , comprising:a substrate with a contact pad;a semiconductor die bonded to the contact pad by a first bonding structure; andwherein the first bonding structure includes a metal ball comprising a non-solder material, a solder layer over a surface of the non-solder material, and an intermediate layer between the solder layer and the non-solder material, wherein the intermediate layer is configured to prevent formation of an intermetallic compound between the metal ball and the solder layer, wherein the non-solder material includes copper, aluminum, silver, gold, nickel, tungsten, alloys thereof, or combinations thereof, and the intermediate layer comprises titanium.2. The semiconductor device package of claim 1 , wherein a width or diameter of the metal ball is in a range from about 100 μm to about 200 μm.3. The semiconductor device package of claim 1 , wherein the semiconductor device package has another metal ball next to the metal ball claim 1 , and a pitch of the metal ball and the another metal ball is in a range from about 150 μm to about 300 μm.4. The semiconductor device package of claim 1 , wherein the solder layer is a continuous layer that coats the intermediate layer.5. The semiconductor device package of claim 1 , wherein the metal ball is arranged over and electrically ...

Method and Apparatus for Image Sensor Packaging

A backside illuminated image sensor having a photodiode and a first transistor in a sensor region and located in a first substrate, with the first transistor electrically coupled to the photodiode. The image sensor has logic circuits formed in a second substrate. The second substrate is stacked on the first substrate and the logic circuits are coupled to the first transistor through bonding pads, the bonding pads disposed outside of the sensor region.

LEAD STRUCTURE OF CIRCUIT

The present invention discloses a lead structure of the circuit, which comprises a first lead and a second lead. The first lead includes a first bump connecting part and a first lead segment. The first lead segment is connected to the first bump connecting part. The width of the first lead segment is smaller than the width of the first bump connecting part. The second lead is adjacent to the first lead and there is a lead gap therebetween. The second lead also includes a second bump connecting part and a first lead segment. The first lead segment of the second lead is connected to the second bump connecting part. The second bump connecting part and the first bump connecting part are arranged staggeredly. The second bump connecting part is adjacent to the first lead segment of the first lead. 1. A lead structure of the circuit , comprising:a first lead, including a first bump connecting part and a first lead segment, said first lead segment connected to said first bump connecting part, and the width of said first lead segment is smaller than the width of said first bump connecting part; anda second lead, adjacent to said first lead, having a lead gap between said second lead and said first lead, including a second bump connecting part and a first lead segment, said first lead segment of said second lead connected to said second bump connecting part, said first bump connecting part and said second bump connecting part arranged staggeredly, and said second bump connecting part adjacent to said first lead segment of said first lead.2. The lead structure of the circuit of claim 1 , wherein the width of said first lead segment of said second lead is smaller than the width of said second bump connecting part.3. The lead structure of the circuit of claim 1 , wherein said first lead segment of said first lead is adjacent to said first lead segment of said second lead; said first lead segment of said first lead and said first lead segment of said second lead form a gap ...

Chip stack with electrically insulating walls

A chip stack is provided and includes two or more chips, a solder joint operably disposed between adjacent ones of the two or more chips, the solder joint occupying about 25-30% or more of an area of the chip stack and insulating walls disposed on at least one of the two or more chips to separate the solder joint from an adjacent solder joint.

Structures for Providing Electrical Isolation in Semiconductor Devices

Semiconductor package structures are provided. An interposer is bonded to a printed circuit board (PCB) or package substrate through first solder bumps disposed on a first side of the interposer. The first solder bumps have a first pitch. A plurality of semiconductor chips are formed, and each of the semiconductor chips is bonded to a second side of the interposer through second solder bumps. The second solder bumps have a second pitch that is less than the first pitch. Each of the semiconductor chips includes a substrate with one or more transistors or integrated circuits formed thereon. 1. A semiconductor package structure comprising:a printed circuit board (PCB) or package substrate;an interposer bonded to the PCB or package substrate through first solder bumps disposed on a first side of the interposer; anda plurality of semiconductor chips, each of the semiconductor chips being bonded to a second side of the interposer through second solder bumps;wherein the first solder bumps have diameters of 10 μm or less, and the second solder bumps have diameters of 100 to 300 μm.2. The semiconductor package structure of claim 1 , wherein adjacent semiconductor chips bonded to the interposer are separated by air gaps or insulating passivation material claim 1 , the air gaps or insulating passivation material providing electrical isolation between the adjacent chips.3. The semiconductor package structure of claim 1 , wherein the semiconductor chips are bonded to the second side of the interposer in an arrangement that minimizes distances between adjacent semiconductor chips bonded to the interposer.4. The semiconductor package structure of claim 1 , wherein diameters of the first solder bumps are greater than diameters of the second solder bumps.5. The semiconductor package structure of claim 1 , wherein the interposer comprises silicon material and conductive lines and conductive vias formed in the silicon material claim 1 , the conductive lines and conductive vias being ...

PACKAGE SYSTEM FOR INTEGRATED CIRCUITS

A package system includes a first interposer including a first substrate having first and second primary surfaces on opposite sides of the first substrate. The package system includes a first interconnect structure over the first surface, the first interconnect structure having a first metallic line pitch LP. The package system includes a plurality of first through silicon via (TSV) structures in the first substrate. The package system includes a molding compound material partially enveloping the first substrate. The package system includes a plurality of through vias in the molding compound material, wherein each through via of the plurality of through vias is offset from the first substrate. The package system includes a second interconnect structure on a second surface of the first substrate. The second interconnect structure has a second metallic line pitch LP, and LP>LP. The package system includes a first integrated circuit over the first interposer. 1. A package system comprising: [{'sub': '1', 'a first substrate having first and second primary surfaces, the first and second primary surfaces being on opposite sides of the first substrate with secondary surfaces extending between the primary surfaces, and the first substrate has a first coefficient of thermal expansion (CTE);'}, {'sub': '1', 'a first interconnect structure over the first surface, the first interconnect structure having a first metallic line pitch LP;'}, 'a plurality of first through silicon via (TSV) structures in the first substrate;', 'a molding compound material partially enveloping the first substrate and covering both the second primary surface and the secondary surfaces;', 'a plurality of through vias in the molding compound material, wherein each through via of the plurality of through vias are parallel to each first TSV structure of the plurality of first TSV structures and each through via of the plurality of through vias is offset from the secondary surfaces in a direction away from ...

BUMP-ON-TRACE INTERCONNECT

Disclosed herein is a bump-on-trace interconnect with a wetted trace sidewall and a method for fabricating the same. A first substrate having conductive bump with solder applied is mounted to a second substrate with a trace disposed thereon by reflowing the solder on the bump so that the solder wets at least one sidewall of the trace, with the solder optionally wetting between at least half and all of the height of the trace sidewall. A plurality of traces and bumps may also be disposed on the first substrate and second substrate with a bump pitch of less than about 100 μm, and volume of solder for application to the bump calculated based on at least one of a joint gap distance, desired solder joint width, predetermined solder joint separation, bump geometry, trace geometry, minimum trace sidewall wetting region height and trace separation distance. 1. A method of forming a semiconductor package , the method comprising:receiving a first semiconductor package, the first semiconductor package comprising a first substrate and a conductive pillar at a first side of the first substrate;receiving a second semiconductor package, the second semiconductor package comprising a second substrate and a conductive trace on a first surface of the second substrate, a sidewall of the conductive trace having a first height; andbonding the conductive pillar to the conductive trace using a conductive joint, wherein after the bonding, the conductive joint covers the sidewall of the conductive trace by at least half the first height, and the conductive pillar is spaced from the conductive trace by a first distance, the first distance being smaller than the first height.2. The method of claim 1 , wherein the conductive joint comprises solder.3. The method of claim 2 , wherein bonding the conductive pillar comprises performing a reflow process to bond the conductive pillar to the conductive trace.4. The method of claim 1 , wherein a first surface of the conductive pillar distal from the ...

PRE-PATTERNED FINE-PITCH BOND PAD INTERPOSER

Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises, a package substrate, a die stack on the package substrate, and a mold layer encapsulating the die stack. In an embodiment, the electronic package further comprises a bond pad having a first surface and a second surface, where the die stack is electrically coupled to the first surface of the bond pad with a wire bond, and the second surface of the bond pad is substantially coplanar with a surface of the mold layer. 1. An electronic package , comprising:a package substrate;a die stack on the package substrate;a mold layer encapsulating the die stack; anda bond pad having a first surface and a second surface, wherein the die stack is electrically coupled to the first surface of the bond pad with a wire bond, and wherein the second surface of the bond pad is substantially coplanar with a surface of the mold layer.2. The electronic package of claim 1 , further comprising a heat spreader over a surface of the die stack.3. The electronic package of claim 2 , wherein a surface of the heat spreader is substantially coplanar with a surface of the mold layer.4. The electronic package of claim 2 , wherein a thickness of the heat spreader is substantially coplanar with a thickness of the bond pad.5. The electronic package of claim 2 , wherein the heat spreader and the bond pad comprise the same material.6. The electronic package of claim 1 , wherein the die stack is separated from the package substrate by the mold layer.7. The electronic package of claim 1 , further comprising:a wire bond electrically coupling the second surface of the bond pad to the package substrate.8. The electronic package of claim 1 , further comprising:a second die stack positioned above the first die stack.9. The electronic package of claim 8 , wherein the second die stack is encapsulated in a second mold layer.10. The electronic package of claim 9 ...

OFFSET INTERPOSERS FOR LARGE-BOTTOM PACKAGES AND LARGE-DIE PACKAGE-ON-PACKAGE STRUCTURES

An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads. 2. The structure of wherein the first land side pad is electrically coupled to the first POP side pad by direct contact with a via interconnect structure.3. The structure of wherein the center to center spacing between the first land side pad and the second land side pad does not overlap the spacing between the first POP side pad and the second POP side pad.4. The structure of wherein the center to center spacing between the first land side pad and the second land side pad overlaps the spacing between the first POP side pad and the second POP side pad.5. The structure of wherein the first and second land side pads are part of an array of land side pads that are all configures at a first pitch claim 1 , and wherein the first and second POP side pads are part of an array of POP side pads that are all configured at a second pitch claim 1 , wherein the first pitch is larger than the second pitch.6. The structure of wherein the first and second land side pads are part of an array of land side pads that are all configures at a first pitch claim 1 , and wherein the first and second POP side pads are part of an array of POP side pads that are all configured at a second pitch claim 1 , wherein the first pitch is larger than the second pitch.7. The structure of wherein the memory device is electrically coupled to the POP substrate by one of a wire bond connection or a ...

PACKAGE ON PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME

Some embodiments relate to a semiconductor device package, which includes a substrate with a contact pad. A non-solder ball is coupled to the contact pad at a contact pad interface surface. A layer of solder is disposed over an outer surface of the non-solder ball, and has an inner surface and an outer surface which are generally concentric with the outer surface of the non-solder ball. An intermediate layer separates the non-solder ball and the layer of solder. The intermediate layer is distinct in composition from both the non-solder ball and the layer of solder. Sidewalls of the layer of solder are curved or sphere-like and terminate at a planar surface, which is disposed at a maximum height of the layer of solder as measured from the contact pad interface surface. 1. A semiconductor device comprising a solder ball , the solder ball comprising:a metal ball;a layer of solder over an outer surface of the metal ball; andan intermediate layer separating the metal ball and the layer of solder, wherein the intermediate layer has a first annular thickness on a first portion of the metal ball and has a second annular thickness on a second portion of the metal ball, the second annular thickness being greater than the first annular thickness.2. The semiconductor device of claim 1 , further comprising:a semiconductor substrate; anda contact pad over the semiconductor substrate, wherein the metal ball is disposed over the contact pad; andwherein the intermediate layer is elongated along an axis that is perpendicular to an upper surface of the contact pad, such that the intermediate layer has a height as measured from the upper surface of the contact pad to an uppermost extent of the intermediate layer along the axis, and has a diametric width between its outermost sidewalls, the diametric width being less than the height.3. The semiconductor device of claim 1 , wherein the intermediate layer is configured to prevent formation of an intermetallic compound between the metal ...

WIRING BOARD AND METHOD FOR MOUNTING SEMICONDUCTOR ELEMENT ON WIRING BOARD

A wiring board of the present invention includes an insulating board having a mounting portion on an upper surface to mount a semiconductor element, and semiconductor element connection pads formed on the mounting portion, on which at least three first dummy pads arranged on a center portion of the mounting portion, and at least three second dummy pads arranged on a peripheral portion of the mounting portion, are formed, and a dummy solder bump is formed on each of the first dummy pad and the second dummy pad. 1. A wiring board comprising:an insulating board having a mounting portion on an upper surface to mount a semiconductor element;a plurality of semiconductor element connection pads formed on the mounting portion, whereinat least three first dummy pads arranged on a center portion of the mounting portion so as to surround the center portion, and at least three second dummy pads arranged on a peripheral portion of the mounting portion so as to surround the center portion, are formed,a dummy solder bump is formed on each of the first and second dummy pads, anda height of the dummy solder bump is greater than a total of a height of an electrode terminal formed on the semiconductor element to be mounted and a height of a solder bump formed on the electrode terminal.2. The wiring board according to claim 1 , whereinthe insulating board has a thermal expansion coefficient of 10 ppm/° C. to 20 ppm/° C. with respect to a direction along a connection surface with the semiconductor element.3. The wiring board according to claim 1 , whereinthe semiconductor element to be mounted has a thermal expansion coefficient of 3 ppm/° C. to 4 ppm/° C. with respect to a direction along a connection surface with the wiring board.4. The wiring board according to claim 1 , whereinthe semiconductor element connection pads are formed at an arrangement pitch smaller by 0.1 μm to 1 μm than an arrangement pitch of the electrode terminals provided on the semiconductor element corresponding ...

Semiconductor device and method of manufacturing the same

A semiconductor chip includes a chip body and a plurality of solder-including electrodes provided on an element-formation surface of the chip body. A packaging substrate includes a substrate body, and a plurality of wirings and a solder resist layer that are provided on a front surface of the substrate body. The plurality of solder-including electrodes include a plurality of first electrodes and a plurality of second electrodes. The plurality of first electrodes supply a first electric potential, and the plurality of second electrodes supply a second electric potential different from the first electric potential. The plurality of first electrodes and the plurality of second electrodes are disposed alternately in both a row direction and a column direction, in a central part of the chip body. The plurality of wirings include a plurality of first wirings and a plurality of second wirings. The plurality of first wirings connect the plurality of first electrodes, and the plurality of second wirings connect the plurality of second electrodes.

Protrusion Bump Pads for Bond-on-Trace Processing

An embodiment apparatus includes a dielectric layer, a conductive trace in the dielectric layer, and a bump pad. The conductive trace includes a first portion having an exposed top surface, wherein the exposed top surface is recessed from a top surface of the dielectric layer. Furthermore, the bump pad is disposed over and is electrically connected to a second portion of the conductive trace. 1. A device comprising:a substrate;an insulating layer on the substrate;a conductive line in the insulating layer; anda conductive pad in the insulating layer and directly over a first region of the conductive line, wherein the conductive pad has a different material composition than the conductive line, wherein a top surface of the conductive pad is not higher than a top surface of the insulating layer, wherein no portions of the insulating layer and no portions of the conductive pad extend directly over a second region of the conductive line.2. The device of claim 1 , wherein the conductive pad comprises nickel or tin claim 1 , and wherein the conductive line comprises copper.3. The device of claim 1 , wherein the conductive pad is connected to a contact pad through the conductive line claim 1 , wherein the conductive pad is disposed in the insulating layer claim 1 , and wherein the device further comprises a conductive pillar extending from the contact pad through the insulating layer.4. The device of claim 3 , wherein the contact pad and the conductive line have a same material composition.5. The device of claim 3 , wherein a top surface of the contact pad is lower than a top surface of the insulating layer.6. The device of further comprising:an integrated circuit chip; anda solder region physically coupling the integrated circuit chip to the conductive pad.7. The device of claim 1 , wherein a top surface of the conductive pad is substantially level with the top surface of the insulating layer.8. The device of claim 1 , wherein a top surface of the second region of the ...

Semiconductor devices having a tsv, a front-side bumping pad, and a back-side bumping pad

Semiconductor devices are provided. The semiconductor devices include a substrate, a first interlayer insulating layer disposed on a front-side of the substrate, a TSV structure passing through the first interlayer insulating layer and the substrate. The TSV structure has a bottom end protruding from a back-side of the substrate, a back-side insulating layer and a back-side passivation layer disposed on the back-side of the substrate, and a bumping pad buried in the back-side insulating layer and the back-side passivation layer and disposed on the bottom end of the TSV structure. The bottom end of the TSV structure protrudes into the back-side bumping pad, and top surfaces of the back-side passivation layer and the back-side bumping pad are coplanar.

IMAGE SENSOR WITH TOLERANCE OPTIMIZING INTERCONNECTS

Embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed. Embodiments of the above may include systems, methods and processes for staggering ADC or column circuit bumps in a column or sub-column hybrid image sensor using vertical interconnects are also disclosed. 1. An imaging sensor comprising:a plurality of substrates comprising a first substrate and at least one second, subsequent supporting substrate;a pixel array;a plurality of interconnects; anda plurality of supporting circuits;wherein the first substrate of the plurality of substrates comprises a plurality of pixel read buses and the pixel array, wherein the pixel array comprises a plurality of pixel groups, and wherein there is one pixel read bus per pixel group;wherein the at least one second, subsequent supporting substrate comprises a plurality of circuit buses and the plurality of supporting circuits, including a plurality of readout supporting circuits, with one circuit bus per readout supporting circuit;wherein said plurality of supporting circuits are electrically connected to, and in electrical communication with, said pixel array via the plurality of interconnects disposed between said first substrate and said at least one second, subsequent supporting substrate;wherein each of the plurality of interconnects reads out a pixel group to one of the circuit buses;wherein said at least one second, subsequent supporting substrate is disposed behind said first substrate relative to an object to be imaged;wherein said plurality of ...

DISPLAY APPARATUS

A display device includes a substrate including a display region, and a peripheral region that is outside of the display region, a plurality of dummy pads at the peripheral region, an insulating layer covering the plurality of dummy pads, wherein top surfaces of first portions of the insulating layer above the plurality of dummy pads are higher than top surfaces of second portions of the insulating layer between the plurality of dummy pads, and a plurality of pads over the second portions of the insulating layer at the peripheral region. 1. A display device comprising:a substrate comprising a display region, and a peripheral region that is outside of the display region;a first dummy pad and a second dummy pad at the peripheral region;an insulating layer completely covering the first and second dummy pads such that each of the first and second dummy pads does not contact a conductive layer, wherein top surfaces of first portions of the insulating layer above centers of the first and second dummy pads are higher than a top surface of a second portion of the insulating layer between the first and second dummy pads; anda pad over the second portion of the insulating layer at the peripheral region, the pad being electrically connected to an electronic chip or a printed circuit board.2. The display device of claim 1 , wherein a first distance from a top surface of the substrate to the top surfaces of the first portions of the insulating layer is greater than a second distance from the top surface of the substrate to the top surface of the pad.3. The display device of claim 1 , further comprising conductive balls having a diameter that is greater than a difference between the first distance and the second distance claim 1 , and being in electrical contact with the top surface of the pad claim 1 ,wherein the electronic chip or the printed circuit board is in electrical contact with the conductive balls to be electrically connected to the pad.4. The display device of claim 1 ...

Semiconductor package and method of manufacturing semiconductor package

A semiconductor package includes a wiring substrate that includes a first conductive member; a semiconductor chip that is mounted on the wiring substrate and includes a second conductive member, the first conductive member and the second conductive member being positioned to face each other; and a bonding member that bonds and electrically connects the first conductive member and the second conductive member, at least one of the first conductive member and the second conductive member being a pillar-shaped terminal, the bonding member being bonded to an end surface of the pillar-shaped terminal and a portion of a side surface of the pillar-shaped terminal, an intermetallic compound layer being formed at an interface of the bonding member and the pillar-shaped terminal.

High density interconnect device and method

Embodiments that allow both high density and low density interconnection between microelectronic die and motherboard via Direct Chip Attach (DCA) are described. In some embodiments, microelectronic die have a high density interconnect with a small bump pitch located along one edge and a lower density connection region with a larger bump pitch located in other regions of the die. The high density interconnect regions between die are interconnected using an interconnecting bridge made out of a material that can support high density interconnect manufactured into it, such as silicon. The lower density connection regions are used to attach interconnected die directly to a board using DCA. The high density interconnect can utilize current Controlled Collapsed Chip Connection (C4) spacing when interconnecting die with an interconnecting bridge, while allowing much larger spacing on circuit boards.

SEMICONDUCTOR ASSEMBLY HAVING ANTI-WARPING CONTROLLER AND VERTICAL CONNECTING ELEMENT IN STIFFENER

A semiconductor assembly includes an anti-warping controller, a semiconductor device, a balance layer and a first routing circuitry positioned within a through opening of a stiffener and a second routing circuitry positioned outside of the through opening of the stiffener and electrically connected to the first routing circuitry and a vertical connecting element of the stiffener. The mechanical robustness of the stiffener and the anti-warping controller can prevent the assembly from warping, whereas the vertical connecting element of the stiffener provides electrical connection between two opposite sides of the stiffener. The first routing circuitry can enlarge the pad size and pitch of the semiconductor device, whereas the second routing circuitry not only provides further fan-out wiring structure, but also mechanically binds the first routing circuitry with the stiffener. 1. A semiconductor assembly having an anti-warping controller and a vertical connecting element in a stiffener , comprising:a subassembly that includes an anti-warping controller, a first semiconductor device, a balance layer and a first routing circuitry having a first surface and an opposite second surface, wherein (i) the first semiconductor device is attached to the anti-warping controller and electrically coupled to the first routing circuitry from the first surface of the first routing circuitry, (ii) the first routing circuitry includes at least one conductive trace laterally extending beyond peripheral edges of the first semiconductor device, and (iii) the balance layer laterally surrounds the first semiconductor device and covers the first surface of the first routing circuitry;a stiffener having a first surface, an opposite second surface, a through opening and a first vertical connecting element, wherein the through opening extends through the stiffener between the first surface and the second surface thereof, and the subassembly is positioned within the through opening of the ...

SEMICONDUCTOR LOGIC DEVICE AND SYSTEM AND METHOD OF EMBEDDED PACKAGING OF SAME

A reconfigured semiconductor device includes a semiconductor device comprising an active surface having a plurality of input/output (I/O) pads spaced at a non-solderable pitch thereon and at least one redistribution layer overlying the active surface of the semiconductor device. Each at least one redistribution layer includes an insulating layer and a patterned conductive layer comprising a plurality of discrete terminal pads formed on the insulating layer, each of the plurality of discrete terminal pads electrically coupled to a respective I/O pad of the plurality of I/O pads by a conductive via formed through the insulating layer. 1. A reconfigured semiconductor device comprising:a semiconductor device comprising an active surface having a plurality of input/output (I/O) pads spaced at a non-solderable pitch thereon; and an insulating layer; and', 'a patterned conductive layer comprising a plurality of discrete terminal pads formed on the insulating layer, each of the plurality of discrete terminal pads electrically coupled to a respective I/O pad of the plurality of I/O pads by a conductive via formed through the insulating layer., 'at least one redistribution layer overlying the active surface of the semiconductor device, each at least one redistribution layer comprising2. The reconfigured semiconductor device of wherein the plurality of I/O pads comprise a plurality of signal I/O pads claim 1 , a plurality of power I/O pads claim 1 , and a plurality of ground I/O pads; and a first plurality of discrete terminal pads electrically coupled to the plurality of signal I/O pads; and', 'a second plurality of discrete terminal pads electrically coupled to respective I/O pads of the plurality of power I/O pads and the plurality of ground I/O pads, the second plurality of discrete terminal pads larger than the first plurality of discrete terminal pads., 'wherein the plurality of discrete terminal pads comprise3. The reconfigured semiconductor device of wherein the ...

THROUGH-HOLE ELECTRODE SUBSTRATE

A through-hole electrode substrate includes a substrate including a through-hole extending from a first aperture of a first surface to a second aperture of a second surface, an area of the second aperture being larger than that of the first aperture, the through-hole having a minimum aperture part between the first aperture and the second aperture, wherein an area of the minimum aperture part in a planer view is smallest among a plurality of areas of the through-hole in a planer view, a filler arranged within the through-hole, and at least one gas discharge member contacting the filler exposed to one of the first surface and the second surface. 1. A through-hole electrode substrate comprising:a substrate including a through-hole extending from a first aperture of a first surface to a second aperture of a second surface, an area of the second aperture being larger than an area of the first aperture, the through-hole having a minimum aperture part between the first aperture and the second aperture, wherein an area of the minimum aperture part in a planar view is smallest among a plurality of areas of the through-hole in a planar view;an inner member arranged within the through-hole; anda gas discharge member contacting the inner member exposed to one of the first surface and the second surface,wherein a shape of a first side wall of the through-hole between the first aperture and the second aperture is a consecutive curve shape.2. The through-hole electrode substrate according to claim 1 , whereinthe gas discharge member has a via, andthe via overlaps with the through-hole in a planar view.3. The through-hole electrode substrate according to claim 2 , wherein the via has a tapered shape.4. The through-hole electrode substrate according to claim 3 , wherein an angle between a second side wall of the via and a top surface of the inner member in a cross sectional view is 45 degrees or more and 89 degrees or less.5. The through-hole electrode substrate according to claim ...

Package on package structure and method for forming the same

Some embodiments relate to a semiconductor device package, which includes a substrate with a contact pad. A non-solder ball is coupled to the contact pad at a contact pad interface surface. A layer of solder is disposed over an outer surface of the non-solder ball, and has an inner surface and an outer surface which are generally concentric with the outer surface of the non-solder ball. An intermediate layer separates the non-solder ball and the layer of solder. The intermediate layer is distinct in composition from both the non-solder ball and the layer of solder. Sidewalls of the layer of solder are curved or sphere-like and terminate at a planar surface, which is disposed at a maximum height of the layer of solder as measured from the contact pad interface surface.

SEMICONDUCTOR CHIP WITH REDUCED PITCH CONDUCTIVE PILLARS

Various semiconductor chips and packages are disclosed. In one aspect, an apparatus is provided that includes a semiconductor chip that has a side, and plural conductive pillars on the side. Each of the conductive pillars includes a pillar portion that has an exposed shoulder facing away from the semiconductor chip. The shoulder provides a wetting surface to attract melted solder. The pillar portion has a first lateral dimension at the shoulder. A solder cap is positioned on the pillar portion. The solder cap has a second lateral dimension smaller than the first lateral dimension. 1. An apparatus , comprising: a semiconductor chip having a side; plural conductive pillars on the side , each of the conductive pillars including a pillar portion having an exposed shoulder facing away from the semiconductor chip , the shoulder providing a wetting surface to attract melted solder , the pillar portion having a first lateral dimension at the shoulder; and a solder cap positioned on the pillar portion , the solder cap having a second lateral dimension smaller than the first lateral dimension.2. The apparatus of claim 1 , wherein the pillar portion includes a pillar base portion and a pillar barrier layer positioned on the pillar base portion claim 1 , the solder cap being positioned on the pillar barrier layer.3. The apparatus of claim 2 , comprising an underbump metallization (UBM) seed layer positioned beneath the pillar base portion.4. The apparatus of claim 2 , wherein the pillar base portion has the exposed shoulder.5. The apparatus of claim 1 , wherein the pillar portion comprises a pillar base portion and pillar pedestal portion projecting away from the pillar base portion claim 1 , the pillar base portion having the exposed shoulder.6. The apparatus of claim 5 , wherein the pillar portion and the pillar pedestal comprise the same material.7. The apparatus of claim 1 , comprising a circuit board claim 1 , the semiconductor being mounted on the circuit board.8. An ...

CONDUCTIVE PILLAR SHAPED FOR SOLDER CONFINEMENT

A pillar-type connection includes a first conductive layer that includes a hollow core. A second conductive layer is connected to the first conductive layer defining a conductive pillar that includes a top surface defining a recess aligned with the hollow core. A conductive via terminates at a top surface of the first conductive layer. 1. A pillar-type connection comprising:a first conductive layer that includes a hollow core;a second conductive layer coupled to the first conductive layer defining a conductive pillar that includes a top surface defining a recess aligned with the hollow core; anda conductive via that terminates at a top surface of the first conductive layer.2. The pillar-type connection of claim 1 , further comprising:a plating mask that includes an opening aligned with the conductive via; anda sacrificial plug disposed within the opening.3. The pillar-type connection of claim 2 , wherein the top surface of the conductive pillar is adjusted using factors comprising at least one of dimensions of the sacrificial plug and height of the hollow core before removing the sacrificial plug.4. The pillar-type connection of claim 3 , further comprising:vertical surfaces aligned parallel to sidewalls of the opening in the plating mask and inclined surfaces connecting a horizontal surface and a vertical surface to define a cavity, wherein the sacrificial plug has a top surface, and the first conductive layer is formed inside the opening by depositing the first conductive layer such that the top surface of the first conductive layer is recessed relative to the top surface of the sacrificial plug.5. The pillar-type connection of claim 2 , wherein the sacrificial plug is formed as part of a different plating mask.6. The pillar-type connection of claim 3 , further comprising:a feature on a package, the feature attached to the conductive pillar using a solder body, wherein the recess is dimensioned to receive the feature so that the feature is self-aligned with the ...

SUBSTRATE COMPRISING IMPROVED VIA PAD PLACEMENT IN BUMP AREA

Some novel features pertain to an integrated device that includes a substrate, a first via, and a first bump pad. The first via traverses the substrate. The first via has a first via dimension. The first bump pad is on a surface of the substrate. The first bump pad is coupled to the first via. The first bump pad has a first pad dimension that is equal or less then the first via dimension. In some implementations, the integrated device includes a second via and a second bump pad. The second via traverses the substrate. The second via has a second via dimension. The second bump pad is on the surface of the substrate. The second bump pad is coupled to the second via. The second bump pad has a second pad dimension that is equal or less then the second via dimension. 1. An integrated device comprising:a substrate;a first via traversing the substrate, wherein the first via has a first via dimension; anda first bump pad on a surface of the substrate, the first bump pad coupled to the first via, wherein the first bump pad has a first pad dimension that is equal or less then the first via dimension.2. The integrated device of claim 1 , further comprising:a second via traversing the substrate, wherein the second via has a second via dimension; anda second bump pad on the surface of the substrate, the second bump pad coupled to the second via, wherein the second bump pad has a second pad dimension that is equal or less then the second via dimension.3. The integrated device of claim 2 , wherein a pitch between the first via and the second via is about 80 microns (μm) or less.4. The integrated device of claim 2 , wherein a pitch between the first via and the second via is about 125 microns (μm) or less.5. The integrated device of claim 1 , wherein the first bump pad is configured to couple to an interconnect of a die.6. The integrated device of claim 1 , wherein the first bump pad is a peripheral bump pad that is located near an edge of a die area of the substrate.7. The ...

HIGH DENSITY BALL GRID ARRAY (BGA) PACKAGE CAPACITOR DESIGN

A circuit package is provided that includes a substrate having a first side and a second side, an integrated circuit component coupled to the second side of the substrate, and a ball grid array formed on the first side of the substrate, the ball grid array including multiple contact balls arranged in a pattern. Each of a first subset of the contact balls is electrically coupled to a first voltage input of an integrated circuit component, and each of a second subset of the contact balls is electrically coupled to a second voltage input of the integrated circuit component. The package also includes a capacitor mounted to the first side and having a first terminal coupled to a first contact ball in the first subset of the contact balls and a second terminal coupled to a second contact ball in the second subset of the contact balls. 1. An integrated circuit package , comprising:a substrate having a first side and a second side opposite the first side;an integrated circuit component coupled to the second side of the substrate;a ball grid array formed on the first side of the substrate, the ball grid array comprising multiple contact balls arranged in a pattern, wherein each of a first subset of the contact balls is electrically coupled to a first voltage input of an integrated circuit component, and each of a second subset of the contact balls is electrically coupled to a second voltage input of the integrated circuit component; anda capacitor mounted to the first side and having a first terminal coupled to a first contact ball in the first subset of the contact balls and a second terminal coupled to a second contact ball in the second subset of the contact balls.2. The integrated circuit package of claim 1 , wherein the first voltage input is a drain voltage input of a complementary claim 1 , metal-oxide-semiconductor circuit claim 1 , and the second voltage input is a sink voltage input of the complementary claim 1 , metal-oxide-semiconductor circuit.3. The integrated ...

High density package interconnects

Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed.

DISPLAY DEVICE AND ARRAY SUBSTRATE FOR DISPLAY DEVICE

An array substrate for a display device can include a substrate, a pad positioned on the substrate, an insulating layer positioned on the pad and including a plurality of open portions exposing the pad, a first metal layer positioned on the insulating layer and disposed to be in contact with the pad, a second metal layer positioned on the first metal layer, and a bump electrode positioned on the second metal layer and including a plurality of dimples. 1. An array substrate for a display device , the array substrate comprising:a substrate;a pad positioned on the substrate;an insulating layer positioned on the pad and including a plurality of open portions exposing the pad;a first metal layer positioned on the insulating layer and disposed to be in contact with the pad;a second metal layer positioned on the first metal layer; anda bump electrode positioned on the second metal layer and including a plurality of dimples.2. The array substrate of claim 1 , wherein at least one of the plurality of open portions has a width equal to or greater than 5 μm and a length equal to or greater than 10 μm.3. The array substrate of claim 2 , wherein a pitch between the plurality of open portions is equal to or greater than 4 μm.4. The array substrate of claim 1 , wherein a bonding area in which the insulating layer and the bump electrode are in contact is equal to or greater than 1500 μm claim 1 , and an area of the plurality of open portions is equal to or greater than 15% of the bonding area.5. The array substrate of claim 1 , wherein the plurality of open portions are formed as a plurality of line-shaped open portions or a plurality of dot-shaped open portions.6. A display device claim 1 , comprising:a substrate including a display area for displaying an image and a non-display area; anda chip on glass (COG) unit positioned in the non-display area and including a plurality of bumps,wherein each of the plurality of bumps includes:a pad positioned on the substrate;an insulating ...

Bump-on-Trace Interconnect

Disclosed herein is a bump-on-trace interconnect with a wetted trace sidewall and a method for fabricating the same. A first substrate having conductive bump with solder applied is mounted to a second substrate with a trace disposed thereon by reflowing the solder on the bump so that the solder wets at least one sidewall of the trace, with the solder optionally wetting between at least half and all of the height of the trace sidewall. A plurality of traces and bumps may also be disposed on the first substrate and second substrate with a bump pitch of less than about 100 μm, and volume of solder for application to the bump calculated based on at least one of a joint gap distance, desired solder joint width, predetermined solder joint separation, bump geometry, trace geometry, minimum trace sidewall wetting region height and trace separation distance. 1. A method comprising:providing a first substrate having a bump disposed thereon, and the bump having a volume of conductive material disposed thereon;providing a second substrate having a conductive trace, the conductive trace having a sidewall; andmounting the first substrate on the second substrate, the mounting resulting in an electrical connection from the bump to the conductive trace, wherein the bump is separated from the conductive trace by a distance less than a height of the conductive trace, and wherein the conductive material at least partially covers a sidewall of the conductive trace.2. The method of wherein:providing a first substrate comprises forming a plurality of bumps on the first substrate, each of the plurality of bumps having a volume of conductive material disposed thereon;providing a second substrate comprises forming a plurality of conductive traces on the second substrate; andmounting the first substrate to the second substrate comprises electrically connecting the plurality of bumps with respective ones of the plurality of conductive traces.3. The method of claim 2 , wherein the conductive ...

HIGH DENSITY PACKAGE INTERCONNECTS

Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed. 126-. (canceled)27. A method for forming an interconnect , comprising:providing a first metal bump electrically coupled to an I/O signal region on a die, the first metal bump including a solder resistant coating that covers a first portion of the first metal bump and leaves a second portion of the first metal bump uncovered;providing a substrate having a first pad, the first pad having a pad width;forming a solder connection between the first metal bump and the first pad, wherein the solder connection includes an interface between the solder connection and the second portion of the first metal bump, the interface having a width; andwherein the solder connection is controlled so that the width of the interface between the solder connection and the second portion of the first metal bump is greater than the pad width of the first pad.28. The method of claim 27 , further comprising:providing a second metal bump electrically coupled to a power region on the die, the second metal bump including a solder resistant coating that covers a first portion of the second metal bump and leaves a second portion of the second metal bump uncovered;providing a second pad on the substrate, the second pad having a pad width;forming a second solder connection between the second metal bump and the second pad, wherein the second solder connection includes an interface between the second solder connection and the second portion of the second metal bump, the interface having a width; andwherein the second solder connection is ...

PACKAGING ASSEMBLY AND METHOD OF MAKING THE SAME

A packaging assembly includes a semiconductor device. The semiconductor device includes a conductive pad having a first width, and an under-bump metallization (UBM) layer on the conductive pad, wherein the UBM layer has a second width greater than the first width. The semiconductor device further includes a conductive pillar on the UBM layer, and a cap layer over the conductive pillar, wherein the cap layer exposes sidewalls of the UBM layer. The packaging assembly further includes a substrate. The substrate includes a conductive region, and a mask layer overlying the substrate and exposing a portion of the conductive region. The packaging assembly further includes a joint solder structure between the conductive pillar and the conductive region. 1. A packaging assembly , comprising: a conductive pad having a first width,', 'an under-bump metallization (UBM) layer on the conductive pad, wherein the UBM layer has a second width greater than the first width,', 'a conductive pillar on the UBM layer, and', 'a cap layer over the conductive pillar, wherein the cap layer exposes sidewalls of the UBM layer;, 'a semiconductor device comprising a conductive region, and', 'a mask layer overlying the substrate and exposing a portion of the conductive region; and, 'a substrate comprisinga joint solder structure between the conductive pillar and the conductive region.2. The packaging assembly of claim 1 , wherein the mask layer has a mask opening exposing a portion of the conductive region claim 1 , and the width of the mask opening is smaller than and the second width.3. The packaging assembly of claim 2 , wherein a ratio between the width of the mask opening and the second width ranges from about 0.7 and about 0.8.4. The packaging assembly of claim 1 , wherein the conductive pillar comprises a copper pillar claim 1 , and the conductive region is a copper trace.5. The packaging assembly of claim 1 , wherein the mask layer is a solder resist layer.6. A packaging assembly claim 1 , ...

IMAGE SENSOR WITH TOLERANCE OPTIMIZING INTERCONNECTS

Embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed. Embodiments of the above may include systems, methods and processes for staggering ADC or column circuit bumps in a column or sub-column hybrid image sensor using vertical interconnects are also disclosed. 1. An imaging sensor comprising:a plurality of substrates comprising a first substrate and at least one second, subsequent supporting substrate;a pixel array;a plurality of interconnects; anda plurality of support circuits;wherein the first substrate of the plurality of substrates comprises the pixel array;wherein the plurality of supporting circuits are disposed on the at least one second, subsequent supporting substrate that is disposed remotely relative to said first substrate;wherein said plurality of supporting circuits are electrically connected to, and in electrical communication with, said pixel array via the plurality of interconnects disposed between said first substrate and said at least one second, subsequent supporting substrate;wherein said second, subsequent supporting substrate is disposed behind said pixel array relative to an object to be imaged;wherein said plurality of interconnects are spaced relative to one another at a distance that is greater than a pixel pitch of said pixel array.2. The imaging sensor of claim 1 , wherein said imaging sensor is backside illuminated.3. The imaging sensor of claim 1 , wherein the plurality of substrates further comprise a plurality of second claim 1 , subsequent supporting ...

MULTI-CHIP PACKAGE WITH HIGH DENSITY INTERCONNECTS

An apparatus is provided which comprises: a plurality of first conductive contacts having a first pitch spacing on a substrate surface, a plurality of second conductive contacts having a second pitch spacing on the substrate surface, and a plurality of conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings are present in a layer of the substrate above the conductive interconnects to couple the second groupings. Other embodiments are also disclosed and claimed. 125-. (canceled)26. An apparatus comprising:a plurality of organic dielectric layers forming a substrate;a plurality of first conductive contacts having a first pitch spacing on a top surface of the substrate;a plurality of second conductive contacts having a second pitch spacing on the top surface of the substrate;a plurality of first conductive interconnects disposed within the substrate to couple the plurality of first conductive contacts on the top surface of the substrate with a plurality of conductive contacts having a third pitch spacing on a bottom surface of the substrate; anda plurality of second conductive interconnects disposed within the substrate to couple a first linearly arranged grouping of the plurality of second conductive contacts associated with a first die site with a first linearly arranged grouping of the plurality of second conductive contacts associated with a second die site and to couple a second linearly arranged grouping of the plurality of second conductive contacts associated with the first ...

Semiconductor package system

A semiconductor package system includes a substrate, a first and a second semiconductor package, a first thermal conductive layer, a first passive device, and a heat radiation structure. The first and second semiconductor package and first passive device may be mounted on a top surface of the substrate. The first semiconductor package may include a first semiconductor chip that includes a plurality of logic circuits. The first thermal conductive layer may be on the first semiconductor package. The heat radiation structure may be on the first thermal conductive layer, the second semiconductor package, and the first passive device. The heat radiation structure may include a first bottom surface physically contacting the first thermal conductive layer, and a second bottom surface at a higher level than that of the first bottom surface. The second bottom surface may be on the second semiconductor package and/or the first passive device.

Bump structures for multi-chip packaging

A multi-chip package includes a substrate having a plurality of first bump structures. A pitch between first bump structures of the plurality of first bump structures is uniform across a surface of the substrate. The multi-chip package includes a first chip bonded to the substrate and a second chip bonded to the substrate. The first chip includes a plurality of second bump structures, and the plurality of second bump structures are bonded to a first set of first bump structures of the plurality of first bump structures. The second chip includes a plurality of third bump structures, and the plurality of third bump structures are bonded to a second set of first bump structures of the plurality of first bump structures. A pitch between second bump structures of the plurality of second bump structures is different from a pitch between third bump structures of the plurality of third bump structures.

Design and placement of de-coupling capacitors for pdn design

Systems and methods for placing capacitors between IC bumps and BGA balls are described. In one embodiment, the method may include placing a ball grid array (BGA) package or integrated circuit (IC) package on a printed circuit board (PCB) of an electronic device, and placing a capacitor between a first BGA ball and a second BGA ball of the BGA package and/or placing a capacitor between a first IC bump and a second IC bump of the IC package to maintain impedance of a power delivery network (PDN) of the BGA package or IC package below a target impedance.

Ncf for pressure mounting, cured product thereof, and semiconductor device including same

There is provided a pre-applied semiconductor sealing film for curing under pressure atmosphere as a non conductive film (NCF) suitable for pressure mounting. This NCF includes (A) a solid epoxy resin, (B) an aromatic amine which is liquid at room temperature and contains at least one of structures represented by formulae 1 and 2 below, (C) a silica filler, and (D) a polymer resin having a mass average molecular weight (Mw) of 6000 to 100000. The epoxy resin of the component (A) has an epoxy equivalent weight of 220 to 340. The component (B) is included in an amount of 6 to 27 parts by mass relative to 100 parts by mass of the component (A). The component (C) is included in an amount of 20 to 65 parts by mass relative to 100 parts by mass in total of the components. A content ratio ((A):(D)) between the component (A) and the component (D) is 99:1 to 65:35. This NCF further has a melt viscosity at 120° C. of 100 Pa·s or less, and has a melt viscosity at 120° C., after heated at 260° C. or more for 5 to 90 seconds, of 200 Pa·s or less.

ANISOTROPIC CONDUCTIVE FILM, METHOD FOR PRODUCING ANISOTROPIC CONDUCTIVE FILM, METHOD FOR PRODUCING CONNECTION BODY, AND CONNECTION METHOD

To reduce substrate warp occurring after connection an anisotropic conductive film is used. An anisotropic conductive film has: a first insulating adhesive layer; a second insulating adhesive layer; and a conductive particle-containing layer sandwiched by the first insulating adhesive layer and the second insulating adhesive layer and having conductive particles contained in an insulating adhesive, wherein air bubbles are contained between the conductive particle-containing layer and the first insulating adhesive layer, and, the conductive particle-containing layer, a portion thereof below the conductive particles and in contact with the second insulating adhesive layer has a lower degree of cure than other portions thereof. 1. A method for producing a connection body , the connection body being obtained by anisotropic conductive connection between a terminal of a first electronic component and a terminal of a second electronic component by using an anisotropic conductive film , the anisotropic conductive film comprising:a first insulating adhesive layer; anda conductive particle-containing layer laminated on the first insulating adhesive layer and having conductive particles each contained independently in an insulating adhesive;wherein air bubbles are contained between the conductive particle-containing layer and the first insulating adhesive layer, andwherein the air bubbles are contained in accordance with the conductive particles, the method comprising curing the anisotropic conductive film in a sandwiched state of sandwiching the anisotropic conductive film between the first electronic component and the second electronic component.2. A connection body obtained by anisotropic conductive connection between a first electronic component and a second electronic component by using an anisotropic conductive film , the anisotropic conductive film comprising:a first insulating adhesive layer; anda conductive particle-containing layer laminated on the first insulating ...

IMAGE SENSOR FOR ENDOSCOPIC USE

An endoscopic device having embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed. Embodiments of the above may include systems, methods and processes for staggering ADC or column circuit bumps in a column or sub-column hybrid image sensor using vertical interconnects are also disclosed. 137-. (canceled)38. An imaging device comprising: a first substrate including a pixel array comprising a plurality of pixels disposed on the first substrate;', 'a first substrate read bus communicating with at least one of the plurality of pixels on the pixel array;', 'a plurality of interconnects;', 'a second substrate including supporting circuitry for the pixel array and a second substrate read bus, the second substrate being in electrical communication with the first substrate by the plurality of interconnects;', 'wherein at least one interconnect of the plurality of interconnects connects the first substrate read bus to the second substrate read bus, thereby providing electrical communication between the at least one pixel and the supporting circuitry., 'an image sensor comprising39. The imaging device of claim 38 , wherein the supporting circuitry includes one or more of an analog to digital converter claim 38 , a power circuit claim 38 , a power harvester claim 38 , an amplifier circuit claim 38 , a dedicated signal processor claim 38 , a filter claim 38 , and a serializer.40. The imaging device of claim 38 , wherein the interconnects include one or more of a wirebond claim 38 , a μbump claim 38 , a ...

Method of manufacturing package system

A method of manufacturing a package system includes forming a first interconnect structure over a first surface of a first substrate, forming at least one first through silicon via (TSV) structure in the first substrate, disposing the first substrate over a carrier with the first surface facing the carrier, depositing a molding compound material over the carrier and around the first substrate, forming a second interconnect structure over a second surface of the first substrate, removing the carrier to expose the first interconnect structure over the first surface of the first substrate, and disposing a first integrated circuit over the first surface of the first substrate. The first integrated circuit is electrically coupled with the at least one first TSV structure through the first interconnect structure and connecting bumps.

Assembly Method, of the Flip-Chip Type, for Connecting Two Electronic Components, Assembly Obtained by the Method

The invention relates to an assembly method for connecting two electronic components together, said components each having an assembly face, wherein the two assembly faces are moved together in what is known as an assembly direction X, and a given force F is applied to one and/or the other of the components, one and/or the other assembly face(s) having: —connection inserts made of rigid material having an elongate longitudinal shape in the assembly direction X; —connection tracks made of material having a hardness less than that of the inserts and having an elongate longitudinal shape transversely to the assembly direction X, wherein, in said method: —the inserts are aligned opposite corresponding tracks such that the inserts and the tracks form in pairs, after assembly, at least one approximately transverse intersection, —the force F is applied so as make the inserts penetrate into the tracks until the assembly is produced.

Anisotropic conductive film, method for producing anisotropic conductive film, method for producing connection body, and connection method

To reduce substrate warp occurring after connection an anisotropic conductive film is used. An anisotropic conductive film has: a first insulating adhesive layer; a second insulating adhesive layer; and a conductive particle-containing layer sandwiched by the first insulating adhesive layer and the second insulating adhesive layer and having conductive particles contained in an insulating adhesive, wherein air bubbles are contained between the conductive particle-containing layer and the first insulating adhesive layer, and, the conductive particle-containing layer, a portion thereof below the conductive particles and in contact with the second insulating adhesive layer has a lower degree of cure than other portions thereof.

Methods related to managing parasitic capacitance and voltage handling of stacked radio frequency devices

Various implementations enable management of parasitic capacitance and voltage handling of stacked integrated electronic devices. A method can include providing a stack in a radio frequency switch arrangement, the stack arranged in relation to a ground plane, the stack including a plurality of switching elements coupled in series with one another, the stack having first and second ends, the first end including a respective terminal of a first one of the plurality of switching elements. The method can also include forming a first solder bump coupled to the respective terminal of the first one of the plurality of switching elements such that at least a portion of the first solder bump overlaps with one or more of the plurality of switching elements, an overlap dimension set in relation to a first threshold value in order to set a respective contribution to a parasitic capacitance of the radio frequency switch arrangement.

TEMPORARY INTERCONNECT FOR USE IN TESTING A SEMICONDUCTOR PACKAGE

Embodiments described herein are directed to a temporary interconnect for use in testing one or more devices (e.g., one or more dies, inductors, capacitors, etc.) formed in semiconductor package. In one scenario, a temporary interconnect acts an electrical bridge that electrically couples a contact pad on a surface of a substrate and the test pad. Coupling the contact pad and the test pad to each other enables the device(s) coupled the contact pad to be tested. Following testing, the temporary interconnect can be removed or severed so that an electrical break is formed in the conductive path between test pad and the contact pad. 1. A semiconductor package , comprising:a die stack comprising one or more dies;a molding compound encapsulating the die stack;a substrate over the molding compound;a test pad on a surface of the substrate;a contact pad on the surface of the substrate and electrically coupled to the die stack; anda conductive path between the test pad and the contact pad, wherein the conductive path comprises an electrical break at a point along the conductive path.2. The semiconductor package of claim 1 , wherein the conductive path is linear.3. The semiconductor package of claim 2 , wherein the conductive path comprises two linear segments and wherein an angle between the two linear segments is greater than zero degrees.4. The semiconductor package of claim 1 , wherein the conductive path comprises a trace.5. The semiconductor package of claim 4 , wherein the trace terminates at the electrical break.6. The semiconductor package of claim 4 , further comprising a wire extending from the trace.7. The semiconductor package of claim 6 , wherein the electrical break occurs at an end of the wire opposite from the trace.8. The semiconductor package of claim 1 , further comprising:a second test pad on the surface of the substrate;a second contact pad on the surface of the substrate and electrically coupled to the die stack; anda second conductive path between the ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

According to one embodiment, the first resin layer is provided on the first face of the upper layer chip. The first interconnect layer is electrically connected to the upper layer chip. The second resin layer extends into a region outside chip. The region is outer side of a side face of the upper layer chip. The second interconnect layer is provided in the second resin layer. The second interconnect layer is connected to the first interconnect layer and extending into the region outside chip. The lower layer chip is mounted on the surface side of the first resin layer, and is connected to the first interconnect layer. The first sealing resin covers the upper layer chip. 1. A semiconductor device , comprising:an upper layer chip having a first face and a second face opposite to the first face;a first resin layer provided on the first face of the upper layer chip;a first interconnect layer provided in the first resin layer, the first interconnect layer electrically connected to the upper layer chip;a second resin layer provided on a surface side of the first resin layer, the second resin layer extending into a region outside chip, the region being outer side of a side face of the upper layer chip,a second interconnect layer provided in the second resin layer, the second interconnect layer connected to the first interconnect layer and extending into the region outside chip;a lower layer chip mounted on the surface side of the first resin layer, and connected to the first interconnect layer; anda first sealing resin covering the upper layer chip.2. The device according to claim 1 , wherein the lower layer chip is disposed in an opening formed in the second resin layer.3. The device according to claim 1 , wherein the second resin layer covers the lower layer chip.4. The device according to claim 1 , further comprising external terminals provided on a surface side of the second resin layer claim 1 , and connected to the second interconnect layer.5. The device according to ...

Semiconductor device

A semiconductor device includes a semiconductor chip provided with a plurality of bumps arranged in a peripheral alignment, a substrate provided with a plurality of electrodes, and an insulating resin adhesive film. The semiconductor chip is affixed to the substrate via the insulating resin adhesive film such that the electrodes are in positions corresponding to the positions of the bumps. The insulating resin adhesive film has a minimum melt viscosity of 8×10 3 to 1×10 5 Pa·s, covers 70 to 90% the area of the region enclosed with the plurality of bumps, and heat cured. The bumps and the electrodes corresponding thereto are arranged so that they are opposed to each other and establish metallic contact therebetween. A periphery of the insulating resin adhesive film is defined between the plurality of bumps and the outer edge of the semiconductor chip, exclusive.

Electronic control device

A control unit that controls a motor includes a semiconductor device, the semiconductor device includes a semiconductor package including a plurality of first electrodes, a wiring board including a plurality of second electrodes arranged so as to correspond to each of the plurality of first electrodes, and solder joints connecting the plurality of first electrodes and the plurality of second electrodes, and a tip end of a second electrode arranged at an outermost corner of the wiring board is located outside an outer peripheral end of the semiconductor package.

METHODS OF CONNECTING A FIRST ELECTRONIC PACKAGE TO A SECOND ELECTRONIC PACKAGE

A method of fabricating an electronic package. The method includes filling a mold with an electric conductor to form a number of electrical interconnects within the mold. The mold includes openings that are filled with several electric conductors to form a number of electrical interconnects. The method of fabricating an electronic package further includes attaching the mold to a substrate such that the electrical interconnects engage electrical contacts on the substrate. The method of fabricating an electronic package may further include forming conductive pads on the electrical insulator that engage the electrical interconnects and attaching a die to the substrate such that the die is electrically connected to at least some of the electrical interconnects. 1. A method , comprising:filling a mold with an electric conductor to form a number of electrical interconnects within the mold;attaching the mold to a substrate such that the electrical interconnects engage electrical contacts on the substrate;removing the mold from the electrical interconnects; andcovering the electrical interconnects with an electrical insulator.2. The method of claim 1 , wherein filling a mold with the electrical conductor to form a number of electrical interconnects within the mold includes filling the mold with copper.3. The method of claim 1 , wherein attaching the mold to the substrate such that electrical interconnects engage electrical contacts on the substrate includes attaching the mold to the substrate with a solder paste.4. The method of claim 3 , wherein attaching the mold to the substrate with a solder paste includes attaching the solder paste to conductive pads on the substrate.5. The method of claim 1 , wherein covering the electrical interconnects with an electrical insulator includes leaving a portion of the electrical interconnects exposed from the electrical insulator.6. The method of claim 1 , wherein covering the electrical interconnects with an electrical insulator ...

Semiconductor packages and methods of fabricating the same

A semiconductor package includes a wiring board, a semiconductor chip mounted on the wiring board, and a mounting connection terminal electrically connecting a bonding pad of the semiconductor chip to a first connection pad of the wiring board. The mounting connection terminal includes a core portion and a connecting shell solder portion substantially surrounding the core portion. The core portion of the mounting connection terminal is not in contact with the bonding pad of the semiconductor chip.

Trace Design for Bump-on-Trace (BOT) Assembly

A bump-on-trace (BOT) interconnection in a package and methods of making the BOT interconnection are provided. An embodiment BOT interconnection comprises a landing trace including a distal end, a conductive pillar extending at least to the distal end of the landing trace; and a solder feature electrically coupling the landing trace and the conductive pillar. In an embodiment, the conductive pillar overhangs the end surface of the landing trace. In another embodiment, the landing trace includes one or more recesses for trapping the solder feature after reflow. Therefore, a wetting area available to the solder feature is increased while permitting the bump pitch of the package to remain small. 1. A structure comprising:a substrate; anda landing trace on the substrate, the landing trace having a first side and a second side opposite to the first side, the landing trace having a plurality of indents extending into the first side in a plan view, the second side being free of indents in the plan view.2. The structure of claim 1 , further comprising a solder feature over the landing trace claim 1 , the solder feature extending into the plurality of indents.3. The structure of claim 2 , wherein solder feature is in physical contact with the plurality of indents.4. The structure of claim 2 , further comprising a conductive pillar over the solder feature claim 2 , the conductive pillar overlapping with the plurality of indents in the plan view.5. The structure of claim 4 , wherein a width of the solder feature is greater than a width of the conductive pillar.6. The structure of claim 4 , wherein a width of the landing trace is less than a width of the conductive pillar.7. The structure of claim 1 , wherein the plurality of indents have a comb pattern in the plan view.8. A structure comprising:a substrate; anda landing trace on the substrate, the landing trace having a first sidewall and a second sidewall opposite to the first sidewall, the first sidewall having a plurality ...

SEMICONDUCTOR PACKAGE STRUCTURE

A semiconductor package structure is disclosed. The semiconductor package structure comprises a plurality of layered structures, a plurality of wires, and a first ring structure. The wires are connected to each of the layered structures. The first ring structure is coupled to at least one of the layered structures and positioned between the wires. 1. A semiconductor package structure , comprising:a plurality of layered structures;a plurality of wires configured for connecting each of the layered structures; anda first ring structure coupled to at least one of the layered structures and positioned between the wires.2. The semiconductor package structure of claim 1 , wherein the first ring structure comprises a first wire and one of the layered structures.3. The semiconductor package structure of claim 2 , wherein a first end of the first wire and a second end of the first wire are respectively coupled to one of the layered structures.4. The semiconductor package structure of claim 3 , wherein one of the layered structures is a ground layer.5. The semiconductor package structure of claim 2 , wherein a first end of the first wire is coupled to one of the layered structures and a second end of the first wire is coupled to another one of the layered structures.6. The semiconductor package structure of claim 5 , wherein one of the layered structures is a ground layer claim 5 , and another one of the layered structures is a chip.7. The semiconductor package structure of claim 1 , further comprising:a second ring structure coupled to at least one of the layered structures and positioned between the wires.8. The semiconductor package structure of claim 7 , wherein the second ring structure is parallel to the first ring structure.9. The semiconductor package structure of claim 7 , wherein the second ring structure is positioned below the first ring structure claim 7 , and the first ring structure and the second ring structure form a third ring structure through at least one ...

WARPAGE-COMPENSATED BONDED STRUCTURE INCLUDING A SUPPORT CHIP AND A THREE-DIMENSIONAL MEMORY CHIP

A first semiconductor die and a second semiconductor die can be bonded in a manner that enhances alignment of bonding pads. Non-uniform deformation of a first wafer including first semiconductor dies can be compensated for by forming a patterned stress-generating film on a backside of the first wafer. Metallic bump portions can be formed on concave surfaces of metallic bonding pads by a selective metal deposition process to reduce gaps between pairs of bonded metallic bonding pads. Pad-to-pad pitch can be adjusted on a semiconductor die to match the pad-to-pad pitch of another semiconductor die employing a tilt-shift operation in a lithographic exposure tool. A chuck configured to provide non-uniform displacement across a wafer can be employed to hold a wafer in a contoured shape for bonding with another wafer in a matching contoured position. Independently height-controlled pins can be employed to hold a wafer in a non-planar configuration. 1. A method of forming a semiconductor structure , comprising:forming a plurality of first semiconductor dies on a first wafer, wherein the first wafer has a non-planar backside surface due to stress generated by the plurality of first semiconductor dies;disposing the first wafer on a first chuck, wherein the first chuck includes first pins configured to provide a local vertical displacement of the non-planar backside surface of the first wafer from a planar top surface of the first chuck;providing non-uniform vertical displacement to the first pins to provide structural support to the first wafer;disposing a second wafer including a plurality of second semiconductor dies over the first wafer; andbonding the plurality of second semiconductor dies to the plurality of first semiconductor dies while the first wafer is disposed over the first chuck.2. The method of claim 1 , further comprising measuring vertical deviation of the non-planar backside surface from a planar horizontal surface prior to providing structural support to the ...

WARPAGE-COMPENSATED BONDED STRUCTURE INCLUDING A SUPPORT CHIP AND A THREE-DIMENSIONAL MEMORY CHIP

A first semiconductor die and a second semiconductor die can be bonded in a manner that enhances alignment of bonding pads. Non-uniform deformation of a first wafer including first semiconductor dies can be compensated for by forming a patterned stress-generating film on a backside of the first wafer. Metallic bump portions can be formed on concave surfaces of metallic bonding pads by a selective metal deposition process to reduce gaps between pairs of bonded metallic bonding pads. Pad-to-pad pitch can be adjusted on a semiconductor die to match the pad-to-pad pitch of another semiconductor die employing a tilt-shift operation in a lithographic exposure tool. A chuck configured to provide non-uniform displacement across a wafer can be employed to hold a wafer in a contoured shape for bonding with another wafer in a matching contoured position. Independently height-controlled pins can be employed to hold a wafer in a non-planar configuration. 1. A method of forming a semiconductor structure , comprising:providing a first semiconductor die including first semiconductor devices, first metal interconnect structures, and first metal bonding pads having first concave top surfaces;forming metallic bump portions directly on the first concave top surfaces of the first metal bonding pads by selectively depositing a metallic material on the first concave top surfaces of the first metal bonding pads;providing a second semiconductor die including second semiconductor devices, second metal interconnect structures, and second metal bonding pads; andattaching the second semiconductor die to the first semiconductor die by bonding the second metal bonding pads to the metallic bump portions via metal-to-metal bonding.2. The method of claim 1 , wherein:the first metal bonding pads are formed by forming pad-level recesses within a first pad level dielectric layer that overlies the first metal interconnect structures, depositing at least one metallic material in the pad-level recesses ...

Offset interposers for large-bottom packages and large-die package-on-package structures

An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.

Drive chip and display apparatus

This drive chip has a configuration that is provided with: a base main body; two terminal groups that are respectively disposed along the base main body sides in the longitudinal direction of the base main body, said sides facing each other; a narrow-pitch section in one terminal group wherein terminals are disposed in a zigzag manner in two or more rows, said narrow-pitch section having a narrow terminal pitch in the longitudinal direction; a rough pitch section in the one terminal group, said rough pitch section having a terminal pitch in the longitudinal direction wider than that of the narrow pitch section; and a dummy bump that is disposed between the two terminal groups, said dummy bump being disposed parallel to the rough pitch section.

Selective wetting process to increase solder joint standoff

One embodiment of the invention sets forth a packaging system, which includes a first package substrate, an electrically conductive pad formed on a surface of the first package substrate, and a supporting structure formed on the electrically conductive pad. The supporting structure has a top surface and a side surface, and only the top surface of the supporting structure is coupled to a solder joint to establish an electrical connection between the first package substrate and an adjacent, parallel second package substrate. By having the solder joint connected only to the top surface of the supporting structure, the resulting solder joint structure is narrower and taller. Therefore, even if solder joints are placed at a finer pitch, a standoff height between the first and second package substrates can be maintained at a desired height to accommodate a fixed-size IC chip that is disposed between the first and second package substrates.

SEMICONDUCTOR PACKAGE, PRINTED CIRCUIT BOARD SUBSTRATE AND SEMICONDUCTOR DEVICE

A semiconductor package includes: a semiconductor integrated circuit; an interlayer film disposed on the semiconductor integrated circuit; a rewiring layer disposed on the interlayer film; post electrodes disposed on the rewiring layer; a protective layer which is disposed on the interlayer film and covers the rewiring layer and the post electrodes; and a plurality of balls which is respectively disposed on the post electrodes and is connected to the rewiring layer, wherein balls existing on a wiring path of internal wirings connected to inner lands of a plurality of lands, which is arranged on a printed circuit board substrate to face the plurality of balls and is connectable to the plurality of balls, are non-connected to the rewiring layer.

Use of Pre-Channeled Materials for Anisotropic Conductors

A semiconductor device assembly has a first substrate, a second substrate, and an anisotropic conductive film. The first substrate includes a first plurality of connectors. The second substrate includes a second plurality of connectors. The anisotropic conductive film is positioned between the first plurality of connectors and the second plurality of connectors. The anisotropic conductive film has an electrically insulative material and a plurality of interconnects laterally separated by the electrically insulative material. The plurality of interconnects forms electrically conductive channels extending from the first plurality of connectors to the second plurality of connectors. A method includes connecting the plurality of interconnects to the first plurality of connectors and the second plurality of connectors, such that the electrically conductive channels are operable to conduct electricity from the first substrate to the second substrate. The method may include passing electrical current through the plurality of interconnects. 1. A semiconductor device assembly comprising:a first substrate having a first plurality of connectors;a second substrate having a second plurality of connectors; andan anisotropic conductive film positioned between the first plurality of connectors and the second plurality of connectors, the anisotropic conductive film having an electrically insulative material and a plurality of interconnects laterally separated by the electrically insulative material, the plurality of interconnects forming electrically conductive channels extending from the first plurality of connectors to the second plurality of connectors.2. The semiconductor device assembly of claim 1 , wherein the anisotropic conductive film is a microporous film and the plurality of interconnects are pores of the microporous film.3. The semiconductor device assembly of claim 2 , wherein the electrically insulative material is acrylic-based or epoxy-based.4. The semiconductor ...

HIGH DENSITY PACKAGE INTERCONNECTS

Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed. 17-. (canceled)8. An apparatus comprising:a semiconductor die structure including I/O signal lines and power lines, the power lines including at least one of core power lines and I/O power lines;the die structure including a plurality of metal bumps, including a first group of metal bumps coupled to the I/O signal lines, and a second group of metal bumps coupled to the power lines; andwherein at least some of the metal bumps of the first group have a different pitch than at least some of the metal bumps of the second group.9. The apparatus of claim 8 , wherein at least some of metal bumps of the first group have at least one difference selected from the group consisting of a different shape and a different width claim 8 , than at least some of the metal bumps of the second group.10. The apparatus of claim 8 , wherein at least some of the metal bumps of the first group are rectangular in shape.11. The apparatus of claim 9 , wherein at least some of the metal bumps of the second group are circular in shape.12. The apparatus of claim 8 , wherein the first group of metal bumps includes a first sub-group of metal bumps and a second sub-group of metal bumps claim 8 , wherein the first sub-group has a smaller pitch than the second sub-group.13. The apparatus of claim 8 , further comprising a solder coupled to each of the first group of metal bumps claim 8 , wherein the solder defines an interface on the metal bump where the solder and metal bump are in contact claim 8 , and wherein the interface has a width that is ...

Method for bonding bare chip dies

A method is provided for assembly of a micro-electronic component comprising the steps of: providing a conductive die bonding material comprising of a conductive thermosettable resin material or flux based solder and a dynamic release layer adjacent to the conductive thermoplastic material die bonding material layer; and impinging a laser beam on the dynamic release layer adjacent to the die bonding material layer; in such a way that the dynamic release layer is activated to direct conductive die bonding material matter towards the pad structure to be treated to cover a selected part of the pad structure with a transferred conductive die bonding material; and wherein the laser beam is restricted in timing and energy, in such a way that the die bonding material matter remains thermosetting. Accordingly adhesive matter can be transferred while preventing that the adhesive is rendered ineffective by thermal overexposure in the transferring process.

Method and ic structure for increasing pitch between gates

Aspects of the present disclosure include integrated circuit (IC) structure and methods for increasing a pitch between gates. Methods according to the present disclosure can include: providing an IC structure including: a first gate structure and a second gate structure each positioned on a substrate, a dummy gate positioned between the first and second gate structures, and forming a mask over the first and second gate structures; and selectively etching the dummy gate from the IC structure to expose a portion of the substrate underneath the dummy gate of the IC structure, without affecting the first and second gate structures.

Package on package structure and method for forming the same

Some embodiments relate to a semiconductor device package, which includes a substrate with a contact pad. A non-solder ball is coupled to the contact pad at a contact pad interface surface. A layer of solder is disposed over an outer surface of the non-solder ball, and has an inner surface and an outer surface which are generally concentric with the outer surface of the non-solder ball. An intermediate layer separates the non-solder ball and the layer of solder. The intermediate layer is distinct in composition from both the non-solder ball and the layer of solder. Sidewalls of the layer of solder are curved or sphere-like and terminate at a planar surface, which is disposed at a maximum height of the layer of solder as measured from the contact pad interface surface.

BUMP-ON-TRACE INTERCONNECT

Disclosed herein is a bump-on-trace interconnect with a wetted trace sidewall and a method for fabricating the same. A first substrate having conductive bump with solder applied is mounted to a second substrate with a trace disposed thereon by reflowing the solder on the bump so that the solder wets at least one sidewall of the trace, with the solder optionally wetting between at least half and all of the height of the trace sidewall. A plurality of traces and bumps may also be disposed on the first substrate and second substrate with a bump pitch of less than about 100 μm, and volume of solder for application to the bump calculated based on at least one of a joint gap distance, desired solder joint width, predetermined solder joint separation, bump geometry, trace geometry, minimum trace sidewall wetting region height and trace separation distance. 1. A semiconductor package comprising: a first substrate;', 'a conductive land proximate a first side of the first substrate; and', 'a conductive pillar, a first surface of the conductive pillar coupled to the conductive land;, 'a first semiconductor device comprising a second substrate; and', 'a conductive trace on a surface of the second substrate facing the conductive pillar, a sidewall of the conductive trace having a first height; and, 'a second semiconductor device comprisinga conductive joint between the conductive pillar and the conductive trace, the conductive joint covering the sidewall of the conductive trace by at least half the first height, the conductive pillar being spaced from the conductive trace by a first distance, the first distance being smaller than the first height.2. The semiconductor package of claim 1 , wherein a second surface of the conductive pillar opposing the first surface of the conductive pillar has a first width claim 1 , wherein a third surface of the conductive trace facing the conductive pillar has a second width claim 1 , the first width being larger than the second width.3. The ...

3D STACK OF ELECTRONIC CHIPS

A 3D stack includes a first chip having first interconnection pads of rectangular section, the first interconnection pads having a first pitch in a first direction and a second pitch in a second direction perpendicular to the first direction; and a second chip having second interconnection pads, the second interconnection pads having a third pitch in the first direction and a fourth pitch in the second direction, at least one part of the second interconnection pads being in contact with the first interconnection pads to electrically couple the first and second chips. The first interconnection pads have a first dimension in the first direction equal to m times the third pitch and a second dimension in the second direction equal to n times the fourth pitch. The first interconnection pads are separated two by two in the first direction by a first distance equal to q times the third pitch. 2. The 3D stack according to claim 1 , wherein the first dimension of the first interconnection pads is further equal to the first pitch divided by 2 and wherein the second dimension of the first interconnection pads is further equal to the second pitch divided by 2.3. The 3D stack according to claim 2 , wherein the first pitch is equal to the second pitch.4. The 3D stack according to wherein the second interconnection pads have a rectangular claim 1 , round or octagonal section.5. The 3D stack according to claim 1 , wherein the second interconnection pads have a first dimension in the first direction equal to the third pitch divided by 2 and a second dimension in the second direction equal to the fourth pitch divided by 2.6. The 3D stack according to claim 5 , wherein the third pitch is equal to the fourth pitch.7. The 3D stack according to claim 1 , wherein:the first dimension of the first interconnection pads is equal to the third pitch;the second dimension of the first interconnection pads is equal to the fourth pitch;the first distance is equal to the third pitch; andthe second ...

SEMICONDUCTOR DEVICE AND FABRICATING METHOD OF THE SAME

A semiconductor device includes a first substrate having a first face and a second face, a first semiconductor chip on the first face, a first wire which electrically connects the first semiconductor chip and the first substrate, a first resin which seals the first semiconductor chip and the first wire, a first metal bump on the second face, a second substrate below the first substrate, the second substrate having a third face and a fourth face, a second semiconductor chip on the third face and electrically connected to the first metal bump, a second wire which electrically connects the second semiconductor chip and the second substrate, a second resin between the second face and the third face, the second resin sealing the first metal bump, the second semiconductor chip and the second wire, and a second metal bump on the fourth face. 1. A semiconductor device , comprising:a first substrate having a first face and a second face opposite the first face;a first semiconductor chip on the first face of the first substrate;a first wire which electrically connects the first semiconductor chip and the first substrate;a first resin which seals the first semiconductor chip and the first wire;a first metal bump on the second face;a second substrate below the first substrate, the second substrate having a third face and a fourth face opposite to the third face;a second semiconductor chip on the third face and electrically connected to the first metal bump;a second wire which electrically connects the second semiconductor chip and the second substrate;a second resin between the second face of the first substrate and the third face of the second substrate, the second resin sealing the first metal bump, the second semiconductor chip and the second wire; anda second metal bump on the fourth face.2. The semiconductor device according to claim 1 , wherein the second resin is a continuous material from the first metal bump along the second semiconductor chip to the second wire at a ...

System and method for sub-column parallel digitizers for hybrid stacked image sensor using vertical interconnects

Embodiments of a hybrid imaging sensor and methods for pixel sub-column data read from the within a pixel array.

Light emitting diode display device

A light emitting diode display device includes a display board comprising a plurality of unit pixels, a drive circuit board including a plurality of drive circuit regions corresponding to the plurality of unit pixels, and a plurality of bumps interposed between the plurality of unit pixels and the plurality of drive circuit regions. The plurality of unit pixels comprises a first unit pixel including a first P electrode. The plurality of drive circuit regions comprises a first drive circuit region corresponding to the first unit pixel and a first pad connected to a first drive transistor, the plurality of bumps includes a first solder in contact with the first pad, and a first bump on the first solder and including a first filler in contact with the first P electrode, the first solder includes at least one of tin and silver, and the first filler includes copper or nickel.

STACKING MULTIPLE DIES HAVING DISSIMILAR INTERCONNECT STRUCTURE LAYOUT AND PITCH

An apparatus is provided comprising: first die, wherein a first plurality of interconnect structures is formed on the first die; one or more layers, wherein a first surface of the one or more layers is attached to the first plurality of interconnect structures; a second plurality of interconnect structures formed on a second surface of the one or more layers; and a second die, wherein a third plurality of interconnect structures is formed on the second die, wherein a first interconnect structure of the first plurality of interconnect structures is electrically connected to a second interconnect structure of the second plurality of interconnect structures through the one or more layers, and wherein the first die is mounted on the second die such that the second interconnect structure of the second plurality of interconnect structures is attached to a third interconnect structure of the third plurality of interconnect structures. 125-. (canceled)26. An apparatus comprising:a first die, wherein a first plurality of interconnect structures is on the first die;one or more layers, wherein a first surface of the one or more layers is adjacent to the first plurality of interconnect structures;a second plurality of interconnect structures on a second surface of the one or more layers; anda second die, wherein a third plurality of interconnect structures is on the second die,wherein a first interconnect structure of the first plurality of interconnect structures is electrically coupled to a second interconnect structure of the second plurality of interconnect structures through the one or more layers, andwherein the first die is on the second die such that the second interconnect structure of the second plurality of interconnect structures is adjacent to a third interconnect structure of the third plurality of interconnect structures via an attachment component.27. The apparatus of claim 26 , wherein:the first plurality of interconnect structures has a first pitch;the second ...

PATTERNABLE DIE ATTACH MATERIALS AND PROCESSES FOR PATTERNING

A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die. 1. A die assembly , comprising:a die;one or more die pads on a first surface of the die; anda die attach film on the die, wherein the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.2. The die assembly of claim 1 , further comprising one or more die pads attached to a second surface of the die.3. The die assembly of claim 1 , wherein the one or more openings include one or more channels that contain an underfill material.4. The die assembly of claim 1 , wherein the one or more openings include one or more channels that contain an underfill material that is different from the die attach film material.5. The die assembly of claim 1 , wherein the one or more die pads are through silicon via (TSV) backside die pads.6. The die assembly of claim 1 , wherein the die assembly is on a first package substrate and the one or more die pads are connected to an individual die claim 1 , a first die and a second die claim 1 , a second package substrate or an interposer.7. The die assembly of claim 1 , wherein the die assembly is surrounded by mold.8. A system claim 1 , comprising:one or more storage components; and a die in a die mount space;', 'one or more die pads attached to a first surface of the die; and', 'a die attach film on the die, wherein the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die., 'one or more integrated circuit die including a die assembly that includes9. The system claim 8 , further comprising one or more die pads attached to a second surface of the die.10. The system of claim 8 , wherein the one or more openings ...

SEMICONDUCTOR PACKAGE, PRINTED CIRCUIT BOARD SUBSTRATE AND SEMICONDUCTOR DEVICE

A semiconductor package includes: a semiconductor integrated circuit; an interlayer film disposed on the semiconductor integrated circuit; a rewiring layer disposed on the interlayer film; post electrodes disposed on the rewiring layer; a protective layer which is disposed on the interlayer film and covers the rewiring layer and the post electrodes; and a plurality of balls which is respectively disposed on the post electrodes and is connected to the rewiring layer, wherein balls existing on a wiring path of internal wirings connected to inner lands of a plurality of lands, which is arranged on a printed circuit board substrate to face the plurality of balls and is connectable to the plurality of balls, are non-connected to the rewiring layer. 143-. (canceled)44. A semiconductor device , comprising:a semiconductor package including a first substrate having a first surface and a second surface, a first wiring formed on the first surface of the first substrate, and a plurality of electrodes formed on the first wiring and electrically connected with the first wiring; anda second substrate having a first surface facing the first surface of the first substrate, and a second surface, the second substrate including second wirings respectively connected to the plurality of electrodes, the second wirings being formed on the first surface of the second substrate from an inside of a portion facing the semiconductor package to an outside of a periphery of the portion facing the semiconductor package,wherein, when viewed along a direction perpendicular to the first surface of the first substrate, the first wiring and the second wirings are formed between the electrodes adjacent to each other such that a center of the first wiring and centers of the second wirings deviate from each other.45. The semiconductor device of claim 44 , wherein between the adjacent electrodes when viewed along the direction perpendicular to the first surface of the first substrate claim 44 , the first ...