ВЫСОКОЧАСТОТНЫЙ СИЛОВОЙ ДИОД И СПОСОБ ЕГО ИЗГОТОВЛЕНИЯ

Высокочастотный силовой диод содержит полупроводниковую подложку, имеющую первую главную сторону (101) и вторую главную сторону (102), первый слой (103) первого типа проводимости, сформированный на первой главной стороне (101), второй слой (105) второго типа проводимости, сформированный на второй главной стороне (102) подложки, и третий слой (104) второго типа проводимости, сформированный между первым слоем (103) и вторым слоем (105). Первый слой (103) имеет концентрацию легирующей примеси, которая понижается от 10смили более вблизи первой главной стороны (101) подложки до концентрации 1,5⋅10смили менее на границе раздела первого слоя (103) с третьим слоем (104). Второй слой (105) имеет концентрацию легирующей примеси, которая понижается от 10смили более вблизи второй главной стороны (102) подложки до концентрации 1,5⋅10смна границе раздела второго слоя (105) с третьим слоем (104), а третий слой (104) имеет концентрацию легирующей примеси 1,5⋅10смили менее. Концентрация легирующей примеси ...

КРИСТАЛЛ УЛЬТРАБЫСТРОГО ВЫСОКОВОЛЬТНОГО СИЛЬНОТОЧНОГО АРСЕНИД-ГАЛЛИЕВОГО ДИОДА

Изобретение относится к микроэлектронике. Изобретение обеспечивает улучшение динамических свойств, расширение диапазона рабочих напряжений, увеличение плотности токов, повышение термодинамической устойчивости высоковольтных ультрабыстрых арсенид-галлиевых диодов. Сущность изобретения: в конструкции кристалла арсенид-галлиевого диода в эпитаксиальных анодных и катодных областях структуры профиль концентрации легирующей примеси резко выраженный ступенчатый с резким - плавным - резким убыванием и возрастанием разностной концентрации донорной и акцепторной примесей. Кристалл ультрабыстрого мощного высоковольтного арсенид-галлиевого диода содержит высоколегированную монокристаллическую подложку первого типа проводимости с концентрацией легирующей примеси не менее чем 10см; эпитаксиальный слой первого типа проводимости с областями резкого, плавного, резкого уменьшения разностной концентрации донорной и акцепторной примесей от уровня концентрации в подложке 10смдо менее чем 10см; эпитаксиальный ...

Halbleitervorrichtung und Verfahren zu ihrer Herstellung

Es wird eine Technik bereitgestellt, die die Latch-up-Festigkeit eines IGBT oder einer Halbleitervorrichtung, die ähnlich dem IGBT arbeitet, verbessert und eine Ein-Spannung verringert. Eine Halbleitervorrichtung (1A) enthält eine Driftschicht (3) eines ersten Leitfähigkeitstyps, eine Mesa-Region (5), die zwischen benachbarten Gräben (4) auf der Driftschicht (3) angeordnet ist, eine Gate-Elektrode (8), die in jedem Graben (4) durch einen Gate-Isolierfilm (6) vergraben ist, eine Basisregion (9) eines zweiten Leitfähigkeitstyps, die in der Mesa-Region (5) vergraben ist, mehrere Emitterregionen (11) des ersten Leitfähigkeitstyps, die periodisch in einem Oberflächenschichtabschnitt der Basisregion (9) entlang einer längeren Richtung des Grabens (4) vergraben sind, und Kontaktregionen (12) des zweiten Leitfähigkeitstyps, die abwechselnd in der längeren Richtung zusammen mit den Emitterregionen (11) dergestalt vergraben sind, dass jede Emitterregion (11) zwischen den Kontaktregionen (12) angeordnet ...

Halbleiterbauelement mit temporärem Feldstoppbereich und Verfahren zu dessen Herstellung

Halbleiterbauelement mit einem Halbleiterkörper (1) und wenigstens zwei Elektroden (2, 3), zwischen denen sich im Halbleiterkörper (1) mindestens ein pn-Übergang (4) und ein Spannung aufnehmendes Gebiet (5) des einen Leitungstyps, in welchem sich eine Raumladungszone (6) ausbreitet, wenn an die Elektroden (2, 3) eine den pn-Übergang (4) in dessen Sperrrichtung beaufschlagende Spannung angelegt ist, befinden, wobei in dem Spannung aufnehmenden Gebiet (5) ein temporär wirksamer Bereich (9) des einen Leitungstyps vorgesehen ist, der zwischen seinem Leitungsband (L) und seinem Valenzband (V) Zentren (Z) aufweist, die bei einer Überschwemmung des Spannung aufnehmenden Gebiets (5) freie Ladungsträger einfangen können, sich bei einer Ausbreitung der Raumladungszone (6) aber wieder entladen, so dass der Bereich (9) nur bei einem Abschaltvorgang nach der Überschwemmung mit freien Ladungsträgern zeitweise wirksam ist, dadurch gekennzeichnet, dass der temporär wirksame Bereich (9) in einer Tiefe von ...

Halbleiterbauteil und Verfahren zu dessen Herstellung

Eine elektrische Feld-Pufferschicht (13) wird eine aktive Zone (12) umgebend ausgebildet. Die elektrische Feld-Pufferschicht (13) umfasst mehrere Fremdstoffschichten des P-Typs (21 bis 25). Jede der Fremdstoffschichten des P-Typs (21 bis 25) umfasst Implantationsschichten des P-Typs (21a bis 25a) und Diffusionsschichten des P-Typs (21b bis 25b), die so ausgebildet werden, dass sie jeweils die Implantationsschichten des P-Typs (21a bis 25a) umgeben und Fremdstoffe des P-Typs in einer Konzentration enthalten, die geringer ist als diejenige der Implantationsschichten des P-Typs (21a bis 25a). Eine erste Implantationsschicht des P-Typs (21a) wird in Kontakt mit der oder die aktive Zone (12) teilweise überlagernd ausgebildet. Jede der Diffusionsschichten des P-Typs (21b bis 25b) wird mit einer Ausdehnung in einem Ausmaß ausgebildet, in dem die erste Diffusionsschicht des P-Typs (21b) mit der zweiten Diffusionsschicht des P-Typs (22b) in Kontakt steht oder diese überlagert. Abstände (s2 bis s5 ...

Halbleitervorrichtung

Diese Halbleitervorrichtung (100) verfügt über ein auf einem n-Driftgebiet (2) angeordnetes p-Anodengebiet (4) und ein p-Diffusionsgebiet (5), welches so angeordnet ist, dass es mit dem p-Anodengebiet (4) auf dem n-Driftgebiet (2) in Kontakt steht. Ein Widerstandsgebiet (6), das so angeordnet ist, dass es mit dem p-Diffusionsgebiet (5) auf einem n-Gebiet (3) in Kontakt steht, eine Vielzahl von p-Schutzringgebieten (8) und ein entfernt von den p-Schutzringgebieten (8) angeordnetes Stoppergebiet (9) sind vorgesehen. Durch Vorsehen des p-Diffusionsgebiets (5) wird das Abziehen von Löchern, welche sich zur Zeit der Sperrverzögerung im p-Anodengebiet konzentrieren, unterdrückt, so dass die Halbleitervorrichtung mit einer hohen Sperrverzögerungstoleranz bereitgestellt werden kann.

Verfahren zum Herstellen einer Schutzstruktur

Verfahren zur Herstellung einer Schutzstruktur (100, 200), wobei das Verfahren folgende Merkmale aufweist: – Bereitstellen eines Halbleitersubstrats (110) mit einer Dotierung von einem ersten Leitfähigkeitstyp, – Aufbringen einer Halbleiterschicht (120) mit einer Dotierung von einem zweiten Leitfähigkeitstyp an einer Oberfläche des Halbleitersubstrats (110), – Ausbilden einer vergrabenen Schicht (140) mit einer Dotierung von einem zweiten Leitfähigkeitstyp in einem ersten Bereich (150) der Halbleiterschicht (120), wobei die vergrabene Schicht (140) am Übergang (170) von der Halbleiterschicht (120) zum Halbleitersubstrat (110) erzeugt wird, – Ausbilden eines ersten Dotierstoffgebiets (180) mit einer Dotierung von einem ersten Leitfähigkeitstyp in dem ersten Bereich (150) der Halbleiterschicht (120) über der vergrabenen Schicht (140), – Ausbilden eines zweiten Dotierstoffgebiets (190) mit einer Dotierung von einem zweiten Leitfähigkeitstyp in einem zweiten Bereich (160) der Halbleiterschicht ...

III-V-Halbleiterdiode

Stapelförmige III-V-Halbleiterdiode (10), aufweisend eine n-Schicht (12) mit einer Dotierstoffkonzentration von mindestens 10N/cm3 und einer Schichtdicke (D1) von 50-675 µm, eine n-Schicht (14) mit einer Dotierstoffkonzentration von 10-10N/cm, einer Schichtdicke (D2) von 10-300 µm, eine p-Schicht (18) mit einer Dotierstoffkonzentration von 5•10-5•10cm, mit einer Schichtdicke (D3) größer 2 µm, wobei die Schichten in der genannten Reihenfolge aufeinander folgen, jeweils eine GaAs-Verbindung umfassen oder aus einer GaAs Verbindung bestehen und monolithisch ausgebildet sind, die n-Schicht (12) oder die p-Schicht (18) als Substrat ausgebildet ist und eine Unterseite der n-Schicht (14) stoffschlüssig mit einer Oberseite der n-Schicht (12) verbunden ist, die stapelförmige III-V-Halbleiterdiode (10) eine erste Defektschicht (16) mit einer Schichtdicke (D4) größer 0,5 µm umfasst, die Defektschicht (16) innerhalb der n-Schicht angeordnet ist und die Defektschicht (16) eine Defektkonzentration im ...

STABILIZED MAGNETICALLY SENSITIVE AVALANCHE TRANSISTOR

Gruppe-III-Nitrid-basierte ESD-Schutzvorrichtung

Vorrichtung zum Schutz vor elektrostatischen Entladungen, umfassend:eine erste Gruppe-III-Nitrid-p-i-n-Diode; undeine zweite Gruppe-III-Nitrid-p-i-n-Diode, die mit der ersten Gruppe-III-Nitrid-p-i-n-Diode in einer antiparallelen Anordnung verbunden ist, wobei die Anordnung eingerichtet ist,ein Spannungsklemmen bei 5V oder weniger unter Vorspannung in Durchlassrichtung entweder der ersten oder der zweiten Gruppe-III-Nitrid-p-i-n-Diode für transienten Strom sowohl in der Durchlass- als auch in der Sperrrichtung bereitzustellen,wobei die erste Gruppe-III-Nitrid-p-i-n-Diode eine erste intrinsische Gruppe-III-Nitridzone umfasst, die zwischen einer ersten Gruppe-III-Nitridzone vom n-Typ und einer ersten Gruppe-III-Nitridzone vom p-Typ angeordnet ist;die zweite Gruppe-III-Nitrid-p-i-n-Diode eine zweite intrinsische Gruppe-III-Nitridzone umfasst, die zwischen einer zweiten Gruppe-III-Nitridzone vom n-Typ und einer zweiten Gruppe-III-Nitridzone vom p-Typ angeordnet ist;die erste Gruppe-III-Nitridzone ...

Halbleiterbauteil

Halbleiterbauteil, mit: einem Substrat, das eine Hauptfläche aufweist; einem Halbleiterelement, das auf der Hauptfläche montiert ist und das eine Hauptflächenelektrode beinhaltet, die in der gleichen bzw. in die gleiche Richtung orientiert ist wie die Hauptfläche; einem Verbindungs-Pad, das aus Cu gebildet ist, das in einer ersten Richtung, die parallel ist zu der Hauptfläche, von dem Substrat getrennt ist, und das eine Verbindungsfläche beinhaltet, die in der gleichen Richtung orientiert ist wie die Hauptfläche; einer plattierten Schicht, die aus Ni gebildet ist und die die Verbindungsfläche teilweise bedeckt; einem Draht, der aus Al gebildet ist und der ein erstes Ende, das an die Hauptflächenelektrode gebondet ist, und ein zweites Ende aufweist, das an die plattierte Schicht gebondet ist; und einem Verkapselungsharz, das das Halbleiterelement, das Verbindungs-Pad, die plattierte Schicht und den Draht verkapselt.

Corrugated semiconductor devices

A semiconductor device, for example a p-i-n diode, comprises a corrugated semiconductor body having a plurality of complementary grooves and ridges on opposite sides of the body. The junction between the p-type region and the n-type intrinsic region has substantially the same configuration as, and extends substantially parallel to, the surface, while the junction between the n-type region and the intrinsic region similarly extends substantially parallel to the surface. Devices with narrow intrinsic regions can be made accurately by diffusion of the p-type region and the n-type region because the whole of the diode can be made relatively thin, for example, 90 micrometers without sacrificing strength and rigidity. In comparison with an equivalent planar device, the active area and current handling capability is increased. To avoid premature breakdown the diode may be surrounded by a thicker peripheral portion.

DIODE DEVICES AND ACTIVE MATRIX ADDRESSED DISPLAY DEVICES INCORPORATING SUCH

Improved auger suppressed device

METHOD OF MANUFACTURING A SEMICONDUCTOR STRUCTURE FOR MICROWAVE OPERATION INCLUDING A THIN INSULATING OR WEAKLY DOPED LAYER

... 1524709 Semiconductor device manufacture THOMSON CSF 17 Oct 1975 [18 Oct 1974] 42824/75 Heading H1K The face of a layer or wafer of N-type gallium arsenide is implanted with Be ions to produce a P-type layer separated from the residual N-type layer by a lightly doped layer less than 1 Á thick. In one embodiment, one face of a 100 Á wafer with a doping of 3 Î 1018 atoms/cm.3 is bombarded with 50 keV Be ions at a dosage of 1014/cm.2 at ambient temperature to yield a PIN diode structure with an I layer 1/ 10 Á thick. An NIP microwave avalanche diode may be formed by bombarding the outer N + layer of an N + + N + NN + structure with Be ions. The resulting structure may be annealed for 1 hour at 600-700‹ C. after coating with a 2000Š layer of SiO 2 by a low temperature process such as cathode sputtering or pyrolysis of an organic compound of silicon.

SEMICONDUCTOR ARRANGEMENT WITH SEVERAL TRANSITIONS.

GATE TURN-OFF DIODES

Surface pin device

EPITAXIAL EDGE TERMINATION FOR SILICON CARBIDE SCHOTTKY DEVICES AND METHODS OF FABRICATING SILICON CARBIDE DEVICES INCORPORATING SAME

Edge termination for a silicon carbide Schottky rectifier is provided by including a silicon carbide epitaxial region (16) on a voltage blocking layer (14) of the Schottky rectifier and adjacent a Schottky contact (18) of the silicon carbide Schottky rectifier. The silicon carbide epitaxial layer (16) may have a thickness and a doping level so as to provide a charge in the silicon carbide epitaxial region based on the surface doping of the blocking layer (14). The silicon carbide epitaxial region (16) may form a non-ohmic contact with the Schottky contact (18). The silicon carbide epitaxial region (16) may have a width of from about 1.5 to about 5 times the thickness of the blocking layer (14). Schottky rectifiers with such edge termination and methods of fabricating such edge termination and such rectifiers are also provided.

CONTROLLED AVALANCHE VOLTAGE TRANSISTOR AND MAGNETIC SENSOR

p-n-Gleichrichter mit Mittelzone

Elément redresseur

Halbleiterventil

Solid state pinch diode - has three zone structure with channel form and schottky electrode regions

The solid state pinch diode has three impregnated zones. A high impregnated zone (3) is located between an electrode (4) and a substrate (11) that is of a low impregnated zone (5) of the same conductive type as the first zone (3). The third zone is in the form of channels (6.1 - 6.3) of a second type and PN transfer regions are available (7.1 - 7.3). The ends have electrodes (9) of a schottky contact form and these are also located in the channels (11.1 - 11.3). The surfaces (8) provide boundaries for the elements. ADVANTAGE - Main surface structure provides zone boundaries.

Semiconductor device for the prevention of the destruction during an off-condition.

ПОЛУПРОВОДНИКОВЫЙ СВЕРХВЫСОКОЧАСТОТНЫЙ ДИОД

Полупроводниковый сверхвысокочастотный р-и-n-диод содержит кристалл в виде мезоструктуры из высокоомного полупроводникового материала, на противоположных поверхностях которого сформированы сильнолегованные слои р- и n-типу проводимости, омические контакты к ним, смонтированный осесимметрично внутри кольцевого диэлектрического корпуса с металлизированными противоположными плоскостями. Полупроводниковый кристалл выполнен из карбида кремния.

БЕЗКОРПУСНИЙ КРЕМНІЄВИЙ НАДВИСОКОЧАСТОТНИЙ Р-І-N-ДІОД

Безкорпусний кремнієвий надвисокочастотний р-і-n-діод містить кремнієвий кристал із високоомної напівпровідникової пластини, на протилежних поверхнях якої сформовані два сильнолегованих шари p+- і n+ -типу провідності і омічні контакти до них, металеву основу, смужковий вивід, захисне покриття. Кремнієвий кристал виконано у вигляді псевдосфери методом двостороннього ізотропного травлення напівпровідникової структури p+-ni -n+- або p+-pi-n+-типу із симетричними омічними контактами. Товщина високоомної (ρ > 500 Ом·м) nі- або рі -зони визначає величину теоретично розрахованої пробивної напруги, а металева основа має бортики, що забезпечують формування кремнієорганічного захисного покриття у вигляді півсфери.

Preparation method of heterogeneous GaAs-Ge-GaAs pin diode for multi-layer holographic antenna

Preparation method for solid-state plasma reconfigurable dipole antenna

Manufacturing method for solid-state plasma diode equipped with table-shaped active region and used for preparing holographic antenna

Semiconductor switches with evenly distributed structures

Semiconductor device and manufacturing method of semiconductor device

A diode PIN manufacturing method of the electrode

A AlGaAs beam lead PIN diode and its preparation method

Semiconductor device and method for manufacturing semiconductor device

The thin-film capacitor and the Zener diode of the composite electronic component and its manufacturing method

PHOTODETECTEUR A BANDE INTERDITE PROGRESSIVE

L'INVENTION CONCERNE LES PHOTODETECTEURS A SEMICONDUCTEUR. UN PHOTODETECTEUR A AVALANCHE COMPREND UNE REGION DE TYPE P 21, UNE REGION DE TYPE N 23 ET UNE REGION D'AVALANCHE A BANDE INTERDITE PROGRESSIVE 22 SITUEE ENTRE LES REGIONS DE TYPE P ET DE TYPE N. LORSQUE LE DISPOSITIF EST POLARISE EN INVERSE, UN TYPE DE PORTEUR DE CHARGE GENERE PAR LE RAYONNEMENT A DETECTER EST INJECTE PAR DIFFUSION DANS LA REGION A BANDE INTERDITE PROGRESSIVE OU IL DECLENCHE UNE DECHARGE D'AVALANCHE. LA VARIATION DE LA LARGEUR DE LA BANDE INTERDITE CREE UNE DIFFERENCE ELEVEE ENTRE LES COEFFICIENTS D'IONISATION DES DEUX TYPES DE PORTEURS DE CHARGE, CE QUI PROCURE UNE REDUCTION DU BRUIT. APPLICATION AUX PHOTODETECTEURS A AVALANCHE A BRUIT REDUIT.

Pin and similar diodes contg. groove filled with glass - made by simple process where glass passivates edges of pn junction

DIODE HAS AVALANCHE OF THE DOUBLE DIFFUSION TYPE HAS TENSION OF BREAKDOWN RANGING BETWEEN 4 AND 8 VOLTS

Avalanche diode with rectifying contact between differing layers - has very low series resistance and wide applications

SEMICONDUCTOR DEVICES

COMPOSANT SEMICONDUCTEUR RAPIDE, NOTAMMENT DIODE PIN HAUTE TENSION

L'INVENTION CONCERNE UN COMPOSANT SEMICONDUCTEUR HAUTE TENSION RAPIDE, NOTAMMENT UNE DIODE, COMPRENANT UNE ZONE INTERNE, FORMEE D'AU MOINS UNE COUCHE DE SILICIUM A HAUTE RESISTIVITE, COMPRISE ENTRE DEUX COUCHES EXTERIEURES SUPERIEURE ET INFERIEURE DE SILICIUM EXTRINSEQUE. SELON L'INVENTION, L'UNE ET L'AUTRE DES COUCHES EXTERIEURES INFERIEURE ET SUPERIEURE SONT, AU MOINS DANS UNE REGION ACTIVE 11, DU COMPOSANT, DES COUCHES MINCES P, N ET LA COUCHE DE SILICIUM A HAUTE RESISTIVITE I EST DEPOURVUE DE CENTRES DE RECOMBINAISON SUPPLEMENTAIRES SUSCEPTIBLES DE REDUIRE LA DUREE DE VIE DES PORTEURS MINORITAIRES PRESENTS DANS CETTE COUCHE AU MOMENT DE LA TRANSITION DE L'ETAT PASSANT A L'ETAT BLOQUE, L'EPAISSEUR ET LE DOPAGE DES COUCHES EXTERIEURES P, N ETANT DETERMINES EN FONCTION DU DEGRE D'INJECTION SOUHAITE DESDITS PORTEURS MINORITAIRES DANS LA PHASE DE CONDUCTION.

METHOD FOR REALIZATION Of HOMOJONCTION PN IN a NANOSTRUCTURE

FAST COMPONENT SEMICONDUCTOR, IN PARTICULAR DIODE PINE HIGH VOLTAGE

STRUCTURE D'ELECTRODES POUR DISPOSITIFS SEMI-CONDUCTEURS

L'INVENTION SE RAPPORTE A UNE STRUCTURE D'ELECTRODES A UTILISER DANS DES DISPOSITIFS SEMI-CONDUCTEURS. SELON L'INVENTION, ELLE COMPREND UNE COUCHE 20 DE SEMI-CONDUCTEUR, UNE COUCHE CONDUCTRICE 23 DISPOSEE SUR UNE SURFACE DE LA COUCHE 20, DES PREMIERES REGIONS 22 ENTRE LES COUCHES 20 ET 23 ET JOUANT LE ROLE DE PASSAGES PRINCIPAUX POUR LA TRANSMISSION DES PORTEURS MINORITAIRES DE LA COUCHE 20 A LA COUCHE 23; ET DES SECONDES REGIONS 21 ENTRE LES COUCHES 20 ET 23 ET JOUANT LE ROLE DE PASSAGES PRINCIPAUX POUR LE TRANSFERT DE PORTEURS MAJORITAIRES ENTRE ELLES, LES PREMIERES ET SECONDES REGIONS ETANT SELECTIVEMENT FORMEES SUR LA COUCHE 20, AFIN D'ETRE ADJACENTES LES UNES AUX AUTRES ET DE SE TROUVER PARALLELES AUX TRAJETS ELECTRIQUES. L'INVENTION S'APPLIQUE NOTAMMENT A LA FORMATION DE DIODES, THYRISTORS ET TRANSISTORS.

PROCEDE DE REALISATION D'UNE DIODE EN SILICIUM AMORPHE, EQUIPEMENT POUR LA MISE EN OEUVRE D'UN TEL PROCEDE ET APPLICATION A UN DISPOSITIF D'AFFICHAGE A CRISTAL LIQUIDE

PROCEDE DE REALISATION D'UNE DIODE EN SILICIUM AMORPHE COMPRENANT AU MOINS TROIS COUCHES DIFFEREMMENT DOPEES DEPOSEES SUR UN SUBSTRAT ET COMPORTANT UNE PHASE DE DEPOT PAR DECOMPOSITION THERMIQUE D'UN MELANGE GAZEUX SOUS PRESSION ATMOSPHERIQUE A UNE TEMPERATURE INFERIEURE A LA TEMPERATURE DE CRISTALLISATION DU SILICIUM ET UNE PHASE DE RECUIT THERMIQUE EN MILIEU NON IONISE SOUS ATMOSPHERE CONSTITUEE D'HYDROGENE ATOMIQUE. REALISATION PAR CE PROCEDE DE DIODES A FORTE DENSITE DE COURANT ET A TENSION INVERSE ELEVEE. APPLICATIONS DE CES DIODES AUX ECRANS DE VISUALISATION A CRISTAUX LIQUIDES A EFFET THERMO-ELECTRIQUE OU ELLES PEUVENT ETRE INTEGREES DIRECTEMENT SUR LE SUBSTRAT DE CES ECRANS.

SEMICONDUCTOR DEVICES

Microwave diode of the PIN type and its method of manufacture

Horizontal Type PIN Diode and The Manufacturing Method Thereof

PIN DIODE AND MANUFACTURING METHOD THEREOF

PURPOSE: A pin diode is to reduce a forward resistance by forming a n-typed Ohmic metal layer on an exposed side of a n-typed epitaxial layer and a substrate near the epitaxial layer. CONSTITUTION: A pin diode comprises a substrate(31) with a step being formed between a portion to be formed with the pin diode and the remainder portion, a n-typed epitaxial layer(32) formed on the substrate to be formed with the pin diode and having a trapezoidal cross section, a buffer layer(33), a p-typed epitaxial layer(34), a p-typed Ohmic metal layer(35) formed on the p-typed epitaxial layer, a n-typed Ohmic metal layer(38) formed on an exposed side of the n-typed epitaxial layer and the substrate near the epitaxial layer. COPYRIGHT 2000 KIPO ...

Semiconductor device

A semiconductor device includes a semiconductor layer having a first p-type semiconductor region at a first surface and a first n-type semiconductor region at a second surface opposite the first. A second n-type semiconductor region having a n-type dopant concentration lower than the first n-type semiconductor region is between the first p-type and first n-type semiconductor regions. A third n-type semiconductor region is disposed between the second n-type semiconductor region and the first p-type semiconductor region. a fourth n-type semiconductor region is disposed between the first n-type semiconductor region and the second n-type semiconductor region. The fourth n-type semiconductor region has a stored carrier lifetime longer than the third n-type semiconductor region and a crystal lattice defect level is higher in the third n-type semiconductor than in the fourth n-type semiconductor region. An anode is disposed on the first surface and a cathode is disposed on the second surface.

SCHOTTKY DIODES INCLUDING POLYSILICON HAVING LOW BARRIER HEIGHTS AND METHODS OF FABRICATING THE SAME

Hybrid semiconductor devices including a PIN diode portion and a Schottky diode portion are provided. The PIN diode portion is provided on a semiconductor substrate and has an anode contact on a first surface of the semiconductor substrate. The Schottky diode portion is also provided on the semiconductor substrate and includes a polysilicon layer on the semiconductor substrate and a ohmic contact on the polysilicon layer. Related Schottky diodes are also provided herein.

PRODUCTION METHOD FOR SEMICONDUCTOR DEVICE

A production method for a semiconductor device, that includes: an injection step in which proton injection occurs from the rear surface of a first conductivity-type semiconductor substrate (101); and a forming step in which, after the injection step, a first conductivity-type first semiconductor area (101a) having a higher impurity concentration than the semiconductor substrate (101) is formed, by annealing the semiconductor substrate (101) in a furnace. The forming step uses a furnace in a hydrogen atmosphere, and uses a hydrogen volume concentration for the furnace annealing of 0.5%-4.65%. As a result, said production method is capable of reducing crystallization defects during donor generation by proton injection, as well as increasing donor rates.

SEMICONDUCTOR ARRANGEMENT WITH A PIN DIODE

A semiconductor arrangement with a PIN diode is proposed, comprising a heavily n-doped layer (1), a lightly n-doped layer (2) arranged on the heavily n-doped layer (1) and a p-doped layer (3) arranged on the lightly n-doped layer (2), wherein the p-doped layer (3) forms an ohmic contact with a first metallization (5) and the heavily n-doped layer (1) forms an ohmic contact with a second metallization (7). During operation in the forward direction, a high injection takes place, in which the lightly n-doped layer (2) is flooded with charge carriers. At least two trench structures (4) are incorporated in the lightly n-doped layer (2), wherein the trench structures (4) have a dielectric layer (6) on a surface that is in contact with the n-doped surface. The surface (10) of the lightly n-doped layer (2) that is in contact with the dielectric layer (6) has an increased surface recombination velocity for charge carriers.

SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING SAME

To provide a semiconductor device which lowers movable ions within an insulating layer of a surface of a main surface as well as increasing breakdown voltage thereof. A semiconductor device (2) is provided with a plurality of FLRs (14), an insulating layer (5), and semiconductor layers (3). The plurality of FLRs (14), in plan view of a substrate (8), surround an active region formed by elements. The insulating layer (5) is provided upon a main surface of the semiconductor device (2), and covers the plurality of FLRs (14). The semiconductor layers (3) are provided within the insulating layer, and surround the active region in parallel with the FLRs (14). The semiconductor layer (3) includes impurities in a lower density than the density of a RESURF condition. In addition, the semiconductor layers (3), in plan view, overlap portions of a range (inter-ring range (Ra)) between adjacent FLRs (14), and does not overlap with the remainder of the inter-ring range (Ra).

SEMICONDUCTOR RECTIFIER

A semiconductor rectifier provided according to one aspect of the present disclosure is provided with a transistor and a diode. The transistor has a source electrode, a drain electrode, and a gate electrode. The diode has an anode electrode and a cathode electrode. The anode electrode is electrically connected to the gate electrode and the cathode electrode is electrically connected to the source electrode.

SILICON CARBIDE EPITAXIAL SUBSTRATE AND SILICON CARBIDE SEMICONDUCTOR DEVICE

A silicon carbide epitaxial substrate (51) has a silicon carbide monocrystalline substrate (10) of one conductivity type, a first silicon carbide layer (21) of the one conductivity type, a second silicon carbide layer (22) of the one conductivity type, and a third silicon carbide layer (23) of the one conductivity type. The silicon carbide monocrystalline substrate (10) has a first impurity concentration. The first silicon carbide layer (21) is provided on the silicon carbide monocrystalline substrate (10), and has a second impurity concentration lower than the first impurity concentration. The second silicon carbide layer (22) is provided on the first silicon carbide layer (21), and has a third impurity concentration higher than the first impurity concentration. The third silicon carbide layer (23) is provided on the second silicon carbide layer (22), and has a fourth impurity concentration lower than the second impurity concentration.

MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE

Inside a semiconductor substrate which serves as an n- drift layer, a p+ collector layer is provided on the surface layer on the rear surface side, and an n+ field stop layer comprising a plurality of n+ layers is provided in an area which is deeper than the rear surface side p+ collector layer. A front surface element structure is formed on the front surface of the semiconductor substrate, and then proton radiation is carried out on the rear surface of the semiconductor substrate, at an acceleration voltage that corresponds to the depth at which the n+ field stop layer is formed (step S5). Next, protons are donated by means of a first annealing at an annealing temperature which corresponds to the proton radiation (step S6). By annealing using annealing conditions that have been adapted to the conditions for multiple repetitions of proton radiation, each of the crystal defects formed by each of the repetitions of proton radiation can be recovered, enabling the formation of multiple regions ...

PIN DIODE WITH SIGE LOW CONTACT RESISTANCE AND METHOD FOR FORMING THE SAME

A semiconductor p-i-n diode and method for forming the same are described herein. In one aspect, a SiGe region is formed between a region doped to have one conductivity (either p+ or n+) and an electrical contact to the p-i-n diode. The SiGe region may serve to lower the contact resistance, which may increase the forward bias current. The doped region extends below the SiGe region such that it is between the SiGe region and an intrinsic region of the diode. The p-i-n diode may be formed from silicon. The doped region below the SiGe region may serve to keep the reverse bias current from increasing as result of the added SiGe region. In one embodiment, the SiGe is formed such that the forward bias current of an up-pointing p-i-n diode in a memory array substantially matches the forward bias current of a down-pointing p-i-n diode which may achieve better switching results when these diodes are used with the R/W material in a 3D memory array.

SEMICONDUCTOR DEVICE

This semiconductor device comprises: a semiconductor layer of a first conductivity type, which has a main surface; a diode region of the first conductivity type, which is formed in a superficial part of the main surface of the semiconductor layer; a carrier trapping region which contains a crystal defect and is formed along the peripheral edge of the diode region in the superficial part of the main surface of the semiconductor layer; and an anode electrode which is formed on the main surface of the semiconductor layer, while forming a Schottky junction with the diode region.

SILICON CARBIDE SEMICONDUCTOR DEVICE

According to the present invention, first to third electric field relaxation layers (11-13) are provided in an edge termination region so as to be concentric around the circumference of an active region. First to third p-type spatial modulation regions (21-23) are provided between the adjacent first to third electric field relaxation layers (11-13) and on the outer side relative to the third electric field relaxation layer (13), respectively. The spatial modulation regions are each formed by low-concentration small regions (32) and high-concentration small regions (31) being alternately and repetitively arranged from the inner side so as to be concentric around the circumference of the electric field relaxation layer that is on the inner side. The lengths (Lb1-Lb3) of the first to third spatial modulation regions (21-23) are set to be dimensions satisfying Lb1≤Lb2 Подробнее

METHOD FOR PRODUCING SEMICONDUCTOR ELEMENT, AND SEMICONDUCTOR DEVICE

A method for manufacturing a semiconductor element includes: a step for providing a mask 21 leaving a step 23 in an upper-surface region surrounding an opening 22 above the surface 11a of a substrate 11; a step for epitaxially growing a semiconductor from the surface 11a exposed through the opening 22 above the surrounding upper-surface region, and preparing a semiconductor element having a semiconductor layer 31 that has a first surface on which the step 23 is transferred; and a step for dry-etching the first surface of the semiconductor layer 31 contacting the mask 21, and transferring the step 23. The mask 21 includes an element that is a donor or acceptor of the semiconductor layer 31.

VERTICAL PIN DIODE

A diode semiconductor structure is described. In one example, a diode device includes a substrate, a layer of first semiconductor material of a first doping type, a layer of intrinsic semiconductor material, and a layer of second semiconductor material of a second doping type. The diode device also includes a metal contact formed on the layer of first semiconductor material and a metal via formed from a backside of the substrate, through the substrate, and through the layer of first semiconductor material, where the metal via contacts a bottom surface of the metal contact on the layer of first semiconductor material. In this configuration, a direct electrical connection can be achieved between the backside of the substrate and the metal contact on the layer of first semiconductor material without the need for an additional metal connection, such as a metal air bridge, to the metal contact.

PROCESS FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

A process for producing a semiconductor device includes: forming an SiC epitaxial layer on an SiC substrate; implanting the epitaxial layer with ions; forming a gettering layer having a higher defect density than a defect density of the SiC substrate; and carrying out a heat treatment on the epitaxial layer. The semiconductor device includes an SiC substrate, an SiC epitaxial layer formed on the SiC substrate, and a gettering layer having a higher defect density than a defect density of the SiC substrate.

RECONFIGURABLE ANTENNA

A reconfigurable antenna capable of dynamic reconfigurability of several antenna parameters. Specifically, the present invention is an antenna comprising a plurality of surface PIN devices arranged in a gridlike array. Each of the SPIN devices can be individually activated or deactivated. When a SPIN device is activated, the surface of the device is injected with carriers such that a plasma is produced within the intrinsic region of the device. The plasma can be sufficiently conductive to produce conductor or metal like characteristics at the surface of the device. Various ones of the SPIN devices can be activated to electronically paint a conductive pattern upon the substrate supporting the PIN devices. Through selective activation of the SPIN devices various surface antenna patterns can be produced upon the substrate including dipoles, cross dipoles, loop antennas, Yagi-Uda type antennas, log periodic antennas, and the like. Additionally, the SPIN device grid may be selectively activated ...

HIGH VOLTAGE SEMICONDUCTOR DEVICE

A compound semiconductor device is comprising a compound semiconductor substrate (219) having a ground plane (205); an active element (201) disposed on the substrate; a passive element (211) disposed on the substrate and electrically coupled to the active element; and an insulating layer (202) adjacent the substrate and interposed between the passive device and ground surface such that there is no resistive ground path from the passive device to the ground surface.

SEMICONDUCTOR DEVICE MANUFACTURING METHOD

According to the present invention, an insulating film 6 having a thickness of 0.5 μm or more is formed on an epitaxial layer 2 in which a well region 3, a source region 4, and a contact region 5, which are impurity diffusion regions, are formed, an opening having dimensions of 2 mm × 2 mm or more in a planar view is formed in the insulating film 6, and at least a part of the impurity diffusion region is exposed from the insulating film 6. A step for forming the opening in the insulating film 6 is performed by separate steps including: a step for removing the insulating film 6 through dry etching using a photoresist 102 as a mask so as to leave a half or less of the thickness of the insulating film 6 unremoved; and a step for removing the insulating film 6 through wet etching using the photoresist 102 as a mask until the upper surface of the epitaxial layer 2 is reached.

IMPROVED SCHOTTKY RECTIFIER

A semiconductor rectifier includes a semiconductor substrate having a first type of conductivity. A first layer, which is formed on the substrate, has the first type of conductivity and is more lightly doped than the substrate. A second layer having a second type of conductivity is formed on the substrate and a metal layer is disposed over the second layer. The second layer is lightly doped so that a Schottky contact is formed between the metal layer and the second layer. A first electrode is formed over the metal layer and a second electrode is formed on a backside of the substrate.

SEMICONDUCTOR DEVICE

This semiconductor device comprises: a semiconductor layer; an insulated gate first transistor formed in the semiconductor layer; an insulated gate second transistor formed in the semiconductor layer; and a control wire which is formed on the semiconductor layer so as to be electrically connected to the first transistor and the second transistor, and transmits a control signal for controlling the first transistor and the second transistor to an on-state during a conventional operation, and for controlling the second transistor to an on-state while controlling the first transistor to an off-state during an active clamp operation.

METHOD FOR THE PRODUCTION OF A BURIED STOP ZONE IN A SEMI-CONDUCTOR ELEMENT AND SEMI-CONDUCTOR ELEMENT COMPRISING A BURIED STOP ZONE

The invention relates to a method for producing a stop zone in a doped zone of a semi-conductor body which comprises a first side and a second side. Said method comprises the following steps: applying a mask comprising a recess to one of the sides of the semi-conductor body; subjecting the side provided with the mask to proton radiation and carrying out a tempering method in order to produce hydrogen-induced dome gates in the semi-conductor body. The invention also relates to a semi-conductor body provided with a buried stop zone.

Diamond semiconductor system and method

Disclosed herein is a new and improved system and method for fabricating diamond semiconductors. The method may include the steps of selecting a diamond semiconductor material having a surface, exposing the surface to a source gas in an etching chamber, forming a carbide interface contact layer on the surface; and forming a metal layer on the interface layer.

Thin-film transistor and thin-film diode having amorphous-oxide semiconductor layer

A thin-film transistor including a channel layer being formed of an oxide semiconductor transparent to visible light and having a refractive index of nx, a gate-insulating layer disposed on one face of the channel layer, and a transparent layer disposed on the other face of the channel layer and having a refractive index of nt, where there is a relationship of nx>nt. A thin-film transistor including a substrate having a refractive index of no, a transparent layer disposed on the substrate and having a refractive index of nt, and a channel layer disposed on the transparent layer and having a refractive index of nx, where there is a relationship of nx>nt>no.

Tunneling magnetoresistive element, semiconductor junction element, magnetic memory and semiconductor light emitting element

A pin junction element includes a ferromagnetic p-type semiconductor layer and a n-type semiconductor layer which are connected via an insulating layer, and which shows a tunneling magnetic resistance according to the magnetization of the ferromagnetic p-type semiconductor layer and the magnetization of the ferromagnetic n-type semiconductor layer. In this pin junction element, an empty layer is formed with an applied bias, thereby generating tunnel current via an empty layer. As a result, it is possible to generate tunnel current even when adopting a thicker insulating layer than that of the conventional tunnel magnetic resistance element.

Semiconductor device having high breakdown voltage

A semiconductor body (100) has a first device region (20) of one conductivity type forming with a second device region (13) of the opposite conductivity type provided adjacent one major surface (11) of the semiconductor body (100) a first pn junction (40) which is reverse-biassed in at least one mode of operation. A floating further region (50) of the opposite conductivity type is provided within the first device region (20) remote from the major surfaces (11 and 12) of the semiconductor body (100) and spaced from the second device region (13) so that, in the one mode, the depletion region of the first pn junction (40) reaches the floating further region (50) before the first pn junction (40) breaks down. The floating further region (50) forms a further pn junction (51) with a highly doped capping region (60) of the one conductivity type which is provided within the first device region (20) between the floating further region (50) and the second device region (13) and spaced from the second ...

Integrated trigger injector for avalanche semiconductor switch devices

An avalanche semiconductor switch device utilizes trigger input. The integrated trigger input is a charge carrier injector which injects charge carriers directly into the avalanche semiconductor switch device. The avalanche semiconductor switch device includes: an active, semi-insulating layer; an anode; a cathode; and an injector disposed on the anode contact. The injector serves to switch the device into a state of very high conductance when a positive bias is applied to the injector. The integrated trigger input allows low power optical sources to be used with the avalanche semiconductor switch device further back in the trigger chain. The injector may inject holes or electrons. The injector may be integrated on one side of the substrate.

COMPOUND SEMICONDUCTOR MONOLITHIC INTEGRATED CIRCUIT DEVICE WITH TRANSISTORS AND DIODES

A compound semiconductor monolithically integrated circuit device with transistors and diodes comprises a compound semiconductor substrate, a transistor epitaxial structure, a transistor upper structure, a first diode, and a second diode. The transistor epitaxial structure forms on the compound semiconductor substrate. The first diode, the second diode, and the transistor upper structure form on a first part, a second part, and a third part of the transistor epitaxial structure, respectively. The transistor upper structure and the third part of the transistor epitaxial structure form a transistor. The first diode comprises a first part of an n-type doped epitaxial layer, a first part of a first intrinsic epitaxial layer, a first electrode, and a second electrode. The second diode comprises a second part of the n-type doped epitaxial layer, a second part of the first intrinsic epitaxial layer, a first electrode, and a second electrode.

SEMICONDUCTOR DEVICE

A semiconductor device is provided having a first region and a second region surrounding the first region includes a first electrode, a second electrode, a first semiconductor layer of a first conductivity type between the first electrode and the second electrode, a second semiconductor layer of the first conductivity type located over the first semiconductor layer, a third semiconductor layer of the second conductivity type on the second semiconductor layer in the first region, a fourth semiconductor layer of the first conductivity type between the third semiconductor layer and the second semiconductor layer, a fifth semiconductor layer of the second conductivity type on the second semiconductor layer in the second region, and a sixth semiconductor layer of the first conductivity type located between the fifth semiconductor layer and the second semiconductor layer, wherein the width of the fourth semiconductor layer is less than the width of the sixth semiconductor layer.

SILICON CARBIDE EPITAXIAL SUBSTRATE, METHOD OF MANUFACTURING THEREOF, SILICON CARBIDE SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THEREOF

A silicon carbide epitaxial substrate including a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, and a high-density foreign element region. The first semiconductor layer is provided at a front surface of the silicon carbide semiconductor substrate and has an impurity concentration lower than that of the silicon carbide semiconductor substrate. The high-density foreign element region is provided in the silicon carbide semiconductor substrate at a predetermined depth from the front surface thereof. The high-density foreign element region contains an element other than carbon and silicon, at a density higher than that of the silicon carbide semiconductor substrate.

SEMICONDUCTOR DEVICE

A semiconductor device comprising: a Metal Oxide Semiconductor Field Effect Transistor including: a semiconductor substrate including a first semiconductor layer of a first conductivity type; second semiconductor layers of a second conductivity type extending in a depth direction from one surface of the semiconductor substrate, and having space each other; a first diode including a fifth semiconductor layer of the second conductivity type contacting the second semiconductor layer in one surface side of the semiconductor substrate, the first semiconductor layer and the second semiconductor layers; and an anode of the second diode connected to an anode of the first diode.

FABRICATING HIGH-POWER DEVICES

According to an embodiment of the present invention, a method for fabricating a semiconductor device comprises depositing a transition layer on a substrate, depositing GaN material on the transition layer, forming a contact on the GaN material, depositing a stressor layer on the GaN material, separating the transition layer and the substrate from the GaN material, patterning and removing portions of the GaN material to expose portions of the stressor layer.

SEMICONDUCTOR DEVICE

A semiconductor device according to an embodiment includes first and second electrode, and semiconductor layer between the first and the second electrode. The semiconductor layer has first and second plane. The semiconductor layer includes first region of first conductivity type, second region of second conductivity type between the first plane and the first region, third region of second conductivity type between the first plane and the first region and, fourth region of second conductivity type between the second and the third region, and fifth region of first conductivity type having first portion provided between the first and the fourth region. Width of the fourth region is larger than that of the second region. Distance between the second region and the first portion is smaller than distance between the second and the fourth region. And width of the first portion is smaller than that of the fourth region.

Semiconductor devices and their manufacture

A localised reduced lifetime region (1,25,41) is provided in a semiconductor device formed substantially of silicon. A predetermined concentration of carbon is provided in the region, and then the body is heated to incorporate a lifetime controlling impurity substantially within the carbon region. It is believed that the association between the impurity ions (M+) and the carbon atoms (C) on silicon lattice sites produces C-M+ complexes with significant capture cross-sections. The carbon may be provided by addition during epitaxial growth of silicon material, during bulk growth of the silicon, or by implantation and/or diffusion.

Diode

A diode of the present disclosure includes a stacked structure, and a first connection section and a second connection section provided at respective ends of the stacked structure in a length direction. The stacked structure includes a first structure and a second structure each having a nanowire structure or a nanosheet structure and stacked alternately in a thickness direction. The first connection section has a first conductivity type, and the second connection section has a second conductivity type. The diode A further includes a control electrode section formed to extend at least from a top portion to a side surface of the stacked structure and spaced apart from the first connection section and the second connection section. The first connection section and the control electrode section or the second connection section and the control electrode section are connected electrically.

METHOD FOR MANUFACTURING AN EDGE TERMINATION FOR A SILICON CARBIDE POWER SEMICONDUCTOR DEVICE

SEMICONDUCTOR ELEMENT, ELECTRIC APPARATUS, BIDIRECTIONAL FIELD EFFECT TRANSISTOR, AND MOUNTING STRUCTURAL BODY

Provided are a semiconductor device and a bidirectional field effect transistor which can easily overcome the tradeoff relation between the high voltage resistance and high speed in the semiconductor device using a polarization super junction, realize both the high voltage resistance and elimination of the occurrence of current collapse, operate at a high speed, and further the loss is low. The semiconductor device comprises a polarization super junction region and a p-electrode contact region. The polarization super junction region comprises an undoped GaN layer 11, an undoped AlxGa1-xN layer 12 with a thickness not smaller than 25nm and not larger than 47nm and 0.17≤x≤0.35, an undoped GaN layer 13 and a p-type GaN layer 14. When the reduced thickness tR is defined as tR=u+v(1+w×10-18) for the thickness u [nm] of the undoped GaN layer 13, the thickness v [nm] and the Mg concentration w[cm-3] of the p-type GaN layer 14, tR≥0.864/(x-0.134)+46.0 [nm] is satisfied. The p-electrode contact ...

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE FABRICATION METHOD

A protective diode (101) has a basic structure (103) including an n+ layer (11), an n- layer (10), a p+ layer (12), and an n- layer (10) in this order. A p-type layer forming the protective diode (101) is the p+ layer (12) with high impurity concentration. Therefore, the spreading of a depletion layer is suppressed and it is possible to reduce the area of the protective diode (101). In addition, phosphorus ions with a large diffusion coefficient are implanted to form the n- layer (10) with low impurity concentration in the polysilicon layer (9) forming the protective diode (101). A heat treatment is performed at a temperature of 1000°C or higher to diffuse the phosphorus ions implanted into the polysilicon layer (9). Therefore, the impurity profile of the n- layer (10) in the depth direction can be uniformized in the depth direction. As a result, a pn junction surface between the p+ layer (12) with high impurity concentration and the n- layer (10) with low impurity concentration is substantially ...

Semi-conductor device with a low parasitic capacitance having beam-lead type external connectors, and process for the production of that device

半導体装置および半導体装置の製造方法

非線形素子、及び表示装置

炭化珪素半導体装置の製造方法

ОКСИД Р-ТИПА, ПОЛУЧЕНИЕ ОКСИДНОЙ КОМПОЗИЦИИ Р-ТИПА, СПОСОБ ПОЛУЧЕНИЯ ОКСИДА Р-ТИПА, ПОЛУПРОВОДНИКОВЫЙ ПРИБОР, ИНДИКАТОРНОЕ УСТРОЙСТВО, АППАРАТУРА ВОСПРОИЗВЕДЕНИЯ ИЗОБРАЖЕНИЯ И СИСТЕМА

Изобретение относится к оксиду р-типа, оксидной композиции р-типа, способу получения оксида р-типа, полупроводниковому прибору, аппаратуре воспроизведения изображения и системе. Оксид р-типа является аморфным соединением и представлен следующей композиционной формулой: xAO∙yCuO, где x обозначает долю молей AO и y обозначает долю молей CuO, x и y удовлетворяют следующим условиям: 0≤x<100 и x+y=100 и А является любым одним из Mg, Са, Sr и Ва или смесью, содержащей, по меньшей мере, два элемента, выбранные из группы, состоящей из Mg, Са, Sr и Ва. Оксид р-типа производится при относительно низкой температуре и в реальных условиях и способен проявлять отличные свойства, то есть достаточную удельную электропроводность. 7 н. и 4 з.п. ф-лы, 36 ил., 8 табл., 52 пр.

ПОЛУПРОВОДНИКОВОЕ УСТРОЙСТВО ТАНДЕМНОГО ТИПА

Изобретение относится к оптоэлектронике и направлено на повышение качества преобразования энергии. Многопереходное полупроводниковое устройство, содержащее слой типа p, слой типа n из аморфного полупроводника или из аморфного полупроводника, включающего микрокристаллы и слой, блокирующий диффузию, расположенный между слоем типа p и слоем типа n толщиной от 5 до предпочтительно от 10 до Полупроводниковое устройство может уменьшать ухудшение качества, вызываемое диффузией атомов легирующего материала, присутствующего соответственно в слое типа p слое типа n в другой слой. 1 ил. 3 табл.

Verfahren zur Herstellung eines Halbleiterbauelements und Halbleiterbauelement

Die vorliegende Erfindung betrifft ein Verfahren zur Herstellung eines Halbleiterbauelements, das folgende Merkmale aufweist: DOLLAR A - Bereitstellen eines Halbleiterkörpers (100) mit einer ersten und einer zweiten Oberfläche (101, 102), DOLLAR A - Herstellen einer Vielzahl von Poren (103) in dem Halbleiterkörper (100), die sich, ausgehend von der ersten Oberfläche (101), in den Halbleiterkörper (100) hinein erstrecken und die unterhalb der zweiten Oberfläche (102) enden, DOLLAR A - Steigern der elektrischen Leitfähigkeit des Halbleiterkörpers (100) im Bereich der Poren (103). DOLLAR A Die Erfindung betrifft des weiteren ein Halbleiterbauelement.

Method of manufacturing diode, and diode

The present specification provides a method of efficiently manufacturing diodes in which recovery surge voltage is hardly generated. The method manufactures a diode including a high concentration n-type semiconductor layer, a medium concentration n-type semiconductor layer formed on the high concentration n-type semiconductor layer, a low concentration n-type semiconductor layer formed on the medium concentration n-type semiconductor layer, and a p-type semiconductor layer formed on the low concentration n-type semiconductor layer. This manufacturing method includes growing the low concentration n-type semiconductor layer on an n-type semiconductor substrate by epitaxial growth, wherein a concentration of n-type impurities in the low concentration n-type semiconductor layer is lower than that in the n-type semiconductor substrate, and forming the high concentration n-type semiconductor layer by injecting n-type impurities to a lower surface of the n-type semiconductor substrate.

High Voltage Semiconductor Devices

In one embodiment, the semiconductor device includes a first source of a first doping type disposed in a substrate. A first drain of the first doping type is disposed in the substrate. A first gate region is disposed between the first source and the first drain. A first channel region of a second doping type is disposed under the first gate region. The second doping type is opposite to the first doping type. A first extension region of the first doping type is disposed between the first gate and the first drain. The first extension region is part of a first fin disposed in or over the substrate. A first isolation region is disposed between the first extension region and the first drain. A first well region of the first doping type is disposed under the first isolation region. The first well region electrically couples the first extension region with the first drain.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a drift layer, a base layer on the drift layer, and trench gate structures. Each trench gate structure includes a trench reaching the drift layer by penetrating the base layer, a gate insulation layer on a wall surface of the trench, and a gate electrode on the gate insulation layer. A bottom portion of the trench gate structure is located in the drift layer and expands in a predetermined direction so that a distance between the bottom portions of adjacent trench gate structures is less than a distance between opening portions of adjacent trench gate structures in the direction. A thickness of the gate insulation layer is greater in the bottom portion than in the opening portion.

Semiconductor device and manufacturing method for the same

A semiconductor device includes a first conductive type first semiconductor region, a second semiconductor region, and a second conductive type lateral RESURF region. The first semiconductor region is arranged on a first electrode side. The second semiconductor region includes first conductive type first pillar regions and a terminal part. The second pillar regions are alternately arranged on an element part. The terminal part is formed around the element part along a surface of the first semiconductor region on a second electrode side opposite to the first electrode side of the first semiconductor region. Furthermore, the second conductive type lateral RESURF region is formed in the second semiconductor region on the terminal part.

Semiconductor device

A semiconductor device is disclosed wherein a peripheral region with a high breakdown voltage and high robustness against induced surface charge is manufactured using a process with high mass productivity. The device has n-type drift region and p-type partition region of layer-shape deposited in a vertical direction to one main surface of n-type semiconductor substrate with high impurity concentration form as drift layer, alternately adjacent parallel pn layers in a direction along one main surface. Active region through which current flows and peripheral region enclosing the active region include parallel pn layers. P-type partition region has impurity concentration distribution where concentration decreases from surface toward substrate side, n-type surface region disposed on parallel pn layers in peripheral region, p-type guard rings disposed separately from each other on n-type surface region, and field plate disposed on inner and outer circumferential sides of p-type guard rings, and electrically connected.

Schottky rectifier

A semiconductor rectifier includes a semiconductor substrate having a first type of conductivity. A first layer, which is formed on the substrate, has the first type of conductivity and is more lightly doped than the substrate. A second layer having a second type of conductivity is formed on the substrate and a metal layer is disposed over the second layer. The second layer is lightly doped so that a Schottky contact is formed between the metal layer and the second layer. A first electrode is formed over the metal layer and a second electrode is formed on a backside of the substrate.

Bipolar transistor with guard region

A bipolar transistor comprising an emitter region, a base region and a collector region, and a guard region spaced from and surrounding the base. The guard region can be formed in the same steps that form the base, and can serve to spread out the depletion layer in operation.

Semiconductor device

A semiconductor device includes an epitaxial layer having a first conductive type, and at least one first semiconductor layer and a second semiconductor layer having a second conductive type. The first semiconductor layer is disposed in the epitaxial layer of a peripheral region, and has an arc portion, and a first strip portion and a second strip portion extended from two ends of the arc portion. The first strip portion points to an active device region, and the second strip portion is perpendicular to the first strip portion The second semiconductor layer is disposed in the epitaxial layer of the peripheral region between the active device region and the second strip portion, and the second semiconductor has a sidewall facing and parallel to the first semiconductor layer.

Semiconductor device

In a semiconductor power device such as a power MOSFET having a super-junction structure in each of an active cell region and a chip peripheral region, an outer end of a surface region of a second conductivity type coupled to a main junction of the second conductivity type in a surface of a drift region of a first conductivity type and having a concentration lower than that of the main junction is located in a middle region between an outer end of the main junction and an outer end of the super-junction structure in the chip peripheral region.

Semiconductor rectifier device

A semiconductor rectifier device according to an embodiment includes a semiconductor substrate of a first conductive type of a wide gap semiconductor, a semiconductor layer of the first conductive type of the wide gap semiconductor formed on an upper surface of the semiconductor substrate, wherein an impurity concentration of the semiconductor layer is between 1E+14 atoms/cm 3 and 5E+16 atoms/cm 3 inclusive, and a thickness thereof is 8 μm or more, a first semiconductor region of the first conductive type of the wide gap semiconductor formed on the semiconductor layer surface, a second semiconductor region of the second conductive type of the wide gap semiconductor formed as sandwiched by the first semiconductor regions, wherein a width of the second semiconductor region is 15 μm or more, a first electrode formed on the first and second semiconductor regions, and a second electrode formed on a lower surface of the semiconductor substrate.

Semiconductor device

According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductive type, and a periodic array structure having a second semiconductor layer of a first conductive type and a third semiconductor layer of a second conductive type periodically arrayed on the first semiconductor layer in a direction parallel with a major surface of the first semiconductor layer. The second semiconductor layer and the third semiconductor layer are disposed in dots on the first semiconductor layer. A periodic structure in the outermost peripheral portion of the periodic array structure is different from a periodic structure of the periodic array structure in a portion other than the outermost peripheral portion.

Semiconductor system including a schottky diode

A semiconductor system is described, which includes a trench junction barrier Schottky diode having an integrated p-n type diode as a clamping element, which is suitable for use in motor vehicle generator system, in particular as a Zener diode having a breakdown voltage of approximately 20V. In this case, the TJBS is a combination of a Schottky diode and a p-n type diode. Where the breakdown voltages are concerned, the breakdown voltage of the p-n type diode is lower than the breakdown voltage of Schottky diode. The semiconductor system may therefore be operated using high currents at breakdown.

Flexible lateral pin diodes and three-dimensional arrays and imaging devices made therefrom

Flexible lateral p-i-n (“PIN”) diodes, arrays of flexible PIN diodes and imaging devices incorporating arrays of PIN diodes are provided. The flexible lateral PIN diodes are fabricated from thin, flexible layers of single-crystalline semiconductor. A plurality of the PIN diodes can be patterned into a single semiconductor layer to provide a flexible photodetector array that can be formed into a three-dimensional imaging device.

Vertical junction field effect transistor with mesa termination and method of making the same

A vertical junction field effect transistor (VJFET) having a mesa termination and a method of making the device are described. The device includes: an n-type mesa on an n-type substrate; a plurality of raised n-type regions on the mesa comprising an upper n-type layer on a lower n-type layer; p-type regions between and adjacent the raised n-type regions and along a lower sidewall portion of the raised regions; dielectric material on the sidewalls of the raised regions, on the p-type regions and on the sidewalls of the mesa; and electrical contacts to the substrate (drain), p-type regions (gate) and the upper n-type layer (source). The device can be made in a wide-bandgap semiconductor material such as SiC. The method includes selectively etching through an n-type layer using a mask to form the raised regions and implanting p-type dopants into exposed surfaces of an underlying n-type layer using the mask.

Semiconductor mos entrance window for radiation detectors

A semiconductor detector device, such as a PIN diode or silicon drift detector, including a substrate with an entrance window. The entrance window comprises a conductive layer, and an insulating layer disposed between the conductive layer and the substrate. The insulating layer and conductive layer cover a center portion of the surface of the substrate.

Mosfet-schottky rectifier-diode integrated circuits with trench contact structures

A trench MOSFET device with embedded Schottky rectifier, Gate-Drain and Gate-Source clamp diodes on single chip is formed to achieve device shrinkage and performance improvement. The present semiconductor devices achieve low Vf and reverse leakage current for embedded Schottky rectifier, have overvoltage protection for Gate-Source clamp diode and avalanche protection for Gate-Drain clamp diode.

Power semiconductor device

A power semiconductor device includes a high resistance epitaxial layer having a first pillar region and a second pillar region as a drift layer. The first pillar region includes a plurality of first pillars of the first conductivity type and a plurality of second pillars of the second conductivity type disposed alternately along a first direction. The second pillar region is adjacent to the first pillar region along the first direction. The second pillar region includes a third pillar and a fourth pillar of a conductivity type opposite to a conductivity type of the third pillar. A net quantity of impurities in the third pillar is less than a net quantity of impurities in each of the plurality of first pillars. A net quantity of impurities in the fourth pillar is less than the net quantity of impurities in the third pillar.

SCHOTTKY BARRIER DIODE AND METHOD OF FORMING A SCHOTTKY BARRIER DIODE

Disclosed is a silicon-on-insulator-based Schottky barrier diode with a low forward voltage that can be manufactured according to standard SOI process flow. An active silicon island is formed using an SOI wafer. One area of the island is heavily-doped with an n-type or p-type dopant, one area is lightly-doped with the same dopant, and an isolation structure is formed on the top surface above a junction between the two areas. A metal silicide region contacts the lightly-doped side of the island forming a Schottky barrier. Another discrete metal silicide region contacts the heavily-doped area of the island forming an electrode to the Schottky barrier (i.e., a Schottky barrier contact). The two metal silicide regions are isolated from each other by the isolation structure. Contacts to each of the discrete metal silicide regions allow a forward and/or a reverse bias to be applied to the Schottky barrier. 1. A method of forming a Schottky barrier diode comprising:forming a silicon island in an insulator, said silicon island having an exposed top surface, a first area, and a second area;forming an isolation structure on said exposed top surface between said first area and said second area;doping said first area with one of a p-type dopant and an n-type dopant; andperforming a metal silicide formation process such that a first metal silicide region contacts said first area and extends above said top surface and such that a second metal silicide region contacts said second area and extends above said top region,said isolation structure separating said first metal silicide region from said second metal silicide region, andsaid second metal silicide region forming a Schottky barrier contact to said second area.2. The method of claim 1 , further comprising before said forming of said isolation structure claim 1 , doping said silicon island with said one of said p-type dopant and said n-type dopant in a lower concentration as compared to said first area.3. The method of claim 1 ...

Semiconductor device and manufacturing method of the same

A semiconductor device includes first, second, and third semiconductor layers each having multiple diffusion layers. The first direction widths of the first diffusion layers are the same. The amount of impurity within the first diffusion layers gradually increases from the bottom end towards the top end of the first semiconductor layer. The first direction widths of the second diffusion layers are the same. The amounts of impurity within the second diffusion layers are the same. The first direction widths of the third diffusion layers are narrower than the first direction widths of the first diffusion layers and the first direction widths of the second diffusion layers at the same level, and gradually become narrower from the bottom end towards the top end of the third semiconductor layer. The amount of impurity within the third. diffusion layers are the same.

Plasma Dicing and Semiconductor Devices Formed Thereof

In one embodiment, a method of forming a semiconductor device includes forming islands by forming deep trenches within scribe lines of a substrate. The islands have a first notch disposed on sidewalls of the islands. A first electrode stack is formed over a top surface of the islands. The back surface of the substrate is thinned to separate the islands. A second electrode stack is formed over a back surface of the islands. 1. A semiconductor device comprising:a first doped region disposed adjacent a top surface of a substrate;a first electrode disposed on the top surface;a second doped region disposed adjacent a bottom surface of the substrate, wherein the bottom surface is opposite to the top surface;a second electrode disposed on the bottom surface; anda first notch disposed around sidewalls of the substrate in a first region, wherein the substrate has a first dimension at the top surface, wherein the substrate has a second dimension in the first region, and wherein the second dimension is smaller than the first dimension.2. The semiconductor device of claim 1 , wherein the first region overlays a junction between the first and the second doped regions claim 1 , and wherein a conductivity type of the first doped region is opposite to the second doped region.3. The semiconductor device of claim 1 , further comprising a second notch disposed around the sidewalls of the substrate in a second region claim 1 , the second region disposed between the first region and the top surface claim 1 , wherein the substrate has a third dimension in the second region claim 1 , the third dimension being smaller than the first dimension claim 1 , wherein the substrate has the first dimension in a region between the first and the second regions.4. The semiconductor device of claim 3 , wherein the first region is adjacent a junction between a first doped region and an intrinsic region claim 3 , wherein the second region is adjacent a junction between a second doped region and the ...

Edge Termination by Ion Implantation in GaN

An edge terminated semiconductor device is described including a GaN substrate; a doped GaN epitaxial layer grown on the GaN substrate including an ion-implanted insulation region, wherein the ion-implanted region has a resistivity that is at least 90% of maximum resistivity and a conductive layer, such as a Schottky metal layer, disposed over the GaN epitaxial layer, wherein the conductive layer overlaps a portion of the ion-implanted region. A Schottky diode is prepared using the Schottky contact structure.

JUNCTION BARRIER SCHOTTKY RECTIFIERS HAVING EPITAXIALLY GROWN P+-N JUNCTIONS AND METHODS OF MAKING

A junction barrier Schottky (JBS) rectifier device and a method of making the device are described. The device comprises an epitaxially grown first n-type drift layer and p-type regions forming p-n junctions and self-planarizing epitaxially over-grown second n-type drift regions between and, optionally, on top of the p-type regions. The device may include an edge termination structure such as an exposed or buried P guard ring, a regrown or implanted junction termination extension (JTE) region, or a “deep” mesa etched down to the substrate. The Schottky contact to the second n-type drift region and the ohmic contact to the p-type region together serve as an anode. The cathode can be formed by ohmic contact to the n-type region on the backside of the wafer. The devices can be used in monolithic digital, analog, and microwave integrated circuits. 150-. (canceled)51. A semiconductor device comprising:a semiconductor substrate of a first conductivity type;a semiconductor drift layer above the substrate;a plurality of highly doped epitaxial layer regions of semiconductor material of a second conductivity type different than the first conductivity type, each of the highly doped epitaxial layer regions separated from one another on the drift layer to form a plurality of junction barriers therewith, the highly doped epitaxial layer regions each having an upper surface and sidewalls; anda plurality of epitaxial drift layer regions of semiconductor material of the first conductivity type, at least some of the epitaxial drift layer regions being disposed between sidewalls of adjacent of the highly doped epitaxial layer regions to electrically couple with the drift layer;at least one ohmic contact with at least some of the plurality of highly doped epitaxial layer regions; andat least one Schottky contact with at least some of the drift layer regions of semiconductor material.52. The semiconductor device of claim 51 , wherein each of the highly doped epitaxial layer regions is ...

Method and system for fabricating edge termination structures in gan materials

A method for fabricating an edge termination, which can be used in conjunction with GaN-based materials, includes providing a substrate of a first conductivity type. The substrate has a first surface and a second surface. The method also includes forming a first GaN epitaxial layer of the first conductivity type coupled to the first surface of the substrate and forming a second GaN epitaxial layer of a second conductivity type opposite to the first conductivity type. The second GaN epitaxial layer is coupled to the first GaN epitaxial layer. The substrate, the first GaN epitaxial layer and the second GaN epitaxial layer can be referred to as an epitaxial structure.

SUPER TRENCH SCHOTTKY BARRIER SCHOTTKY DIODE

A Schottky diode includes an n-substrate, an n-epilayer, trenches introduced into the n-epilayer, floating Schottky contacts being located on their side walls and on the entire trench bottom, mesa regions between the adjacent trenches, a metal layer on its back face, this metal layer being used as a cathode electrode, and an anode electrode on the front face of the Schottky diode having two metal layers, the first metal layer of which forms a Schottky contact and the second metal layer of which is situated below the first metal layer and also forms a Schottky contact. Preferably, these two Schottky contacts have different barrier heights. 1. A Schottky diode , comprising:{'sup': '+', 'an n-substrate;'}an n-epilayer;trenches introduced into the n-epilayer;mesa regions between adjacent trenches;a metal layer on a back face of the diode, the metal layer being used as a cathode electrode;an anode electrode provided on a front face of the diode, the anode electrode having two metal layers, a first metal layer forming a Schottky contact, and a second metal layer being situated below the first metal layer and also forming a Schottky contact; andadditional, floating Schottky contacts situated on walls of the trenches between the second metal layer and bottoms of the trenches.2. The Schottky diode according to claim 1 , wherein the first metal layer and the second metal layer claim 1 , each of which forms a Schottky contact claim 1 , have different barrier heights.3. The Schottky diode according to claim 2 , wherein the second metal layer has a greater barrier height than the first metal layer.4. The Schottky diode according to claim 1 , wherein a distance (D gap) is provided between the second metal layer and the additional Schottky contact adjacent to the second metal layer claim 1 , and between the additional Schottky contacts.5. The Schottky diode according to claim 1 , wherein each of the additional Schottky contacts has a same barrier height as the second metal layer ...

METHOD OF FABRICATING A SELF-ALIGNING DAMASCENE MEMORY STRUCTURE

A method of forming a memory cell is provided. The method includes forming a first pillar-shaped element that includes a first semiconductor material, forming a first opening self-aligned with the first pillar-shaped element, and depositing a second semiconductor material in the first opening to form a second pillar-shaped element above the first pillar-shaped element. Other aspects are also provided. 1. A method of forming a memory cell , the method comprising:forming a first pillar-shaped element comprising a first semiconductor material;forming a first opening self-aligned with the first pillar-shaped element; anddepositing a second semiconductor material in the first opening to form a second pillar-shaped element above the first pillar-shaped element.2. The method of claim 1 , wherein the first semiconductor material comprises N-type semiconductor material claim 1 , and the second semiconductor material comprises P-type semiconductor material.3. The method of claim 1 , wherein the first semiconductor material comprises P-type semiconductor material claim 1 , and the second semiconductor material comprises N-type semiconductor material.4. The method of claim 1 , wherein forming the first pillar shaped element comprises:depositing the first semiconductor material over a substrate;depositing a first sacrificial material over the first semiconductor material; andpatterning and etching the first sacrificial material and the first semiconductor material to form the first pillar shaped element.5. The method of claim 4 , wherein the first sacrificial material comprises a dielectric material.6. The method of claim 4 , wherein the first sacrificial material comprises SiN.7. The method of claim 1 , wherein the first pillar-shaped element further comprises first sacrificial material claim 1 , and wherein forming the first opening comprises:depositing an insulating material on the first pillar-shaped element; andremoving the first sacrificial material to form the first ...

SUPER-JUNCTION SCHOTTKY OXIDE PIN DIODE HAVING THIN P-TYPE LAYERS UNDER THE SCHOTTKY CONTACT

A semiconductor chip, which includes an n-type substrate, over which an n-type epitaxial layer having trenches introduced into the epitaxial layer and filled with p-type semiconductor is situated, the trenches each having a heavily doped p-type region on their upper side, the n-type substrate being situated in such a manner, that an alternating sequence of n-type regions having a first width and p-type regions having a second width is present; a first metallic layer, which is provided on the front side of the semiconductor chip, forms an ohmic contact with the heavily doped p-type regions and is used as an anode electrode; a second metallic layer, which is provided on the back side of the semiconductor chip, constitutes an ohmic contact and is used as a cathode electrode; a dielectric layer provided, in each instance, between an n-type region and an adjacent p-type region, as well as p-type layers provided between the n-type regions and the first metallic layer. 1. A semiconductor chip , comprising:{'sup': +', '+, 'an n-type substrate, over which an n-type epitaxial layer having trenches that are introduced into the epitaxial layer and filled with p-type semiconductor material, is situated, the trenches each having a highly doped p-type region on an upper side, and the n-type substrate being situated in such a manner that an alternating sequence of n-type regions having a first width and p-type regions having a second width is present;'}a first metallic layer provided on a front side of the semiconductor chip, which forms an ohmic contact with heavily doped p-type regions and is used as an anode electrode; anda second metallic layer provided on a back side of the semiconductor chip, the second metallic layer constituting an ohmic contact and is used as a cathode electrode, and in each instance, a dielectric layer is provided between an n-type region and an adjacent p-type region;wherein in each instance, a p-type layer is provided between each n-type region and the ...

DEVICES AND METHODS RELATED TO ELECTROSTATIC DISCHARGE PROTECTION BENIGN TO RADIO-FREQUENCY OPERATION

Disclosed are systems, devices and methods for providing electrostatic discharge (ESD) protection for integrated circuits. In some implementations, first and second conductors with ohmic contacts on an intrinsic semiconductor region can function similar to an x-i-y type diode, where each of x and y can be n-type or p-type. Such a diode can be configured to turn on under selected conditions such as an ESD event. Such a structure can be configured so as to provide an effective ESD protection while providing little or substantially nil effect on radio-frequency (RF) operating properties of a device. 1. A device , comprising:a semiconductor substrate having an intrinsic region;a circuit disposed on the semiconductor substrate;a first conductor disposed relative to the intrinsic region and electrically connected to the circuit; anda second conductor disposed relative to the intrinsic region and the first conductor, the second conductor configured so that a potential difference greater than a selected value between the first and second conductors results in a conduction path through the intrinsic region between the first and second conductors.2. The device of wherein the substrate further includes an insulating region disposed between the first and second conductors and above the intrinsic region so that the conduction path through the intrinsic region is away from a surface of the substrate.3. The device of wherein each of the first and second conductors is formed from metal such that the conduction path includes a metal-semiconductor-metal junction.4. The device of wherein the metal-semiconductor-metal junction includes a first turn-on voltage for conduction along a first direction between the first and second conductors claim 5 , and a second turn-on voltage for conduction along a second direction between the first and second conductors.5. The device of wherein the magnitude of the first turn-on voltage is lower than the magnitude of the second turn-on voltage.6. The ...

SEMICONDUCTOR DEVICE

A semiconductor device that can achieve a high-speed operation at a time of switching, and the like. The semiconductor device includes: a p-type buried layer buried within an n-type semiconductor layer; and a p-type surface layer formed in a central portion of each of cells. In a contact cell, the p-type buried layer is in contact with the p-type surface layer. The semiconductor device further includes: a p-type contact layer formed on the p-type surface layer of the contact cell; and an anode electrode provided on the n-type semiconductor layer. The anode electrode forms a Schottky junction with the n-type semiconductor layer and forms an ohmic junction with the p-type contact layer. 1. A semiconductor device including a cell array in which first cells are arranged and second cells are interspersed around the arrangement of the first cells , said semiconductor device comprising:a semiconductor layer having a first conductive type, said semiconductor layer being epitaxially formed on a semiconductor substrate having the first conductive type;a buried layer made of a semiconductor having a second conductive type, said buried layer being buried within said semiconductor layer, said buried layer being provided in a peripheral portion of said first cell and provided throughout an entire region of said second cell;at least one of a first surface layer made of a semiconductor having the second conductive type and a contact layer made of a semiconductor having the second conductive type, said first surface layer being formed in a central portion of said second cell on a surface of said semiconductor layer, said contact layer being formed in a central portion of said second cell on the surface of said semiconductor layer; anda second surface layer made of a semiconductor having the second conductive type, said second surface layer being formed in a central portion of said first cell on the surface of said semiconductor layer,whereinin said second cell, said buried layer is ...

NITRIDE SEMICONDUCTOR DEVICE

According to one embodiment, a nitride semiconductor device including a device region and a guard ring formation region surrounding the device region, the nitride semiconductor device includes a first nitride semiconductor layer provided in the device region and the guard ring formation region; a second nitride semiconductor layer provided on the first nitride semiconductor layer and forming a hetero-junction with the first nitride semiconductor layer; and a shielding layer provided on the second nitride semiconductor layer in the guard ring formation region and electrically protecting the device region. A two-dimensional electron gas is present near an interface between the first nitride semiconductor layer and the second nitride semiconductor layer within the first nitride semiconductor layer below the shielding layer, and the shielding layer is in ohmic contact with the two-dimensional electron gas. 1. A nitride semiconductor device including a device region and a guard ring formation region surrounding the device region , the nitride semiconductor device comprising:a first nitride semiconductor layer provided in the device region and the guard ring formation region;a second nitride semiconductor layer provided on the first nitride semiconductor layer and forming a hetero-junction with the first nitride semiconductor layer; anda shielding layer provided on the second nitride semiconductor layer in the guard ring formation region and electrically protecting the device region,wherein a two-dimensional electron gas is present near an interface between the first nitride semiconductor layer and the second nitride semiconductor layer within the first nitride semiconductor layer below the shielding layer, andthe shielding layer is in ohmic contact with the two-dimensional electron gas.2. The device according to claim 1 , wherein the device region is surrounded by the shielding layer and the two-dimensional electron gas.3. The device according to claim 1 , further ...

NITRIDE SEMICONDUCTOR SCHOTTKY DIODE AND METHOD FOR MANUFACTURING SAME

According to an embodiment, a nitride semiconductor Schottky diode includes a first layer including a first nitride semiconductor and a second layer provided on the first layer and including a second nitride semiconductor having a wider band gap than the first nitride semiconductor. The diode also includes an ohmic electrode provided on the second layer and a Schottky electrode provided on the second layer. The second layer includes a region containing an acceptor in the vicinity of the Schottky electrode between the Schottky electrode and the ohmic electrode. 1. A nitride semiconductor Schottky diode comprising:a first layer including a first nitride semiconductor;a second layer provided on the first layer and including a second nitride semiconductor having a wider band gap than the first nitride semiconductor;an ohmic electrode provided on the second layer; anda Schottky electrode provided on the second layer,the second layer including a region containing an acceptor in the vicinity of the Schottky electrode between the Schottky electrode and the ohmic electrode.2. The diode according to claim 1 , wherein the acceptor is fluorine.3. The diode according to claim 1 , wherein the first layer and the second layer are grown in a vertical direction with respect to a (0001) plane.4. The diode according to claim 1 , wherein a thickness of the region containing the acceptor is ½ or less of a thickness of the second layer.5. The diode according to claim 1 , wherein the region containing the acceptor is provided in the vicinity of a surface of the second layer.6. The diode according to claim 1 , wherein a width of the region containing the acceptor is ½ or less of an interval between the Schottky electrode and the ohmic electrode.7. The diode according to claim 1 , wherein the region containing the acceptor is provided in contact with the Schottky electrode.8. The diode according to claim 1 , wherein the first layer is GaN claim 1 , and the second layer is AlGaN.9. The diode ...

TRENCHED SEMICONDUCTOR STRUCTURE

A trenched semiconductor structure comprises a semiconductor substrate, an epitaxial layer, an ion implantation layer, a termination region dielectric layer, an active region dielectric layer, and a first polysilicon layer. The epitaxial layer doped with impurities of a first conductive type is formed on the semiconductor substrate. A plurality of active region trenches and a termination region trench are formed in the epitaxial layer. The ion implantation layer is formed in the active region trenches by doping impurities of a second conductive type. The termination region dielectric layer covers the termination region trench. The active region dielectric layer covers the ion implantation region. The first polysilicon layer covers the active region dielectric layer and fills the active region trenches. The depth of the termination region trench is greater than that of the active region trenches and close to that of the depletion region under reverse breakdown. 1. A trenched semiconductor structure , comprising:a semiconductor substrate doped with impurities of a first conductive type having a first impurity concentration;an epitaxial layer doped with impurities of the first conductive type of a second impurity concentration, formed on the semiconductor substrate;a plurality of active region trenches, formed in the epitaxial layer;at least a termination region trench, formed in the epitaxial layer and away from the active region trenches;an ion implantation layer, formed in a bottom of the active region trenches by doping impurities of a second conductive type ;a termination region dielectric layer, covering the termination region trench;an active region dielectric layer, covering the ion implantation region in the active region trenches; anda first polysilicon layer, covering the active region dielectric layer and filling the active region trenches;wherein, the first impurity concentration is greater than the second impurity concentration, and a depth of the ...

SEMICONDUCTOR DIODE AND METHOD OF MANUFACTURE

A diode () is disclosed having improved efficiency, smaller form factor, and reduced reverse biased leakage current. Schottky diodes () are formed on the sidewalls () of a mesa region (). The mesa region () is a cathode of the Schottky diode (). The current path through the mesa region () has a lateral and a vertical current path. The diode () further comprises a MOS structure (), p-type regions (), MOS structures (), and p-type regions (). MOS structure () with the p-type regions () pinch-off the lateral current path under reverse bias conditions. P-type regions (), MOS structures (), and p-type regions () each pinch-off the vertical current path under reverse bias conditions. MOS structure () and MOS structures () reduce resistance of the lateral and vertical current path under forward bias conditions. The mesa region () can have a uniform or non-uniform doping concentration. 114-. (canceled)15. A method of forming a semiconductor device comprising the steps of:forming more than one trench to a first depth in a semiconductor substrate to form at least one mesa region of a first conductivity type;placing dopant of a second conductivity type into a sidewall of the at least one mesa region to form a first region of the second conductivity type, where the dopant is located a first predetermined distance below a major surface of the at least one mesa region;forming a barrier metal overlying a portion of the sidewall of the at least one mesa region to form a Schottky diode; andforming a MOS structure overlying the major surface of the at least one mesa region, where the gate of the MOS structure is coupled to the barrier metal.16. The method of further including the steps of:forming an insulating layer overlying the major surface of the at least one mesa region;forming an insulating layer overlying sidewalls of the at least one mesa region to a first depth;exposing major surfaces of the more than one trench;forming the more than one trench to a second depth;forming an ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a semiconductor layer and a Schottky electrode, a Schottky junction being formed between the semiconductor layer and the Schottky electrode. The Schottky electrode includes a metal part containing a metal, a Schottky junction being formed between the semiconductor layer and the metal part; and a nitride part around the metal part, the nitride part containing a nitride of the metal, and a Schottky junction being formed between the semiconductor layer and the nitride part.

SCHOTTKY BARRIER DIODE HAVING A TRENCH STRUCTURE

A TMBS diode is disclosed. In an active portion and voltage withstanding structure portion of the diode, an end portion trench surrounds active portion trenches. An active end portion which is an outer circumferential side end portion of an anode electrode is in contact with conductive polysilicon inside the end portion trench. A guard trench is separated from the end portion trench and surrounds it. A field plate provided on an outer circumferential portion of the anode electrode is separated from the anode electrode, and contacts both part of a surface of n-type drift layer in a mesa region between the end portion trench and the guard trench and the conductive polysilicon formed inside the guard trench. The semiconductor device has high withstand voltage without injection of minority carriers, and relaxed electric field intensity of the trench formed in an end portion of an active portion. 1. A semiconductor device comprising:a cathode layer made of a first conductivity type semiconductor substrate;a drift layer provided on one principal surface of the cathode layer and made of a first conductivity type semiconductor substrate lower in concentration than the cathode layer;at least one first trench and an end portion trench provided in an upper surface of the drift layer so that the first trench is surrounded by the end portion trench;a first conductor embedded in each of the first trench and the end portion trench through an insulating film;an anode electrode provided on the upper surface of the drift layer so that the anode electrode is in contact with the first conductor, and that a Schottky barrier junction is formed between the anode electrode and the drift layer; anda cathode electrode provided on the other principal surface of the cathode layer, wherein:an outer circumferential side end portion of the anode electrode is in contact with the first conductor of the end portion trench;a field plate is provided separately from the anode electrode;a second trench ...

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES

A method of manufacturing a semiconductor device is disclosed. The method includes forming a first trench and a second trench in an n-type substrate surface, the first trenches being spaced apart from each other, the second trench surrounding the first trenches, the second trench being wider than the first trench. The method also includes forming a gate oxide film on the inner surfaces of the first and second trenches, and depositing an electrically conductive material to the thickness a half or more as large as the first trench width. The method further includes removing the electrically conductive material using the gate oxide film as a stopper layer, forming an insulator film thicker than the gate oxide film, and polishing the insulator film by CMP for exposing the n-type substrate and the electrically conductive material in the first trench. 1. A semiconductor device , comprising:a semiconductor substrate of a first conductivity type;at least one active section trench; anda ring-shaped edge termination trench spaced apart from a nearest one of the at least one active section trench for a predetermined spacing by a mesa region;wherein a height of an upper surface of an insulating film buried in the ring-shaped edge termination trench is substantially the same as the height of an exposed surface of the mesa region.2. The semiconductor device of claim 1 , wherein the ring-shaped edge termination trench is deeper than the at least one active section trench.3. The semiconductor device of claim 1 , wherein the at least one active section trench includes a plurality of active section trenches claim 1 , and a distance between an end portion of one of the plurality of active section trenches and the ring-shaped edge termination trench is narrower than a distance between the plurality of active section trenches. This application is a divisional of application Ser. No. 13/294,169, filed on Nov. 10, 2011. Furthermore, this application claims the benefit of priority of ...

Narrow active cell ie type trench gate igbt and a method for manufacturing a narrow active cell ie type trench gate igbt

In an equal width active cell IE type IGBT, a wide active cell IE type IGBT, and the like, an active cell region is equal in trench width to an inactive cell region, or the trench width of the inactive cell region is narrower. Accordingly, it is relatively easy to ensure the breakdown voltage. However, with such a structure, an attempt to enhance the IE effect entails problems such as further complication of the structure. The present invention provides a narrow active cell IE type IGBT having an active cell two-dimensional thinned-out structure, and not having a substrate trench for contact.

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a first type semiconductor layer doped with an N type ion, a second type semiconductor layer formed over the first type semiconductor layer, and a silicon germanium (SiGe) layer doped with a P type ion formed over the second type semiconductor layer. 1. A semiconductor device , comprising:a first type semiconductor layer doped with an N type ion;a second type semiconductor layer formed over the first type semiconductor layer; anda silicon germanium (SiGe) layer doped with a P type ion formed over the second type semiconductor layer.2. The semiconductor device of claim 1 , wherein the first type semiconductor layer and the SiGe layer are crystallized by a spike rapid thermal annealing (RTA) process.3. The semiconductor device of claim 2 , further comprising a diffusion barrier layer interposed between the first type semiconductor layer and the second type semiconductor layer.4. The semiconductor device of claim 1 , wherein Ge content of the SiGe layer is in a range of 5% to 50%.5. The semiconductor device of claim 1 , wherein a top doping concentration of the P type ion in the SiGe layer is in a range of 1E19 atoms/cmto 1E22 atoms/cm.6. The semiconductor device of claim 1 , wherein a bottom doping concentration of the N type ion in the first type semiconductor layer is in a range of 1E19 atoms/cmto 1E22 atoms/cm.7. The semiconductor device of claim 1 , wherein the second type semiconductor layer is an intrinsic semiconductor layer.8. The semiconductor device of claim 1 , further comprising a diffusion barrier layer interposed between the first type semiconductor layer and the second type semiconductor layer.9. A method of fabricating a semiconductor device claim 1 , the method comprising:forming a first type semiconductor layer doped with an N type ion over a semiconductor substrate;forming a second type semiconductor layer over the first type semiconductor layer; ...

Electrical Device and Method for Manufacturing Same

An electrical device includes a first layer, a second layer and an intrinsic layer. The first layer is of a first conductivity type, wherein the second layer is of a second conductivity type opposite to the first conductivity type. The intrinsic layer is arranged between the first and the second layer and has a reduced thickness at at least one portion. An area of the at least one portion is less than 50% of an active area in which the first and second layer face each other.

PROTECTIVE STRUCTURE

A protective structure may include: a semiconductor substrate having a doping of a first conductivity type; a semiconductor layer having a doping of a second conductivity type arranged at a surface of the semiconductor substrate; a buried layer having a doping of the second conductivity type arranged in a first region of the semiconductor layer and at the junction between the semiconductor layer and the semiconductor substrate; a first dopant zone having a doping of the first conductivity type arranged in the first region of the semiconductor layer above the buried layer; a second dopant zone having a doping of the second conductivity type arranged in a second region of the semiconductor layer; an electrical insulation arranged between the first region and the second region of the semiconductor layer; and a common connection device for the first dopant zone and the second dopant zone. 1. A protective structure comprising:a semiconductor substrate having a doping of a first conductivity type;a semiconductor layer having a doping of a second conductivity type arranged at a surface of the semiconductor substrate;a buried layer having a doping of the second conductivity type arranged in a first region of the semiconductor layer and at the junction between the semiconductor layer and the semiconductor substrate;a first dopant zone having a doping of the first conductivity type arranged in the first region of the semiconductor layer above the buried layer;a second dopant zone having a doping of the second conductivity type arranged in a second region of the semiconductor layer;an electrical insulation arranged between the first region and the second region of the semiconductor layer; anda common connection device for the first dopant zone and the second dopant zone.2. The protective structure as claimed in claim 1 , wherein the semiconductor layer has a dopant concentration k≦1×10cm.3. The protective structure as claimed in claim 1 , wherein the semiconductor layer has a ...

DOUBLE-RECESSED TRENCH SCHOTTKY BARRIER DEVICE

A Schottky barrier device includes a semiconductor substrate, a first contact metal layer, a second contact metal layer and an insulating layer. The semiconductor substrate has a first surface, and plural trenches are formed on the first surface. Each trench includes a first recess having a first depth and a second recess having a second depth. The second recess extends down from the first surface while the first recess extends down from the second recess. The first contact metal layer is formed on the second recess. The second contact metal layer is formed on the first surface between two adjacent trenches. The insulating layer is formed on the first recess. A first Schottky barrier formed between the first contact metal layer and the semiconductor substrate is larger than a second Schottky barrier formed between the second contact metal layer and the semiconductor substrate. 1. A Schottky barrier device , comprising:a semiconductor substrate, having a first surface and a second surface positioned oppositely, and a plurality of trenches formed on the first surface, each trench comprising a first recess having a first depth and a second recess having a second depth, the second recess extending down from the first surface, the first recess extending down from the second recess, and the first depth larger than the second depth;a first contact metal layer at least formed on a surface of the second recess;a second contact metal layer formed on the first surface and between two adjacent trenches; andan insulating layer formed on a surface of the first recess,wherein a first Schottky barrier is formed between the first contact metal layer and the semiconductor substrate, a second Schottky barrier is formed between the second contact metal layer and the semiconductor substrate, and the first Schottky barrier is larger than the second Schottky barrier.2. The Schottky barrier device according to claim 1 , wherein a material of the semiconductor substrate comprises silicon ...

Schottky-barrier device with locally planarized surface and related semiconductor product

The present disclosure is related to alleviation of at least some of the above drawbacks of the prior art and to provide an improved alternative to the prior art. Generally, at least some of the embodiments are related to a high voltage power conversion semiconductor device, in particular a SiC Schottky-barrier power rectifier device, having a surface (of the drift layer) with improved smoothness. Further, at least some of the embodiments are related to a method of manufacturing a power rectifier device with reduced leakage currents.

Semiconductor Arrangement Having a Schottky Diode

A semiconductor assemblage of a super-trench Schottky barrier diode (STSBD) made up of an n substrate, an n-epilayer, trenches etched into the n-epilayer that have a width and a distance from the n substrate, mesa regions between the adjacent trenches having a width, a metal layer on the front side of the chip that is a Schottky contact and serves as an anode electrode, and a metal layer on the back side of the chip that is an ohmic contact and serves as a cathode electrode, wherein multiple Schottky contacts having a width or distance and a distance between the Schottky contacts, and between the Schottky contact as anode electrode and the first Schottky contact, are located on the trench wall. 119-. (canceled)20. A semiconductor assemblage , comprising:{'sup': +', '+, 'a super-trench Schottky barrier diode (STSBD) having an n substrate, an n-epilayer, trenches etched into the n-epilayer that have a width and a distance from the n substrate, mesa regions between the adjacent trenches having a width, a metal layer on a front side of the chip that is a Schottky contact and serves as an anode electrode, a metal layer on a back side of the chip that is an ohmic contact and serves as a cathode electrode, multiple Schottky contacts having a width or distance and a distance between the Schottky contacts, and between the Schottky contact as anode electrode and the first Schottky contact, being located on the trench wall.'}21. The semiconductor assemblage of claim 20 , wherein the Schottky contacts are floated on the trench wall.22. The semiconductor assemblage of claim 20 , wherein the metal layer on the front side of the chip claim 20 , which is a Schottky contact and serves as an anode electrode claim 20 , covers the trench wall up to a depth.23. The semiconductor assemblage of claim 20 , wherein the metal layer on the front side of the chip fills up the trenches up to a depth.24. The semiconductor assemblage of claim 20 , wherein the last floated Schottky contact covers ...

Large Bit-Per-Cell Three-Dimensional Mask-Programmable Read-Only Memory

A large bit-per-cell three-dimensional mask-programmable read-only memory (3D-MPROM B ) is disclosed. It can achieve large bit-per-cell (e.g. 4-bpc or more). 3D-MPROM B can be realized by adding resistive layer(s) or resistive element(s) to the memory cells.

METHODS OF MANUFACTURING THE GALLIUM NITRIDE BASED SEMICONDUCTOR DEVICES

Gallium nitride (GaN) based semiconductor devices and methods of manufacturing the same. The GaN-based semiconductor device may include a heterostructure field effect transistor (HFET) or a Schottky diode, arranged on a heat dissipation substrate. The HFET device may include a GaN-based multi-layer having a recess region; a gate arranged in the recess region; and a source and a drain that are arranged on portions of the GaN-based multi-layer at two opposite sides of the gate (or the recess region). The gate, the source, and the drain may be attached to the heat dissipation substrate. The recess region may have a double recess structure. While such a GaN-based semiconductor device is being manufactured, a wafer bonding process and a laser lift-off process may be used. 1. A gallium nitride (GaN) based semiconductor device comprising:a heat dissipation substrate; anda heterostructure field effect transistor (HFET) device arranged on the heat dissipation substrate, a GaN-based multi-layer having a recess region close to the heat dissipation layer;', 'a gate arranged in the recess region; and', 'a source and a drain that are arranged on portions of the GaN-based multi-layer at two opposite sides of the gate, and, 'wherein the HFET device comprisesthe gate, the source, and the drain are attached to the heat dissipation substrate.2. The GaN-based semiconductor device of claim 1 , wherein the recess region has a double recess structure.3. The GaN-based semiconductor device of claim 1 , wherein the GaN-based multi-layer comprises a 2-dimensional electron gas (2DEG) layer.4. The GaN-based semiconductor device of claim 1 , wherein the GaN multi-layer comprises an AlGN layer and an AlGaN layer which are sequentially disposed from the heat dissipation substrate claim 1 , and{'sub': y', '1-y, 'in the AlGN layer, 0.1≦y≦0.6, and'}{'sub': x', '1-, 'in the AlGaN layer, 0≦x<0.01.'}5. The GaN-based semiconductor device of claim 4 , wherein the GaN-based multi-layer further comprises a ...

SEMICONDUCTOR STRUCTURE FOR ANTENNA SWITCHING CIRCUIT AND MANUFACTURING METHOD THEREOF

A manufacturing method for antenna switching circuit includes the following steps of: providing a GaAs wafer, which includes a capping layer; disposing an isolation layer to the GaAs wafer for forming a device area; and disposing a gate metal on the capping layer within the device area, wherein an interface between the gate metal and the capping layer forms a Schottky contact, and the Schottky contact is parallel connected with an impedance. The present invention also discloses a semiconductor structure for antenna switching circuit. 1. A manufacturing method of a semiconductor structure for antenna switching circuit , comprising steps of:providing a GaAs wafer having a capping layer;disposing an isolation layer to the GaAs wafer to form a device area; anddisposing a gate metal to the capping layer within the device area, wherein an interface between the gate metal and the capping layer forms a Schottky contact that is parallel connected to an impedance.2. The manufacturing method as recited in claim 1 , wherein the GaAs wafer includes a buffer layer claim 1 , a channel layer claim 1 , a space layer claim 1 , a donor layer and the capping layer.3. The manufacturing method as recited in claim 1 , wherein the isolation layer is made by insulating material and disposed to the GaAs wafer by an ion implantation.4. The manufacturing method as recited in claim 1 , wherein the gate metal is disposed on the capping layer by a vapor deposition.5. The manufacturing method as recited in claim 1 , further comprising steps of:disposing a first ohmic layer and a second ohmic layer on the capping layer; anddisposing a first metal layer on the first ohmic layer and the gate metal, and disposing a second metal on the second ohmic layer.6. A semiconductor structure for an antenna switching circuit claim 1 , comprising:a buffer layer;a channel layer disposed on the channel layer;a space layer disposed on the channel layer;a donor layer disposed on the space layer;a capping layer ...

RADIO FREQUENCY ISOLATION FOR SOI TRANSISTORS

According to one example embodiment, a structure includes at least one SOI (semiconductor-on-insulator) transistor situated over a buried oxide layer, where the buried oxide layer overlies a bulk substrate. The structure further includes an electrically charged field control ring situated over the buried oxide layer and surrounding the at least one SOI transistor. A width of the electrically charged field control ring is greater than a thickness of the buried oxide layer. The electrically charged field control ring reduces a conductivity of a surface portion of the bulk substrate underlying the field control ring, thereby reducing RF coupling of the at least one SOI transistor through the bulk substrate. The structure further includes an isolation region situated between the electrically charged field control ring and the at least one SOI transistor. A method to achieve and implement the disclosed structure is also provided. 1. A method for reducing RF coupling of at least one SOI (semiconductor-on-insulator) transistor through a bulk substrate of an SOI substrate , said method comprising:forming or providing a field control ring in a silicon layer, above said SOI substrate, said field control ring surrounding said at least one SOI transistor;providing a bias voltage; andcoupling the field control ring to the bias voltage to provide an electrical charge to said field control ring to generate an electrical field that forms a resistive surface portion on said bulk substrate underlying said field control ring to reduce RF coupling of said at least one SOI transistor through said bulk substrate.2. The method of wherein said field control ring includes a conductive material selected from the group consisting of silicon claim 1 , polysilicon claim 1 , and a metal.3. The method of wherein a width of said field control ring is greater than a thickness of a buried oxide layer situated over said bulk substrate.4. The method of further comprising doping the field control ring ...

SCHOTTKY DIODE

A Schottky diode has: a semiconductor layer stack including a GaN layer formed over a substrate and an AlGaN layer formed on the GaN layer and having a wider bandgap than the GaN layer; an anode electrode and a cathode electrode which are formed at an interval therebetween on the semiconductor layer stack; and a block layer formed in a region between the anode electrode and the cathode electrode so as to contact the AlGaN layer. A part of the anode electrode is formed on the block layer so as not to contact the surface of the AlGaN layer. The barrier height between the anode electrode and the block layer is greater than that between the anode electrode and the AlGaN layer. 1. A Schottky diode , comprising:a substrate;a semiconductor layer stack including a first nitride semiconductor layer formed over the substrate and a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a wider bandgap than the first nitride semiconductor layer;an anode electrode and a cathode electrode which are formed at an interval therebetween on the semiconductor layer stack; anda block layer formed in a region between the anode electrode and the cathode electrode so as to contact the second nitride semiconductor layer, whereina part of the anode electrode is formed on the block layer so as not to contact a surface of the second nitride semiconductor layer, anda barrier height between the anode electrode and the block layer is greater than that between the anode electrode and the second nitride semiconductor layer.2. The Schottky diode of claim 1 , whereinthe semiconductor layer stack includes multiple ones of the first nitride semiconductor layer and multiple ones of the second nitride semiconductor layer, andthe first nitride semiconductor layers and the second nitride semiconductor layers are alternately stacked.3. The Schottky diode of claim 1 , whereinthe semiconductor layer stack has a stepped portion formed by removing a part of the second ...

SILICON CARBIDE SCHOTTKY DIODE

A SiC Schottky diode which includes a Schottky barrier formed on a silicon face 4H-SiC body. 1a SiC substrate of one conductivity;a silicon face SiC epitaxial body of said one conductivity formed on a first surface of a said SiC substrate;a Schottky metal barrier formed on said silicon face of said SiC epitaxial body;a back power electrode on a second surface of said SiC substrate opposite said first surface of said SiC substrate.. A semiconductor device, comprising: This application is a continuation of and claims the benefit of co-pending, commonly-owned U.S. patent application Ser. No. 11/581,536, with Attorney Docket No. VISH-IR257, filed on Oct. 16, 2006, by Giovanni Richieri, and titled “Silicon carbide schottky diode,” which claims the benefit of and priority to the provisional patent application, Ser. No. 60/728,728, with Attorney Docket No. VISH-IR257.Pro, filed on Oct. 20, 2005, by Giovanni Richieri, and titled “Silicon carbide schottky diode,” each of which are hereby incorporated by reference in their entirety.The present invention relates to Schottky diodes and in particular to SiC Schottky diodes.Although the main intrinsic parameters in Silicon Carbide material have not been exhaustively studied, several experimental and theoretical studies have been performed in recent years in order to better describe the current transport in ohmic and rectifying contact on SiC.It has been known that in Schottky diodes the metal semiconductor interface (MST) between the Schottky barrier metal and the semiconductor plays a crucial role in the electrical performance of electronic devices. Many factors can worsen the performance of the MSI in a Schottky diode. For example, the quality of the semiconductor surface prior to the deposition of the Schottky barrier metal can cause the device to exhibit characteristics that are different from the ideal characteristics.Current-voltage (I-V) and capacitance-voltage (C-V) characterizations are useful methods for determining the ...

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

A semiconductor device includes a substrate including a first region and a second region, a trench-gate transistor in the first region, the trench-gate transistor including a first trench in the substrate, a gate filling at least part of the first trench, and a source in the substrate and on each sidewall of the first trench, a first field diffusion junction in the second region, an interlayer insulating film on the substrate, the interlayer insulating film covering the trench-gate transistor and the first field diffusion junction, a first contact in the first region, the first contact passing through the interlayer insulating film and contacting the source, and a second contact in the second region, the second contact passing through the interlayer insulating film and contacting the first field diffusion junction, the first contact and the second contact having an equal height and including a same material. 1. A semiconductor device , comprising:a substrate including a first region and a second region; a first trench in the substrate,', 'a gate filling at least part of the first trench, and', 'a source in the substrate and on each sidewall of the first trench;, 'a trench-gate transistor in the first region, the trench-gate transistor includinga first field diffusion junction in the second region;an interlayer insulating film on the substrate, the interlayer insulating film covering the trench-gate transistor and the first field diffusion junction;a first contact in the first region, the first contact passing through the interlayer insulating film and contacting the source; anda second contact in the second region, the second contact passing through the interlayer insulating film and contacting the first field diffusion junction, the first contact and the second contact having an equal height and including a same material.2. The semiconductor device as claimed in claim 1 , wherein the first contact and the second contact are fabricated simultaneously.3. The ...

Device-Manufacturing Scheme for Increasing the Density of Metal Patterns in Inter-Layer Dielectrics

A method includes forming a transistor at a surface of a semiconductor substrate, wherein the step of forming the transistor comprises forming a gate electrode, and forming a source/drain region adjacent the gate electrode. First metal features are formed to include at least portions at a same level as the gate electrode. Second metal features are formed simultaneously, and are over and contacting the first metal features. A first one of the second metal features is removed and replaced with a third metal feature, wherein a second one of the second metal features is not removed. A fourth metal feature is formed directly over and contacting the gate electrode, wherein the third and the fourth metal features are formed using a same metal-filling process.

DIODE, SEMICONDUCTOR DEVICE, AND MOSFET

Disclosed is a technique capable of reducing loss at the time of switching in a diode. A diode disclosed in the present specification includes a cathode electrode, a cathode region made of a first conductivity type semiconductor, a drift region made of a low concentration first conductivity type semiconductor, an anode region made of a second conductivity type semiconductor, an anode electrode made of metal, a barrier region formed between the drift region and the anode region and made of a first conductivity type semiconductor having a concentration higher than that of the drift region, and a pillar region formed so as to connect the barrier region to the anode electrode and made of a first conductivity type semiconductor having a concentration higher than that of the barrier region. The pillar region and the anode are connected through a Schottky junction. 1. A diode comprising:a cathode electrode;a cathode region made of a first conductivity type semiconductor;a drift region made of a low concentration first conductivity type semiconductor;an anode region made of a second conductivity type semiconductor;an anode electrode made of metal;a barrier region formed between the drift region and the anode region and made of a first conductivity type semiconductor having a concentration higher than that of the drift region; anda pillar region formed so as to connect the barrier region to the anode electrode and made of a first conductivity type semiconductor having a concentration higher than that of the barrier region,wherein the pillar region and the anode electrode are connected through a Schottky junction.2. The diode according to claim 1 , further comprising an electric field progress preventing region formed between the barrier region and the drift region and made of the second conductivity type semiconductor.3. The diode according to claim 1 , wherein a trench extending from the anode region to the drift region is formed claim 1 , anda trench electrode which is ...

Lateral diffusion metal oxide semiconductor transistor structure

A lateral diffusion metal-oxide-semiconductor (LDMOS) transistor structure comprises a barrier layer, a semiconductor layer, a source, a first drain and a guard ring. The barrier layer with a first polarity is disposed in a substrate. The semiconductor layer with a second polarity is disposed on the barrier layer. The source has a first polarity region and a second polarity region both formed in the semiconductor layer. The first drain is disposed in the semiconductor layer and has a drift region with the second polarity. The guard ring with the first polarity extends downward from a surface of the semiconductor layer in a manner of getting in touch with the barrier layer and to surround the source and the drain, and is electrically connected to the source.

RECTIFIER OF ALTERNATING-CURRENT GENERATOR FOR VEHICLE

In a rectifier device () for full-wave rectifying an output of a vehicle alternating-current generator (), a schottky barrier diode having a characteristic whose forward voltage drop with respect to a forward current is small and whose reverse leakage current is small, is used as a rectifier semiconductor element (),() constituting the rectifier device (). 1. A rectifier device of a vehicle alternating-current generator that performs full-wave rectification of an output of the vehicle alternating-current generator , wherein , as a rectifier semiconductor element constituting the rectifier device , a diode is used which has a characteristic whose forward voltage drop with respect to a forward current is smaller than that of a PN junction diode , and whose reverse leakage current is as small as the same level as that of the PN junction diode.2. The rectifier device of a vehicle alternating-current generator of claim 1 , wherein claim 1 , as the diode claim 1 , a schottky barrier diode having a junction barrier schottky structure is used so as to suppress the reverse leakage current.3. The rectifier device of a vehicle alternating-current generator of claim 2 , wherein the junction barrier schottky structure includes a plurality of P-type semiconductor regions formed under a schottky electrode claim 2 , so that PN junction portions are formed inside the schottky barrier diode. This invention relates to rectifier devices of alternating-current generators for on-vehicle use, and in particular, to rectifier devices of vehicle alternating-current generators in which schottky barrier diodes are used as semiconductor devices constituting the rectifier devices.is a circuit configuration diagram for showing an example of conventional rectifier device of a vehicle alternating-current generator.The conventional rectifier device with a vehicle alternating-current generator is configured with: an alternating-current generator comprising a field coil that is activated by a not ...

WIDE GAP SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A wide gap semiconductor device has a substrate and a Schottky electrode. The substrate is made of a wide gap semiconductor material and has a first conductivity type. The Schottky electrode is arranged on the substrate to be in contact therewith and is made of a single material. The Schottky electrode includes a first region having a first barrier height and a second region having a second barrier height higher than the first barrier height. The second region includes an outer peripheral portion of the Schottky electrode. Thus, a wide gap semiconductor device capable of achieving less leakage current and a method for manufacturing the same can be provided. 1. A wide gap semiconductor device , comprising:a substrate made of a wide gap semiconductor material and having a first conductivity type; anda Schottky electrode arranged on said substrate to be in contact therewith and made of a single material,said Schottky electrode including a first region having a first barrier height and a second region having a second barrier height higher than said first barrier height, andsaid second region including an outer peripheral portion of said Schottky electrode.2. The wide gap semiconductor device according to claim 1 , whereinsaid wide gap semiconductor material is silicon carbide.3. The wide gap semiconductor device according to claim 1 , whereina width of said second region in a direction in parallel to a main surface of said substrate and from said outer peripheral portion of said Schottky electrode toward a center is not smaller than 2 μm and not greater than 100 μm.4. The wide gap semiconductor device according to claim 1 , whereinsaid substrate includes a second conductivity type region in contact with said outer peripheral portion of said Schottky electrode.5. A method for manufacturing a wide gap semiconductor device claim 1 , comprising the steps of:preparing a substrate made of a wide gap semiconductor material and having a first conductivity type; andforming a ...

WIDE GAP SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

A wide gap semiconductor device includes a substrate and a Schottky electrode. The substrate formed of a wide gap semiconductor material has a main face, and includes a first-conductivity-type region and a second-conductivity-type region. The Schottky electrode is arranged adjoining the main face of the substrate. At the substrate, there is foamed a trench having a side face continuous with the main face and a bottom continuous with the side face. The Schottky electrode adjoins the first-conductivity-type region at the side face of the trench and the main face, and adjoins the second-conductivity-type region at the bottom of the trench. The side face of the trench is inclined relative to the main face of the substrate. 1. A wide gap semiconductor device comprising:a substrate formed of a wide gap semiconductor material, having a main face, and including a first-conductivity-type region and a second-conductivity-type region, anda Schottky electrode arranged adjoining said main face of said substrate,said substrate having a trench formed, said trench including a side face continuous with said main face, and a bottom continuous with said side face,said Schottky electrode adjoining said first-conductivity-type region at said side face of said trench and said main face, and adjoining said second-conductivity-type region at said bottom of said trench,said side face of said trench inclined relative to said main face of said substrate.2. The wide gap semiconductor device according to claim 1 , wherein said wide gap semiconductor material includes silicon carbide.3. The wide gap semiconductor device according to claim 1 , wherein an angle of said main face relative to said side face is greater than or equal to 50° and less than or equal to 85°.4. The wide gap semiconductor device according to claim 1 , whereinsaid trench includes a first trench and a second trench adjacent to each other,said second-conductivity-type region includes a first second-conductivity-type region ...

Tunable Schottky Diode

A device includes a semiconductor substrate, first and second electrodes supported by the semiconductor substrate, laterally spaced from one another, and disposed at a surface of the semiconductor substrate to form an Ohmic contact and a Schottky junction, respectively. The device further includes a conduction path region in the semiconductor substrate, having a first conductivity type, and disposed along a conduction path between the first and second electrodes, a buried region in the semiconductor substrate having a second conductivity type and disposed below the conduction path region, and a device isolating region electrically coupled to the buried region, having the second conductivity type, and defining a lateral boundary of the device. The device isolating region is electrically coupled to the second electrode such that a voltage at the second electrode during operation is applied to the buried region to deplete the conduction path region.

DIODE AND METHOD OF MANUFACTURING DIODE

A diode includes a first semiconductor layer configured by a compound semiconductor containing impurities of a first conductivity type; a high dislocation density region; a second semiconductor layer which is laminated on the first semiconductor layer, which is lower in a concentration of impurities in a region of a side of an interface with the first semiconductor layer than that of the first semiconductor layer, and which has an opening in which a portion which corresponds to the high dislocation density region is removed; an insulating film pattern which is provided to cover an inner wall of the opening; an electrode which is provided so as to cover the insulating film pattern and to contact the second semiconductor layer; and an opposing electrode which is provided to interpose the first semiconductor layer, the second semiconductor layer and the insulating film pattern between the electrode and the opposing electrode. 1. A diode comprising:a first semiconductor layer configured by a compound semiconductor containing impurities of a first conductivity type;a high dislocation density region which penetrates the first semiconductor layer in the film thickness direction;a second semiconductor layer which has a crystalline structure continuous with the first semiconductor layer, which is laminated on the first semiconductor layer, which is lower in a concentration of the impurities in a region of a side of an interface with the first semiconductor layer than that of the first semiconductor layer, and which has an opening in which a portion which corresponds to the high dislocation density region is removed such that the first semiconductor layer is in an exposed state;an insulating film pattern which is provided in a state of covering an inner wall including a base portion of the opening;an electrode which is provided so as to cover the insulating film pattern and to contact the second semiconductor layer; andan opposing electrode which is provided in a state of ...

SEMICONDUCTOR DEVICE COMPRISING A SCHOTTKY BARRIER DIODE

The present invention aims to enhance the reliability of a semiconductor device equipped with a Schottky barrier diode within the same chip, and its manufacturing technology. The semiconductor device includes an n-type n-well region formed over a p-type semiconductor substrate, an n-type cathode region formed in part thereof and higher in impurity concentration than the n-well region, a p-type guard ring region formed so as to surround the n-type cathode region, an anode conductor film formed so as to integrally cover the n-type cathode region and the p-type guard ring region and to be electrically coupled thereto, n-type cathode conduction regions formed outside the p-type guard ring region with each separation portion left therebetween, and a cathode conductor film formed so as to cover the n-type cathode conduction regions and to be electrically coupled thereto. The anode conductor film and the n-type cathode region are Schottky-coupled to each other. 116-. (canceled)17. A semiconductor device comprising:(a) a semiconductor substrate of a first conductivity type;(b) a first semiconductor region of a second conductivity type corresponding to a conductivity type opposite to the first conductivity type, the first semiconductor region being formed in the semiconductor substrate;(c) a second semiconductor region of the first conductivity type, the second semiconductor region being formed circularly in the semiconductor substrate within the first semiconductor region;(d) a third semiconductor region of the first conductivity type, the third semiconductor region being formed circularly in the semiconductor substrate within the second semiconductor region;(e) a first conductor film formed over the semiconductor substrate so as to integrally cover the first semiconductor region, the second semiconductor region, and the third semiconductor region provided thereinside and to be electrically coupled to the first semiconductor region and the third semiconductor region ...

Method of manufacturing vertical pin diodes

Disclosed is a vertical PIN diode having: an N-type layer; a cathode contact formed on a first portion of the N-type layer defining a cathode region; an intrinsic layer formed on a second portion of the N-type layer; a portion of a P-type layer formed on a first portion of the intrinsic layer and defining an anode region; an anode contact formed on the portion of the P-type layer defining the anode region; and a protection structure formed on a second portion of the intrinsic layer to laterally protect the portion of the P-type layer defining the anode region from an etching intended to expose the first portion of the N-type layer defining the cathode region, wherein the protection structure is formed by implanting ions in a further portion of the P-type layer, which laterally surrounds the portion of the P-type layer defining the anode region.

TRENCH SCHOTTKY RECTIFIER DEVICE AND METHOD FOR MANUFACTURING THE SAME

A trench Schottky rectifier device includes a substrate having a first conductivity type, a plurality of trenches formed in the substrate, and an insulating layer formed on sidewalls of the trenches. The trenches are filled with conductive structure. There is an electrode overlying the conductive structure and the substrate, and thus a Schottky contact forms between the electrode and the substrate. A plurality of embedded doped regions having a second conductivity type are formed in the substrate and located under the trenches. Each doped region and the substrate form a PN junction to pinch off current flowing toward the Schottky contact so as to suppress current leakage. 1. A trench Schottky rectifier device comprising:a substrate having a first conductivity type;a first plurality of trenches and a second plurality of trenches formed in the substrate;an insulating layer formed on sidewalls of the first plurality of trenches and the second plurality of trenches;a first plurality of conductive structures formed in the first plurality of trenches and a second plurality of conductive structures formed in the second plurality of trenches;an isolation layer covered on a first portion of the substrate;an electrode overlying the isolation layer, the first plurality of conductive structures, the second plurality of conductive structures and a second portion of the substrate, wherein a Schottky contact forms between the electrode and the second portion of the substrate; anda plurality of doped regions having a second conductivity type formed in the substrate and located under the first plurality of trenches and the second plurality of trenches, and in contact with the first plurality of conductive structures and the second conductive structures in the first plurality of trenches and the second plurality of trenches.2. The trench Schottky rectifier device according to claim 1 , wherein the trench Schottky rectifier device further comprises an adhesion layer disposed between ...

SEMICONDUCTOR DEVICE

According to one embodiment, a semiconductor device includes a first semiconductor region, a first electrode, a second semiconductor region, a third semiconductor region, a fourth semiconductor region, a fifth semiconductor region, and a second electrode. The first electrode forms a Schottky junction with the first region. The second region is provided between the first region and the first electrode. The third region is provided between the first region and the first electrode and forms an ohmic junction with the first electrode. The fourth region is provided between the first region and the third region. The fourth region has a higher impurity concentration than the first region. The fifth region is provided between the third region and the first electrode. The fifth region has a higher impurity concentration than the third region. The second electrode is provided on opposite side of the first region from the first electrode. 1. A semiconductor device comprising:a first semiconductor region of a first conductivity type;a first electrode forming a Schottky junction with the first semiconductor region;a second semiconductor region of a second conductivity type provided between the first semiconductor region and the first electrode;a third semiconductor region of the second conductivity type provided between the first semiconductor region and the first electrode, the third semiconductor region forming an ohmic junction with the first electrode;a fourth semiconductor region of the first conductivity type provided between the first semiconductor region and the third semiconductor region, the fourth semiconductor region having a higher impurity concentration than the first semiconductor region;a fifth semiconductor region of the second conductivity type provided between the third semiconductor region and the first electrode, the fifth semiconductor region having a higher impurity concentration than the third semiconductor region; anda second electrode provided on ...

TRENCH MOSFET WITH INTEGRATED SCHOTTKY BARRIER DIODE

A Schottky diode includes first and second trenches formed in a semiconductor layer where the first and second trenches are lined with a thin dielectric layer and filled partially with a trench conductor layer with the remaining portion being filled with a first dielectric layer. Well regions are formed spaced-apart in a top portion of the semiconductor layer between the first and second trenches. A Schottky metal layer is formed on a top surface of the semiconductor layer between the first and second trenches. The Schottky diode is formed with the Schottky metal layer as the anode and the semiconductor layer between the first and second trenches as the cathode. The trench conductor layer in the first and second trenches is electrically connected to the anode of the Schottky diode. In one embodiment, the Schottky diode is formed integrated with a trench field effect transistor on the same semiconductor substrate. 1. A Schottky diode comprising:a semiconductor substrate of a first conductivity type;a semiconductor layer of the first conductivity type and being lightly doped formed on the semiconductor substrate;first and second trenches formed in the semiconductor layer, the first and second trenches being lined with a thin dielectric layer, a bottom portion of each of the first and second trenches being filled with a trench conductor layer and a top portion of each of the first and second trenches being filled with a first dielectric layer;a plurality of well regions of a second conductivity type formed in a top portion of the semiconductor layer between the first trench and the second trench, the plurality of well regions being spaced apart in a longitudinal direction parallel to the longitudinal axis of the first and second trenches, the first dielectric layer filling each of the first and second trenches at least from a bottom surface of the well regions adjacent the trenches; anda Schottky metal layer formed on at least a top surface of the lightly doped ...

SCHOTTKY DIODE STRUCTURE

The invention provides a Schottky diode structure. An exemplary embodiment of a Schottky diode structure includes a semiconductor substrate having an active region. A first well region having a first conductive type is formed in the active region. A first doped region having the first conductive type is formed on the first well region. A first electrode is disposed on the active region, covering the first doped region. A second electrode is disposed on the active region, contacting to the first well region. A gate structure is disposed on the first well region. A second doped region, having a second conductive type opposite to the first conductive type, and is formed on the first well region. The gate structure and the second doped region are disposed between the first and second electrodes. 1. A Schottky diode structure , comprising:a semiconductor substrate having an active region;a first well region having a first conductive type formed in the active region;a first doped region having the first conductive type formed on the first well region;a first electrode disposed on the active region, covering the first doped region;a second electrode disposed on the active region, contacting to the first well region;a gate structure disposed on the first well region; anda second doped region, having a second conductive type opposite to the first conductive type, formed on the first well region, wherein the gate structure and the second doped region are disposed between the first and second electrodes.2. The Schottky diode structure as claimed in claim 1 , further comprising:an isolation region disposed in the first well region, having opposite sides respectively adjacent to the first doped region and the second doped region.3. The Schottky diode structure as claimed in claim 1 , wherein the second doped region is disposed within a boundary of the gate structure.4. The Schottky diode structure as claimed in claim 1 , wherein the first doped region is separated from the ...

Power Semiconductor Device Edge Structure

A semiconductor device having a first load terminal, a second load terminal and a semiconductor body is presented. The semiconductor body comprises an active region configured to conduct a load current between the first load terminal and the second load terminal and a junction termination region surrounding the active region. The semiconductor body includes a drift layer arranged within both the active region and the junction termination region and having dopants of a first conductivity type at a drift layer dopant concentration of equal to or less than 10cm; a body zone arranged in the active region and having dopants of a second conductivity type complementary to the first conductivity type and isolating the drift layer from the first load terminal; a guard zone arranged in the junction termination region and having dopants of the second conductivity type and being configured to extend a depletion region formed by a transition between the drift layer and the body zone; a field stop zone arranged adjacent to the guard zone, the field stop zone having dopants of the first conductivity type at a field stop zone dopant concentration that is higher than the drift layer dopant concentration by a factor of at least 2; a low doped zone arranged adjacent to the field stop zone, the low doped zone having dopants of the first conductivity type at a dopant concentration that is lower than the drift layer dopant concentration by a factor of at least 1.5, wherein the body zone, the guard zone, the field stop zone and the low doped zone are arranged in the semiconductor body such that they exhibit a common depth range (DR) of at least μm along a vertical extension direction (Z). 1. A semiconductor device having a first load terminal , a second load terminal and a semiconductor body , the semiconductor body comprising an active region configured to conduct a load current between the first load terminal and the second load terminal and a junction termination region surrounding the ...

TRENCHED AND IMPLANTED BIPOLAR JUNCTION TRANSISTOR

The present invention concerns a monolithically merged trenched-and-implanted Bipolar Junction Transistor (TI-BJT) with antiparallel diode and a method of manufacturing the same. Trenches are made in a collector, base, emitter stack downto the collector. The base electrode is formed on an implanted base contact region at the bottom surface of the trench. The present invention also provides for products produced by the methods of the present invention and for apparatuses used to perform the methods of the present invention. 1. A trenched-and-implanted bipolar junction transistor (TI-BJT) comprising:a drift layer of a second conductivity type;a channel layer of the second conductivity type formed on top of the drift layer;a base layer of a first conductivity type formed on top of the channel layer, wherein the base layer has a thickness which extends along a first direction, wherein the thickness is in the range of 0.02 to 2 microns;an emitter layer of the second conductivity type formed on top of the base layer, the emitter layer having a bottom surface located adjacent to the base layer and a top surface opposite the first bottom surface along the first direction; a first side surface, a second side surface, and a bottom surface, the first side surface, second side surface, and the bottom surface being substantially planar;', 'the first and the second side surfaces spaced apart along a second direction, the second direction being perpendicular to the first direction, the first and second side surfaces extending (1) along the first direction, (2) from the top surface of the emitter layer to the bottom surface of the at least one U-shaped trench, and (3) through the emitter layer, through the base layer, and at least partially into the channel layer; and', 'the bottom surface of the at least one U-shaped trench extending (1) along the second direction and (2) between the first and the second wall of the at least one U-shaped trench;, 'at least one U-shaped trench ...

CARRIER INJECTION CONTROL FAST RECOVERY DIODE STRUCTURES AND METHODS OF FABRICATION

Semiconductor devices and methods of fabrication are provided. The semiconductor device includes a Charge Injection Controlled (CIC) Fast Recovery Diode (FRD) to control charge injection by lowering carrier storage. The device can have a first conductivity type semiconductor substrate, and a drift region that includes a doped buffer region, a doped middle region and a doped field stop region or carrier storage region. The device can also include a second conductivity type shield region including a deep junction encircling (or substantially laterally beneath) the buffer region and a second conductivity type shallow junction anode region in electrical contact with a second conductivity type anode electrode. The deep junction can have a range of doping concentrations surrounding the buffer regions to deplete buffer charge laterally as well as vertically to prevent premature device breakdown. The first conductivity type may be N type and the second conductivity type may be P type. 1. A method of fabricating a Charge Injection Controlled (CIC) Fast Recovery Diode (FRD) , the method comprising:forming a drift region of a first conductivity type on top of a heavily doped semiconductor substrate by epitaxial growth, the drift region supporting blocking of high voltage and comprising a buffer region on the top region of the drift region, a lightly doped middle region, and a medium level doped charge storage region;forming trenches, in the drift region, having depth ranging from 2-6 microns;ion implanting dopants of a second conductivity type into the trenches for forming a shield region of the second conductivity type, the shield region comprising a deep junction substantially spreading laterally beneath the buffer region of the first conductivity type;filling the trenches with poly silicon having lightly doped second conductivity type impurities encircling the buffer region of the first conductivity type;after planarizing the poly silicon in the trenches, ion implanting ...

CONFIGURATION AND METHOD TO GENERATE SADDLE JUNCTION ELECTRIC FIELD IN EDGE TERMINATION

This invention discloses a semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area the edge termination area wherein the edge termination area comprises a superjunction structure having doped semiconductor columns of alternating conductivity types with a charge imbalance between the doped semiconductor columns to generate a saddle junction electric field in the edge termination. 1. A semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area wherein:the edge termination area comprises a superjunction structure having doped semiconductor columns of alternating conductivity types wherein the doped semiconductor columns extends along a slanted direction in the edge termination area.2. The semiconductor power device of wherein:the doped semiconductor columns having electric charge imbalance to create a net P type doping in the edge termination area.3. The semiconductor power device of wherein:the edge termination area having a saddle junction electric field.4. The semiconductor power device of wherein:the doped semiconductor columns comprise P-columns and N-columns and the P-columns having greater electric charges than the N-columns.5. The semiconductor power device of wherein:the doped semiconductor columns comprise P-columns and N-columns and the P-columns have greater width than the N-columns.6. The semiconductor power device of wherein:the doped semiconductor columns comprise P-columns and N-columns and the P-columns have a higher dopant concentration than the N-columns.7. The semiconductor power device of wherein the doped semiconductor columns comprise P-columns and N-columns and wherein:the P-columns have a higher dopant concentration on a top portion than a bottom portion.8. The semiconductor power device of wherein:the doped semiconductor columns comprise P-columns and N-columns and the super-junction structure is formed in a P- ...

SEMICONDUCTOR DEVICE

A highly reliable semiconductor device with high withstand voltage is provided. As means therefor, an impurity concentration in a first JTE region is set to 4.4×10cmor higher and 6×10cmor lower and an impurity concentration in a second JTE region is set to 2×10cmor lower in a case of a Schottky diode, and an impurity concentration in the first JTE region is set to 6×10cmor higher and 8×10cmor lower and an impurity concentration in the second JTE region is set to 2×10cmor lower in a case of a junction barrier Schottky diode. 1. A semiconductor device comprising: a main junction region on a drift region having an n-type conductivity; and a p-type JTE region formed adjacently around the main junction region ,wherein the JTE region includes a first JTE region and a second JTE region having an impurity concentration lower than that of the first JTE region,the first JTE region is disposed so as to be sandwiched between the second JTE regions,{'sup': 17', '−3', '17', '−3', '17', '−3, 'an impurity concentration in the first JTE region is set to 4.4×10cmor higher and 8×10cmor lower and an impurity concentration in the second JTE region is set to 2×10cmor lower in a case of a Schottky diode, and'}{'sup': 17', '−3', '17', '−3', '17', '−3, 'an impurity concentration in the first JTE region is set to 6×10cmor higher and 8×10cmor lower and an impurity concentration in the second JTE region is set to 2×10cmor lower in a case of a junction barrier Schottky diode.'}2. The semiconductor device according to claim 1 ,wherein a difference in impurity concentration between the first JTE region and the second JTE region at a p-n junction depth is made small.3. The semiconductor device according to claim 1 ,wherein a ratio between width and space of the second JTE regions decreases in accordance with a distance from the main junction region. The present invention relates to a semiconductor device.Non-Patent Document 1 discloses a vertical p-n diode in which a JTE (Junction Termination ...

METHOD OF FABRICATING A MERGED P-N JUNCTION AND SCHOTTKY DIODE WITH REGROWN GALLIUM NITRIDE LAYER

A method for fabricating a merged p-i-n Schottky (MPS) diode in gallium nitride (GaN) based materials includes providing an n-type GaN-based substrate having a first surface and a second surface. The method also includes forming an n-type GaN-based epitaxial layer coupled to the first surface of the n-type GaN-based substrate, and forming a p-type GaN-based epitaxial layer coupled to the n-type GaN-based epitaxial layer. The method further includes removing portions of the p-type GaN-based epitaxial layer to form a plurality of dopant sources, and regrowing a GaN-based epitaxial layer including n-type material in regions overlying portions of the n-type GaN-based epitaxial layer, and p-type material in regions overlying the plurality of dopant sources. The method also includes forming a first metallic structure electrically coupled to the regrown GaN-based epitaxial layer. 1. A method for fabricating a merged p-i-n Schottky (MPS) diode in gallium nitride (GaN) based materials , the method comprising:providing an n-type GaN-based substrate having a first surface and a second surface;forming an n-type GaN-based epitaxial layer coupled to the first surface of the n-type GaN-based substrate;forming a p-type GaN-based epitaxial layer coupled to the n-type GaN-based epitaxial layer;removing portions of the p-type GaN-based epitaxial layer to form a plurality of dopant sources;regrowing a GaN-based epitaxial layer including n-type material in regions overlying portions of the n-type GaN-based epitaxial layer and p-type material in regions overlying the plurality of dopant sources; andforming a first metallic structure electrically coupled to the regrown GaN-based epitaxial layer.2. The method of wherein the first metallic structure comprises Schottky contacts electrically coupled to the n-type material in the regions overlying portions of the n-type GaN-based epitaxial layer and ohmic contacts electrically coupled to the p-type material in the regions overlying the ...

MANUFACTURING METHOD OF SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR APPARATUS

A screen oxide film is formed on an n-drift layer () that is disposed on an anterior side of an n-type low-resistance layer (), and a nitride film is formed on the screen oxide film. The nitride film is photo-etched using a first mask and thereby, a nitride shielding film () is formed. N-type impurity ions at a concentration higher than that of the n-drift layer are implanted through the nitride shielding film () from an anterior side of a semiconductor substrate and are thermally diffused and thereby, an n counter layer () is formed. The screen oxide film is removed. A gate oxide film () is formed. A gate electrode () is formed on the gate oxide film (). P-type impurity ions are implanted from the anterior side of the semiconductor substrate using the gate electrode () and the nitride shielding film () as a mask and thereby, p- well regions () are formed. N-type impurity ions are implanted from the anterior side of the semiconductor substrate using the gate electrode () and the nitride shielding film () as a mask and thereby, n source regions () are formed. 1. A semiconductor apparatus provided with an active portion and a voltage-resistant structure portion that surrounds the active portion on a same semiconductor substrate , comprising:a first semiconductor region of a first conductivity;a second semiconductor region of a second conductivity selectively provided in a surface layer on an anterior side of the first semiconductor region;a third semiconductor region of the first conductivity selectively provided in a surface layer of the second semiconductor region;a control electrode that is provided, through a first insulating film, on a surface of the second semiconductor region sandwiched by the first and the third semiconductor regions;a second insulating film that covers the control electrode;a first electrode that contacts the third semiconductor region and is insulated by the second insulating film from the control electrode;a second electrode that is ...

Method of Reducing an Impurity Concentration in a Semiconductor Body

A method includes kicking out impurity atoms from substitutional sites of a crystal lattice of a semiconductor body by implanting particles via a first surface into the semiconductor body, reducing a thickness of the semiconductor body by removing semiconductor material of the semiconductor body, and annealing the semiconductor body in a first annealing process at a temperature of between 300° C. and 450° C. to diffuse impurity atoms out of the semiconductor body. 1. A method , comprising:kicking out impurity atoms from substitutional sites of a crystal lattice of a semiconductor body by implanting particles via a first surface into the semiconductor body;reducing a thickness of the semiconductor body by removing semiconductor material of the semiconductor body; andannealing the semiconductor body in a first annealing process at a temperature of between 300° C. and 450° C. to diffuse impurity atoms out of the semiconductor body.2. The method of claim 1 , wherein a duration of the first annealing process is between 30 minutes and 80 hours.3. The method of claim 1 , wherein the temperature in the first annealing process is between 350° C. and 400° C. claim 1 , and wherein a duration of the first annealing process is between 30 minutes and 10 hours.4. The method of claim 3 , wherein the duration of the first annealing process is between 2 hours and 4 hours.5. The method of claim 2 , wherein the temperature in the first annealing process is between 300° C. and 350° C. claim 2 , and wherein the duration of the first annealing process is between 2 hours and 80 hours.6. The method of claim 1 , wherein reducing the thickness of the semiconductor body comprises removing semiconductor material of the semiconductor body at a second surface opposite the first surface.7. The method of claim 6 , wherein implanting the particles into the semiconductor body comprises implanting the particles into an end-of-range region spaced apart from the first surface claim 6 , and wherein ...

LATCH-UP IMMUNIZATION TECHNIQUES FOR INTEGRATED CIRCUITS

In an integrated circuit supporting complementary metal oxide semiconductor (CMOS) integrated circuits, latch-up immunity is supported by surrounding a hot n-well with an n-well strap spaced from the hot n-well by a specified distance in accordance with design rules. The n-well strap is positioned between the hot n-well and other n-well or n-type diffusion structures. 1. An integrated circuit , comprising:a semiconductor substrate doped with a first conductivity type; a first region heavily doped with the second conductivity type, wherein the first region is connected to a supply node; and', 'a second region heavily doped with the first conductivity type, wherein the second region is connected to an integrated circuit pad;, 'a first semiconductor well doped with a second conductivity type within the semiconductor substrate and includinga second semiconductor well doped with the second conductivity type within the semiconductor substrate;a third region heavily doped with the second conductivity type within the second semiconductor well, wherein the third region is connected to a ground node;a third semiconductor well doped with the second conductivity type within the semiconductor substrate; anda fourth region heavily doped with the second conductivity type within the third semiconductor well, wherein the fourth region is connected to the integrated circuit pad through a resistor;wherein the third semiconductor well is positioned within the semiconductor substrate between the first semiconductor well and the second semiconductor well.2. The integrated circuit of claim 1 , wherein the third semiconductor well is laterally spaced from the first semiconductor well by a design specific distance between adjacent wells having a same conductivity type as specified by design rules for the integrated circuit.3. The integrated circuit of claim 1 , wherein the third semiconductor well is laterally spaced from the second semiconductor well by a design specific distance between ...

ELECTROSTATIC DISCHARGE PROTECTION SEMICONDUCTOR DEVICE

An ESD protection semiconductor device is disclosed. The ESD protection semiconductor device includes a substrate and a gate set disposed on the substrate. A plurality of source fins and a plurality of drain fins are formed in the substrate respectively at two sides of the gate set. At least a first doped fin is formed in the substrate at one side of the gate set the same as the source fins. A plurality of isolation structures are formed in one of the drain fins to define at least a second doped fin in the one of the drain fins. The source fins and the drain fins are of a first conductivity type. The first doped fin is of a second conductivity type that is complementary to the first conductivity type. The first doped fin and the second doped fin are electrically connected to each other. 1. An ESD protection semiconductor device , comprising:a substrate;a gate set disposed on the substrate;a plurality of source fins and a plurality of drain fins disposed in the substrate respectively at two sides of the gate set, wherein the source fins and the drain fins comprise a first conductivity type;at least a first doped fin disposed in the substrate at one side of the gate set the same as the source fins and being spaced apart from the source fins, wherein the first doped fin comprises a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other; anda plurality of isolation structures disposed in one of the drain fins to define at least a second doped fin in the one of the drain fins, wherein the second doped fin is electrically connected to the first doped fin.2. The ESD protection semiconductor device according to claim 1 , wherein the source fins are electrically connected to a ground pad claim 1 , and the drain fins are electrically connected to an IO pad.3. The ESD protection semiconductor device according to claim 1 , wherein the source fins and the drain fins extend along a first direction and are ...

METHOD FOR REDUCING SCHOTTKY BARRIER HEIGHT AND SEMICONDUCTOR DEVICE WITH REDUCED SCHOTTKY BARRIER HEIGHT

A method for controlling Schottky barrier height in a semiconductor device includes forming an alloy layer including at least a first element and a second element on a first surface of a semiconductor substrate. The semiconductor substrate is a first element-based semiconductor substrate, and the first element and the second element are Group IV elements. A first thermal anneal of the alloy layer and the first element-based substrate is performed. The first thermal anneal causes the second element in the alloy layer to migrate towards a surface of the alloy layer. A Schottky contact layer is formed on the alloy layer after the first thermal anneal. 1. A method for controlling Schottky barrier height in a semiconductor device comprising:forming an alloy layer comprising at least a first element and a second element on a surface of a semiconductor substrate,wherein the semiconductor substrate is a first element-based semiconductor substrate, and the first element and the second element are Group IV elements;performing a first thermal anneal of the alloy layer and the first element-based substrate,wherein the first thermal anneal causes the second element in the alloy layer to migrate towards a surface of the alloy layer; andforming a Schottky contact layer on the alloy layer after the first thermal anneal.2. The method according to claim 1 , wherein the semiconductor substrate is a first element-based wafer claim 1 , a first element-on-insulator substrate claim 1 , or an epitaxial first element layer.3. The method according to claim 1 , wherein the alloy layer as formed on the first element-based substrate has a second element content of 0.1 atomic % to 12 atomic % based on a total amount of the first element and the second element in the alloy layer.4. The method according to claim 1 , wherein the first thermal anneal is performed at a temperature of 300° C. to 460° C.5. The method according to claim 1 , further comprising forming an ohmic contact layer on the ...

IGBT Having a Barrier Region

An IGBT having a barrier region is presented. A power unit cell of the IGBT has at least two trenches that may both extend into the barrier region. The barrier region may be p-doped and vertically confined, i.e., in and against the extension direction, by means of the drift region. The barrier region can be electrically floating. 1. An IGBT , comprising:a semiconductor body coupled to a first load terminal and a second load terminal of the IGBT and comprising a drift region configured to conduct a load current between the first and the second load terminals, the drift region comprising dopants of a first conductivity type; a control trench having a control trench electrode and a further trench having a further trench electrode electrically coupled to the control trench electrode;', 'an active mesa comprising a source region with dopants of the first conductivity type and electrically connected to the first load terminal and a channel region with dopants of a second conductivity type, the channel region separating the source region and the drift region, wherein in the active mesa, at least a respective section of each of the source region, the channel region and the drift region are arranged adjacent to a sidewall of the control trench, and wherein the control trench electrode is configured to receive a control signal from a control terminal of the IGBT and to control the load current in the active mesa, the further trench electrode not being configured to control the load current; and', 'an electrically floating semiconductor barrier region in the semiconductor body and comprising dopants of the second conductivity type, the barrier region laterally overlapping with both the active mesa and a bottom of the further trench., 'a power unit cell comprising2. The IGBT of claim 1 , wherein at least one of:the power unit cell further comprises an inactive mesa arranged adjacent to the further trench, a transition between the first load terminal and the inactive mesa ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A semiconductor device includes: a semiconductor base body where a second semiconductor layer is stacked on a first semiconductor layer, a trench is formed on a surface of the second semiconductor layer, and a third semiconductor layer which is formed of an epitaxial layer is formed in the inside of the trench; a first electrode; an interlayer insulation film which has a predetermined opening; and a second electrode, wherein metal is filled in the opening, the opening is disposed at a position avoiding a center portion of the third semiconductor layer, the second electrode is connected to the third semiconductor layer through the metal, and a surface of the center portion of the third semiconductor layer is covered by the interlayer insulation film. 1. A semiconductor device comprising:a semiconductor base body where a second semiconductor layer of a first conductive type is stacked on a first semiconductor layer of the first conductive type or a second conductive type, a trench having a predetermined depth is formed on a surface of the second semiconductor layer, and a third semiconductor layer of the second conductive type which is formed of a monocrystal epitaxial layer is formed in the inside of the trench;a first electrode which is positioned on a surface of the first semiconductor layer;an interlayer insulation film which is positioned on a surface of the second semiconductor layer and on a surface of the third semiconductor layer and has a predetermined opening formed within a region where at least the third semiconductor layer is formed as viewed in a plan view, the opening being filled with metal; anda second electrode which is positioned over the interlayer insulation film, whereinthe opening is disposed at a position avoiding a center portion of the third semiconductor layer as viewed in a plan view,the second electrode is connected to at least the third semiconductor layer through the metal filled in the opening, anda surface of the center portion of the ...

HIGH VOLTAGE DEVICE

A high voltage device includes a semiconductor substrate, an ion well, a Schottky diode in the ion well, an isolation structure in the ion well surrounding the Schottky diode, and an assistant gate surrounding the Schottky diode. The assistant gate is disposed only on the isolation structure and is not in direct contact with the ion well. 1. A high voltage device , comprising:a semiconductor substrate having a first conductivity type;a first ion well having a second conductivity type;a Schottky diode disposed in the first ion well;an isolation structure in the first ion well and surrounding the Schottky diode; andan assistant gate disposed only on the isolation structure and surrounding the Schottky diode, wherein the assistant gate is electrically connected to the Schottky diode by the assistant gate connected to a first contact element, the first contact element connected to an interconnection, the interconnection connected to a second contact element, and the second contact element connected to the Schottky diode.2. The high voltage device according to claim 1 , wherein the Schottky diode comprises a silicide layer in direct contact with the first ion well.3. The high voltage device according to further comprising a second ion well having the first conductivity type in the first ion well claim 1 , wherein the second ion well is disposed along an inner side of the isolation structure and surrounds the Schottky diode claim 1 , and wherein the second ion well overlaps with an inner portion of the isolation structure claim 1 , and wherein the second ion well is disposed in between the Schottky diode and the assistant gate.4. The high voltage device according to further comprising a salicide block (SAB) layer disposed on the second ion well and surrounding the Schottky diode claim 3 , wherein the SAB layer extends to above the inner portion of the isolation structure.5. The high voltage device according to further comprising a first heavily doped region having the ...

Integrated device having multiple transistors

An integrated device includes a semiconductor well formed in an epitaxial layer, and a guard ring formed in the epitaxial layer and surrounding the semiconductor well. The semiconductor well and the guard ring include a type of semiconductor different from that of the epitaxial layer. The integrated device also includes an insulating layer formed atop the guard ring, and multiple gate electrodes formed on a top surface of the insulating layer, overlapping the guard ring and surrounding the semiconductor well. The gate electrodes include a first gate electrode and a second gate electrode separated by a gap. An intersecting line between the top surface of the insulating layer and a side wall of the first gate electrode partially overlaps an area that is defined based on an intersecting line between the top surface of the insulating layer and a side wall of the second gate electrode above the guard ring.

POWER SEMICONDUCTOR DEVICE WITH THICK TOP-METAL-DESIGN AND METHOD FOR MANUFACTURING SUCH POWER SEMICONDUCTOR DEVICE

The present application contemplates a method for manufacturing a power semiconductor device. The method comprises: providing a wafer of a first conductivity type, the wafer having a first main side and a second main side opposite to the first main side, and the wafer including an active cell area, which extends from the first main side to the second main side, in a central part of the wafer and a termination area surrounding the active cell area in an orthogonal projection onto a plane parallel to the first main side; forming a metallization layer on the first main side to electrically contact the wafer in the active cell area, wherein the surface of the metallization layer, which faces away from the wafer, defines a first plane parallel to the first main side; forming an isolation layer on the first main side in the termination area, wherein the surface of the isolation layer facing away from the wafer defines a second plane parallel to the first main side; after the step of forming the metallization layer and after the step of forming the isolation layer, mounting the wafer with its first main side to a flat surface of a chuck; and thereafter thinning the wafer from its second main side by grinding while pressing the second main side of the wafer onto a grinding wheel by applying a pressure between the chuck and the grinding wheel, wherein the first plane is further away from the wafer than a third plane, which is parallel to the second plane and arranged at a distance of 1 μm from the second plane in a direction towards the wafer. 1. A method for manufacturing a power semiconductor device , the method comprising the following steps:providing a wafer of a first conductivity type, the wafer having a first main side and a second main side opposite to the first main side, and the wafer including an active cell area, which extends from the first main side to the second main side, in a central part of the wafer and a termination area surrounding the active cell area ...

SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS INCLUDING THE SAME

A semiconductor device includes a plurality of transistor components disposed on a semiconductor substrate, and a guard ring disposed on the semiconductor substrate surrounding the transistor components. The guard ring includes a plurality of fin structures disposed in parallel on the semiconductor substrate, a plurality of first conductive connection members disposed on the fin structures and connecting at least two fin structures, and a plurality of second conductive connection members connecting at least two first conductive connection members. The first conductive connection members and the second conductive connection members are formed as one structure. 1. A semiconductor device comprising:a plurality of transistor components disposed on a semiconductor substrate; a plurality of fin structures disposed in parallel on the semiconductor substrate;', 'a plurality of first conductive connection members disposed on the fin structures and connecting at least two fin structures; and', 'a plurality of second conductive connection members connecting at least two first conductive connection members,', 'wherein the first conductive connection members and the second conductive connection members are formed as one structure., 'a guard ring disposed on the semiconductor substrate surrounding the transistor components, wherein the guard ring comprises2. The semiconductor device according to claim 1 , wherein the first conductive connection members and the second conductive connection members are formed in a mesh configuration.3. The semiconductor device according to claim 1 , wherein the second conductive connection member is perpendicular to the first conductive connection member.4. The semiconductor device according to claim 1 , wherein the second conductive connection members have a same width claim 1 , and wherein adjacent second conductive connection members are spaced apart by a same distance.5. The semiconductor device according to claim 1 , wherein the first ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor substrate in which an active region and an edge termination region are defined, a semiconductor element formed in the active region, and first to fourth P layers formed in a region spanning from an edge portion of the active region to the edge termination region in the surface of the semiconductor substrate. The first to fourth P layers respectively have surface concentrations P(1) to P(4) that decrease in this order, bottom-end distances D(1) to D(4) that increase in this order, and distances B(1) to B(4) to the edge of the semiconductor substrate that increase in this order. The surface concentration P(4) is 10 to 1000 times the impurity concentration of the semiconductor substrate, and the bottom-end distance D(4) is in the range of 15 to 30 μm. 1. A semiconductor device comprising:a semiconductor substrate of a first conductivity type in which an active region and an edge termination region that is spaced from and encloses said active region are defined;a semiconductor element formed in said active region; anda plurality of impurity layers of a second conductivity type that are formed at least partly overlapping one another in a region spanning from an edge portion of said active region to said edge termination region in a surface of said semiconductor substrate,wherein, for an arbitrary pair of adjacent ith and an i+1th impurity layers among said plurality of impurity layers, P(i)>P(i+1), D(i) Подробнее

SEMICONDUCTOR DEVICE WITH FIELD THRESHOLD MOSFET FOR HIGH VOLTAGE TERMINATION

This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a lightly doped layer formed on a heavily doped layer and having an active cell area and an edge termination area. The edge termination area comprises a plurality P-channel MOSFETs. By connecting the gate to the drain electrode, the P-channel MOSFET transistors formed on the edge termination are sequentially turned on when the applied voltage is equal to or greater than the threshold voltage Vt of the P-channel MOSFET transistors, thereby optimizing the voltage blocked by each region. 1. A semiconductor power device disposed in a semiconductor substrate comprising a lightly doped layer formed on top of a heavily doped layer and having an active cell area and an edge termination area wherein:said edge termination area comprises a plurality of termination trenches formed in said lightly doped layer and lined with a dielectric layer and filled with a conductive material therein; anda plurality of series connected MOSFET transistors, each of which comprises a trench gate region, a drain and source regions disposed on two opposite sides of each of said termination trenches, with said conductive material in each of said termination trenches functions as a trench gate for each of said MOSFET transistors, wherein each trench gate is electrically connected to said drain region.2. The semiconductor power device of wherein:said plurality of MOSFET transistors comprising a plurality of P-channel MOSFET transistors.3. The semiconductor power device of wherein:one of the plurality of MOSFET transistors is turned on when the applied voltage is greater than or equal to a threshold voltage of said MOSFET transistor, wherein said threshold voltage ranging from 0.5 to 80 volts.4. The semiconductor power device of wherein:said edge termination has a width ranging from 5 microns to 250 microns to form between 1 to 25 termination trenches in said edge termination.5. The semiconductor ...

SEMICONDUCTOR DEVICE HAVING INDUCTOR

A semiconductor device includes first and second winding portions disposed in a first level of an insulating layer and surrounding a center region thereof. Each of the winding portions includes conductive lines arranged from the inside to the outside. First and second extending conductive lines are disposed in the first level of the insulating layer. A third extending conductive line is disposed in a second level of the insulating layer. The first extending conductive line is coupled between the innermost conductive line of the second winding and the third extending conductive line. The second extending conductive line is coupled between the innermost conductive line of the first winding portion and the third extending conductive line. The first extending conductive line and the third extending conductive line coupled thereto are arranged in a helix or a spiral spatial configuration. 1. A semiconductor device , comprising:an insulating layer disposed over a substrate, wherein the insulating layer has a center region;a first winding portion and a second winding portion electrically connected to the first winding portion, disposed in a first level of the insulating layer and surrounding the center region, wherein each of the first winding portion and the second winding portion comprises a plurality of conductive lines arranged from the inside to the outside;a first extending conductive line and a second extending conductive line partially surrounding the first extending conductive line, disposed in the first level of the insulating layer, wherein the first winding portion and the second winding portion surround the first extending conductive line and the second extending conductive line; anda third extending conductive line disposed in a second level of the insulating layer and surrounding the center region,wherein the extending conductive lines and the conductive lines have a first end and a second end, wherein the first end and the second end of the first extending ...

SURFACE DEVICES WITHIN A VERTICAL POWER DEVICE

A semiconductor device comprises a vertical power device, such as a superjunction MOSFET, an IGBT, a diode, and the like, and a surface device that comprises one or more lateral devices that are electrically active along a top surface of the semiconductor device. 1. A semiconductor device comprising:a surface device; and,a vertical power device that is controlled by the surface device.2. The semiconductor device of further comprising:an insulator; and,the surface device and the vertical power device separated by the insulator.3. The semiconductor device of further comprising:epitaxial silicon;the surface device formed on the epitaxial silicon; and,the vertical power device formed on the epitaxial silicon as a superjunction metal oxide semiconductor field effect transistor.4. The semiconductor device of further comprising:the vertical power device including one or more power devices in which subsets of the one or more power devices are connected in parallel.5. The semiconductor device of further comprising:a wafer on which the semiconductor device is formed and which includes a front-side and a back-side;a first metal layer on the front-side of the wafer;a second metal layer on the back-side of the wafer; and,the vertical power device configured so that power flows between the first metal layer and the second metal layer.6. The semiconductor device of wherein the surface device further comprises:a set of analog circuits and a set of digital circuits formed by a set of metal oxide semiconductor regions.7. The semiconductor device of wherein the set of metal oxide semiconductor regions further comprises:a medium voltage N-type metal oxide semiconductor region;a medium voltage P-type metal oxide semiconductor region;a low voltage N-type metal oxide semiconductor region; and,a low voltage P-type metal oxide semiconductor region.8. The semiconductor device of further comprising:each region of the set of metal oxide semiconductor regions including a set of transistors ...

SEMICONDUCTOR DEVICES AND METHOD OF MAKING THE SAME

In one embodiment, the semiconductor devices relate to using one or more super-junction trenches for termination. 1. A semiconducting device comprising:a semiconductor substrate of a first conductivity type;a first layer of the first conductivity type overlying the semiconductor substrate;an active region; and [ a first semiconducting region having a second conductivity type;', 'a second semiconducting region adjacent to the first semiconducting region, wherein the second semiconducting region has a third conductivity type that is different than the second conductivity type;', 'a first buffer region adjacent to the second semiconducting region;', 'a third semiconducting region adjacent to the first buffer region, wherein the third semiconducting region has the third conductivity type; and', 'a fourth semiconducting region adjacent to the third semiconducting region, wherein the fourth semiconducting region has the second conductivity type; and, 'two or more first segments each comprising a first super-junction trench, wherein the first super-junction trench comprises, 'two or more second segments each comprising a fifth semiconducting region having the first conductivity type,', 'wherein the first segments and the second segments are alternatively arranged to form the ring structure., 'one or more ring structures surrounding the active region, the ring structures each comprising2. The semiconductor device of claim 1 , wherein the first conductivity type is a n-type conductivity and the second conductivity type is a n-type conductivity.3. The semiconductor device of claim 1 , wherein the third conductivity type is a p-type conductivity.4. The semiconductor device of claim 1 , wherein the first buffer region comprises a dielectric material and at least one void.5. The semiconducting device of claim 1 , wherein the second segments each further comprise a sixth semiconducting region having the third conductivity type claim 1 , wherein the sixth semiconducting region is ...

SCHOTTKY BARRIER DIODE AND A METHOD OF MANUFACTURING THE SAME

A Schottky metal is in Schottky-contact with a center portion of a surface of an epitaxial layer. A peripheral trench is formed by digging from the surface of the epitaxial layer on a boundary portion between an active region where the Schottky metal is in Schottky-contact with the surface of the epitaxial layer and a peripheral region outside of the active region in a surface layer portion of the epitaxial layer. An insulating film is formed on an entire area of inner wall surfaces of the peripheral trench. There is provided with a conductor which is connected to the Schottky metal and is opposed to the entire area of the inner wall surfaces of the peripheral trench via the insulating film in the peripheral trench. 1. A method for manufacturing a Schottky barrier diode , comprising:forming an epitaxial layer having a first conductivity type and having an impurity concentration lower than that of a semiconductor substrate having a first conductivity type on the semiconductor substrate;forming a peripheral trench on a surface of the epitaxial layer by digging from the surface of the epitaxial layer;forming an insulating film on an entire area of inner wall surfaces of the peripheral trench;forming a conductor which is opposed to the entire area of the inner wall surfaces of the peripheral trench via the insulating film; andforming a Schottky metal which is connected to the conductor and is in Schottky-contact with the surface of the epitaxial layer,wherein the peripheral trench is formed in a boundary portion between an active region where the Schottky metal is in Schottky-contact with the surface of the epitaxial layer and a peripheral region surrounding the outside of the active region.2. The method for manufacturing a Schottky barrier diode according to claim 1 , wherein the inner wall surfaces of the peripheral trench include side surfaces and a bottom surface of the peripheral trench.3. The method for manufacturing a Schottky barrier diode according to claim 1 , ...

MOSFET DEVICE OF SILICON CARBIDE HAVING AN INTEGRATED DIODE AND MANUFACTURING PROCESS THEREOF

An integrated MOSFET device is formed in a body of silicon carbide and with a first type of conductivity. The body accommodates a first body region, with a second type of conductivity; a JFET region adjacent to the first body region; a first source region, with the first type of conductivity, extending into the interior of the first body region; an implanted structure, with the second type of conductivity, extending into the interior of the JFET region. An isolated gate structure lies partially over the first body region, the first source region and the JFET region. A first metallization layer extends over the first surface and forms, in direct contact with the implanted structure and with the JFET region, a JBS diode. 1. An integrated metal-oxide semiconductor field effect transistor (MOSFET) device comprising:a body, of silicon carbide and with a first type of conductivity, having a first surface and a second surface;a first body region with a second type of conductivity, extending from the first surface into the body;a junction field effect transistor (JFET) region adjacent to the first body region and facing the first surface;a first source region, with the first type of conductivity, extending from the first surface into the first body region;an isolated gate structure extending over the first surface and lying partially over the first body region, the first source region and the JFET region;an implanted structure, with the second type of conductivity, extending into the JFET region from the first surface; anda first metallization layer extending over the first surface, the first metallization layer being in direct contact with the implanted structure and with the JFET region and forming a Junction-Barrier Schottky (JBS) diode that includes the implanted structure and the JFET region.2. The device according to claim 1 , furthermore comprising a second metallization layer extending on the second surface of the body.3. The device according to claim 1 , ...

LAMINATED ARTICLE

A laminated body comprising a substrate, an ohmic electrode layer, a metal oxide semiconductor layer, a Schottky electrode layer and a buffer electrode layer in this order, wherein a reduction suppressing layer is provided between the Schottky electrode layer and the buffer electrode layer. 1. A laminated body comprising a substrate , an ohmic electrode layer , a metal oxide semiconductor layer , a Schottky electrode layer and a buffer electrode layer in this order , whereina reduction suppressing layer is provided between the Schottky electrode layer and the buffer electrode layer.2. The laminated body according to claim 1 , wherein the reduction suppressing layer comprises one or more elements selected from the group consisting of Pd claim 1 , Mo claim 1 , Pt claim 1 , Ir claim 1 , Ru claim 1 , Au claim 1 , Ni claim 1 , W claim 1 , Cr claim 1 , Re claim 1 , Te claim 1 , Tc claim 1 , Mn claim 1 , Os claim 1 , Fe claim 1 , Rh and Co.3. The laminated body according to claim 1 , wherein the Schottky electrode layer comprises an oxide of one or more metal elements having a work function of 4.4 eV or more.4. The laminated body according to claim 1 , wherein the Schottky electrode layer comprises an oxide of one or more metals selected from the group consisting of Pd claim 1 , Mo claim 1 , Pt claim 1 , Ir claim 1 , Ru claim 1 , Ni claim 1 , W claim 1 , Cr claim 1 , Re claim 1 , Te claim 1 , Tc claim 1 , Mn claim 1 , Os claim 1 , Fe claim 1 , Rh and Co.5. The laminated body according to claim 1 , wherein the substrate is a conductive substrate.6. The laminated body according to claim 1 , wherein the substrate is an insulating substrate.7. The laminated body according to claim 1 , wherein the substrate is a semiconductor substrate.8. The laminated body according to claim 1 , which comprises a layer structure comprising one or more layers selected from the group consisting of an electrode layer and an insulating layer.9. The laminated body according to claim 1 , wherein the ...

POWER SCHOTTKY DIODES HAVING CLOSELY-SPACED DEEP BLOCKING JUNCTIONS IN A HEAVILY-DOPED DRIFT REGION

A Schottky diode includes a drift region, a channel in an upper portion of the drift region, and first and second adjacent blocking junctions in the upper portion of the drift region that define the channel therebetween. The drift region and channel are doped with dopants having a first conductivity type, and the first and second blocking junctions doped with dopants having a second conductivity type that is opposite the first conductivity type. The blocking junctions extend at least one micron into the upper portion of the drift region and are spaced apart from each other by less than 3.0 microns. 1. A Schottky diode , comprising:a drift region having an upper portion and a lower portion, the drift region doped with dopants having a first conductivity type;a channel in the upper portion of the drift region, the channel having the first conductivity type;a first blocking junction and a second blocking junction adjacent the first blocking junction in the upper portion of the drift region, the first and second blocking junctions defining the channel therebetween, the first and second blocking junctions doped with dopants having a second conductivity type that is opposite the first conductivity type, the first and second blocking junctions extending at least one micron into the upper portion of the drift region and being spaced apart from each other by less than 3.0 microns;a first contact on the upper portion of the drift region; anda second contact on the lower portion of the drift region and vertically spaced apart from the first contact.2. The Schottky diode of claim 1 , wherein a doping concentration of the drift region is greater than 1.5×10/cm.3. The Schottky diode of claim 2 , wherein a doping concentration of the drift region is less than 5×10/cm.4. The Schottky diode of claim 3 , wherein the first and second blocking junctions each have a depth from the upper surface of the drift region of between 1.0 microns and 1.5 microns.5. The Schottky diode of claim 4 , ...

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

The semiconductor device includes a substrate, a fin structure, a source/drain region, and a gate structure. The fin structure includes a first-stage fin region, a second-stage fin region, and a third-stage fin region. The second-stage fin region is under the first-stage fin region. The third-stage fin region is under the second-stage fin region. The source/drain region is on a top surface of the second-stage fin region. The gate structure is over the first-stage fin region and wraps around a top surface and sidewalls of the first-stage fin region. The top surface of the second-stage fin region is lower than the top surface of the first-stage fin region. A width of the third-stage fin region is greater than a width of the second-stage fin region, and the width of the second-stage fin region is substantially the same as a width of the first-stage fin region. 1. A semiconductor device , comprising:a substrate; a first-stage fin region;', 'a second-stage fin region under the first-stage fin region; and', 'a third-stage fin region under the second-stage fin region;, 'a fin structure on the substrate, comprisinga source/drain region on a top surface of the second-stage fin region; anda gate structure over the first-stage fin region, configured to wrap around a top surface and sidewalls of the first-stage fin region, wherein the top surface of the second-stage fin region is lower than the top surface of the first-stage fin region; andwherein a width of the third-stage fin region is greater than a width of the second-stage fin region, and the width of the second-stage fin region is substantially the same as a width of the first-stage fin region.2. The semiconductor device of claim 1 , wherein a width of the first-stage fin region is between about 3 nm and about 10 nm claim 1 , a width of the second-stage fin region is between about 5 nm and about 10 nm claim 1 , and a width of the third-stage fin region is between about 30 nm and about 80 nm.3. The semiconductor device of ...

VERTICAL ETCH HETEROLITHIC INTEGRATED CIRCUIT DEVICES

Vertical etch heterolithic integrated circuit devices are described. A method of manufacturing NIP diodes is described in one example. A P-type substrate is provided, and an intrinsic layer is formed on the P-type substrate. An oxide layer is formed on the intrinsic layer, and one or more openings are formed in the oxide layer. One or more N-type regions are implanted in the intrinsic layer through the openings in the oxide layer. The N-type regions form cathodes of the NIP diodes. A dielectric layer deposited over the oxide layer is selectively etched away with the oxide layer to expose certain ranges of the intrinsic layer to define a geometry of the NIP diodes. The intrinsic layer and the P-type substrate are vertically etched away within the ranges to expose sidewalls of the intrinsic layer and the P-type substrate. The P-type substrate forms the anodes of the NIP diodes. 1. A method of manufacturing a device , comprising:providing a P-type silicon substrate;forming an intrinsic layer on the P-type silicon substrate;growing an oxide layer on the intrinsic layer;forming at least one opening in the oxide layer;implanting an N-type region in the intrinsic layer through the at least one opening in the oxide layer;depositing a dielectric layer over the oxide layer and the N-type region;selectively etching the dielectric layer and the oxide layer away expose the intrinsic layer within at least one range to define a geometry of the device; andvertically etching the intrinsic layer and the P-type silicon substrate away within the at least one range to expose sidewalls of the intrinsic layer and the P-type silicon substrate.2. The method according to claim 1 , further comprising forming conductive regions on the sidewalls of the intrinsic layer and the P-type silicon substrate by diffusion of a P-type acceptor into the sidewalls.3. The method according to claim 1 , further comprising encapsulating the device in an insulative material.4. The method according to claim 3 , ...

SEMICONDUCTOR PLASMA ANTENNA APPARATUS

Provided is a semiconductor plasma antenna apparatus. The apparatus includes: a cell array unit in which a plurality of PIN diode cells are arranged, and in which a cell pattern is formed by using a predefined PIN diode cell among the plurality of PIN diode cells; and a driver circuit unit configured to control a drive of the predefined PIN diode cell, wherein the driver circuit unit comprises: a direct-current conversion unit equipped with a DC-DC converter configured to drive a diode load of the cell pattern by applying an output voltage to a PIN diode cell corresponding to the cell patterns formed in the cell array unit; and a constant current controller configured to controlling a plasma concentration of the PIN diode cell by controlling a constant current for the diode load of the cell pattern. 1. A semiconductor plasma antenna apparatus comprising:a cell array unit in which a plurality of PIN diode cells are arranged, and in which a cell pattern is formed by using a predefined PIN diode cell among the plurality of PIN diode cells; anda driver circuit unit configured to control a drive of the predefined PIN diode cell,wherein the driver circuit unit comprises: a direct-current conversion unit equipped with a DC-DC converter configured to drive a diode load of the cell pattern by applying an output voltage to a PIN diode cell corresponding to the cell patterns formed in the cell array unit; and a constant current controller configured to controlling a plasma concentration of the PIN diode cell by controlling a constant current for the diode load of the cell pattern.2. The semiconductor plasma antenna apparatus of claim 1 , wherein the predefined PIN diode cell is connected in series in the cell pattern.3. The semiconductor plasma antenna apparatus of claim 1 , wherein the predefined PIN diode cell is connected in parallel in the cell pattern.4. The semiconductor plasma antenna apparatus of claim 1 , wherein claim 1 , when a single cell pattern is divided into ...

Schottky Diode and Method of Manufacturing the Same

A Schottky diode includes a drift region of a first conductive type formed at a surface portion of a substrate, an insulating layer disposed on the substrate and having an opening exposing a portion of the drift region, and a titanium silicide layer disposed on the portion of the drift region exposed by the opening. 1. A Schottky diode comprising:a drift region of a first conductive type formed at a surface portion of a substrate;an insulating layer disposed on the substrate, the insulating layer having an opening exposing a portion of the drift region; anda titanium silicide layer disposed on the portion of the drift region exposed by the opening.2. The Schottky diode of claim 1 , further comprising a guard ring of a second conductive type disposed under an edge portion of the titanium silicide layer.3. The Schottky diode of claim 1 , further comprising:a landing pad disposed on the titanium silicide layer and the insulating layer;a second insulating layer disposed on the landing pad;a metal wiring disposed on the second insulating layer; andat least one via contact connecting the landing pad with the metal wiring.4. The Schottky diode of claim 3 , further comprising a contact pad disposed between the titanium silicide layer and the landing pad.5. The Schottky diode of claim 4 , wherein the contact pad extends along an upper surface of the titanium silicide layer and an inner side surface of the opening.6. The Schottky diode of claim 1 , further comprising:a titanium layer disposed on an inner side surface of the opening; anda titanium nitride layer disposed on the titanium silicide layer and the titanium layer.7. A method of manufacturing a Schottky diode claim 1 , the method comprising:forming a drift region of a first conductive type at a surface portion of a substrate;forming an insulating layer on the substrate, the insulating layer having an opening exposing a portion of the drift region; andforming a titanium silicide layer on the portion of the drift region ...

TRANSISTOR

A transistor includes: a semiconductor substrate; a plurality of gate electrodes, a plurality of source electrodes, and a plurality of drain electrodes on the semiconductor substrate; a drain pad on the semiconductor substrate and connected to the plurality of drain electrodes; a metal wiring on the semiconductor substrate and arranged spaced apart from, adjacent to and parallel to the drain pad; and a ground pad on the semiconductor substrate and connected to both ends of the metal wiring. 1. A transistor comprising:a semiconductor substrate;a plurality of gate electrodes, a plurality of source electrodes, and a plurality of drain electrodes on the semiconductor substrate;a drain pad on the semiconductor substrate and connected to the plurality of drain electrodes;a metal wiring on the semiconductor substrate and arranged spaced apart from, adjacent to and parallel to the drain pad; anda ground pad on the semiconductor substrate and connected to both ends of the metal wiring.2. The transistor of claim 1 , wherein the entire drain pad faces the metal wiring to constitute a capacitor.3. The transistor of claim 1 , wherein a ground potential is applied to the ground pad.4. The transistor of claim 3 , further comprising a wire or a via hole inside the semiconductor substrate claim 3 , wherein the ground potential is applied to the ground pad using the wire or the via hole.5. The transistor of claim 1 , wherein a distance between the drain pad and the metal wiring is 100 microns or less.6. The transistor of claim 1 , further comprising a resistor connected between the metal wiring and the ground pad.7. The transistor of claim 6 , wherein the resistor is an ion implantation resistor claim 6 , a film resistor or a wire resistor.8. The transistor of claim 1 , further comprising a guard ring on the semiconductor substrate and surrounding the plurality of gate electrodes claim 1 , the plurality of source electrodes and the plurality of drain electrodes claim 1 ,wherein the ...

SCHOTTKY DIODE STRUCTURE AND METHOD OF FABRICATION

The disclosed technology relates to a device including a diode. In one aspect, the device includes a lower group III metal nitride layer and an upper group III metal nitride layer and a heterojunction formed therebetween, where the heterojunction extends horizontally and is configured to form a two-dimensional electron gas (2DEG) that is substantially confined in a vertical direction and within the lower group III metal nitride layer. The device additionally includes a cathode forming an ohmic contact with the upper group III metal nitride layer. The device additionally includes an anode, which includes a first portion that forms a Schottky barrier contact with the upper group III metal nitride layer, and a second portion that is separated vertically from the upper group III metal nitride layer by a layer of dielectric material. The anode is configured such that the second portion is horizontally located between the anode and the cathode and the dielectric material is configured to pinch off the 2DEG layer in a reverse biased configuration of the device. The device further includes a passivation area formed between the anode and the cathode to horizontally separate the anode and the cathode from each other. 1. A Schottky diode device comprising:a lower group III metal nitride layer and an upper group III metal nitride layer and a heterojunction formed therebetween, wherein the heterojunction extends horizontally and is configured to form a two-dimensional electron gas (2DEG) that is substantially confined in a vertical direction and within the lower group III metal nitride layer;a cathode forming an ohmic contact with the upper group III metal nitride layer; a first portion that forms a Schottky barrier contact with the upper group III metal nitride layer; and', 'a second portion that is separated vertically from the upper group III metal nitride layer by a layer of dielectric material,', 'wherein the second portion is horizontally located between the anode and the ...

Bipolar junction transistor having an integrated switchable short

The invention solves the problem of depressed SOA of a bipolar junction transistor (BJT) when operated in an open base configuration by integrating in the same semiconductor chip a switchable short between the base and the emitter of the BJT. The switchable short switches between a high resistive value when the collector voltage of the BJT is lower than the base voltage. and a lower resistive value when the collector voltage is higher than the voltage base to effectively lower the BJT current gain (hFE). The switchable short in one implementation of the invention is in the form of a MOSFET with its gate connected to the BJT collector. The invention further teaches disposing in the integrated circuit chip a junction diode with a breakdown voltage lower than the BVCBO of the BJT. The addition of the junction diode provides a measure of maintaining the effectiveness of the MOSFET as switchable short at a reduced size.

SEMICONDUCTOR DEVICE

A semiconductor device, including a substrate of a first conductivity type, an active region and a termination structure portion formed on a front surface of the substrate, and a plurality of regions of a second conductivity type formed concentrically surrounding the periphery of the active region in the termination structure portion. Each region has a higher impurity concentration than one of the regions adjacent thereto on an outside thereof. The plurality regions include first and second semiconductor regions, and an intermediate region sandwiched between, and in contact with, the first and second semiconductor regions, and a third semiconductor region. The intermediate region includes a plurality of first subregions and a plurality of second subregions that are alternately arranged along a path in parallel to a boundary between the active region and the termination structure portion, the second subregions having a lower impurity concentration than the first subregions. 1. A semiconductor device , comprising:a semiconductor substrate;an active region formed on a front surface of the semiconductor substrate;a termination structure portion formed on the front surface of the semiconductor substrate and surrounding a periphery of the active region, to thereby form a boundary line on the front surface between the active region and the termination structure portion; anda third semiconductor region, a first semiconductor region, an intermediate region, and a second semiconductor region, formed in the termination structure portion and concentrically surrounding the boundary line on the front surface in this order, whereinthe second semiconductor region surrounds the first semiconductor region, an impurity concentration of the second semiconductor region being lower than an impurity concentration of the first semiconductor region,the third semiconductor region has an impurity concentration that is different from the impurity concentration of the first semiconductor region ...

VERTICAL BIPOLAR TRANSISTOR DEVICE

A vertical bipolar transistor device includes a heavily-doped semiconductor substrate, a first semiconductor epitaxial layer, at least one doped well, an isolation structure, and an external conductor. The heavily-doped semiconductor substrate and the doped well have a first conductivity type, and the first semiconductor epitaxial layer has a second conductivity type. The first semiconductor epitaxial layer is formed on the heavily-doped semiconductor substrate. The doped well is formed in the first semiconductor epitaxial layer. The isolation structure, formed in the heavily-doped semiconductor substrate and the first semiconductor epitaxial layer, surrounds the first semiconductor epitaxial layer and the at least one doped well. The external conductor is arranged outside the first semiconductor epitaxial layer and the doped well and electrically connected to the first semiconductor epitaxial layer and the doped well. 1. A vertical bipolar transistor device comprising:a heavily-doped semiconductor substrate having a first conductivity type;a first semiconductor epitaxial layer, having a second conductivity type, formed on the heavily-doped semiconductor substrate;at least one doped well, having the first conductivity type, formed in the first semiconductor epitaxial layer;an isolation structure, formed in the heavily-doped semiconductor substrate and the first semiconductor epitaxial layer, surrounding the first semiconductor epitaxial layer and the at least one doped well; andan external conductor arranged outside the first semiconductor epitaxial layer and the at least one doped well and electrically connected to the first semiconductor epitaxial layer and the at least one doped well;wherein there is nothing between the external conductor and the first semiconductor epitaxial layer and there is nothing between the external conductor and the at least one doped well.2. The vertical bipolar transistor device according to claim 1 , wherein the first conductivity type ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME

A semiconductor device may include an element region and a peripheral voltage withstanding region. The peripheral voltage withstanding region includes inner circumferential guard rings; and outer circumferential guard rings having a width narrower than a width of the inner circumferential guard rings. An interval between the inner circumferential guard rings is narrower than an interval between the outer circumferential guard rings. Each of the inner circumferential guard rings includes a first high concentration region and a first low concentration region. Each of the outer circumferential guard rings includes a second high concentration region and a second low concentration region. A width of a part of each first low concentration region that is exposed on a front surface of the semiconductor device is wider than a width of a part of each second low concentration region that is exposed on the front surface. 1. A semiconductor device , comprising:a semiconductor substrate;a front surface electrode being in contact with a front surface of the semiconductor substrate;a rear surface electrode being in contact with a rear surface of the semiconductor substrate, whereinthe semiconductor substrate comprises:an element region overlapping with a contact surface between the front surface electrode and the semiconductor substrate in a planar view along a thickness direction of the semiconductor substrate, and comprising a semiconductor element configured to electrically connect the front surface electrode and the rear surface electrode; and a plurality of p-type guard rings exposed on the front surface and surrounding the element region in a pattern of layers of rings; and', 'an n-type peripheral drift region separating the plurality of guard rings from each other,, 'a peripheral voltage withstanding region located around the element region and comprisingwherein the plurality of guard rings comprises:a plurality of inner circumferential guard rings; anda plurality of outer ...

JUNCTION BARRIER SCHOTTKY DIODE AND MANUFACTURING METHOD THEREOF

The present invention discloses a junction barrier Schottky (JBS) diode and a manufacturing method thereof. The JBS diode includes: an N-type gallium nitride (GaN) substrate; an aluminum gallium nitride (AlGaN) barrier layer, which is formed on the N-type GaN substrate; a P-type gallium nitride (GaN) layer, which is formed on or above the N-type GaN substrate; an anode conductive layer, which is formed at least partially on the AlGaN barrier layer, wherein a Schottky contact is formed between part of the anode conductive layer and the AlGaN barrier layer; and a cathode conductive layer, which is formed on the N-type GaN substrate, wherein an ohmic contact is formed between the cathode conductive layer and the N-type GaN substrate, and the cathode conductive layer is not directly connected to the anode conductive layer. 1. A junction barrier Schottky (JBS) diode comprising:an N-type gallium nitride (GaN) substrate;an aluminum gallium nitride (AlGaN) barrier layer, which is formed on the N-type GaN substrate;a P-type gallium nitride (GaN) layer, which is formed on the AlGaN barrier layer or on the N-type GaN substrate;an anode conductive layer, which is formed at least partially on the AlGaN barrier layer, wherein a Schottky contact is formed between part of the anode conductive layer and the AlGaN barrier layer; anda cathode conductive layer, which is formed on the N-type GaN substrate, wherein an ohmic contact is formed between the cathode conductive layer and the N-type GaN substrate, and the cathode conductive layer is not directly connected to the anode conductive layer.2. The JBS diode of claim 1 , wherein the P-type GaN layer is formed on the AlGaN barrier layer claim 1 , and the P-type GaN layer and the N-type GaN substrate are separated by the AlGaN barrier layer.3. The JBS diode of claim 2 , wherein a Schottky diode is formed by the anode conductive layer claim 2 , the AlGaN barrier layer claim 2 , the N-type GaN substrate claim 2 , and the cathode ...