Method and apparatus for obfuscating an integrated circuit with camouflaged gates and logic encryption
Номер патента: EP3516555A1
Опубликовано: 31-07-2019
Автор(ы): Bryan J. WANG, James P. Baukus, Lap Wai Chow, Ronald P. Cocchi
Принадлежит: Inside Secure SA
Опубликовано: 31-07-2019
Автор(ы): Bryan J. WANG, James P. Baukus, Lap Wai Chow, Ronald P. Cocchi
Принадлежит: Inside Secure SA
Реферат: A method and apparatus for obfuscating at least a portion of an integrated circuit is disclosed. In one embodiment, the method comprises computing a number of observable points (COP) for each net of the portion of the integrated circuit, computing a selection weight (WS) for each net, and selecting one or more nets for insertion of at least one protection element based on the computed selection weights (WS).
Method (and related apparatus) that reduces cycle time for forming large field integrated circuits
Номер патента: US11081352B2. Автор: Wen-Chen LU,Yi-Min Chen,Ming-Chang Hsieh. Владелец: Taiwan Semiconductor Manufacturing Co TSMC Ltd. Дата публикации: 2021-08-03.