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Rapid estimation of the uncertainty of the output of a neural task network

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PULSE AMPLITUDE CONVERTER1 The invention relates to a pulse technique and can be used in devices for converting amplitudes and amplitude selection of pulses. Pulse amplitude transducers are known, which contain an amplitude-storage element, a key, and an output pulse generator. the possibility of obtaining the amplitude of the output pulses, equal to the difference between a given constant value and the amplitude of the input pulses, and inverting the amplitudes, which would allow using them, for example, together with threshold devices for selecting pulses with an amplitude below the set threshold. The purpose of the invention is to obtain an amplitude of output pulses equal to the difference between 20 predetermined constant value and amplitude of input pulses By the fact that in the proposed pulse amplitude converter, made on the basis of a core of a material with a rectangular hysteresis loop (GHP) with four windings, the first winding is connected by beginning through a diode d and a differentiating circuit to the input terminal of the device, the second winding is connected in series with the load of the shaper of the core installation signal in the “O” state, the third is connected in series with the load of the shaper of the core installation signal into the 1 state; the end of the first winding is connected to the grounded pole of the power source, the end of the second and the beginning of the third winding • —to the negative pole of the power source, the fourth winding is connected to the output of the core signal in the “O” state by the end, and through the diode and differentiating the circuit to the output terminal of the device. In the drawing, the diagram of the device is shown. The converter contains a core 1 with a cross circuit voltage switch, carrying four windings, a signal generator setting the core zero 2, a signal generator setting the ser 3. In the input I and output IV circuits of the windings, there are RC circuits connected through diodes. The converter operates as follows. In the absence of input pulses, core 1 is in the initial position "1" corresponding to the limiting magnetization + 5, and drivers 2 and 3 - in standby mode. The diode in the output winding circuit of the IV core is locked with a negative voltage taken from the switching output of the driver 2.

Номер патента: SU459851A1. Автор: Владимир Филиппович Дубовицкий,Яков Исаакович Хавкин,Владимир Степанович Сухотин. Владелец: Предприятие П/Я Г-4312. Дата публикации: 1975-02-05.

DEVICE FOR MEASURING ANGLES | WITH MOVEMENTSff -L21The invention is not related to the field of nifferent electric drive and discrete automation. There are known devices for generating angular displacements that contain a disk with holes evenly spaced around the circumference, fixed reading elements and a logic circuit connected to reversible pulse counter. The proposed device differs from the known. The fact that the adder and the inverter are entered into Herq, the outputs of the reading elements are connected to the inputs of the adder, and the output of one count The pinch element is connected to the logic circuit through the inverter, the outputs of the matrix, and another capacitance element is connected to the outputs of the lower digits of the output code of the device. This improves the performance of the device. In FIG. 1 depicted the scheme of the proposed device; in fig. 2 and a diagram explaining its operation. The device contains a disk / with holes and reading elements 2 and 3, with the opening width h being equal to the distance between adjacent holes, and the distance between the two-reading elements is equal to - 2 hn, • where is an integer number (1015202. T30 / 7 = 0 in Fig. 1). The output of the reading element 3 is connected to an inverter 4, the output of which is connected to the spreading input of the logic circuit 5. The output of the reading element 2 is connected to the second input of the logic circuit 5, the output [> & [which connects 1s to the corresponding To the inputs of a two-stage reverse binary counter 6. The inputs of both reading elements' 2 and 3 are connected to the inputs; Sum'Mator 7 modulo "2". 1 '] 11; a circuit 5, in turn, consists of an inverter 8, waiting for multivibrators 9, 10, and coincidence circuits 11,' G2. The proposed device output of the sum of the matrix 7 is considered as a junior "! the bit code of the angular displacement, the output of the reading element 2 as the second bit, and the outputs of the counter 6 as the subsequent first digit of the specified code. This increase in the digit of the code of the angular displacement by two small binary digits leads to an increase in the accuracy of the measurement Four times. Disk rotation / at the outputs of elements 2 and 3 alternate. potentials of high and low level (see. Fig. 2), the low urovei corresponds \ 'yuschy location openings against the read element is received per unit, and the high voltage level corresponding to the spacing between The relative

Номер патента: SU432565A1. Автор: И. Д. Розов Ю. Фельдман В. И. Холодный изобретени В. С. Рафф. Владелец: Украинский государственный проектный институт жпромэлектропроект. Дата публикации: 1974-06-15.

A DEVICE FOR RESEARCH OF PROBABLE GRAPHS WITH RESTRICTIONS between them does not exceed a predetermined value. A device is known to simulate probability graphs containing its memorized vertex triggers, controllable key vertex schemes, the AND scheme is memorized, and the trigger of edges, controllable key schemes of edges, keys, distributor, delay line, counter, clock signal key, bus for outputting the results of the vertex and edge state drawing, widening of the conductivity test and the reset bus. It is impossible to determine the characteristics of the connectivity of a probabilistic graph with the constraint imposed by connectivity in this device. The purpose of the objectivity is the possibility of determining the connectivity characteristics of probabilistic graphs when imposing constraints on connectivity. ystvo introduced additional storage triggers vertices, controlled by the key circuit nodes controlled by the key circuit reber.skhema "AND" and "OR" bus circuit and reset. The unit inputs of the additional memorized trigger points of the vertices are connected to the corresponding outputs of the distributor 5 and to the outputs of the corresponding OR circuits. The reset inputs to the zero position of the additional memory triggers of the vertices are connected to the reset bus, and their single outputs to the corresponding inputs of the additional AND circuit and to the control inputs of the corresponding additional controlled key vertex circuits whose inputs are connected to the output of the clock key signals, and the outputs are connected by the inputs of the respective 15 “OR” schemes and are connected to a diagram representing a graph with the outputs of additional controlled key edge circuits, the control inputs of which are connected to the single outputs corresponding trigger-memory-20 ditch ribs. The output of the additional AND circuit is connected to the control input of the clock signal key and to the input of the delay line. Diagram of the device shown in the drawing. The device contains memory triggers of 25 vertices 1, which are connected to controlled key circuits of vertices 2 with one input 3 and several outputs 4; memory triggers of edges 5, connected to controllable key schemes of edges 6 with two 30 moves 7 and to additional controllable

Номер патента: SU435536A1. Автор: . Владелец: . Дата публикации: 1974-07-05.

DEVICE FOR RECEIVING DISCRETE INFORMATION The proposed device relates to the field of telemechanics and can be used to implement computer communication with external objects in information and control systems. pulses by duration, logical “AND” elements, the first 10 inputs of which are connected to the output of the pulse selector by duration, and the outputs are connected to the first inputs of memory elements , the logical element "OR" and the key. However, the known devices are complex and not very reliable in operation. The proposed device differs in that it contains an information channel number encoder. The outputs of this encoder are connected to the second inputs of the corresponding “AND” logic elements, and the outputs are connected to the inputs of the OR logic element, the output of which is connected to the input of the pulse selector in amplitude. The key input is connected to the output of the pulse selector 25 in duration, and the output is connected to the second inputs of the memory elements. This significantly simplifies the device and thereby increases the reliability of its operation. 30 The drawing shows the block diagram of the proposed device. channel 1, the logical element "OR" 2, the pulse selector in amplitude 3, the pulse selector in duration 4, the logic elements "AND" 5i — 5l, elements of name 6i — 6 "and key 7. The operation of the proposed device occurs next uyuschim obrazom.Signaly information alternately to the inputs of the encoder number information channel 1, which converts a decimal code for information channel number which the signal was received, in binary code. At the same time, information signals through the logical element "1-1LI" 2 are supplied to the input of the pulse selector in amplitude 3. If the amplitude of the incoming signal matches the reference value from the pulse selector in amplitude 3, a signal arrives at the input of the pulse selector the duration of the reference is sent to one of the inputs of the AND logic elements 5i — 5, j and to the control input of the key 7. At the same time, the other inputs of the AND logic elements 5i — 5 "receive in binary code the signals from the cipher outputs ora traffic channel number 1 defining the channel number on which the signal was received on the device .The inputs. In this case, the corresponding logical elements “AND” are triggered, and from their outputs, the signals are fed to the inputs of the memory elements.

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