ELECTRONIC COMPONENT WITH LAMINATED SUBSTRATE

Disclosed is an electronic component with a laminated substrate that can prevent the occurrence of cracks and delamination near the interface of a conductor pattern and a dielectric layer. The laminated substrate includes: a plurality of dielectric layers laminated together; a first conductor pattern (20) positioned along a main surface (12a) of the dielectric layer (12) and connected electrically to ground; and second conductor patterns (22, 24) positioned along the main surface of the dielectric layer, facing the first conductor pattern (20) through the dielectric layer only, and forming an inductor element. Only the dielectric layers on both sides of the first conductor pattern (20) are bonded together via openings (20a to 20h) in the first conductor pattern (20). When perspectively viewed from the laminated direction, the entirety of the second conductor patterns (42, 44) overlap, except for the openings (20a to 20h) in the first conductor pattern (20).