In-street integrated circuit wafer via

Resistor fabrication

SEMICONDUCTOR DEVICES HAVING SUPERCONDUCTING INTERCONNECTS

A semiconductor device which includes either a single semiconductor chip bearing an integrated circuit (IC) or two or more electrically interconnected semiconductor chips, is disclosed. This device includes interconnects between device components (on the same chip and/or on different chips), at least one of which includes a region of superconducting material, e.g., a region of copper oxide superconductor having a Tc greater than about 77K. Significantly, to avoid undesirable interactions, at high processing temperatures, between the superconducting material and underlying, silicon-containing material (which, among other things, results in the superconducting material reverting to its nonsuperconducting state), the interconnect also includes a combination of material regions which prevents such interactions.

적층된 다이 어셈블리들을 위한 Ｚ-상호연결와 다이 패드 간의 전기 커넥터

... 프로세싱의 웨이퍼 레벨에서 다이 패드들 상에 커넥터들을 형성하는 방법들은, 다이 패드들 위에 경화가능한 전기 전도성 물질의 스팟들을 형성하고 이를 상호연결 다이 에지로 또는 그 위로 연장하는 단계; 상기 전도성 물질을 경화시키는 단계; 및 그 후에 웨이퍼 절단 단계에서 그 스팟들을 절단하는 단계를 포함한다. 또한, 그러한 방법들에 의해 z-상호연결 커넥터들로의 다이패드들이 형성되며, 따라서 형태가 이루어지고 크기가 결정된다. 또한, 적층된 다이 어셈블리들 및 적층된 다이 패키지들은 그러한 방법들에 따라 준비되는 다이를 포함하고, 그러한 방법들에 의해 형성되고 그에따라 형태가 이루어지고 디멘젼이 결정되는 z-상호연결 커넥터들로의 다이 패드를 갖는다.

Chip package and method for forming the same

An embodiment of the invention provides a chip package which includes: a first substrate; a second substrate disposed on the first substrate, wherein the second substrate includes a lower semiconductor layer, an upper semiconductor layer, and an insulating layer therebetween, and a portion of the lower semiconductor layer electrically contacts with at least one pad on the first substrate; a conducting layer disposed on the upper semiconductor layer of the second substrate and electrically connected to the portion of the lower semiconductor layer electrically contacting with the at least one pad; an opening extending from the upper semiconductor layer towards the lower semiconductor layer and extending into the lower semiconductor layer; and a protection layer disposed on the upper semiconductor layer and the conducting layer, wherein the protection layer extends onto a portion of a sidewall of the opening, and does not cover the lower semiconductor layer in the opening.

Package structure and manufacture method thereof

A package structure including a semiconductor die, an insulating encapsulant, a dielectric layer, and a redistribution layer is provided. The semiconductor die has an active surface, a back surface opposite to the active surface, and a plurality of conductive bumps disposed on the active surface. The insulating encapsulant is encapsulating the semiconductor die. The redistribution layer is disposed on the he insulating encapsulant and electrically connected to the plurality of conductive bumps. The dielectric layer is disposed between the insulating encapsulant and the redistribution layer, wherein the dielectric layer encapsulates at least a portion of each of the plurality of conductive bumps. A manufacturing method of the package structure is also provided.

Chip structure and manufacturing method thereof

A chip structure includes a first substrate, a second substrate, a conductive via, and a redistribution layer. The first substrate has a first inclined sidewall. The second substrate is located on a bottom surface of the first substrate, and has an upper portion and a lower portion. The lower portion protrudes from the upper portion. The upper portion is between the first substrate and the lower portion. The upper portion has a second inclined sidewall, and a slope of the first inclined sidewall is substantially equal to a slope of the second inclined sidewall. The conductive via is in the lower portion. The redistribution layer extends from a top surface of the first substrate to a top surface of the lower portion of the second substrate sequentially along the first inclined sidewall and the second inclined sidewall, and is electrically connected to the conductive via.

Stacked chip package and method for forming the same

Light-emitting device, light-emitting element and method of manufacturing same

SEMICONDUCTOR DEVICE, THREE-DIMENSIONAL MOUNTING SEMICONDUCTOR APPARATUS, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Stacked semiconductor devices constitute a three-dimensional mounting semiconductor apparatus. Such a semiconductor device comprise a silicon semiconductor substrate on a major surface of which an integrated circuit part and an electrode pad are provided. A hole is made in the silicon semiconductor substrate by etching using the electrode pad as an etching stopper layer. A buried electrode is provided in this hole and used for electrical connection of the electrode pad to the back major surface of the silicon semiconductor substrate.

Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument

A groove is formed on a semiconductor substrate having integrated circuits and electrodes from a first surface. An insulating layer is formed on an inner surface of the groove. A conductive layer is formed on the insulating layer above the inner surface of the groove. A second surface of the semiconductor substrate opposite to the first surface is ground until the groove is exposed to divide the semiconductor substrate into a plurality of semiconductor chips in which the conductive layer is exposed on a side surface of each semiconductor chip. The semiconductor chips are then stacked. The conductive layer of one of the semiconductor chips is electrically connected to the conductive layer of another one of the semiconductor chips.

Semiconductor package having a redistribution line structure

A semiconductor package may include a first semiconductor chip having first bonding pads on a first active surface. The semiconductor package may include a second semiconductor chip having second bonding pads which are arranged on a second active surface. The first and second semiconductor chips are stacked such that the first and second active surfaces face each other.

INTERCONNECT LAYER CONTACT AND METHOD FOR IMPROVED PACKAGED INTEGRATED CIRCUIT RELIABILITY

Packaged photosensor ICs are made by fabricating an integrated circuit (IC) with multiple bondpads; forming vias from IC backside through semiconductor to expose a first layer metal; depositing conductive metal plugs in the vias; depositing interconnect metal; depositing solder-mask dielectric over the interconnect metal and openings therethrough; forming solder bumps on interconnect metal at the openings in the solder-mask dielectric; and bonding the solder bumps to conductors of a package. The photosensor IC has a substrate; multiple metal layers separated by dielectric layers formed on a first surface of the substrate into which transistors are formed; multiple bondpad structures formed of at least a first metal layer of the metal layers; vias with metal plugs formed through a dielectric over a second surface of the semiconductor substrate, interconnect metal on the dielectric forming connection shapes, and shapes of the interconnect layer coupled to each conductive plug and to solder ...

METHOD AND MOLD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND METHOD FOR MOUNTING THE DEVICE

A method includes a resin sealing step of placing, in a cavity 28 of a mold 20, a substrate 16 to which semiconductor elements 11 on which bumps 12 are arranged, a resin sealing step of supplying resin 35 to positions of the bumps 12 so that a resin layer 13 sealing the bumps 12 is formed, a protruding electrode exposing step of exposing at least ends of the bumps 12 sealed by the resin layer 13 so that ends of the bumps 12 are exposed from the resin layer 13, and a separating step of cutting the substrate 16 together with the resin layer 13 so that the semiconductor elements 11 are separated from each other.

IMAGING MODULE AND METHOD OF MANUFACTURING THE SAME

An imaging module of the invention includes: an imaging element; and a substrate positioned on a rear surface opposite to an imaging surface of the imaging element and provided to extend from the rear surface to a side opposite to the imaging surface. An electrode pad provided on the rear surface of the imaging element and a front end portion of an electrode pad provided on a main surface of the substrate at a position close to the imaging element are electrically connected via a conductive connecting material portion. A notch portion recessed from a distal end of the front end portion is formed at the front end portion of the electrode pad of the substrate.

SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor die having an insulative layer and a conductive feature in the insulative layer, and a shield in contact with a lateral surface of the conductive feature. In some embodiments, the lateral surface of the conductive feature is aligned with an edge of the insulating material. 2. The semiconductor device of claim 1 , wherein the insulative layer surrounds the semiconductor die.3. The semiconductor device of claim 1 , wherein a height of the conductive feature is substantially equal to a thickness of the insulative layer.4. The semiconductor device of claim 1 , further comprising an insulative material isolated from the insulative layer by the conductive feature claim 1 , and the insulative material includes a lateral surface aligned with the lateral surface of the conductive feature and the edge of the insulative layer.5. The semiconductor device of claim 4 , wherein the conductive feature has a substantially semi-circular cross-sectional shape or a substantially U cross-sectional shape.6. The semiconductor device of claim 1 , wherein the conductive feature further includes one or more extension portions extended toward a direction opposite to the edge of the insulative layer.7. The semiconductor device of claim 1 , further comprising a ground terminal over a bottom surface of the insulative layer claim 1 , wherein the shield is electrically connected to the ground terminal through the conductive feature.8. The semiconductor device of claim 1 , further comprising an active redistribution layer (RDL) over the insulative layer and electrically connected to the semiconductor die.9. The semiconductor device of claim 8 , wherein the conductive feature is electrically disconnected from the active RDL.11. The semiconductor device of claim 10 , wherein a height of the conductive feature is substantially equal to a thickness of the first insulative layer.12. The semiconductor device of claim 10 , further comprising:a second ...

MULTI-DIE SEMICONDUCTOR STRUCTURE WITH INTERMEDIATE VERTICAL SIDE CHIP AND SEMICONDUCTOR PACKAGE FOR SAME

Semiconductor multi-die structures having intermediate vertical side chips, and packages housing such semiconductor multi-die structures, are described. In an example, a multi-die semiconductor structure includes a first main stacked dies (MSD) structure having a first substantially horizontal arrangement of semiconductor dies. A second MSD structure having a second substantially horizontal arrangement of semiconductor dies is also included. An intermediate vertical side chip (i-VSC) is disposed between and electrically coupled to the first and second MSD structures. 1. A semiconductor package , comprising:a substrate;a main stacked dies (MSD) structure comprising a substantially horizontal arrangement of semiconductor dies interconnected to the substrate; anda vertical side chip electrically coupled to a side of the MSD structure, wherein the vertical side chip comprises one or more through silicon vias (TSVs).2. The semiconductor package of claim 1 , wherein the vertical side chip is electrically coupled to the side of the MSD structure through one or more interconnections of the vertical side chip.3. The semiconductor package of claim 2 , wherein the one or more interconnections of the vertical side chip are disposed on an active side of the vertical side chip.4. The semiconductor package of claim 2 , wherein an interconnection of the one or more interconnections of the vertical side chip is coupled to the MSD structure through a die side pad (DSP) of the MSD structure.5. The semiconductor package of claim 2 , wherein an interconnection of the one or more interconnections of the vertical side chip is coupled to the MSD structure through an end of metal routing of a die in the MSD structure.6. The semiconductor package of claim 1 , wherein the vertical side chip is interconnected to the substrate.7. The semiconductor package of claim 6 , wherein the vertical side chip is interconnected to the substrate through a die side pad (DSP) of the vertical side chip.8. The ...

Interconnect structure with redundant electrical connectors and associated systems and methods

Semiconductor die assemblies having interconnect structures with redundant electrical connectors are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die, a second semiconductor die, and an interconnect structure between the first and the second semiconductor dies. The interconnect structure includes a first conductive film coupled to the first semiconductor die and a second conductive film coupled to the second semiconductor die. The interconnect structure further includes a plurality of redundant electrical connectors extending between the first and second conductive films and electrically coupled to one another via the first conductive film.

Image pickup apparatus, semiconductor apparatus, and image pickup unit

An image pickup apparatus includes: an image pickup chip including a light receiving section and electrode pads, on a first main face, and a plurality of connection electrodes, each of which is connected to each of the electrode pads via each of a plurality of through-hole interconnections, on a second main face; a transparent cover glass having a larger plan-view dimension than the image pickup chip; a transparent adhesive layer that bonds the first main face of the image pickup chip and the cover glass; and a sealing member that covers a side face of the image pickup chip and a side face of the adhesive layer, and is made of an insulating material having a same plan-view dimension as the cover glass.

Pad configurations for an electronic package assembly

Embodiments of the present disclosure provide an electronic package assembly comprising a solder mask layer, the solder mask layer having at least one opening, and a plurality of pads coupled to the solder mask layer, wherein at least one pad of the plurality of pads includes (i) a first side, (ii) a second side, the first side being disposed opposite to the second side, (iii) a terminal portion and (iv) an extended portion, wherein the first side at the terminal portion is configured to receive a package interconnect structure through the at least one opening in the solder mask layer, the package interconnect structure to route electrical signals between a die and another electronic device that is external to the electronic package assembly, and wherein the second side at the extended portion is configured to receive one or more electrical connections from the die.

Semiconductor chip and semiconductor device using the same, and method of fabricating semiconductor chip

A semiconductor chip in which a through hole penetrating through its surface and reverse surface is formed in a scribe line region in the vicinity of an active region where a functional device is formed, and a conductive member is arranged in the through portion. The through portion may be a groove opening sideward on a sidewall surface of the semiconductor chip. The through portion may be a through hole blocked from a side part of the semiconductor chip. The semiconductor chip may further include wiring for electrically connecting an internal circuit formed in the active region and the conductive member to each other.

SINTERED SOLDER FOR FINE PITCH FIRST-LEVEL INTERCONNECT (FLI) APPLICATIONS

Foundation layers and methods of forming a foundation layer are described. Die pads are formed over a die. A dielectric layer is formed over die pads and the die. The dielectric layer is then recessed to expose top portions of the die pads. A first plurality of sintered conductive vias are formed over the die pads. The first sintered conductive vias are coupled to at least one of the die pads. In addition, a photoresist layer may be formed over the dielectric layer and the top portions of the die pads. Via openings are formed in the photoresist layer. A second plurality of sintered conductive vias may then be formed over the first sintered conductive vias to form a plurality of sintered conductive lines. Each of the first and second sintered conductive vias are formed with a liquid phase sintering (LPS) solder paste.

Semiconductor Device with Shield for Electromagnetic Interference

A semiconductor device includes a first die embedded in a molding material, where contact pads of the first die are proximate a first side of the molding material. The semiconductor device further includes a redistribution structure over the first side of the molding material, a first metal coating along sidewalls of the first die and between the first die and the molding material, and a second metal coating along sidewalls of the molding material and on a second side of the molding material opposing the first side.

Semiconductor packages and methods of formation thereof

In one embodiment, a semiconductor package includes a vertical semiconductor chip having a first major surface on one side of the vertical semiconductor chip and a second major surface on an opposite side of the vertical semiconductor chip. The first major surface includes a first contact region and the second major surface includes a second contact region. The vertical semiconductor chip is configured to regulate flow of current from the first contact region to the second contact region along a current flow direction. A back side conductor is disposed at the second contact region of the second major surface. The semiconductor package further includes a first encapsulant in which the vertical semiconductor chip and the back side conductor are disposed.

Method of bonding integrated circuit chip to display panel, and display apparatus

The present application provides a method of bonding an integrated circuit chip to a display panel. The method includes forming a plurality of first bonding pads in a bonding region on a first side of the display panel; forming a plurality of vias extending through the display panel in the bonding region; subsequent to forming the plurality of vias, disposing an integrated circuit chip having a plurality of second bonding pads on a second side of the display panel substantially opposite to the first side, the plurality of second bonding pads being on a side of the integrated circuit chip proximal to the display panel; and electrically connecting the plurality of first bonding pads respectively with the plurality of second bonding pads by forming a plurality of connectors respectively in the plurality of vias.

METHOD AND MOLD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND METHOD FOR MOUNTING THE DEVICE

A method for manufacturing semiconductor devices includes a resin sealing step of putting a substrate (16) on which bumps (12) and a plurality of semiconductor chips (11) are arranged in the cavity (28) of a mold (20) and supplying a resin (35) to the region where the bumps (12) are provided so as to coat the bumps (12) and form a resin layer (13), a protruded electrode exposing step of exposing at least the front end sections of the bumps (12) coated with the resin layer (13) from the layer (13), and a separating step of separating the semiconductor chips (11) into individual chips (11) by cutting the substrate (16) together with the layer (13).

Verfahren zur Herstellung von Halbleiterbauelementen mit externen Kontaktierungen

Das erfindungsgemäße Verfahren sieht vor, einen Träger 1 bereitzustellen, in welchem ein oder mehrere Halbleiterbauelemente zwischen Grenzlinien 100 angeordnet sind, wobei ein Halbleiterkontaktierungsbereich 3 des Halbleiterbauelements in einer ersten Oberfläche 200 des Trägers 1 liegt. Danach werden konischförmige Gräben 102 mit schrägen Seitenwänden 108 in den Träger eingebracht, wobei die schrägen Seitenwände 108 entlang der Grenzlinien 100 verlaufen. In einem nachfolgenden Verfahrensschritt wird eine Umverdrahtungseinrichtung 5 gebildet, welche mindestens einen der Halbleiterkontaktierungsbereiche 3 mit einer der schrägen Seitenwände 108 eines Grabens 102 verbindet. Danach wird der Träger 1 von einer Seite her abgedünnt, welche der ersten Oberfläche 200 gegenüberliegt. Dabei wird der Träger 1 mindestens so lange abgedünnt, bis der Grabenboden 103 freigelegt wird. Nach dem Entfernen des adhäsiven Trägers 6, welcher unmittelbar vor dem Abdünnen des Trägers 1 aufgebracht wurde, ergeben ...

Production of a chip-like semiconductor component used as a FET chip comprises using chip side edges for contacting an electrode of the component

Production of a chip-like semiconductor component comprises using chip side edges (5) for contacting at least one electrode of the component. Preferred Features: The chip side edge is used as a drain contact. The drain contact is produced by partially metallizing a chip side edge in a front-end process. During production of the metallized sections on the chip side edges, the edge of the chip front side is structured to produce trenches up to 100 microns m depth in the wafer. An electrical insulating layer (9) is applied on the chip rear side (3).

Halbleiteranordnung und Verfahren zur Herstelllung von Halbleiteranordnungen

Die vorliegende Anmeldung betrifft eine Halbleiteranordnung umfassend einen Halbleiterchip, einen den Halbleiterchip überdeckenden ausgeformten Körper, wobei der ausgeformte Körper ein Array ausgeformter Strukturelemente umfasst, und erste Lotelemente in Eingriff mit den ausgeformten Strukturelementen.

Halbleiteranordnungen mit supraleitenden Verbindungen.

Chip package, wafer level chip array and manufacturing method thereof

Semiconductor device and manufacturing method thereof

Integrated circuit packaging technology and small form factor or wearable device configuration

Semiconductor device and semiconductor die around the method of forming the insulating layer

METHOD OF ASSEMBLING AND ENCAPSULATION OF MICROBATTERIES LITHIUM AND RESULTING MICROBATTERY

소형 폼 팩터 또는 웨어러블 디바이스를 위한 집적 회로 패키징 기술, 구성, 장치, 조립체 및 방법

... 본 발명의 실시예들은 소형 폼 팩터 또는 웨어러블 디바이스들을 위한 집적 회로(IC) 패키징 기술들 및 구성들에 관한 것이다. 일 실시예에서, 장치는 제 1 면 및 제 1 면에 대향 배치된 제 2 면, 및 제 1 면과 제 2 면 사이에 배치된 측벽을 갖는 기판과 - 측벽은 기판의 둘레를 정의함 -, 기판의 제 1 면과 제 2 면 사이에 배치된 복수의 기판 관통 비아(TSV)와, 제 1 면 상에 배치된 제 1 유전층 - 제 1 유전층은 제 1 유전층의 평면에서 하나 이상의 다이의 전기 신호들을 라우팅하기 위한 전기 라우팅 피처들을 포함함 -을 포함할 수 있다. 다른 실시예들이 설명되고/되거나 청구될 수 있다.

Integrated circuit packaging techniques and configurations for small form-factor or wearable devices

Embodiments of the present disclosure are directed toward integrated circuit (IC) packaging techniques and configurations for small form-factor or wearable devices. In one embodiment, an apparatus may include a substrate having a first side and a second side disposed opposite to the first side and a sidewall disposed between the first side and the second side, the sidewall defining a perimeter of the substrate, and a plurality of through-substrate vias (TSVs) disposed between the first side and the second side of the substrate, and a first dielectric layer disposed on the first side and including electrical routing features to route electrical signals of one or more dies in a plane of the first dielectric layer. Other embodiments may be described and/or claimed.

A packaging method and structure for an image sensing chip

A packaging method and structure for an image sensing chip is provided. The packaging method includes: providing a wafer having a first surface and a second surface opposite to the first surface, the wafer including multiple image sensing chips arranged in a grid, and the image sensing chip including an image sensing region and a pad which are located at the side of the first surface; forming a cutting groove and a hole corresponding to the pad on the second surface of the wafer, the pad being exposed through the hole; filling the cutting groove with a first photosensitive ink; coating the second surface of the wafer with a second photosensitive ink to cause the second photosensitive ink to cover the hole with a cavity being formed in the hole. The packaging structure of the image sensing chip formed by the method can effectively avoid contact of the second photosensitive ink with the bottom of the hole, which improves the yield of packaging the image sensing chip and improves the reliability ...

Wafer level chip scale package

A semiconductor device, a method of manufacturing semiconductor devices and a circuit package assembly are described. A semiconductor device can have a semiconductor substrate with first and second surfaces and a sidewall between them. First and second conductive pads on the first and second surfaces are in electrical contact with corresponding first and second semiconductor device structures in the substrate. An insulator layer on the first surface and sidewall covers a portion of the first conductive pad on the first surface. An electrically conductive layer on part of the insulator layer on the first conductive pad and sidewall is in electrical contact with the second conductive pad. The insulator layer prevents the conductive layer from making electrical contact between the first and second conductive pads.

Image sensor package and fabrication method thereof

An image sensor package includes an image sensor die having an active side and a backside, wherein an image sensor device region and a bond pad are provided on the active side. A through-silicon-via (TSV) structure extending through the thickness of the image sensor die is provided to electrically connect the bond pad. A multi-layer re-distributed interconnection structure is provided on the backside of the image sensor die. A solder mask or passivation layer covers the multi-layer re-distributed interconnection structure.

APPARATUSES COMPRISING SEMICONDUCTOR DIES IN FACE-TO-FACE ARRANGEMENTS

CHIP PACKAGE AND MANUFACTURING METHOD THEREOF

A chip package includes a semiconductor substrate, a supporting element, an antenna layer, and a redistribution layer. The semiconductor substrate has an inclined sidewall and a conductive pad that protrudes from the inclined sidewall. The supporting element is located on the semiconductor substrate, and has a top surface facing away from the semiconductor substrate, and has an inclined sidewall adjoining the top surface. The antenna layer is located on the top surface of the supporting element. The redistribution layer is located on the inclined sidewall of the supporting element, and is in contact with a sidewall of the conductive pad and an end of the antenna.

Semiconductor Device and Method of Stacking Semiconductor Die in Mold Laser Package Interconnected By Bumps and Conductive Vias

A semiconductor wafer contains a plurality of first semiconductor die. The semiconductor wafer is mounted to a carrier. A channel is formed through the semiconductor wafer to separate the first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. An encapsulant is deposited over the carrier and first semiconductor die and into the channel while a side portion and surface portion of the second semiconductor die remain exposed from the encapsulant. A first conductive via is formed through the encapsulant in the channel. A second conductive via is formed through the encapsulant over a contact pad of the first semiconductor die. A conductive layer is formed over the encapsulant between the first and second conductive vias. An insulating layer is formed over the conductive layer and encapsulant. The carrier is removed. An interconnect structure is formed over the first conductive via.

Integrated circuit package having large conductive area and method for fabricating the same

An integrated circuit package having large conductive area and method for fabricating the same is provided. The package includes an integrated circuit chip having upper and lower surfaces and a photosensitive device formed on the upper surface. A bonding pad is subsequently formed on the upper surface of the integrated circuit chip and electrically connected to the photosensitive device. A conductive layer is then formed on a sidewall of the integrated circuit chip and wrapped around an edge of the bonding pad to electrically connect to the bonding pad. In the package, the conductive layer is in contact with the upper and lower surfaces and a sidewall of the bonding pad. Because the conductive layer is wrapped around the edge of the bonding pad, contact surface and structural strength between the conductive layer and the bonding pad are increased.

Self-organizing network with chip package having multiple interconnection configurations

In general, embodiments of the present invention provide a chip package with multiple TSV configurations. Specifically, the chip package typically includes a backend layer (e.g., metal interconnect layer); a substrate coupled to the backend layer; a set (at least one) of backend side interconnects extending (e.g., angularly) from a side surface of the backend layer to a bottom surface of the backend layer; a set of optional vertical TSVs extending from a top surface of the backend layer through the substrate; and a network organizer positioned in the substrate organizer for handling communications made using the set of backend side interconnects and the set of vertical TSVs. A set of connections (e.g., controlled collapse chip connections (C4s) can be positioned adjacent to any of the vias to provide connectively to other hardware elements such as additional chip packages, buses, etc. Among other things, the use of backend side interconnects allows maximum surface area of the chip package ...

WAFER LEVEL ARRAY OF CHIPS AND METHOD THEREOF

A wafer level array of chips is provided. The wafer level array of chips comprises a semiconductor wafer, and a least one extending-line protection. The semiconductor wafer has at least two chips, which are arranged adjacent to each other, and a carrier layer. Each chip has an upper surface and a lower surface, and comprises at least one device. The device is disposed upon the upper surface, covered by the carrier layer. The extending-line protection is disposed under the carrier layer and between those two chips. The thickness of the extending-line protection is less than that of the chip. Wherein the extending-line protection has at least one extending-line therein. In addition, a chip package fabricated by the wafer level array of chips, and a method thereof are also provided.

Wafer level package having a stress relief spacer and manufacturing method thereof

In a semiconductor device package having a stress relief spacer, and a manufacturing method thereof, metal interconnect fingers extend from the body of a chip provide for chip interconnection. The metal fingers are isolated from the body of the chip by a stress-relief spacer. In one example, such isolation takes the form of an air gap. In another example, such isolation takes the form of an elastomer material. In either case, mismatch in coefficient of thermal expansion between the metal interconnect fingers and the body of the chip is avoided, alleviating the problems associated with cracking and delamination, and leading to improved device yield and device reliability.

Manufacturing Method of Semiconductive Element and Ink Jet Head Substrate

A semiconductor device includes a lateral end surface and a connection electrode for external electrical connection. The connection electrode is exposed at the side surface. A manufacturing method of the semiconductor device includes steps of forming a linear recess in a silicon substrate between adjacent semiconductor devices, forming, on an inner surface of the recess, the electrode for external electrical connection of one of the semiconductor devices, and a step of separating the one semiconductor device from another on the silicon substrate by cutting the silicon substrate along the linear recess. Forming the electrode includes steps of forming a metal thin film astride a cutting line at which the silicon substrate is to be cut, forming a resist layer and patterning the resist layer on the metal thin film, growing metal at a portion not having the patterned resist layer, and removing the patterned resist layer and the metal thin film below the patterned resist layer. The connection ...

Integrated Fan-Out Package with 3D Magnetic Core Inductor

Among other things, a method of fabricating an integrated electronic device package is described. First trace portions of an electrically conductive trace are formed on an electrically insulating layer of a package structure, and vias of the conductive trace are formed in a sacrificial layer disposed on the electrically insulating layer. The sacrificial layer is removed, and a die is placed above the electrically insulating layer. Molding material is formed around exposed surfaces of the die and exposed surfaces of the vias, and a magnetic structure is formed within the layer of molding material. Second trace portions of the electrically conductive trace are formed above the molding material and the magnetic structure. The electrically conductive trace and the magnetic structure form an inductor. The electrically conductive trace may have a coil shape surrounding the magnetic structure. The die may be positioned between portions of the inductor.

SEMICONDUCTOR DEVICE MANUFACTURING METHOD

A method of manufacturing a semiconductor device includes a first process in which a first wiring 3 is provided on a first surface 2a of a semiconductor substrate 2; a second process in which a light transmitting substrate 5 is attached to the first surface 2a; a third process in which the semiconductor substrate 2 is thinned so that the thickness of the semiconductor substrate 2 is smaller than the thickness of the light transmitting substrate 5; a fourth process in which a through hole 7 is formed in the semiconductor substrate 2; a fifth process in which a dip coating method is performed using a first resin material and thus a resin insulating layer 10 is provided; a sixth process in which a contact hole 16 is formed in the resin insulating layer 10; and a seventh process in which a second wiring 8 is provided on a surface 10b of the resin insulating layer 10, and the first wiring 3 and the second wiring 8 are electrically connected via a contact hole 16.

SEMICONDUCTOR CHIP, METHOD FOR MANUFACTURING SEMICONDUCTOR CHIP, INTEGRATED CIRCUIT DEVICE, AND METHOD FOR MANUFACTURING INTERGRATED CIRCUIT DEVICE

An integrated circuit device includes a support substrate, a first semiconductor chip and a second semiconductor chip provided on the support substrate, and a connection member made of solder. The first semiconductor chip and the second semiconductor chip each includes a semiconductor substrate, an interconnect layer provided on the semiconductor substrate, and a pad provided on a side surface of the interconnect layer. The connection member contacts a side surface of the pad of the first semiconductor chip and a side surface of the pad of the second semiconductor chip.

Wаfеr lеvеl pасkаging

Тhrоugh viаs in а substrаtе аrе fоrmеd bу сrеаting а trеnсh in а tоp sidе оf thе substrаtе аnd аt lеаst оnе trеnсh in thе bасk sidе оf thе substrаtе. Тhе sum оf thе dеpths оf thе trеnсhеs аt lеаst еquаls thе hеight оf thе substrаtе. Тhе trеnсhеs сrоss аt intеrsесtiоns, whiсh ассоrdinglу fоrm thе thrоugh viаs frоm thе tоp sidе tо thе bасk sidе. Тhе thrоugh viаs аrе fillеd with а соnduсtоr tо fоrm соntасts оn bоth sidеs аnd thе еdgе оf thе substrаtе. Соntасts оn thе bасksidе аrе fоrmеd аt еасh оf thе trеnсh. Тhе thrоugh viаs frоm thе еdgе соntасts. Тrасеs соnnесt bоnd pаds tо thе соnduсtоr in thе thrоugh viа. Sоmе trасеs аrе pаrаllеl tо thе bасk sidе trасеs. Sоmе trасеs аrе skеw tо thе bасk sidе trасеs. Тhе substrаtе is diсеd tо fоrm individuаl diе.

SURFACE-MOUNTED CHIP

ELECTRICAL CONNECTOR BETWEEN DIE PAD AND Z-INTERCONNECT FOR STACKED DIE ASSEMBLIES

Semiconductor Devices and Methods of Fabricating the Same

팬-아웃 반도체 패키지 및 패키지 기판

... 본 개시는 접속패드가 배치된 활성면 및 활성면의 반대측인 비활성면을 갖는 반도체칩, 반도체칩의 비활성면의 적어도 일부를 봉합하는 봉합재, 반도체칩의 활성면 상에 배치되며 반도체칩의 접속패드와 전기적으로 연결된 재배선층을 포함하는 연결부재, 봉합재 상에 배치되며 반도체칩의 비활성면을 향하는 제1면과 제1면의 반대측인 제2면을 갖는 보강판, 및 보강판의 제1면 및 제2면 중 적어도 하나에 형성된 리지드 패턴을 포함하는, 팬-아웃 반도체 패키지 및 이를 포함하는 판넬에 관한 것이다.

Semiconductor device, three-dimensionally mounted semiconductor device, and method of manufacturing semiconductor device

The present invention relates to one semiconductor device of three-dimensionally mounted semiconductor devices. The three-dimensionally mounted semiconductor devices are formed by mounting plural semiconductor devices on top of one another. A silicon semiconductor substrate is used. This silicon semiconductor substrate has a main front surface on which an integrated circuit part and an electrode pad are formed. An etching process is performed on the silicon semiconductor substrate with the electrode pad functioning as an etching stopper layer to form a hole. A buried electrode is provided in the formed hole. The buried electrode electrically leads the electrode pad out to a main back surface of the silicon semiconductor substrate.

Fan-out semiconductor package

Semiconductor device and method for making same

Chip package

Electrical connector between die pad and z-interconnect for stacked die assemblies and forming method thereof

Fanout integration for stacked silicon package assembly

A chip package assembly and method for fabricating the same are provided which utilize a plurality of posts in mold compound for improved resistance to delamination. In one example, a chip package assembly is provided that includes a first integrated circuit (IC) die, a substrate, a redistribution layer, a mold compound and a plurality of posts. The redistribution layer provides electrical connections between circuitry of the first IC die and circuitry of the substrate. The mold compound is disposed in contact with the first IC die and spaced from the substrate by the redistribution layer. The plurality of posts are disposed in the mold compound and are laterally spaced from the first IC die. The plurality of posts are not electrically connected to the circuitry of the first IC die.

Chip package

An embodiment of the invention provides a chip package which includes a substrate having an upper surface and a lower surface. A recess is adjacent to a sidewall of the substrate, wherein the recess is formed along a direction from the upper surface toward the lower surface of the substrate. A device region or sensing region of biological features is located on the upper surface of the substrate. A conducting pad is located on the upper surface of the substrate. A conducting layer is electrically connected to the conducting pad and extends to the recess along the sidewall of the substrate.

Manufacturing method of semiconductor device

A manufacturing method of a semiconductor device is provided. The method includes: a laminated-layer-forming step, that adheres a supporting base covering IC regions with insulating resin on a semiconductor substrate having ICs to form laminated layers; a notch-cutting step, that cuts the semiconductor substrate and the insulating resin with at least a part of the supporting base left; and a slicing step, that dices the supporting base to apart the laminated layers. The notch-cutting step performs cut while cooling the saw that slices the semiconductor substrate.

The method for forming semiconductor device and semiconductor structure

A method of forming a semiconductor device includes forming a plurality of metal pads over a semiconductor substrate of a wafer, forming a passivation layer covering the plurality of metal pads, patterning the passivation layer to reveal the plurality of metal pads, forming a first polymer layer over the passivation layer, forming a plurality of redistribution lines extending into the first polymer layer and the passivation layer to connect to the plurality of metal pads, forming a second polymer layer over the first polymer layer, and patterning the second polymer layer to reveal the plurality of redistribution lines. The first polymer layer is further revealed through openings in remaining portions of the second polymer layer.

Semiconductor device and method for manufacturing the same, semiconductor wafer and semiconductor device manufactured thereby

A semiconductor device including a base semiconductor substrate having an edge area which surrounds an element forming area, a buried oxide film provided over the base semiconductor substrate in the element forming area, and an element forming semiconductor substrate provided over the buried oxide film.

Laminated semiconductor substrate, laminated chip package and method of manufacturing the same

In a laminated semiconductor substrate, a plurality of semiconductor substrates are laminated. Each of the semiconductor substrate has a plurality of scribe-groove parts formed along scribe lines. Further, each of the semiconductor substrate has a plurality of device regions insulated from each other and has a semiconductor device formed therein, a first wiring electrode and a second wiring electrode extend to the inside of a interposed groove part from a first device region and a second device region respectively, and are separated from each other. In the laminated semiconductor substrate, a through hole which the first wiring electrode appears is formed. The laminated semiconductor substrate has a through electrode. The through electrode is contact with all of the first wiring electrodes appearing in the through hole. The laminated semiconductor substrate has a plurality of laminated chip regions.

Integrated Voltage Regulator with Embedded Passive Device(s) for a Stacked IC

A stacked integrated circuit includes a first tier IC and a second tier IC. Active faces of the first tier IC and the second tier IC face each other. An interconnect structure, such as microbumps, couples the first tier IC to the second tier IC. An active portion of a voltage regulator is integrated in the first semiconductor IC and coupled to passive components (for example a capacitor or an inductor) embedded in a packaging substrate on which the stacked IC is mounted. The passive components may be multiple through vias in the packaging substrate providing inductance to the active portion of the voltage regulator. The inductance provided to the active portion of the voltage regulator is increased by coupling the through via in the packaging substrate to through vias in a printed circuit board that the packaging substrate is mounted on.

Electronic component package fabrication method and structure

A redistribution pattern is formed on active surfaces of electronic components while still in wafer form. The redistribution pattern routes bond pads of the electronic components to redistribution pattern terminals on the active surfaces of the electronic components. The bond pads are routed to the redistribution pattern terminals while still in wafer form, which is a low cost and high throughput process, i.e., very efficient process.

Semiconductor device and method of forming through vias with reflowed conductive material

A semiconductor device is made by providing a first semiconductor wafer having semiconductor die. A gap is made between the semiconductor die. An insulating material is deposited in the gap. A portion of the insulating material is removed to form a first through hole via (THV). A conductive lining is conformally deposited in the first THV. A solder material is disposed above the conductive lining of the first THV. A second semiconductor wafer having semiconductor die is disposed over the first wafer. A second THV is formed in a gap between the die of the second wafer. A conductive lining is conformally deposited in the second THV. A solder material is disposed above the second THV. The second THV is aligned to the first THV. The solder material is reflowed to form the conductive vias within the gap. The gap is singulated to separate the semiconductor die.

SEMICONDUCTOR PACKAGE

A semiconductor package is provided comprising a package substrate having an opening located in a central region thereof and a circuit pattern provided adjacent to the opening. A first semiconductor chip is located on the package substrate and includes first bonding pads. A pair of second semiconductor chips are spaced apart from each other across the opening and mounted between the package substrate and the first semiconductor chip. Each of the second semiconductor chips includes a second bonding pad. A connection element is further provided to electrically connect the second bonding pad to a corresponding one of the first bonding pads.

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

A package structure including a redistribution structure, a die, a plurality of conductive structures, a first insulating encapsulant, a chip stack, and a second insulating encapsulant. The die is disposed on and electrically connected to the redistribution structure. The conductive structures are disposed on and electrically connected to the redistribution structure. The conductive structures surround the die. The first insulating encapsulant encapsulates the die and the conductive structures. The first insulating structure includes a plurality of openings exposing top surfaces of the conductive structures. The chip stack is disposed on the first insulating encapsulant and the die. The chip stack is electrically connected to the conductive structures. The second insulating encapsulant encapsulates the chip stack.

Semiconductor Device and Method of Forming Conductive THV and RDL on Opposite Sides of Semiconductor Die for RDL-to-RDL Bonding

A semiconductor device has a plurality of semiconductor die mounted to a carrier. An encapsulant is deposited over the carrier around a peripheral region of the semiconductor die. A plurality of vias is formed through the encapsulant. A first conductive layer is conformally applied over a sidewall of the vias to form conductive vias. A second conductive layer is formed over a first surface of the semiconductor die between the conductive vias and contact pads of the semiconductor die. The first and second conductive layers can be formed during the same manufacturing process. A third conductive layer is formed over a second surface of the semiconductor die opposite the first surface of the semiconductor die. The third conductive layer is electrically connected to the conductive vias. A plurality of semiconductor die is stacked and electrically connected through the conductive vias and second and third conductive layers.

Packaging method and package structure for image sensing chip

A packaging method and a package for an image sensing chip are provided. The packaging method includes: providing a wafer including a first surface and a second surface opposite to the first surface, where the wafer has multiple image sensing chips arranged in a grid, each of the image sensing chips has an image sensing region and contact pads arranged on a side of the first surface; forming an opening corresponding to each of the contact pads and cutting trenches on a side of the second surface of the wafer, where the contact pad is exposed through the opening; filling the cutting trenches with a first photosensitive ink; and applying a second photosensitive ink on the second surface of the wafer to cover the opening with the second photosensitive ink and form a hollow cavity in the opening.

SEMICONDUCTOR PACKAGE ADAPTED FOR HIGH-SPEED DATA PROCESSING AND DAMAGE PREVENTION OF CHIPS PACKAGED THEREIN AND METHOD FOR FABRICATING THE SAME

A semiconductor package includes a semiconductor chip provided with a first surface having a bonding pad, a second surface opposing to the first surface and side surfaces; a first redistribution pattern connected with the bonding pad and extending along the first surface from the bonding pad to an end portion of the side surface which meets with the second surface; and a second redistribution pattern disposed over the first redistribution pattern and extending from the side surfaces to the to first surface. In an embodiment of the present invention, in which the first redistribution pattern connected with the bonding pad is formed over the semiconductor chip and the second redistribution pattern is formed over the first redistribution pattern, it is capable of reducing a length for signal transfer since the second redistribution pattern is used as an external connection terminal. It is also capable of processing data with high speed, as well as protecting the semiconductor chip having weak ...

Fan-out semiconductor package

A wafer level fan out package includes a semiconductor die having a first surface, a second surface, and a third surface. A stiffener is disposed on the third surface of the semiconductor die. A conductive via passes through the stiffener. First and second electrically conductive patterns electrically connected to the conductive via are disposed on the first and second surfaces of the semiconductor die and stiffener. Solder balls are electrically connected to the first or second electrically conductive patterns.

Fan-out semiconductor package

A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface disposed to oppose the active surface; a dummy chip disposed in the through-hole and spaced apart from the semiconductor chip; a second connection member disposed on the first connection member, the dummy chip, and the active surface of the semiconductor chip; and an encapsulant encapsulating at least portions of the first connection member, the dummy chip, and the inactive surface of the semiconductor chip. The first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads.

Semiconductor device and method of manufacture

A semiconductor device structure and method of manufacturing a semiconductor device. The semiconductor device may comprise a semiconductor die having a top major surface that has one or more electrical contacts formed thereon, an opposing bottom major surface, and side surfaces; a molding material encapsulating the top major surface, the bottom major surface and the side surfaces of the semiconductor die, wherein the molding material defines a package body that has a top surface and a side surface; wherein the plurality of electrical contacts are exposed on the top surface of the package body and a metal layer is arranged over and electrically connected to the electrical contacts and wherein the metal layer extends to and at least partially covers a side surface of the package body.

Wаfеr lеvеl pасkаging

Тhrоugh viаs in а substrаtе аrе fоrmеd bу сrеаting а trеnсh in а tоp sidе оf thе substrаtе аnd аt lеаst оnе trеnсh in thе bасk sidе оf thе substrаtе. Тhе sum оf thе dеpths оf thе trеnсhеs аt lеаst еquаls thе hеight оf thе substrаtе. Тhе trеnсhеs сrоss аt intеrsесtiоns, whiсh ассоrdinglу fоrm thе thrоugh viаs frоm thе tоp sidе tо thе bасk sidе. Тhе thrоugh viаs аrе fillеd with а соnduсtоr tо fоrm соntасts оn bоth sidеs аnd thе еdgе оf thе substrаtе. Соntасts оn thе bасksidе аrе fоrmеd аt еасh оf thе trеnсh. Тhе thrоugh viаs frоm thе еdgе соntасts. Тrасеs соnnесt bоnd pаds tо thе соnduсtоr in thе thrоugh viа. Sоmе trасеs аrе pаrаllеl tо thе bасk sidе trасеs. Sоmе trасеs аrе skеw tо thе bасk sidе trасеs. Тhе substrаtе is diсеd tо fоrm individuаl diе.

Semiconductor device and manufacturing method of the same

The invention is directed to a semiconductor device having a penetrating electrode (20) and a manufacturing method thereof in which reliability and a yield of the semiconductor device are enhanced. A refractory metal layer (13) is formed on a pad electrode (12) formed on a semiconductor substrate (10) with a first insulation film (11) therebetween. Next, a passivation layer (14) is formed on a front surface of the semiconductor substrate (10) including on the pad electrode (12) and on the refractory metal layer (13), and a supporting body (16) is further formed with a resin layer (15) therebetween. Next, the semiconductor substrate (10) is etched to form a via hole (17) from a back surface of the semiconductor substrate (10) to the pad electrode (12). Next, a penetrating electrode (20) electrically connected with the pad electrode (12) exposed at a bottom of the via hole (17) and a wiring layer (21) are formed with a second insulation film (18) therebetween. Furthermore, a solder resist ...

Semiconductor device

A wiring board is manufactured by mounting on a mounting board 14 in one of a number of described ways a semiconductor element 11 having protruding electrodes 12 formed at an edge surface thereof, a resin layer 13 which is formed on the surface of the semiconductor element and seals the protruding electrodes except for the ends thereof and external protruding connectors of varying kinds provided to the ends of the protruding electrodes exposed from the resin layer.

Process for the manufacturing of a SOI wafer by oxidation of buried cavities

A contact is formed within an active region of a substrate at the edge of a die, within the first metallization level in the active region of the substrate. An opening having sloped sidewalls is etched into the backside of the substrate, exposing a portion of the active region contact. An interconnect is formed on the opening sidewall to connect the active region contact with a die contact pad on the backside surface of the substrate.. The active region contact spans a boundary between two die, with the opening preferably etched across the boundary to permit interconnects on opposing sidewalls of the opening to each contact the active region contact within different die, connecting the active region contact to die contact pads on different dice. The dies are then separated along the boundary, through the active region contact which becomes two separate active region contacts.

Integrated circuit chip using top post-passivation technology and bottom structure technology

Three-dimensional chip-to-wafer integration

Disclosed is three-dimensional chip-to-wafer integration. An integrated circuit device is disclosed that includes a semiconductor substrate and a die attached to the semiconductor substrate. A conductive pillar is connected to at least one of the semiconductor substrate or the die. An overmold is molded onto the semiconductor substrate over the die, and the conductive pillar extends through the overmold.

The chip module and manufacturing method thereof

Semiconductor package and method of forming a semiconductor package

Process of encapsulation of semiconductor pastilles, device obtained by this process and applicationà interconnection of pastilles in three dimensions

Selon le procédé de l'invention, on câble des fils conducteurs directement sur une rondelle semi-conductrice portant un grand nombre de pastilles, on colle la rondelle sur un film élastique, on scie la rondelle pour individualiser les pastilles puis on étire le film de sorte à écarter les pastilles; on solidarise ensuite l'ensemble des pastilles et des fils dans un matériau isolant, résine polymérisable par exemple, puis, après polissage, on réalise des dépôts métalliques au-dessus des fils de sorte à relier ceux-ci aux côtés des pastilles; on découpe ensuite l'ensemble de façon à séparer les pastilles.

SURFACE-MOUNT CHIP

L'invention concerne une puce à montage en surface réalisée dans et sur un substrat de silicium ayant une face avant et un flanc, la puce comprenant : au moins une métallisation destinée à être brasée à un dispositif extérieur, cette métallisation comprenant une première portion (30a) recouvrant au moins une partie de la face avant du substrat, et une deuxième portion (30b) recouvrant au moins une partie du flanc du substrat ; et une région en silicium poreux (20), incluse dans le substrat, séparant la deuxième portion (30b) de la métallisation du reste du substrat.

CASE OF SEMICONDUCTOR HAVING an ELEMENT SEMICONDUCTOR, a STRUCTURE DEFIXATION OF CASE OF SEMICONDUCTOR ASSEMBLED ON a PLATE OF CIRCUITSIMPRIMES, AND PROCEEDED Of ASSEMBLY OF CASE OF SEMICONDUCTOR

INTEGRATED CIRCUIT CHIP USING TOP POST-PASSIVATION TECHNOLOGY AND BOTTOM STRUCTURE TECHNOLOGY

Chip package and method for forming the same

A chip package including a first substrate having a first surface and a second surface opposite thereto is disclosed. The first substrate has a micro-electric element and has a plurality of conductive pads adjacent to the first surface. The first substrate has a plurality of openings exposing a portion of each conductive pad, respectively. A second substrate is disposed on the first surface. An encapsulation layer is disposed on the first surface and covers the second substrate. A redistribution layer is disposed on the second surface and extends into the openings to electrically connect the conductive pads.

Semiconductor device and method of manufacturing the same

Semiconductor device and manufacturing method thereof

Chip package and fabrication method thereof

Method of forming through-holes in a wafer and then dicing to form stacked semiconductor devices

A semiconductor chip in which a through hole penetrating through its surface and reverse surface is formed in a scribe line region in the vicinity of an active region where a functional device is formed, and a conductive member is arranged in the through portion. The through portion may be a groove opening sideward on a sidewall surface of the semiconductor chip. The through portion may be a through hole blocked from a side part of the semiconductor chip. The semiconductor chip further includes wiring for electrically connecting an internal circuit formed in the active region and the conductive member to each other.

Semiconductor device and method for fabricating the same

In a method, first and second circuit elements are provided on a surface of a semiconductor substrate; and a hole is formed in the semiconductor substrate between the first and second circuit elements. Then, the semiconductor substrate is divided at the hole to separate the first and second circuit elements from each other.

Package-in-package using through-hole via die on saw streets

A semiconductor device includes a first die having top, bottom, and peripheral surfaces. A bond pad is formed over the top surface. An organic material is connected to the first die and disposed around the peripheral surface. A via hole is formed in the organic material. A metal trace connects the via hole to the bond pad. A conductive material is deposited in the via hole. A redistribution layer (RDL) has an interconnection pad disposed over the top surface of the first die.

Semiconductor Device and Method of Manufacture Thereof

A semiconductor device and a method of making a semiconductor device are disclosed. The semiconductor device comprises a redistribution layer arranged over a chip, the redistribution layer comprising a first redistribution line. The semiconductor further comprises an isolation layer disposed over the redistribution layer, the isolation layer having a first opening forming a first pad area and a first interconnect located in the first opening and in contact with the first redistribution line. The redistribution line in the first pad area is arranged orthogonal to a first direction to a neutral point of the semiconductor device.

Chip scale surface mounted semiconductor device package and process of manufacture

A semiconductor device package die and method of manufacture are disclosed. The device package die may comprise a device substrate having one or more front electrodes located on a front surface of the device substrate and electrically connected to one or more corresponding device regions formed within the device substrate proximate the front surface. A back conductive layer is formed on a back surface of the device substrate. The back conductive layer is electrically connected to a device region formed within the device substrate proximate a back surface of the device substrate. One or more conductive extensions are formed on one or more corresponding sidewalls of the device substrate in electrical contact with the back conductive layer, and extend to a portion of the front surface of the device substrate. A support substrate is bonded to the back surface of the device substrate.

Semiconductor Device and Method of Forming a Wafer Level Package Structure Using Conductive Via and Exposed Bump

A semiconductor device has a carrier. A semiconductor wafer including a semiconductor die is mounted to the carrier with an active surface of the semiconductor die facing away from the carrier. A plurality of bumps is formed over the active surface of the semiconductor die. An opening is formed in a periphery of the semiconductor die. An encapsulant is deposited over the carrier and semiconductor die, in the opening, and around the plurality of bumps such that an exposed portion of the plurality of bumps is devoid of encapsulant. A conductive via is formed through the encapsulant, within the opening, and extends to the carrier. A conductive layer is formed over the encapsulant and electrically connects to the conductive via and the exposed portion of the plurality of bumps. The carrier is removed to expose an end of the conductive via.

Semiconductor Device and Method of Forming Bond Wires Between Semiconductor Die Contact Pads and Conductive TOV in Peripheral Area Around Semiconductor Die

A semiconductor wafer has a plurality of semiconductor die with contact pads. An organic material is deposited in a peripheral region around the semiconductor die. A portion of the organic material is removed to form a plurality of vias. A conductive material is deposited in the vias to form conductive TOV. The conductive TOV can be recessed with respect to a surface of the semiconductor die. Bond wires are formed between the contact pads and conductive TOV. The bond wires can be bridged in multiple sections across the semiconductor die between the conductive TOV and contact pads. An insulating layer is formed over the bond wires and semiconductor die. The semiconductor wafer is singulated through the conductive TOV or organic material between the conductive TOV to separate the semiconductor die. A plurality of semiconductor die can be stacked and electrically connected through the bond wires and conductive TOV.

Layered chip package and method of manufacturing same

A layered chip package includes a main body and wiring. The main body includes: a main part having a top surface and a bottom surface and including three or more layer portions stacked on one another; a plurality of first terminals disposed on the top surface of the main part; and a plurality of second terminals disposed on the bottom surface of the main part. Each layer portion includes a semiconductor chip having first and second surfaces, and a plurality of electrodes electrically connected to the wiring. The plurality of electrodes are disposed on a side of the first surface of the semiconductor chip. A first layer portion located closest to the top surface of the main part and a second layer portion located closest to the bottom surface of the main part are arranged so that the second surfaces of their respective semiconductor chips face toward each other. The plurality of first terminals are formed by using the plurality of electrodes of the first layer portion. The plurality of second terminals are formed by using the plurality of electrodes of the second layer portion.

Wafer level chip scale package

A semiconductor device, a method of manufacturing semiconductor devices and a circuit package assembly are described. A semiconductor device can have a semiconductor substrate with first and second surfaces and a sidewall between them. First and second conductive pads on the first and second surfaces are in electrical contact with corresponding first and second semiconductor device structures in the substrate. An insulator layer on the first surface and sidewall covers a portion of the first conductive pad on the first surface. An electrically conductive layer on part of the insulator layer on the first conductive pad and sidewall is in electrical contact with the second conductive pad. The insulator layer prevents the conductive layer from making electrical contact between the first and second conductive pads.

Package-in-Package Using Through-Hole Via Die on Saw Streets

A semiconductor device includes a first die having top, bottom, and peripheral surfaces. A bond pad is formed over the top surface. An organic material is connected to the first die and disposed around the peripheral surface. A via hole is formed in the organic material. A metal trace connects the via hole to the bond pad. A conductive material is deposited in the via hole. A redistribution layer (RDL) has an interconnection pad disposed over the top surface of the first die.

Chip package and method for forming the same

An embodiment of the invention provides a chip package which includes: a carrier substrate; a semiconductor substrate having an upper surface and a lower surface, disposed overlying the carrier substrate; a device region or sensing region located on the upper surface of the semiconductor substrate; a conducting pad located on the upper surface of the semiconductor substrate; a conducting layer electrically connected to the conducting pad and extending from the upper surface of the semiconductor substrate to a sidewall of the semiconductor substrate; and an insulating layer located between the conducting layer and the semiconductor substrate.

Microelectric package utilizing multiple bumpless build-up structures and through-silicon vias

A microelectronic package having a first bumpless build-up layer structure adjacent an active surface and sides of a microelectronic device and a second bumpless build-up layer structure adjacent a back surface of the microelectronic device, wherein conductive routes are formed through the first bumpless build-up layer from the microelectronic device active surface to conductive routes in the second bumpless build-up layer structure and wherein through-silicon vias adjacent the microelectronic device back surface and extending into the microelectronic device are electrically connected to the second bumpless build-up layer structure conductive routes.

Semiconductor package with single sided substrate design and manufacturing methods thereof

A multilayer substrate includes a first outer conductive patterned layer, a first insulating layer exposing a portion of the first outer conductive patterned layer to define a first set of pads, a second outer conductive patterned layer, and a second insulating layer exposing a portion of the second outer conductive patterned layer to define a second set of pads. The multilayer substrate further includes inner layers each with an inner conductive patterned layer, multiple inner conductive posts formed adjacent to the inner conductive patterned layer, and an inner dielectric layer, where the inner conductive patterned layer and the inner conductive posts are embedded in the inner dielectric layer, and a top surface of each of the inner conductive posts is exposed from the inner dielectric layer.

3D Chip-On-Wafer-On-Substrate Structure With Via Last Process

Disclosed herein is a package having a first redistribution layer (RDL) disposed on a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate. The first RDL is bonded to the second RDL. The package further includes an insulating film disposed over the second RDL and around the first RDL and the first semiconductor substrate. A conductive element is disposed in the first RDL. A via extends from a top surface of the insulating film, through the first semiconductor substrate to the conductive element, and a spacer is disposed between the first semiconductor substrate and the via. The spacer extends through the first semiconductor substrate. 1. A package comprising:a first redistribution layer (RDL) disposed on a first semiconductor substrate;a second RDL disposed on a second semiconductor substrate, wherein the first RDL is bonded to the second RDL;an insulating film disposed over the second RDL and around the first RDL and the first semiconductor substrate;a first conductive element disposed in the first RDL;a via extending from a top surface of the insulating film, through the first semiconductor substrate to the first conductive element; anda first spacer disposed between the first semiconductor substrate and the via, wherein the first spacer extends through the first semiconductor substrate.2. The package of claim 1 , wherein a first sidewall of the first spacer is aligned with a sidewall of the insulating film claim 1 , and wherein a second sidewall of the first spacer opposite the first sidewall contacts the first semiconductor substrate.3. The package of claim 1 , wherein top surfaces of the first spacer and the first semiconductor substrate are substantially level claim 1 , and wherein bottom surfaces of the first spacer and the first semiconductor substrate are substantially level.4. The package of further comprising a second spacer disposed between the via and the first spacer.5. The package of claim 4 , wherein the second ...

Multi-die semiconductor structure with intermediate vertical side chip and semiconductor package for same

Semiconductor multi-die structures having intermediate vertical side chips, and packages housing such semiconductor multi-die structures, are described. In an example, a multi-die semiconductor structure includes a first main stacked dies (MSD) structure having a first substantially horizontal arrangement of semiconductor dies. A second MSD structure having a second substantially horizontal arrangement of semiconductor dies is also included. An intermediate vertical side chip (i-VSC) is disposed between and electrically coupled to the first and second MSD structures.

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES

In one example, a semiconductor device structure relates to an electronic device, which includes a device top surface, a device bottom surface opposite to the device top surface, device side surfaces extending between the device top surface and the device bottom surface, and pads disposed over the device top surface. Interconnects are connected to the pads, and the interconnects first regions that each extend from a respective pad in in an upward direction, and second regions each connected to a respective first region, wherein each second region extends from the respective first region in a lateral direction. The interconnects comprise a redistribution pattern on the pads. Other examples and related methods are also disclosed herein. 1. A semiconductor device , comprising: a device top surface;', 'a device bottom surface opposite to the device top surface; and', 'a device side surface extending between the device top surface and the device bottom surface;, 'an electronic device comprising a first region that extends from the device top surface in an upward direction; and', 'a second region coupled to the first region, wherein the second region extends from the first region in a lateral direction; and, 'an interconnect directly attached at the device top surface comprising a first portion of the second region is exposed from a first surface of the encapsulant;', 'a second portion of the second region is exposed from a second surface of the encapsulant; and', 'the encapsulant covers a third portion of the second region., 'an encapsulant that covers the device top surface, the device side surface, and a periphery of the first region, wherein2. The semiconductor device of claim 1 , wherein:the interconnect comprises a severed leadframe lead;the lateral direction is substantially parallel to the device top surface; andthe second portion extends to overlap the device side surface so as to extend outside a perimeter of the electronic device.3. The semiconductor device of ...

Semiconductor device

A semiconductor device includes a protective layer, a redistribution pattern, a pad pattern and an insulating polymer layer. The protective layer may be formed on a substrate. The redistribution pattern may be formed on the protective layer. An upper surface of the redistribution may be substantially flat. The pad pattern may be formed directly on the redistribution pattern. An upper surface of the pad pattern may be substantially flat. The insulating polymer layer may be formed on the redistribution pattern and the pad pattern. An upper surface of the insulating polymer layer may be lower than the upper surface of the pad pattern. The semiconductor device may have a high reliability.

CHIP PACKAGE STRUCTURE

A chip package structure is provided. The chip package structure includes a substrate having a first surface and a second surface opposite to the first surface. The chip package structure includes a first chip structure and a second chip structure over the first surface. The chip package structure includes a protective layer over the first surface and surrounding the first chip structure and the second chip structure. A portion of the protective layer is between the first chip structure and the second chip structure. The chip package structure includes a first anti-warpage bump over the second surface and extending across the portion of the protective layer. The chip package structure includes a conductive bump over the second surface and electrically connected to the first chip structure or the second chip structure. The first anti-warpage bump is wider than the conductive bump. 1. A chip package structure , comprising:a substrate having a first surface and a second surface opposite to the first surface;a first chip structure and a second chip structure over the first surface;a protective layer over the first surface and surrounding the first chip structure and the second chip structure, wherein a portion of the protective layer is between the first chip structure and the second chip structure;a first anti-warpage bump over the second surface and extending across the portion of the protective layer; anda conductive bump over the second surface and electrically connected to the first chip structure or the second chip structure, wherein the first anti-warpage bump is wider than the conductive bump, and wherein the first anti-warpage bump and the conductive bump are exposed.2. The chip package structure as claimed in claim 1 , wherein a width of the first anti-warpage bump is greater than a distance between the first chip structure and the second chip structure.3. The chip package structure as claimed in claim 1 , wherein the first anti-warpage bump is thinner than ...

OFFSET TEST PADS FOR WLCSP FINAL TEST

A device configured for WLCSP, can include: a first pad; a test pad offset from the first pad; a first RDL path that connects the first pad to the test pad; and a second RDL path that connects the test pad to a solder ball. In another case, a device configured for WLCSP can include: a first pad; a test pad offset from the first pad; a first RDL path that connects the first pad to a solder ball; and a second RDL path that connects the test pad to the solder ball. A wafer having devices configured for WLCSP, can include: a first device having a first pad; a second device having a test pad; a first RDL path that connects the first pad to a solder ball; and a second RDL path that connects the test pad to the solder ball. 1. A device configured for wafer level chip scale packaging (WLCSP) , the device comprising:a) a first pad;b) a test pad offset from the first pad;c) a first redistribution layer (RDL) path that connects the first pad to the test pad; andd) a second RDL path that connects the test pad to a solder ball.2. The device of claim 1 , wherein the device comprises a serial non-volatile memory (NVM) device.3. The device of claim 1 , wherein the first and second RDL paths are in a same layer.4. The device of claim 1 , wherein the first and second RDL paths are in different layers.5. The device of claim 1 , further comprising a polymer layer that fully covers the first pad claim 1 , and leaves a portion of the test pad exposed.6. The device of claim 1 , wherein the device further comprises:a) a plurality of the first pads; andb) a plurality of the test pads, where each of the plurality of the test pads is offset from a corresponding of the plurality of the first pads by a same offset length.7. A device configured for WLCSP claim 1 , the device comprising:a) a first pad;b) a test pad offset from the first pad;c) a first RDL path that connects the first pad to a solder ball; andd) a second RDL path that connects the test pad to the solder ball.8. The device of claim ...

Chip-On-Wafer Package and Method of Forming Same

A method includes bonding a die to a substrate, where the substrate has a first redistribution structure, the die has a second redistribution structure, and the first redistribution structure is bonded to the second redistribution structure. A first isolation material is formed over the substrate and around the die. A first conductive via is formed, extending from a first surface of the substrate, where the first surface is opposite the second redistribution structure, the first conductive via contacting a first conductive element in the second redistribution structure. Forming the first conductive via includes patterning an opening in the substrate, extending the opening to expose the first conductive element, where extending the opening includes using a portion of a second conductive element in the first redistribution structure as an etch mask, and filling the opening with a conductive material. 1. A method comprising:bonding a die to a substrate, the substrate having a first redistribution structure disposed at a first surface of the substrate, the die having a second redistribution structure, the first redistribution structure being bonded to the second redistribution structure;forming a first isolation material over the substrate and around the die;patterning an opening in a second surface of the substrate, the second surface being opposite the substrate from the first surface;extending the opening to expose a first conductive element in the second redistribution structure, wherein extending the opening comprises using a second conductive element in the first redistribution structure as an etch mask; andfilling the opening with a conductive material, the conductive material contacting the first conductive element.2. The method of claim 1 , further comprising:after extending the opening, forming an isolation layer in the opening; andetching the isolation layer to form sidewall spacers on sidewalls of the opening.3. The method of claim 2 , wherein the sidewall ...

FAN-OUT SEMICONDUCTOR PACKAGE

A fan-out semiconductor package includes: a support member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the support member and the semiconductor chip; and a connection member disposed on the support member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads. The support member includes a glass plate and an insulating layer connected to the glass plate. 1. A fan-out semiconductor package comprising:a support member having a through-hole;a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;an encapsulant encapsulating at least portions of the support member and the semiconductor chip; anda connection member disposed on the support member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads,wherein the support member includes a glass plate and an insulating layer connected to the glass plate.2. The fan-out semiconductor package of claim 1 , wherein the glass plate is an amorphous solid material including a glass component.3. The fan-out semiconductor package of claim 1 , wherein the insulating layer is formed of an insulating material including an insulating resin and an inorganic filler.4. The fan-out semiconductor package of claim 1 , wherein the support member includes a redistribution layer electrically connected to the connection pads.5. The fan-out semiconductor package of claim 4 , wherein the support member further includes vias penetrating through at least one of the glass plate and the insulating layer and electrically connected to the redistribution layer.6. The fan-out semiconductor ...

Embedded die package multichip module

An embedded die package includes a first die having an operating voltage between a first voltage potential and a second voltage potential that is less than the first voltage potential. A via, including a conductive material, is electrically connected to a bond pad on a surface of the first die, the via including at least one extension perpendicular to a plane along a length of the via. A redistribution layer (RDL) is electrically connected to the via, at an angle with respect to the via defining a space between the surface and a surface of the RDL. A build-up material is in the space.

SEMICONDUCTOR PACKAGE INCLUDING STACKED SEMICONDUCTOR CHIPS

Disclosed is a semiconductor package. The semiconductor package includes a substrate including an opening, a first semiconductor chip, disposed on the substrate, including a plurality of first chip pads exposed through the opening, a second semiconductor chip, disposed on the first semiconductor chip to partially overlap with the first semiconductor chip, including a plurality of second chip pads, aligned with the opening, and a redistribution layer formed on a surface on which the second chip pads of the second semiconductor chip are disposed. One or more of the second chip pads overlaps with the first semiconductor chip and is covered by the first semiconductor chip and with the remaining pads of the second chip pads being exposed through the opening. The redistribution layer includes redistribution pads, exposed through the opening, and includes redistribution lines, configured to connect the one or more of the second chip pads to the redistribution pads. 1. A semiconductor package comprising:a substrate including an opening;a first semiconductor chip, disposed on the substrate, including a plurality of first chip pads exposed through the opening;a second semiconductor chip, disposed on the first semiconductor chip to partially overlap with the first semiconductor chip, including a plurality of second chip pads, aligned with the opening; anda redistribution layer formed on a surface on which the second chip pads of the second semiconductor chip are disposed,wherein one or more of the second chip pads overlap with the first semiconductor chip and are covered by the first semiconductor chip, with remaining pads of the second chip pads being exposed through the opening, andwherein the redistribution layer includes redistribution pads, exposed through the opening, and includes redistribution lines, configured to connect the one or more of the second chip pads to the redistribution pads.2. The semiconductor package of claim 1 , wherein a width of the opening in a ...

3DIC STRUCTURE AND METHOD OF FABRICATING THE SAME

Provided is a three dimensional integrated circuit (3DIC) structure including a first die, a second die, and a hybrid bonding structure bonding the first die and the second die. The hybrid bonding structure includes a first bonding structure and a second bonding structure. The first bonding structure includes a first bonding dielectric layer and a first bonding metal layer. The first bonding metal layer is disposed in the first bonding dielectric layer. The first bonding metal layer includes a first via plug and a first metal feature disposed over the first via plug, wherein a height of the first metal feature is greater than or equal to a height of the first via plug. A method of fabricating the 3DIC structure is also provided. 1. A three dimensional integrated circuit (3DIC) structure , comprising:a first die and a second die; and a first bonding dielectric layer; and', 'a first bonding metal layer, disposed in the first bonding dielectric layer, wherein the first bonding metal layer comprises a first via plug and a first metal feature disposed over the first via plug, a height of the first metal feature is greater than or equal to a height of the first via plug., 'a hybrid bonding structure bonding the first die and the second die, wherein the hybrid bonding structure comprises a first bonding structure and a second bonding structure, the first bonding structure comprises2. The 3DIC structure of claim 1 , wherein a ratio of the height of the first metal feature to the height of the first via plug is 1 to 3 and a width of the first metal feature is greater than a width of the first via plug.3. The 3DIC structure of claim 1 , wherein the first bonding dielectric layer comprises:a first bonding dielectric material conformally cover the first die; anda second bonding dielectric material, disposed over the first bonding dielectric material, wherein a thickness of the second bonding dielectric material is greater than or equal to a thickness of the first bonding ...

SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor package structure includes a conductive structure, at least one semiconductor element, an encapsulant, a redistribution structure and a plurality of bonding wires. The semiconductor element is disposed on and electrically connected to the conductive structure. The encapsulant is disposed on the conductive structure to cover the semiconductor element. The redistribution structure is disposed on the encapsulant, and includes a redistribution layer. The bonding wires electrically connect the redistribution structure and the conductive structure. 1. A semiconductor package structure , comprising:a conductive structure;at least one semiconductor element disposed on and electrically connected to the conductive structure;an encapsulant disposed on the conductive structure to cover the semiconductor element;a redistribution structure including a redistribution layer disposed on the encapsulant; anda plurality of bonding wires electrically connecting the redistribution structure and the conductive structure.2. The semiconductor package structure of claim 1 , wherein the conductive structure has a top surface and includes a plurality of wire bonding pads exposed from the top surface claim 1 , the encapsulant includes a plurality of encapsulant portions spaced apart from each other claim 1 , and the wire bonding pads of the conductive structure are located between the encapsulant portions.3. The semiconductor package structure of claim 2 , wherein the redistribution structure has a first surface facing the encapsulant portions and a second surface opposite to the first surface claim 2 , and further includes a plurality of wire bonding pads disposed on the redistribution layer and exposed from the second surface claim 2 , wherein the wire bonding pads of the redistribution structure are electrically connected to the corresponding wire bonding pads of the conductive structure through the bonding wires.4. The semiconductor package structure of claim 3 , wherein a ...

3D FANOUT STACKING

Semiconductor packages and fan out die stacking processes are described. In an embodiment, a package includes a first level die and a row of conductive pillars protruding from a front side of the first level die. A second level active die is attached to the front side of the first level die, and a redistribution layer (RDL) is formed on an in electrical contact with the row of conductive pillars and a front side of the second level active die. 1. A package comprising:a first-first level die and a second-first level die arranged side-by-side;a first row of conductive pillars protruding from a front side of the first-first level die;a second row of conductive pillars protruding from a front side of the second-first level die;a back side of a second level active die attached to the front side of the first-first level die and the front side of the second-first level die laterally between the first and second rows of conductive pillars; anda redistribution layer (RDL) on and in electrical contact with the first and second rows of conductive pillars and a front side of the second level active die.2. The package of claim 1 , wherein a back side of the second level active die is attached to the first-first level die and the second-first level die with a die attach film.3. The package of claim 1 , wherein the second level active die and the first and second rows of conductive pillars are 30 μm-80 μm tall.4. The package of claim 1 , further comprising a second-second level die and a third-second level die laterally adjacent to opposite sides of the second level active die; wherein the RDL is on an in electrical contact with front sides of the second-second level die and the third-second level die.5. The package of claim 4 , wherein the second level active die is rectangular claim 4 , the first and second rows of conductive pillars are laterally adjacent to a first pair of laterally opposite sides of the second level active die claim 4 , and the second-second level die and the ...

Semiconductor device with photonic and electronic functionality and method for manufacturing a semiconductor device

A semiconductor device has a semiconductor substrate and a first metallization stack arranged on the substrate. The substrate has and/or carries a plurality of electronic circuit elements. The first metallization stack has electrically insulating layers and at least one metallization layer. The semiconductor device further has a second metallization stack arranged on the first metallization stack and comprising further electrically insulating layers and an optical waveguide layer. The optical waveguide layer has at least one optical waveguide structure. Furthermore, one of the electrically insulating layers and one of the further electrically insulating layers are in direct contact with each other and form a pair of directly bonded layers.

Integrated Fan-Out Structure and Method of Forming

Semiconductor devices and methods of forming are provided. A molding compound extends along sidewalls of a first die and a second die. A redistribution layer is formed over the first die, the second die, and the molding compound. The redistribution layer includes a conductor overlying a gap between the first die and the second die. The conductor is routed at a first angle over an edge of the first die. The first angle is measured with respect to a straight line that extends along a shortest between the first die and the second die, and the first angle is greater than 0. 1. A device , comprising:a first die;a second die;a molding material extending between the first die and the second die; anda redistribution layer overlying the first die and the second die, the redistribution layer including a conductor continuously extending, in a plan view, from a sidewall of the first die that is closest to the second die to a sidewall of the second die that is closest to the first die, the conductor being routed at a first angle over an edge of the first die, the first angle being measured in a plan view and with respect to a shortest line between the first die and the second die, and the first angle being greater than 0.2. The device according to claim 1 , wherein:the first die comprises a first dielectric layer on a first substrate, an edge of the first dielectric layer being offset from an edge of the first substrate; andthe second die comprises a second dielectric layer on a top surface of a second substrate, an edge of the second dielectric layer being offset from an edge of the second substrate;wherein the conductor comprises a first turning point over the first dielectric layer, the first turning point being located where the conductor is first routed at the first angle.3. The device according to claim 2 , wherein the conductor is routed at the first angle over the edge of the second dielectric layer claim 2 , and the first angle is greater than about 15 degrees.4. The ...

INTERCONNECT STRUCTURE WITH REDUNDANT ELECTRICAL CONNECTORS AND ASSOCIATED SYSTEMS AND METHODS

Semiconductor die assemblies having interconnect structures with redundant electrical connectors are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die, a second semiconductor die, and an interconnect structure between the first and the second semiconductor dies. The interconnect structure includes a first conductive film coupled to the first semiconductor die and a second conductive film coupled to the second semiconductor die. The interconnect structure further includes a plurality of redundant electrical connectors extending between the first and second conductive films and electrically coupled to one another via the first conductive film. 1. A semiconductor device , comprising:a semiconductor substrate;a dielectric material over the substrate;a conductive trace extending at least partially through the dielectric material; and a conductive member coupled to the conductive trace, and', 'a conductive bond material bonded to the conductive member,, 'a plurality of redundant electrical connectors extending from the conductive trace and through at least a portion of the dielectric material, wherein each of the redundant electrical connectors includes—'}wherein all of the redundant electrical connectors are coupled to the conductive trace.2. The semiconductor device of wherein the dielectric includes a plurality of openings exposing portions of the conductive trace claim 1 , wherein the redundant electrical connectors are formed in the openings.3. The semiconductor device of wherein the conductive member comprises copper and the bond material comprises a solder material.4. The semiconductor device of wherein the conductive member includes an end portion claim 1 , and wherein the conductive bond material and conductive member form a conductive joint at the end portion.5. The semiconductor device of claim 1 , further comprising a through-substrate via (TSV) extending at least partially through the substrate claim 1 , ...

FAN-OUT SEMICONDUCTOR PACKAGE AND PACKAGE SUBSTRATE COMPRISING THE SAME

A fan-out semiconductor package includes: a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the inactive surface of the semiconductor chip; a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip; a reinforcing plate disposed on the encapsulant and having a first surface facing the inactive surface of the semiconductor chip and a second surface opposing the first surface; and rigid patterns formed on at least one of the first surface and the second surface of the reinforcing plate. 1. A fan-out semiconductor package comprising:a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;an encapsulant encapsulating at least portions of the inactive surface of the semiconductor chip;a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip;a reinforcing plate disposed on the encapsulant and having a first surface facing the inactive surface of the semiconductor chip and a second surface opposing the first surface; andrigid patterns disposed on at least one of the first surface and the second surface of the reinforcing plate.2. The fan-out semiconductor package of claim 1 , wherein the reinforcing plate has an elastic modulus greater than that of the encapsulant.3. The fan-out semiconductor package of claim 1 , wherein the reinforcing plate includes a glass fiber claim 1 , an inorganic filler claim 1 , and an insulating resin.4. The fan-out semiconductor package of claim 3 , further comprising a resin layer disposed on the second surface of the reinforcing plate claim 3 ,wherein the resin layer includes ...

Multi-chip package

A multi-chip package may include a package substrate, a connecting substrate, a plurality of semiconductor chips and a logic chip. The package substrate may have an opening. The connecting substrate may be arranged on an upper surface of the package substrate. The semiconductor chips may be stacked on an upper surface of the connecting substrate. The semiconductor chips may be electrically connected with the connecting substrate. The logic chip may be arranged in the opening. The logic chip may be electrically connected between the connecting substrate and the package substrate. Thus, the logic chip may not act as to increase a width of the multi-chip package.

PAD CONFIGURATIONS FOR AN ELECTRONIC PACKAGE ASSEMBLY

Embodiments of the present disclosure provide an electronic package assembly comprising a solder mask layer, the solder mask layer having at least one opening, and a plurality of pads coupled to the solder mask layer, wherein at least one pad of the plurality of pads includes (i) a first side, (ii) a second side, the first side being disposed opposite to the second side, (iii) a terminal portion and (iv) an extended portion, wherein the first side at the terminal portion is configured to receive a package interconnect structure through the at least one opening in the solder mask layer, the package interconnect structure to route electrical signals between a die and another electronic device that is external to the electronic package assembly, and wherein the second side at the extended portion is configured to receive one or more electrical connections from the die. 1. An electronic package assembly comprising:a solder mask layer having one or more openings;a plurality of pads coupled to the solder mask layer, wherein each of at least two pads of the plurality of pads includes (i) a first side, (ii) a second side, the first side being disposed opposite to the second side, (iii) a terminal portion and (iv) an extended portion, wherein the first side at the terminal portion of each of the at least two pads is configured to receive a package interconnect structure through the one or more openings in the solder mask layer, wherein the package interconnect structure is configured to route electrical signals between a die and an electronic device that is external to the electronic package assembly, and wherein the second side at the extended portion of each of the at least two pads is configured to receive one or more electrical connections from the die; anda die pad configured to receive the die,wherein the plurality of pads includes (i) a first row of pads disposed adjacent to the die pad and (ii) a second row of pads disposed adjacent and parallel to the first row of ...

SEMICONDUCTOR PACKAGE HAVING A SIDEWALL CONNECTION

A fan-out wafer level package includes a semiconductor die with a redistribution layer on a sidewall of the semiconductor die. A redistribution layer positioned over the die includes an extended portion that extends along the sidewall. The semiconductor die is encapsulated in a molding compound layer. The molding compound layer is positioned between the extended portion of the redistribution layer and the sidewall of the semiconductor die. Solder contacts, for electrically connecting the semiconductor device to an electronic circuit board, are positioned on the redistribution layer. The solder contacts and the sidewall of the redistribution layer can provide electrical contact on two different locations. Accordingly, the package can be used to improve interconnectivity by providing vertical and horizontal connections. 1. A device , comprising:a semiconductor die including a first surface, a second surface opposite to the first surface, a first sidewall surface transverse to the first and second surfaces; anda contact pad exposed from the first surface;a first dielectric layer on the contact pad and extending from the contact pad to the first sidewall surface, the first dielectric layer including a second sidewall surface coplanar with the first sidewall surface;a second dielectric layer on the contact pad and extending from the contact pad to the first and second sidewall surfaces, the second dielectric layer having a third sidewall surface coplanar with the first and second sidewall surfaces, the second dielectric layer having a surface facing away from the semiconductor die;a mold protection layer on and covering the first, second, and third sidewall surfaces, the mold protection layer having an end surface facing away from the semiconductor die and a fourth sidewall surface transverse to the end surface of the mold protection layer; anda redistribution layer on the contact pad and extending from the contact pad to the mold protection layer, the redistribution ...

FAN-OUT SEMICONDUCTOR PACKAGE

A fan-out semiconductor package includes: a frame including first to third insulating layers, a first wiring layer disposed on a first surface of the first insulating layer and embedded in the second insulating layer, and a second wiring layer disposed on the third insulating layer, and having a through-hole penetrating through the first to third insulating layers; a semiconductor chip disposed in the through-hole and having an active surface on which connection pads are disposed and an inactive surface opposing the active surface; an encapsulant covering at least portions of each of the frame and the semiconductor chip and filling at least portions of the through-hole; and a connection structure disposed on the frame and the active surface of the semiconductor chip and including redistribution layers electrically connected to the connection pads. The first and second wiring layers are electrically connected to the connection pads. 1. A fan-out semiconductor package comprising:a frame including a first insulating layer, a second insulating layer disposed on a first surface of the first insulating layer, a third insulating layer disposed on a second surface of the first insulating layer opposing the first surface, a first wiring layer disposed on the first surface of the first insulating layer and embedded in the second insulating layer, and a second wiring layer disposed on the third insulating layer, and having a through-hole penetrating through the first to third insulating layers;a semiconductor chip disposed in the through-hole and having an active surface on which connection pads are disposed and an inactive surface opposing the active surface;an encapsulant covering at least portions of each of the frame and the semiconductor chip and filling at least portions of the through-hole; anda connection structure disposed on the frame and the active surface of the semiconductor chip and including redistribution layers electrically connected to the connection pads, ...

IC PACKAGE INCLUDING MULTI-CHIP UNIT WITH BONDED INTEGRATED HEAT SPREADER

A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias. 1. An integrated circuit (IC) chip assembly , comprising:a first chip comprising a first integrated circuit, and a second chip comprising a second integrated circuit, wherein the first chip is adjacent to the second chip and an active side of the first and second chips is interconnected to a first side of a metallized redistribution structure, and wherein the metallized redistribution structure has a second side, opposite the first side, to receive a plurality of solder interconnects;a mold material between the first and second chips; and{'sub': 2', '2, 'a heat spreader bonded to an inactive side of both the first and second chips, opposite the metallized redistribution structure, wherein a bond line thickness (BLT) between the heat spreader and the inactive side of both the first and second chips comprises SiOto SiOSi to Si, or SiO to Si bonds between the heat spreader and the first and second IC chips.'}2. The IC chip assembly of claim 1 , wherein the metallized redistribution structure has a thickness less than 50 μm.3. The ...

SEMICONDUCTOR DEVICE PACKAGE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device package includes a first circuit layer, a second circuit layer, a first semiconductor die and a second semiconductor die. The first circuit layer includes a first surface and a second surface opposite to the first surface. The second circuit layer is disposed on the first surface of the first circuit layer. The first semiconductor die is disposed on the first circuit layer and the second circuit layer, and electrically connected to the first circuit layer and the second circuit layer. The second semiconductor die is disposed on the second circuit layer, and electrically connected to the second circuit layer. 1. A semiconductor device package , comprising:a first redistribution layer (RDL) including a first surface and a second surface opposite to the first surface;a second RDL disposed on the first surface of the first RDL;a first semiconductor die disposed on the first RDL and the second RDL, and electrically connected to the first RDL and the second RDL; anda second semiconductor die disposed on the second RDL, and electrically connected to the second RDL.2. The semiconductor device package of claim 1 , wherein the second semiconductor die is further disposed on the first RDL and electrically connected to the first RDL.3. The semiconductor device package of claim 1 , wherein the second RDL comprises a bridge die.4. (canceled)5. The semiconductor device package of claim 1 , further comprising:a plurality of first conductive structures disposed between the first semiconductor die and the first RDL and electrically connecting the first semiconductor die to the first RDL, and disposed between the second semiconductor die and the first RDL and electrically connecting the second semiconductor die to the first RDL; anda plurality of second conductive structures disposed between the first semiconductor die and the second RDL and electrically connecting the first semiconductor die to the second RDL, and disposed between the second semiconductor die ...

PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME

A package structure and a method of manufacturing the same are provided. The package structure includes a substrate, a redistribution layer (RDL) structure, a first die, an encapsulant and a plurality of conductive terminals. The RDL structure is disposed on and electrically connected to the substrate. A width of the RDL structure is less than a width of the substrate. The first die is disposed on the substrate and the RDL structure. The first connectors of the first die are electrically connected to the RDL structure. The second connectors of the first die are electrically connected to the substrate. A first pitch of two adjacent first connectors is less than a second pitch of two adjacent second connectors. The encapsulant is on the substrate to encapsulate the RDL structure and the first die. The conductive terminals are electrically connected to the first die through the substrate and the RDL structure. 1. A package structure , comprising:a substrate;a redistribution layer (RDL) structure disposed on and electrically connected to the substrate, wherein a width of the RDL structure is less than a width of the substrate; a plurality of first connectors electrically connected to the RDL structure; and', 'a plurality of second connectors electrically connected to the substrate,', 'wherein a first pitch of two adjacent first connectors is less than a second pitch of two adjacent second connectors;, 'a first die on the substrate and the RDL structure, comprisingan encapsulant on the substrate, encapsulating the RDL structure and the first die; anda plurality of conductive terminals, electrically connected to the first die through the substrate and the RDL structure.2. The package structure of claim 1 , wherein the RDL structure comprises a redistribution layer claim 1 , the substrate comprises a conductive layer claim 1 , and a pitch of the redistribution layer is less than a pitch of the conductive layer.3. The package structure of claim 1 , whereinthe substrate ...

Chip structure and manufacturing method thereof

A chip structure includes a first substrate, a second substrate, a conductive via, and a redistribution layer. The first substrate has a first inclined sidewall. The second substrate is located on a bottom surface of the first substrate, and has an upper portion and a lower portion. The lower portion extends from the upper portion. The upper portion is between the first substrate and the lower portion. The upper portion has a second inclined sidewall, and a slope of the first inclined sidewall is substantially equal to a slope of the second inclined sidewall. The conductive via is in the lower portion. The redistribution layer extends from a top surface of the first substrate to a top surface of the lower portion of the second substrate sequentially along the first inclined sidewall and the second inclined sidewall, and is electrically connected to the conductive via.

IMAGE PICKUP APPARATUS

An image pickup apparatus includes: an image pickup device including a light receiving surface, an opposite surface, and an inclined surface, and provided with light receiving surface electrodes formed on the light receiving surface; cover glass joined so as to cover the light receiving surface; and a wiring board including second bond electrodes, wherein back surfaces of the light receiving surface electrodes being exposed to an opposite surface side, extended wiring patterns extended from the respective back surfaces of the light receiving surface electrodes through the inclined surface to the opposite surface, each of the extended wiring patterns including a first bond electrode, and the first bond electrode and the second bond electrode being bonded through a bump. 1. An image pickup apparatus comprising:an image pickup device including a light receiving surface where a light receiving portion is formed, an opposite surface opposing the light receiving surface, and an inclined surface inclined at an acute first angle to the light receiving surface, and provided with a plurality of light receiving surface electrodes electrically connected with the light receiving portion and formed on the light receiving surface;a transparent member joined so as to cover the light receiving surface; anda wiring board including a plurality of second bond electrodes on a main surface,wherein the transparent member and the plurality of light receiving surface electrodes are extended to an outside of an end side of the inclined surface, and back surfaces of the plurality of light receiving surface electrodes are exposed to a side of the opposite surface,the image pickup device includes a plurality of extended wiring patterns extended from the respective back surfaces of the plurality of light receiving surface electrodes through the inclined surface to the opposite surface, each of the extended wiring patterns including a first bond electrode on the opposite surface, andthe main ...

PRINTABLE 3D ELECTRONIC STRUCTURE

A printable electronic component includes a component substrate and a circuit disposed in or on the component substrate. One or more electrically conductive connection posts protrude from the component substrate. One or more electrically conductive component contact pads are exposed on or over the component substrate on a side of the component substrate opposite the one or more connection posts. The one or more component contact pads and the one or more electrically conductive connection posts are both electrically connected to the circuit. The components can be printed onto a destination substrate and electrically connected to contact pads on the destination substrate through the connection posts. The components can also be printed onto other components and electrically connected through the connection posts and component contact pads to form a three-dimensional electronic structure. 1. A printable electronic component , comprising:a component substrate and a circuit disposed in or on the component substrate;one or more electrically conductive connection posts protruding from the component substrate; andone or more electrically conductive exposed component contact pads on or over the component substrate on a side of the component substrate opposite the one or more connection posts, the one or more component contact pads and the one or more electrically conductive connection posts both electrically connected to the circuit.2. The printable electronic component of claim 1 , wherein the circuit is a passive circuit claim 1 , the circuit comprises only one or more wires claim 1 , the circuit comprises resistors claim 1 , the circuit comprises capacitors claim 1 , the circuit is an active circuit comprising one or more transistors claim 1 , or the circuit comprises at least one passive element and at least one active element.3. The printable electronic component of claim 1 , wherein the component substrate has a component surface on or over which the circuit is disposed ...

SEMICONDUCTOR DEVICE WITH CONDUCTIVE FILM SHIELDING

A packaged semiconductor device has a conductive film that covers a first major surface and surrounding side surfaces of an integrated circuit die. The conductive film provides five-sided shielding of the integrated circuit die. A metal heat sink may be attached to an exposed major surface of the conductive film for dissipating heat generated by the die. 1. A method of assembling a plurality of semiconductor devices , comprising:attaching a plurality of wafer level semiconductor devices to a carrier, wherein active sides of the devices are attached to the carrier, and passive sides of the devices are face-up; andcovering the passive sides of the devices with a conductive film, wherein the conductive film also covers lateral sides of the devices.2. The method of claim 1 , wherein the conductive film is laminated to the passive and lateral sides of the devices.3. The method of claim 1 , herein the semiconductor devices comprise wafer-level chip scale packages (WLCSP) that include conductive balls on the active sides.4. The method of claim 3 , wherein the wafer-level chip scale packages include a redistribution layer formed between semiconductor dies thereof and the conductive balls.5. The method of claim 1 , wherein the conductive film comprises a die attach film with an inner metal filler.6. The method of claim 5 , wherein the wafer-level chip scale packages include a redistribution layer formed between semiconductor dies thereof and the conductive balls claim 5 , and the conductive film is electrically connected to the redistribution layer.7. The method of claim 1 , further comprising:attaching a metal carrier to a top, exposed surface of the conductive film.8. The method of claim 7 , wherein the metal carrier is attached to the conductive film with an adhesive.9. The method of claim 1 , further comprising:separating adjacent ones of the film-covered devices from each other to provide individual shielded devices.10. A packaged semiconductor device assembled ...

SEMICONDUCTOR PACKAGE STRUCTURE

The present disclosure provides a semiconductor package structure having a semiconductor die having an active surface, a conductive bump on the active surface, configured to electrically couple the semiconductor die to an external circuit, the conductive bump having a bump height, a dielectric encapsulating the semiconductor die and the conductive bump, and a plurality of fillers in the dielectric, each of the fillers comprising a diameter, wherein a maximum diameter of the fillers is smaller than the bump height. 1. A semiconductor package structure , comprising:a semiconductor substrate having an active surface and a sidewall;a conductive bump on the active surface, the conductive bump having a stand-off height extending along a first direction;a passivation on the active surface;an encapsulant encapsulating the semiconductor substate and encapsulating the conductive bump, wherein the encapsulant contacting the sidewall of the semiconductor substrate; anda plurality of fillers in the encapsulant, wherein a diameter of the fillers along the first direction is smaller than the stand-off height.2. (canceled)3. The semiconductor package structure of claim 1 , further comprising:a conductive pad on the active surface, wherein the conductive pad is covered by the passivation.4. (canceled)5. The semiconductor package structure of claim 1 , wherein the encapsulant comprises a surface parallel and proximal to the active surface of the semiconductor substrate claim 1 , the surface of the encapsulant being substantially coplanar with a top surface of the conductive bump.613-. (canceled)14. A semiconductor package structure claim 1 , comprising:a semiconductor substrate having an active surface and a sidewall;a conductive pad on the active surface;a passivation covering the pad and over the active surface;a conductive bump on the conductive pad; andan encapsulant encapsulating the semiconductor substrate and encapsulating the conductive bump, wherein the encapsulant ...

Multiple bond via arrays of different wire heights on a same substrate

An apparatus relating generally to a substrate is disclosed. In such an apparatus, a first bond via array has first wires extending from a surface of the substrate. A second bond via array has second wires extending from the surface of the substrate. The first bond via array is disposed at least partially within the second bond via array. The first wires of the first bond via array are of a first height. The second wires of the second bond via array are of a second height greater than the first height for coupling of at least one die to the first bond via array at least partially disposed within the second bond via array. 1. A method , comprising:obtaining a substrate;forming a first bond via array of first wire bond wires (“first wires”) extending from a surface of the substrate;forming a second bond via array of second wire bond wires (“second wires”) extending from the surface of the substrate;wherein the first bond via array and the second bond via array are external to the substrate;wherein the first bond via array is disposed within a region of the second bond via array;wherein the first wires of the first bond via array are of a first height; andwherein the second wires of the second bond via array are of a second height greater than the first height for a package-on-package configuration.2. The method according to claim 1 , further comprising:coupling a first die to the first bond via array; andcoupling a second die to the second bond via array disposed over the first die.3. The method according to claim 2 , wherein the first die and at least a portion of the second die are located within a perimeter of the second bond via array.4. The method according to claim 2 , further comprising coupling opposing surfaces of the first die and the second die to one another.5. The method according to claim 2 , further comprising attaching the first wires of the first bond via array and the second wires of the second bond via array by fusion bonding to the surface of the ...

FAN-OUT SEMICONDUCTOR PACKAGE

A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface disposed to oppose the active surface; a dummy chip disposed in the through-hole and spaced apart from the semiconductor chip; a second connection member disposed on the first connection member, the dummy chip, and the active surface of the semiconductor chip; and an encapsulant encapsulating at least portions of the first connection member, the dummy chip, and the inactive surface of the semiconductor chip. The first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads. 1. A fan-out semiconductor package comprising:a rigid member having a through-hole;a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface disposed to oppose the active surface;a dummy chip disposed in the through-hole and spaced apart from the semiconductor chip;a connection member disposed on the rigid member, the dummy chip, and the active surface of the semiconductor chip; andan encapsulant encapsulating at least portions of the rigid member, the dummy chip, and the inactive surface of the semiconductor chip,wherein the connection member includes a redistribution layer electrically connected to the connection pads.2. The fan-out semiconductor package of claim 1 , wherein the dummy chip is electrically insulated from the semiconductor chip.3. The fan-out semiconductor package of claim 1 , wherein the dummy chip decreases a warpage generated through disposition of the semiconductor chip.4. The fan-out semiconductor package of claim 1 , wherein the rigid member includes a first redistribution layer exposed to a first surface thereof and contacting the connection member claim 1 , and a second ...

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure includes a die, a molding surrounding the die, an interconnect structure disposed over the die and the molding, and a first seal ring. The interconnect structure includes a dielectric layer and a conductive member disposed within the dielectric layer. The first seal ring is disposed within the dielectric layer and disposed over the molding. 1. A semiconductor structure , comprising:a die;a molding surrounding the die;an interconnect structure disposed over the die and the molding, and including a dielectric layer and a conductive member disposed within the dielectric layer; anda first seal ring is disposed within the dielectric layer and disposed over the molding.2. The semiconductor structure of claim 1 , wherein the first seal ring is disposed adjacent to an edge of the dielectric layer.3. The semiconductor structure of claim 1 , wherein the first seal ring is electrically connected to the conductive member.4. The semiconductor structure of claim 1 , wherein the first seal ring is connected to an electrical ground through a conductive bump.5. The semiconductor structure of claim 1 , wherein the first seal ring surrounds the conductive member.6. The semiconductor structure of claim 1 , wherein a portion of the dielectric layer is disposed between the first seal ring and the molding.7. The semiconductor structure of claim 1 , further comprising a second seal ring vertically extended within the die claim 1 , wherein the second seal ring is disposed adjacent to the edge of the die or the molding.8. The semiconductor structure of claim 7 , wherein a width of the first seal ring is substantially greater than a width of the second seal ring.9. The semiconductor structure of claim 1 , further comprising a via disposed within and extended through the molding.10. The semiconductor structure of claim 9 , wherein the first seal ring is electrically isolated from the via.11. The semiconductor structure of claim 9 , further comprising a conductive bump ...

Integrated circuit die having a split solder pad

The invention relates to an electronic system comprising: an integrated circuit die having: at least 2 bond pads a redistribution layer, said redistribution layer having: at least a solder pad comprising 2 portions arranged to enable an electrical connection between each other by a same solder ball placed on said solder pad, but electrically isolated of each other in the absence of a solder ball on the solder pad at least 2 redistribution wires, each one connecting one of the 2 portions to one of the 2 bond pads, a second bond pad connected via a second redistribution wire to a second portion of the solder pad being dedicated to testing said integrated circuit die a grounded printed circuit board track, a solder ball being placed between the solder pad and the printed circuit board track.

INTEGRATED CIRCUIT DIE HAVING A SPLIT SOLDER PAD

An integrated circuit die having at least two bond pads, a redistribution layer, the redistribution layer including at least one solder pad including comprising two portions arranged to enable an electrical connection between each other by a same solder ball placed on the solder pad, but electrically isolated of each other in the absence of a solder ball on the solder pad at least two redistribution wires, each one connecting one of the two portions to one of the two bond pads, a first bond pad connected via a first redistribution wire to a first portion of the solder pad being dedicated to digital ground and a second bond pad connected via a second redistribution wire to a second portion of the solder pad being dedicated to analog ground. 1. An integrated circuit die comprising:at least two bond pads at least one solder pad comprising two portions arranged to enable an electrical connection between each other by a same solder ball placed on said solder pad, but electrically isolated of each other in the absence of a solder ball on the solder pad,', 'at least two redistribution wires, each one connecting one of the two portions to one of the two bond pads, a first bond pad connected via a first redistribution wire to a first portion of the solder pad being dedicated to digital ground and a second bond pad connected via a second redistribution wire to a second portion of the solder pad being dedicated to analog ground., 'a redistribution layer, said redistribution layer comprising2. The integrated circuit die according to claim 1 , wherein the portions have a shape of a demi-disk.3. An electronic system comprising:{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'an integrated circuit die according to ,'}a grounded printed circuit board track connected to the first bond pad via a first bond-wire and to the second bond pad via a second bond wire.4. The electronic system comprising:{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'an integrated circuit die according ...

Semiconductor Device and Method of Forming Insulating Layers Around Semiconductor Die

A semiconductor device has a semiconductor wafer including a plurality of semiconductor die and a plurality of contact pads formed over a first surface of the semiconductor wafer. A trench is formed partially through the first surface of the semiconductor wafer. An insulating material is disposed over the first surface of the semiconductor wafer and into the trench. A conductive layer is formed over the contact pads. The conductive layer can be printed to extend over the insulating material in the trench between adjacent contact pads. A portion of the semiconductor wafer opposite the first surface of the semiconductor wafer is removed to the insulating material in the trench. An insulating layer is formed over a second surface of the semiconductor wafer and side surfaces of the semiconductor wafer. The semiconductor wafer is singulated through the insulating material in the first trench to separate the semiconductor die. 1. A method of making a semiconductor device , comprising:providing a semiconductor wafer including a contact pad formed over a first surface of the semiconductor wafer;forming a trench into the first surface of the semiconductor wafer;disposing an insulating material over the first surface of the semiconductor wafer and into the trench, wherein the insulating material covers the contact pad;grinding the insulating material over the first surface of the semiconductor wafer to expose the contact pad;backgrinding a second surface of the semiconductor wafer opposite the first surface to expose the insulating material in the trench;forming an insulating layer over the second surface of the semiconductor wafer after backgrinding; anddicing the semiconductor wafer through the trench.2. The method of claim 1 , further including forming a nickel plating over the contact pad prior to disposing the insulating material.3. The method of claim 2 , wherein grinding the insulating material exposes the nickel plating.4. The method of claim 1 , further including ...

SEMICONDUCTOR PACKAGE

An embodiment method includes providing a fan-out package structure having cavities to confine semiconductor dies by applying adhesive material which has similar coefficient of thermal expansion (CTE) with semiconductor dies in the gap between the edges of dies and the edges of cavities. The method further includes forming a molding compound over a fan-out package structure with semiconductor dies, building fan-out redistribution layers over a fan-out package structure with semiconductor dies and electrically connected to the semiconductor dies. 1. A semiconductor package , comprising:a fan-out package structure having a first cavity formed thereon;a first die disposed in the first cavity of the fan-out package structure;an adhesive hardened in the first cavity of the fan-out package structure, the adhesive surrounding the first die to fix the first die in the first cavity of the fan-out package structure; anda molding compound formed over the fan-out package structure.2. The semiconductor package as claimed in claim 1 , further comprising:a redistribution layer disposed under the fan-out package structure;metal pads disposed between the first die and the redistribution layer, wherein the metal pads are electrically connected to the first die and the redistribution layer; andsolder balls disposed under the redistribution layer.3. The semiconductor package as claimed in claim 2 , wherein the fan-out package structure further has a second cavity formed thereon claim 2 , the semiconductor package further comprising:a second die disposed in the second cavity of the fan-out package structure and electrically connected to the redistribution layer by metal pads.4. The semiconductor package as claimed in claim 1 , further comprising:a redistribution layer disposed under the fan-out package structure; andthrough-package interconnections formed around the first die, wherein the through-package interconnections penetrate the molding compound and the fan-out package structure ...

Electronic package and implantable medical device including same

Various embodiments of an electronic package and an implantable medical device that includes such package are disclosed. The electronic package includes a monolithic package substrate having a first major surface and a second major surface, an integrated circuit disposed in an active region of the package substrate, and a conductive via disposed through an inactive region of the package substrate and extending between the first major surface and the second major surface of the package substrate. The conductive via is separated from the active region by a portion of the inactive region of the substrate.

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device. 113-. (canceled)14. A manufacturing method of a semiconductor device , comprising the steps of:(a) providing a semiconductor wafer equipped with a plurality of device formation regions,each device formation region having a semiconductor circuit, a pad electrically coupled to the semiconductor circuit, a first insulating film formed over the pad such that a surface portion of the pad is exposed from an opening of the first insulating film, and a second insulating film formed over the first insulating film such that the surface portion of the pad is exposed from the second insulating film;(b) contacting a probe needle to a first region of the surface portion of the pad of each device formation region; and(c) after the step (b), forming an interconnect layer over a second region of the surface portion of each pad adjacent to the first region by plating, such that the interconnect layer is electrically coupled to the pad at the second region.15. The manufacturing method of a semiconductor device according to claim 14 , further comprising the steps of:(d) after the step (c), coupling a conductive member to one end portion of the ...

METHOD AND SYSTEM FOR SUBSTRATE THINNING

A method and a system for thinning a substrate are provided. The method includes at least the following steps. A liquid seal is provided at an interface between a chuck and a substrate disposed on the chuck. The substrate is thinned during the liquid seal is provided. 1. A manufacturing method of thinning a substrate , comprising:providing a liquid seal at an interface between a chuck and a substrate disposed on the chuck; andthinning the substrate during the liquid seal is provided.2. The manufacturing method according to claim 1 , wherein providing the liquid seal comprises:laterally providing a first liquid to an edge of the substrate to seal a gap between the chuck and the substrate.3. The manufacturing method according to claim 1 , further comprising:performing vacuum suction to the substrate through the chuck when the substrate is thinned.4. The manufacturing method according to claim 1 , further comprising:providing a second liquid downwardly to the substrate when thinning the substrate.5. The manufacturing method according to claim 1 , further comprising:transferring the substrate to place on the chuck via a holding device before providing the liquid seal; andreleasing the substrate from the holding device before thinning the substrate.6. The manufacturing method according to claim 1 , wherein the substrate comprises an insulating encapsulation and a conductive feature covered by the insulating encapsulation claim 1 , and after the substrate is thinned claim 1 , at least a portion of the conductive feature of the substrate is exposed by the insulating encapsulation.7. A manufacturing method for thinning a semiconductor structure claim 1 , comprising:forming a semiconductor structure, wherein the semiconductor structure comprises a first semiconductor die and a first insulating encapsulation encapsulating the first semiconductor die;placing the semiconductor structure on a supporting assembly, wherein the supporting assembly comprises a chuck and a first ...

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

A semiconductor device structure and a method for manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device structure (e.g., a sensor device structure), and method for manufacturing thereof, that comprises a three-dimensional package structure free of wire bonds, through silicon vias, and/or flip-chip bonding. 120-. (canceled)21. A semiconductor package comprising:a substrate comprising a top substrate surface, a bottom substrate surface, substrate sides between the top and bottom substrate surfaces, and a first bond pad on the top substrate surface;a semiconductor die comprising a top die surface, a bottom die surface, die sides between the top and bottom die surfaces, and a second bond pad on the top die surface, where the bottom die surface is mounted on the top substrate surface; a top dielectric layer surface;', 'a bottom dielectric layer surface on at least the top substrate surface and the top die surface;', 'a first dielectric layer aperture that extends from the top dielectric layer surface to the first bond pad; and', 'a second dielectric layer aperture that extends from the top dielectric layer surface to the second bond pad; and, 'a dielectric layer having a single layer of a single dielectric material on the substrate and the semiconductor die, where the dielectric layer comprisesa conductive layer on the dielectric layer that extends between and electrically connects the first and second bond pads.22. The semiconductor package of claim 21 , wherein the dielectric layer directly contacts the top substrate surface and the top die surface.23. The semiconductor package of claim 21 , wherein the substrate comprises a semiconductor die.24. The semiconductor package of claim 23 , wherein the semiconductor die comprises semiconductor circuitry.25. The semiconductor package of claim 21 , wherein the bottom die surface is mounted directly to the top substrate surface.26. The semiconductor ...

MANUFACTURING METHOD OF CHIP PACKAGE

A manufacturing method of a chip package includes forming a temporary bonding layer on a carrier; forming an encapsulation layer on a top surface of a wafer or on the temporary bonding layer; bonding the carrier to the wafer, in which the encapsulation layer covers a sensor and a conductive pad of the wafer; patterning a bottom surface of the wafer to form a through hole, in which the conductive pad is exposed through the through hole; forming an isolation layer on the bottom surface of the wafer and a sidewall of the through hole; forming a redistribution layer on the isolation layer and the conductive pad that is in the through hole; forming a passivation layer on the isolation layer and the redistribution layer; and removing the temporary bonding layer and the carrier. 1. A manufacturing method of a chip package , comprising:forming a temporary bonding layer on a carrier;forming an encapsulation layer on a top surface of a wafer or on the temporary bonding layer;bonding the carrier to the wafer, wherein the encapsulation layer and the temporary bonding layer are located between the wafer and the carrier, and the encapsulation layer covers a sensor and a conductive pad of the wafer;patterning a bottom surface of the wafer to form a through hole, wherein the conductive pad is exposed through the through hole;forming an isolation layer on the bottom surface of the wafer and a sidewall of the through hole;forming a redistribution layer on the isolation layer and the conductive pad that is in the through hole;forming a passivation layer on the isolation layer and the redistribution layer, wherein the passivation layer has an opening, and a portion of the redistribution layer is in the opening; andremoving the temporary bonding layer and the carrier.2. The manufacturing method of the chip package of claim 1 , further comprising:forming a conductive structure on the portion of the redistribution layer.3. The manufacturing method of the chip package of claim 2 , further ...

Semiconductor Device and Method of Forming Insulating Layers Around Semiconductor Die

A semiconductor device has a semiconductor wafer including a plurality of semiconductor die and a plurality of contact pads formed over a first surface of the semiconductor wafer. A trench is formed partially through the first surface of the semiconductor wafer. An insulating material is disposed over the first surface of the semiconductor wafer and into the trench. A conductive layer is formed over the contact pads. The conductive layer can be printed to extend over the insulating material in the trench between adjacent contact pads. A portion of the semiconductor wafer opposite the first surface of the semiconductor wafer is removed to the insulating material in the trench. An insulating layer is formed over a second surface of the semiconductor wafer and side surfaces of the semiconductor wafer. The semiconductor wafer is singulated through the insulating material in the first trench to separate the semiconductor die. 1. A method of making a semiconductor device , comprising:providing a semiconductor wafer including a contact pad formed over a first surface of the semiconductor wafer;forming a first trench into the first surface of the semiconductor wafer;disposing an insulating material over the first surface of the semiconductor wafer and into the first trench, wherein the contact pad is exposed from the insulating material and the insulating material includes a planar section extending from the contact pad to over the first trench;forming a conductive layer over the contact pad;backgrinding a second surface of the semiconductor wafer to expose the insulating material in the first trench;forming an insulating layer over the second surface of the semiconductor wafer; andsingulating the semiconductor wafer through the first trench.2. The method of claim 1 , wherein a portion of the conductive layer includes a footprint that is coextensive with a footprint of the contact pad.3. The method of claim 1 , wherein the insulating material and insulating layer enclose a ...

PHOTOSENSITIVE CHIP PACKAGING STRUCTURE AND PACKAGING METHOD THEREOF

An image sensor chip package and a packaging method thereof are provided. The image sensor chip package includes: an image sensor chip having a first surface and a second surface opposite to each other, a photosensitive region being arranged on the first surface; a protective cover plate having a third surface and a fourth surface opposite to each other, the third surface covering the first surface; and a light shielding layer arranged on the fourth surface of the protective cover plate, the light shielding layer having an opening, and the photosensitive region being exposed through the opening. The light shielding layer includes a light absorbing layer located on the fourth surface and a metal layer located on the light absorbing layer. 1. An image sensor chip package , comprising:an image sensor chip having a first surface and a second surface opposite to each other, a photosensitive region being arranged on the first surface;a protective cover plate having a third surface and a fourth surface opposite to each other, the third surface covering the first surface; anda light shielding layer arranged on the fourth surface of the protective cover plate, the light shielding layer having an opening, and the photosensitive region being exposed through the opening, whereinthe light shielding layer comprises a light absorbing layer located on the fourth surface and a metal layer located on the light absorbing layer.2. The image sensor chip package according to claim 1 , wherein the light absorbing layer is made of black glue.3. The image sensor chip package according to claim 1 , wherein the light absorbing layer is made of black photosensitive glue.4. The image sensor chip package according to claim 1 , wherein the metal layer is processed by surface blackening treatment.5. The image sensor chip package according to claim 4 , wherein the metal layer is made of aluminum.6. The image sensor chip package according to claim 1 , wherein a support dam is arranged on the third ...

EMBEDDED COMPONENT PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

An embedded component package structure including a dielectric structure, a semiconductor chip and a patterned conductive layer is provided. The semiconductor chip is embedded in the dielectric structure, and the dielectric structure encapsulates the semiconductor chip and has a first thickness. The semiconductor chip having a second thickness, and the first thickness is greater than the second thickness, and a ratio of the first thickness to the second thickness is between 1.1 and 28.4. The patterned conductive layer covers an upper surface of the dielectric structure and extending into a first opening of the dielectric structure. The first opening exposes an electrical pad of the semiconductor chip, and the patterned conductive layer is electrically connected to the electrical pad of the semiconductor chip. 1. An embedded component package structure , comprising:a dielectric structure;a semiconductor chip embedded in the dielectric structure, the dielectric structure encapsulating the semiconductor chip and having a first thickness, the semiconductor chip having a second thickness, the first thickness being greater than the second thickness, and a ratio of the first thickness to the second thickness being between 1.1 and 28.4; anda patterned conductive layer covering an upper surface of the dielectric structure and extending into a first opening of the dielectric structure, the first opening exposing an electrical pad of the semiconductor chip, and the patterned conductive layer being electrically connected to the electrical pad of the semiconductor chip.2. The package structure of claim 1 , wherein the first thickness is between 110 and 1420 μm claim 1 , and the second thickness is between 100 and 50 μm.3. The package structure of claim 1 , wherein a portion of the upper surface of the dielectric structure is dry sandblasted to form the first opening recessed into the dielectric structure.4. The package structure of claim 1 , wherein a lower surface of the ...

COMPONENT TERMINATIONS FOR SEMICONDUCTOR PACKAGES

Systems and methods are provide to form one or more pads on at least one surface associated with a portion of a component, for example, a component associated with a surface-mounted device (SMD). Further, the systems and methods are directed to providing metal (for example, copper, Cu) layers on the surface of one or more terminations (for example, solder termination pads) of an electrical component. In one embodiment, the metal layers include metal termination pads that are fabricated on a carrier layer; components can be soldered to these termination pads, then the components with the metal pads can be debonded from the carrier layer. As such, the solder terminations of the components can be covered by the metal pads. 1. A solid assembly comprising:a first termination member having a first end, a second end opposite the first end;a second termination member having a first end, a second end opposite the first end;a coupling element mechanically connected to the first termination member and mechanically connected to the second termination member;a first pad that is at least partially disposed on the first end of the first termination member; anda second pad that is at least partially disposed on the first end of the second termination member.2. The solid assembly of claim 1 , wherein the first end of the first termination member and the first end of second termination member are coplanar.3. The solid assembly of claim 1 , wherein the first termination member has a first side surface and the second termination member has a second side surface claim 1 , and the coupling element is mechanically connected to the first termination member at the first side surface and the coupling element is mechanically connected to the second termination member at the second side surface.4. The solid assembly of claim 1 , wherein the coupling element is mechanically connected to the first termination member at the second end of the first termination member and the coupling element is ...

Semiconductor packages including through electrodes and methods of manufacturing the same

A semiconductor package includes a substrate and a plurality of semiconductor chips stacked on the substrate. Each of the semiconductor chips has a front surface, a rear surface opposite to the front surface, a sidewall surface connecting the front surface to the rear surface, a vertical through electrode extending from the front surface toward the rear surface with a predetermined depth, and a horizontal through electrode laterally extending from the sidewall surface to be connected to the vertical through electrode. At least one connection member is disposed on the sidewall surfaces of the semiconductor chips to connect the horizontal through electrodes of the semiconductor chips to each other. Related methods are also provided.

Method for fabricating a semiconductor package

A method for fabricating a semiconductor package is provided. Semiconductor dice are disposed on a top surface of a carrier. Each of the semiconductor dice has an active surface and a bottom surface that is opposite to the active surface. Input/output (I/O) pads are distributed on the active surface. Interconnect features are printed on the carrier and on the active surface of each of the semiconductor dice. The top surface of the carrier, the semiconductor dice and the interconnect features is encapsulated with an encapsulant. The carrier is then removed.

FAN-OUT SEMICONDUCTOR PACKAGE

A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; and a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip. The first interconnection member and the second interconnection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip, and the encapsulant fills spaces between walls of the through-hole and side surfaces of the semiconductor chip, and at least portions of the encapsulant extend to a space between the first interconnection member and the second interconnection member and a space between the active surface of the semiconductor chip and the second interconnection member. 1. A fan-out semiconductor package comprising:a first interconnection member having a through-hole;a semiconductor chip disposed in the through-hole of the first interconnection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; anda second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip,wherein the first interconnection member and the second interconnection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip, andthe encapsulant fills spaces between walls of the through-hole and side surfaces of the semiconductor chip, and at least portions of the encapsulant extend to a space between the ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor substrate having a first surface, which includes an element forming region and an element isolation region, and a second surface opposite to the first surface, a semiconductor element formed on the semiconductor substrate in the element forming region, an insulator formed on the semiconductor substrate in the element isolation region, a first wiring layer formed on the first surface of the semiconductor substrate, the first wiring layer being connected to the semiconductor element, an alignment mark formed on the semiconductor substrate in the element isolation region, the entire alignment mark overlapping with the insulator in a plan view of the semiconductor device, and a second wiring layer formed on the second surface of the semiconductor substrate. 1. A semiconductor device , comprising:a semiconductor substrate having a primary surface;an insulator filling a recess in the primary surface;a semiconductor element disposed on the primary surface, the semiconductor element being sandwiched by the insulator in a plan view; andan alignment mark overlapping with the insulator in a plan view,wherein a distance between a bottom surface and a top surface of the insulator that sandwiches the semiconductor element in a plan view is equal to a distance between a bottom surface and a top surface of the insulator overlapping the alignment mark in a plan view.2. The semiconductor device according to claim 1 , wherein the semiconductor element includes a gate electrode claim 1 , andwherein the alignment mark is formed in the same layer as the gate electrode.3. The semiconductor device according to claim 1 , further comprising a first wiring layer formed above the primary surface having an insulating layer therebetween claim 1 ,wherein the alignment mark is formed in the same layer as the first wiring layer.4. The semiconductor device according to claim 1 , wherein the semiconductor substrate has a rear surface that faces the ...

Integrated Circuit Dies Having Alignment Marks and Methods of Forming Same

Dies having alignment marks and methods of forming the same are provided. A method includes forming a device on a substrate. A plurality of contact pads is formed over the substrate and the device. Simultaneously with forming the plurality of contact pads, one or more alignment marks are formed over the substrate and the device. 1. A method comprising:forming a device on a substrate;after forming the device, forming a plurality of contact pads over the substrate and the device; andsimultaneously with forming the plurality of contact pads, forming one or more alignment marks over the substrate and the device;forming a passivation layer over the plurality of contact pads and the one or more alignment marks; andpatterning the passivation layer to form a plurality of openings in the passivation layer, wherein each of the plurality of openings expose a first portion of a top surface of a respective one of the plurality of contact pads, and wherein a second portion of the top surface of the respective one of the plurality of contact pads remains unexposed after the patterning.2. The method of claim 1 , further comprising:dicing the substrate to form a die, the die having at least one alignment mark;aligning, using the at least one alignment mark, the die to a workpiece; andattaching the die to the workpiece.3. The method of claim 2 , wherein the die is a discrete semiconductor device chip.4. The method of claim 2 , wherein the workpiece comprises a plurality of encapsulated dies and one or more redistribution lines (RDLs) on plurality of encapsulated dies claim 2 , the die being attached to the one or more RDLs claim 2 , the one or more RDLs being interposed between the plurality of encapsulated dies and the die.5. The method of claim 1 , wherein forming the plurality of contact pads and the one or more alignment marks comprises:depositing a conductive layer over the substrate and the devices; andpatterning the conductive layer to form the plurality of contact pads and ...

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an integrated circuit (IC) component, an insulating layer laterally encapsulating sidewalls of the IC component, a redistribution structure disposed on the insulating layer and the IC component, and a warpage control portion coupling to a back side of the IC component opposite to the redistribution structure. The redistribution structure is electrically connected to the IC component. The warpage control portion includes a substrate, a patterned dielectric layer disposed between the substrate and the IC component, and a metal pattern embedded in the patterned dielectric layer and electrically isolated from the IC component. 1. A semiconductor structure , comprising:an integrated circuit (IC) component;an insulating layer laterally encapsulating sidewalls of the IC component;a redistribution structure disposed on the insulating layer and the IC component, the redistribution structure being electrically connected to the IC component; and a substrate;', 'a patterned dielectric layer disposed between the substrate and the IC component; and', 'a metal pattern embedded in the patterned dielectric layer and electrically isolated from the IC component., 'a warpage control portion coupling to a back side of the IC component opposite to the redistribution structure, the warpage control portion comprising2. The semiconductor structure of claim 1 , further comprising:a bonding layer coupling the warpage control portion to the IC component and the insulating layer.3. The semiconductor structure of claim 1 , wherein the warpage control portion further comprises:an oxide layer interposed between the substrate and the patterned dielectric layer.4. The semiconductor structure of claim 1 , wherein the metal pattern of the warpage control portion is located within a distribution region that underlies a region of the IC component claim 1 , and the metal pattern of the warpage ...

SEMICONDUCTOR DEVICE AND METHOD COMPRISING REDISTRIBUTION LAYERS

A method of making a semiconductor package can include forming a plurality of redistribution layer (RDL) traces disposed over active surfaces of a plurality of semiconductor die and electrically connected to contact pads on the plurality of semiconductor die. The method can include disposing an encapsulant material over the active surfaces, contacting at least four side surfaces of each of the plurality of semiconductor die, and disposed over the plurality of RDL traces. The method can also include forming a via through the encapsulant material to expose at least one of the plurality of RDL traces, forming an electrical interconnect disposed within the via and coupled to the at least one RDL trace, and singulating the plurality of semiconductor packages through the encapsulant material to leave an offset of 30-140 μm of the encapsulant material disposed around a periphery of each of the plurality of semiconductor die. 1. A method of making a plurality semiconductor packages , comprising:forming a plurality of redistribution layer (RDL) traces comprising a thickness greater than 8 μm disposed over active surfaces of a plurality of semiconductor die and electrically connected to contact pads on the plurality of semiconductor die;disposing an encapsulant material over the active surfaces, contacting at least four side surfaces of each of the plurality of semiconductor die, and disposed over the plurality of RDL traces;forming a via through the encapsulant material to expose at least one of the plurality of RDL traces;forming an electrical interconnect disposed within the via and coupled to the at least one RDL trace; andsingulating the plurality of semiconductor packages through the encapsulant material to leave an offset of 30-140 μm of the encapsulant material disposed around a periphery of each of the plurality of semiconductor die.2. The method of claim 1 , further comprising:forming the plurality of RDL traces comprising a thickness or height greater than 20 μm; ...

Method of fabricating wafer-level chip package

A method of fabricating a wafer-level chip package is provided. First, a wafer with two adjacent chips is provided, the wafer having an upper surface and a lower surface, and one side of each chip includes a conducting pad on the lower surface. A recess and an isolation layer extend from the upper surface to the lower surface, which the recess exposes the conducting pad. A part of the isolation layer is disposed in the recess with an opening to expose the conducting pad. A conductive layer is formed on the isolation layer and the conductive pad, and a photo-resist layer is spray coated on the conductive layer. The photo-resist layer is exposed and developed to expose the conductive layer, and the conductive layer is etched to form a redistribution layer. After stripping the photo-resist layer, a solder layer is formed on the isolation layer and the redistribution layer.

SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor substrate including a chip region and an edge region around the chip region, a lower insulating layer on the semiconductor substrate, a chip pad on the lower insulating layer on the chip region, an upper insulating layer provided on the lower insulating layer to cover the chip pad, the upper and different insulating layers including different materials, and a redistribution chip pad on the chip region and connected to the chip pad. The upper insulating layer includes a first portion on the chip region having a first thickness, a second portion on the edge region having a second thickness, and a third portion on the edge region, the third portion extending from the second portion, spaced from the first portion, and having a decreasing thickness away from the second portion. The second thickness is smaller than the first thickness. 1. A semiconductor device , comprising:a semiconductor substrate including a chip region and an edge region around the chip region;a lower insulating layer on the semiconductor substrate;a chip pad on the lower insulating layer on the chip region;an upper insulating layer on the lower insulating layer to cover the chip pad, the upper insulating layer including an insulating material different from the lower insulating layer; anda redistribution chip pad on the chip region to penetrate the upper insulating layer and to be connected to the chip pad, a first portion on the chip region and having a first thickness;', 'a second portion on the edge region, the second portion extending from the first portion and having a second thickness smaller than the first thickness; and', 'a third portion on the edge region, the third portion extending from the second portion, spaced apart from the first portion, and having a decreasing thickness away from the second portion., 'wherein the upper insulating layer includes2. The semiconductor device as claimed in claim 1 , wherein:the upper insulating layer has a ...

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

A package structure including a semiconductor die, an insulating encapsulant, a dielectric layer, and a redistribution layer is provided. The semiconductor die has an active surface, a back surface opposite to the active surface, and a plurality of conductive bumps disposed on the active surface. The insulating encapsulant is encapsulating the semiconductor die. The redistribution layer is disposed on the he insulating encapsulant and electrically connected to the plurality of conductive bumps. The dielectric layer is disposed between the insulating encapsulant and the redistribution layer, wherein the dielectric layer encapsulates at least a portion of each of the plurality of conductive bumps. 1. A package structure , comprising:a semiconductor die having an active surface, a back surface opposite to the active surface, and a plurality of conductive bumps disposed on the active surface;an insulating encapsulant encapsulating the semiconductor die;a redistribution layer disposed on the insulating encapsulant and electrically connected to the plurality of conductive bumps; anda dielectric layer disposed between the insulating encapsulant and the redistribution layer, wherein the dielectric layer encapsulates at least a portion of each of the plurality of conductive bumps.2. The package structure according to claim 1 , wherein a top surface of the dielectric layer is coplanar with a top surface of the plurality of conductive bumps.3. The package structure according to claim 1 , wherein sidewalls of the dielectric layer are aligned with sidewalls of the insulating encapsulant and sidewalls of the redistribution layer.4. The package structure according to claim 1 , wherein a height of the plurality of conductive bumps is in a range from 3 μm to 20 μm.5. The package structure according to claim 1 , wherein the insulating encapsulant further covers the active surface of the semiconductor die.6. The package structure according to claim 5 , wherein the plurality of ...

INTERCONNECT STRUCTURES FOR FINE PITCH ASSEMBLY OF SEMICONDUCTOR STRUCTURES

A semiconductor structure includes a substrate having first and second opposing surfaces and a plurality of electrical connections extending between the first and second surfaces. The semiconductor structure also includes one or more interconnect pads having first and second opposing surfaces and one or more sides. The first surface of each one of the interconnect pads is disposed over or beneath select portions of at least the second surface of the substrate and is electrically coupled to select ones of the plurality of electrical connections. The semiconductor structure additionally includes an isolating layer having first and second opposing surfaces and openings formed in select portions of the isolating layer extending between the second surface of the isolating layer and the second surfaces of the interconnect pads. A corresponding method for fabricating a semiconductor structure is also provided. 1. A method for fabricating a semiconductor structure , comprising:providing a substrate having first and second opposing surfaces and a plurality of electrical connections extending between the first and second surfaces;providing one or more interconnect pads having first and second opposing surfaces and one or more sides, wherein the first surface of each one of the interconnect pads is disposed over or beneath select portions of at least the second surface of the substrate and is electrically coupled to select ones of the plurality of electrical connections;applying an isolating layer having first and second opposing surfaces, wherein the first surface of the isolating layer is disposed over the second surface of the substrate and the second surfaces and one or more sides of the interconnect pads;forming openings having a predetermined shape in select portions of the isolating layer extending between the second surface of the isolating layer and the first surface of the isolating layer;providing one or more pad interconnects having a pad portion and an ...

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

A semiconductor device structure and a method for manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device structure (e.g., a sensor device structure), and method for manufacturing thereof, that comprises a three-dimensional package structure free of wire bonds, through silicon vias, and/or flip-chip bonding. 120-. (canceled)21. A semiconductor package comprising:a bottom side signal distribution structure (BSDS) comprising a first lower dielectric layer and a first lower conductive layer, the bottom side signal distribution structure (BSDS) comprising a top BSDS side and a bottom BSDS side; the bottom D1 side is coupled to the top BSDS side; and', 'the first semiconductor die (D1) comprises a D1 terminal;, 'a first semiconductor die (D1) comprising a top D1 side, a bottom D1 side, and a lateral D1 side, wherea package attachment structure coupled to the bottom BSDS side; 'where the encapsulating material laterally surrounds the first semiconductor die (D1) and covers a portion of the top BSDS side;', 'an encapsulating material comprising a top encapsulant side, a bottom encapsulant side, and a lateral encapsulant side,'}and the bottom D2 side is coupled to the top D1 side; and', 'the second semiconductor die (D2) comprises a D2 terminal that is directly coupled to the D1 terminal in a solderless connection., 'a second semiconductor die (D2) comprising a top D2 side, a bottom D2 side, and a lateral D2 side, where22. The semiconductor package of claim 21 , wherein the second semiconductor die (D2) is laterally wider than the first semiconductor die (D1).23. The semiconductor package of claim 21 , wherein the lateral D2 side is coplanar with the lateral encapsulant side.24. The semiconductor package of claim 21 , wherein the D1 terminal is on the bottom D1 side.25. The semiconductor package of claim 21 , comprising a conductive via that is coupled to the top BSDS side and vertically spans at ...

ELECTRONIC SYSTEM HAVING INCREASED COUPLING BY USING HORIZONTAL AND VERTICAL COMMUNICATION CHANNELS

An electronic system supports superior coupling by implementing a communication mechanism that provides at least for horizontal communication for example, on the basis of wired and/or wireless communication channels, in the system. Hence, by enhancing vertical and horizontal communication capabilities in the electronic system, a reduced overall size may be achieved, while nevertheless reducing complexity in printed circuit boards coupled to the electronic system. In this manner, overall manufacturing costs and reliability of complex electronic systems may be enhanced. 1. An apparatus , comprising:an integrated circuit die comprising a semiconductor substrate and a metallization structure;wherein the semiconductor substrate includes integrated circuits and has a top surface and an oppositely arranged bottom surface and a side surface where the integrated circuit die was singulated from a wafer;wherein the metallization structure is mounted above the top surface of the semiconductor substrate and includes at least one contact pad and an electrical connection between the at least one contact pad and the integrated circuits; anda dielectric layer disposed in contact with a top surface of the metallization structure and the side surface of the semiconductor substrate;wherein the dielectric layer comprises a first communication pad that is electrically connected to said at least one contact pad and a second communication pad that is electrically connected to said at least one contact pad;wherein the first communication pad is disposed on a first face of the dielectric layer extending parallel to the top surface of the metallization structure and the second communication pad is disposed on a second face of the dielectric layer extending parallel to the side surface of the semiconductor substrate.2. The apparatus of claim 1 , wherein the second communication pad is electrically insulated from the side surface of the semiconductor substrate by said dielectric layer and ...

PACKAGE COMPRISING A DIE AND DIE SIDE REDISTRIBUTION LAYERS (RDL)

A package that includes a second redistribution portion, a die coupled to the second redistribution portion, an encapsulation layer encapsulating the die, and a first redistribution portion coupled to the second redistribution portion. The first redistribution portion is located laterally to the die. The first redistribution portion is located over the second redistribution portion. The first redistribution portion and the second redistribution portion are configured to provide one or more electrical paths for the die. 1. A package comprising:a second redistribution portion;a die coupled to the second redistribution portion;an encapsulation layer encapsulating the die; and wherein the first redistribution portion is located laterally to the die,', 'wherein the first redistribution portion is located over the second redistribution portion, and, 'a first redistribution portion coupled to the second redistribution portion,'}wherein the first redistribution portion and the second redistribution portion are configured to provide one or more electrical paths for the die.2. The package of claim 1 , at least one first dielectric layer; and', 'a first plurality of interconnects,, 'wherein the first redistribution portion comprises at least one second dielectric layer; and', 'a second plurality of interconnects,, 'wherein the second redistribution portion compriseswherein the first plurality of interconnects and the second plurality of interconnects are configured provide one or more electrical paths for the die.3. The package of claim 2 , further comprising a third redistribution portion comprising:at least one third dielectric layer; anda third plurality of interconnects,wherein the third redistribution portion is located over the second redistribution portion and the encapsulation layer,wherein the first plurality of interconnects, the second plurality of interconnects, and third plurality of interconnects are configured provide one or more electrical paths for the die.4. ...

SEMICONDUCTOR DEVICE, METHOD FOR PRODUCING THE SAME, AND LAMINATE

Disclosed herein is a semiconductor device including: a support; a double-layered adhesive resin layer formed on the support, an insulating layer and a redistribution layer formed on the adhesive resin layer; a chip layer, and a mold resin layer, wherein the adhesive resin layer includes a resin layer A containing a resin decomposable by light irradiation and a resin layer B containing a non-silicone-based thermoplastic resin, the resin layer A and the resin layer B being provided in this order from the support side, the resin decomposable by light irradiation is a resin containing a fused ring in its main chain, and the non-silicone-based thermoplastic resin has a glass transition temperature of 200° C. or higher. 1. A semiconductor device comprising: a support; a double-layered adhesive resin layer formed on the support , an insulating layer and a redistribution layer formed on the adhesive resin layer; a chip layer , and a mold resin layer , wherein the adhesive resin layer comprises a resin layer A containing a resin decomposable by light irradiation and a resin layer B containing a non-silicone-based thermoplastic resin , the resin layer A and the resin layer B being provided in this order from the support side , the resin decomposable by light irradiation is a resin containing a fused ring in its main chain , and the non-silicone-based thermoplastic resin has a glass transition temperature of 200° C. or higher.2. The semiconductor device according to claim 1 , wherein the resin layer A has a light transmittance at a wavelength of 355 nm of 20% or less.4. The semiconductor device according to claim 1 , wherein the non-silicone-based thermoplastic resin contains an aromatic ring in its main chain.5. A method for producing the semiconductor device according to claim 1 , comprising the steps of:(a) forming a resin layer A directly on a support;(b) forming a resin layer B on the resin layer A;(c) forming an insulating layer on the resin layer B and patterning the ...

SEMICONDUCTOR PACKAGE

A semiconductor package including a semiconductor chip having an active surface and a non-active surface opposite to the active surface, a ground member disposed on the active surface of the semiconductor chip, and an electromagnetic shielding member passing through the semiconductor chip, electrically connected to the ground member, and covering at least some regions of the non-active surface of the semiconductor chip may be provided. 1. A semiconductor package comprising:a semiconductor chip having an active surface and a non-active surface opposite to the active surface;a ground member on the active surface of the semiconductor chip; andan electromagnetic shielding member passing through the semiconductor chip and electrically connected to the ground member, and the electromagnetic shielding member covering at least some regions of the non-active surface of the semiconductor chip.2. The semiconductor package of claim 1 , wherein portions of the electromagnetic shielding member passing through the semiconductor chip are connected together to have a shape in a form of a number sign (#) in the semiconductor chip.3. The semiconductor package of claim 1 , wherein portions of the electromagnetic shielding members in the semiconductor chip have a pillar shape.4. The semiconductor package of claim 1 , wherein the electromagnetic shielding member entirely covers the non-active surface of the semiconductor chip.5. The semiconductor package of claim 1 , wherein a side surface of the semiconductor chip is exposed to an outside.6. The semiconductor package of claim 1 , wherein the ground member is exposed through the non-active surface and connected to the electromagnetic shielding member. The semiconductor package of claim 1 , further comprising:a redistribution layer on the active surface of the semiconductor chip; anda connection member electrically connected to the redistribution layer.8. The semiconductor package of claim 1 , further comprising:a molding member covering ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a semiconductor substrate in which a through hole is formed, a first wiring that is provided on a first surface of the semiconductor substrate, an insulating layer provided on an inner surface of the through hole and a second surface of the semiconductor substrate, and a second wiring that is provided on a surface of the insulating layer and electrically connected to the first wiring in an opening. The surface of the insulating layer includes a first region, a second region, a third region, a fourth region that is curved to continuously connect the first and the second regions, and a fifth region that is curved to continuously connect the second and the third regions. An average inclination angle of the second region is smaller than that of the first region and is smaller than that of the inner surface. 1. A semiconductor device comprising:a semiconductor substrate that has a first surface and a second surface opposite to each other and in which a through hole to extend from the first surface to the second surface is formed;a first wiring that is provided on the first surface and has a portion located above a first opening of the through hole on the first surface side;an insulating layer that is provided on an inner surface of the through hole and the second surface and is continuous through a second opening of the through hole on the second surface side; anda second wiring that is provided on a surface of the insulating layer and is electrically connected to the first wiring in an opening of the insulating layer on the first surface side,wherein the surface of the insulating layer includesa tapered first region that reaches the first opening inside the through hole and enlarges from the first surface to the second surface,a tapered second region that reaches the second opening inside the through hole and enlarges from the first surface to the second surface,a third region that faces the second surface outside the through hole,a ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a semiconductor die. A dielectric material surrounds the semiconductor die to form an integrated semiconductor package. There is a contact coupling to the integrated semiconductor package and configured as a ground terminal for the semiconductor package. The semiconductor device further has an EMI (Electromagnetic Interference) shield substantially enclosing the integrated semiconductor package, wherein the EMI shield is coupled with the contact through a path disposed in the integrated semiconductor package. 1. A semiconductor device , comprising:a semiconductor die;an insulative layer surrounding the semiconductor die;a post passivation interconnect (PPI) over the insulative layer and the semiconductor die;a conductive feature in an edge of the insulative layer and extended through the insulative layer, wherein the conductive feature includes a surface exposed from the insulative layer;an EMI (Electromagnetic Interference) shield substantially covering the edge of the insulative layer and being in contact with the exposed surface of the conductive feature.2. The semiconductor device of claim 1 , wherein the conductive feature is extended through the insulative layer along a direction parallel to a thickness of the semiconductor die.3. The semiconductor device of claim 2 , wherein the conductive feature includes a recessed portion claim 2 , the recessed portion is recessed from the exposed surface of the conductive feature and toward the semiconductor die.4. The semiconductor device of claim 3 , wherein the recessed portion includes an inner surface and the inner surface is isolated from the insulative layer.5. The semiconductor device of claim 3 , wherein the conductive feature further includes an extension portion connected to the recessed portion claim 3 , and the extension portion is extended further away from the exposed surface than the recessed portion.6. The semiconductor device of claim 3 , wherein the conductive feature ...

ELECTRONIC DEVICE PACKAGE AND METHOD FOR MANUFACTURING THE SAME

An electronic device package includes a redistribution layer and a conductive substrate. The RDL includes a first surface. The conductive substrate is disposed on the first surface and electrically connected to the RDL. A circuit density of the RDL is higher than a circuit density of the conductive substrate, and an edge of the RDL laterally protrudes out from a respective edge of the conductive substrate. 1. An electronic device package , comprising:a redistribution layer (RDL) including a first surface; anda conductive substrate disposed on the first surface and electrically connected to the RDL,wherein a circuit density of the RDL is higher than a circuit density of the conductive substrate, and an edge of the RDL laterally protrudes out from a respective edge of the conductive substrate.2. The electronic device package of claim 1 , wherein a line width/spacing (L/S) of the RDL is narrower than an L/S of the conductive substrate.3. The electronic device package of claim 1 , wherein the RDL comprises a fan-out RDL.4. The electronic device package of claim 1 , wherein an area of the RDL is larger than an area of the conductive substrate.5. The electronic device package of claim 1 , further comprising a plurality of first conductive structures disposed between and electrically connected to the RDL and the conductive substrate.6. The electronic device package of claim 1 , further comprising a first underfill disposed between the RDL and the conductive substrate and climbing up the edge of the conductive substrate.7. The electronic device package of claim 6 , wherein the first underfill partially climbs up the edge of the conductive substrate.8. The electronic device package of claim 6 , wherein the first underfill entirely climbs up the edge of the conductive substrate.9. The electronic device package of claim 1 , further comprising a first encapsulation layer disposed on the first surface of the RDL and encapsulating the conductive substrate.10. The electronic ...

Semiconductor Device With shield for Electromagnetic interference

A semiconductor device includes a first die embedded in a molding material, where contact pads of the first die are proximate a first side of the molding material. The semiconductor device further includes a redistribution structure over the first side of the molding material, a first metal coating along sidewalls of the first die and between the first die and the molding material, and a second metal coating along sidewalls of the molding material and on a second side of the molding material opposing the first side.

ELECTRONIC DEVICE PACKAGE AND METHOD FOR MANUFACTURING THE SAME

An electronic device package includes a substrate, a first semiconductor die, a second semiconductor die and an encapsulant. The substrate includes a first surface, and a second surface opposite to the first surface. The substrate defines a cavity recessed from the first surface. The first semiconductor die is disposed in the cavity. The second semiconductor die is disposed over and electrically connected to the first semiconductor die. The encapsulant is disposed in the cavity of the substrate. The encapsulant encapsulates a first sidewall of the first semiconductor die, and exposes a second sidewall of the first semiconductor die. 1. An electronic device package , comprising:a carrier including a first surface and a second surface opposite to the first surface, wherein the carrier defines a cavity recessed from the first surface;a first semiconductor die disposed in the cavity;a second semiconductor die disposed over and electrically connected to the first semiconductor die; anda first redistribution layer (RDL) disposed between the first surface of the carrier and the second semiconductor die, and electrically connected to the first semiconductor die and the second semiconductor die.2. The electronic device package of claim 1 , further comprising an encapsulant disposed in the cavity of the carrier claim 1 , wherein the encapsulant encapsulates a first sidewall of the first semiconductor die and exposes a second sidewall of the first semiconductor die.3. The electronic device package of claim 1 , further comprising a conductive through via extending from the first surface to the second surface of the carrier claim 1 , wherein the first RDL is electrically connected to the conductive through via.4. The electronic device package of claim 3 , further comprising a component disposed on and electrically connected to the first RDL.5. The electronic device package of claim 3 , wherein the first semiconductor die includes a photonic IC claim 3 , and the second ...

Gallium arsenide devices with copper backside for direct die solder attach

Systems, apparatuses, and methods related to the design, fabrication, and manufacture of gallium arsenide (GaAs) integrated circuits are disclosed. Copper can be used as the contact material for a GaAs integrated circuit. Metallization of the wafer and through-wafer vias can be achieved through copper plating processes disclosed herein. Direct die solder (DDS) attach can be achieved by use of electroless nickel plating of the copper contact layer followed by a palladium flash. GaAs integrated circuits can be singulated, packaged, and incorporated into various electronic devices.

IMAGE SENSOR CHIP-SCALE-PACKAGE

An image sensor chip-scale package includes a pixel array, a cover glass covering the pixel array, a dam, and an adhesive layer. The pixel array is embedded in a substrate top-surface of a semiconductor substrate. The semiconductor substrate includes a plurality of conductive pads in a peripheral region of the semiconductor substrate surrounding the pixel array. The dam at least partially surrounds the pixel array and is located (i) between the cover glass and the semiconductor substrate, and (ii) on a region of the substrate top-surface between the pixel array and the plurality of conductive pads. The adhesive layer is (i) located between the cover glass and the semiconductor substrate, (ii) at least partially surrounding the dam, and (iii) configured to adhere the cover glass to the semiconductor substrate. 1. An image sensor chip-scale package comprising:a pixel array embedded in a substrate top-surface of a semiconductor substrate, the semiconductor substrate including a plurality of conductive pads in a peripheral region of the semiconductor substrate surrounding the pixel array;a cover glass covering the pixel array;a dam at least partially surrounding the pixel array and located (i) between the cover glass and the semiconductor substrate, and (ii) on a region of the substrate top-surface between the pixel array and the plurality of conductive pads; andan adhesive layer (i) located between the cover glass and the semiconductor substrate, (ii) at least partially surrounding the dam, and (iii) configured to adhere the cover glass to the semiconductor substrate.2. The image sensor chip-scale package of claim 1 , having a package top-surface that (i) is located above each of the pixel array claim 1 , the dam claim 1 , and the adhesive layer claim 1 , (ii) includes at least part of a cover-glass top-surface of the cover glass claim 1 , and (iii) has a height claim 1 , relative to a bottom-surface of the cover glass opposite the cover-glass top-surface claim 1 , ...

SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR PACKAGE, METHOD OF MANUFACTURING THE SAME

A semiconductor substrate includes a first dielectric structure and a die. The first dielectric structure has a first surface and a second surface opposite to the first surface. The die is embedded within the first dielectric structure. The die includes an active surface facing the first surface of the first dielectric structure, a backside surface opposite to the active surface of the die and a metal layer disposed on the backside surface of the die. The metal layer is a recrystallized layer. 1. A semiconductor substrate , comprising:a first dielectric structure having a first surface and a second surface opposite to the first surface; anda die embedded within the first dielectric structure,wherein the die comprises an active surface facing the first surface of the first dielectric structure, a backside surface opposite to the active surface of the die and a metal layer disposed on the backside surface of the die, andwherein the metal layer is a recrystallized layer.2. The semiconductor substrate of claim 1 , further comprising a patterned conductive layer disposed on the first surface of the first dielectric structure and extending to the active surface of the die.3. The semiconductor substrate of claim 1 , wherein the metal layer is exposed from the second surface of the first dielectric structure.4. The semiconductor substrate of claim 3 , wherein the exposed surface of the metal layer is coplanar with the second surface of the first dielectric structure.5. The semiconductor substrate of claim 2 , further comprising an redistribution layer (RDL) structure disposed on the patterned conductive layer and the first surface of the first dielectric structure.6. The semiconductor substrate of claim 1 , further comprising a second dielectric structure attached to the second surface of the first dielectric structure.7. The semiconductor substrate of claim 1 , further comprising an redistribution layer (RDL) structure disposed on the second surface of the first dielectric ...

PACKAGE STRUCTURE WITH STRUCTURE REINFORCING ELEMENT AND MANUFACTURING METHOD THEREOF

A package structure includes a redistribution structure, a chip, one or more structural reinforcing elements, and a protective layer. The redistribution structure includes a first circuit layer and a second circuit layer disposed over the first circuit layer. The first circuit layer is electrically connected to the second circuit layer. The chip is disposed over the redistribution structure and electrically connected to the second circuit layer. The one or more structural reinforcing elements are disposed over the redistribution structure. The structural reinforcing element has a Young's modulus in a range of 30 to 200 GPa. The protective layer overlays the chip and a sidewall of the structural reinforcing element. 1. A package structure , comprising:a redistribution structure comprising a first circuit layer and a second circuit layer disposed over the first circuit layer, wherein the first circuit layer is electrically connected to the second circuit layer;a chip disposed over the redistribution structure and electrically connected to the second circuit layer; ["a reinforcing layer having a Young's modulus in a range of 30 to 200 GPa, wherein the reinforcing layer has a through hole; and", 'a conductive connector disposed in the through hole, wherein a top portion of the conductive connector and a bottom portion thereof are exposed outside the reinforcing layer, and the bottom portion of the conductive connector is electrically connected to the second circuit layer;, 'an inner conductive reinforcing element disposed over the redistribution structure, wherein the inner conductive reinforcing element comprisesa protective layer overlying the chip and a sidewall of the inner conductive reinforcing element; andan antenna pattern disposed over the protective layer and electrically connected to the top portion of the conductive connector.2. The package structure of claim 1 , wherein the inner conductive reinforcing element surrounds the chip.3. The package structure of ...

MULTI-CHIP PACKAGE STRUCTURES FORMED BY JOINING CHIPS TO PRE-POSITIONED CHIP INTERCONNECT BRIDGE DEVICES

Techniques are provided for constructing multi-chip package structures using pre-positioned interconnect bridge devices that are fabricated on a bridge wafer. For example, integrated circuit chips are mounted to a bridge wafer which is formed to have a plurality of pre-positioned interconnect bridge devices, wherein at least two integrated circuit chips are joined to each interconnect bridge device, and wherein each interconnect bridge device includes wiring to provide chip-to-chip connections between the integrated circuit chips connected to the interconnect bridge device. A wafer-level molding layer is formed on the bridge wafer to encapsulate the integrated circuit chips mounted to the bridge wafer. The interconnect bridge devices are released from the bridge wafer. The wafer-level molding layer is then diced to form a plurality of individual multi-chip modules. 1. A method for constructing a package structure , comprising:mounting a plurality of integrated circuit chips to a bridge wafer comprising a plurality of pre-positioned interconnect bridge devices, wherein at least two integrated circuit chips are joined to each interconnect bridge device, and wherein each interconnect bridge device comprises wiring to provide chip-to-chip connections between the integrated circuit chips connected to the interconnect bridge device;forming a wafer-level molding layer on the bridge wafer to encapsulate the plurality of integrated circuit chips mounted to the bridge wafer;releasing the interconnect bridge devices from the bridge wafer; anddicing the wafer-level molding layer to form a plurality of individual multi-chip modules.2. The method of claim 1 , wherein mounting the plurality of integrated circuit chips to the bridge wafer comprises flip-chip bonding the integrated circuit chips to the interconnect bridge devices using solder bumps formed on upper surfaces of the interconnect bridge devices.3. The method of claim 1 , wherein the bridge wafer comprises a ...

CHIP PACKAGE AND MANUFACTURING METHOD THEREOF

A chip package includes a chip, a laser stopper, an isolation layer, a redistribution layer, an insulating layer, and a conductive structure. The chip has a conductive pad, a first surface, and a second surface opposite to the first surface. The conductive pad is located on the first surface. The second surface has a first though hole to expose the conductive pad. The laser stopper is located on the conductive pad. The isolation layer is located on the second surface and in the first though hole. The isolation layer has a third surface opposite to the second surface. The isolation layer and the conductive pad have a second though hole together, such that the laser stopper is exposed through the second though hole. The redistribution layer is located on the third surface, the sidewall of the second though hole, and the laser stopper. 1. A chip package , comprising:a chip having a conductive pad, a first surface, and a second surface opposite to the first surface, wherein the conductive pad is located on the first surface, and the second surface has a first through hole to expose the conductive pad;a laser stopper located on the conductive pad;an isolation layer located on the second surface and in the first though hole, and having a third surface opposite to the second surface, wherein the isolation layer and the conductive pad have a second though hole together, such that the laser stopper is exposed through the second though hole;a redistribution layer located on the third surface, a sidewall of the second though hole, and the laser stopper that is in the second though hole;an insulating layer located on the third surface and the redistribution layer, and having an opening for exposing the redistribution layer; anda conductive structure located on the redistribution layer that is in the opening of the insulating layer, such that the conductive structure is electrically connected to the conductive pad.2. The chip package of claim 1 , wherein the laser stopper is ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device and a manufacturing method thereof, which can reduce a size of the semiconductor device. As a non-limiting example, various aspects of this disclosure provide for a reduction in package size based at least in part on patterning techniques for forming interconnection structures. 1. A method of manufacturing a semiconductor package , the method comprising:forming a dielectric layer on a semiconductor die, where the semiconductor die comprises a die pad;forming a conductive layer on the dielectric layer, wherein the conductive layer is electrically connected to the die pad through an opening in the dielectric layer;forming a first temporary structure on the conductive layer;forming a mold material to cover at least portions of the dielectric layer, the conductive layer and the first temporary structure;removing the first temporary structure from the mold material; andforming an interconnection structure in a cavity in the mold material created by said removing the first temporary structure.2. The method of claim 1 , wherein the first temporary structure comprises a photoresist material and/or a dry film material.3. The method of claim 1 , wherein:the first temporary structure comprises a top surface, a bottom surface coupled to the conductive layer, and a plurality of side surfaces; andat least one of the side surfaces of the interconnection structure is planar.4. The method of claim 3 , wherein each of the plurality of side surfaces of the first temporary structure is planar.5. The method of claim 1 , comprising thinning the mold material to expose the first temporary structure.6. The method of comprising:forming a second temporary structure on the semiconductor die for singulating the semiconductor package;removing the second temporary structure from the mold material; andsingulating the semiconductor package at a groove in the mold material created by said removing the second temporary structure.7. The method of claim 6 , wherein said removing ...

High-frequency circuit

A high-frequency circuit includes: a first substrate; a transmission line formed on the first substrate and having first and second output portions branched from an input portion; a second substrate; first and second pads formed on the second substrate; a first wire connecting the first output portion to the first pad; and a second wire connecting the second output portion to the second pad, wherein an electrical length from the input portion to an edge of the second output portion is longer than an electrical length from the input portion to an edge of the first output portion, and a length from a junction between the second wire and the second output portion to the edge of the second output portion is longer than a length from a junction between the first wire and the first output portion to the edge of the first output portion.

ELECTRONIC SYSTEM HAVING INCREASED COUPLING BY USING HORIZONTAL AND VERTICAL COMMUNICATION CHANNELS

An electronic system supports superior coupling by implementing a communication mechanism that provides at least for horizontal communication for example, on the basis of wired and/or wireless communication channels, in the system. Hence, by enhancing vertical and horizontal communication capabilities in the electronic system, a reduced overall size may be achieved, while nevertheless reducing complexity in printed circuit boards coupled to the electronic system. In this manner, overall manufacturing costs and reliability of complex electronic systems may be enhanced. 1. An apparatus , comprising:a first integrated circuit die singulated from a wafer and comprising a first semiconductor substrate and a first metallization structure mounted to the first semiconductor substrate, wherein the first metallization structure includes a first contact pad;a second integrated circuit die singulated from a wafer and comprising a second semiconductor substrate and a second metallization structure mounted to the second semiconductor substrate, wherein the second metallization structure includes a second contact pad;a first dielectric layer disposed in contact with the first metallization structure and a side surface of the first semiconductor substrate, said first dielectric layer including a first communication pad that is electrically connected to said first contact pad;a second dielectric layer disposed in contact with the second metallization structure and a side surface of the second semiconductor substrate, said second dielectric layer including a second communication pad that is electrically connected to said second contact pad;wherein the first dielectric layer is positioned in physical contact with the second dielectric layer, andwherein the first communication pad is positioned for direct mechanical and electrical connection with the second communication pad.2. The apparatus of claim 1 , wherein the first communication pad is disposed on a face of the first dielectric ...

Semiconductor device

Provided is a semiconductor device including: a first substrate having a first primary surface, a second primary surface, and a side surface; a semiconductor element formed on the first primary surface; a first electrode formed on the first primary surface and connected to the semiconductor element on the first primary surface; a second electrode formed on the second primary surface; a through-electrode formed so as to penetrate the first substrate and connecting the first electrode and the second electrode to each other; a second substrate bonded to the first substrate so as to face the first primary surface; and a third electrode formed on the side surface of the first substrate and connected to the second electrode.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device and a manufacturing method thereof, which can reduce a number of manufacturing processes and/or can reduce a thickness of the semiconductor device. As a non-limiting example, various aspects of this disclosure provide for the elimination process steps and/or a reduction in package size based on dielectric layer characteristics. 1. A semiconductor device comprising: a first die surface;', 'a second die surface opposite the first die surface; and', 'a third die surface extending between the first die surface and the second die surface;, 'a semiconductor die comprisinga die dielectric layer on the first die surface, the die dielectric layer comprising a first die dielectric layer surface facing away from the semiconductor die and a second die dielectric layer surface facing the semiconductor die; a first dielectric layer portion on the third die surface and having a uniform thickness; and', 'a second dielectric layer portion that extends outwardly from the first dielectric layer portion and comprises a first surface that is coplanar with the first die dielectric layer surface;, 'a first dielectric layer comprisingan encapsulant layer on the first dielectric layer; anda conductive layer on the first surface of the semiconductor die and on the second dielectric layer portion.2. The semiconductor device of claim 1 , wherein the first dielectric layer portion has a first thickness claim 1 , and the second dielectric layer portion has a second thickness that is the same as the first thickness.3. The semiconductor device of claim 1 , wherein the die dielectric layer comprises an inorganic dielectric layer.4. The semiconductor device of claim 3 , comprising a second dielectric layer that comprises an organic dielectric layer that directly contacts the inorganic dielectric layer of the die dielectric layer.5. The semiconductor device of claim 1 , wherein the die dielectric layer is directly on the first die surface.6. The semiconductor device of claim 1 ...

Semiconductor device and method of making a semiconductor device

A semiconductor device and a method of making the same. The device includes a semiconductor substrate having a major surface, one or more contacts located on the major surface and an encapsulant covering at least the major surface. A peripheral edge of each contact defines a contact area on the major surface. The device also includes one or more bond pads located outside the encapsulant. Each bond pad is electrically connected to a respective contact located on the major surface of the substrate by a respective metal filled via that passes through the encapsulant. A sidewall of each respective metal filled via, at the point at which it meets the respective contact, falls inside the contact area defined by the respective contact when viewed from above the major surface of the substrate, whereby none of the metal filling each respective via extends outside the contact area of each respective contact.

Ball Amount Process in the Manufacturing of Integrated Circuit

An integrated circuit structure includes a semiconductor substrate, a metal pad over the semiconductor substrate, a passivation layer including a portion over the metal pad, a polymer layer over the passivation layer, and a Post-Passivation Interconnect (PPI) over the polymer layer. The PPI is electrically connected to the metal pad. The PPI includes a PPI line have a first width, and a PPI pad having a second width greater than the first width. The PPI pad is connected to the PPI line. The PPI pad includes an inner portion having a first thickness, and an edge portion having a second thickness smaller than the first thickness.

Method of processing a substrate

In a method of processing a substrate in accordance with an embodiment, a trench may be formed in the substrate, imprint material may be deposited at least into the trench, the imprint material in the trench may be embossed using a stamp device, and the stamp device may be removed from the trench.

SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device package includes a substrate, a first semiconductor die, a conductive via, a first contact pad and a second contact pad. The substrate includes a first surface, and a second surface opposite to the first surface, the substrate defines a cavity through the substrate. The first semiconductor die is disposed in the cavity, wherein the first semiconductor die includes an active surface adjacent to the first surface, and an inactive surface. The conductive via penetrates through the substrate. The first contact pad is exposed from the active surface of the first semiconductor die and adjacent to the first surface of the substrate. The second contact pad is disposed on the first surface of the substrate, wherein the second contact pad is connected to a first end of the conductive via. 1. A semiconductor device package , comprising:a substrate including a first surface, and a second surface opposite to the first surface, the substrate defining a cavity through the substrate;a first semiconductor die disposed in the cavity, wherein the first semiconductor die includes an active surface adjacent to the first surface;a conductive via through the substrate;a first contact pad exposed from the active surface of the first semiconductor die and adjacent to the first surface of the substrate; anda second contact pad disposed on the first surface of the substrate, wherein the second contact pad is connected to a first end of the conductive via.2. The semiconductor device package of claim 1 , further comprising a first redistribution layer (RDL) disposed on the first surface of the substrate and electrically connected to the first contact pad and the second contact pad.3. The semiconductor device package of claim 1 , wherein the conductive via comprises an insulating structure through the substrate claim 1 , and a conductive structure between an edge of the substrate and a sidewall of the insulating structure and electrically connected to the second contact ...

ELECTRONIC DEVICE PACKAGE AND METHOD FOR MANUFACTURING THE SAME

An electronic device package includes a substrate, a first semiconductor die, a second semiconductor die and an encapsulant. The substrate includes a first surface, and a second surface opposite to the first surface. The substrate defines a cavity recessed from the first surface. The first semiconductor die is disposed in the cavity. The second semiconductor die is disposed over and electrically connected to the first semiconductor die. The encapsulant is disposed in the cavity of the substrate. The encapsulant encapsulates a first sidewall of the first semiconductor die, and exposes a second sidewall of the first semiconductor die. 1. An electronic device package , comprising:a substrate including a first surface, and a second surface opposite to the first surface, wherein the substrate defines a cavity recessed from the first surface;a first semiconductor die disposed in the cavity;a second semiconductor die disposed over and electrically connected to the first semiconductor die; andan encapsulant disposed in the cavity of the substrate, wherein the encapsulant encapsulates a first sidewall of the first semiconductor die, and exposes a second sidewall of the first semiconductor die.2. The electronic device package of claim 1 , wherein the first semiconductor die comprises a photonic IC claim 1 , and the second semiconductor die comprises an electronic IC.3. The electronic device package of claim 1 , wherein the encapsulant further partially encapsulates a first active surface of the first semiconductor die.4. The electronic device package of claim 3 , wherein an edge of the encapsulant is substantially coplanar with the second sidewall of the first semiconductor die.5. The electronic device package of claim 1 , wherein a first active surface of the first semiconductor die faces a second active surface of the second semiconductor die.6. The electronic device package of claim 1 , further comprising a first redistribution layer (RDL) disposed between the first ...

Vertically connected integrated circuits

In some examples, an integrated circuit (IC) includes a semiconductor substrate defining a perimeter of the integrated circuit and a castellation formed at the perimeter. The IC also may include a layer including an electrically conductive material formed on a surface of the castellation. In some examples, the layer including the electrically conductive material is not substantially parallel to adjacent portions of the perimeter of the IC. The integrated circuit may be used in a system, in which the metallized castellation may be used to electrically connect the IC to an external structure, such as another IC or a printed board.

Integrated Fan-Out Structure and Method of Forming

Semiconductor devices and methods of forming are provided. A molding compound extends along sidewalls of a first die and a second die. A redistribution layer is formed over the first die, the second die, and the molding compound. The redistribution layer includes a conductor overlying a gap between the first die and the second die. The conductor is routed at a first angle over an edge of the first die. The first angle is measured with respect to a straight line that extends along a shortest between the first die and the second die, and the first angle is greater than 0. 1. A method of forming a semiconductor device , the method comprising:forming a molding compound extending along sidewalls of a first die and a second die; andforming a redistribution layer over the first die, the second die, and the molding compound, the redistribution layer including a conductor overlying a gap between the first die and the second die, the conductor being routed at a first angle over an edge of the first die, the first angle being measured with respect to a shortest line between the first die and the second die, and the first angle being greater than 0.2. The method of claim 1 , wherein the first die comprises a first dielectric layer on a top surface of a first substrate claim 1 , and the second die comprises a second dielectric layer on a top surface of a second substrate claim 1 , wherein an edge of the first dielectric layer is offset from an edge of the first substrate claim 1 , and an edge of the second dielectric layer is offset from an edge of the second substrate.3. The method of claim 2 , wherein the conductor comprises a first turning point over the first dielectric layer claim 2 , the first turning point located where the conductor is first routed to the first angle.4. The method of claim 2 , wherein the conductor comprises a second turning point over the second dielectric layer claim 2 , the second turning point located where the conductor is first routed differently ...

Chip Packages and Methods of Manufacture Thereof

A chip package may include a die and a redistribution structure over the die. The redistribution structure may include a die, a redistribution structure over the die, and an under-bump metallurgy (UBM) structure over the redistribution structure. The UBM structure may include a central portion, a peripheral portion physically separated from and surrounding a perimeter of the central portion, and a bridging portion having a first end and a second end opposite the first end. The first end of the bridging portion may be coupled to the central portion of the UBM structure, while the second end of the bridging portion may be coupled to the peripheral portion of the UBM structure. 1. A chip package , comprising:a die;a redistribution structure over the die; andan under-bump metallurgy (UBM) structure over the redistribution structure, the UBM structure comprising a central portion, a peripheral portion physically separated from and surrounding a perimeter of the central portion, and a bridging portion having a first end and a second end opposite the first end, the first end of the bridging portion coupled to the central portion of the UBM structure, the second end of the bridging portion coupled to the peripheral portion of the UBM structure, the second end having a greater width than the first end.2. The chip package of claim 1 , further comprising a polymer layer encapsulating the peripheral portion of the UBM structure claim 1 , wherein a sidewall of the polymer layer is separated from a sidewall of the central portion of the UBM structure.3. The chip package of claim 2 , where the sidewall of the polymer layer and the sidewall of the central portion of the UBM structure are separated by a distance in a range from about 2 micrometers to about 50 micrometers.4. The chip package of claim 2 , wherein an air gap is disposed between the sidewall of the polymer layer and the sidewall of the central portion of the UBM structure.5. The chip package of claim 1 , further ...

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

A package structure includes a redistribution structure, a chip, one or more structural reinforcing elements, and a protective layer. The redistribution structure includes a first circuit layer and a second circuit layer disposed over the first circuit layer. The first circuit layer is electrically connected to the second circuit layer. The chip is disposed over the redistribution structure and electrically connected to the second circuit layer. The one or more structural reinforcing elements are disposed over the redistribution structure. The structural reinforcing element has a Young's modulus in a range of of 30 to 200 GPa. The protective layer overlays the chip and a sidewall of the structural reinforcing element. 1. A package structure , comprising:a redistribution structure comprising a first circuit layer and a second circuit layer disposed over the first circuit layer, wherein the first circuit layer is electrically connected to the second circuit layer;a chip disposed over the redistribution structure and electrically connected to the second circuit layer;one or more structural reinforcing elements disposed over the redistribution structure, wherein the structural reinforcing element has a Young's modulus of 30 to 200 GPa; anda protective layer overlying the chip and a sidewall of the structural reinforcing element.2. The package structure of claim 1 , wherein the package structure comprises one structural reinforcing element claim 1 , and the structural reinforcing element surrounds the chip.3. The package structure of claim 1 , wherein the package structure comprises a plurality of structural reinforcing elements claim 1 , and one of the structural reinforcing elements is disposed at a first side of the chip claim 1 , and another of the structural reinforcing elements is disposed at a second side of the chip claim 1 , and the second side is opposite or adjacent to the first side.4. The package structure of claim 1 , wherein the structural reinforcing ...

CHIP PACKAGE AND MANUFACTURING METHOD THEREOF

A chip package includes a chip structure, a molding material, a conductive layer, a redistribution layer, and a passivation layer. The chip structure has a front surface, a rear surface, a sidewall, a sensing area, and a conductive pad. The molding material covers the rear surface and the sidewall. The conductive layer extends form the conductive pad to the molding material located on the sidewall. The redistribution layer extends form the molding material that is located on the rear surface to the molding material that is located on the sidewall. The redistribution layer is in electrical contact with an end of the conductive layer facing away from the conductive pad. The passivation layer is located on the molding material and the redistribution layer. The passivation layer has an opening, and a portion of the redistribution layer is located in the opening. 1. A chip package , comprising:a chip structure having a front surface, a rear surface opposite the front surface, a sidewall adjacent to the front surface and the rear surface, and a sensing area and a conductive pad that are on the front surface;a molding material covering the rear surface and the sidewall of the chip structure;a conductive layer extending from the conductive pad to the molding material that is on the sidewall of the chip structure;a redistribution layer extending from the molding material that is on the rear surface of the chip structure to the molding material that is on the sidewall of the chip structure, wherein the redistribution layer is in electrical contact with an end of the conductive layer facing away from the conductive pad; anda passivation layer on the molding material and the redistribution layer, the passivation layer having an opening, wherein a portion of the redistribution layer is located in the opening.2. The chip package of claim 1 , wherein the molding material surrounds the sidewall of the chip structure claim 1 , and is in contact with the rear surface and the sidewall ...