Chip package

An embodiment of the invention provides a chip package which includes a substrate having an upper surface and a lower surface. A recess is adjacent to a sidewall of the substrate, wherein the recess is formed along a direction from the upper surface toward the lower surface of the substrate. A device region or sensing region of biological features is located on the upper surface of the substrate. A conducting pad is located on the upper surface of the substrate. A conducting layer is electrically connected to the conducting pad and extends to the recess along the sidewall of the substrate.