Interconnection [...] structure and method

Semiconductor structure and methods of forming semiconductor constructions

METHOD OF ELECTROPLATING PHOTORESIST DEFINED FEATURES FROM COPPER ELECTROPLATING BATHS CONTAINING REACTION PRODUCTS OF ALPHA AMINO ACIDS AND BISEPOXDES

Semiconductor device and process for manufacturing the same

A semiconductor device has a pad structure with a ring-shaped stress buffer layer between a metal pad and an under-bump metallization (UBM) layer. The stress buffer layer is formed of a dielectric layer with a dielectric constant less than 3.5, a polymer layer, or an aluminum layer. The stress buffer layer is a circular ring, a square ring, an octagonal ring, or any other geometric ring.

METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE

A method of manufacturing a semiconductor structure include: providing a die including a die pad disposed over the die; disposing a conductive member over the die pad of the die; forming a molding surrounding the die and the conductive member; disposing a dielectric layer over the molding, the die and the conductive member; and forming an interconnect structure including a land portion and a plurality of via portions. The land portion is disposed over the dielectric layer, the plurality of via portions are disposed over the conductive member and protruded from the land portion to the conductive member through the dielectric layer, and each of the plurality of via portions at least partially contacts with the conductive member.

Semiconductor package and fabrication method thereof

A semiconductor package is provided, which includes: a first semiconductor device having a first top surface and a first bottom surface opposite to the first top surface; a plurality of conductive balls formed on the first top surface of the first semiconductor device; a second semiconductor device having a second top surface and a second bottom surface opposite to the second top surface; and a plurality of conductive posts formed on the second bottom surface of the second semiconductor device and correspondingly bonded to the conductive balls for electrically connecting the first semiconductor device and the second semiconductor device, wherein the conductive posts have a height less than 300 um. Therefore, the present invention can easily control the height of the semiconductor package and is applicable to semiconductor packages having fine-pitch conductive balls.

DIE STRUCTURE, DIE STACK STRUCTURE AND METHOD OF FABRICATING THE SAME

Provided is a die structure including a die, a bonding structure, and a protection structure. The die includes a substrate and a metal feature disposed over the substrate. The bonding structure is disposed over the die. The bonding structure includes a bonding dielectric layer and a bonding metal layer disposed in the bonding dielectric layer. The bonding metal layer is electrically connected to the metal feature of the die. The protection structure is disposed between a top portion of the bonding metal layer and a top portion of the bonding dielectric layer. A die stack structure and a method of fabricating the die structure are also provided. 1. A die structure , comprising:a die;a bonding structure disposed over the die, the bonding structure comprising a bonding dielectric layer and a bonding metal layer disposed in the bonding dielectric layer, wherein the bonding metal layer is electrically connected to a metal feature of the die; anda protection structure disposed between a top portion of the bonding metal layer and a top portion of the bonding dielectric layer, wherein a material of the protection structure comprises an insulating material.2. The die structure of claim 1 , wherein a top surface of the protection structure claim 1 , a top surface of the bonding metal layer claim 1 , and a top surface of the bonding dielectric layer are substantially coplanar.3. The die structure of claim 1 , wherein the protection structure has a tapered sidewall claim 1 , a horizontal cross-sectional area of the protection structure gradually decreases in a direction from a top of the protection structure to a bottom of the protection structure.4. The die structure of claim 1 , wherein sidewalls of the protection structure are straight or curved.5. The die structure of claim 1 , wherein the top portion of the bonding metal layer has a tapered sidewall claim 1 , a horizontal cross-sectional area of the top portion of the bonding metal layer gradually decreases in a direction ...

Silicon photonic interposer with two metal redistribution layers

A ROUTING LAYER FOR MITIGATING STRESS IN A SEMICONDUCTOR DIE

Semiconductor device

Disclosed is a semiconductor device including a conductive pattern on a substrate, a passivation layer on the substrate and including an opening that partially exposes the conductive pattern, and a pad structure in the opening of the passivation layer and connected to the conductive pattern. The pad structure includes a first metal layer that fills the opening of the passivation layer and has a width greater than that of the opening, and a second metal layer on the first metal layer. The first metal layer has a first thickness at an outer wall of the first metal layer, a second thickness on a top surface of the passivation layer, and a third thickness on a top surface of the conductive pattern. The second thickness is greater than the first thickness, and the third thickness is greater than the second thickness.

Mechanically anchored backside C4 pad

The present invention relates generally to flip chip technology and more particularly, to a method and structure for fabricating a mechanically anchored controlled collapse chip connection (C4) pad on a semiconductor structure. In an embodiment, a method is disclosed that may include forming a bonding pad having one or more anchor regions that extend into a semiconductor structure and may inhibit the bonding pad from physically separating from the TSV during temperature fluctuations.

CONTACT STRUCTURES WITH POROUS NETWORKS FOR SOLDER CONNECTIONS, AND METHODS OF FABRICATING SAME

A contact pad includes a solder-wettable porous network () which wicks the molten solder () and thus restricts the lateral spread of the solder, thus preventing solder bridging between adjacent contact pads. 1. An assembly comprising:a first contact pad of a first microelectronic component, the first contact pad comprising a porous network; anda second contact pad of a second microelectronic device, the second contact pad bonded to the first contact pad via a solder at least partly disposed in pores of the porous network.2. The assembly of claim 1 , wherein the porous network comprises gold or a gold alloy.3. The assembly of claim 1 , wherein the first contact pad comprises an open-pore sponge with 70-80% porosity.4. The assembly of claim 1 , wherein the porous network comprises pore sizes from 15 nm to 360 nm.5. The assembly of claim 1 , further comprising a film deposited on pores of the porous network claim 1 , the film comprising titanium claim 1 , nickel claim 1 , or copper in a thickness of 2-5 nm.6. The assembly of claim 1 , wherein both the first contact pad and the second contact pad comprise porous networks.7. The assembly of claim 6 , wherein the solder penetrates at least 15 nm into each of the first contact pad and the second contact pad.8. The assembly of claim 1 , wherein the solder has been diffusion bonded to the porous network via thermocompression bonding.9. The assembly of claim 8 , wherein the solder that has been diffusion bonded to the porous network of the first contact pad contains indium and has a melting temperature below 180° C.10. A contact pad resistant to solder-bridges between adjacent contact pads claim 8 , for making a microelectronic component with contact pads at fine pitch claim 8 , comprising:a gold alloy at a bonding interface of the microelectronic component; anda wicking layer of the gold alloy comprising a porous network, the wicking layer comprising pores with diameters between 15-360 nm to absorb a solder at least 15 nm ...

Routing layer for mitigating stress in a semiconductor die

A routing layer for a semiconductor die is disclosed. The routing layer includes traces interconnecting integrated circuit bond-pads to UBMs. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces arranged underneath the UBMs as to absorb stress from solder bumps attached to the UMBs. Traces beneath the UBMs protect parts of the underlying dielectric material proximate the solder bumps, from the stress.

Pad structure, circuit carrier and integrated circuit chip

A pad structure is suitable for a circuit carrier or an integrated circuit chip. The pad structure includes an inner pad, a conductive via and an outer pad. The conductive via connects the inner pad. The outer pad connects the conductive via and further connects a conductive ball or a conductive bump. The outer diameter of the outer pad is greater than the outer diameter of the inner pad.

Compliant interconnects in wafers

A microelectronic assembly includes a substrate and an electrically conductive element. The substrate can have a CTE less than 10 ppm/° C., a major surface having a recess not extending through the substrate, and a material having a modulus of elasticity less than 10 GPa disposed within the recess. The electrically conductive element can include a joining portion overlying the recess and extending from an anchor portion supported by the substrate. The joining portion can be at least partially exposed at the major surface for connection to a component external to the microelectronic unit.

SEMICONDUCTOR DEVICE AND WAFER LEVEL PACKAGE INCLUDING SUCH SEMICONDUCTOR DEVICE

An RDL structure on a passivation layer includes a first landing pad disposed directly above a first on-chip metal pad; a first via in a passivation layer to electrically connecting the first landing pad with the first on-chip metal pad; a second landing pad disposed directly above the second on-chip metal pad; a second via in the passivation layer to electrically connecting the second landing pad with the second on-chip metal pad; and at least five traces being disposed on the passivation layer and passing through a space between the first landing pad and the second landing pad.

Barrierestrukturen zwischen externen elektrischen Anschlussteilen

Eine Struktur umfasst ein Die-Substrat; eine Passivierungsschicht auf dem Die-Substrat; eine erste und eine zweite Verbindungsstruktur auf der Passivierungsschicht; und eine Barriere auf der Passivierungsschicht, mindestens der ersten oder der zweiten Verbindungsstruktur oder einer Kombination daraus. Die erste und die zweite Verbindungsstruktur umfassen einen ersten und einen zweiten Via-Abschnitt durch die Passivierungsschicht zu einem ersten bzw. einem zweiten leitenden Merkmal des Die-Substrats. Die erste und die zweite Verbindungsstruktur umfassen weiter ein erstes bzw. ein zweites Pad und ein erstes bzw. ein zweites Übergangselement auf einer Oberfläche der Passivierungsschicht zwischen dem ersten und dem zweiten Via-Abschnitt und dem ersten und dem zweiten Pad. Die Barriere ist zwischen dem ersten Pad und dem zweiten Pad angeordnet. Die Barriere umgibt mindestens das erste Pad oder das zweiten Pad nicht vollständig.

SEMICONDUCTOR DEVICE

This semiconductor device has a laminated chip resulting from joining a first semiconductor chip (100) and a second semiconductor chip (200). On the primary surface of the first semiconductor chip are formed a first electrode pad (110) and a first bump (120) formed on the first electrode pad. On the primary surface of the second semiconductor chip (200) is formed a second bump (220) for joining to the first bump. The first electrode pad (110) has an aperture such that the central portion has a stepped shape. The first bump (120) has a concavity of which the central portion is depressed formed in a manner so as to straddle the stepped shape of the aperture and peripheral section of the first electrode pad (110).

Mutli-chip package with encapsulated conductor via

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a first semiconductor die, at least one first conductive connector disposed beside the first semiconductor die and electrically coupled to the first semiconductor die, an insulating encapsulation laterally encapsulating the first semiconductor die and the at least one first conductive connector, and a redistribution structure disposed on the insulating encapsulation and being in contact with the first semiconductor die and the at least one first conductive connector. A thickness of the at least one first conductive connector is less than a thickness of the insulating encapsulation.

METHOD OF ELECTROPLATING PHOTORESIST DEFINED FEATURES FROM COPPER ELECTROPLATING BATHS CONTAINING REACTION PRODUCTS OF PYRIDYL ALKYLAMINES AND BISEPOXIDES

Electroplating methods enable the plating of photoresist defined features which have substantially uniform morphology. The electroplating methods include copper electroplating baths with reaction products of pyridyl alkylamines and bisepoxides to electroplate the photoresist defined features. Such features include pillars, bond pads and line space features. 1. A method for electroplating photoresist defined features comprising:a) providing a substrate comprising a layer of photoresist, wherein the layer of photoresist comprises a plurality of apertures;b) providing a copper electroplating bath comprising one or more reaction products of one or more pyridyl alkylamines and one or more bisepoxides; an electrolyte; one or more accelerators; and one or more suppressors;c) immersing the substrate comprising the layer of photoresist with the plurality of apertures in the copper electroplating bath; andd) electroplating a plurality of copper photoresist defined features in the plurality of apertures, the plurality of photoresist defined features comprise an average % TIR of −5% to +12%.2. The method of claim 1 , wherein a % WID of the plurality of photoresist defined features is from 5% to 14%.6. The method of claim 1 , wherein the one or more reaction products are in amounts of 0.25 ppm to 20 ppm in the copper electroplating bath.7. The method of claim 1 , wherein the one or more photoresist defined features is chosen from a pillar claim 1 , bond pad and line space feature.8. The method of claim 1 , wherein a current density is from 0.25 ASD to 40 ASD.9. An array of photoresist defined features on a substrate comprising an average % TIR of −5% to +12% and a % WID of 5% to 14%. The present invention is directed to a method of electroplating photoresist defined features from copper electroplating baths which include reaction products of pyridyl alkylamines and bisepoxides. More specifically, the present invention is directed to a method of electroplating photoresist defined ...

Routing layer for mitigating stress in a semiconductor die

A routing layer for a semiconductor die is disclosed. The routing layer includes traces interconnecting integrated circuit bond-pads to UBMs. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces arranged underneath the UBMs as to absorb stress from solder bumps attached to the UMBs. Traces beneath the UBMs protect parts of the underlying dielectric material proximate the solder bumps, from the stress.

Semiconductor device for use in flip-chip bonding, which reduces lateral displacement

A semiconductor device includes multilayer chips in which a first semiconductor chip and a second semiconductor chip are bonded together. A first electrode pad is formed on a principal surface of the first semiconductor chip, and a first bump is formed on the first electrode pad. A second bump is formed on the principal surface of the second semiconductor chip such that the second bump is bonded to the first bump. The first electrode pad has an opening, and the opening and an entire peripheral portion of the opening form a stepped shape form a stepped shape. The first bump has a recessed shape that is recessed at a center thereof and covers the stepped shape.

SEMICONDUCTOR PACKAGE

Disclosed is a semiconductor package including a package substrate, a semiconductor chip mounted on the package substrate, a connection solder pattern between the package substrate and the semiconductor chip, and a dummy bump between the package substrate and the semiconductor chip and spaced apart from the connection solder pattern. The connection solder pattern includes a first intermetallic compound layer, a connection solder layer, and a second intermetallic compound layer. The dummy bump includes a dummy pillar and a dummy solder pattern. A thickness of the dummy solder pattern is less than a thickness of the connection solder pattern. A melting point of the dummy solder pattern is greater than that of the connection solder layer.

Interconnection structure

Interconnection structure

A routing layer for mitigating stress in a semiconductor die

A routing layer for a semiconductor die is disclosed. The routing layer includes traces interconnecting integrated circuit bond-pads to UBMs. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces arranged underneath the UBMs as to absorb stress from solder bumps attached to the UMBs. Traces beneath the UBMs protect parts of the underlying dielectric material proximate the solder bumps, from the stress.

Semiconductor device and method of manufacturing the same

Semiconductor device package and device for semiconductor packaging

METAL PAD MODIFICATION

The present invention provides a structure. In an exemplary embodiment, the structure includes a base material, at least one metal pad, where a first surface of the metal pad is in contact with the base material, and a metal pedestal, where the metal pedestal is in contact with the metal pad, where a radial alignment of the metal pad is shifted by an offset distance, with respect to the metal pedestal, such that the metal pad is shifted towards a center axis of the base material, where a first dimension of the metal pad is smaller than a second dimension of the metal pad, where the second dimension is orthogonal to a line running from a center of the metal pad to the center axis of the base material, where the first dimension is parallel to the line.

반도체 장치

... 반도체 장치가 제공된다. 반도체 장치는 기판, 기판 상에 배치되는 보호막으로, 보호막을 관통하는 트렌치를 포함하는 보호막, 트렌치의 적어도 일부를 채우는 제1 부분과, 보호막 상에 배치되는 제2 부분을 포함하는 하부 범프 및 하부 범프 상에 배치되는 상부 범프를 포함하고, 보호막은, 트렌치의 측벽을 포함하는 제1 부분 및 제2 부분을 포함하고, 기판의 상면으로부터 상기 보호막의 제1 부분의 상면까지의 제1 높이는, 기판의 상면으로부터 상기 보호막의 제2 부분의 상면까지의 제2 높이보다 크다.

Method of electroplating photoresist defined features from copper electroplating baths containing reaction products of pyridyl alkylamines and bisepoxides

Electroplating methods enable the plating of photoresist defined features which have substantially uniform morphology. The electroplating methods include copper electroplating baths with reaction products of pyridyl alkylamines and bisepoxides to electroplate the photoresist defined features. Such features include pillars, bond pads and line space features.

SEMICONDUCTOR DEVICE

To provide a semiconductor device with a wafer level package structure that allows for probing while reducing the area occupied by the pad electrodes. 1. A semiconductor device comprising:a semiconductor chip having a plurality of first pad electrodes and a plurality of second pad electrodes; anda wiring structure provided on the semiconductor chip, wherein the wiring structure includes a plurality of external terminals, a plurality of wiring patterns that electrically connect the plurality of external terminals and the plurality of first pad electrodes, and bridge wiring that is not electrically connected to any of the plurality of external terminals within the wiring structure, but that electrically connects the plurality of second pad electrodes in a shared fashion.2. The semiconductor device according to claim 1 , wherein the same power supply voltage appears in the plurality of second pad electrodes.3. The semiconductor device according to claim 2 , wherein the semiconductor chip further includes an internal voltage generation circuit that receives an external power supply voltage supplied via the plurality of first pad electrodes and generates an internal power supply voltage claim 2 , and the internal power supply voltage appears on the plurality of second pad electrodes.4. The semiconductor device according to claim 2 , wherein the same voltage as the external power supply voltage supplied via the plurality of first pad electrodes appears on the plurality of second pad electrodes.5. The semiconductor device according to claim 1 , wherein the area of the plurality of first pad electrodes is greater than the area of the plurality of second pad electrodes.6. The semiconductor device according to claim 1 , wherein the semiconductor chip further includes a plurality of first bump electrodes formed on the plurality of first pad electrodes claim 1 , and a plurality of second bump electrodes formed on the plurality of second pad electrodes claim 1 , the wiring ...

Two-component bump metallization

A technique relates to a structure. An under-bump-metallization (UBM) structure includes a first region and a second region. The first and second regions are laterally positioned in the UBM structure. The first region includes a superconducting material. A substrate opposes the UBM structure. A superconducting solder material joins the first region to the substrate and the second region to the substrate.

Tiled-stress-alleviating pad structure

Structure and method for reducing thermal-mechanical stresses generated for a semiconductor device are provided, which includes a tiled-stress-alleviating pad structure.

Contact Pad for Semiconductor Device

A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound. 1. A device comprising:a substrate;contact pads over the substrate; anddummy pad features over the substrate, each of the dummy pad features being adjacent to a corresponding one of the contact pads, each of the dummy pad features being electrically disconnected from the corresponding one of the contact pads, wherein no other conductive material is interposed directly between each of the dummy pad features and the corresponding one of the contact pads.2. The device of claim 1 , wherein the substrate comprises a semiconductor die and molding compound along sidewalls of the semiconductor die.3. The device of claim 2 , wherein at least one of the dummy pad features is adjacent an interface between the sidewalls of the semiconductor die and the molding compound in a plan view.4. The device of claim 1 , further comprising:a protective layer over the dummy pad features; anda plurality of under bump metallization features, wherein each of the plurality of under bump metallization features extends through the protective layer to one of the contact pads.5. The device of claim 4 , wherein the protective layer extends along sidewalls of the dummy pad features and the contact pads.6. The device of claim 1 , wherein a first set of the contact pads are free of the dummy pad ...

Metal pad modification

The present invention provides a structure. In an exemplary embodiment, the structure includes a base material, at least one metal pad, where a first surface of the metal pad is in contact with the base material, and a metal pedestal, where the metal pedestal is in contact with the metal pad, where a radial alignment of the metal pad is shifted by an offset distance, with respect to the metal pedestal, such that the metal pad is shifted towards a center axis of the base material, where a first dimension of the metal pad is smaller than a second dimension of the metal pad, where the second dimension is orthogonal to a line running from a center of the metal pad to the center axis of the base material, where the first dimension is parallel to the line.

Device package and methods of forming the same

A device package includes a die, fan-out redistribution layers (RDLs) over the die, and an under bump metallurgy (UBM) over the fan-out RDLs. The UBM comprises a conductive pad portion and a trench encircling the conductive pad portion. The device package further includes a connector disposed on the conductive pad portion of the UBM. The fan-out RDLs electrically connect the connector and the UBM to the die.

Rigid wave pattern design on chip carrier substrate and printed circuit board for semiconductor and electronic sub-system packaging

A rigid wave pattern formed on a first side of a substrate in a semiconductor die package. The rigid wave pattern aligns with and overlies the contact fingers formed on the second side of the substrate. When the substrate and dice are encased during the molding process, the rigid wave pattern effectively reduces deformation of and stresses on the dice, therefore substantially alleviating die cracking.

Bump on pad (BOP) bonding structure

The embodiments described above provide enlarged overlapping surface areas of bonding structures between a package and a bonding substrate. By using elongated bonding structures on either the package and/or the bonding substrate and by orienting such bonding structures, the bonding structures are designed to withstand bonding stress caused by thermal cycling to reduce cold joints.

Semiconductor package structure

Semiconductor package structure is provided. A semiconductor package structure includes a chip, a molding material surrounding the chip, a through-via extending from a first surface to a second surface of the molding material, a first re-distribution layer (RDL) wire disposed on the second surface of the molding material and coupled to the through-via, and a second RDL wire disposed on the second surface of the molding material and parallel to the first RDL wire. The second surface is opposite to the first surface. A portion of the second RDL wire across the through-via has a first segment with a first width and a second segment with a second width different from the first width.

Semiconductor devices

COMPLIANT INTERCONNECTS IN WAFERS

A microelectronic unit 12 includes a substrate 20 and an electrically conductive element 40. The substrate 20 can have a CTE less than 10 ppm/°C, a major surface 21 having a recess 30 not extending through the substrate, and a material 50 having a modulus of elasticity less than 10 GPa disposed within the recess. The electrically conductive element 40 can include a joining portion 42 overlying the recess 30 and extending from an anchor portion 41 supported by the substrate 20. The joining portion 42 can be at least partially exposed at the major surface 21 for connection to a component 14 external to the microelectronic unit 12.

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

A semiconductor package and a method of making a semiconductor package. As non-limiting examples, various aspects of this disclosure provide various semiconductor packages, and methods of making thereof, that comprise a conductive layer that comprises an anchor portion extending through at least one dielectric layer.

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE

A semiconductor device includes a first gate electrode, a plurality of first source electrodes, a second gate electrode, and a plurality of second source electrodes. The first gate electrode is arranged with no other electrode between the first gate electrode and a first short side of the semiconductor substrate. The plurality of first source electrodes include a plurality of approximately rectangular first source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate. The second gate electrode is arranged with no other electrode between the second gate electrode and a second short side of the semiconductor substrate. The plurality of second source electrodes include a plurality of approximately rectangular second source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate.

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure includes a die including a die pad disposed over the die; a conductive member disposed over and electrically connected with the die pad; a molding surrounding the die and the conductive member; and a redistribution layer (RDL) disposed over the molding, the conductive member and the die, and including a dielectric layer and an interconnect structure, wherein the interconnect structure includes a land portion and a plurality of via portions, the land portion is disposed over the dielectric layer, the plurality of via portions are protruded from the land portion to the conductive member through the dielectric layer, and each of the plurality of via portions at least partially contacts with the conductive member.

SEMICONDUCTOR DEVICE

Disclosed is a semiconductor device including a conductive pattern on a substrate, a passivation layer on the substrate and including an opening that partially exposes the conductive pattern, and a pad structure in the opening of the passivation layer and connected to the conductive pattern. The pad structure includes a first metal layer that fills the opening of the passivation layer and has a width greater than that of the opening, and a second metal layer on the first metal layer. The first metal layer has a first thickness at an outer wall of the first metal layer, a second thickness on a top surface of the passivation layer, and a third thickness on a top surface of the conductive pattern. The second thickness is greater than the first thickness, and the third thickness is greater than the second thickness. 1. A method of manufacturing a semiconductor device , comprising:forming a conductive pattern on a substrate;forming a passivation layer on the substrate, the passivation layer including a first opening that partially exposes the conductive pattern;depositing a metal seed layer on a surface of the passivation layer;forming a mask pattern having a second opening partially exposes the metal seed layer, the second opening having a second width greater than a first width of the first opening;performing a first electroplating process to form a first metal layer in the first opening of the passivation layer and in a lower portion of the second opening of the mask pattern;performing a second electroplating process to form a second metal layer on the first metal layer in an upper portion of the second opening of the mask pattern;{'b': '1', 'after removing the mask pattern, patterning the metal seed layer to form a metal seed pattern, p wherein the first electroplating process is performed by using a plating solution comprising an electrolyte solution, an accelerator, and a suppressor, and'}wherein a plating rate on a central region of the second opening is different ...

Rigid wave pattern design on chip carrier substrate and printed circuit board for semiconductor and electronic sub-system packaging

A rigid wave pattern formed on a first side of a substrate in a semiconductor die package. The rigid wave pattern aligns with and overlies the contact fingers formed on the second side of the substrate. The rigid wave pattern includes a first pattern with an etched portion and an unetched portion around the etched portion. When the substrate and dice are encased during the molding process, the rigid wave pattern effectively reduces deformation of and stresses on the dice, therefore substantially alleviating die cracking.

Interconnection Structure

An electrical interconnect for connecting an IC chip to a PCB, the electrical interconnect comprising a first polymer layer 5 defining a first surface; a connection element 9 being attached to the first surface such that it protrudes from the first polymer layer 5, a connection pad 4 separated from the connection element 9 by the first polymer layer 5; and a collection of discrete conductive connections 8 through the first polymer layer 5 such that the connection element 9 and connection pad 4 are coupled together; at least a part of each discrete conductive connection 8 contacts the connection element 9 directly underneath the connection element 9. The connection element 9 is preferably provided as a solder ball 6 with a metal contact 7. The present invention is designed to improve the amount of thermal and/or mechanical stress that each solder element connection can take before failing.

Semiconductor device

PAD STRUCTURE, CIRCUIT CARRIER AND INTEGRATED CIRCUIT CHIP

A pad structure is suitable for a circuit carrier or an integrated circuit chip. The pad structure includes an inner pad, a conductive via and an outer pad. The conductive via connects the inner pad. The outer pad connects the conductive via and further connects a conductive ball or a conductive bump. The outer diameter of the outer pad is greater than the outer diameter of the inner pad.

Contact structures with porous networks for solder connections, and methods of fabricating same

A contact pad includes a solder-wettable porous network (310) which wicks the molten solder (130) and thus restricts the lateral spread of the solder, thus preventing solder bridging between adjacent contact pads.

Anschlussstruktur mit reduzierter Spannung für integrierte Schaltungen

Vorrichtung, insbesondere Anschlussstruktur, umfassend: ein Substrat; ein Metall-Pad über dem Substrat; eine Passivierungsschicht, die Kantenabschnitte des Metall-Pads bedeckt, wobei die Passivierungsschicht eine erste Öffnung aufweist, die das Metall-Pad überlappt, und wobei die erste Öffnung eine erste seitliche Abmessung aufweist, die in einer zu einer Hauptfläche des Substrats parallelen Richtung gemessen ist; eine Polymerschicht über der Passivierungsschicht, die die Kantenabschnitte des Metall-Pads bedeckt, wobei die Polymerschicht eine zweite Öffnung aufweist, die das Metall-Pad überlappt, wobei die zweite Öffnung eine zweite seitliche Abmessung aufweist, die in der Richtung gemessen ist, und wobei die erste seitliche Abmessung um mehr als ca. 7 m größer als die zweite seitliche Abmessung ist; und eine Under-Bump-Metallurgie (Under-Bump metallurgy (UBM)), die einen ersten Abschnitt in der zweiten Öffnung und einen zweiten Abschnitt aufweist, der über Abschnitten der Polymerschicht ...

Pad structure, circuit carrier and integrated circuit chip

SEMICONDUCTOR DEVICE

Disclosed is a semiconductor device including a conductive pattern on a substrate, a passivation layer on the substrate and including an opening that partially exposes the conductive pattern, and a pad structure in the opening of the passivation layer and connected to the conductive pattern. The pad structure includes a first metal layer that fills the opening of the passivation layer and has a width greater than that of the opening, and a second metal layer on the first metal layer. The first metal layer has a first thickness at an outer wall of the first metal layer, a second thickness on a top surface of the passivation layer, and a third thickness on a top surface of the conductive pattern. The second thickness is greater than the first thickness, and the third thickness is greater than the second thickness.

Bonding pads with thermal pathways

Apparatuses and methods for providing thermal pathways from a substrate to a thermal bonding pad. The thermal pathways may be metal extensions of the thermal bonding pad that are disposed in channels formed in a backside passivation layer underneath the thermal bonding pad, and may be in direct contact with an underlying substrate. The thermal pathways may provide improved thermal dissipation from the substrate.

SEMICONDUCTOR DEVICE CAPABLE OF DISPERSING STRESSES

A semiconductor device includes a semiconductor substrate including a circuit layer disposed therein, a bonding pad disposed on the semiconductor substrate, the bonding pad being electrically connected to the circuit layer, and a metal layer electrically connected to the bonding pad. The metal layer includes a first via electrically connected to the bonding pad, the first via providing an electrical path between the metal layer and the circuit layer, and a second via protruding toward the semiconductor substrate, the second via supporting the metal layer on the semiconductor substrate.

EFFICIENT REDISTRIBUTION LAYER TOPOLOGY

In some examples, a chip scale package (CSP) comprises a semiconductor die; a passivation layer abutting the semiconductor die; a via extending through the passivation layer; and a first metal layer abutting the via. The CSP also includes an insulation layer abutting the first metal layer, with the insulation layer having an orifice with a maximal horizontal area of less than 32400 microns2. The CSP further includes a second metal layer abutting the insulation layer and adapted to couple to a solder ball. The second metal layer abuts the first metal layer at a point of contact defined by the orifice in the insulation layer.

Silicon photonic interposer with two metal redistribution layers

A first metallic trace of a redistribution layer 105 is coated by a dielectric layer 110 with contact openings 120, 125 for contacting a further conductive trace 115 and a bond pad. A first metallic barrier layer 116 is used to form an under bump metallization layer of the bond pad and also a layer of a second conductive trace. The second conductive trace contacts the first conductive trace of the redistribution layer through a via hole 120 formed in the dielectric layer 110. The IC may be a photonic IC.

Semiconductor package and fabrication method thereof

一种半导体封装件及其制法，该半导体封装件包括：第一半导体装置，其具有相对的第一顶面与第一底面；多个导通球，其形成于该第一顶面；第二半导体装置，其具有相对的第二顶面与第二底面，且该第二底面为面向该第一顶面；以及多个导电柱，其形成于该第二底面，并分别接合该些导通球以电性连接该第一及第二半导体装置，且该导电柱的高度小于300微米。藉此，本发明可易于控制该半导体封装件的高度，并用于具有更精细间距的导通球的半导体封装件上。

Semiconductor package and manufacturing method thereof

RIGID WAVE PATTERN DESIGN ON CHIP CARRIER SUBSTRATE AND PRINTED CIRCUIT BOARD FOR SEMICONDUCTOR AND ELECTRONIC SUB-SYSTEM PACKAGING

강체 웨이브 패턴이 반도체 다이 패키지에서의 기판의 제 1 사이드에 형성된다. 이 강체 웨이브 패턴은 기판의 제 2 사이드에 형성된 콘택 핑거들에 맞추어 정렬되고 이 콘택 핑거들의 위에 놓인다. 이 기판과 다이스는 몰딩 공정 동안 케이싱되고, 이 강체 웨이브 패턴은 다이 상의 응력 및 다이의 변형을 효과적으로 감소시키며, 그 결과 다이 크래킹을 실질적으로 경감시킨다. 강체 웨이브 패턴, 다이 패키지, 콘택 핑거, 응력, 다이 크래킹

WAFER SCALE PACKAGING DIE WITH OFFSET REDISTRIBUTION LAYER CAPTURE PAD

A wafer scale packaging ("WSP") die having a redistribution layer ("RDL") with an RDL capture pad (41) that has an RDL pad central axis RR and a RDL pad outer peripheral edge (49) arranged about the RDL capture pad central axis RR and an under bump metal ("UBM") pad (60) positioned above the RDL capture pad. The UBM pad has a UBM pad central axis UU and a UBM pad outer peripheral edge (67) arranged around the UBM pad central axis UU. The UBM pad central axis UU is laterally offset from the RDL pad central axis RR.

Compliant interconnects in wafers

A microelectronic assembly includes a substrate and an electrically conductive element. The substrate can have a CTE less than 10 ppm/° C., a major surface having a recess not extending through the substrate, and a material having a modulus of elasticity less than 10 GPa disposed within the recess. The electrically conductive element can include a joining portion overlying the recess and extending from an anchor portion supported by the substrate. The joining portion can be at least partially exposed at the major surface for connection to a component external to the microelectronic unit.

Interconnect crack arrestor structure and methods

A system and method for preventing cracks is provided. An embodiment comprises placing crack stoppers into a connection between a semiconductor die and a substrate. The crack stoppers may be in the shape of hollow or solid cylinders and may be placed so as to prevent any cracks from propagating through the crack stoppers.

SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE USING THE CHIP

A semiconductor chip includes at least one electrode pad formed on a substrate; a protective film formed on the substrate and the electrode pad, and having an opening exposing the electrode pad; an under barrier metal layer formed on the electrode pad to cover an edge of the opening of the protective film; and a bump formed on the under barrier metal layer. A contact angle between the under barrier metal layer and the protective film is less than 90° at an edge of the under barrier metal layer. A contact angle between the bump and the under barrier metal layer is less than 90° at an edge of the bump.

Concentric bump design for the alignment in die stacking

An integrated circuit structure includes an alignment bump and an active electrical connector. The alignment bump includes a first non-solder metallic bump. The first non-solder metallic bump forms a ring encircling an opening therein. The active electrical connector includes a second non-solder metallic bump. A surface of the first non-solder metallic bump and a surface of the second non-solder metallic bump are substantially coplanar with each other.

Structure and method for semiconductor packaging

A semiconductor packaging structure includes a die including a bond pad and a first metal layer structure disposed on the die, the first metal layer structure having a first width, the first metal layer structure including a first metal layer, the first metal layer electrically coupled to the bond pad. The semiconductor packaging structure also includes a first photosensitive material around sides of the first metal layer structure and a second metal layer structure disposed over the first metal layer structure and over a portion of the first photosensitive material, the second metal layer structure electrically coupled to the first metal layer structure, the second metal layer structure having a second width, where the second width is greater than the first width. Additionally, the semiconductor packaging structure includes a second photosensitive material around sides of the second metal layer structure.

Halbleitervorrichtung

... [Problem] Reduzierung der Impedanz einer in einem Halbleiterchip bereitgestellten vorgegebenen Verdrahtung. [Lösung] Ein Halbleiterchip (100) mit einer Vielzahl von Anschlusselektroden (110a, 110c) und ein Verdrahtungssubstrat (200) als auf dem Halbleiterchip (100) bereitgestellte Verdrahtungsstruktur sind bereitgestellt. Das Verdrahtungssubstrat (200) hat eine Vielzahl von externen Anschlüssen (260), eine Vielzahl von Verdrahtungsmustern (240) für die elektrische Verbindung jedes der externen Anschlüsse (260) mit den Anschlusselektroden (110a) und eine Brückenverdrahtung (290) für die elektrische Verbindung der Vielzahl von Anschlusselektroden (110c) in gemeinsam benutzter Weise, ohne mit jeglichem der externen Anschlüsse (260) im Verdrahtungssubstrat (200) elektrisch verbunden zu sein. Da die der Verdrahtungsstruktur bereitgestellte Brückenverdrahtung (290) die Verdrahtung im Halbleiterchip (100) ergänzt, ist es durch die vorliegende Erfindung möglich, die Impedanz einer vorgegebenen ...

Compliance interconnection pillars having directions or geometrical shapes depending on positions on dies or provided with patterned structure between pillars and spacer of die for reducing thermal stress

Pillars (300, 346, 502) having a directed compliance geometry are arranged to couple a semiconductor die (400, 500) to a substrate. The direction of maximum compliance of each pillar (300, 346, 502) may be aligned with the direction of maximum stress caused by unequal thermal expansion and contraction of the semiconductor die (400, 500) and substrate. Pillars (300, 346, 502) may be designed and constructed with various shapes having particular compliance characteristics and particular directions (302, 304, 308, 310, 504) of maximum compliance. The shape and orientation of the pillars (300, 346, 502) may be selected as a function of their location on a die (400, 500) to accommodate the direction and magnitude of stress at their location. A method includes fabricating pillars with particular shapes by patterning by patterning materials (604) such as passivation materials on a spacer of a die (600) to increase surface of materials (604) upon which the pillar (610) is plated or deposited.

반도체 구조 및 반도체 구조를 형성하는 방법

일부 실시예는 반도체 구조를 포함한다. 이 구조는 반도체 다이를 관통하여 연장하는 전기 전도성 포스트를 갖는다. 포스트는 다이의 후표면 위에 상위 표면을 가지며, 후표면과 상위 표면 사이를 연장하는 측벽 표면을 갖는다. 감광성 물질이 후표면 위에 그리고 측벽 표면을 따라 있다. 전기 전도성 물질이 포스트의 상위 표면에 바로 닿아 있다. 전기 전도성 물질은 포스트 위에 캡으로서 구성된다. 캡은, 포스트를 넘어서 측방향 외부로 연장하며 포스트를 에워싸는 에지를 갖는다. 에지 전체는 감광성 물질 바로 위에 있다. 일부 실시예는, 웨이퍼-관통 상호연결 인근에 감광성 물질을 갖고, 상호연결의 상위 표면 위에 그리고 그에 바로 닿아 있으며, 감광성 물질의 상위 표면에 바로 닿아 있는 전기 전도성 물질 캡을 갖는 반도체 구조를 형성하는 방법을 포함한다.

Semiconductor structure having a patterned surface structure and semiconductor chips including such structures

BONDING PADS WITH THERMAL PATHWAYS

Apparatuses and methods for providing thermal pathways from a substrate to a thermal bonding pad. The thermal pathways may be metal extensions of the thermal bonding pad that are disposed in channels formed in a backside passivation layer underneath the thermal bonding pad, and may be in direct contact with an underlying substrate. The thermal pathways may provide improved thermal dissipation from the substrate. 1. A method , comprising:forming a passivation layer on a wafer;etching a portion of the passivation layer to form etched trenches for the. pathways; andforming a bonding pad on the thermal pathways.2. The method of claim 1 , further comprising:aligning the wafer with a photolithography mask to etch the portion of the passivation layer.3. The method of claim 1 , wherein aligning the passivation layer on the wafer comprises coating the wafer with at least one layer of photoresist.4. The method of claim 1 , wherein etching the portion of the passivation layer to form the etched trenches comprises delineating the etched trenches with a photolithography mask that forms the etched trenches including the thermal pathways.5. The method of claim 1 , further comprising:dicing the wafer into a plurality of dies; andstacking a first die of the plurality of dies onto a second die of the plurality of dies.6. The method of claim 1 , further comprising forming the thermal pathways in the etched trenches.7. The method of claim 6 , wherein forming the thermal pathways comprises forming the thermal pathways as concentric circles or as a spiral in the etched trenches of the passivation layer.8. The method of claim 6 , wherein forming the thermal pathways comprises distributing the formation of the thermal pathways in parallel claim 6 , relative to each other.9. The method of claim 1 , herein forming the bonding pad on the thermal pathways comprises:plating the bonding pad on the thermal pathways and the passivation layer; andremoving photoresist from the wafer.10. The method ...

SEMICONDUCTOR DEVICE AND WAFER LEVEL PACKAGE INCLUDING SUCH SEMICONDUCTOR DEVICE

An RDL structure on a passivation layer includes a first landing pad disposed directly above a first on-chip metal pad; a first via in a passivation layer to electrically connect the first landing pad with the first on-chip metal pad; a second landing pad disposed directly above the second on-chip metal pad; a second via in the passivation layer to electrically connect the second landing pad with the second on-chip metal pad; and at least five traces being disposed on the passivation layer and passing through a space between the first landing pad and the second landing pad.

SEMICONDUCTOR PACKAGE

A semiconductor package includes; a redistribution substrate including a redistribution pattern, a semiconductor chip mounted on a top surface of the redistribution substrate, and a connection terminal between the semiconductor chip and the redistribution substrate. The redistribution substrate further includes; a pad structure including a pad interconnection and a pad via, disposed between the redistribution pattern and the connection terminal, wherein the pad structure is electrically connected to the redistribution pattern and a top surface of the pad structure contacts the connection terminal, a shaped insulating pattern disposed on a top surface of the redistribution pattern, and a pad seed pattern disposed on the redistribution pattern and covering the shaped insulating pattern. 1. A semiconductor package comprising:a redistribution substrate including a redistribution pattern;a semiconductor chip mounted on a top surface of the redistribution substrate; anda connection terminal between the semiconductor chip and the redistribution substrate,{'claim-text': ['a pad structure including a pad interconnection and a pad via, disposed between the redistribution pattern and the connection terminal, wherein the pad structure is electrically connected to the redistribution pattern and a top surface of the pad structure contacts the connection terminal;', 'a shaped insulating pattern disposed on a top surface of the redistribution pattern; and', 'a pad seed pattern disposed on the redistribution pattern and covering the shaped insulating pattern.'], '#text': 'wherein the redistribution substrate further includes:'}2. The semiconductor package of claim 1 , wherein the pad structure comprises:a first metal pattern and a second metal pattern sequentially stacked on the pad interconnection, wherein the connection terminal contacts a top surface of the second metal pattern.3. The semiconductor package of claim 1 , wherein the redistribution substrate further includes an ...

Semiconductor device and its wafer level package

Substrate structure

Provided is a substrate structure, comprising: a substrate body and an electrical connecting pad disposed on the substrate, wherein the electrical connecting pad has at least a hollow portion for exposing parts of the substrate body therefrom, thereby reducing rigidity of the connecting pad and thus the resistance torque generated by the force of the substrate structure to prevent substrate breakage.

Semiconductor device and electronic apparatus

A first connection pad connected with a first wiring and a first floating metal greater than the first connection pad are formed at a bonding surface of a first substrate, whereas a second connection pad connected with a second wiring and a second floating metal greater than the second connection pad are formed at a bonding surface of a second substrate. The first joint pad and the second floating metal are connected to each other, the second floating metal and the first floating metal are connected to each other, and the first floating metal and the second joint pad are connected to each other, whereby the first floating metal and the second floating metal formed at the first substrate and the second substrate are bonded to each other. The present disclosure is applicable to a CMOS solid-state imaging device used for an imaging apparatus such as a camera, for example.

TWO-COMPONENT BUMP METALLIZATION

A structure has a first substrate bonded to a first under-bump metallization (UBM) structure, the first UBM structure comprising a first bonding region laterally surrounded by a first superconducting region. A second substrate is bonded to a second under-bump metallization (UBM) structure, the second UBM structure comprising a second bonding region laterally surrounded by a second superconducting region; and a superconducting solder material joins the first UBM structure to the second UBM structure. 1. A structure , comprising:an under-bump metallization (UBM) structure comprising a bonding region laterally surrounded by a superconducting region; anda superconducting solder material joining the UBM structure to a substrate.2. The structure of claim 1 , wherein the bonding region comprises a non-oxidizing metal.3. The structure of claim 1 , wherein the superconducting region is an annular ring that circumferentially surrounds the bonding region.4. The structure of claim 1 , wherein the bonding region has a lower level of surface oxidation than the superconducting region.5. The structure of claim 1 , wherein the bonding region has a higher enthalpy of vaporization than the superconducting region.6. The structure of claim 1 , wherein the bonding region is selected from a group consisting of: titanium; palladium or gold.7. The structure of claim 1 , wherein the superconducting region has greater electrical coupling than the bonding region.8. The structure of claim 1 , wherein the superconducting region is selected from a group consisting of: titanium nitride claim 1 , tantalum or aluminum.9. A structure claim 1 , comprising:a first substrate bonded to a first under-bump metallization (UBM) structure, the first UBM structure comprising a first bonding region laterally surrounded by a first superconducting region;a second substrate bonded to a second under-bump metallization (UBM) structure, the second UBM structure comprising a second bonding region laterally surrounded ...

Semiconductor assembly and method for manufacturing semiconductor assembly

SEMICONDUCTOR DEVICE HAVING PAD STRUCTURE WITH STRESS BUFFER LAYER

SUBSTRATE STRUCTURE

Interconnection Structure

An electrical interconnect for connecting an IC chip to a PCB, the electrical interconnect comprising a plurality of connection elements for connection to the PCB attached to a first surface of the electrical interconnect, wherein the amount of thermal and/or mechanical stress that each solder element connection can take before failing is improved.

Leistungs-Halbleitervorrichtung

Bei einer Leistungs-Halbleitervorrichtung (100), wird eine vorderseitige Elektrode (41a) eines Leistungs-Halbleiterelements derart gebildet, dass auf einer Cu-Schicht (81), die hauptsächlich aus Cu besteht, durch nicht-elektrolytisches Plattieren gebildet wird, und eine Vickershärte von 200 bis 350 Hv aufweist, eine Cu-Schicht 82 laminiert wird, die hauptsächlich aus Cu besteht, durch nicht-elektrolytisches Plattieren gebildet wird, und eine Vickershärte von 70 bis 150 Hv aufweist und daher weicher als die Cu-Schicht 81 ist. Die Cu-Schicht 82 und ein Draht 6 aus Cu werden miteinander drahtgebondet.

Längliche Bumps in integrierten Schaltungen

Eine Vorrichtung enthält ein Substrat, ein Metall-Pad über dem Substrat und eine Passivierungsschicht, die Kantenabschnitte des Metall-Pads bedeckt. Die Passivierungsschicht weist eine erste Öffnung auf, die das Metall-Pad überlappt, wobei die erste Öffnung eine erste seitliche Abmessung aufweist, die in einer zu einer Hauptfläche des Substrats parallelen Richtung gemessen ist. Eine Polymerschicht befindet sich über der Passivierungsschicht und bedeckt die Kantenabschnitte des Metall-Pads. Die Polymerschicht weist eine zweite Öffnung auf, die das Metall-Pad überlappt. Die zweite Öffnung weist eine zweite seitliche Abmessung auf, die in der Richtung gemessen ist. Die erste seitliche Abmessung ist um mehr als ca. 7 m größer als die zweite seitliche Abmessung. Eine Under-Bump-Metallurgie (Under-Bump metallurgy (BM)) enthält einen ersten Abschnitt in der zweiten Öffnung und einen zweiten Abschnitt, der Abschnitte der Polymerschicht überlagert.

COMPLIANT INTERCONNECT PILLARS WITH ORIENTATION OR GEOMETRY DEPENDENT ON THE POSITION ON A DIE OR FORMED WITH A PATTERNED STRUCTURE BETWEEN THE PILLAR AND A DIE PAD FOR REDUCTION OF THERMAL STRESS

Semiconductor device and method for forming the same

COMPLIANT INTERCONNECT PILLARS WITH ORIENTATION OR GEOMETRY DEPENDENT ON THE POSITION ON A DIE OR FORMED WITH A PATTERNED STRUCTURE BETWEEN THE PILLAR AND A DIE PAD FOR REDUCTION OF THERMAL STRESS

Pillars (300, 306, 502) having a directed compliance geometry are arranged to couple a semiconductor die (400, 500) to a substrate. The direction of maximum compliance of each pillar (300, 306, 502) may be aligned with the direction of maximum stress caused by unequal thermal expansion and contraction of the semiconductor die (400, 500) and the substrate. Pillars (300, 306, 502) may be designed and constructed with various shapes having particular compliance characteristics and particular directions (302, 304, 308, 310, 504) of maximum compliance. The shape and orientation of the pillars (300, 306, 502) may be selected as a function of their location on a die (400, 500) to accommodate the direction and magnitude of stress at their location. Pillars (610) may also be fabricated with particular shapes by patterning a material (604) such as a passivation material on a pad on a die (600) to increase the surface area upon which the pillar (610) is plated or deposited.

FLIP-CHIP FLEXIBLE UNDER BUMP METALLIZATION SIZE

Disclosed is a flip-chip device. The flip-chip device includes a die having a plurality of under bump metallizations (UBMs); and a package substrate having a plurality of bond pads. The plurality of UBMs include a first set of UBMs having a first size and a first minimum pitch and a second set of UBMs having a second size and a second minimum pitch. The first set of UBMs and the second set of UBMs are each electrically coupled to the package substrate by a bond-on-pad connection.

Semiconductor package

The present disclosure provides a semiconductor package, including a substrate, an active region in the substrate, an interconnecting layer over the active region, a conductive pad over the interconnecting layer, surrounded by a dielectric layer. At least two discrete regions of the conductive pad are free from coverage of the dielectric layer. A method of manufacturing the semiconductor package is also disclosed.

Concentric Bump Design for the Alignment in Die Stacking

An integrated circuit structure includes an alignment bump and an active electrical connector. The alignment bump includes a first non-solder metallic bump. The first non-solder metallic bump forms a ring encircling an opening therein. The active electrical connector includes a second non-solder metallic bump. A surface of the first non-solder metallic bump and a surface of the second non-solder metallic bump are substantially coplanar with each other.

Semiconductor device and method of forming guard ring around conductive TSV through semiconductor wafer

A semiconductor device has a plurality of conductive vias formed into a semiconductor wafer. An insulating lining is formed around the conductive vias and a conductive layer is formed over the insulating lining. A portion of the semiconductor wafer is removed so the conductive vias extend above a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and conductive vias. A first portion of the first insulating layer is removed and a second portion of the first insulating layer remains as guard rings around the conductive vias. A conductive layer is formed over the conductive vias. A second insulating layer is formed over the surface of the semiconductor wafer, guard rings, and conductive vias. A portion of the second insulating layer is removed to expose the conductive vias and a portion of the guard rings.

SEMICONDUCTOR DEVICES HAVING A NON-GALVANIC CONNECTION

A semiconductor device comprises a semiconductor chip having a radio-frequency circuit and a radio-frequency terminal, an external radio-frequency terminal, and a non-galvanic connection arranged between the radio-frequency terminal of the semiconductor chip and the external radio-frequency terminal, wherein the non-galvanic connection is designed to transmit a radio-frequency signal.

A ROUTING LAYER FOR MITIGATING STRESS IN A SEMICONDUCTOR DIE

알파 아미노산 및 비스에폭사이드의 반응 산물을 함유하는 구리 전기도금조로부터 포토레지스트 정의된 특징부의 전기도금 방법

... 전기도금 방법은 실질적으로 균일한 형태를 갖는 포토레지스트 정의된 특징부의 도금을 가능케 한다. 전기도금 방법에는 포토레지스트 정의된 특징부를 전기도금하기 위해 α-아미노산 및 비스에폭사이드의 반응 산물을 포함하는 구리 전기도금조가 포함된다. 이러한 특징부에는 기둥, 결합 패드 및 라인 스페이스 특징부가 포함된다.

반도체 디바이스, 집적 회로 구조체 및 반도체 디바이스의 제조 방법

... 반도체 디바이스는 기판, 반도체 구조체, 금속 패드 및 응력 해소 재료를 포함한다. 반도체 구조체는 기판 상에 배치된다. 금속 패드는 반도체 구조체 상에 배치된다. 금속 패드는 관통공을 포함한다. 이 관통공에 응력 해소 재료가 배치된다.

Structures, architectures, systems, methods, algorithms and software for configuring and integrated circuit for multiple packaging types

Structures, architectures, systems, an integrated circuit, methods and software for configuring an integrated circuit for multiple packaging types and/or selecting one of a plurality of packaging types for an integrated circuit. The structure generally comprises a bump pad, a plurality of bond pads configured for independent electrical connection to the bump pad, and a plurality of conductive traces, each adapted to electrically connect one of the bond pads to the bump pad. The software is generally configured to place and route components of such a structure. The method of configuring generally includes the steps of forming the bump pad, the bond pads, and the conductive traces from an uppermost metal layer, and forming an insulation layer thereover. The method of selecting generally comprises the uppermost metal layer-forming step, and forming either (i) a wire bond to at least one of the bond pads, or (ii) a bumping metal configured to electrically connect at least one of the bond pads ...

Semiconductor device and semiconductor package

The present disclosure relates to bonding structures useful in semiconductor packages. In an embodiment, a semiconductor device includes a semiconductor element, two pillar structures, and an insulation layer. The semiconductor element has a surface and includes at least one bonding pad disposed adjacent to the surface. The two pillar structures are disposed on a single bonding pad. The insulation layer is disposed adjacent to the surface of the semiconductor element. The insulation layer defines an opening, the opening exposes a portion of the single bonding pad, and the two pillar structures are disposed in the opening.

COMPLIANT INTERCONNECTS IN WAFERS

A microelectronic assembly includes a substrate and an electrically conductive element. The substrate can have a CTE less than 10 ppm/° C., a major surface having a recess not extending through the substrate, and a material having a modulus of elasticity less than 10 GPa disposed within the recess. The electrically conductive element can include a joining portion overlying the recess and extending from an anchor portion supported by the substrate. The joining portion can be at least partially exposed at the major surface for connection to a component external to the microelectronic unit.

Semiconductor device having pad structure with stress buffer layer

A semiconductor device has a pad structure with a ring-shaped stress buffer layer between a metal pad and an under-bump metallization (UBM) layer. The stress buffer layer is formed of a dielectric layer with a dielectric constant less than 3.5, a polymer layer, or an aluminum layer. The stress buffer layer is a circular ring, a square ring, an octagonal ring, or any other geometric ring.

Bond pad design for improved routing and reduced package stress

A bond pad design comprises a plurality of bond pads on a semiconductor chip and a plurality of under-bump metallurgy (UBM) layers formed on respective bond pads of the plurality. At least one of the bond pads has an elongated shape having an elongated portion and a contracted portion, the elongated portion oriented substantially along a stress direction radiating from a center to the periphery of the chip.

Semiconductor Device and Method of Forming Guard Ring Around Conductive TSV Through Semiconductor Wafer

A semiconductor device has a plurality of conductive vias formed into a semiconductor wafer. An insulating lining is formed around the conductive vias and a conductive layer is formed over the insulating lining. A portion of the semiconductor wafer is removed so the conductive vias extend above a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and conductive vias. A first portion of the first insulating layer is removed and a second portion of the first insulating layer remains as guard rings around the conductive vias. A conductive layer is formed over the conductive vias. A second insulating layer is formed over the surface of the semiconductor wafer, guard rings, and conductive vias. A portion of the second insulating layer is removed to expose the conductive vias and a portion of the guard rings.

SEMICONDUCTOR DEVICE WITH FINE PITCH REDISTRIBUTION LAYERS

A semiconductor device with fine pitch redistribution layers is disclosed and may include a semiconductor die with a bond pad and a first passivation layer comprising an opening above the bond pad. A redistribution layer (RDL) may be formed on the passivation layer with one end of the RDL electrically coupled to the bond pad and a second end comprising a connection region. A second passivation layer may be formed on the RDL with an opening for the connection region of the RDL. An under bump metal (UBM) may be formed on the connection region of the RDL and a portion of the second passivation layer. A bump contact may be formed on the UBM, wherein a width of the RDL is less than a width of the opening in the second passivation layer and may be constant from the bond pad through at least a portion of the opening. 1. A semiconductor device comprising:a semiconductor die comprising a bond pad;a first passivation layer covering a first surface of the semiconductor die, the first passivation layer comprising an opening above the bond pad;a redistribution layer (RDL) on the first passivation layer with one end of the RDL electrically coupled to the bond pad and a second end comprising a connection region;a second passivation layer on the RDL and on a portion of the first passivation layer, the second passivation layer comprising an opening for the connection region of the RDL;an under bump metal (UBM) on the connection region of the RDL and a portion of the second passivation layer; anda bump contact on the UBM, wherein a width of the RDL is less than a width of the opening in the second passivation layer.2. The semiconductor device according to claim 1 , wherein the width of the RDL is constant from the bond pad through at least a portion of the opening.3. The semiconductor device according to claim 1 , wherein the UBM is on a portion of the first passivation layer.4. The semiconductor device according to claim 1 , wherein the connection region comprises a region of the ...

METHOD OF ELECTROPLATING PHOTORESIST DEFINED FEATURES FROM COPPER ELECTROPLATING BATHS CONTAINING REACTION PRODUCTS OF ALPHA AMINO ACIDS AND BISEPOXIDES

Electroplating methods enable the plating of photoresist defined features which have substantially uniform morphology. The electroplating methods include copper electroplating baths with reaction products of α-amino acids and bisepoxides to electroplate the photoresist defined features. Such features include pillars, bond pads and line space features. 1. A method comprising:a) providing a substrate comprising a layer of photoresist, wherein the layer of photoresist comprises a plurality of apertures;b) providing a copper electroplating bath comprising one or more reaction products of one or more α-amino acids and one or more bisepoxides; an electrolyte; one or more accelerators; and one or more suppressors;c) immersing the substrate comprising the layer of photoresist with the plurality of apertures in the copper electroplating bath; andd) electroplating a plurality of copper photoresist defined features in the plurality of apertures, the plurality of photoresist defined features comprise an average % TIR of -5% to -1%.2. The method of claim 1 , wherein an average % WID of an array of copper photoresist defined features on the substrate is 12% to 15%.3. The method of claim 1 , wherein the one or more α-amino acids are chosen from arginine and lysine.6. The method of claim 1 , wherein the one or more reaction products are in amounts of 0.25 ppm to 20 ppm in the copper electroplating bath.7. The method of claim 1 , wherein electroplating is done at a current density of 0.25 ASD to 40 ASD.8. The method of claim 1 , wherein the one or more copper photoresist defined features are pillars claim 1 , bond pads or line space features.9. A plurality of photoresist defined features on a substrate comprising an average % TIR of −5% to −1% and an average % WID of 12% to 15%. The present invention is directed to a method of electroplating photoresist defined features from copper electroplating baths which include reaction products of α-amino acids and bisepoxides. More ...

Semiconductor device and semiconductor package

The present disclosure relates to bonding structures useful in semiconductor packages. In an embodiment, a semiconductor device includes a semiconductor element, two pillar structures, and an insulation layer. The semiconductor element has a surface and includes at least one bonding pad disposed adjacent to the surface. The two pillar structures are disposed on a single bonding pad. The insulation layer is disposed adjacent to the surface of the semiconductor element. The insulation layer defines an opening, the opening exposes a portion of the single bonding pad, and the two pillar structures are disposed in the opening.

Semiconductor device and electronic apparatus

The present disclosure relates to a semiconductor device and an electronic apparatus which is capable of reducing variations and deterioration of transistor characteristics. A first connection pad connected with a first wiring and a first floating metal greater than the first connection pad are formed at a bonding surface of a first substrate, whereas a second connection pad connected with a second wiring and a second floating metal greater than the second connection pad are formed at a bonding surface of a second substrate. The, and the first floating metal and the second floating metal formed at the first substrate and the second substrate are bonded to each other. The present disclosure is applicable to a CMOS solid-state imaging device used for an imaging apparatus such as a camera, for example.

RIGID WAVE PATTERN DESIGN ON CHIP CARRIER SUBSTRATE AND PRINTED CIRCUIT BOARD FOR SEMICONDUCTOR AND ELECTRONIC SUB-SYSTEM PACKAGING

A rigid wave pattern formed on a first side of a substrate in a semiconductor die package. The rigid wave pattern aligns with and overlies the contact fingers formed on the second side of the substrate. The rigid wave pattern includes a first pattern with an etched portion and an unetched portion around the etched portion. When the substrate and dice are encased during the molding process, the rigid wave pattern effectively reduces deformation of and stresses on the dice, therefore substantially alleviating die cracking. 1. A substrate for supporting and electrically connecting to a semiconductor dice , the substrate including a first surface supporting the semiconductor die and a second surface opposite the first surface , the second surface including portions defining a planar surface and a patterned area recessed within the planar surface , the substrate comprising:a first pattern on the first surface of the substrate, the first pattern aligning with the patterned area, the first pattern comprising:an etched portion within a footprint of the aligned patterned area; andan unetched portion surrounding the etched portion, the first pattern reducing a mechanical stress generated by the patterned area on the semiconductor dice during a molding process.2. A substrate as recited in claim 1 , wherein the patterned area includes a contact finger for forming an external electrical connection.3. A substrate as recited in claim 2 , wherein the etched portion of the first pattern includes a pair of straight edges claim 2 , a distance between the straight edges being approximately equal to a width of the contact finger claim 2 , and a length of the straight edges being approximately equal to a length of the contact finger.4. A substrate as recited in claim 2 , wherein the etched portion of the first pattern includes two pair of etched sections claim 2 , each pair of etched sections including straight sections inclined toward each other from a middle of the etched portion to ...

Integrated circuit die having a split solder pad

The invention relates to an electronic system comprising: an integrated circuit die having: at least 2 bond pads a redistribution layer, said redistribution layer having: at least a solder pad comprising 2 portions arranged to enable an electrical connection between each other by a same solder ball placed on said solder pad, but electrically isolated of each other in the absence of a solder ball on the solder pad at least 2 redistribution wires, each one connecting one of the 2 portions to one of the 2 bond pads, a second bond pad connected via a second redistribution wire to a second portion of the solder pad being dedicated to testing said integrated circuit die a grounded printed circuit board track, a solder ball being placed between the solder pad and the printed circuit board track.

POWER SEMICONDUCTOR DEVICE

In a power semiconductor device, a front-surface electrode of a power semiconductor element is formed in such a manner that, on a first Cu layer consisting mainly of Cu, formed by non-electrolytic plating and having a Vickers hardness of 200 to 350 Hv, a second Cu layer consisting mainly of Cu, formed by non-electrolytic plating and having a Vickers hardness of 70 to 150 Hv and thus being softer than the first Cu layer, is laminated. The second Cu layer and a wire made of Cu are wire-bonded together. 122.-. (canceled)23. A power semiconductor device , comprising:a power semiconductor element;a first electrode layer formed on the power semiconductor element;a second electrode layer formed on the first electrode layer, said second electrode layer consisting mainly of Cu and having a hardness lower than that of the first electrode layer; anda bonding wire consisting mainly of Cu and connected to the second electrode layer;wherein the first electrode layer has a Vickers hardness of 200 to 350 Hv, and the second electrode layer has a Vickers hardness of 70 to 150 Hv.24. The power semiconductor device according to claim 23 , wherein the first electrode layer is a layer consisting mainly of Cu.25. The power semiconductor device according to claim 23 , wherein the first electrode layer comprises: an underlayer; and a layer consisting mainly of Cu and formed on the underlayer by non-electrolytic plating.26. The power semiconductor device according to claim 25 , wherein the second electrode layer is a layer consisting mainly of Cu and formed by non-electrolytic plating using the first electrode as a base.27. The power semiconductor device according to claim 23 , wherein the first electrode layer comprises an underlayer only claim 23 , and the second electrode layer is a layer consisting mainly of Cu and formed by non-electrolytic plating using the first electrode layer as a base.28. The power semiconductor device according to claim 23 , wherein the first electrode layer has ...

BONDING PADS WITH THERMAL PATHWAYS

Apparatuses and methods for providing thermal pathways from a substrate to a thermal bonding pad. The thermal pathways may be metal extensions of the thermal bonding pad that are disposed in channels formed in a backside passivation layer underneath the thermal bonding pad, and may be in direct contact with an underlying substrate. The thermal pathways may provide improved thermal dissipation from the substrate. 1. An apparatus , comprising:a substrate; anda first bonding pad including thermal pathways in direct contact with a backside of the substrate, wherein the thermal pathways are disposed in channels formed in a passivation layer on the backside of the substrate.2. The apparatus of claim 1 , wherein the thermal pathways are formed under the first bonding pad.3. The apparatus of claim 1 , wherein the thermal pathways are disposed in the channels formed in the passivation layer such that the thermal pathways form concentric circles or a spiral in the passivation layer.4. The apparatus of claim 1 , wherein the thermal pathways are disposed in the channels formed in the passivation layer such that the thermal pathways are distributed in parallel relative to each other and such that the thermal pathways extend along a length of the first bonding pad.5. The apparatus of claim 1 , wherein the substrate further includes a through-via extending from the backside of the substrate to a frontside of the substrate.6. The apparatus of claim 5 , further comprising a second bonding pad disposed on the passivation layer and coupled to the through-via.7. The apparatus of claim 6 , wherein the second bonding is disposed as a circular bonding pad on the through-via.8. The apparatus of claim 6 , wherein the first bonding pad and the second bonding pad are substantially equal in height.9. The apparatus of claim 6 , further comprising electrical interconnections formed on the first bonding pad and the second bonding pad.10. The apparatus of claim 6 , wherein the first bonding pad ...

METAL LAYER PATTERNING FOR MINIMIZING MECHANICAL STRESS IN INTEGRATED CIRCUIT PACKAGES

A method may include forming a metal pattern in a metal layer of a fabricated integrated circuit device and under a target bump of the fabricated integrated circuit device, wherein the metal pattern has an inner shape and an outer field such that a void space in the metal layer is created between the inner shape and the outer field and approximately centering the void space on an outline of an under-bump metal formed under the target bump with a keepout distance from the inner shape and the outer field on either side of the outline such that the metal minimizes local variations in mechanical stress on underlying structures within the fabricated integrated circuit device. 1. A method comprising:forming a metal pattern in a metal layer of a fabricated integrated circuit device and under a target bump of the fabricated integrated circuit device, wherein the metal pattern has an inner shape and an outer field such that a void space in the metal layer is created between the inner shape and the outer field; andapproximately centering the void space on an outline of an under-bump metal formed under the target bump with a keepout distance from the inner shape and the outer field on either side of the outline such that the metal minimizes local variations in mechanical stress on underlying structures within the fabricated integrated circuit device.2. The method of claim 1 , wherein the metal layer is a top-level metal of the fabricated integrated circuit device.3. The method of claim 1 , wherein the metal layer comprises one of copper claim 1 , a copper alloy claim 1 , and aluminum.4. The method of claim 1 , wherein the keepout distance is of a sufficient distance such that the metal pattern does not encroach on non-target bumps adjacent to the target bump.5. The method of claim 1 , wherein the outer field has an outer edge such that the outer field maintains the keepout distance from the under-bump metal outline.6. The method of claim 1 , further comprising forming multiple ...

SHIELDING STRUCTURES

Semiconductor device packages and method are provided. A semiconductor device package according to the present disclosure includes a substrate including a first region, a passive device disposed over the first region of the substrate, a contact pad disposed over the passive device, a passivation layer disposed over the contact pad, a recess through the passivation layer, and an under-bump metallization (UBM) layer. The recess exposes the contact pad and the UBM layer includes an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess. A projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad. 1. A method , comprising:receiving a design of a device package including a first coefficient of thermal expansion (CTE);determining a threshold radius from a geometric center of the device package based on the first CTE and a second CTE of a substrate;overlapping a center of a circle having the threshold radius with the geometric center to identify a first area of the device package outside of the circle and a second area of the device package within the circle;fabricating a first-type contact pad in the first area; andfabricating a second-type contact pad in the second area.2. The method of claim 1 , wherein the first CTE is smaller than the second CTE.3. The method of claim 1 ,wherein the design of the device package includes a plurality of bump features,wherein first stresses on a first portion of the plurality of bump features within the threshold radius is below a threshold stress level, andwherein second stresses on a second portion of the plurality of bump features outside the threshold radius is above the threshold stress level.4. The method of claim 3 , wherein each of the plurality of bump features comprises a racetrack shape or an oval shape that includes a long axis pointing toward the geometric center.5. The method of claim 1 , ...

TWO-COMPONENT BUMP METALLIZATION

A technique relates to a structure. An under-bump-metallization (UBM) structure includes a first region and a second region. The first and second regions are laterally positioned in the UBM structure. The first region includes a superconducting material. A substrate opposes the UBM structure. A superconducting solder material joins the first region to the substrate and the second region to the substrate. 1. A structure comprising:an under-bump-metallization (UBM) structure comprising a first region and a second region, the first and second regions being laterally positioned in the UBM structure, wherein the first region comprises a superconducting material;a substrate opposing the UBM structure; anda superconducting solder material joining the first region to the substrate and the second region to the substrate.2. The structure of claim 1 , wherein the UBM structure is arranged such that the first region is laterally adjacent to the second region claim 1 , enabling the superconducting solder material to contact both the first and second regions.3. The structure of claim 1 , wherein the UBM structure is arranged to have one or more first locations containing the first region and have one or more second locations containing the second region.4. The structure of claim 3 , wherein the one or more first locations are different from the one or more second locations.5. The structure of claim 1 , wherein the second region comprises a non-superconducting material.6. The structure of claim 1 , wherein the substrate comprises a superconducting circuit connected to the superconducting solder material claim 1 , such that the first region is electrically connected to the superconducting circuit.7. The structure of claim 1 , wherein a superconducting junction is formed between the superconducting solder material and the first region.8. A structure comprising:a first under-bump-metallization (UBM) structure comprising a first region and a second region, the first and second regions ...

Final passivation for wafer level warpage and ulk stress reduction

Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having an annular PSPI region formed under a BLM pad. An annular region is formed under a barrier layer metallurgy (BLM) pad. The annular region includes a photosensitive polyimide (PSPI). A conductive pedestal is formed on a surface of the BLM pad and a solder bump is formed on a surface of the conductive pedestal. The annular PSPI region reduces wafer warpage and ULK peeling stress.

STRUCTURE AND METHOD FOR SEMICONDUCTOR PACKAGING

A semiconductor packaging structure includes a die including a bond pad and a first metal layer structure disposed on the die, the first metal layer structure having a first width, the first metal layer structure including a first metal layer, the first metal layer electrically coupled to the bond pad. The semiconductor packaging structure also includes a first photosensitive material around sides of the first metal layer structure and a second metal layer structure disposed over the first metal layer structure and over a portion of the first photosensitive material, the second metal layer structure electrically coupled to the first metal layer structure, the second metal layer structure having a second width, where the second width is greater than the first width. Additionally, the semiconductor packaging structure includes a second photosensitive material around sides of the second metal layer structure. 1. A semiconductor packaging structure , comprising:a die comprising a bond pad;a first metal layer structure disposed on the die, the first metal layer structure having a first width, the first metal layer structure comprising a first metal layer, the first metal layer electrically coupled to the bond pad;a first photosensitive material around sides of the first metal layer structure;a second metal layer structure disposed over the first metal layer structure and over a portion of the first photosensitive material, the second metal layer structure electrically coupled to the first metal layer structure, the second metal layer structure having a second width, wherein the second width is greater than the first width; anda second photosensitive material around sides of the second metal layer structure.2. The semiconductor packaging structure of claim 1 , wherein the first photosensitive material is a permanent photoresist.3. The semiconductor packaging structure of claim 1 , wherein the first metal layer structure comprises a first seed layer between the first metal ...

MULTI-METAL CONTACT STRUCTURE

A first conductive material having a first hardness is disposed within a recess or opening of a microelectronic component, in a first preselected pattern, and forms a first portion of an interconnect structure. A second conductive material having a second hardness different from the first hardness is disposed within the recess or opening in a second preselected pattern and forms a second portion of the interconnect structure. 1. A microelectronic component comprising one or more semiconductor devices , the microelectronic component comprising:a substrate including a recess or opening extending from a first surface of the substrate, at least a portion of the first surface of the substrate having a planarized topography;a first conductive material having a first melting point, disposed within the recess or opening and forming a first portion of an interconnect structure of the microelectronic component; anda second conductive material having a second melting point different from the first melting point, disposed within the recess or opening and at least partially surrounded by or adjacent to the first conductive material, the second conductive material forming a second portion of the interconnect structure of the microelectronic component, the second portion of the interconnect structure extending normal to the plane of the substrate; anda barrier layer between the substrate and the first conductive material.2. The microelectronic component of claim 1 , further comprising a layer of the first conductive material disposed over an exposed surface of the second portion of the interconnect structure.3. The microelectronic component of claim 1 , further comprising a layer of a third conductive material claim 1 , different from the first and second conductive materials claim 1 , disposed over an exposed surface of the first and second portions of the interconnect structure.4. The microelectronic component of claim 1 , further comprising one or more additional conductive ...

Bump on Pad (BOP) Bonding Structure in Semiconductor Packaged Device

The embodiments described above provide enlarged overlapping surface areas of bonding structures between a package and a bonding substrate. By using elongated bonding structures on either the package and/or the bonding substrate and by orienting such bonding structures, the bonding structures are designed to withstand bonding stress caused by thermal cycling to reduce cold joints. 1. A package structure comprising:an integrated circuit package comprising a conductive post, the conductive post having a first racetrack shape in a plan view; a first contact pad having a second racetrack shape in the plan view, a line extending through a first center of the first racetrack shape and a second center of the second racetrack shape intersecting the-conductive post at an angle different from 90 degrees; and', 'a first dielectric layer over the first contact pad; and, 'a substrate bonded to the integrated circuit package, the substrate comprisinga solder layer extending through the first dielectric layer, the solder layer electrically and mechanically coupling the conductive post to the first contact pad.2. The package structure of claim 1 , wherein a long axis of the first racetrack shape is oriented toward a center of the integrated circuit package.3. The package structure of claim 1 , wherein an area of the first racetrack shape is less than an area of the second racetrack shape.4. The package structure of claim 1 , wherein the substrate further comprises a routing line claim 1 , the routing line being in electrical contact with the first contact pad.5. The package structure of claim 1 , wherein a coefficient of thermal expansion (CTE) of the integrated circuit package is less than a CTE of the substrate.6. The package structure of claim 1 , wherein the first racetrack shape overlaps with the second racetrack shape.7. The package structure of claim 1 , wherein a long axis of the first racetrack shape is collinear with a long axis of the second racetrack shape.8. A package ...

Method of forming a bondpad and bondpad

Various embodiments provide a method of forming a bondpad, wherein the method comprises providing a raw bondpad, and forming a recess structure at a contact surface of the raw bondpad, wherein the recess structure comprises sidewalls being inclined with respect to the contact surface. 1. A method of forming a bondpad , the method comprising:providing a raw bondpad; andforming a recess structure at a contact surface of the raw bondpad, wherein the recess structure comprises sidewalls being inclined with respect to the contact surface.2. The method according to claim 1 , wherein the sidewalls comprise an inclination angle in the range between 2° and 60° degree.3. The method according to claim 1 , wherein the recess structure is formed by removing a surface portion of the raw bondpad.4. The method according to claim 1 , wherein the removing is performed by an etching step.5. The method according to claim 1 , wherein the recess structure is formed by depositing additional material on the raw bondpad.6. The method according to claim 5 , wherein the additional material is the same material from which the bondpad is formed.7. The method according to claim 1 , wherein the recess structure has a conical form.8. The method according to claim 1 , wherein the sidewalls have a continuous surface.9. A bondpad for wire bonding with a bond wire claim 1 , the bondpad comprising a recess structure formed in a contact surface of the bondpad claim 1 , wherein the recess structure comprises sidewalls being inclined with respect to the contact surface.10. The bondpad according to claim 9 , wherein the recess structure has a size which is smaller than the diameter of the bonded bond wire.11. The bondpad according to claim 9 , wherein the sidewalls have a form selected out of the group consisting of:a conical form,a spherical form, andan ellipsoidal form.12. The bondpad according to claim 9 , wherein the bondpad comprises at least one material selected out of the group consisting of:copper ...

Semiconductor package structure

Semiconductor package structures are provided. A semiconductor package structure includes a chip, a molding material surrounding the chip, a through-via extending from a first surface to a second surface of the molding material, a first re-distribution layer (RDL) wire disposed on the second surface of the molding material and coupled to the through-via, and a second RDL wire disposed on the second surface of the molding material and parallel to the first RDL wire. The second surface is opposite to the first surface. A portion of the second RDL wire across the through-via has a first segment with a first width and a second segment with a second width different from the first width.

SILICON PHOTONIC INTERPOSER WITH TWO METAL REDISTRIBUTION LAYERS

A silicon integrated circuit. In some embodiments, the silicon integrated circuit includes a first conductive trace, on a top surface of the silicon integrated circuit, a dielectric layer, on the first conductive trace, and a second conductive trace, on the dielectric layer, connected to the first conductive trace through a first via. 1. A silicon integrated circuit , comprising:a first conductive trace, on a top surface of the silicon integrated circuit;a dielectric layer, on the first conductive trace; anda second conductive trace, on the dielectric layer, connected to the first conductive trace through a first via.2. The silicon integrated circuit of claim 1 , further comprising an under bump metallization capture pad claim 1 , on claim 1 , and connected to the first conductive trace through claim 1 , a second via.3. The silicon integrated circuit of claim 2 , wherein the under bump metallization capture pad comprises:a layer of nickel, and a layer of gold on the layer of nickel.4. The silicon integrated circuit of claim 1 , further comprising a wire bond pad claim 1 , on claim 1 , and connected to the first conductive trace through claim 1 , a second via.5. The silicon integrated circuit of claim 1 , wherein the first conductive trace is composed of a material selected from the group consisting of gold claim 1 , aluminum claim 1 , copper claim 1 , and alloys and combinations thereof.6. The silicon integrated circuit of claim 1 , wherein the second conductive trace is composed of a material selected from the group consisting of gold claim 1 , aluminum claim 1 , copper claim 1 , titanium claim 1 , tungsten claim 1 , tantalum claim 1 , and alloys and combinations thereof.7. The silicon integrated circuit of claim 6 , wherein the second conductive trace further comprises a layer of titanium tungsten.8. The silicon integrated circuit of claim 1 , wherein the dielectric layer is composed of a material selected from the group consisting of silicon dioxide claim 1 , ...

MICROELECTRONIC DEVICES AND APPARATUSES HAVING A PATTERNED SURFACE STRUCTURE

A connector structure and a manufacturing method thereof are provided. The connector structure includes a semiconductor substrate, a metal layer, a passivation layer, and a conductive structure. The metal layer is over the semiconductor substrate. The passivation layer is over the metal layer and includes an opening. The conductive structure is in contact with the metal layer in a patterned surface structure of the conductive structure through the opening of the passivation layer. 1. A microelectronic device , comprising:a metal material comprising a single material over and in contact with a base material;a passivation material over the metal material;a patterned surface structure comprising portions of the passivation material located in at least one opening of the passivation material; anda conductive structure comprising a solder material located over the patterned surface structure and in direct contact with the metal material through the at least one opening of the passivation material, portions of the conductive structure extending through the at least one opening of the passivation material and substantially conforming to surfaces of the patterned surface structure.2. The microelectronic device of claim 1 , wherein the passivation material comprises a single material in direct contact with each of the metal material and the conductive structure.3. The microelectronic device of claim 1 , wherein the at least one opening is bounded by a vertical sidewall of the passivation material claim 1 , the patterned surface structure comprising multiple laterally spaced portions of the passivation material located directly on the metal material in the at least one opening of the passivation material.4. The microelectronic device of claim 3 , wherein a portion of the conductive structure extending above the passivation material exhibits a lateral boundary substantially coincident with the vertical sidewall of the passivation material.5. The microelectronic device of claim ...

Shielding Structures

Semiconductor device packages and method are provided. A semiconductor device package according to the present disclosure includes a substrate including a first region, a passive device disposed over the first region of the substrate, a contact pad disposed over the passive device, a passivation layer disposed over the contact pad, a recess through the passivation layer, and an under-bump metallization (UBM) layer. The recess exposes the contact pad and the UBM layer includes an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess. A projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad. 1. A semiconductor device package comprising:a substrate including a first region;a passive device disposed over the first region of the substrate;a contact pad disposed over the passive device;a passivation layer disposed over the contact pad;a recess through the passivation layer, the recess exposing the contact pad; andan under-bump metallization (UBM) layer, the UBM layer including an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess,wherein a projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad.2. The semiconductor device package of claim 1 , wherein the first region is around an edge of the semiconductor device package.3. The semiconductor device package of claim 1 , wherein the passive device comprises a metal-insulator-metal (MIM) capacitor or a metal-oxide-metal (MOM) capacitor.4. The semiconductor device package of claim 1 ,wherein the contact pad includes a circular area within a surface area of the contact pad, the circular area having a radius R,wherein the upper portion includes a maximum radius A and a minimum radius B,wherein R is between one half of a sum of A and B ((A+B)/2) and the sum ...

Contact structures with porous networks for solder connections, and methods of fabricating same

A contact pad includes a solder-wettable porous network ( 310 ) which wicks the molten solder ( 130 ) and thus restricts the lateral spread of the solder, thus preventing solder bridging between adjacent contact pads.

Bonding pads with thermal pathways

Apparatuses and methods for providing thermal pathways from a substrate to a thermal bonding pad. The thermal pathways may be metal extensions of the thermal bonding pad that are disposed in channels formed in a backside passivation layer underneath the thermal bonding pad, and may be in direct contact with an underlying substrate. The thermal pathways may provide improved thermal dissipation from the substrate.

SEMICONDUCTOR STRUCTURE, REDISTRIBUTION LAYER (RDL) STRUCTURE, AND MANUFACTURING METHOD THEREOF

The present disclosure relates to a redistribution layer (RDL) structure, a manufacturing method thereof, and a semiconductor structure having the same. The RDL structure includes an RDL, disposed on a substrate, and including a bond pad portion and a wire portion connected to the bond pad portion, where a thickness of the bond pad portion is greater than a thickness of the wire portion. According to the RDL structure provided by the present disclosure, a bond pad portion has a thickness greater than a wire portion, so that the thicker bond pad portion can provide more impact buffer areas in gold or copper wire bonding of packaging to prevent a substrate from breaking due to a stress, and prevent an increase in a parasitic capacitance between wires. 1. A wiring layer (WL) structure , comprising:a WL, disposed on a substrate and comprising a bond pad portion and a wire portion connected to the bond pad portion,wherein a thickness of the bond pad portion is greater than a thickness of the wire portion.2. The WL structure according to claim 1 , wherein the bond pad portion comprises a bond pad body portion and a bond portion disposed on a surface of the bond pad body portion facing away from the substrate.3. The WL structure according to claim 2 , whereinthe bond pad portion is of a step shape; anda length and a width of the bond pad body portion are greater than a length and a width of an orthographic projection of the bond portion on the bond pad body portion respectively.4. The WL structure according to claim 3 , wherein a preset distance is provided between side edges of the bond portion and side edges of the bond pad body portion claim 3 , and the preset distance ranges from 0.5 μm to 3 μm.5. The WL structure according to claim 1 , wherein a bottom of the bond pad portion is aligned or unaligned with a bottom of the wire portion.6. The WL structure according to claim 2 , wherein the thickness of the wire portion is the same as the thickness of the bond pad body ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device is provided. The semiconductor device includes an electrode pad provided above a semiconductor substrate; and a wire bonded on the electrode pad and including copper. The electrode pad includes an electrode layer including aluminum and a support layer harder than the wire and the electrode layer. The wire is in contact with the electrode layer and the support layer. 1. A semiconductor device , comprising:an electrode pad provided above a semiconductor substrate; anda wire bonded on the electrode pad and including copper,whereinthe electrode pad comprises an electrode layer including aluminum and a support layer harder than the wire and the electrode layer, andthe wire is in contact with the electrode layer and the support layer.2. The semiconductor device of claim 1 , wherein the support layer penetrates the electrode layer from an upper surface of the electrode layer to a lower surface of the electrode layer.3. The semiconductor device of claim 1 , wherein the support layer comprises a ring-shaped portion extending in a ring shape at an upper surface of the electrode pad.4. The semiconductor device of claim 3 , wherein the support layer comprises a lattice-shaped portion extending in a lattice shape at the upper surface of the electrode pad in a range surrounded by the ring-shaped portion.5. The semiconductor device claim 3 , wherein the wire is in contact with an entirety of the ring-shaped portion.6. The semiconductor device of claim 1 , wherein the electrode pad comprises a plurality of the support layers being in contact with the wire.7. The semiconductor device of claim 1 , whereinthe electrode pad and the wire are covered with a resin including sulfur, anda combination of the wire and the support layer is less likely to be alloyed than a combination of the wire and the electrode layer.8. The semiconductor device of claim 1 , wherein the support layer includes tungsten.9. The semiconductor device of claim 1 , wherein the support layer ...

METHODS OF FORMING SEMICONDUCTOR STRUCTURES HAVING A PATTERNED SURFACE STRUCTURE

A connector structure and a manufacturing method thereof are provided. The connector structure includes a semiconductor substrate, a metal layer, a passivation layer, and a conductive structure. The metal layer is over the semiconductor substrate. The passivation layer is over the metal layer and includes an opening. The conductive structure is in contact with the metal layer in a patterned surface structure of the conductive structure through the opening of the passivation layer. 1. A method of forming a semiconductor structure , comprising:forming a metal material over a semiconductor substrate;forming a passivation material over the metal;removing at least a portion of the passivation material to form a patterned surface structure in at least one opening in the passivation material; andforming a conductive structure comprising a solder material over the patterned surface structure, the conductive structure being in contact with the metal material through the at least one opening of the passivation material.2. The method of claim 1 , wherein removing the at least a portion of the passivation material to form the patterned surface structure in the at least one opening comprises:applying a photoresist onto the passivation material; andperforming lithography and etching the passivation material to form the at least one opening with a remaining portion of the passivation material as a supporting portion therein.3. The method of claim 2 , wherein forming the conductive structure comprises:applying metal into the at least one opening of the passivation material; andreflowing the metal to form the conductive structure.4. The method of claim 1 , further comprising forming a supporting portion in the at least one opening after removing the at least a portion of the passivation material and before forming the conductive structure.5. The method of claim 4 , wherein forming the conductive structure comprises:applying metal into the at least one opening of the passivation ...

Compliant interconnects in wafers

A microelectronic assembly includes a substrate and an electrically conductive element. The substrate can have a CTE less than 10 ppm/° C., a major surface having a recess not extending through the substrate, and a material having a modulus of elasticity less than 10 GPa disposed within the recess. The electrically conductive element can include a joining portion overlying the recess and extending from an anchor portion supported by the substrate. The joining portion can be at least partially exposed at the major surface for connection to a component external to the microelectronic unit.

METAL PAD MODIFICATION

The present invention provides a structure. In an exemplary embodiment, the structure includes a base material, at least one metal pad, where a first surface of the metal pad is in contact with the base material, and a metal pedestal, where the metal pedestal is in contact with the metal pad, where a radial alignment of the metal pad is shifted by an offset distance, with respect to the metal pedestal, such that the metal pad is shifted towards a center axis of the base material, where a first dimension of the metal pad is smaller than a second dimension of the metal pad, where the second dimension is orthogonal to a line running from a center of the metal pad to the center axis of the base material, where the first dimension is parallel to the line. 1a base material; wherein a first surface of the metal pad is in contact with a surface of the base material,', 'wherein the metal pad is deposited within the base material;, 'at least one metal pad,'} wherein a first surface of the metal pedestal is in contact with a second surface of the metal pad,', 'wherein the offset distance ranges from 0 μm to 20 μm,', 'wherein a radial alignment of the metal pad is shifted by an offset distance, with respect to the metal pedestal, such that the metal pad is shifted towards a center axis of the base material,'}, 'wherein a first dimension of the metal pad is smaller than a second dimension of the metal pad,', 'wherein the second dimension is orthogonal to a line running from a center of the metal pad to the center axis of the base material,', 'wherein the first dimension is parallel to the line running from the center of the metal pad to the center axis of the base material,', 'wherein an aspect ratio of the second dimension to the first dimension is greater than 1:1 and less than 2:1; and, 'a metal pedestal,'}a solder bump in contact with a second surface of the metal pedestal; wherein the metal pedestal contacts the metal pad through the via in the passivation layer,', 'wherein ...

MULTI-METAL CONTACT STRUCTURE

A first conductive material having a first hardness is disposed within a recess or opening of a microelectronic component, in a first preselected pattern, and forms a first portion of an interconnect structure. A second conductive material having a second hardness different from the first hardness is disposed within the recess or opening in a second preselected pattern and forms a second portion of the interconnect structure. 1. A method comprising:providing a substrate having a recess or opening extending from a first surface of the substrate, at least a portion of the first surface of the substrate having a planarized topography;disposing a first conductive material having a first melting point within the recess or opening and forming a first portion of an interconnect structure of the substrate; anddisposing a second conductive material having a second melting point different from the first melting point within the recess or opening and at least partially surrounded by or adjacent to the first conductive material, the second conductive material forming a second portion of the interconnect structure of the substrate, the second portion of the interconnect structure extending normal to the plane of the substrate; andproviding a barrier layer between the substrate and the first conductive material.2. The method of claim 1 , further comprising disposing a layer of the first conductive material over an exposed surface of the second portion of the interconnect structure.3. The method of claim 1 , further comprising disposing a layer of a third conductive material claim 1 , different from the first and second conductive materials over an exposed surface of the first and second portions of the interconnect structure.4. The method of claim 1 , further comprising disposing one or more additional conductive materials having one or more additional melting points different from the first melting point and the second melting point within the recess or opening and forming one ...

SEMICONDUCTOR DEVICE AND WAFER LEVEL PACKAGE INCLUDING SUCH SEMICONDUCTOR DEVICE

An RDL structure on a passivation layer includes a first landing pad disposed directly above a first on-chip metal pad; a first via in a passivation layer to electrically connect the first landing pad with the first on-chip metal pad; a second landing pad disposed directly above the second on-chip metal pad; a second via in the passivation layer to electrically connect the second landing pad with the second on-chip metal pad; and at least five traces being disposed on the passivation layer and passing through a space between the first landing pad and the second landing pad. 1. A semiconductor device , comprising:an integrated circuit (IC) die having an active surface, wherein at least a first on-chip metal pad and a second on-chip metal pad in close proximity to the first on-chip metal pad are disposed on the active surface;a passivation layer on the active surface and covering the first on-chip metal pad and the second on-chip metal pad; and a first landing pad disposed directly above the first on-chip metal pad;', 'a first via in the RDL structure to electrically connect the first landing pad with the first on-chip metal pad;', 'a second landing pad disposed directly above the second on-chip metal pad;', 'a second via in the RDL structure to electrically connect the second landing pad with the second on-chip metal pad; and', 'at least three traces being disposed on the RDL structure and passing through a space between the first landing pad and the second landing pad., 'a redistribution layer (RDL) structure on the passivation layer, the RDL structure comprising2. The semiconductor device according to claim 1 , wherein the first on-chip metal pad is an aluminum pad.3. The semiconductor device according to claim 2 , wherein the second on-chip metal pad is an aluminum pad.4. The semiconductor device according to claim 1 , wherein the passivation layer comprises silicon oxide claim 1 , silicon nitride claim 1 , silicon oxynitride claim 1 , undoped silicon glass claim ...

Multi-metal contact structure

A first conductive material having a first hardness is disposed within a recess or opening of a microelectronic component, in a first preselected pattern, and forms a first portion of an interconnect structure. A second conductive material having a second hardness different from the first hardness is disposed within the recess or opening in a second preselected pattern and forms a second portion of the interconnect structure. 1. A microelectronic component comprising one or more semiconductor devices , the microelectronic component comprising:a substrate including a recess or opening extending from a first surface of the substrate, at least a portion of the first surface of the substrate having a planarized topography;a first conductive material having a first hardness, disposed within the recess or opening in a first preselected pattern and forming a first portion of an interconnect structure of the microelectronic component, the first portion of the interconnect structure extending normal to a plane of the substrate; anda second conductive material having a second hardness different from the first hardness, disposed within the recess or opening in a second preselected pattern and forming a second portion of the interconnect structure of the microelectronic component, the second portion of the interconnect structure extending normal to the plane of the substrate.2. The microelectronic component of claim 1 , further comprising a layer of the first conductive material disposed over an exposed surface of the second portion of the interconnect structure.3. The microelectronic component of claim 1 , further comprising a layer of a third conductive material claim 1 , different from the first and second conductive materials claim 1 , disposed over an exposed surface of the first and second portions of the interconnect structure.4. The microelectronic component of claim 1 , further comprising a conductive layer disposed at a preselected depth below the first surface of the ...

Efficient redistribution layer topology

In some examples, a chip scale package (CSP) comprises a semiconductor die; a passivation layer abutting the semiconductor die; a via extending through the passivation layer; and a first metal layer abutting the via. The CSP also includes an insulation layer abutting the first metal layer, with the insulation layer having an orifice with a maximal horizontal area of less than 32400 microns 2 . The CSP further includes a second metal layer abutting the insulation layer and adapted to couple to a solder ball. The second metal layer abuts the first metal layer at a point of contact defined by the orifice in the insulation layer.

METHODS OF FORMING MICROELECTRONIC STRUCTURES HAVING A PATTERNED SURFACE STRUCTURE

A connector structure and a manufacturing method thereof are provided. The connector structure includes a semiconductor substrate, a metal layer, a passivation layer, and a conductive structure. The metal layer is over the semiconductor substrate. The passivation layer is over the metal layer and includes an opening. The conductive structure is in contact with the metal layer in a patterned surface structure of the conductive structure through the opening of the passivation layer. 1. A method of forming a microelectronic structure , comprising:forming a metal material over a base material;forming a passivation material over the metal material;removing at least a portion of the passivation material to form a patterned surface structure in at least one opening in the passivation material;forming an under-bump metallurgy (UBM) material in the at least one opening in the passivation material, an outer periphery of the UBM material abutting the passivation material without overlapping portions of the passivation material external to the at least one opening therein; andforming a conductive structure comprising a solder material over the UBM material, the conductive structure being in contact with the metal material through the UBM material, wherein the conductive structure extends from the abutting portion of the UBM material with a maximum lateral extent of the conductive structure being the same or less than a maximum lateral extent of the UBM material.2. The method of claim 1 , further comprising forming a supporting portion in the at least one opening after removing the at least a portion of the passivation material and before forming the conductive structure.3. The method of claim 2 , wherein forming the supporting portion comprises forming the supporting portion of at least one inorganic material comprising one or more of silicon dioxide claim 2 , silicon nitride claim 2 , titanium dioxide claim 2 , aluminum oxide claim 2 , or at least one organic material ...

SEMICONDUCTOR PACKAGE STRUCTURE

Semiconductor package structures are provided. A semiconductor package structure includes a chip, a molding material surrounding the chip, a through-via extending from a first surface to a second surface of the molding material, and a first re-distribution layer (RDL) wire disposed on the second surface of the molding material and electrically separated from the through-via. The second surface is opposite to the first surface. A portion of the first RDL wire across the through-via has a first segment with a first width and a second segment with a second width different from the first width. 1. A semiconductor package structure , comprising:a chip;a molding material surrounding the chip;a through-via extending from a first surface to a second surface of the molding material, wherein the second surface is opposite to the first surface; anda first re-distribution layer (RDL) wire disposed on the second surface of the molding material and electrically separated from the through-via,wherein a portion of the first RDL wire across the through-via has a first segment with a first width and a second segment with a second width different from the first width.2. The semiconductor package structure as claimed in claim 1 , wherein the first width of the first segment of the first RDL wire on a boundary between the through-via and the molding material is greater than the second width of the second segment of the first RDL wire on the through-via.3. The semiconductor package structure as claimed in claim 1 , wherein the first RDL wire has a connecting pattern on a boundary between the through-via and the molding material claim 1 , and a center of the connecting pattern is centered on an edge of the through-via.4. The semiconductor package structure as claimed in claim 3 , wherein the connecting pattern comprises a main portion having a circular shape claim 3 , a regular polygonal shape claim 3 , an ellipse shape or an oval shape.5. The semiconductor package structure as claimed in ...

Contact Pad For Semiconductor Device

A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound.

METAL PAD MODIFICATION

The present invention provides a structure. In an exemplary embodiment, the structure includes a base material, at least one metal pad, where a first surface of the metal pad is in contact with the base material, and a metal pedestal, where the metal pedestal is in contact with the metal pad, where a radial alignment of the metal pad is shifted by an offset distance, with respect to the metal pedestal, such that the metal pad is shifted towards a center axis of the base material, where a first dimension of the metal pad is smaller than a second dimension of the metal pad, where the second dimension is orthogonal to a line running from a center of the metal pad to the center axis of the base material, where the first dimension is parallel to the line. 1. A structure comprising:a base material; 'wherein a first surface of the metal pad is in contact with a surface of the base material;', 'at least one metal pad,'} wherein a first surface of the metal pedestal is in contact with a second surface of the metal pad,', 'wherein a first dimension of the metal pad is smaller than a second dimension of the metal pad; and, 'a metal pedestal;'}a solder bump in contact with a second surface of the metal pedestal.2. The structure of claim 1 , wherein the metal pad has a cross sectional shape selected from the group consisting of rounded rectangle claim 1 , elliptical claim 1 , and oblong.3. The structure of further comprising: wherein the metal pedestal contacts the metal pad through the via in the passivation layer; and', 'wherein the metal pedestal is deposited on the passivation layer and the second surface of the metal pad., 'a passivation layer between the metal pedestal and the metal pad with a via in the passivation layer,'}4. The structure of claim 3 , wherein the passivation layer has a thickness ranging from 0 μm to 20 μm. The present disclosure relates to integrated circuit chips, and more specifically, to metal pad modification.The present invention provides a ...

Interconnect Crack Arrestor Structure and Methods

A system and method for preventing cracks is provided. An embodiment comprises placing crack stoppers into a connection between a semiconductor die and a substrate. The crack stoppers may be in the shape of hollow or solid cylinders and may be placed so as to prevent any cracks from propagating through the crack stoppers. 1. A semiconductor device comprising:a conductive pad on a substrate; anda first crack stopper extending from the conductive pad, the first crack stopper comprising a hollow tube, the first crack stopper located along an exterior region of the conductive pad; anda first conductive material surrounding the first crack stopper.2. The semiconductor device of claim 1 , wherein the wire comprises a cylindrical shape.3. The semiconductor device of claim 1 , wherein the conductive region is an underbump metallization.4. The semiconductor device of claim 1 , wherein the first crack stopper has an outer diameter between 15 microns and 60 microns.5. The semiconductor device of claim 1 , wherein the first crack stopper has an inner diameter between 5 microns and 20 microns.6. The semiconductor device of claim 1 , wherein the first crack stopper comprises one or more additional hollow tubes claim 1 , wherein each of the hollow tubes of the first crack stopper are spaced equidistant from each other along the exterior region of the conductive pad.7. The semiconductor device of claim 1 , wherein the first crack stopper comprises an additional hollow tube claim 1 , the additional hollow tube disposed at a center of the conductive pad.8. The semiconductor device of claim 1 , wherein the first conductive material is coupled to a second conductive pad on a second substrate.9. The semiconductor device of claim 8 , wherein the first conductive material is electrically coupled to a second crack stopper disposed on the second conductive pad.10. A semiconductor device comprising:a conductive pad on a substrate; anda first crack stopper extending from the conductive pad, ...

BUMP ON PAD (BOP) BONDING STRUCTURE IN SEMICONDUCTOR PACKAGED DEVICE

The embodiments described above provide enlarged overlapping surface areas of bonding structures between a package and a bonding substrate. By using elongated bonding structures on either the package and/or the bonding substrate and by orienting such bonding structures, the bonding structures are designed to withstand bonding stress caused by thermal cycling to reduce cold joints. 1. A package structure comprising:an integrated circuit package comprising a conductive post, the conductive post having a first plan-view shape; a first dielectric layer;', 'a first contact pad over the first dielectric layer, a bottom surface of the first contact pad being in physical contact with a topmost surface of the first dielectric layer, the first contact pad having a second plan-view shape, a line extending through a first center of the first plan-view shape and a second center of the second plan-view shape intersecting the first contact pad at an angle having less than 90 degrees, at least one of the first plan-view shape and the second plan-view shape being a racetrack shape; and', 'a second dielectric layer over the first contact pad and the first dielectric layer, the second dielectric layer being in physical contact with the topmost surface of the first dielectric layer; and, 'a substrate bonded to the integrated circuit package, the substrate comprisinga solder layer extending through the second dielectric layer, the solder layer electrically and mechanically coupling the conductive post to the first contact pad.2. The package structure of claim 1 , wherein a long axis of the racetrack shape is oriented toward a center of the integrated circuit package.3. The package structure of claim 1 , wherein the integrated circuit package further comprises:a second contact pad; andan under bump metallurgy (UBM) interposed between the second contact pad and the conductive post.4. The package structure of claim 1 , wherein a coefficient of thermal expansion (CTE) of the integrated ...

CONNECTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A connector structure and a manufacturing method thereof are provided. The connector structure includes a semiconductor substrate, a metal layer, a passivation layer, and a conductive structure. The metal layer is over the semiconductor substrate. The passivation layer is over the metal layer and includes an opening. The conductive structure is contacted with the metal layer in a patterned surface structure of the conductive structure through the opening of the passivation layer. 1. A connector structure , comprising:a semiconductor substrate;a metal layer over the semiconductor substrate;a passivation layer over the metal layer and comprising an opening; anda conductive structure contacted with the metal layer in a patterned surface structure of the conductive structure through the opening of the passivation layer.2. The connector structure of claim 1 , wherein the conductive structure comprises a bump or a soldering ball.3. The connector structure of claim 1 , wherein the patterned surface structure of the conductive structure comprises a metal portion and a supporting portion.4. The connector structure of claim 1 , further comprising an under-bump metallurgy (UBM) layer disposed between the metal layer and the conductive structure.5. The connector structure of claim 3 , wherein the supporting portion of the patterned surface structure is a mesh claim 3 , regularly aligned pillars claim 3 , or a concentric cylinder.6. The connector structure of claim 5 , wherein the pillars have a cross section comprising a polygon claim 5 , a circle or an oval.7. The connector structure of claim 3 , wherein the supporting portion of the patterned surface structure is made of at least one inorganic material such as silicon dioxide claim 3 , silicon nitride claim 3 , titanium dioxide claim 3 , aluminum oxide claim 3 , or at least one organic material such as polyimide claim 3 , polybenzoxazole (PBO) claim 3 , or a combination thereof.8. The connector structure of claim 3 , wherein ...

SEMICONDUCTOR DEVICE

An object of the present invention is to provide a semiconductor device capable of eliminating unevenness of current distribution in a plane. A semiconductor device according to the present invention is a semiconductor device including a transistor cell region where a plurality of transistor cells is arranged on a semiconductor substrate, the semiconductor device including an electrode pad which is arranged avoiding the transistor cell region on the semiconductor substrate and is electrically connected to a one-side current electrode of each of the cells, in which the transistor cell region contains a plurality of regions each of which has a different current drive capability from each other depending on a distance from the electrode pad. 1. A semiconductor device including a transistor cell region where a plurality of transistor cells is arranged on a semiconductor substrate ,said semiconductor device comprising an electrode pad which is arranged avoiding said transistor cell region on said semiconductor substrate and is electrically connected to a one-side current electrode of each of said cells, whereinsaid transistor cell region contains a plurality of regions, each of which has a different current drive capability from each other depending on a distance from said electrode pad.2. The semiconductor device according to claim 1 , whereinsaid electrode pad has a circular shape, an elliptical shape, or a polygonal shape having at least five or more vertices.3. The semiconductor device according to claim 1 , whereinat least part of said cells includes, in addition to said one-side current electrode, a current detection electrode having a smaller area than that of said one-side current electrode.4. The semiconductor device according to claim 1 , further comprising a temperature detection diode which detects a temperature of said semiconductor device.5. The semiconductor device according to claim 4 , whereinan anode of said temperature detection diode is connected to ...

BONDING PADS WITH THERMAL PATHWAYS

Apparatuses and methods for providing thermal pathways from a substrate to a thermal bonding pad. The thermal pathways may be metal extensions of the thermal bonding pad that are disposed in channels formed in a backside passivation layer underneath the thermal bonding pad, and may be in direct contact with an underlying substrate. The thermal pathways may provide improved thermal dissipation from the substrate. 1. An apparatus , comprising:a substrate; anda first bonding pad including thermal pathways in direct contact with a backside of the substrate, wherein the thermal pathways are disposed in channels formed in a passivation layer on the backside of the substrate.2. The apparatus of claim 1 , wherein the thermal pathways are formed under the first bonding pad.3. The apparatus of claim 1 , wherein the thermal pathways are disposed in the channels formed in the passivation layer such that the thermal pathways form concentric circles or a spiral in the passivation layer.4. The apparatus of claim 1 , wherein the thermal pathways are disposed in the channels formed in the passivation layer such that the thermal pathways are distributed in parallel relative to each other and such that the thermal pathways extend along a length of the first bonding pad.5. The apparatus of claim 1 , wherein the substrate further includes a through-via extending from the backside of the substrate to a frontside of the substrate.6. The apparatus of claim 5 , further comprising a second bonding pad disposed on the passivation layer and coupled to the through-via.7. The apparatus of claim 6 , further comprising:an additional substrate including a frontside passivation layer; anda third bonding pad disposed on the frontside passivation layer.8. The apparatus of claim 7 , wherein the first and third bonding pad are configured to form a first bond to provide an electrical connection to an active region of the additional substrate.9. The apparatus of claim 7 , further comprising:a fourth ...

SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS

The present disclosure relates to a semiconductor device and an electronic apparatus which is capable of reducing variations and deterioration of transistor characteristics. 111-. (canceled)12. A semiconductor device comprising:a first substrate; and a first floating metal at a bonding surface between the first-substrate and the second substrate;', 'a first pad formed at the bonding surface and spaced apart from the first floating metal by part of the first substrate; and', 'a first wiring connected to the first pad,, 'a second substrate bonded to the first substrate, wherein the first substrate includes a second floating metal at the bonding surface;', 'a second pad formed at the bonding surface and spaced apart from the second floating metal by part of the second substrate; and', 'a second wiring connected to the second pad,, 'wherein the second substrate includeswherein the first pad is bonded to the second floating metal, the first floating metal is bonded to the second floating metal, and the second pad is bonded to the first floating metal,wherein, in a plan view, the first wiring overlaps the first floating metal and the first pad, andwherein, in the plan view, the second wiring overlaps the second floating metal and the second pad.13. The semiconductor device according to claim 12 , wherein claim 12 , in the plan view claim 12 , the second floating metal completely overlaps the first pad.14. The semiconductor device according to claim 13 , wherein claim 13 , in the plan view claim 13 , the first floating metal completely overlaps the second pad.15. The semiconductor device according to claim 12 , wherein the first floating metal is larger than the first pad.16. The semiconductor device according to claim 12 , wherein the second floating metal is larger than the second pad.17. The semiconductor device according to claim 12 , wherein the first floating metal and the first pad are formed in rectangular shapes at the bonding surface claim 12 , and the second ...

Multi-metal contact structure

A first conductive material having a first hardness is disposed within a recess or opening of a microelectronic component, in a first preselected pattern, and forms a first portion of an interconnect structure. A second conductive material having a second hardness different from the first hardness is disposed within the recess or opening in a second preselected pattern and forms a second portion of the interconnect structure.

Multi-metal contact structure in microelectronic component

A first conductive material having a first hardness is disposed within a recess or opening of a microelectronic component, in a first preselected pattern, and forms a first portion of an interconnect structure. A second conductive material having a second hardness different from the first hardness is disposed within the recess or opening in a second preselected pattern and forms a second portion of the interconnect structure.

CU PADS FOR REDUCED DISHING IN LOW TEMPERATURE ANNEALING AND BONDING

A device includes an array of light sources (e.g., micro-LEDs, micro-RCLEDs, micro-laser: micro-SLEDs, or micro-VCSELs), a dielectric layer on the array of light sources, and a set of metal bonding pads (e.g., copper bonding pads) in the dielectric layer. Each metal bonding pad of the set of metal bonding pads is electrically connected to a respective light source of the array of light sources. Each metal bonding pad of the set of metal bonding pads includes a first portion at a bonding surface and characterized by a first lateral cross-sectional area, and a second portion away from the bonding surface and characterized by a second lateral cross-sectional area larger than two times of the first lateral cross-sectional area. The device can be bonded to a backplane that includes a drive circuit through a low annealing temperature hybrid bonding. 1. A device comprising:an array of light sources;a dielectric layer on the array of light sources; and a bonding surface for bonding to a drive circuit;', 'a first portion at the bonding surface and characterized by a first lateral cross-sectional area; and', 'a second portion away from the bonding surface and electrically connected to a respective light source of the array of light sources, the second portion characterized by a second lateral cross-sectional area larger than 1.2 times of the first lateral cross-sectional area., 'a set of metal bonding pads in the dielectric layer, each metal bonding pad of the set of metal bonding pads including2. The device of claim 1 , wherein a pitch of the set of metal bonding pads is less than 10 μm claim 1 , less than 5 μm claim 1 , less than 3 μm claim 1 , or less than 2 μm.3. The device of claim 1 , wherein:each metal bonding pad of the set of metal bonding pads has a circular, elliptical, triangular, rectangular, quadrilateral, or another polygonal shape at the bonding surface; anda linear dimension of each metal bonding pad of the set of metal bonding pads at the bonding surface is ...

Contact Pad for Semiconductor Device

本发明提供了利用邻近接触焊盘的伪焊盘部件的器件及其制造方法。接触焊盘可以是集成的扇出封装件中的接触焊盘，在集成的扇出封装件中，模塑料沿着管芯的侧部放置并且接触焊盘在管芯和模塑料的上方延伸。接触焊盘使用一个或多个重分布层电连接至管芯。伪焊盘部件与接触焊盘电隔离。在一些实施例中，伪焊盘部件部分地环绕接触焊盘，并且位于模塑料的拐角区域中、管芯的中心区域中和/或管芯的边缘和模塑料之间的界面区域中。本发明涉及用于半导体器件的接触焊盘。

Attachment structure and manufacture method thereof

本发明公开了一种连接结构及其制造方法。该连接结构包含半导体基板、金属层、钝化层以及导电结构。金属层位于半导体基板的上方。钝化层位于金属层的上方，且包含一个开口。导电结构具有图案化表面结构，图案化表面结构通过钝化层的开口与金属层接触。借此，本发明的连接结构及其制造方法，其中连接结构的图案化表面结构，可改善在回焊期间的晶片翘曲，以避免晶片破裂并增加可靠性，还降低整体的翘曲级。

Method of electroplating photoresist defined features from copper electroplating baths containing reaction products of pyridyl alkylamines and bisepoxides

전기도금 방법은 실질적으로 균일한 형태를 갖는 포토레지스트 한정된 피쳐의 도금을 가능하게 한다. 상기 전기도금 방법은 포토레지스트 한정된 피쳐를 전기도금하기 위해 피리딜 알킬아민과 비스에폭사이드의 반응 생성물을 포함하는 구리 전기도금조를 포함한다. 그와 같은 피쳐는 필러, 결합 패드 및 라인 공간 피쳐를 포함한다. The electroplating process enables the plating of photoresist-defined features having a substantially uniform shape. The electroplating process includes a copper electroplating bath comprising a reaction product of a pyridyl alkylamine and bis epoxide to electroplating a photoresist-limited feature. Such features include fillers, bond pads, and line space features.

Semiconductor Device and Manufacturing Method Thereof

본 발명에서는 재배선층 중 UBM이 형성되는 접속 영역 및 접속 영역을 제외한 다른 영역의 너비를 모두 동일하게 형성함으로써, 재배선층 경로 설계시 공간의 확보가 용이한 반도체 디바이스 및 그 제조 방법이 개시된다. 일 예로, 다수의 본드 패드가 형성된 반도체 다이; 상기 반도체 다이의 상부에 형성되며 일단부가 상기 본드 패드와 전기적으로 연결되는 재배선층; 상기 재배선층의 타단부에 형성되며 상기 재배선층과 전기적으로 연결되는 UBM; 및 상기 UBM과 접속하는 범프를 포함하고, 상기 재배선층은 상기 UBM이 형성되는 접속 영역 및 상기 접속 영역을 제외한 다른 영역의 너비가 동일하게 형성되는 반도체 디바이스가 개시된다. The present invention discloses a semiconductor device and a manufacturing method thereof, in which space is easily secured in designing a rewiring layer path by forming the same widths of regions other than the connection region and the connection region where the UBMs are formed in the rewiring layer. As an example, a semiconductor die having a plurality of bond pads formed therein; A re-wiring layer formed on the semiconductor die and having one end electrically connected to the bond pad; A UBM formed at the other end of the re-distribution layer and electrically connected to the re-distribution layer; And a bump connected to the UBM, wherein the re-wiring layer is formed such that the connection area where the UBM is formed and the other area except the connection area are formed to have the same width.

Semiconductor device with a plurality of transistors

公开了一种半导体器件，所述半导体器件包括：导电图案，所述导电图案位于基板上；钝化层，所述钝化层位于所述基板上并包括部分地暴露所述导电图案的开口；以及焊盘结构，所述焊盘结构设置在所述钝化层上以及所述钝化层的所述开口中并连接到所述导电图案。所述焊盘结构包括填充所述钝化层的所述开口且宽度大于所述开口的宽度的第一金属层和位于所述第一金属层上的第二金属层。所述第一金属层在所述第一金属层的外壁处具有第一厚度，在所述钝化层的顶表面上具有第二厚度以及在所述导电图案的顶表面上具有第三厚度。所述第二厚度大于所述第一厚度，并且所述第三厚度大于所述第二厚度。

Rigid wave pattern design on chip carrier substrate and printed circuit board for semiconductor and electronic sub-system packaging

강체 웨이브 패턴이 반도체 다이 패키지에서의 기판의 제 1 사이드에 형성된다. 이 강체 웨이브 패턴은 기판의 제 2 사이드에 형성된 콘택 핑거들에 맞추어 정렬되고 이 콘택 핑거들의 위에 놓인다. 이 기판과 다이스는 몰딩 공정 동안 케이싱되고, 이 강체 웨이브 패턴은 다이 상의 응력 및 다이의 변형을 효과적으로 감소시키며, 그 결과 다이 크래킹을 실질적으로 경감시킨다. 강체 웨이브 패턴, 다이 패키지, 콘택 핑거, 응력, 다이 크래킹

Device package and methods of forming same

디바이스 패키지는, 다이; 상기 다이 위의 팬아웃 재분배 층(redistribution layers; RDLs); 상기 팬아웃 재분배 층 위에 있고 도전성 패드부 및 상기 도전성 패드부를 둘러싸는 트렌치를 포함하는 언더 범프 금속(UBM); 그리고 상기 언더 범프 금속의 상기 도전성 패드부에 배치된 커넥터를 포함하며, 상기 팬아웃 재분배 층은 상기 커넥터 및 상기 언더 범프 금속을 상기 다이에 전기적으로 연결하는 것을 특징으로 한다. The device package includes a die; Fanout redistribution layers (RDLs) on the die; An under bump metal (UBM) over the fanout redistribution layer and including a conductive pad portion and a trench surrounding the conductive pad portion; And a connector disposed on the conductive pad portion of the under bump metal, the fan out redistribution layer electrically connecting the connector and the under bump metal to the die.

Power semiconductor device

パワー半導体装置１００において、パワー半導体素子４の表面電極４１ａは、ビッカース硬度が２００〜３５０ＨｖのＣｕを主成分とする無電解めっきで形成されたＣｕ層８１上に、Ｃｕ層８１より柔らかいビッカース硬度が７０〜１５０ＨｖのＣｕを主成分とする無電解めっきで形成されたＣｕ層８２が積層して設けられ、Ｃｕ層８２とＣｕ製のワイヤ６とをワイヤボンディングする。 In the power semiconductor device 100, the surface electrode 41 a of the power semiconductor element 4 has a softer Vickers hardness than the Cu layer 81 on the Cu layer 81 formed by electroless plating whose main component is Cu having a Vickers hardness of 200 to 350 Hv. A Cu layer 82 formed by electroless plating containing 70 to 150 Hv of Cu as a main component is provided in a laminated manner, and the Cu layer 82 and the Cu wire 6 are wire-bonded.

Bump on pad (BOP) bonding structure in semiconductor packaged device

The embodiments described above provide enlarged overlapping surface areas of bonding structures between a package and a bonding substrate. By using elongated bonding structures on either the package and/or the bonding substrate and by orienting such bonding structures, the bonding structures are designed to withstand bonding stress caused by thermal cycling to reduce cold joints.

Structures, architectures, systems, methods, algorithms and software for configuring an integrated circuit for multiple packaging types

Structures, architectures, systems, an integrated circuit, methods and software for configuring an integrated circuit for multiple packaging types and/or selecting a packaging type for an integrated circuit. A structure generally includes a bump pad having a plurality of electrically disconnected bump pad sections, a plurality of bond pads each configured for electrical connection to one of the bump pad sections, and a plurality of conductive traces, each adapted to electrically connect one of the bond pads to the one bump pad section. A method generally includes the steps of forming the bump pad, the bond pads, and the conductive traces from an uppermost metal layer, and forming an insulation layer thereover. Another method generally includes forming the uppermost metal layer, and forming either a wire bond to at least one of the bond pads, or a ball bond or solder ball to electrically connect the bump pad section.

Structures, architectures, systems, methods, algorithms and software for configuring an integrated circuit for multiple packaging types

Structures, architectures, systems, an integrated circuit, methods and software for configuring an integrated circuit for multiple packaging types and/or selecting one of a plurality of packaging types for an integrated circuit. The structure generally comprises a bump pad, a plurality of bond pads configured for independent electrical connection to the bump pad, and a plurality of conductive traces, each adapted to electrically connect one of the bond pads to the bump pad. The software is generally configured to place and route components of such a structure. The method of configuring generally includes the steps of forming the bump pad, the bond pads, and the conductive traces from an uppermost metal layer, and forming an insulation layer thereover. The method of selecting generally comprises the uppermost metal layer-forming step, and forming either (i) a wire bond to at least one of the bond pads, or (ii) a bumping metal configured to electrically connect at least one of the bond pads to the bump pad. The present invention advantageously provides reduced manufacturing costs and reduced inventory management issues by enabling one device to be manufactured at a wafer level for a plurality of different packaging options, thereby enabling packaging decisions to be made at a later time in the manufacturing process.

Bonding pads with thermal pathways

Apparatuses and methods for providing thermal pathways from a substrate to a thermal bonding pad. The thermal pathways may be metal extensions of the thermal bonding pad that are disposed in channels formed in a backside passivation layer underneath the thermal bonding pad, and may be in direct contact with an underlying substrate. The thermal pathways may provide improved thermal dissipation from the substrate.

Semiconductor device and method of manufacturing the same

A semiconductor device is provided. The semiconductor device includes an electrode pad provided above a semiconductor substrate; and a wire bonded on the electrode pad and including copper. The electrode pad includes an electrode layer including aluminum and a support layer harder than the wire and the electrode layer. The wire is in contact with the electrode layer and the support layer.

Semiconductor device

第１の半導体チップ（１００）と第２の半導体チップ（２００）とが接合された積層チップを有する半導体装置である。第１の半導体チップの主面上には、第１の電極パッド（１１０）と、第１の電極パッドの上に形成された第１のバンプ（１２０）とが形成されている。第２の半導体チップ（２００）の主面上には、第１のバンプと接合するように第２のバンプ（２２０）が形成されている。第１の電極パッド（１１０）は、中央に段差状となる開口部を有している。第１のバンプ（１２０）は、第１の電極パッド（１１０）における開口部とその周辺部との段差状に跨るように形成された中央が窪んだ凹状を有する。 A semiconductor device having a laminated chip in which a first semiconductor chip (100) and a second semiconductor chip (200) are joined. On the main surface of the first semiconductor chip, a first electrode pad (110) and a first bump (120) formed on the first electrode pad are formed. On the main surface of the second semiconductor chip (200), second bumps (220) are formed so as to be joined to the first bumps. The first electrode pad (110) has an opening having a step shape at the center. The first bump (120) has a concave shape in which the center is formed so as to straddle the step shape between the opening and the peripheral portion of the first electrode pad (110).

Bond pad design for improved routing and reduced package stress

A bond pad design comprises a plurality of bond pads on a semiconductor chip and a plurality of under-bump metallurgy (UBM) layers formed on respective bond pads of the plurality. At least one of the bond pads has an elongated shape having an elongated portion and a contracted portion, the elongated portion oriented substantially along a stress direction radiating from a center to the periphery of the chip.

Chip Scale Package With Flexible Interconnect

一种芯片尺寸封装及其制造方法。芯片尺寸封装包括基片、挠性互连结构和粘结结构。基片在主表面处具有接触垫。挠性互连结构包括：在基片的主表面上的第一介电层；第一通路，电气接触接触垫并从接触垫延伸至第一介电层的第一上部主表面；平面金属弹簧，该弹簧位于第一上部主表面上，且在该弹簧的第一端处电气接触第一通路；第二介电层和第二通路，第二介电层位于第一介电层的顶部上并覆盖该弹簧，第二通路电气接触该弹簧的第二端，并从该弹簧延伸至第二介电层的第二上部主表面；位于第二上部主表面上的第二金属，电气接触第二通路。位于挠性互连结构顶部上的粘结结构电气接触第二金属。挠性互连结构的第一和第二介电层具有低于200MPa的弹性模量。

Contact Pad for Semiconductor Device

A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound.

Structure and method for sealing cavity of micro-electro-mechanical device

A cavity package ( 100 ) for micrometer-scale MEMS devices surrounding the cavity ( 210 ) with the MEMS device ( 220 ) with a rim ( 232 ) of solder-wettable metal, and then covering the cavity with a roof ( 240 ) of solder spanning from rim to rim. A solder body, placed over the cavity to rest on the rim, is reflowed; the surface tension of the liquid solder is reduced by the interfacial tension of the rim metal so that the liquid solder spreads over the rim surface and thereby stretches the liquid ball to a plate-like roof over the cavity. After solidifying the solder, the solder-to-metal seal renders the cavity package hermetic.

Chip scale package with flexible interconnect

A chip scale package and a method for fabrication thereof. The chip scale package 100 comprises a substrate 1 with a contact pad 2 at a first main surface 3, a flexible interconnect structure 45 and a bonding structure 10. The flexible interconnect structure 45 comprises a first dielectric layer 4 on top of the first main surface 3 of the substrate 1. A first via 5 electrically contacts the contact pad 2. The first via 5 extends from the contact pad 3 through the first dielectric layer 4 to a first planar upper main surface 11 of the first dielectric layer 4. The flexible interconnect structure 45 further comprises a planar metal spring 6 on top of the first planar upper main surface 11 electrically contacts the first via 5, at a first end 12 of the planar metal spring 6. The flexible interconnect structure 45 further comprises a second dielectric layer 7 on top of the first dielectric layer 4, and a second via 8 electrically contacts the planar metal spring 6, at a second end 13 of the planar metal spring 6. The second dielectric layer 7 covers the planar metal spring 6. The second via 8 extends from the planar metal spring 6 through the second dielectric layer 7 to a second planar upper main surface 14 of the second dielectric layer 7. The flexible interconnect structure 45 further comprises a second metal 9 on top of the second planar upper main surface 14. The second metal 9 electrically contacts the second via 8. A bonding structure 10 on top of the flexible interconnect structure 45, electrically contacts the second metal 9. The first and second dielectric layers 4,7 of the flexible interconnect structure 45 have an elastic modulus below 200MPa.

Barrier Structures Between External Electrical Connectors

A structure includes a die substrate; a passivation layer on the die substrate; first and second interconnect structures on the passivation layer; and a barrier on the passivation layer, at least one of the first or second interconnect structures, or a combination thereof. The first and second interconnect structures comprise first and second via portions through the passivation layer to first and second conductive features of the die substrate, respectively. The first and second interconnect structures further comprise first and second pads, respectively, and first and second transition elements on a surface of the passivation layer between the first and second via portion and the first and second pad, respectively. The barrier is disposed between the first pad and the second pad. The barrier does not fully encircle at least one of the first pad or the second pad.

Rigid wave pattern design on chip carrier substrate and printed circuit board for semiconductor and electronic sub-system packaging

在半导体小片封装中衬底的第一侧上形成硬波图案。所述硬波图案与形成在所述衬底的第二侧上的接触指对准并覆在其上面。当在模制过程期间包装所述衬底和小片时，所述硬波图案有效地减少所述小片的变形和所述小片上的应力，因此实质上减轻小片断裂。

For improving the bond pad designs of wiring and reduction encapsulation stress

接合焊盘设计包括：多个接合焊盘，位于半导体芯片上方；和多个凸块下金属(UBM)层，形成在多个接合焊盘的相应接合焊盘的上方。接合焊盘中的至少一个具有包括伸长部和收缩部的伸长形状，伸长部大体上沿着从芯片的中心辐射到外围的应力方向定向。本发明公开了用于改善布线和减小封装应力的接合焊盘设计。

Barrier structures between external electrical connectors

A structure includes a die substrate; a passivation layer on the die substrate; first and second interconnect structures on the passivation layer; and a barrier on the passivation layer, at least one of the first or second interconnect structures, or a combination thereof. The first and second interconnect structures comprise first and second via portions through the passivation layer to first and second conductive features of the die substrate, respectively. The first and second interconnect structures further comprise first and second pads, respectively, and first and second transition elements on a surface of the passivation layer between the first and second via portion and the first and second pad, respectively. The barrier is disposed between the first pad and the second pad. The barrier does not fully encircle at least one of the first pad or the second pad.

Contact pad for semiconductor device

A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated fan-out package in which a molding compound is placed along sidewalls of a die and the contact pads extend over the die and the molding compound. The contact pads are electrically coupled to the die using one or more redistribution layers. The dummy pad features are electrically isolated from the contact pads. In some embodiments, the dummy pad features partially encircle the contact pads and are located in a corner region of the molding compound, a corner region of the die, and/or an interface region between an edge of the die and the molding compound.

Semiconductor device

반도체 장치가 제공된다. 반도체 장치는 기판, 기판 상에 배치되는 보호막으로, 보호막을 관통하는 트렌치를 포함하는 보호막, 트렌치의 적어도 일부를 채우는 제1 부분과, 보호막 상에 배치되는 제2 부분을 포함하는 하부 범프 및 하부 범프 상에 배치되는 상부 범프를 포함하고, 보호막은, 트렌치의 측벽을 포함하는 제1 부분 및 제2 부분을 포함하고, 기판의 상면으로부터 상기 보호막의 제1 부분의 상면까지의 제1 높이는, 기판의 상면으로부터 상기 보호막의 제2 부분의 상면까지의 제2 높이보다 크다.

Method for manufacturing semiconductor structure

A method of manufacturing a semiconductor structure include: providing a die including a die pad disposed over the die; disposing a conductive member over the die pad of the die; forming a molding surrounding the die and the conductive member; disposing a dielectric layer over the molding, the die and the conductive member; and forming an interconnect structure including a land portion and a plurality of via portions. The land portion is disposed over the dielectric layer, the plurality of via portions are disposed over the conductive member and protruded from the land portion to the conductive member through the dielectric layer, and each of the plurality of via portions at least partially contacts with the conductive member.

Semiconductor package

본 발명의 기술적 사상에 의한 반도체 패키지는, 반도체 기판, 반도체 기판 상에 형성되며 중심부 및 주변부를 포함하고 주변부에 제1 패턴을 갖는 전극 패드, 반도체 기판 및 전극 패드 상에 형성되며, 전극 패드의 중심부를 노출하는 개구부 및 제1 패턴 상에 제2 패턴을 갖는 패시베이션막, 전극 패드 및 패시베이션막 상에 형성되며 제2 패턴 상에 제3 패턴을 갖는 시드층, 및 시드층 상에 형성되며 전극 패드와 전기적으로 연결되는 범프를 포함하고, 범프 하부의 가장자리 아래의 제3 패턴 주위에 언더컷이 형성되어 있는 것을 특징으로 한다.