УСТРОЙСТВО С ПЕРЕХОДНЫМИ ОТВЕРСТИЯМИ В ПОДЛОЖКЕ И СПОСОБ ЕГО ПРОИЗВОДСТВА

Изобретение относится к устройству (10) с переходными отверстиями в подложке, содержащему подложку (12), выполненную из материала подложки и имеющую первую поверхность (12а) подложки и вторую поверхность (12b) подложки, противоположную первой поверхности (12а) подложки. Устройство (10) с переходными отверстиями в подложке также содержит множество соседних первых канавок (14), обеспеченных проводящим материалом и проходящих с первой поверхности (12а) подложки внутрь подложки (12), так что между первыми канавками (14) формируется множество спейсеров (16) из материала подложки. Устройство (10) с переходными отверстиями в подложке также содержит вторую канавку (18), обеспеченную проводящим материалом и проходящую со второй поверхности (12b) подложки внутрь подложки (12). Вторая канавка (18) соединена с первыми канавками (14). Устройство 10 с переходными отверстиями в подложке также содержит проводящий слой (20), выполненный из проводящего материала и сформированный на стороне первой поверхности ...

ELEKTRONISCHES BAUELEMENTGEHÄUSE

Die Technologie eines elektronischen Bauelementgehäuses ist offenbart. Ein elektronisches Bauelementgehäuse gemäß der vorliegenden Offenbarung kann ein Gehäusesubstrat, eine elektronische Komponente, eine Formmasse, die die elektronische Komponente einkapselt, und eine Redistributionsschicht umfassen, die derart angeordnet ist, dass die Formmasse zwischen dem Gehäusesubstrat und der Redistributionsschicht ist. Die Redistributionsschicht und das Gehäusesubstrat können elektrisch gekoppelt sein. Außerdem können die Redistributionsschicht und die elektronische Komponente elektrisch gekoppelt sein, um die elektronische Komponente und das Gehäusesubstrat elektrisch zu koppeln. Zugeordnete Systeme und Verfahren sind auch offenbart.

Verpackungsstruktur für elektronische Bauteile und Methode zu deren Herstellung

HALBLEITERGEHÄUSE, HALBLEITERVORRICHTUNG, ELEKTRONIKELEMENT UND HERSTELLUNG EINES HALBLEITERGEHÄUSES

Verfahren zum Herstellen eines Halbleiterbauelements

Es wird ein Verfahren zum Herstellen eines Halbleiterbauelements (100) offenbart. Eine Ausführungsform stellt einen Träger (10) bereit. Halbleiterchips (11, 12) werden über dem Träger (10) platziert. Die Halbleiterchips (11, 12) enthalten Kontaktelemente (13). Ein Polymermaterial (15) wird über den Halbleiterchips (11, 12) und dem Träger (10) aufgebracht. Das Polymermaterial (15) wird entfernt, bis die Kontaktelemente (13) exponiert sind. Der Träger (10) wird von den Halbleiterchips (11, 12) entfernt.

Method of producing an electrical connection to a surface of an electronic device

... 1,100,718. Semi-conductor devices; printed circuits. HUGHES AIRCRAFT CO. 4 Feb.. 1966 [1 March, 1965], No. 5010/66. Headings H1K and HIR. In a semi-conductor device having an electrode contacting the semi-conductor body through an aperture in an insulating layer, part of the electrode is thickened by masking and electroplating. A plurality of transistors simultaneously produced in a silicon wafer (4) by the planar technique, and having a glass or silicon oxide layer (10) which may be thickened by pyrolytic decomposition, are contacted by etching base and emitter contact windows in layer (10), vapour depositing a silver layer over the surfaces, and masking and etching to form the required electrode pattern which includes pads (15, 16) overlying layer (10) and connected by strips (12, 14) to base and emitter contact areas (81, 91) respectively, Fig. 4 (not shown). The masking layer is removed and a thin silver layer (17) is vapour deposited over the whole surface, Fig. 6 ...

ELECTRONIC CIRCUIT DEVICE AND PORDUCTION METHOD THEREFOR

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device provided with: a semiconductor element forming an integrated circuit; a plurality of electrode pads formed on the integrating circuit forming surface side of the semiconductor element; bump electrodes for external units electrically connected to the electrode pads through conductive layers; and a stress relieving layer which is formed between the integrated circuit forming surface and electrode pads and between the bump electrodes and the conductive layers, is bonded to the surface, pads, electrodes, and layers, is cut off by at least l/3 from its surface, and is divided into a plurality of areas. The semiconductor device is highly reliable, and can be mounted at a high packing density and at a low cost.

Integrierte Festkörperschaltung mit lediglich zwei Elektrodenzuleitungen

Semiconductor device and semiconductor package comprising the same

Electronic package and fabrication method thereof

Ultraviolet semiconductor sensor device and method of measuring ultraviolet radiation

Semiconductor device and manufacturing method thereof

Ultraviolet semiconductor sensor device and measuring the ultraviolet radiation of the method

ASSEMBLING AN INTEGRATED CIRCUIT DIE AND A PLATE

METHOD FOR MAKING AN ELECTRICAL INTERCONNECT LEVEL

Electronic component e.g. microelectromechanical system type component, for use in e.g. three-dimensional heterogeneous electronic device, has conductor via comprising hollow space that forms fluid circulation zone extending between ends

Composant électronique (100) comportant au moins un via conducteur (106) réalisé dans au moins un substrat (101), dans lequel le via conducteur s'étend entre une première extrémité (105) qui forme une ouverture débouchant au niveau d'une face (104) du substrat et une seconde extrémité (107), le via conducteur comportant en outre au moins une portion de matériau électriquement conducteur (110) s'étendant depuis la première extrémité jusqu'à la seconde extrémité et au moins un espace vide (114) apte à former une zone de circulation d'un fluide s'étendant depuis la première extrémité jusqu'à la seconde extrémité ...

반도체 디바이스 및 제조 방법

... 반도체 디바이스 및 제조 방법이 제공된다. 리플로우 가능 물질이 관통 비아와 전기 접속하고, 관통 비아는 봉지재를 통해 연장된다. 보호층이 리플로우 가능 물질 위에 형성된다. 실시예에서, 개구부는 리플로우 가능 물질을 노출하기 위해 보호층 내에 형성된다. 다른 실시예에서, 보호층은 리플로우 가능 물질이 보호층으로부터 멀리 연장되도록 형성된다.

Semiconductor integrated circuit device and its manufacturing method

마주보는（ＦＡＣＥ­ＴＯ­ＦＡＣＥ, Ｆ2Ｆ） 하이브리드 구조를 갖는 집적 회로(ＩＣ), ＩＣ 조립체, ＩＣ 제품 및 이들을 제조하는 방법, 그리고 이를 위한 컴퓨터-판독가능 매체

... 재분배 층(RDL)을 포함하는 집적 회로(IC) 제품이 제공되며, 재분배 층(RDL)은 IC 내에서 전기적 정보를 하나의 위치로부터 또 하나의 위치로 분배하도록 구성된 적어도 하나의 전도성 층을 갖는다. RDL은 또한 복수의 와이어 본드 패드들 및 복수의 솔더 패드들을 포함한다. 복수의 솔더 패드들 각각은 RDL과 직접적으로 전기적 통신을 하는 솔더 가용성 물질을 포함한다.

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING INSULATION FILM FORMED ON REAR SURFACE OF SEMICONDUCTOR SUBSTRATE AS MASK WHEN PAD ELECTRODE IS EXPOSED

PURPOSE: A method for manufacturing a semiconductor device is provided to securely contact an electrode inside a via hole with a semiconductor substrate by exposing a pad electrode by selectively removing an insulation film at a bottom portion inside the via hole. CONSTITUTION: A first insulation film(12) is applied on a semiconductor substrate. A pad electrode(11) is formed on the semiconductor substrate. A via hole, which penetrates a surface of the semiconductor substrate from a position corresponding to a pad electrode at a rear surface of the semiconductor substrate, is formed. The first insulation film, which is exposed from a bottom portion of the via hole, is etched away. A second insulation film(17) is formed on the rear surface of the semiconductor substrate. A metal layer(20) is formed on the second insulation film except for the via hole. The second insulation film is etched by using the metal layer as a mask, such that the pad electrode is exposed. The metal layer is removed ...

SEMICONDUCTOR DEVICE USING ENHANCED ARRANGEMENT OF METAL LINE LAYER AND REFLECTIVE COATING CAPABLE OF PREVENTING CONDUCTIVE TERMINAL FROM BEING CONTAINED IN OUTPUT IMAGE

PURPOSE: A semiconductor device is provided to prevent a metal line layer from being contained in an output image by using an improved arrangement of the metal line layer and a reflective coating. CONSTITUTION: A semiconductor device includes a semiconductor substrate(2) having a light receiving element(1), a light transmitting substrate(6) attached to the substrate on the light receiving element, a metal line layer(10) formed on a rear surface of the substrate, and a reflective coating. The reflective coating(8) is formed between the light receiving element and the metal line layer to reflect the infrared ray supplied to the metal line layer from the light transmitting substrate through the substrate. The reflective coating is completely overlapped with the light receiving element forming region. The metal line layer is formed along a lateral portion of the substrate. © KIPO 2007 ...

DIRECTLY SAWING WAFERS COVERED WITH LIQUID MOLDING COMPOUND

정전기 방전 다이오드

... 방법은 기판에 형성되는 제 1 비아의 일 부분을 노출시키기 위해 기판의 이면을 씨닝하는 단계를 포함한다. 방법은 또한 기판의 이면에 제 1 다이오드를 형성하는 단계를 포함한다. 제 1 다이오드는 제 1 비아에 결합된다.

LATCH-UP SUPPRESSION AND SUBSTRATE NOISE COUPLING REDUCTION THROUGH A SUBSTRATE BACK-TIE FOR 3D INTEGRATED CIRCUITS

Chip package and method for forming the same

An embodiment of the invention provides a chip package which includes: a first substrate; a second substrate disposed on the first substrate, wherein the second substrate includes a lower semiconductor layer, an upper semiconductor layer, and an insulating layer therebetween, and a portion of the lower semiconductor layer electrically contacts with at least one pad on the first substrate; a conducting layer disposed on the upper semiconductor layer of the second substrate and electrically connected to the portion of the lower semiconductor layer electrically contacting with the at least one pad; an opening extending from the upper semiconductor layer towards the lower semiconductor layer and extending into the lower semiconductor layer; and a protection layer disposed on the upper semiconductor layer and the conducting layer, wherein the protection layer extends onto a portion of a sidewall of the opening, and does not cover the lower semiconductor layer in the opening.

Semiconductor device, method for manufacturing semiconductor device, circuit board, and electronic instrument

A semiconductor device includes: a semiconductor substrate having an active surface and a back surface; an integrated circuit formed on the active surface; a feedthrough electrode penetrating the semiconductor substrate, and projecting from the active surface and the back surface; a first resin layer formed on the active surface, having a thickness greater than a height of a portion of the feedthrough electrode that projects from the active surface, and having an opening portion for exposing at least a portion of the feedthrough electrode; a wiring layer which is formed on the first resin layer, and which is connected to the feedthrough electrode through the opening portion; and an external connecting terminal connected to the wiring layer.

PACKAGING METHODS FOR IMAGER DEVICES

An imager device is disclosed which includes at least one photosensitive element positioned on a front surface of a substrate and a conductive structure extending at least partially through an opening defined in the substrate to conductively couple to an electrical contact or bond pad on the first surface. An insulating material of a conductive laminate film and/or a mold compound material is positioned within the opening between at least a portion of the conductive structure and the substrate. Also disclosed is a device that comprises a substrate and a plurality of openings in the substrate, wherein each of the openings is adapted to be positioned above an imager device when the substrate is positioned above and secured to an imager substrate. A method of forming an imager device is also disclosed.

Through via connected backside embedded circuit features structure and method

A method includes forming through vias in a substrate of an array. Nubs of the through vias are exposed from a backside surface of the substrate. A backside passivation layer is applied to enclose the nubs. Laser-ablated artifacts are formed in the backside passivation layer to expose the nubs. Circuit features are formed within the laser-ablated artifacts. By forming the circuit features within the laser-ablated artifacts in the backside passivation layer, the cost of fabricating the array is minimized. More particularly, the number of operations to form the embedded circuit features is minimized thus minimizing fabrication cost of the array.

Semiconductor packaging process using through silicon vias

A microelectronic unit can include a semiconductor element having a front surface, a microelectronic semiconductor device adjacent to the front surface, contacts at the front surface and a rear surface remote from the front surface. The semiconductor element can have through holes extending from the rear surface through the semiconductor element and through the contacts. A dielectric layer can line the through holes. A conductive layer may overlie the dielectric layer within the through holes. The conductive layer can conductively interconnect the contacts with unit contacts.

Metal Bump Joint Structure and Methods of Forming

A structure comprises a first semiconductor chip with a first metal bump and a second semiconductor chip with a second metal bump. The structure further comprises a solder joint structure electrically connecting the first semiconductor chip and the second semiconductor chip, wherein the solder joint structure comprises an intermetallic compound region between the first metal bump and the second metal bump, wherein the intermetallic compound region is with a first height dimension and a surrounding portion formed along exterior walls of the first metal bump and the second metal bump, wherein the surrounding portion is with a second height dimension, and wherein the second height dimension is greater than the first height dimension.

Interconnect structures for preventing solder bridging, and associated systems and methods

Semiconductor dies having interconnect structures formed thereon, and associated systems and methods, are disclosed herein. In one embodiment, an interconnect structure includes a conductive material electrically coupled to an electrically conductive contact of a semiconductor die. The conductive material includes a first portion vertically aligned with the conductive contact, and a second portion that extends laterally away from the conductive contact. A solder material is disposed on the second portion of the interconnect structure such that the solder material is at least partially laterally offset from the conductive contact of the semiconductor die. In some embodiments, an interconnect structure can further include a containment layer that prevents wicking or other undesirable movement of the solder material during a reflow process.

METHOD FOR REMOVING ELECTROPLATED METAL FACETS AND REUSING A BARRIER LAYER WITHOUT CHEMICAL MECHANICAL POLISHING

A method for avoiding using CMP for eliminating electroplated copper facets and reusing barrier layer in the back end of line (BEOL) manufacturing processes. Electropolishing is employed to remove the deposited surface metal, stopping at the barrier layer to form a smooth surface that may be utilized in subsequent steps. The method is suitable for the electropolishing of metal surfaces after formation of filled vias for through-silicon via processes employing metals such as copper, tungsten, aluminum, or alloys thereof. The remaining barrier layer may be reused to fabricate the redistribution layer.

PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME

A package structure includes a circuit element, a first semiconductor die, a second semiconductor die, a heat dissipating element, and an insulating encapsulation. The first semiconductor die and the second semiconductor die are located on the circuit element. The heat dissipating element connects to the first semiconductor die, and the first semiconductor die is between the circuit element and the heat dissipating element, where a sum of a first thickness of the first semiconductor die and a third thickness of the heat dissipating element is substantially equal to a second thickness of the second semiconductor die. The insulating encapsulation encapsulates the first semiconductor die, the second semiconductor die and the heat dissipating element, wherein a surface of the heat dissipating element is substantially leveled with the insulating encapsulation.

SEMICONDUCTOR DEVICE

A semiconductor device includes: a semiconductor substrate having an integrated circuit formed thereon and an electrode electrically coupled to the integrated circuit; a passivation film formed on a surface of the semiconductor substrate, the surface having the electrode formed thereon; a first metal layer formed so as to come into contact with the passivation film; a resin layer formed on the first metal layer; a wiring formed so as to be electrically coupled to the electrode and reach an upper surface of the resin layer; and a second metal layer formed so as to be in contact with the first metal layer and reach the upper surface of the resin layer.

Passivation layer for integrated circuit structure and forming the same

A method includes forming metal lines over an interconnect structure that is formed above transistors; depositing a liner layer over the metal lines using a first high density plasma chemical vapor deposition (HDPCVD) process with a zero RF bias power depositing a first passivation layer over the liner layer using a second HDPCVD process with a non-zero RF bias power; and depositing a second passivation layer in contact with a top surface of the first passivation layer using a third HDPCVD process with a non-zero RF bias power.

Semiconductor apparatus and production method thereof

A semiconductor apparatus includes (i) a semiconductor substrate, (ii) a field oxide film, formed in a surface of the semiconductor substrate, having an aperture section, (iii) a electrode pad formed on the field oxide film, and (iv) a penetration electrode electrically connected to the electrode pad via the aperture section of the field oxide film and a hole formed in the semiconductor substrate. The hole is formed in the aperture section of the field oxide film, when perpendicularly viewing the semiconductor substrate.

Solder bumping of integrated circuit die

A method for forming a solder bump on an integrated circuit die utilizes a terminal (12) formed of an electrically conductive, solder-wettable composite material composed of copper particles and a polymeric binder. The terminal comprises a bond pad (24) overlying a passivation layer (20) on the die and a runner section (26) connecting the bond pad to a metal contact (16). The terminal is applied to the die, for example, as an ink by screen printing, after which a body of solder alloy is reflowed in contact with the bond pad to form the bump. A preferred material for the terminal is composed of silver-plated copper particles and a resol type phenolic binder.

USING AN INTERCONNECT BUMP TO TRAVERSE THROUGH A PASSIVATION LAYER OF A SEMICONDUCTOR DIE

A semiconductor die, which includes a first semiconductor device, a first passivation layer, and a first interconnect bump, is disclosed. The first passivation layer is over the first semiconductor device, which includes a first group of device fingers. The first interconnect bump is thermally and electrically connected to each of the first group of device fingers. Additionally, the first interconnect bump protrudes through a first opening in the first passivation layer.

INTERCONNECT LAYER CONTACT AND METHOD FOR IMPROVED PACKAGED INTEGRATED CIRCUIT RELIABILITY

Packaged photosensor ICs are made by fabricating an integrated circuit (IC) with multiple bondpads; forming vias from IC backside through semiconductor to expose a first layer metal; depositing conductive metal plugs in the vias; depositing interconnect metal; depositing solder-mask dielectric over the interconnect metal and openings therethrough; forming solder bumps on interconnect metal at the openings in the solder-mask dielectric; and bonding the solder bumps to conductors of a package. The photosensor IC has a substrate; multiple metal layers separated by dielectric layers formed on a first surface of the substrate into which transistors are formed; multiple bondpad structures formed of at least a first metal layer of the metal layers; vias with metal plugs formed through a dielectric over a second surface of the semiconductor substrate, interconnect metal on the dielectric forming connection shapes, and shapes of the interconnect layer coupled to each conductive plug and to solder ...

Interconnect structure and method of fabricating same

An interconnect structure and a method of fabrication of the same are introduced. In an embodiment, a post passivation interconnect (PPI) structure is formed over a passivation layer of a substrate. A bump is formed over the PPI structure. A molding layer is formed over the PPI structure. A film is applied over the molding layer and the bump using a roller. The film is removed from over the molding layer and the bump, and the remaining material of the film on the molding layer forms the protective layer. A plasma cleaning is preformed to remove the remaining material of the film on the bump.

Light Emitting Diode With Metal Piles and Multi-Passivation Layers and Its Manufacturing Method

The present invention relates to a light emitting diode with metal piles and one or more passivation layers and a method for making the diode including a first steps of performing mesa etching respectively on a first semiconductor layer and a second semiconductor layer belonging to stacked layers formed on a substrate in sequence! a second step of forming a reflector layer on the mesa-etched upper and side face! a third step of contacting one or more first electrodes with the first semiconductor layer and one or more second electrodes through the reflector layer with the second semiconductor layer; a fourth step of forming a first passivation layer on the reflector layer and the contacted electrodes; and a fifth step of connecting the first electrodes to a first bonding pad through one or more first electrode lines, bring one ends of vertical extensions having the shape of a metal pile into contact with one or more second electrodes, and connecting the other ends of the vertical extensions ...

Semiconductor device comprising a chip substrate, a mold, and a buffer layer

A semiconductor device and a method of manufacturing the semiconductor device are disclosed. The semiconductor device includes a chip substrate, a mold, and a buffer layer. The mold is disposed over the chip substrate. The buffer layer is externally embedded between the chip substrate and the mold. The buffer layer has an elastic modulus or a coefficient of thermal expansion less than that of the mold. The method includes disposing a buffer layer at least covering scribe lines of a substrate, forming a mold over the substrate and covering the buffer layer, and cutting along the scribe lines and through the mold, the buffer layer and the substrate.

SEMICONDUCTOR DEVICES HAVING CUTOUTS IN AN ENCAPSULATION MATERIAL AND ASSOCIATED PRODUCTION METHODS

A method comprises providing a least one semiconductor component, wherein each of the at least one semiconductor component comprises: a semiconductor chip, wherein the semiconductor chip comprises a first main surface and a second main surface opposite the first main surface, and a sacrificial layer arranged above the opposite second main surface of the semiconductor chip. The method further comprises encapsulating the at least one semiconductor component with an encapsulation material. The method further comprises removing the sacrificial material, wherein above each of the at least one semiconductor chip a cutout is formed in the encapsulation material. The method further comprises arranging at least one lid above the at least one cutout, wherein a closed cavity is formed by the at least one cutout and the at least one lid above each of the at least one semiconductor chip.

OPTICAL COVER PLATE WITH IMPROVED SOLDER MASK DAM ON GALSS FOR IMAGE SENSOR PACKAGE AND FABRICATION METHOD THEREOF

An optical cover plate for image sensor package includes a transparent substrate, at least an annular dam structure, and a barrier layer. The annular dam structure is disposed on the transparent substrate and encompasses a light-receiving area. The barrier layer conformally covers at least a sidewall of the annular dam structure. A method of manufacturing the optical cover plate, an image sensor package and fabrication method thereof are also disclosed.

CHIP PACKAGE AND FABRICATION METHOD THEREOF

A chip package includes a chip, a laser stop layer, a first though hole, an isolation layer, a second though hole and a conductive layer. The laser stop layer is disposed above a first surface of the chip, and the first though hole is extended from a second surface to the first surface of the chip to expose the laser stop layer. The isolation layer is below the second surface and in the first through hole, and the isolation layer has a third surface opposite to the second surface. The second though hole is extended from the third surface to the first surface, and the second though hole is through the first through hole to expose the laser stop layer. The conductive layer is disposed below the third surface and extended into the second though hole to contact the laser stop layer.

Semiconductor device having wire studs as vertical interconnect in FO-WLP

A semiconductor device has a substrate and semiconductor die disposed over a first surface of the substrate. A wire stud is attached to the first surface of the substrate. The wire stud includes a base portion and stem portion. A bonding pad is formed over a second surface of the substrate. An encapsulant is deposited over the substrate, semiconductor die, and wire stud. A portion of the encapsulant is removed by LDA to expose the wire stud. A portion of the encapsulant is removed by LDA to expose the substrate. An interconnect structure is formed over the encapsulant and electrically connected to the wire stud and semiconductor die. A bump is formed over the interconnect structure. A semiconductor package is disposed over the encapsulant and electrically connected to the substrate. A discrete semiconductor device is disposed over the encapsulant and electrically connected to the substrate.

Fabrication method of semiconductor structure

The present invention provides a semiconductor structure and a method of fabricating the same. The method includes: providing a chip having conductive pads, forming a metal layer on the conductive pads, forming a passivation layer on a portion of the metal layer, and forming conductive pillars on the metal layer. Since the metal layer is protected by the passivation layer, the undercut problem is solved, the supporting strength of the conductive pillars is increased, and the product reliability is improved.

Package structure having adhesive layer surrounded dam structure

A package structure includes a substrate, a die, an adhesive layer, a dam structure, and an encapsulant. The die is disposed on the substrate. The adhesive layer is disposed between the substrate and the die. The adhesive layer has a curved surface. The dam structure is disposed on the substrate and surrounded by the adhesive layer. The encapsulant encapsulates the die.

Bumping process

A bumping process wherein a substrate is first provided with many electrical connections. Subsequently, the bumps on the bump transfer substrate are pressed onto the electrical connections of the substrate accompanying a heating process and then the bumps are transferred onto the electrical connections of the substrate because the adhesion characteristic between the bumps and the electrical connections is better than that between the bumps and the release layer.

Package structure and manufacturing method thereof

A package structure including a first chip, a second chip, a dielectric body, a third chip, an encapsulant, a first conductive terminal, and a circuit layer is provided. The dielectric body covers the first chip and the second chip. The third chip is disposed on the dielectric body such that a third active surface thereof faces a first active surface of the first chip or a second active surface of the second chip. The encapsulant covers the third chip. The first conductive terminal is disposed on the dielectric body and is opposite to the third chip. The circuit layer includes a first circuit portion and a second circuit portion. The first circuit portion penetrates the dielectric body. The first chip, the second chip, or the third chip is electrically connected to the first conductive terminal through the first circuit portion. The second circuit portion is embedded in the dielectric body.

Semiconductor device having low dielectric insulating film and manufacturing method of the same

A semiconductor device includes a semiconductor substrate on which a structure portion is provided except a peripheral portion thereof, and has a laminated structure including low dielectric films and wiring lines, the low dielectric films having a relative dielectric constant of 3.0 or lower and a glass transition temperature of 400° C. or higher. An insulating film is formed on the structure portion. A connection pad portion is arranged on the insulating film and connected to an uppermost wiring line of the laminated structure portion. A bump electrode is provided on the connection pad portion. A sealing film made of an organic resin is provided on a part of the insulating film which surrounds the pump electrode. Side surfaces of the laminated structure portion are covered with the insulating film and/or the sealing film.

Die-wafer package and method of fabricating same

A die-wafer package includes a singulated semiconductor die having a first plurality of bond pads on a first surface and a second plurality of bond pads on a second opposing surface thereof. Each of the first and second pluralities of bond pads includes an under-bump metallization (UBM) layer. The singulated semiconductor die is disposed on a semiconductor die site of a semiconductor wafer and a first plurality of conductive bumps electrically couples the first plurality of bond pads of the singulated semiconductor die with a first set of bond pads formed on the semiconductor die site. A second plurality of conductive bumps is disposed on a second set of bond pads of the semiconductor die site. A third plurality of conductive bumps is disposed on the singulated semiconductor die's second plurality of bond pads. The second and third pluralities of conductive bumps are configured for electrical interconnection with an external device.

Interconnect structure with redundant electrical connectors and associated systems and methods

Semiconductor die assemblies having interconnect structures with redundant electrical connectors are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die, a second semiconductor die, and an interconnect structure between the first and the second semiconductor dies. The interconnect structure includes a first conductive film coupled to the first semiconductor die and a second conductive film coupled to the second semiconductor die. The interconnect structure further includes a plurality of redundant electrical connectors extending between the first and second conductive films and electrically coupled to one another via the first conductive film.

Image pickup apparatus, semiconductor apparatus, and image pickup unit

An image pickup apparatus includes: an image pickup chip including a light receiving section and electrode pads, on a first main face, and a plurality of connection electrodes, each of which is connected to each of the electrode pads via each of a plurality of through-hole interconnections, on a second main face; a transparent cover glass having a larger plan-view dimension than the image pickup chip; a transparent adhesive layer that bonds the first main face of the image pickup chip and the cover glass; and a sealing member that covers a side face of the image pickup chip and a side face of the adhesive layer, and is made of an insulating material having a same plan-view dimension as the cover glass.

Package structure and manufacturing method thereof

A manufacturing method of a package structure includes at least the following steps. A plurality of conductive connectors are formed on a circuit layer. The circuit layer includes a central region and a peripheral region electrically connected to the central region. A chip is disposed on the central region of the circuit layer. The chip includes an active surface at a distance from the circuit layer and a sensing area on the active surface. An encapsulant is formed on the circuit layer to encapsulate the chip and the conductive connectors. A redistribution layer is formed on the encapsulant to electrically connect the chip and the conductive connectors. The redistribution layer partially covers the chip and includes a window corresponding to the sensing area of the chip. A package structure is also provided.

Semiconductor package and manufacturing method of semiconductor package

A manufacturing method of a semiconductor package includes the following steps. At least one lower semiconductor device is provided. A plurality of conductive pillars are formed on the at least one lower semiconductor device. A dummy die is disposed on a side of the at least one lower semiconductor device. An upper semiconductor device is disposed on the at least one lower semiconductor device and the dummy die, wherein the upper semiconductor device reveals a portion of the at least one lower semiconductor device where the plurality of conductive pillars are disposed. The at least one lower semiconductor device, the dummy die, the upper semiconductor device, and the plurality of conductive pillars are encapsulated in an encapsulating material. A redistribution structure is formed over the upper semiconductor device and the plurality of conductive pillars.

Semiconductor device and method comprising redistribution layers

A method of making a semiconductor package can include forming a plurality of redistribution layer (RDL) traces disposed over active surfaces of a plurality of semiconductor die and electrically connected to contact pads on the plurality of semiconductor die. The method can include disposing an encapsulant material over the active surfaces, contacting at least four side surfaces of each of the plurality of semiconductor die, and disposed over the plurality of RDL traces. The method can also include forming a via through the encapsulant material to expose at least one of the plurality of RDL traces, forming an electrical interconnect disposed within the via and coupled to the at least one RDL trace, and singulating the plurality of semiconductor packages through the encapsulant material to leave an offset of 30-140 μm of the encapsulant material disposed around a periphery of each of the plurality of semiconductor die.

Structure of semiconductor chip and display device using the same

Provided is a structure which is capable of narrowing a semiconductor chip in width and a display device which is narrowed in frame by using the same. In the structure of a semiconductor chip provided such that the semiconductor chip is mounted on a glass substrate and a plurality of power lines (a first wiring and a second wiring) of the semiconductor chip are extended in a continuous direction so as to form, the structure of the semiconductor chip comprises the power lines with different electric potentials, which is formed by overlapping. Rather than making a capacity at the overlapped area of wirings and forming the wiring alone, a wiring which is narrowed in width may be achieved.

Semiconductor Package

A semiconductor device is disclosed. The semiconductor device comprises a first die, a second die, and a redistribution structure. The first die and the second die are electrically connected to the redistribution structure. There are no solder bumps between the first die and the redistribution structure. There are no solder bumps between the second die and the redistribution structure. The first die and the second die have a shift with regard to each other from a top view.

METHOD OF FABRICATING SEMICONDUCTOR PACKAGE

A method of fabricating a semiconductor package includes providing a wafer which includes an upper area having through silicon vias (TSVs) and a lower area not having the TSVs; mounting a semiconductor chip on the upper area of the wafer; forming a passivation layer to a predetermined thickness to cover the semiconductor chip; exposing the TSVs by removing the lower area of the wafer in a state where no support is attached to the wafer; and exposing a top surface of the semiconductor chip by partially removing the passivation layer.

Directly Sawing Wafers Covered with Liquid Molding Compound

A method includes forming a passivation layer over a metal pad, wherein the metal pad is further overlying a semiconductor substrate of a wafer. A Post-Passivation Interconnect (PPI) is formed to electrically couple to the metal pad, wherein a portion of the PPI is overlying the passivation layer. A metal bump is formed over and electrically coupled to the PPI. The method further includes applying a molding compound over the metal bump and the PPI, applying a release film over the molding compound, pressing the release film against the molding compound, and curing the molding compound when the release film is pressed against the molding compound. The release film is then removed from the molding compound. The wafer is sawed into dies using a blade, with the blade cutting through the molding compound.

Semiconductor device and manufacturing method thereof

A semiconductor device manufacturing method is disclosed. The method includes etching a silicon on insulator (SOI) from its surface (i.e., semiconductor substrate layer) to form a first trench and a second trench. The first trench extends through the SOI substrate and reaches an electrode pad. The second trench terminates in the semiconductor substrate layer. The manufacturing method also includes forming an insulation film that covers the surface of the semiconductor substrate layer as well as the side walls and bottoms of the first and second trenches. The manufacturing method also includes removing the insulation film from the bottoms of the first and second trenches to expose the electrode pad from the first trench bottom and to expose the semiconductor substrate layer from the second trench bottom.

Semiconductor device and manufacturing method thereof

An electronic device and a method of making an electronic device. As non-limiting examples, various aspects of this disclosure provide various methods of making electronic devices, and electronic devices made thereby, that utilize a film assist mold process.

Isolated complementary metal-oxide semiconductor (CMOS) devices for radio-frequency (RF) circuits

Isolated complementary metal-oxide semiconductor (CMOS) devices for radio-frequency (RF) circuits are disclosed. In some aspects, an RF circuit includes CMOS devices, a silicon substrate having doped regions that define the CMOS devices, and a trench through the silicon substrate. The trench through the silicon substrate forms a continuous channel around the doped regions of one of the CMOS devices to electrically isolate the CMOS device from other CMOS devices embodied on the silicon substrate. By so doing, performance characteristics of the CMOS device, such as linearity and signal isolation, may be improved over those of conventional CMOS devices (e.g., bulk CMOS).

METHOD FOR FORMING C4 CONNECTIONS ON INTEGRATED CIRCUIT CHIPS AND THE RESULTING DEVICES

METHOD OF MANUFACTURING SEMICONDUCTOR MODULE

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor module which improves electrical connection of a copper plate and a semiconductor device. SOLUTION: In the semiconductor module 1, a copper plate is etched and a bump electrode 110 and a recess are formed. An insulating resin layer 120 is formed to a position lower than the height of the bump electrode 115 in the recess. Then, a semiconductor device 210 and a copper plate including a wiring layer 135 formed integrally with the bump electrode 110 are pressure bonded. The wiring layer 135 is curved such that it is protruded to a semiconductor device 210 side. Accordingly, electrical connection of the bump electrode 110 and an element electrode 211 is secured. COPYRIGHT: (C)2011,JPO&INPIT ...

УСТРОЙСТВО С ПЕРЕХОДНЫМИ ОТВЕРСТИЯМИ В ПОДЛОЖКЕ И СПОСОБ ЕГО ПРОИЗВОДСТВА

... 1. Устройство (10) с переходными отверстиями в подложке, содержащее:подложку (12), выполненную из материала подложки и имеющую первую поверхность (12а) подложки и вторую поверхность (12b) подложки, противоположную первой поверхности (12а) подложки,множество соседних первых канавок (14), обеспеченных проводящим материалом и проходящих с первой поверхности (12а) подложки внутрь подложки (12), так что между первыми канавками (14) формируется множество спейсеров (16) из материала подложки,вторую канавку (18), обеспеченную проводящим материалом и проходящую со второй поверхности (12b) подложки внутрь материала подложки (12), причем вторая канавка (18) соединена с первыми канавками (14),проводящий слой (20), выполненный из проводящего материала и сформированный на стороне первой поверхности (12а) подложки, причем проводящий материал заполняет первые канавки (14), так что первый проводящий слой (20) имеет, по существу, планарную и закрытую поверхность, покрывающую заполненные первые канавки и ...

Halbleiter

HALBLEITERANORDNUNG

Halbleitervorrichtung mit Nachpassivierung-Zwischenverbindungsstruktur und Verfahren zu ihrer Bildung

Halbleitervorrichtung mit Nachpassivierungs-Zwischenverbindungsstruktur, umfassend: – eine auf einem Halbleitersubstrat (10) ausgebildete Schaltungsanordnung (12) mit elektrische Vorrichtungen überlagernden dielektrischen Schichten und dazwischenliegend ausgebildeten Metallschichten; – eine dielektrische Zwischenschicht (14) aufgetragen durch plasmaunterstützte chemische Gasphasenabscheidung mit mehreren dielektrischen Schichten und darin ausgebildeten Kontakten zum Kontaktieren der Schaltungsanordnung (12); – mehrere dielektrische Zwischenmetallschichten (16) aufgetragen durch chemische Gasphasenabscheidung mit hochdichtem Plasma mit zugeordneten Metallisierungsschichten, die der dielektrischen Zwischenschicht (14) überlagert sind, wobei die Metallisierungsschichten mittels Ätzprozess unter Verwendung von Ätzstoppschichten aufgetragen durch plasmaunterstützte chemische Gasphasenabscheidung Metallleitungen (18) und Durchkontakte (19) zum Zusammenschalten der Schaltungsanordnung (12) schaffen ...

Halbleiterbauelemente und Verfahren zur Herstellung von Halbleiterbauelementen

Bauelement, umfassend:ein Halbleitermaterial (1), das eine erste Hauptoberfläche (2), eine gegenüberliegende Oberfläche (3), die der ersten Hauptoberfläche gegenüberliegt, und eine seitliche Oberfläche (4), die sich von der ersten Hauptoberfläche zur gegenüberliegenden Oberfläche erstreckt, umfasst, wobei das Halbleitermaterial eine Funktionsfläche umfasst, die in einem Hochfrequenzbereich betrieben wird;ein erstes elektrisches Kontaktelement (5), das auf der ersten Hauptoberfläche (2) des Halbleitermaterials angeordnet ist;ein Glasmaterial (6), das eine zweite Hauptoberfläche (7) umfasst, wobei das Glasmaterial die seitliche Oberfläche (4) des Halbleitermaterials kontaktiert und wobei die erste Hauptoberfläche (2) des Halbleitermaterials und die zweite Hauptoberfläche des Glasmaterials in einer gemeinsamen Ebene angeordnet sind; undeine Metallschicht (11), die über der ersten Hauptoberfläche (2) des Halbleitermaterials und über dem Glasmaterial angeordnet ist, wobei eine passive elektronische ...

Chipanordnungen

Chipanordnung (310), welche aufweist:eine Leiterplatte (362), welche aufweist:• ein Durchgangsloch (364), das in der Leiterplatte (362) ausgebildet ist,• und ein oder mehrere Leiterplattenkontaktgebiete (366S, 366G, 366D) , die in der Nähe des Durchgangslochs (364) angeordnet sind, undein Chipgehäuse (210, 160) mit einem Chip (104), das innerhalb des Durchgangslochs (364) angeordnet ist, wobei mindestens ein Leiterplattenkontaktgebiet (366S, 366G) elektrisch mit einem oder mit mehreren elektrisch leitenden Verbindungsstrukturen (144, 146) verbunden ist, die über einer Oberseite (152) des Chipgehäuses (210, 160) ausgebildet sind und in elektrischem Kontakt mit einer Chipoberseite (122) stehen, undwobei mindestens ein weiteres Leiterplattenkontaktgebiet (366D) elektrisch mit einer elektrisch leitenden Verbindungsstruktur (148) verbunden ist, die über einer Unterseite (154) des Chipgehäuses (210, 160) ausgebildet ist und in elektrischem Kontakt mit einer Chipunterseite (124) steht,wobei das ...

Power management applications of interconnect substrates

Various applications of interconnect substrates in power management systems are described.

Fan out system in package and method for forming the same

Handling thin wafer during chip manufacture

Semiconductor device

Chip package, wafer level chip array and manufacturing method thereof

Semiconductor device and manufacturing method thereof

Semiconductor device

IMPROVED METHOD FOR PRODUCING A STRUCTURE CONTACT ELEMENT

3D STACK ELECTRONIC CHIPS

3D STACK ELECTRONIC CHIPS

Forming vias in semiconductor wafer, by making wafer having closed perimeter on its front side, filling wafer with dielectric material, thinning wafer by abrasion and/or etching, and removing semiconductor extending inside perimeter

L'invention concerne un procédé de formation d'un via dans une plaquette de semi-conducteur (1"), comprenant les étapes consistant à pratiquer une tranchée (401) sur une face avant de la plaquette, la tranchée délimitant un périmètre fermé, remplir la tranchée avec un matériau diélectrique (402), amincir la plaquette par abrasion de sa face arrière, jusqu'à atteindre au moins le fond de la tranchée, et graver le semi-conducteur s'étendant à l'intérieur du périmètre fermé délimité par la tranchée, de manière à faire apparaitre une cavité (408) dont la paroi est revêtue par le matériau diélectrique (402).

METHOD FOR FORMING THROUGH ELECTRODE, AND SEMICONDUCTOR DEVICE

반도체 장치 및 이의 제조 방법

... 본 발명은 반도체 장치 및 이의 제조 방법을 제공한다. 이 반도체 장치에서는, 재배선 패턴들 사이에 유기 절연 패턴이 개재된다. 상기 재배선 패턴이 열에 의해 팽창될 경우 발생되는 물리적 스트레스를 상기 유기 절연 패턴이 흡수할 수 있다. 이로써 유연성을 증대시킬 수 있다. 재배선 패턴들 사이에 유기절연 패턴이 개재되므로, 재배선 패턴들 사이에 반도체 패턴이 개재되는 경우에 비해, 절연성을 증대시킬 수 있다. 또한 재배선 패턴과 유기 절연 패턴 사이 그리고 반도체 기판과 유기 절연 패턴 사이에 시드막 패턴이 개재되므로, 재배선 패턴의 접착력이 향상되어 박리 문제를 개선할 수 있다. 또한 재배선 패턴을 구성하는 금속이 유기 절연 패턴으로 확산되는 것을 시드막 패턴이 방지할 수 있다. 이로써, 신뢰성이 향상된 반도체 장치를 구현할 수 있다.

RECESSED SEMICONDUCTOR SUBSTRATES

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

Provided are a semiconductor device and a method for manufacturing the same. A reflowable material is electrically connected to a through via, wherein the through via is extended through a sealing material. A protective layer is formed on the reflowable material. According to an embodiment, an opening part is formed within the protective layer to expose the reflowable material. According to other embodiments, the protective layer is formed so that the reflowable material is extended far from the protective layer. COPYRIGHT KIPO 2016 ...

SEMICONDUCTOR CHIP PACKAGE, SEMICONDUCTOR MODULE AND FABRICATION METHOD THEREOF

BUMP WITH MULTIPLE VIAS FOR SEMICONDUCTOR PACKAGE TO INCREASE SURFACE AREA OF WIRING, FABRICATING METHOD THEREOF, AND SEMICONDUCTOR PACKAGE USING THE SAME

PURPOSE: A bump with multiple vias for a semiconductor package, a fabricating method thereof, and a semiconductor package using the same are provided to increase a surface area of a wiring by forming a polymer layer having the multiple vias on an electrode pad. CONSTITUTION: An electrode pad(115) is formed on a semiconductor chip(110), and a polymer layer(130) having plural vias(135) is formed on the electrode pad. An under bump metal layer(170) having plural vias is formed on the polymer layer. A metal bump(180) is bonded on the under bump metal layer. The electrode pad is redistributed from a first region to a second region. A stress relaxation layer(160) is formed on the polymer layer having the vias. The under bump metal layer includes at least one of an adhesion layer, a diffusion-barrier layer, and a wetting layer. © KIPO 2007 ...

Semiconductor structure

The present disclosure relates to a semiconductor structure, which includes a semiconductor substrate, an insulating layer and a plurality of traces. The insulating layer is disposed on the semiconductor substrate. The plurality of traces are disposed between the insulating layer and the semiconductor substrate. At least one of the plurality of traces includes a plurality of apertures, wherein a total area of the plurality of apertures ranges from 10% to 70% of a surface area of the at least one trace.

Substrate structure and manufacturing method thereof

This invention provides a substrate structure, comprising: a substrate body, an insulating protective layer provided on the substrate body and having a plurality of open-pores, and at least one electrical contact pad and at least one ring body provided in the open-pore, such that each electrical contact pad corresponds to expose on each open-pore, and each ring body corresponds to surround the edge of each electrical contact pad, so as to form a conductive element in each ring body in a follow-up process, and therefore when back welds the conductive element, the ring body can confine the conductive element to expand outwards, and the conductive element thereby can avoid extruding the insulating protective layer and causing the fragmentation of the insulating protective layer. This invention further provides a manufacturing method of the substrate structure.

A packaging method and structure for an image sensing chip

A packaging method and structure for an image sensing chip is provided. The packaging method includes: providing a wafer having a first surface and a second surface opposite to the first surface, the wafer including multiple image sensing chips arranged in a grid, and the image sensing chip including an image sensing region and a pad which are located at the side of the first surface; forming a cutting groove and a hole corresponding to the pad on the second surface of the wafer, the pad being exposed through the hole; filling the cutting groove with a first photosensitive ink; coating the second surface of the wafer with a second photosensitive ink to cause the second photosensitive ink to cover the hole with a cavity being formed in the hole. The packaging structure of the image sensing chip formed by the method can effectively avoid contact of the second photosensitive ink with the bottom of the hole, which improves the yield of packaging the image sensing chip and improves the reliability ...

Package and method

A package includes a die, which includes a semiconductor substrate, a plurality of through-vias penetrating through the semiconductor substrate, a seal ring overlapping and connected to the plurality of through-vias, and a plurality of electrical connectors underlying the semiconductor substrate and connected to the seal ring. An interposer is underlying and bonded to the die. The interposer includes a substrate, and a plurality of metal lines over the substrate. The plurality of metal lines is electrically coupled to the plurality of electrical connectors. Each of the plurality metal lines has a first portion overlapped by the first die, and a second portion misaligned with the die. A thermal conductive block encircles the die, and is mounted on the plurality of metal lines of the interposer.

Image sensor package and fabrication method thereof

An image sensor package includes an image sensor die having an active side and a backside, wherein an image sensor device region and a bond pad are provided on the active side. A through-silicon-via (TSV) structure extending through the thickness of the image sensor die is provided to electrically connect the bond pad. A multi-layer re-distributed interconnection structure is provided on the backside of the image sensor die. A solder mask or passivation layer covers the multi-layer re-distributed interconnection structure.

Electronic device and manufacturing method thereof

An electronic device and a manufacturing method thereof are provided. The electronic device includes a chip package, a core dielectric layer disposed on the chip package, and an antenna pattern disposed on the core dielectric layer opposite to the chip package. The chip package includes a semiconductor chip, an insulating encapsulation encapsulating the semiconductor chip, and a redistribution structure electrically coupled to the semiconductor chip. The redistribution structure includes a first circuit pattern located at an outermost side of the chip package, and a patterned dielectric layer disposed between the first circuit pattern and the insulating encapsulation. The core dielectric layer is in contact with the first circuit pattern. The core dielectric layer and the patterned dielectric layer are of different materials. The antenna pattern is electrically coupled to the chip package.

Integrated circuit packaging system with active surface heat removal and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing an interconnect structure having a structure bottom side, a structure top side, and a cavity, the structure bottom side electrically connected to the structure top side; mounting an integrated circuit entirely within the cavity, the integrated circuit having an active side coplanar with the structure top side; forming an encapsulation partially covering the interconnect structure and the integrated circuit, the encapsulation having an encapsulation top side coplanar with the structure top side and the active side; forming a top re-passivation layer over the structure top side and the encapsulation; and mounting a heat sink over the top re-passivation layer for removing heat from the active side.

Semiconductor Device and Method of Manufacture Thereof

A semiconductor device and a method of making a semiconductor device are disclosed. The semiconductor device comprises a redistribution layer arranged over a chip, the redistribution layer comprising a first redistribution line. The semiconductor further comprises an isolation layer disposed over the redistribution layer, the isolation layer having a first opening forming a first pad area and a first interconnect located in the first opening and in contact with the first redistribution line. The redistribution line in the first pad area is arranged orthogonal to a first direction to a neutral point of the semiconductor device.

Customized rf mems capacitor array using redistribution layer

Disclosed is a method for fabricating a customized micro-electromechanical systems (MEMS) integrated circuit using at least one redistribution layer. The method includes steps of providing a substrate on which MEMS components are fabricated and coupling predetermined ones of the MEMS components via the redistribution traces.

Chip package structure

The formation of the conductive wire of a chip package consists of a plurality of steps. Coat a first dielectric layer on the pad-mounting surface and a slot is formed on each bonding pad correspondingly. Then coat a second dielectric layer and produce a wiring slot corresponding to each bonding pad and the slot thereof. Next each wiring slot is filled with electrically conductive metal so as to form a conductive wire. Later Coat a third dielectric layer and a corresponding slot is formed on one end of each conductive wire while this slot is filled with electrically conductive metal to form a solder point. The above steps can further be repeated so as to form an upper-layer and a lower-layer conductive wire. Thereby precision of the chip package, use efficiency of the wafer and yield rate of manufacturing processes are all improved.

Device mounting board and method of manufacturing the same, semiconductor module, and mobile device

A device mounting board includes: an insulating resin layer; a wiring layer formed on one of the principal surfaces of the insulating resin layer; a protection layer covering the insulating resin layer and the wiring layer; a protruding electrode electrically connected to the wiring layer, the protruding electrode protruding from the wiring layer toward the insulating resin layer and penetrating through the insulating resin layer; a wiring-layer-side convex portion protruding from the wiring layer toward the insulating resin layer and having the top end thereof located inside the insulating resin layer; and a resin-layer-side convex portion protruding from the protection layer toward the insulating resin layer and having the top end thereof located inside the insulating resin layer.

Wafer Level Packaging of Electronic Devices

Aspects of the invention include an electronic device comprising a first contact point; a metal pad disposed to provide electrical connection to the first contact point; a substrate comprising a first face and a second face opposing the first face of the substrate, the first face of the substrate adjacent a face of the electronic device; and a VIA passing through the substrate from the second face of the substrate to the metal pad, the VIA exhibiting: a pass through extending through the substrate from the first face to the second face; a metal layer disposed within the pass through arranged to provide electrical connectivity to the metal pad from an area adjacent the second face of the substrate; and an electrically insulating first passivation layer disposed between the metal layer and the substrate arranged to provide electrical insulation between the substrate and the metal layer.

Microelectronic devices having conductive through via electrodes insulated by gap regions

A microelectronic device includes a substrate having a trench extending therethrough between an active surface thereof and an inactive surface thereof opposite the active surface, a conductive via electrode extending through the substrate between sidewalls of the trench, and an insulating layer extending along the inactive surface of the substrate outside the trench and extending at least partially into the trench. The insulating layer defines a gap region in the trench that separates the substrate and the via electrode. Related devices and methods of fabrication are also discussed.

Stacked wafer level package having a reduced size

A stacked wafer level package includes a first semiconductor chip having a first bonding pad and a second semiconductor chip having a second bonding pad. Both bonding pads of the semiconductor chips face the same direction. The second semiconductor chip is disposed in parallel to the first semiconductor chip. A third semiconductor chip is disposed over the first and second semiconductor chips acting as a supporting substrate. The third semiconductor chip has a third bonding pad that is exposed between the first and the second semiconductor chips upon attachment. Finally, a redistribution structure is electrically connected to the first, second, and third bonding pads.

Layered chip package and method of manufacturing same

A layered chip package includes a main body and wiring. The main body includes: a main part having a top surface and a bottom surface and including three or more layer portions stacked on one another; a plurality of first terminals disposed on the top surface of the main part; and a plurality of second terminals disposed on the bottom surface of the main part. Each layer portion includes a semiconductor chip having first and second surfaces, and a plurality of electrodes electrically connected to the wiring. The plurality of electrodes are disposed on a side of the first surface of the semiconductor chip. A first layer portion located closest to the top surface of the main part and a second layer portion located closest to the bottom surface of the main part are arranged so that the second surfaces of their respective semiconductor chips face toward each other. The plurality of first terminals are formed by using the plurality of electrodes of the first layer portion. The plurality of second terminals are formed by using the plurality of electrodes of the second layer portion.

Method for manufacturing a circuit device

A semiconductor substrate and a copper sheet stacked with an insulating resin layer are bonded together at a temperature of 130° C. or below (first temperature) so that an element electrode provided on the semiconductor substrate connects to the copper sheet before a thinning process. Then the semiconductor substrate and the copper sheet, on which the insulating resin layer has been stacked, are press-bonded at a high temperature of 170° C. or above (second temperature) with the copper sheet thinned to thickness of a wiring layer. Then the wiring layer (rewiring) is formed by patterning the thinned copper sheet.

Power management applications of interconnect substrates

Various applications of interconnect substrates in power management systems are described.

Methods of Packaging Semiconductor Devices and Structures Thereof

Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies.

Semiconductor device having a through-substrate via

Semiconductor devices are described that include a via that extends only partially through the substrate. Through-substrate vias (TSV) furnish electrical interconnectivity to electronic components formed in the substrates. In implementations, the semiconductor devices are fabricated by first bonding a semiconductor wafer to a carrier wafer with an adhesive material. The semiconductor wafer includes an etch stop disposed within the wafer (e.g., between a first surface a second surface of the wafer). One or more vias are formed through the wafer. The vias extend from the second surface to the etch stop.

Semiconductor Packaging Structure and Method

A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a first bump that is located over a surface of a semiconductor element, and is formed on a first bump formation face distanced from a back surface of the semiconductor element at a first distance, and a second bump that is located over the surface of the semiconductor element, and is formed on a second bump formation face distanced from the back surface of the semiconductor element at a second distance being longer than the first distance, the second bump having a diameter larger than a diameter of the first bump.

Interposer substrate manufacturing method and interposer substrate

A method for manufacturing an interposer substrate includes: forming a conductive portion on a first surface of a semiconductor substrate via a first insulating layer, the conductive portion being formed of a first metal; forming a through hole at a second surface side of the semiconductor substrate located on an opposite side to the first surface so as to expose the first insulating layer; forming a second insulating layer on at least an inner wall surface and a bottom surface of the through hole; exposing the conductive portion by removing portions of the first and second insulating layers using a dry etching method that uses an etching gas containing a fluorine gas, the portions of the first and second insulating layers being located on the bottom surface of the through hole; and forming a conductive layer on the second insulating layer and electrically connecting the conductive layer to the conductive portion, wherein when exposing the conductive portion, forming a tapered portion is performed.

Semiconductor chip package, semiconductor module, and method for manufacturing same

In one embodiment, a semiconductor chip package includes an insulation frame having an opening part formed in a center thereof and a via hole formed around the opening part; a semiconductor chip disposed cm the opening part; a conductive part filling the via hole; an inner insulation layer formed on bottom surfaces of the semiconductor chip and the insulation frame so as to expose a bottom surface of the conductive part; and an inner signal pattern formed on the inner insulation layer and electrically connecting the semiconductor chip and the conductive part. Embodiments also relate to a semiconductor module including a vertical stack of a plurality of the semiconductor chip packages, and to a method for manufacturing the same.

Semiconductor Package and Method of Manufacturing the Same

A method of forming a semiconductor package having a large capacity and a reduced or minimized volume includes: attaching a semiconductor substrate on a support substrate using an adhesive layer, wherein the semiconductor substrate includes a plurality of first semiconductor chips and a chip cutting region, wherein first and second ones of the plurality of first semiconductor chips are separated each other by the chip cutting region, and the semiconductor substrate includes a first surface on which an active area is formed and a second surface opposite to the first surface; forming a first cutting groove having a first kerf width, between the first and second ones of the plurality of first semiconductor chips, so that the semiconductor substrate is separated into a plurality of first semiconductor chips; attaching a plurality of second semiconductor chips corresponding to the first semiconductor chips, respectively, to the plurality of first semiconductor chips; forming a molding layer so as to fill the first cutting groove; and forming a second cutting groove having a second kerf width that is less than the first kerf width, in the molding layer, so as to separate the molding layer into individual molding layers covering one of the plurality of first semiconductor chips and corresponding one of the plurality of second semiconductor chips.

Through-Substrate Vias and Methods for Forming the Same

A device includes a semiconductor substrate and a Metal-Oxide-Semiconductor (MOS) transistor. The MOS transistor includes a gate electrode over the semiconductor substrate, and a source/drain region on a side of the gate electrode. A source/drain contact plug includes a lower portion and an upper portion over the lower portion, wherein the source/drain contact plug is disposed over and electrically connected to the source/drain region. A gate contact plug is disposed over and electrically connected to the gate electrode, wherein a top surface of the gate contact plug is level with a top surface of the top portion of the source/drain contact plug. A Through-Substrate Via (TSV) extends into the semiconductor substrate. A top surface of the TSV is substantially level with an interface between the gate contact plug and the gate electrode.

Semiconductor device having wafer-level chip size package

A semiconductor device including a semiconductor substrate with circuit elements and electrode pads formed on one surface. The surface is covered by a dielectric layer with openings above the electrode pads. A metal layer is included on the dielectric layer and patterned to form a conductive pattern with traces leading to the electrode pads. A protective layer is included as having openings exposing part of the conductive pattern. Each opening is covered by an electrode such as a solder bump, which is electrically connected through the conductive pattern to one of the electrode pads. The thickness of the protective layer, which may function as a package of the semiconductor device, is thus reduced. The protective layer may be formed from a photosensitive material, simplifying the formation of the openings for the electrodes.

Chip package and method for forming the same

An embodiment of the invention provides a chip package including: a first semiconductor substrate; a second semiconductor substrate disposed on the first semiconductor substrate, wherein the second semiconductor substrate includes a lower semiconductor layer, an upper semiconductor layer, and an insulating layer located between the lower semiconductor layer and the upper semiconductor layer, and a portion of the lower semiconductor layer electrically contacts with at least a pad on the first semiconductor substrate; a signal conducting structure disposed on a lower surface of the first semiconductor substrate, wherein the signal conducting structure is electrically connected to a signal pad on the first semiconductor substrate; and a conducting layer disposed on the upper semiconductor layer of the second semiconductor substrate and electrically contacted with the portion of the lower semiconductor layer electrically contacting with the at least one pad on the first semiconductor substrate.

Cte adaption in a semiconductor package

A device such as a wafer-level package (WLP) device is proposed in which a dielectric layer is disposed between a surface of a semiconductor device and a surface of a redistribution layer (RDL). The dielectric layer may have at least one interconnect extending through the dielectric layer. The dielectric layer may have a coefficient of thermal expansion (CTE) value in a direction perpendicular to the surface of the semiconductor device that is less than a threshold value, and a Young's modulus that is greater than another threshold value. The dielectric layer may have a CTE value in a direction parallel to the surface of the semiconductor device at a surface of the dielectric layer facing the RDL that is greater than another threshold value

Integrating through substrate vias from wafer backside layers of integrated circuits

A semiconductor wafer has an integrated through substrate via created from a backside of the semiconductor wafer. The semiconductor wafer includes a semiconductor substrate and a shallow trench isolation (STI) layer pad on a surface of the semiconductor substrate. The semiconductor wafer also includes an inter-layer dielectric (ILD) layer formed on a contact etch stop layer, separating the ILD layer from the STI layer pad on the surface of the semiconductor substrate. The semiconductor wafer further includes a through substrate via that extends through the STI layer pad and the semiconductor substrate to couple with at least one contact within the ILD layer. The through substrate via includes a conductive filler material and a sidewall isolation liner layer. The sidewall isolation liner layer has a portion that possibly extends into, but not through, the STI layer pad.

Method for fabricating a through wire interconnect (twi) on a semiconductor substrate having a bonded connection and an encapsulating polymer layer

A method for fabricating a through wire interconnect for a semiconductor substrate having a substrate contact includes the steps of: forming a via through the semiconductor substrate from a first side to a second side thereof; placing a wire in the via having a first end with a bonded connection to the substrate contact and a second end proximate to the second side; forming a first contact on the wire proximate to the first side; forming a second contact on the second end of the wire; and forming a polymer layer on the first side at least partially encapsulating the wire while leaving the first contact exposed.

Methods and Apparatus of Packaging Semiconductor Devices

Methods and apparatuses for wafer level packaging (WLP) semiconductor devices are disclosed. A redistribution layer (RDL) is formed on a first passivation layer in contact with a conductive pad over a surface of a die. The RDL layer is on top of a first region of the first passivation layer. A second passivation layer is formed on the RDL layer with an opening to expose the RDL layer, and over the first passivation layer. An under bump metallization (UBM) layer is formed over the second passivation layer in contact with the exposed RDL layer. A second region of the first passivation layer disjoint from the first region is determined by projecting an outer periphery of a solder ball or other connector onto the surface.

3DIC Stacking Device and Method of Manufacture

A system and method for stacking semiconductor devices in three dimensions is provided. In an embodiment two or more semiconductor dies are attached to a carrier and encapsulated. Connections of the two or more semiconductor dies are exposed, and the two or more semiconductor dies may be thinned to form connections on an opposite side. Additional semiconductor dies may then be placed in either an offset or overhanging position. 1. A semiconductor device comprising:a first semiconductor die encapsulated by a first encapsulant;at least one through substrate via extending through at least a portion of the first semiconductor die and being exposed on a first side of the first semiconductor die;first external connectors located on a second side of the first semiconductor die;a first redistribution layer in electrical connection with the first external connectors, the first redistribution layer extending over the first encapsulant; anda second semiconductor die in electrical connection with the at least one through substrate via, the second semiconductor die extending over the first encapsulant.2. The semiconductor device of claim 1 , further comprising;a third semiconductor die encapsulated by the first encapsulant; anda fourth semiconductor die in electrical connection with the third semiconductor die, the fourth semiconductor die extending over the first encapsulant.3. The semiconductor device of claim 2 , wherein the second semiconductor die and the fourth semiconductor die are encapsulated by a second encapsulant.4. The semiconductor device of claim 1 , further comprising a second redistribution layer in electrical connection with the at least one through substrate via claim 1 , the second redistribution layer extending over the first encapsulant.5. The semiconductor device of claim 1 , wherein the second semiconductor die is offset from the first semiconductor die.6. The semiconductor device of claim 5 , wherein the offset is between about 100 um and about 3 mm.7. ...

Methods and Apparatus of Packaging Semiconductor Devices

Methods and apparatuses for wafer level packaging (WLP) semiconductor devices are disclosed. A redistribution layer (RDL) is formed on a first passivation layer in contact with a conductive pad over a surface of a die. The RDL layer is on top of a first region of the first passivation layer. A second passivation layer is formed on the RDL layer with an opening to expose the RDL layer, and over the first passivation layer. An under bump metallization (UBM) layer is formed over the second passivation layer in contact with the exposed RDL layer. A second region of the first passivation layer disjoint from the first region is determined by projecting an outer periphery of a solder ball or other connector onto the surface. 1. A semiconductor device comprising:a contact pad over a substrate;a redistribution layer in electrical connection with the contact pad;a passivation layer over the redistribution layer;an underbump metallization extending through the passivation layer to be in physical contact with a surface of the redistribution layer facing away from the substrate; anda solder ball in physical contact with the underbump metallization, wherein the solder ball is laterally separated from the redistribution layer in a direction parallel with a major surface of the substrate.2. The semiconductor device of claim 1 , wherein the underbump metallization comprises a reflowable material along a top surface of the underbump metallization.3. The semiconductor device of claim 1 , wherein the underbump metallization extends through the passivation layer at two or more locations.4. The semiconductor device of claim 1 , wherein the redistribution layer comprises a plurality of sub-layers.5. The semiconductor device of claim 1 , wherein the underbump metallization comprises a plurality of sub-layers.6. The semiconductor device of claim 1 , wherein the underbump metallization comprises a plurality of connection branches.7. The semiconductor device of claim 1 , wherein a sidewall of ...

Semiconductor device

A semiconductor device includes a protective layer, a redistribution pattern, a pad pattern and an insulating polymer layer. The protective layer may be formed on a substrate. The redistribution pattern may be formed on the protective layer. An upper surface of the redistribution may be substantially flat. The pad pattern may be formed directly on the redistribution pattern. An upper surface of the pad pattern may be substantially flat. The insulating polymer layer may be formed on the redistribution pattern and the pad pattern. An upper surface of the insulating polymer layer may be lower than the upper surface of the pad pattern. The semiconductor device may have a high reliability.

SEMICONDCUTOR PACKAGE AND MANUFACTURING METHOD THEREOF

A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has a redistribution layer, at least one die over the redistribution layer, through interlayer vias on the redistribution layer and aside the die and a molding compound encapsulating the die and the through interlayer vias disposed on the redistribution layer. The semiconductor package has connectors connected to the through interlayer vias and a protection film covering the molding compound and the die. The protection film is formed by a printing process. 1. A semiconductor package comprising:a redistribution layer;at least one die, disposed on the redistribution layer;a molding compound, disposed on the redistribution layer and encapsulating the at least one die;through interlayer vias, disposed on the redistribution layer and penetrating the molding compound, wherein the through interlayer vias are electrically connected to the redistribution layer and the at least one die;a protection film, disposed on the molding compound and the at least one die, wherein the protection film located on the at least one die includes a trench pattern with trenches of substantially flat bottoms;connectors, disposed on the through interlayer vias; andconductive elements, electrically connected to the redistribution layer.2. The semiconductor package as claimed in claim 1 , further comprising a dielectric material layer disposed on the molding compound claim 1 , on the at least one die and disposed between the molding compound claim 1 , the at least one die and the protection film claim 1 , wherein the dielectric material layer exposes the through interlayer vias.3. The semiconductor package as claimed in claim 2 , wherein the dielectric material layer located on the molding compound includes first openings and the connectors located within the first openings are in direct contact with the through interlayer vias.4. The semiconductor package as claimed in claim 3 ...

RF DEVICES WITH ENHANCED PERFORMANCE AND METHODS OF FORMING THE SAME

The present disclosure relates to a radio frequency device that includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion, first bump structures, a first mold compound, and a second mold compound. The FEOL portion includes an active layer, a contact layer, and isolation sections. Herein, the active layer and the isolation sections reside over the contact layer, and the active layer is surrounded by the isolation sections. The BEOL portion is formed underneath the FEOL portion, and the first bump structures and the first mold compound are formed underneath the BEOL portion. Each first bump structure is partially encapsulated by the first mold compound, and electrically coupled to the FEOL portion via connecting layers within the BEOL portion. The second mold compound resides over the active layer without a silicon material, which has a resistivity between 5 Ohm-cm and 30000 Ohm-cm, in between. 1. An apparatus comprising: the BEOL portion comprises a plurality of connecting layers;', 'the FEOL portion comprises an active layer, a contact layer, and isolation sections;', 'the active layer and the isolation sections reside over the contact layer, and the isolation sections surround the active layer;', 'the active layer does not extend vertically beyond the isolation sections;, 'a device region including a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion residing over the BEOL portion, whereina plurality of first bump structures formed at a bottom surface of the BEOL portion, wherein the plurality of first bump structures is electrically coupled to the FEOL portion via the plurality of connecting layers;a first mold compound formed over the bottom surface of the BEOL portion and partially encapsulating each of the plurality of first bump structures, wherein a bottom portion of each of the plurality of first bump structures is not covered by the first mold compound; anda second mold compound residing over ...

DEVICE CONTAINING AND METHOD OF PROVIDING CARBON COVERED COPPER LAYER

A device and method of preventing corrosion of a copper layer in a PCB is disclosed. A first dielectric is disposed on a substrate. A copper layer is plated in an opening in the first dielectric and, after conditioning the copper layer, a redistribution layer is plated on the copper layer. A solder resist layer is disposed above the copper layer. A solder ball is disposed in an opening in the solder resist layer. The solder ball is in conductive contact with the copper layer and in physical contact with the redistribution layer. A non-conductive carbon layer is disposed on and in contact with the redistribution layer or tsi-diehe solder resist layer. The carbon layer is substantially thinner than the copper layer and acts as a diffusion barrier to moisture for the copper layer. 1. A device comprising:a substrate comprising at least one of a semiconductor or mold compound;a first dielectric disposed on substrate;a copper layer plated in an opening in the first dielectric;a solder resist layer above the copper layer;a solder ball in an opening in the solder resist layer, the solder ball in conductive contact with the copper layer; anda non-conductive carbon layer on the substrate, the non-conductive carbon layer formed from carbon rather than a carbon compound and configured to act as a diffusion barrier to moisture for the copper layer.2. The device of claim 1 , wherein the carbon layer is disposed on the substrate below the first dielectric.3. The device of claim 1 , wherein the carbon layer is disposed between the solder resist layer and the first dielectric.4. The device of claim 1 , wherein the carbon layer is disposed on the solder resist layer.5. The device of claim 4 , wherein the carbon layer is further disposed on at least one of the solder ball or an interconnect element.6. The device of claim 4 , wherein the carbon layer is adjacent to the solder ball and the solder ball is free from the carbon layer.7. The device of claim 1 , further comprising:a ...

Method of packaging chip and chip package structure

A method of packaging a chip includes laminating a first substrate with a second substrate, the first substrate being capable of withstanding a greater stress than the second substrate; applying an adhesive layer on the second substrate; bonding the chip on the adhesive layer; and forming an encapsulation layer that covers at least the chip.

OFFSET TEST PADS FOR WLCSP FINAL TEST

A device configured for WLCSP, can include: a first pad; a test pad offset from the first pad; a first RDL path that connects the first pad to the test pad; and a second RDL path that connects the test pad to a solder ball. In another case, a device configured for WLCSP can include: a first pad; a test pad offset from the first pad; a first RDL path that connects the first pad to a solder ball; and a second RDL path that connects the test pad to the solder ball. A wafer having devices configured for WLCSP, can include: a first device having a first pad; a second device having a test pad; a first RDL path that connects the first pad to a solder ball; and a second RDL path that connects the test pad to the solder ball. 1. A device configured for wafer level chip scale packaging (WLCSP) , the device comprising:a) a first pad;b) a test pad offset from the first pad;c) a first redistribution layer (RDL) path that connects the first pad to the test pad; andd) a second RDL path that connects the test pad to a solder ball.2. The device of claim 1 , wherein the device comprises a serial non-volatile memory (NVM) device.3. The device of claim 1 , wherein the first and second RDL paths are in a same layer.4. The device of claim 1 , wherein the first and second RDL paths are in different layers.5. The device of claim 1 , further comprising a polymer layer that fully covers the first pad claim 1 , and leaves a portion of the test pad exposed.6. The device of claim 1 , wherein the device further comprises:a) a plurality of the first pads; andb) a plurality of the test pads, where each of the plurality of the test pads is offset from a corresponding of the plurality of the first pads by a same offset length.7. A device configured for WLCSP claim 1 , the device comprising:a) a first pad;b) a test pad offset from the first pad;c) a first RDL path that connects the first pad to a solder ball; andd) a second RDL path that connects the test pad to the solder ball.8. The device of claim ...

Semiconductor Device with Shielding Structure for Cross-Talk Reduction

A method includes embedding a die in a molding material; forming a first dielectric layer over the molding material and the die; forming a conductive line over an upper surface of the first dielectric layer facing away from the die; and forming a second dielectric layer over the first dielectric layer and the conductive line. The method further includes forming a first trench opening extending through the first dielectric layer or the second dielectric layer, where a longitudinal axis of the first trench is parallel with a longitudinal axis of the conductive line, and where no electrically conductive feature is exposed at a bottom of the first trench opening; and filling the first trench opening with an electrically conductive material to form a first ground trench.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, a first metal layer located on the first semiconductor substrate, a second metal layer located on the second semiconductor substrate, a third metal layer, a first alloy layer, and a second alloy layer. The third metal layer extends between the first metal layer and the second metal layer. The first alloy layer comprises components of the first and third metal layers, and is provided between the first metal layer and the third metal layer. The second alloy layer comprises components of the second and third metal layers, and is provided between the second metal layer and the third metal layer. At least one of the first metal the second metal layers projects into the third metal layer at a circumferential edge portion thereof. 1. A semiconductor device comprising:a first semiconductor substrate;a second semiconductor substrate facing the first semiconductor substrate;a first pad electrode disposed on a surface of the first semiconductor substrate facing the second semiconductor substrate;a second pad electrode disposed on a surface of the second semiconductor substrate facing the first semiconductor substrate;a first insulating layer disposed on an edge portion of the first pad electrode and the first semiconductor substrate;a second insulating layer disposed on an edge portion of the second pad electrode and the second semiconductor substrate;a first metal layer disposed over the first pad electrode and facing the second semiconductor substrate;a second metal layer disposed over the second pad electrode and facing the first semiconductor substrate;a third metal layer disposed between the first metal layer and the second metal layer;a first alloy layer disposed between the first metal layer and the third metal layer and comprising a component of the first metal layer and a component of the third metal layer; anda second alloy layer disposed between the second metal layer ...

THREE-DIMENSIONAL INTEGRATED FAN-OUT WAFER LEVEL PACKAGE

An integrated fan-out wafer level package houses a semiconductor package having a first semiconductor die encapsulated by a dielectric compound. A plurality of redistribution layers are formed on a first side of the semiconductor package which are in electrical contact with contact pads of the first semiconductor die. A plurality of solder balls located on the first side of the semiconductor package is electrically connected to the contact pads of the semiconductor die via the redistribution layers. A second semiconductor die is further attached to the first side of the semiconductor package and is electrically connected to the contact pads of the first semiconductor die via the redistribution layers. 1. An integrated fan-out wafer level package comprising:a semiconductor package comprising a first semiconductor die encapsulated by a dielectric compound;a plurality of redistribution layers formed on a first side of the semiconductor package in electrical contact with contact pads of the first semiconductor die;a plurality of solder balls located on the first side of the semiconductor package and electrically connected to the contact pads of the semiconductor die via the redistribution layers; anda second semiconductor die attached to the first side of the semiconductor package and electrically connected to the contact pads of the first semiconductor die via the redistribution layers; anda plurality of wire bond pads formed on the redistribution layers on the first side of the semiconductor package and wire bonds directly connecting the second semiconductor die to the wire bond pads.2. The integrated fan-out wafer level package as claimed in claim 1 , wherein the plurality of solder balls is arranged for electrically mounting the integrated fan-out wafer level package onto a printed circuit board.3. The integrated fan-out wafer level package as claimed in claim 1 , wherein the first semiconductor die comprises an application processor chip.4. The integrated fan-out ...

Single-Shot Encapsulation

A semiconductor device includes a semiconductor wafer. A plurality of pillar bumps is formed over the semiconductor wafer. A solder is deposited over the pillar bumps. The semiconductor wafer is singulated into a plurality of semiconductor die after forming the pillar bumps while the semiconductor wafer is on a carrier. An encapsulant is deposited around the semiconductor die and pillar bumps while the semiconductor die remains on the carrier. The encapsulant covers an active surface of the semiconductor die between the pillar bumps. 1. A method of making a semiconductor device , comprising:providing a semiconductor wafer;forming a plurality of pillar bumps over the wafer;singulating the semiconductor wafer into a plurality of semiconductor die; anddepositing an encapsulant over the semiconductor die with the pillar bumps exposed from the encapsulant.2. The method of claim 1 , wherein the pillar bumps include solder caps.3. The method of claim 2 , wherein the solder caps include lead-free solder.4. The method of claim 1 , further including transfer-mounting the semiconductor die prior to depositing the encapsulant.5. The method of claim 1 , further including singulating the semiconductor die through the encapsulant.6. The method of claim 5 , further including singulating the semiconductor die with a plurality of semiconductor die packaged together.7. A method of making a semiconductor device claim 5 , comprising:providing a semiconductor die;forming a pillar bump over the semiconductor die;forming a solder cap over the pillar bump; anddepositing an encapsulant over the semiconductor die, pillar bump, and solder cap.8. The method of claim 7 , wherein a surface of the encapsulant is coplanar with a surface of the solder cap.9. The method of claim 7 , further including disposing the semiconductor die over a substrate after depositing the encapsulant claim 7 , wherein the encapsulant contacts the substrate.10. The method of claim 9 , further including reflowing the ...

LOGIC DRIVE USING STANDARD COMMODITY PROGRAMMABLE LOGIC IC CHIPS COMPRISING NON-VOLATILE RANDOM ACCESS MEMORY CELLS

A multi-chip package includes a field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a truth table, wherein the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip comprises multiple non-volatile memory cells therein configured to store multiple resulting values of the truth table, and a programmable logic block therein configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output; and a memory chip coupling to the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip, wherein a data bit width between the field-programmable-gate-array (FPGA) integrated-circuit (IC) chip and the memory chip is greater than or equal to 64. 1. A chip package comprising:a non-volatile memory cell configured to store resulting data of a look-up table (LUT) therein;a sense amplifier configured to sense input data thereof associated with the resulting data of the look-up table (LUT) stored in the non-volatile memory cell to generate output data of the sense amplifier;a logic circuit comprising a static-random-access-memory (SRAM) cell configured to store first data therein associated with the output data of the sense amplifier, and a selection circuit comprising a first set of input points for a first input data set for input data of a logic operation and a second set of input points for a second input data set having second data associated with the first data stored in the static-random-access-memory (SRAM) cell, wherein the selection circuit is configured to select, in accordance with the first input data set, input data from the second input data set as output data of the logic operation; anda plurality of metal bumps at a bottom of the chip package, wherein the plurality of metal bumps comprise five metal bumps arranged in a line.2. The chip package of claim 1 , wherein the sense amplifier and logic circuit are provided by a ...

SEMICONDUCTOR PACKAGE DEVICE AND MANUFACTURING METHOD THEREOF

A method of manufacturing a semiconductor device including providing a die, forming a pad on the die, disposing a first polymer over the die, patterning the first polymer with an opening over the pad, disposing a sacrificial layer over the patterned first polymer, disposing a molding surrounding the die, removing a portion of the molding thereby exposing the sacrificial layer, removing the sacrificial layer thereby exposing the pad and the first polymer, disposing a second polymer on the first polymer, patterning the second polymer with the opening over the pad, and disposing a conductive material on the pad within the opening. 1. A method of manufacturing a semiconductor device , comprising:providing a die;forming a pad on the die;disposing a first polymer over the die;patterning the first polymer with an opening over the pad;disposing a sacrificial layer over the patterned first polymer;disposing a molding surrounding the die;removing a portion of the molding thereby exposing the sacrificial layer;removing the sacrificial layer thereby exposing the pad and the first polymer;disposing a second polymer an the first polymer;patterning the second polymer with the opening over the pad; anddisposing a conductive material on the pad within the opening.2. The method of claim 1 , wherein the first polymer is surrounded by the molding.3. The method of claim 1 , wherein a portion of the pad is exposed from the first polymer.4. method of claim 1 , wherein the opening is disposed between the sacrificial layer and the pad.5. method of claim 1 , wherein the sacrificial layer includes a polymeric material.6. The method of claim 1 , wherein the molding is disposed over the sacrificial layer.7. The method of claim 1 , wherein the patterning the first polymer is performed by photolithography and etching operations.8. The method of claim 1 , wherein the removing the sacrificial layer is performed by etching operations.9. The method of claim 1 , wherein the removing the portion of the ...

RDL-FIRST PACKAGING PROCESS

A method includes forming a first plurality of Redistribution Lines (RDLs) over a carrier, and bonding a device die to the first plurality of RDLs through flip-chip bonding. The device die and the first plurality of RDLs are over the carrier. The device die is molded in a molding material. After the molding, the carrier is detached from the first plurality of RDLs. The method further includes forming solder balls to electrically couple to the first plurality of RDLs, wherein the solder balls and the device die are on opposite sides of the first plurality of RDLs. 1. A method comprising:forming a first plurality of Redistribution Lines (RDLs) over a carrier;bonding a device die to the first plurality of RDLs through flip-chip bonding, wherein the device dies and the first plurality of RDLs are over the carrier;molding the device die in a molding material;after the molding, detaching the carrier from the first plurality of RDLs; andforming solder balls to electrically couple to the first plurality of RDLs, wherein the solder balls and the device die are on opposite sides of the first plurality of RDLs.2. The method of further comprising forming a plurality of through-vias electrically coupled to the first plurality of RDLs claim 1 , wherein during the molding claim 1 , the plurality of through-vias are molded in the molding material.3. The method of further comprising claim 2 , after the forming the solder balls claim 2 , grinding the molding material to reveal the plurality of through-vias.4. The method of further comprising:before the forming the solder balls and before the detaching the carrier, grinding the molding material to reveal the plurality of through-vias; andafter the grinding the molding material and before the detaching the carrier, forming a plurality of solder regions on the plurality of through-vias.5. The method of further comprising:plating a plurality of solder regions over the plurality of through-vias, with edges of the plurality of solder ...

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

A manufacturing method of a package structure is described. The method includes at least the following steps. A carrier is provided. A semiconductor die and a sacrificial structure are disposed on the carrier. The semiconductor die is electrically connected to the bonding pads on the sacrificial structure through a plurality of conductive wires. As encapsulant is formed on the carrier to encapsulate the semiconductor die, the sacrificial structure and the conductive wires. The carrier is debonded, and at least a portion of the sacrificial structure is removed through a thinning process. A redistribution layer is formed on the semiconductor die and the encapsulant. The redistribution layer is electrically connected to the semiconductor die through the conductive wires. 1. A manufacturing method of a package structure , comprising:providing a carrier,disposing a semiconductor die and at least one sacrificial structure on the carrier;electrically connecting the semiconductor die to bonding pads on the sacrificial structure through a plurality of conductive wires;forming an encapsulant on the carrier to encapsulate the semiconductor die, the sacrificial structure and the conductive wires;debonding the carrier,removing at least a portion of the sacrificial structure through a thinning process; andforming a redistribution layer on the semiconductor die and the encapsulant, the redistribution layer is electrically connected to the semiconductor die through the conductive wires.2. The manufacturing method of a package structure according to claim 1 , wherein the sacrificial structure is disposed on the carrier claim 1 , and the semiconductor die is disposed on the sacrificial structure.3. The manufacturing method of a package structure according to claim 2 , wherein a width of the sacrificial structure is greater than a width of the semiconductor die.4. The manufacturing method of a package structure according to claim 2 , wherein the redistribution layer is formed on the ...

Wafer-level packaging for enhanced performance

The present disclosure relates to a mold module that includes a device layer, a number of first bump structures, a first mold compound, a stop layer, and a second mold compound. The device layer includes a number of input/output (I/O) contacts at a top surface of the device layer. Each first bump structure is formed over the device layer and electronically coupled to a corresponding I/O contact. The first mold compound resides over the device layer, and a portion of each first bump structure is exposed through the first mold compound. The stop layer is formed underneath the device layer. The second mold compound resides underneath the stop layer, such that the stop layer separates the device layer from the second mold compound.

WAFER-LEVEL PACKAGING FOR ENHANCED PERFORMANCE

The present disclosure relates to a wafer-level packaging process. According to an exemplary process, a precursor wafer that includes a device layer with a number of input/output (I/O) contacts, a number of bump structures over the device layer, the stop layer underneath the device layer, and a silicon handle layer underneath the stop layer is provided. Herein, each bump structure is electronically coupled to a corresponding I/O contact. A first mold compound is then applied over the device layer to encapsulate each bump structure. Next, the silicon handle layer is removed substantially. A second mold compound is applied to an exposed surface from which the silicon handle layer was removed. Finally, the first mold compound is thinned down to expose a portion of each bump structure. 1. A method comprising: the device layer has a plurality of input/output (I/O) contacts at a top surface of the device layer;', 'the plurality of first bump structures are formed over the device layer, wherein each of the plurality of first bump structures is electronically coupled to a corresponding I/O contact;', 'the stop layer resides underneath the device layer; and', 'the silicon handle layer resides underneath the stop layer, such that the stop layer separates the device layer from the silicon handle layer;, 'providing a precursor wafer that includes a silicon handle layer, a stop layer, a device layer, and a plurality of first bump structures, whereinapplying a first mold compound over the device layer to encapsulate each of the plurality of first bump structures;removing substantially the silicon handle layer;applying a second mold compound to an exposed surface from which the silicon handle layer was removed; andthinning down the first mold compound to provide a mold wafer, wherein a portion of each of the plurality of first bump structures is exposed.2. The method of wherein removing substantially the silicon handle layer is provided by one of a group consisting of chemical ...

Semiconductor package and manufacturing method thereof

A method of forming a Fan-Out Wafer Level semiconductor device includes forming only a plurality of metal bonding pads on a glass carrier. Electrode pads of a semiconductor chip are coupled to the plurality of metal bonding pads. The semiconductor chip and the plurality of metal bonding pads are encapsulated with a molding compound. The glass carrier can then be removed to expose a surface of the FOWLP structure. A redistribution layer is then formed on the exposed surface of the FOWLP structure. At least one metal trace within the redistribution layer is in electrical contact with the plurality of metal bonding pads. Solder balls may be mounted on the redistribution layer to provide electrical contact between the solder balls and the electrode pads of the semiconductor chip. 1: A Fan-Out Wafer Level semiconductor device comprising:a plurality of metal bonding pads coplanar to each other;a passivation layer surrounding the plurality of metal bonding pads;a semiconductor chip having an active surface whereon a plurality of electrode pads are formed, the plurality of electrode pads is correspondingly coupled to and electrically connected with the plurality of metal bonding pads;a molding compound encapsulating the semiconductor chip and the plurality of metal bonding pads, the molding compound having a surface coplanar to a surface of each of the plurality of metal bonding pads, the molding compound, the passivation layer, and the plurality of metal bonding pads all disposed on a same side of the surface coplanar to the surface of each of the plurality of metal bonding pads; anda redistribution layer formed on the molding compound and electrically connected to the plurality of metal bonding pads.2: The Fan-Out Wafer Level semiconductor device of further comprising the metal bonding pads are formed on another passivation layer and surrounded by the passivation layer.3: The Fan-Out Wafer Level semiconductor device of further comprising a conductive layer formed to have ...

SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor package device includes a carrier, a first electronic component, and a conductive element on the carrier. The first electronic component is over the carrier. The conductive element is on the carrier and electrically connects the first electronic component to the carrier. The conductive element includes at least one conductive particle and a solder material covering the conductive particle, and the conductive particle includes a metal core, a barrier layer covering the metal core, and a metal layer covering the barrier layer. 1. A conductive particle , comprising:a metal core;a barrier layer surrounding the metal core;a first conductive layer surrounding the barrier layer; anda second conductive layer surrounding the first conductive layer,wherein a ratio of a sum of volumes of the metal core, the barrier layer and the first conductive layer to a volume of the second conductive layer is from about 0.1 to about 200.21. The conductive particle of claim 1 , wherein a ratio of a thickness (t) of the second conductive layer to a distance (r) between a center of the metal core and an outer surface of the first conductive layer is from about 0.04 to about 110.31. The conductive particle of claim 2 , wherein about 0.05 micrometers (μm) Подробнее

SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device package includes an electronic component, a first set of conductive wires electrically connected to the electronic component, and an insulation layer surrounding the first set of conductive wires. The insulation layer exposes a portion of the first set of the conductive wires. The insulation layer is devoid of a filler. 1. A semiconductor device package , comprising:an electronic component;a first set of conductive wires electrically connected to the electronic component; andan insulation layer having a top surface and surrounding the first set of conductive wires, the top surface of the insulation layer exposing a portion of the first set of the conductive wires,wherein the insulation layer is devoid of a filler.2. The semiconductor device package of claim 1 , further comprising an encapsulant encapsulating the electronic component and the insulation layer.3. The semiconductor device package of claim 1 , further comprising a first patterned conductive layer disposed over the insulation layer and including a plurality of conductive pads claim 1 , wherein the conductive pads of the first patterned conductive layer are respectively electrically connected to the exposed portion of the first set of conductive wires.4. The semiconductor device package of claim 3 , whereinthe electronic component comprises a plurality of conductive contacts electrically connected to the first set of the conductive wires; anda pitch between at least two adjacent conductive contacts of the electronic component is less than a pitch between at least two adjacent conductive pads of the first patterned conductive layer.5. The semiconductor device package of claim 1 , further comprising a second set of conductive wires disposed on the insulation layer and electrically connected to the exposed portion of the first set of the conductive wires.6. The semiconductor device package of claim 5 , further comprising an encapsulant covering the electronic component claim 5 , the ...

Interconnect structures with intermetallic palladium joints and associated systems and methods

Interconnect structures with intermetallic palladium joints are disclosed herein. In one embodiment, a method of forming an interconnect structure includes depositing a first conductive material comprising nickel on a first conductive surface of a first die, and depositing a second conductive material comprising nickel on a second conductive surface of a second die spaced apart from the first surface. The method further includes depositing a third conductive material on the second conductive material, and thermally compressing tin/solder between the first and third conductive materials to form an intermetallic palladium joint that extends between the first conductive material and the second conductive material such that one end of the intermetallic palladium joint is bonded directly to the first conductive material and an opposite end of the intermetallic palladium joint is bonded directly to the second conductive material.

PACKAGING METHOD AND PACKAGE STRUCTURE FOR FINGERPRINT RECOGNITION CHIP AND DRIVE CHIP

A packaging method and a package structure for a fingerprint recognition chip and a drive chip are provided. The packaging method is a wafer-level packaging method. According to the method, a blind hole is formed on the back surface of a wafer and the drive chip is secured in the blind hole, then the wafer is cut to obtain a package structure for the fingerprint recognition chip and the drive chip. In this way, the drive chip is packaged in the back surface of the wafer-level fingerprint recognition chip, thereby reducing the complexity of the package process. In addition, the size of the package structure is close to the size of the single fingerprint recognition chip, thereby greatly reducing the size of the package structure and improving the integration of the package structure. 1. A packaging method for a fingerprint recognition chip and a drive chip , comprising:preparing a wafer and a drive chip, wherein the wafer has a first surface and a second surface facing away from the first surface, the first surface of the wafer is provided with a fingerprint recognition chip, the drive chip has a first surface and a second surface facing away from the first surface, and the first surface of the drive chip is provided with a drive circuit and a second contact pad;forming a blind hole from the second surface of the wafer;securing the drive chip in the blind hole, with the first surface of the drive chip being flush with the second surface of the wafer; andcutting the wafer.2. The packaging method according to claim 1 , wherein the fingerprint recognition chip comprises a sensing region and a first contact pad around the sensing region claim 1 , and the blind hole is formed in a region corresponding to the sensing region of the fingerprint recognition chip.3. The packaging method according to claim 2 , wherein after the securing the drive chip in the blind hole and before the cutting the wafer claim 2 , the packaging method further comprises:forming a through hole from ...

METHOD OF MANUFACTURING 3DIC STRUCTURE

A method of manufacturing a 3DIC structure includes the following processes. A die is bonded to a wafer. A first dielectric layer is formed on the wafer and laterally aside the die. A second dielectric material layer is formed on the die and the first dielectric layer. A portion of the second dielectric material layer over a non-edge region of the wafer is selectively removed to form a protruding portion over an edge region of the wafer. The second dielectric material layer is planarized to form a second dielectric layer on the first dielectric layer and the die. A bonding film is formed on the second dielectric layer. A carrier is bonded to the wafer through the bonding film. 1. A method of manufacturing a 3DIC structure , comprising:bonding a die to a wafer;forming a first dielectric layer on the wafer and laterally aside the die;forming a second dielectric material layer on the die and the first dielectric layer;selectively removing a portion of the second dielectric material layer over a non-edge region of the wafer to form a protruding portion over an edge region of the wafer; andplanarizing the second dielectric material layer to form a second dielectric layer on the first dielectric layer and the die.2. The method of claim 1 , where the selectively removing the portion of the second dielectric material layer comprises:forming a mask layer on the second dielectric material layer;pattering the mask layer to form a patterned mask layer having an opening, wherein the patterned mask layer covers the second dielectric material layer on the edge region of the wafer, and the opening exposes the portion of the second dielectric material layer over the non-edge region of the wafer;etching the portion of the second dielectric material layer exposed by the opening, wherein the second dielectric material layer covered by the patterned mask layer form the protruding portion; andremoving the patterned mask layer.3. The method of claim 1 , wherein the planarizing the second ...

Semiconductor Structure and Method of Forming the Same

A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region. 1. A structure comprising:a device die;an encapsulant encapsulating the device die therein;a first plurality of Redistribution Lines (RDLs) overlying and electrically coupling to the device die, wherein the first plurality of RDLs have a first pitch, and the first plurality of RDLs are substantially free from undercuts; anda second plurality of RDLs overlying and electrically coupling to the device die, wherein the second plurality of RDLs have a second pitch greater than the first pitch, and the second plurality of RDLs have undercuts.2. The structure of claim 1 , wherein each of the first plurality of RDLs and the second plurality of RDLs comprises an adhesion layer and a metal region over the adhesion layer claim 1 , wherein the adhesion layers in the first plurality of RDLs are free from undercuts claim 1 , and the adhesion layers in the second plurality of RDLs have undercuts.3. The structure of claim 1 , wherein all RDLs at a same level as the first plurality of RDLs are substantially free from undercuts claim 1 , and all RDLs at a same level as the second plurality of RDLs have undercuts.4. The structure of claim 1 , wherein all RDLs at levels underlying the first plurality of RDLs and over the device die are substantially free from ...

Semiconductor Device and Method of Forming EMI Shielding Layer with Conductive Material Around Semiconductor Die

A semiconductor device has a plurality of first semiconductor die mounted over an interface layer formed over a temporary carrier. An encapsulant is deposited over the first die and carrier. A flat shielding layer is formed over the encapsulant. A channel is formed through the shielding layer and encapsulant down to the interface layer. A conductive material is deposited in the channel and electrically connected to the shielding layer. The interface layer and carrier are removed. An interconnect structure is formed over conductive material, encapsulant, and first die. The conductive material is electrically connected through the interconnect structure to a ground point. The conductive material is singulated to separate the first die. A second semiconductor die can be mounted over the first die such that the shielding layer covers the second die and the conductive material surrounds the second die or the first and second die. 1. A method of making a semiconductor device , comprising:providing a first semiconductor die;depositing an encapsulant around the first semiconductor die;forming a shielding layer over the first semiconductor die;forming a channel through the encapsulant around the first semiconductor die;depositing a conductive material in the channel around the first semiconductor die and electrically connected to the shielding layer; andforming an interconnect structure over the conductive material, encapsulant, and first semiconductor die, wherein the interconnect structure is electrically connected to the conductive material.2. The method of claim 1 , wherein the conductive material extends into the interconnect structure.3. The method of claim 1 , wherein the conductive material terminates at a boundary between the encapsulant and interconnect structure.4. The method of claim 1 , further including providing side-by-side first semiconductor die each covered by the shielding layer and surrounded by the conductive material.5. The method of claim 1 , further ...

Semiconductor device for detection of radiation and method of producing a semiconductor device for detection of radiation

The semiconductor device for detection of radiation comprises a semiconductor substrate ( 1 ) with a main surface ( 11 ), a dielectric layer ( 6 ) comprising at least one compound of a semiconductor material, an integrated circuit ( 2 ) including at least one component sensitive to radiation ( 3 ), a wiring ( 4 ) of the integrated circuit embedded in an intermetal layer ( 8 ) of the dielectric layer ( 6 ), an electrically conductive through-substrate via ( 5 ) contacting the wiring, and an optical filter element ( 7 ) arranged immediately on the dielectric layer above the component sensitive to radiation. The dielectric layer comprises a passivation layer ( 9 ) at least above the through-substrate via, the passivation layer comprises a dielectric material that is different from the intermetal layer ( 8 ), and the wiring is arranged between the main surface and the passivation layer.

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure includes a conductive bump, and a ferromagnetic member extended within the conductive bump, wherein a center of the conductive bump is disposed on a central axis of the ferromagnetic member. 2. The semiconductor structure of claim 1 , wherein the ferromagnetic member is entirely enclosed by the conductive bump.3. The semiconductor structure of claim 1 , wherein an end of the ferromagnetic member is exposed from the conductive bump.4. The semiconductor structure of claim 1 , wherein an end of the ferromagnetic member is coupled with an outer surface of the conductive bump.5. The semiconductor structure of claim 1 , wherein the conductive bump is in a spherical claim 1 , hemispherical or cylindrical shape.6. The semiconductor structure of claim 1 , wherein a width of the ferromagnetic member is substantially smaller than a length of the ferromagnetic member.7. The semiconductor structure of claim 1 , wherein the ferromagnetic member has a ratio of a width to a length of about 1:1.5 to about 1:30.9. The semiconductor structure of claim 8 , wherein a central axis of the ferromagnetic member passes through the first end and the second end.10. The semiconductor structure of claim 9 , wherein the central axis of the ferromagnetic member is substantially orthogonal to the substrate.11. The semiconductor structure of claim 8 , wherein the substrate includes a conductive trace extended within the substrate claim 8 , and the conductive bump is coupled with at least a portion of the conductive trace.12. The semiconductor structure of claim 11 , wherein the second end of the ferromagnetic member is coupled with at least a portion of the conductive trace.13. The semiconductor structure of claim 8 , wherein the conductive bump is disposed at a corner of the substrate.14. The semiconductor structure of claim 8 , wherein a cross section of the first end exposed from the conductive bump in a circular claim 8 , quadrilateral or cross shape.16. The method of ...

SEMICONDUCTOR DEVICE WITH REDISTRIBUTION LAYERS ON PARTIAL ENCAPSULATION AND NON-PHOTOSENSITIVE PASSIVATION LAYERS

A semiconductor device with redistribution layers on partial encapsulation is disclosed and may include providing a carrier with a non-photosensitive protection layer, forming a pattern in the non-photosensitive protection layer, providing a semiconductor die with a contact pad on a first surface, and bonding the semiconductor die to the non-photosensitive protection layer such that the contact pad aligns with the pattern formed in the non-photosensitive protection layer. A second surface opposite to the first surface of the semiconductor die, side surfaces between the first and second surfaces of the semiconductor die, and a portion of a first surface of the non-photosensitive protection layer may be encapsulated with an encapsulant. The carrier may be removed leaving the non-photosensitive protection layer bonded to the semiconductor die. A redistribution layer may be formed on the contact pad and a second surface of the non-photosensitive protection layer opposite to the first surface. 1. A method for manufacturing a semiconductor device , the method comprising:providing a carrier with a non-photosensitive protection layer;forming a pattern in the non-photosensitive protection layer;providing a semiconductor die with a contact pad on a first surface;bonding the semiconductor die to the non-photosensitive protection layer such that the contact pad aligns with the pattern formed in the non-photosensitive protection layer;encapsulating a second surface opposite to the first surface of the semiconductor die, side surfaces between the first and second surfaces of the semiconductor die, and a portion of a first surface of the non-photosensitive protection layer with an encapsulant;removing the carrier and leaving the non-photosensitive protection layer bonded to the semiconductor die; andforming a redistribution layer on the contact pad and a second surface of the non-photosensitive protection layer opposite to the first surface.2. The method according to claim 1 , ...

Packaging Devices and Methods of Manufacture Thereof

Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a method of manufacturing a packaging device includes forming an interconnect wiring over a substrate, and forming conductive balls over portions of the interconnect wiring. A molding material is deposited over the conductive balls and the substrate, and a portion of the molding material is removed from over scribe line regions of the substrate. 1. A packaging device comprising:a contact pad over a circuit region of a substrate, the substrate comprising a seal ring proximate a perimeter of the circuit region;a passivation layer over the substrate and over a first portion of the contact pad;a post passivation interconnect (PPI) structure over the passivation layer, wherein the PPI structure is coupled to a second portion of the contact pad;a conductive ball coupled to the PPI structure; anda molding material around the conductive ball, over the PPI structure, and over the passivation layer, wherein the molding material comprises a first thickness directly over the seal ring and a second thickness proximate the conductive ball, the second thickness being greater than the first thickness.2. The package device of claim 1 , wherein the molding material comprises:a first upper surface directly over the seal ring;a second upper surface proximate the conductive ball; anda slanted sidewall connecting the first upper surface and the second upper surface.3. The package device of claim 1 , wherein the conductive ball extends above an uppermost surface of the molding material.4. The package device of claim 1 , wherein the first thickness is about 30 μm or less.5. The package device of claim 1 , wherein the seal ring extends from a first surface of the passivation layer distal the substrate to a second surface of the passivation layer opposing the first surface.6. The package device of claim 5 , wherein the seal ring further extends into the substrate.7. The package ...

Semiconductor device and a manufacturing method thereof

A semiconductor device including: a substrate; a via which penetrates the substrate; a via insulating film formed along an inner wall of the via; and a core plug which fills the via, wherein a residual stress of the via insulating film is 60 MPa to −100 MPa.

METHOD OF FORMING SEMICONDUCTOR DEVICE HAVING A DUAL MATERIAL REDISTRIBUTION LINE AND SEMICONDUCTOR DEVICE

A method of making a semiconductor device includes depositing a second conductive material over a first conductive material, wherein the second conductive material is different from the first conductive material, and the second conductive material defines a redistribution line (RDL). The method further includes depositing a passivation layer over the RDL, wherein depositing the passivation layer comprises forming a plurality of convex sidewalls, and each of the plurality of convex sidewalls extends beyond an edge of the RDL. 1. A method of making a semiconductor device , the method comprising:depositing a second conductive material over a first conductive material, wherein the second conductive material is different from the first conductive material, and the second conductive material defines a redistribution line (RDL); anddepositing a passivation layer over the RDL, wherein depositing the passivation layer comprises forming a plurality of convex sidewalls, and each of the plurality of convex sidewalls extends beyond an edge of the RDL.2. The method of claim 1 , wherein depositing the second conductive material comprises depositing aluminum.3. The method of claim 1 , further comprising depositing the first conductive material over an interconnect structure.4. The method of claim 3 , wherein depositing the first conductive material comprises depositing a copper containing material.5. The method of claim 1 , further comprising patterning the second conductive material to define the RDL.6. The method of claim 1 , wherein depositing the passivation layer comprises depositing the passivation layer to define a flat top surface of the passivation layer over the RDL.7. The method of claim 1 , wherein depositing the passivation layer comprises depositing the passivation layer to a thickness ranging from about 200 nanometers (nm) to about 2 claim 1 ,000 nm.8. A method of making a semiconductor device claim 1 , the method comprising:plating a first conductive material over ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device including a relatively thin interposer excluding a through silicon hole and a manufacturing method thereof are provided. The method includes forming an interposer on a dummy substrate. The forming of the interposer includes, forming a dielectric layer on the dummy substrate, forming a pattern and a via on the dielectric layer, and forming a seed layer at the pattern and the via of the dielectric layer and forming a redistribution layer and a conductive via on the seed layer. A semiconductor die is connected with the conductive via facing an upper portion of the interposer, and the semiconductor die is encapsulated with an encapsulant. The dummy substrate is removed from the interposer. A bump is connected with the conductive via facing a lower portion of the interposer. 120-. (canceled)21. A semiconductor device comprising: a first interposer side;', 'a second interposer side opposite the first interposer side;', 'a first dielectric layer at the first interposer side;', 'a first conductive via that extends through at least the first dielectric layer;', 'a second conductive via at the second interposer side; and', 'a redistribution structure in contact with the first dielectric layer and electrically connected to the first conductive via and the second conductive via;, 'an interposer comprising a first die side that faces away from the first interposer side;', 'a second die side that faces toward the first interposer side and comprises a die connection terminal that is coupled to the first conductive via; and', 'a lateral die side that extends between the first die side and the second die side;, 'a semiconductor die comprising the encapsulating material comprises an uppermost surface facing away from the interposer, a lowermost surface facing the interposer, and a lateral surface that extends entirely between the uppermost surface and the lowermost surface;', 'no portion of the encapsulating material is substantially vertically higher than the ...

Advanced INFO POP and Method of Forming Thereof

In accordance with some embodiments, a package-on-package (PoP) structure includes a first semiconductor package having a first side and a second side opposing the first side, a second semiconductor package having a first side and a second side opposing the first side, and a plurality of inter-package connector coupled between the first side of the first semiconductor package and the first side of the second semiconductor package. The PoP structure further includes a first molding material on the second side of the first semiconductor package. The second side of the second semiconductor package is substantially free of the first molding material. 1. A package-on-package (PoP) structure comprising:a first semiconductor package having a first side, a second side opposing the first side, and external connectors at the second side of the first semiconductor package;a second semiconductor package having a third side and a fourth side opposing the third side, wherein the fourth side of the second semiconductor package faces the first side of the first semiconductor package;inter-package connectors coupled between the first side of the first semiconductor package and the fourth side of the second semiconductor package; anda first molding material, wherein the first molding material is disposed between the first semiconductor package and the second semiconductor package, and extends along the second side of the first semiconductor package, wherein the third side of the second semiconductor package is free of the first molding material.2. The PoP structure of claim 1 , wherein the external connectors extend further from the second side of the first semiconductor package than the first molding material.3. The PoP structure of claim 2 , further comprising an integrated passive device (IPD) attached to the first side of the first semiconductor package between the external connectors claim 2 , wherein the IPD is encapsulated by the first molding material.4. The PoP structure of ...

SEMICONDUCTOR DEVICE WITH FINE PITCH REDISTRIBUTION LAYERS

A semiconductor device with fine pitch redistribution layers is disclosed and may include a semiconductor die with a bond pad and a first passivation layer comprising an opening above the bond pad. A redistribution layer (RDL) may be formed on the passivation layer with one end of the RDL electrically coupled to the bond pad and a second end comprising a connection region. A second passivation layer may be formed on the RDL with an opening for the connection region of the RDL. An under bump metal (UBM) may be formed on the connection region of the RDL and a portion of the second passivation layer. A bump contact may be formed on the UBM, wherein a width of the RDL is less than a width of the opening in the second passivation layer and may be constant from the bond pad through at least a portion of the opening. 1. A semiconductor device comprising:a semiconductor die comprising a bond pad;a first passivation layer covering a first surface of the semiconductor die, the first passivation layer comprising an opening above the bond pad;a redistribution layer (RDL) on the first passivation layer with one end of the RDL electrically coupled to the bond pad and a second end comprising a connection region;a second passivation layer on the RDL and on a portion of the first passivation layer, the second passivation layer comprising an opening for the connection region of the RDL;an under bump metal (UBM) on the connection region of the RDL and a portion of the second passivation layer; anda bump contact on the UBM, wherein a width of the RDL is less than a width of the opening in the second passivation layer.2. The semiconductor device according to claim 1 , wherein the width of the RDL is constant from the bond pad through at least a portion of the opening.3. The semiconductor device according to claim 1 , wherein the UBM is on a portion of the first passivation layer.4. The semiconductor device according to claim 1 , wherein the connection region comprises a region of the ...

Integrated Circuit Packages and Methods for Forming the Same

A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies. 1. A chip comprising:a substrate;a metal pad over the substrate;a passivation layer having a portion over the metal pad;a polymer layer over the passivation layer, wherein the polymer layer extends to an edge of the chip, and a first edge of the polymer layer forms a part of the edge of the chip;an electrical connector; and a first horizontal surface substantially perpendicular to the edge of the chip; and', 'a slant sidewall surface, wherein the first horizontal surface is connected to a first end of the slant sidewall surface, and the slant sidewall surface is neither perpendicular to nor parallel to the edge of the chip., 'a molding compound encircling a portion of the electrical connector, wherein a lower portion of the electrical connector is in the molding compound, and wherein the molding compound comprises a surface comprising2. The chip of further comprising a second horizontal surface substantially perpendicular to the edge of the chip claim 1 , wherein the second horizontal surface is connected to a second end of the slant sidewall surface claim 1 , and the first horizontal surface claim 1 , the slant sidewall surface claim 1 , and the second horizontal surface form a step.3. The chip of claim 1 , wherein the first horizontal surface extends to the electrical connector.4. The chip of further comprising:a plurality of dielectric layers underlying the metal pad; anda seal ring proximal edges of the chip, wherein the seal ring extends into the plurality of dielectric layers.5. The chip of claim 4 , wherein the molding compound comprises:first portions on opposite sides of electrical connector, ...

INTERCONNECT STRUCTURE WITH REDUNDANT ELECTRICAL CONNECTORS AND ASSOCIATED SYSTEMS AND METHODS

Semiconductor die assemblies having interconnect structures with redundant electrical connectors are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die, a second semiconductor die, and an interconnect structure between the first and the second semiconductor dies. The interconnect structure includes a first conductive film coupled to the first semiconductor die and a second conductive film coupled to the second semiconductor die. The interconnect structure further includes a plurality of redundant electrical connectors extending between the first and second conductive films and electrically coupled to one another via the first conductive film. 1. A semiconductor device , comprising:a semiconductor substrate;a dielectric material over the substrate;a conductive trace extending at least partially through the dielectric material; and a conductive member coupled to the conductive trace, and', 'a conductive bond material bonded to the conductive member,, 'a plurality of redundant electrical connectors extending from the conductive trace and through at least a portion of the dielectric material, wherein each of the redundant electrical connectors includes—'}wherein all of the redundant electrical connectors are coupled to the conductive trace.2. The semiconductor device of wherein the dielectric includes a plurality of openings exposing portions of the conductive trace claim 1 , wherein the redundant electrical connectors are formed in the openings.3. The semiconductor device of wherein the conductive member comprises copper and the bond material comprises a solder material.4. The semiconductor device of wherein the conductive member includes an end portion claim 1 , and wherein the conductive bond material and conductive member form a conductive joint at the end portion.5. The semiconductor device of claim 1 , further comprising a through-substrate via (TSV) extending at least partially through the substrate claim 1 , ...

COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) IMAGE SENSOR (CIS) PACKAGE WITH AN IMAGE BUFFER

A complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) package is provided. The image sensor package comprises a first integrated circuit (IC) die, a second IC die, and a fan-out structure. The first IC die comprises a pixel sensor array, and the second IC die is under and bonded to the first IC die. Further, the fan-out structure is under and bonded to the second IC die. The fan-out structure comprises a third IC die, a fan-out dielectric layer laterally adjacent to the third IC die, a through insulator via (TIV) extending through the fan-out dielectric layer, and one or more redistribution layers (RDLs) under the third IC die and the TIV. The one or more RDLs electrically couple to the third IC die and the TIV. A method for manufacturing the CIS package is also provided. 1. An image sensor package comprising:a first integrated circuit (IC) die comprising a pixel sensor array;a second IC die under and bonded to the first IC die;an interface layer between the first IC die and the second IC die, wherein the interface layer is configured to bond and electrically couple the second IC die to the first IC die at an insulator-to-insulator interface and a metal-to-metal interface, and wherein the metal-to-metal interface is even with the insulator-to-insulator interface; and a third IC die;', 'a fan-out dielectric layer laterally adjacent to the third IC die;', 'a through insulator via (TIV) extending through the fan-out dielectric layer; and', 'one or more redistribution layers (RDLs) under the third IC die and the TIV, wherein the one or more RDLs electrically couple to the third IC die and the TIV., 'a fan-out structure under and bonded to the second IC die, wherein the fan-out structure comprises2. An image sensor package comprising:a first integrated circuit (IC) die comprising a pixel sensor array;a second IC die under and bonded to the first IC die; and a third IC die;', 'a fan-out dielectric layer laterally adjacent to the third IC die;', 'a through ...

METHOD FOR MANUFACTURING PRINTED WIRING BOARD AND PRINTED WIRING BOARD

A method for manufacturing a printed wiring board includes forming, on a surface of an insulating layer, a patterned catalyst film including a catalyst for electroless plating such that the patterned catalyst film has a pattern corresponding to a conductor circuit, and applying electroless plating on the patterned catalyst film such that a conductor metal is deposited on the patterned catalyst film and that the conductor circuit is formed on the surface of the insulating layer. 1. A method for manufacturing a printed wiring board , comprising:forming, on a surface of an insulating layer, a patterned catalyst film comprising a catalyst for electroless plating such that the patterned catalyst film has a pattern corresponding to a conductor circuit; andapplying electroless plating on the patterned catalyst film such that a conductor metal is deposited on the patterned catalyst film and that the conductor circuit is formed on the surface of the insulating layer.2. A method for manufacturing a printed wiring board according to claim 1 , wherein the forming of the patterned catalyst film comprises forming a photosensitive catalyst film for electroless plating on the surface of the insulating layer and subjecting the photosensitive catalyst film to exposure and development such that the patterned catalyst film is formed on the surface of the insulating layer.3. A method for manufacturing a printed wiring board according to claim 1 , wherein the forming of the patterned catalyst film comprising printing the catalyst on the surface of the insulating layer by inkjet such that the patterned catalyst film is formed on the surface of the insulating layer.4. A method for manufacturing a printed wiring board according to claim 1 , wherein the applying of electroless plating comprises applying electroless plating such that the conductor metal is deposited in anisotropic growth with respect to amounts of the conductor metal on an upper surface and a side surface of the patterned ...

SEMICONDUCTOR DEVICES, SEMICONDUCTOR PACKAGES, AND METHODS OF MANUFACTURING THE SEMICONDUCTOR DEVICES

A semiconductor device includes a conductive component on a substrate, a passivation layer on the substrate and including an opening that exposes at least a portion of the conductive component, and a pad structure in the opening and located on the passivation layer, the pad structure being electrically connected to the conductive component. The pad structure includes a lower conductive layer conformally extending on an inner sidewall of the opening, the lower conductive layer including a conductive barrier layer, a first seed layer, an etch stop layer, and a second seed layer that are sequentially stacked, a first pad layer on the lower conductive layer and at least partially filling the opening, and a second pad layer on the first pad layer and being in contact with a peripheral portion of the lower conductive layer located on the top surface of the passivation layer. 1. A semiconductor device comprising:a conductive component on a substrate;a passivation layer on the substrate and including an opening therein, wherein the opening exposes at least a portion of the conductive component; and a lower conductive layer conformally extending on an inner sidewall of the opening and on a top surface of the passivation layer around the opening, the lower conductive layer including a conductive barrier layer, a first seed layer, an etch stop layer, and a second seed layer that are sequentially stacked,', 'a first pad layer on the lower conductive layer, the first pad layer at least partially filling the opening, and', 'a second pad layer on the first pad layer, the second pad layer laterally extending beyond the first pad layer to contact a peripheral portion of the lower conductive layer located on the top surface of the passivation layer., 'a pad structure on the passivation layer and in the opening, the pad structure electrically connected to the conductive component, the pad structure comprising2. The semiconductor device of claim 1 , wherein the second pad layer is ...

PACKAGING STRUCTURE AND FORMING METHOD THEREOF

Packaging structure and method of forming a packaging structure are provided. A substrate is provided, and an adhesive layer is formed on the substrate. An improvement layer is formed on the adhesive layer. The improvement layer contains openings exposing surface portions of the adhesive layer at bottoms of the openings. A plurality of chips is provided and includes functional surfaces. The plurality of chips is mounted on the substrate such that the functional surfaces are bonded to the adhesive layer at the bottoms of the openings. 1. A method of forming a packaging structure , comprising:providing a substrate;forming an adhesive layer on the substrate;forming an improvement layer on the adhesive layer, wherein the improvement layer contains openings there-in, exposing surface portions of the adhesive layer at bottoms of the openings;providing a plurality of chips, wherein the plurality of chips includes functional surfaces; andmounting the plurality of chips on the substrate such that the functional surfaces are bonded to the adhesive layer at the bottoms of the openings.2. The method according to claim 1 , wherein the substrate is made of a material including glass claim 1 , ceramic claim 1 , metal claim 1 , or polymer.3. The method according to claim 1 , wherein the plurality of chips has a top surface higher than the improvement layer.4. The method according to claim 3 , wherein the plurality of chips has a thickness in a range of approximately 20 micrometers to 100 micrometers.5. The method according to claim 3 , wherein the openings have a depth in a range of approximately 10 micrometers to 50 micrometers.6. The method according to claim 1 , wherein the adhesive layer includes an ultraviolet adhesive claim 1 , an acrylic pressure sensitive adhesive claim 1 , or an epoxy pressure sensitive adhesive.7. The method according to claim 1 , wherein forming the improvement layer includes:forming an improvement film on the adhesive layer; andforming openings in the ...

Packaging structure and forming method thereof

Packaging structure and method for forming a packaging structure are provided. A bonding layer is formed on the substrate. An improvement layer is formed on the bonding layer. The improvement layer contains openings exposing surface portions of the bonding layer at bottoms of the openings. Chips are provided and include functional surfaces. The chips are mounted on the substrate by bonding the functional surfaces of the chips to the bonding layer through the openings. Top surfaces of the chips are lower than or flush with a top surface of the improvement layer.

PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF

The present disclosure provides a package structure and its packaging method. The packaging method includes: providing a bonding layer on a substrate; forming an improvement layer on the bonding layer, where the improvement layer has openings, and bottoms of the openings expose a surface of the bonding layer; providing chips, each including a non-functional surface; and mounting the chips by attaching the non-functional surface to the bonding layer at the bottoms of the openings. 1. A fabrication method of a package structure , comprising:providing a bonding layer on a substrate;forming an improvement layer on the bonding layer, wherein the improvement layer has openings, and bottoms of the openings expose a surface of the bonding layer;providing chips, each including a non-functional surface; andmounting the chips by attaching the non-functional surfaces to the bonding layer at the bottoms of the openings.2. The fabrication method according to claim 1 , wherein:each chip includes a functional surface opposing to the non-functional surface; andthe functional surface of the chip is lower than or equal to a top surface of the improvement layer; or the functional surface of the chip is higher than a top surface of the improvement layer.3. The fabrication method according to claim 1 , wherein:the bonding layer includes an ultraviolet adhesive, an acrylic acid pressure sensitive adhesive or an epoxy resin pressure sensitive adhesive.4. The fabrication method according to claim 1 , wherein forming the improvement layer and the openings includes:forming an improvement film on the surface of the bonding layer; andexposing and developing the improvement film to form the improvement layer having the openings.5. The fabrication method according to claim 4 , wherein:a material of the improvement film includes a photoresist.6. The fabrication method according to claim 2 , after mounting the chips claim 2 , further including:forming an encapsulation layer on the top surface of ...

SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF

A method for fabricating a semiconductor structure includes providing a substrate with a first surface and a second surface, wherein at least one soldering pad is formed on the first surface of the substrate. The method also includes forming at least one via to expose each soldering pad by etching the substrate from the second surface, forming a seed layer to cover the second surface of the substrate and the sidewall and the bottom surfaces of each via, and then forming a redistribution metal layer over a portion of the seed layer formed on the sidewall and the bottom surfaces of each via and the second surface of the substrate surrounding each via. The method further includes alternately performing a pre-wetting process and a chemical etching process to completely remove the portion of the seed layer not covered by the redistribution metal layer. 1. A method for fabricating a semiconductor structure , comprising:providing a semiconductor substrate with a first surface and a second surface opposite to the first surface, wherein at least one soldering pad is formed on the first surface of the semiconductor substrate;forming at least one via in the semiconductor substrate to expose each soldering pad by etching the semiconductor substrate from the second surface of the semiconductor substrate;forming a seed layer to cover a sidewall surface and a bottom surface of each via and the second surface of the semiconductor substrate;forming a redistribution metal layer to cover a portion of the seed layer formed on the sidewall and the bottom surfaces of each via and on a portion of the second surface of the semiconductor substrate surrounding each via;performing a pre-wetting process by spraying a diluting agent onto the seed layer and the redistribution metal layer to let each via retain a portion of the diluting agent;performing a chemical etching process right after the pre-wetting process by spraying an etch solution onto the seed layer and the redistribution metal ...

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME, AND SEMICONDUCTOR PACKAGES INCLUDING THE SEMICONDUCTOR DEVICES

A semiconductor device includes a substrate having a die region and a scribe region surrounding the die region, a plurality of via structures penetrating through the substrate in the die region, a portion of the via structure being exposed over a surface of the substrate, and a protection layer pattern structure provided on the surface of the substrate surrounding a sidewall of the exposed portion of the via structure and having a protruding portion covering at least a portion of the scribe region adjacent to the via structure. 1. A semiconductor device , comprising:a substrate including a die region and a scribe region surrounding the die region;a plurality of via structures penetrating through the substrate in the die region, a portion of the via structure being exposed over a surface of the substrate; anda protection layer pattern structure on the surface of the substrate surrounding a sidewall of the exposed portion of the via structure and having a protruding portion covering at least a portion of the scribe region adjacent to the via structure.2. The semiconductor device of claim 1 , wherein the protection layer pattern structure has a scribe lane recess along the scribe region of the substrate.3. The semiconductor device of claim 2 , wherein the protruding portion has a width substantially the same as a width of the scribe lane recess.4. The semiconductor device of claim 2 , wherein the protruding portion protrudes in a first direction from the via structure and the scribe lane recess extends in a second direction substantially perpendicular to the first direction.5. The semiconductor device of claim 1 , wherein the protruding portion protrudes in a first direction from the via structure and the protruding portion is spaced apart from the outermost via structure by a distance less than or equal to ten times the diameter of the via structure.6. The semiconductor device of claim 5 , wherein the protruding portion extends in a second direction substantially ...

Packaging Devices and Methods of Manufacture Thereof

Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad, a second portion of the contact pad being exposed. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to the second portion of the contact pad. A PPI pad is disposed over the passivation layer and is coupled to the PPI line. An insulating material is disposed over the PPI line, the PPI pad being exposed. The insulating material is spaced apart from an edge portion of the PPI pad by a predetermined distance. 1. A method of forming a packaging device , the method comprising:forming a contact pad over a substrate;forming a passivation layer over the substrate and a first portion of the contact pad yet leaving a second portion of the contact pad exposed;forming a post passivation interconnect (PPI) line and a PPI pad over the passivation layer, the PPI line being coupled to the second portion of the contact pad, the PPI pad being coupled to the PPI line;depositing a first insulating material over the PPI line, the PPI pad, and the passivation layer; andpatterning the first insulating material to expose the PPI pad, wherein after the patterning, the first insulating material has a first sidewall spaced apart from a second sidewall of the PPI pad by a predetermined distance, the first sidewall of the first insulating material extending below a top surface of the PPI pad.2. The method of further comprising:forming a conductive material on the PPI pad.3. The method of further comprising:depositing a second insulating material over the first insulating material and surrounding at least a lower portion of the conductive material, the second insulating material being interposed between the first sidewall of the first insulating material and the second sidewall ...

Bump structural designs to minimize package defects

A method of forming a chip package includes providing a chip with a plurality of first bumps, wherein the plurality of first bumps has a first height. The method further includes providing a substrate with a plurality of second bumps, wherein the plurality of second bumps has a second height. The method further includes bonding the plurality of first bumps to the plurality of second bumps to form a first bump structure of the chip package, wherein the first bump structure has a standoff, wherein a ratio of a sum of the first height and the second height to the standoff is equal to or greater than about 0.6 and less than 1.

STACKED STRUCTURE OF SEMICONDUCTOR CHIPS HAVING VIA HOLES AND METAL BUMPS

A stacked structure comprises a semiconductor chip which includes a substrate having at least one substrate via hole penetrating through the substrate; at least one backside metal layer formed on a backside of the substrate covering an inner surface of the substrate via hole and at least part of the backside of the substrate; at least one front-side metal layer formed on the front-side of the substrate and electrically connected to the at least one backside metal layer on a top of at least one of the at least one substrate via hole; at least one electronic device formed on the front-side of the substrate and electrically connected to the at least one front-side metal layer; and at least one metal bump formed on at least one of the backside metal layer and the front-side metal layer. 1. A stacked structure , comprising: a first substrate having at least one first substrate via hole penetrating through said first substrate;', 'at least one first backside metal layer formed on a backside of said first substrate and covering an inner surface of said at least one first substrate via hole and at least part of said backside of said first substrate;', 'at least one first front-side metal layer formed on a front-side of said first substrate, wherein said at least one first front-side metal layer is electrically connected to said at least one first backside metal layer on a top of at least one of said at least one first substrate via hole;', 'at least one first electronic device formed on said front-side of said first substrate, wherein at least one of said at least one first electronic device is electrically connected to said at least one first front-side metal layer; and', 'at least one first metal bump formed on at least one of said at least one first backside metal layer and said at least one first front-side metal layer., 'a first semiconductor chip, which includes2. The stacked structure according to claim 1 , further comprising a second semiconductor chip claim 1 , ...

SEMICONDUCTOR DEVICE

In the semiconductor device, a bump electrode which connects a semiconductor chip and a wiring board is made up of a first part surrounded by an insulating film and a second part exposed from the insulating film. Since it is possible to reduce a width of the bump electrode while increasing a height of the bump electrode, a distance between the neighboring bump electrodes can be increased, and a filling property of a sealing material can be improved. 1. A semiconductor device comprising:a semiconductor substrate;a conductive layer formed on the semiconductor substrate;a first insulating film which is formed on the conductive layer and covers the conductive layer;a second insulating film which is formed on the first insulating film and includes an opening which exposes a part of a surface of the conductive layer;a bump electrode which is made up of a first part which is in contact with the conductive layer and positioned in the opening and a second part which is positioned on the opening and exposed from the second insulating film;a terminal which is connected to the bump electrode and is formed on a surface of a wiring board; anda sealing material which fills a gap between the semiconductor substrate and the wiring board.2. The semiconductor device according to claim 1 ,wherein a height of the first part is larger than a height of the second part.3. The semiconductor device according to claim 1 ,wherein a width of the first part is smaller than a width of the second part.4. The semiconductor device according to claim 1 ,wherein the second insulating film covers a periphery of the first part of the bump electrode.5. The semiconductor device according to claim 4 ,wherein a film thickness of the second insulating film is larger than a film thickness of the first insulating film.6. The semiconductor device according to claim 4 ,wherein the sealing material is in contact with the first insulating film on an outer side of the second insulating film which covers the ...

Device Package with Reduced Thickness and Method for Forming Same

A device package includes a die and a molding compound around the die. The molding compound has a non-planar surface recessed from a top surface of the die. The device package also includes an interconnect structure over the die. The interconnect structure includes a redistribution layer extending onto the molding compound and conformal to the non-planar surface of the molding compound. The device package further includes a first connector disposed over the die and bonded to the interconnect structure. 1. A device package comprising:a die comprising a die contact;a molding compound around the die and having a non-planar top surface recessed from a top surface of the die; andan interconnect structure disposed over the die, wherein the interconnect structure comprises a redistribution layer extending onto the molding compound and being conformal to the non-planar top surface of the molding compound, the redistribution layer comprising a first contact pad and a second contact pad, the first contact pad being electrically coupled to the die contact and the second contact pad being over the molding compound, an entirety of a bottom surface of the second contact pad contacting the molding compound.2. The device package of claim 1 , further comprising a first connector mounted on a first contact pad and a second connector mounted on a second contact pad.3. The device package of claim 2 , wherein the first connector and the second connector have a thickness difference.4. The device package of claim 3 , wherein the first connector and the second connector have different volumes claim 3 , and the thickness difference is attributed from the different volumes between the first connector and the second connector.5. The device package of claim 4 , wherein the first contact pad and the second contact pad have different surface areas claim 4 , wherein the thickness difference is attributed from the different surface areas between the first contact pad and the second contact pad.6. ...

PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME

An embodiment is a structure including a first die, a molding compound at least laterally encapsulating the first die, a first redistribution structure including metallization patterns extending over the first die and the molding compound, a first conductive connector comprising a solder ball and an under bump metallization coupled to the first redistribution structure, and an integrated passive device bonded to a first metallization pattern in the first redistribution structure with a micro bump bonding joint, the integrated passive device being adjacent the first conductive connector. 1. A structure comprising:a first die;a molding compound at least laterally encapsulating the first die;a first redistribution structure comprising metallization patterns extending over the first die and the molding compound;a first conductive connector comprising a solder ball and an under bump metallization coupled to the first redistribution structure; andan integrated passive device bonded to a first metallization pattern in the first redistribution structure with a micro bump bonding joint, the integrated passive device being adjacent the first conductive connector.2. The structure of claim 1 , wherein a solder layer of the micro bump bonding joint contacts the first metallization pattern of the first redistribution structure claim 1 , and wherein the under bump metallization of the first conductive connector contacts a second metallization pattern in the first redistribution structure.3. The structure of claim 2 , wherein the first metallization pattern is at a same level in the first redistribution structure as the second metallization pattern.4. The structure of further comprising:a substrate bonded to the first redistribution structure using the first conductive connector.5. The structure of claim 4 , wherein the integrated passive device is interposed between the first redistribution structure and the substrate.6. The structure of further comprising:an electrical connector ...

WAFER-LEVEL CHIP SCALE PACKAGING STRUCTURE AND METHOD FOR MANUFACTURING SAME

The present disclosure provides a wafer-level chip scale packaging structure and a method for manufacturing the same. The method includes the following steps: 1) providing a first supporting substrate; 2) placing a first chip on the first supporting substrate, and forming a first packaging layer on the first chip; 3) separating the first chip and the surface of the first packaging layer in contact with the first chip from the first supporting substrate, and attaching the other surface of the first packaging layer to a second supporting substrate; 4) disposing a second packaging layer on the surface of the first packaging layer which is in contact with the first chip; 5) forming a rewiring layer on the second packing layer, the rewiring layer is electrically connected to the first chip; and 6) electrically connecting a second chip to the rewiring layer. 1. A method for preparing a wafer-level chip scale packaging structure , comprising:placing a first chip on a first supporting substrate;forming a first packaging layer on the first chip, wherein the first packaging layer comprises a first surface and a second surface opposing to each other, wherein the first chip is in contact of the first surface;separating the first packaging layer and the first chip from the first supporting substrate at the first surface of the first packaging layer;attaching the second surface of the first packaging layer to a second supporting substrate;disposing a second packaging layer on the first surface of the first packaging layer;forming a rewiring layer on the second packing layer, wherein the rewiring layer is electrically connected to the first chip; andattaching a second chip to the rewiring layer, wherein the second chip is electrically connected to the rewiring layer.2. The method for preparing a wafer-level chip scale packaging structure according to claim 1 , further comprising:before placing the first chip on the first supporting substrate, coating a release layer on the first ...

CHIP PACKAGING METHOD

The method of chip packaging comprises: S1: providing a carrier, and forming an adhesive layer on a surface of the carrier; S2: forming a first dielectric layer on a surface of the adhesive layer, and forming a plurality of first through holes corresponding to electrical leads of a semiconductor chip in the dielectric layer; S3: attaching the semiconductor chip with the front surface facing downwards to the surface of the first dielectric layer; S4: forming a plastic encapsulation layer covering the chip on the surface of the first dielectric layer; S5: separating the adhesive layer and the first dielectric layer to remove the carrier and the adhesive layer; and S6: forming a redistribution layer for the semiconductor chip based on the first dielectric layer and the first through holes. 1. A chip packaging method , wherein , the method comprises the following steps:S1: providing a carrier, and forming an adhesive layer on a surface of the carrier;S2: forming a first dielectric layer on a surface of the adhesive layer, and forming a plurality of first through holes in the first dielectric layer;S3: attaching a semiconductor chip's front surface to a surface of the first dielectric layer, wherein the plurality of first through holes connects to electrical leads of the semiconductor chip;S4: forming a plastic encapsulation layer covering the semiconductor chip on the surface of the first dielectric layer;S5: removing the carrier and the adhesive layer from the first dielectric layer; andS6: forming a redistribution layer of the semiconductor chip on the first dielectric layer and filling the first through holes.2. The chip packaging method according to claim 1 , the method further comprises step S7 of: forming an under-bump metal layer on a surface of the redistribution layer claim 1 , and forming solder ball bumps on a surface of the under-bump metal layer.3. The chip packaging method according to claim 2 , wherein step S7 further comprises:S7-1: forming a second ...

FAN-OUT SEMICONDUCTOR PACKAGE

A fan-out semiconductor package may include a support member having a through-hole, a semiconductor chip disposed in the through-hole, a component embedded structure disposed adjacent to and spaced apart from the semiconductor chip in the through-hole by a predetermined distance, an encapsulant, and a connection member. The semiconductor chip has an active surface having connection pads disposed thereon and an inactive surface opposing the active surface. The component embedded structure has a plurality of passive components embedded therein. The encapsulant encapsulates at least portions of the support member, the component embedded structure, and the semiconductor chip. The connection member is disposed on the support member, the component embedded structure, and the active surface of the semiconductor chip. The connection member includes redistribution layers and vias electrically connecting the redistribution layers to the plurality of passive components and the connection pads of the semiconductor chip. 1. A fan-out semiconductor package comprising:a support member having a through-hole;a semiconductor chip disposed in the through-hole, the semiconductor chip comprising an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;a component embedded structure disposed adjacent to and spaced apart from the semiconductor chip in the through-hole by a predetermined distance and comprising a plurality of passive components embedded therein;an encapsulant encapsulating at least portions of the support member, the component embedded structure, and the semiconductor chip; anda connection member disposed on the support member, the component embedded structure, and the active surface of the semiconductor chip,wherein the connection member includes redistribution layers and vias electrically connecting the redistribution layers to the plurality of passive components and the connection pads.2. The fan-out semiconductor ...

LTHC as Charging Barrier in InFO Package Formation

A method includes forming a release film over a carrier, forming a polymer buffer layer over the release film, forming a metal post on the polymer buffer layer, encapsulating the metal post in an encapsulating material, performing a planarization on the encapsulating material to expose the metal post, forming a redistribution structure over the encapsulating material and the metal post, and decomposing a first portion of the release film. A second portion of the release film remains after the decomposing. An opening is formed in the polymer buffer layer to expose the metal post. 1. A method comprising:forming a release film over a carrier;forming a polymer buffer layer over the release film;forming a metal post on the polymer buffer layer;encapsulating the metal post in an encapsulating material;performing a planarization on the encapsulating material to expose the metal post;forming a redistribution structure over the encapsulating material and the metal post;decomposing a first portion of the release film, wherein a second portion of the release film remains after the decomposing; andforming an opening in the polymer buffer layer to expose the metal post.2. The method of further comprising:bonding a package component to the metal post; anddispensing an underfill between the package component and the second portion of the release film.3. The method of claim 1 , wherein the decomposing the first portion of the release film is performed by projecting a laser beam on the release film.4. The method of claim 1 , wherein the release film comprises a polymer base material and carbon black particles.5. The method of further comprising removing the second portion of the release film before the opening is formed in the polymer buffer layer.6. The method of claim 1 , wherein the opening extends into both the polymer buffer layer and the second portion of the release film.7. The method of claim 1 , wherein the first portion of the release film has a first thickness before the ...

Package structure and manufacturing method thereof

A package structure including a frame structure, a die, an encapsulant, and a redistribution structure is provided. The frame structure has a cavity. The die is disposed in the cavity. The die has an active surface, a rear surface opposite to the active surface, a plurality of lateral sides connecting the active surface and the rear surface, and a plurality of connection pads disposed on the active surface. The encapsulant encapsulates at least a portion of the frame structure and lateral sides of the die. The redistribution structure is disposed on the encapsulant and the active surface of the die. The connection pads are directly in contact with the redistribution structure.

Interconnections for a substrate associated with a backside reveal

An apparatus relating generally to a substrate is disclosed. In this apparatus, a post extends from the substrate. The post includes a conductor member. An upper portion of the post extends above an upper surface of the substrate. An exterior surface of the post associated with the upper portion is in contact with a dielectric layer. The dielectric layer is disposed on the upper surface of the substrate and adjacent to the post to provide a dielectric collar for the post. An exterior surface of the dielectric collar is in contact with a conductor layer. The conductor layer is disposed adjacent to the dielectric collar to provide a metal collar for the post, where a top surface of each of the conductor member, the dielectric collar and the metal collar have formed thereon a bond structure for interconnection of the metal collar and the conductor member.

Semiconductor device assembly with through-package interconnect and associated systems, devices, and methods

Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material on an encapsulant such that the encapsulant separates the spacer material from an active surface of a semiconductor device and at least one interconnect projecting away from the active surface. The method further includes molding the encapsulant such that at least a portion of the interconnect extends through the encapsulant and into the spacer material. The interconnect can include a contact surface that is substantially co-planar with the active surface of the semiconductor device for providing an electrical connection with the semiconductor device.

Hollow Metal Pillar Packaging Scheme

An integrated circuit includes a bottom substrate, a metal layer disposed over the bottom substrate and a hollow metal pillar disposed on the metal layer. The metal layer and the hollow metal pillar are electrically connected. 1. A structure comprising:a substrate;a redistribution layer over the substrate;a conductive pillar over the redistribution layer, the conductive pillar having an annular shape in a plan view; andan insulating material extending along an inner sidewall and an outer sidewall of the conductive pillar.2. The structure of claim 1 , wherein a topmost surface of the conductive pillar is above a topmost surface of the insulating material.3. The structure of claim 1 , further comprising a solder layer over the conductive pillar.4. The structure of claim 1 , wherein the annular shape comprises one or more holes.5. The structure of claim 1 , wherein the annular shape comprises two holes and a divider separating the two holes.6. The structure of claim 1 , wherein an inner diameter of the annular shape is between about 140 μm and about 160 μm.7. The structure of claim 1 , wherein a height of the annular shape is between about 80 μm and about 90 μm.8. The structure of claim 1 , wherein a distance between the inner sidewall and the outer sidewall of the conductive pillar is between about 40 μm and about 50 μm.9. A structure comprising:a substrate;a redistribution layer over the substrate;a molding compound over the redistribution layer; anda conductive pillar in the molding compound, the conductive pillar surrounding a portion of the molding compound, the conductive pillar being electrically coupled to the redistribution layer.10. The structure of claim 9 , further comprising a contact pad between the substrate and the redistribution layer claim 9 , the redistribution layer electrically coupling the contact pad to the conductive pillar.11. The structure of claim 10 , further comprising a passivation layer between the contact pad and the redistribution layer ...

IMAGE PICKUP APPARATUS

An image pickup apparatus includes: an image pickup device including a light receiving surface, an opposite surface, and an inclined surface, and provided with light receiving surface electrodes formed on the light receiving surface; cover glass joined so as to cover the light receiving surface; and a wiring board including second bond electrodes, wherein back surfaces of the light receiving surface electrodes being exposed to an opposite surface side, extended wiring patterns extended from the respective back surfaces of the light receiving surface electrodes through the inclined surface to the opposite surface, each of the extended wiring patterns including a first bond electrode, and the first bond electrode and the second bond electrode being bonded through a bump. 1. An image pickup apparatus comprising:an image pickup device including a light receiving surface where a light receiving portion is formed, an opposite surface opposing the light receiving surface, and an inclined surface inclined at an acute first angle to the light receiving surface, and provided with a plurality of light receiving surface electrodes electrically connected with the light receiving portion and formed on the light receiving surface;a transparent member joined so as to cover the light receiving surface; anda wiring board including a plurality of second bond electrodes on a main surface,wherein the transparent member and the plurality of light receiving surface electrodes are extended to an outside of an end side of the inclined surface, and back surfaces of the plurality of light receiving surface electrodes are exposed to a side of the opposite surface,the image pickup device includes a plurality of extended wiring patterns extended from the respective back surfaces of the plurality of light receiving surface electrodes through the inclined surface to the opposite surface, each of the extended wiring patterns including a first bond electrode on the opposite surface, andthe main ...

DEVICES INCLUDING COAX-LIKE ELECTRICAL CONNECTIONS AND METHODS FOR MANUFACTURING THEREOF

A device includes a semiconductor chip including an electrical contact arranged on a main surface of the semiconductor chip. The device includes an external connection element configured to provide a first coax-like electrical connection between the device and a printed circuit board, wherein the first coax-like electrical connection includes a section extending in a direction vertical to the main surface of the semiconductor chip. The device further includes an electrical redistribution layer arranged over the main surface of the semiconductor chip and configured to provide a second coax-like electrical connection between the electrical contact of the semiconductor chip and the external connection element, wherein the second coax-like electrical connection includes a section extending in a direction parallel to the main surface of the semiconductor chip. 1. Device , comprising:a semiconductor chip comprising an electrical contact arranged on a main surface of the semiconductor chip;an external connection element configured to provide a first coax-like electrical connection between the device and a printed circuit board, wherein the first coax-like electrical connection comprises a section extending in a direction vertical to the main surface of the semiconductor chip; andan electrical redistribution layer arranged over the main surface of the semiconductor chip and configured to provide a second coax-like electrical connection between the electrical contact of the semiconductor chip and the external connection element, wherein the second coax-like electrical connection comprises a section extending in a direction parallel to the main surface of the semiconductor chip.2. The device of claim 1 , wherein the external connection element is configured to provide a mechanical connection between the device and the printed circuit board.3. The device of claim 1 , further comprising:an encapsulation material, wherein the semiconductor chip is at least partly embedded in the ...

ELECTRONIC PACKAGE HAVING REDISTRIBUTION STRUCTURE

An electronic package is provided, including an electronic component, a redistribution structure formed on the electronic component, a plurality of conductive posts bonded to the redistribution structure, and a redistribution layer bonded to the conductive posts. As such, the electronic component that meets the requirement of miniaturization can be electrically connected to an electronic device through the redistribution structure, the conductive posts and the redistribution layer. 1. An electronic package , comprising:an electronic component having an active surface and a non-active surface opposite to the active surface;a redistribution structure formed on the active surface of the electronic component and electrically connected to the electronic component;a plurality of conductive posts bonded to and electrically connected to the redistribution structure;a redistribution layer bonded to and electrically connected to the conductive posts, wherein each of the conductive posts has one end connected to the redistribution structure and the other end connected to the redistribution layer;an encapsulating layer bonded to the electronic component and formed on the non-active surface of the electronic component anda packaging layer bonded to the encapsulating layer, wherein a top surface of the encapsulating layer is exposed from an upper surface of the packaging layer.23-. (canceled)4. The electronic package of claim 1 , wherein the packaging layer is in direct contact with the encapsulating layer.5. The electronic package of claim 1 , wherein the packaging layer is further formed on the redistribution layer to encapsulate the encapsulating layer.67-. (canceled)8. The electronic package of claim 1 , wherein the electronic component has a lateral surface adjacent to and connected with the active surface and the non-active surface.9. The electronic package of claim 8 , wherein the encapsulating layer is bonded to the lateral surface of the electronic component.10. The ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device including a semiconductor substrate having oppositely facing first and second surfaces, the first surface being an active surface and provided with an electronic element thereon, a pad electrode to be connected to the electronic element in a peripheral portion of the electronic element on the active surface, a first opening extending from the second surface toward the pad electrode so as not to reach the first surface of the semiconductor substrate, a second opening formed to reach the pad electrode from a bottom surface of the first opening and having a diameter smaller than that of the first opening, an insulating layer formed to cover sidewall surfaces of the first opening and the second opening, and a conductive layer formed, inside of the insulating layer, to cover at least an inner wall surface of the insulating layer and a bottom surface of the second opening. 1. A device comprising:a semiconductor substrate including an image sensor on a first surface of the semiconductor substrate, the semiconductor substrate including an opening at a peripheral region of the semiconductor substrate, the peripheral region being outside the image sensor;a pad electrode disposed on the first surface of the semiconductor substrate and electrically connected with the image sensor;a conductor disposed in the opening formed at the peripheral region of the semiconductor substrate and electrically connected to the pad electrode; andan insulating layer disposed in the opening and between the conductor and the semiconductor substrate, the opening includes a first portion and a second portion, an end of the second portion being defined by an end of the first portion,', 'the second portion is closer to the pad electrode than the first portion, and', 'a largest diameter of the second portion is smaller than a smallest diameter of the first portion., 'wherein,'}2. The device of claim 1 , further comprising:a transparent substrate disposed over an active surface of ...

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

A semiconductor package and a manufacturing method are provided. The semiconductor package includes a die, a dummy cube, a stress relaxation layer, an encapsulant and a redistribution structure. The dummy cube is disposed beside the die. The stress relaxation layer covers a top surface of the dummy cube. The encapsulant encapsulates the die and the dummy cube. The redistribution structure is disposed over the encapsulant and is electrically connected to the die. The stress relaxation layer is interposed between the dummy cube and the redistribution structure. 1. A semiconductor package , comprising:a die;a dummy cube, disposed beside the die;a stress relaxation layer, covering a top surface of the dummy cube;an encapsulant encapsulating the die and the dummy cube; anda redistribution structure disposed over the encapsulant and electrically connected to the die,wherein the stress relaxation layer is interposed between the dummy cube and the redistribution structure.2. The semiconductor package of claim 1 , wherein the dummy cube is electrically isolated from the redistribution structure.3. The semiconductor package of claim 1 , wherein the stress relaxation layer comprises a portion of the encapsulant.4. The semiconductor package of claim 1 , wherein the stress relaxation layer comprises a polymeric layer claim 1 , and the polymeric layer is not in physical contact with the redistribution structure.5. The semiconductor package of claim 1 , wherein the stress relaxation layer comprises a first polymeric layer and a second polymeric layer claim 1 , and a material of the first polymeric layer is different from a material of the second polymeric layer.6. The semiconductor package of claim 1 , wherein the stress relaxation layer comprises a polymeric layer extending from the top surface of the dummy cube to the redistribution structure.7. The semiconductor package of claim 6 , wherein a material of the polymeric layer comprises polyimide claim 6 , polybenzooxazole claim 6 ...

Buffer layer(s) on a stacked structure having a via

A structure includes first and second substrates, first and second stress buffer layers, and a post-passivation interconnect (PPI) structure. The first and second substrates include first and second semiconductor substrates and first and second interconnect structures on the first and second semiconductor substrates, respectively. The second interconnect structure is on a first side of the second semiconductor substrate. The first substrate is bonded to the second substrate at a bonding interface. A via extends at least through the second semiconductor substrate into the second interconnect structure. The first stress buffer layer is on a second side of the second semiconductor substrate opposite from the first side of the second semiconductor substrate. The PPI structure is on the first stress buffer layer and is electrically coupled to the via. The second stress buffer layer is on the PPI structure and the first stress buffer layer.

ELECTRONIC DEVICE AND MANUFACTURING METHOD THEREOF

An electronic device and a manufacturing method thereof are provided. The electronic device includes a chip package, a core dielectric layer disposed on the chip package, and an antenna pattern disposed on the core dielectric layer opposite to the chip package. The chip package includes a semiconductor chip, an insulating encapsulation encapsulating the semiconductor chip, and a redistribution structure electrically coupled to the semiconductor chip. The redistribution structure includes a first circuit pattern located at an outermost side of the chip package, and a patterned dielectric layer disposed between the first circuit pattern and the insulating encapsulation. The core dielectric layer is in contact with the first circuit pattern. The core dielectric layer and the patterned dielectric layer are of different materials. The antenna pattern is electrically coupled to the chip package. 1. An electronic device , comprising: a semiconductor chip;', 'an insulating encapsulation, encapsulating the semiconductor chip; and', a first circuit pattern, located at an outermost side of the chip package; and', 'a patterned dielectric layer, disposed between the first circuit pattern and the insulating encapsulation; and, 'a redistribution structure, electrically coupled to the semiconductor chip and comprising], 'a chip package, comprisinga core dielectric layer, disposed on the chip package, being in contact with the first circuit pattern of the redistribution structure, wherein the core dielectric layer and the patterned dielectric layer of the redistribution structure are of different materials; andan antenna pattern, disposed on the core dielectric layer opposite to the chip package and electrically coupled to the chip package.2. The electronic device of claim 1 , wherein the antenna pattern is tapered with first surfaces comprising widths greater than that of second surfaces claim 1 , the first surfaces opposite to the second surfaces of the antenna pattern are in ...

Single-Shot Encapsulation

A semiconductor device includes a semiconductor wafer. A plurality of pillar bumps is formed over the semiconductor wafer. A solder is deposited over the pillar bumps. The semiconductor wafer is singulated into a plurality of semiconductor die after forming the pillar bumps while the semiconductor wafer is on a carrier. An encapsulant is deposited around the semiconductor die and pillar bumps while the semiconductor die remains on the carrier. The encapsulant covers an active surface of the semiconductor die between the pillar bumps.

Semiconductor device

An inventive semiconductor device includes: a semiconductor chip including an integrated circuit; a plurality of electrode pads provided on the semiconductor chip and connected to the integrated circuit; a rewiring to which the electrode pads are electrically connected together, the rewiring being exposed on an outermost surface of the semiconductor chip and having an exposed surface area greater than the total area of the electrode pads; and a resin package which seals the semiconductor chip.

Semiconductor Packaging Structure and Method

A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections. 1. A semiconductor device comprising:a first external conductive connector in physical contact with a first post-contact material over a first underbump metallization over a first contact of a first package; anda second package over the first package, wherein the first external conductive connector extends away from the first package a first distance, the second package extends away from the first package a second distance, the second distance being parallel to and less than the first distance, and wherein the second package comprises a second conductive connector in physical contact with a second underbump metallization.2. The semiconductor device of claim 1 , wherein the first external conductive connector comprises a solder material.3. The semiconductor device of claim 1 , wherein the first post-contact material has a thickness of between about 10 μm and about 200 μm.4. The semiconductor device of claim 1 , wherein the second package comprises a semiconductor die.5. The semiconductor device of claim 1 , wherein the second conductive connector comprises solder.6. The semiconductor device of claim 5 , wherein the second package comprises a copper pillar is physical contact with the second conductive connector.7. A semiconductor device comprising:a post contact material located on a first set of a first plurality of package contacts on a first side of a first package;a second package with external connections bonded directly to a second set of the first plurality of package contacts, the second package comprising a first surface facing away from ...

INTEGRATED CIRCUIT PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME

An integrated circuit (IC) package structure includes a chip, a redistribution layer (RDL) structure, a molding compound structure and an electromagnetic interference (EMI) shielding structure. The RDL structure is formed on the chip and electrically connected thereto. The molding compound layer is provided on outer surfaces of the chip and the RDL structure. The EMI shielding structure is provided on outer surfaces of the molding compound structure. The molding compound structure layer provided on outer surfaces of the chip and the RDL structure provide protection and reinforcement to multiple faces of the IC package structure; and the EMI shielding structure provided on outer surfaces of the molding compound structure provides EMI protection to multiple faces of the chip and the RDL structure. The IC package structure has upgraded structural strength, reliability and stability in use. A method of manufacturing the above IC package structure is also introduced.

SEMICONDUCTOR PACKAGES WITH ELECTROMAGNETIC INTERFERENCE SHIELDING

Semiconductor packages having an electromagnetic interference (EMI) shielding layer and methods for forming the same are disclosed. The method includes providing a base carrier defined with an active region and a non-active region. A fan-out redistribution structure is formed over the base carrier. A die having elongated die contacts are provided. The die contacts corresponding to conductive pillars. The die contacts are in electrical communication with the fan-out redistribution structure. An encapsulant having a first major surface and a second major surface opposite to the first major surface is formed. The encapsulant surrounds the die contacts and sidewalls of the die. An electromagnetic interference (EMI) shielding layer is formed to line the first major surface and sides of the encapsulant. An etch process is performed after forming the EMI shielding layer to completely remove the base carrier and singulate the semiconductor package. 1. A method for forming a semiconductor package , comprising:providing a base carrier defined with an active region and a non-active region;forming a fan-out redistribution structure over the base carrier;providing a die having first and second major surfaces, the first major surface is an active surface of the die and the second major surface is an inactive surface of the die, wherein the die comprises elongated die contacts protruding from the active surface of the die, the die contacts corresponding to conductive pillars, wherein the die contacts are in electrical communication with the fan-out redistribution structure;forming an encapsulant having a first major surface and a second major surface opposite to the first major surface, wherein the first major surface is proximate to the inactive surface of the die, wherein the encapsulant surrounds the die contacts and sidewalls of the die;forming an electromagnetic interference (EMI) shielding layer, wherein the EMI shielding layer lines the first major surface and sides of the ...

Buffer Layer(s) on a Stacked Structure Having a Via

A structure includes first and second substrates, first and second stress buffer layers, and a post-passivation interconnect (PPI) structure. The first and second substrates include first and second semiconductor substrates and first and second interconnect structures on the first and second semiconductor substrates, respectively. The second interconnect structure is on a first side of the second semiconductor substrate. The first substrate is bonded to the second substrate at a bonding interface. A via extends at least through the second semiconductor substrate into the second interconnect structure. The first stress buffer layer is on a second side of the second semiconductor substrate opposite from the first side of the second semiconductor substrate. The PPI structure is on the first stress buffer layer and is electrically coupled to the via. The second stress buffer layer is on the PPI structure and the first stress buffer layer. 1. A structure comprising:a first substrate comprising a first semiconductor substrate and a first interconnect structure on the first semiconductor substrate;a second substrate comprising a second semiconductor substrate and a second interconnect structure on a first side of the second semiconductor substrate, the first substrate being bonded to the second substrate at a bonding interface, the first interconnect structure and the second interconnect structure being disposed between the first semiconductor substrate and the second semiconductor substrate;a via extending at least through the second semiconductor substrate into the second interconnect structure;a first stress buffer layer on a second side of the second semiconductor substrate, the second side of the second semiconductor substrate being opposite from the first side of the second semiconductor substrate;a post-passivation interconnect (PPI) structure on the first stress buffer layer and electrically coupled to the via; anda second stress buffer layer on the PPI structure ...

Interconnection structure and fabrication thereof

A method of forming an interconnection structure is disclosed, including providing a substrate having a first side and a second side opposite to the first side, forming a via hole through the substrate, wherein the via hole has a first opening in the first side and a second opening in the second side, forming a first pad covering the first opening, and forming a via structure in the via hole subsequent to forming the first pad, wherein the via structure includes a conductive material and is adjoined to the first pad.

STRUCTURE AND LAYOUT OF BALL GRID ARRAY PACKAGES

A ball grid array for an integrated circuit package includes an array of connection points derived from a base unit of hexagonal pattern repeated in at least one or more sections of the integrated circuit package. According to one embodiment, the connection points are solder balls mounted on a lower surface of the integrated circuit package. 1. A ball grid array for an integrated circuit package , comprising:an array of connection points derived from a base unit of hexagonal pattern repeated in at least one or more sections of the integrated circuit package.2. The ball grid array for an integrated circuit package according to claim 1 , wherein the array of connection points are arranged in a staggered pattern.3. The ball grid array for an integrated circuit package according to claim 1 , wherein the connection points are solder balls mounted on a lower surface of the integrated circuit package.4. The ball grid array for an integrated circuit package according to claim 3 , wherein the solder balls are arranged at a fixed pitch.5. The ball grid array for an integrated circuit package according to claim 3 , wherein the base unit of hexagonal pattern comprises seven balls including a central ball and six other balls around the central ball.6. The ball grid array for an integrated circuit package according to claim 5 , wherein the central ball is equidistant to said six other balls.7. The ball grid array for an integrated circuit package according to claim 5 , wherein an included angle between centers of any three balls of the seven balls is sixty degrees.8. A ball grid array for an integrated circuit package claim 5 , comprising:a plurality of first connection points in an array within a first region, wherein the array of first connection points are arranged in a square grid-shaped pattern or a rectangle pattern; anda plurality of second connection points in an array within a second region, wherein the array of the second connection points is derived from a repeating ...