HALBLEITERGEHÄUSE, HALBLEITERVORRICHTUNG, ELEKTRONIKELEMENT UND HERSTELLUNG EINES HALBLEITERGEHÄUSES

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device provided with: a semiconductor element forming an integrated circuit; a plurality of electrode pads formed on the integrating circuit forming surface side of the semiconductor element; bump electrodes for external units electrically connected to the electrode pads through conductive layers; and a stress relieving layer which is formed between the integrated circuit forming surface and electrode pads and between the bump electrodes and the conductive layers, is bonded to the surface, pads, electrodes, and layers, is cut off by at least l/3 from its surface, and is divided into a plurality of areas. The semiconductor device is highly reliable, and can be mounted at a high packing density and at a low cost.

Semiconductor device structure with stacked semiconductor dies

SEMICONDUCTOR DEVICES HAVING CRACK-INHIBITING STRUCTURES

Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-κ dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include (a) a metal lattice extending laterally between the bond pad and the semiconductor substrate and (b) barrier members extending vertically between the metal lattice and the bond pad.

SEMICONDUCTOR DEVICE

A semiconductor device includes: a semiconductor substrate having an integrated circuit formed thereon and an electrode electrically coupled to the integrated circuit; a passivation film formed on a surface of the semiconductor substrate, the surface having the electrode formed thereon; a first metal layer formed so as to come into contact with the passivation film; a resin layer formed on the first metal layer; a wiring formed so as to be electrically coupled to the electrode and reach an upper surface of the resin layer; and a second metal layer formed so as to be in contact with the first metal layer and reach the upper surface of the resin layer.

SEMICONDUCTOR PACKAGE

The invention provides a semiconductor package. The semiconductor package includes a semiconductor die having a central area and a peripheral area surrounding the central area. A first conductive bump is disposed on the semiconductor die in the central area. A second conductive bump is disposed on the semiconductor die in the peripheral area. An area ratio of the first conductive bump to the second conductive bump from a top view is larger than 1, and less than or equal to 3.

Stress buffering package for a semiconductor component

The present invention relates to a stress buffering package for a semiconductor component, wherein a stress buffering means comprises individual stress buffering elements that do not influence the stress buffering effect from each other. Furthermore the invention relates a method for manufacturing a stress buffering package for a semiconductor component.

METHOD FOR FORMING C4 CONNECTIONS ON INTEGRATED CIRCUIT CHIPS AND THE RESULTING DEVICES

DEVICE WITH FLEXIBLE ELECTRICAL CONNECTIONS, AND PROCEDURE FOR THEIR PRODUCTION

TENSION BUFFERING HOUSING FOR A SEMICONDUCTOR COMPONENT

Improved stack structures in electronic devices

Structures, methods and devices are disclosed, related to improved stack structures in electronic devices. In some embodiments, a stack structure includes a pad implemented on a substrate, the pad including a polymer layer having a side that forms an interface with another layer of the pad, the pad further including an upper metal layer over the interface, the upper metal layer having an upper surface. In some embodiments, the stack structure also includes a passivation layer implemented over the upper metal layer, the passivation layer including a pattern configured to provide a compressive force on the upper metal layer to thereby reduce the likelihood of delamination at the interface, the pattern defining a plurality of openings to expose the upper surface of the upper metal layer.

Conductive bump structure

The present invention provides a conductive bump structure. This structure comprises a buffer layer. The buffer layer may form a deformation during package process. This deformation may compensate the height difference among the gold bumps to improve the convenience of the manufacture process and the yield of the production.

Bonding pad structure and integrated cicruit comprise a pluirality of bonding pad structures

Semiconductor process, semiconductor element and package having semiconductor element

Wafer level chip package and a method of fabricating thereof

Wafer level chip packages including risers having sloped sidewalls and methods of fabricating such chip packages are disclosed. The inventive wafer level chip packages may advantageously be used in various microelectronic assemblies.

Semiconductor device and fabrication process thereof

A semiconductor device includes a conductive layer with a plurality of wires, and a bonding pad formed in a region overlapping with the plurality of wires of the conductive layer. One of the wires is connected to the bonding pad, and an insulating protective film is formed between the remaining wires and the bonding pad. The protective film is bridged between adjacent wires at least in a region overlapping with the bonding pad. As a result, the protective film on the wires forms a bridge structure, which is effective in preventing cracking at a lower portion of the protective film. Further, a void formed underneath the bridged portion serves as an air spring to prevent damage to the structural elements, such as the wires, formed under the protective film. Further, because a polyimide film, which serves as a shock absorber, is not required, working efficiency can be improved and chip cost can be reduced.

Wafer level chip scale packaging structure and method of fabricating the same

A wafer level chip scale packaging structure and the method of fabricating the same are provided to form a sacrificial layer below the bump using a normal semiconductor process. The bump is used to connect the signals between the Si wafer and the PCB. The interface between the sacrificial layer and the adjacent layers is the weakest part in the whole structure. When the stress applied to the bump is overloaded, the interface between the sacrificial layer and the adjacent layers will crash to remove the stress generated by different thermal expansion coefficients of the Si wafer and the PCB. The sacrificial layer would help avoid the crash occurring to the bump to protect the electrical conduction between the Si wafer and the PCB.

Semiconductor device having semiconductor substrate, and method of manufacturing the same

A semiconductor device includes a semiconductor substrate having a plurality of electrode pads, a protective film covering the upper surface of the semiconductor substrate and having an opening so that the electrode pad is exposed therethrough, a metal film formed on the electrode pad exposed through the opening, and a bump formed on the metal film. The metal film includes a plurality of grooves radially formed from the center thereof toward the periphery thereof.

Conductive bump structure

The present invention provides a conductive bump structure. This structure comprises a buffer layer. The buffer layer may form a deformation during package process. This deformation may compensate the height difference among the gold bumps to improve the convenience of the manufacture process and the yield of the production.

SEMICONDUCTOR DEVICE

Method of forming bump pad structure having buffer pattern

The method includes forming an upper layer on a lower layer, forming a metal interconnection in the upper layer, forming a passivation layer exposing a center part of the metal interconnection on the upper layer, forming a buffer pattern exposing the center part of the metal interconnection, and selectively and asymmetrically covering a peripheral region of the metal interconnect and a part of the passivation layer, forming a wrapping pattern covering the buffer pattern and exposing the center part of the metal interconnection on the passivation layer, and forming a pad pattern on the center part of the metal interconnection.

PROCEDURE FOR THE ELECTRICAL CONNECTION OF A CONSTRUCTION UNIT WITH EMPLOYMENTS WITH BALANCE BLOCKS

SEMICONDUCTOR DEVICE HAS STUDS OF CONNECTION PROVIDED With INSERTS

Dispositif semi-conducteur comprenant un circuit intégré et des plots de connexion électrique extérieure, dans lequel les plots (3) présentent des évidements (E) au moins partiellement remplis par une matière différente de celle les constituant, de façon à former des inserts (I).

Method for fabricating semiconductor component having encapsulated through wire interconnect (TWI)

A method for fabricating a semiconductor component with an encapsulated through wire interconnect includes the steps of providing a substrate having a first side, a second side and a substrate contact; forming a via in the substrate contact and the substrate to the second side; placing a wire in the via; forming a first contact on the wire proximate to the first side and a second contact on the wire proximate to the second side; and forming a polymer layer on the first side leaving the first contact exposed. The polymer layer can be formed using a film assisted molding process including the steps of: forming a mold film on tip portions of the bonding members, molding the polymer layer, and then removing the mold film to expose the tip portions of the bonding members. The through wire interconnect provides a multi level interconnect having contacts on opposing sides of the semiconductor substrate.

Wafer level packaging method and packages formed

A method for fabricating a wafer level package and packages formed are disclosed. In the method, an elastomeric material layer is first deposited on top of a passivation layer by a printing, coating or laminating method to form a plurality of isolated islands. The islands may have a thickness of less than 100 mum. Metal traces for I/O redistribution are then formed to connect the isolated islands with bond pads provided on the surface of the wafer such that one bond pad is connected electrically to one isolated island. On top of the metal trace is then deposited an organic material for insulation with the metal trace on top of the isolated islands exposed. After an UBM layer is formed on top of the metal traces that are exposed on the isolated islands, solder balls of suitable size may be planted by a plating technique, a printing technique or a pick and place technique to complete the wafer level package.

CONDUCTIVE PATHS FOR TRANSMITTING AN ELECTRICAL SIGNAL THROUGH AN ELECTRICAL CONNECTOR

The claimed invention relates to structures suitable for improving the performance and reliability of electrical connectors. One embodiment of the claimed invention includes an integrated circuit die having an electrical contact coupled with electrically conductive paths that share a common electrical source. The conductive paths are configured to transmit the same electrical signal to the electrical contact, which supports an electrical connector, such as a solder bump. The electrical connector couples the die with an outside component, such as a circuit board. Each of the conductive paths connect to the electrical contact at different interface locations. When the electrical signal passes through the interface locations, the paths are configured to have non-zero current densities at those locations. The electrical resistance of the conductive paths may be substantially similar. Thus, instead of being concentrated at a single point, current is more evenly distributed along the junction ...

Package with solder regions aligned to recesses

A method includes forming a passivation layer over a portion of a metal pad, forming a polymer layer over the passivation layer, and exposing the polymer layer using a photolithography mask. The photolithography mask has an opaque portion, a transparent portion, and a partial transparent portion. The exposed polymer layer is developed to form an opening, wherein the metal pad is exposed through the opening. A Post-Passivation Interconnect (PPI) is formed over the polymer layer, wherein the PPI includes a portion extending into the opening to connect to the metal pad.

Microelectronic device, stacked die package and computing system containing same, method of manufacturing a multi-channel communication pathway in same

A microelectronic device comprises a first surface (110, 710), a second surface (120, 720), and a passageway (130, 730) extending from the first surface to the second surface. The passageway contains a plurality of electrically conductive channels (131, 132, 231, 232) separated from each other by an electrically insulating material (133, 1 133).

SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, CIRCUIT BOARD AND ELECTRONIC APPARATUS

Method for forming c4 connections on integrated circuit chips and the resulting devices

COMPENSATING FOR WARPAGE OF A FLIP CHIP PACKAGE BY VARYING HEIGHTS OF A REDISTRIBUTION LAYER ON AN INTEGRATED CIRCUIT CHIP

Structures and methods of making a flip chip package that employ polyimide pads of varying heights at a radial distance from a center of an integrated circuit (IC) chip for a flip chip package. The polyimide pads may be formed under electrical connectors, which connect the IC chip to a chip carrier of the flip chip package, so that electrical connectors formed on polyimide pads of greater height are disposed at a greater radial distance from the center of the IC chip, while electrical connectors formed on polyimide pads of a lesser height are disposed more proximately to the center of the IC chip. Electrical connectors of a greater relative height to the IC chip's surface may compensate for a gap, produced by heat-induced warpage during the making of the flip chip package, that separates the electrical connectors on the IC chip from flip chip attaches on the chip carrier.

Method for fabrication of wafer level package incorporating dual compliant layers

A method is provided for forming wafer level package that incorporates dual compliant layers and a metal cap layer on top of I/O pads. The wafer level package includes a plurality of metal cap layers formed on top of a plurality of I/O pads to function as stress buffering and avoiding sharp corners in metal traces formed on top of the metal cap layers. A first compliant layer and a second compliant layer are formed under the metal trace to provide the necessary standoff and to accommodate differences in coefficients of thermal expansion of the various materials on an IC die. The wafer level package is particularly suitable for copper devices or in devices wherein copper lines are used.

Semiconductor device

A semiconductor device includes a semiconductor chip having a first main surface having an electrode pad in an exposed state, and an interlayer insulation layer formed on the first main surface so that the electrode pad is partially exposed; a re-wiring layer including a wiring pattern having a linear portion having one end portion electrically connected to the electrode pad and extending from the electrode pad, and a post electrode mounting portion with a recessed polygonal shape and connected to the other end portion of the linear portion; a post electrode formed on the post electrode mounting portion and having a bottom surface with a contour crossing an upper contour of the post electrode mounting portion at more than two points; a sealing portion disposed so that a top of the post electrode is exposed; and an outer terminal formed on the top of the post electrode.

Semiconductor Device and Method

A semiconductor device and method of manufacturing is provided, whereby a support structure is utilized to provide additional support for a conductive element in order to eliminate or reduce the formation of a defective surface such that the conductive element may be formed to have a thinner structure without suffering deleterious structures.

補償ブロックを備えるインサートを備える接続構成部品

... 本発明は、1つの面上に、別の構成部品の導電性埋込領域に電気的接続される1組の導電性インサートを備える構成部品に関し、前記インサートは、変形可能材料から有利に作成されて構成部品の面に配置された導電性ブロック上に支えられる。ブロックの、インサートと接触することになる面は、埋設領域の寸法より大きな少なくとも1つの寸法を有する。 ...

Semiconductor device and method for manufacturing the same

STACK STRUCTURES IN ELECTRONIC DEVICES

Method of fabricating semiconductor device

COMPONENT OF CONNECTION PROVIDED With INSERTS WITH COMPENSATION HOLDS.

L'invention concerne un composant comportant, sur une face, un ensemble d'inserts conducteurs destinés à être connectés électriquement avec des zones enterrées conductrices d'un autre composant, lesdits inserts reposant sur des cales conductrices, avantageusement réalisées en matériau déformable, qui sont positionnées à la surface du composant et qui présentent, au niveau de la surface de contact avec l'insert, au moins une dimension supérieure à celle de la zone enterrée.

MICROELECTRONIC DEVICE, STACKED DIE PACKAGE AND COMPUTING SYSTEM CONTAINING SAME, METHOD OF MANUFACTURING A MULTI-CHANNEL COMMUNICATION PATHWAY IN SAME, AND METHOD OF ENABLING ELECTRICAL COMMUNICATION BETWEEN COMPONENTS OF A STACKED-DIE PACKAGE

Photosensitive resin composition, pattern cured film and method for producing the same, semiconductor element and electronic device

The invention discloses a photosensitive resin composition including: (A) an alkali soluble resin having a structure unit represented by General Formula (1) below, (B) a compound which generates an acid by light, (C) a thermal crosslinking agent, and (D) an acrylic resin having a structure unit represented by General Formula (2) below. [In General Formula (1), R1 represents a hydrogen atom or a methyl group, R2 represents an alkyl group etc. having a carbon quantity from 1 to 10, a represents an integer from 0 to 3, b represents an integer from 1 to 3. A total amount of a and b is 5 or less.] [In General Formula (2), R3 represents a hydrogen atom or a methyl group, R4 represents a hydroxyalkyl group having a carbon quantity from 2 to 20.] ...

Method for manufacturing i/o terminals and the structure thereof

A method for manufacturing I/O terminals and the structure thereof is provided. The present invention provides movable supporting elements instead of copper posts in the conventional package process. A conductive composite layer covering the supporting elements is patterned to form metal traces connecting between metal pads and the supporting elements on a semiconductor wafer, so as to provide I/O electrical connections of the metal pads with externals. When a stress applied to the supporting element, the supporting element deforms/or attachably moves, and thus providing a cushion effect to release the stress. By the way, the conductive composite layer covering the supporting element confines the space the supporting element can move, limiting the supporting element still in the attached position. The present invention can solve the issue of breakage between the copper post and a solder ball in the conventional wafer-level package. Hence, the quality reliability of package devices can be ...

Substrate structure and method of manufacture

SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE

A flat-shaped table electrode (13) is placed between a bump electrode (14) and an electrode pad (6) formed on a semiconductor chip surface. The table electrode (13) has a greater area than the tip end of the bump electrode (14), a thickness smaller than the height of the bump electrode (14), and a Young's modulus smaller than the bump electrode (14). When the semiconductor chip (3) is flip-chip mounted on a substrate (1), the bump electrode (14) is plastically deformed and the table electrode (13) is elastically deformed appropriately, thereby obtaining a preferable conductive state.

Stacked semiconductor dies with a conductive feature passing through a passivation layer

A semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor die, and a second semiconductor die bonded on the first semiconductor die. A through-substrate via penetrates through a semiconductor substrate of the second semiconductor die. A passivation layer is disposed between the first semiconductor die and the second semiconductor die, wherein the passivation layer is directly bonded to the semiconductor substrate of the second semiconductor die. A conductive feature passes through the passivation layer, wherein the conductive feature is bonded to the through-substrate via. A barrier layer is disposed between the conductive feature and the passivation layer. The barrier layer covers sidewalls of the conductive feature and separates the surface of the conductive feature from a nearest neighboring surface of the first or second semiconductor die.

SEMICONDUCTOR DEVICE HAVING THROUGH-SILICON-VIA AND METHODS OF FORMING THE SAME

Semiconductor devices having a through-silicon-via and methods of forming the same are described herein. As an example, a semiconductor device may include a substrate material, a through-silicon-via protrusion extending from the substrate material, a first dielectric material formed on the substrate material, a second dielectric material formed on the first dielectric material, and an interconnect formed on the through-silicon-via protrusion, where the interconnect formed is in an opening in the second dielectric material. 116-. (canceled)17. A semiconductor device , comprising:a through-silicon-via providing a conductive path between opposing sides of a semiconductor die;an interconnect formed on an exposed surface of the through-silicon-via, the exposed surface providing a conductive contact surface for the interconnect; anda number of conductive plugs providing a respective number of additional conductive contact surfaces for the interconnect.18. The semiconductor device of claim 17 , wherein the number of conductive plugs and the through-silicon-via comprise a same conductive material.19. The semiconductor device of claim 17 , wherein the interconnect is formed on a planarized surface that includes the exposed surface of the through-silicon-via and exposed surfaces of the number of conductive plugs.20. The semiconductor device of claim 17 , wherein the number of conductive plugs are formed in a respective number of vias formed in a dielectric material.21. The semiconductor device of claim 17 , wherein the interconnect is formed on an area of the conductive material of 17 square microns to 500 square microns.22. The semiconductor device of claim 17 , wherein at least one of the number of conductive plugs extends from a planarized surface to a location below an upper surface of the through-silicon-via.23. A semiconductor device claim 17 , comprising:a through-silicon-via providing a conductive path between opposing sides of a semiconductor die;a number of ...

Semiconductor device, its manufacturing method and mounting structure of semiconductor device

The object of the present invention is to realize a semiconductor device enabling a flip chip connection without use of under-fill. The semiconductor device is composed of the followings: a semiconductor element having a plurality of circuit electrodes disposed thereon and a circuit surface coated with a protecting film; a stress relaxation layer, which is made by coating a cured thermoplastic resin onto the protecting film of the circuit surface of the semiconductor element to expose the circuit electrodes, curing it and having an inclination in the edge portion thereof; a wiring layer, which consists of a plurality of wirings connected to each of the circuit electrodes and disposed to make an electrical connection from the circuit electrodes via the edge portion of the stress relaxation layer and to a desired portion on the surface of the stress relaxation layer; a surface protecting film, which is provided to coat the wiring layer surface at each regulated position of the plural wirings ...

Semiconductor device, method of manufacturing thereof, circuit board and electronic apparatus

The object of the invention disclosed here is the provision of a semiconductor device, which can correspond to a large size chip and be provided with many external terminals with fine wirings with high reliable connection. A semiconductor device comprises a semiconductor element (2) including a plurality of electrodes (9), a single or a plurality of resin layers, a plurality of wirings (4) electrically connected to the electrode (9), and a plurality of external terminals (7) electrically connected to the wirings (4). A part of or all of the plurality of wirings (4) comprises a first wirings (4a) directed toward the center (10) of the semiconductor element (2) from a portion coupled to the electrodes (9); and a second wirings (4b) which is directed to an outer area from the center (10) of the semiconductor element (2) and coupled to the external terminals (7). At least one resin layer is formed between the first wirings (4a) and the second wirings (4b).

Structure of package

The present invention discloses a structure of wafer level packaging. The structure comprises a first patterning isolation layer, a conductive layer and a second patterning isolation layer. The first patterning isolation layer is combined with a passivation layer of an IC (Integrated Circuit). The conductive layer is combined with the passivation layer and metal pads of the IC to form a curve or winding conductive pattern. The second patterning isolation layer is combined with the conductive layer having a plurality of openings, and contact metal balls can form on the openings to electrically couple to a print circuit board.

METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE

In a method for fabricating a semiconductor, a first conductive pattern structure partially protruding upwardly from first insulating interlayer is formed in first insulating interlayer. A first bonding insulation layer pattern covering the protruding portion of first conductive pattern structure is formed on first insulating interlayer. A first adhesive pattern containing a polymer is formed on first bonding insulation layer pattern to fill a first recess formed on first bonding insulation layer pattern. A second bonding insulation layer pattern covering the protruding portion of second conductive pattern structure is formed on second insulating interlayer. A second adhesive pattern containing a polymer is formed on second bonding insulation layer pattern to fill a second recess formed on second bonding insulation layer pattern. The first and second adhesive patterns are melted. The first and second substrates are bonded with each other so that the conductive pattern structures contact each other.

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

A semiconductor package and a method of making a semiconductor package. As non-limiting examples, various aspects of this disclosure provide various semiconductor packages, and methods of making thereof, that comprise a conductive layer that comprises an anchor portion extending through at least one dielectric layer.

Semiconductor device

A semiconductor device includes a semiconductor element, a lead on which the semiconductor element is mounted, a bonding member fixing the semiconductor element to the lead, and a resin package enclosing the semiconductor element and a portion of the lead. This lead is formed with a groove recessed at a location spaced from the semiconductor element. The groove has first and second inner surfaces, where the first inner surface is closer to the semiconductor element than is the second inner surface. The angle the first inner surface forms with respect to the thickness direction of the semiconductor element is smaller than the angle the second inner surface forms with respect to the thickness direction.

STRUCTURES AND METHODS FOR IMPROVING SOLDER BUMP CONNECTIONS IN SEMICONDUCTOR DEVICES

Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The method includes forming a plurality of trenches in a dielectric layer extending to an underlying metal layer. The method further includes depositing metal in the plurality of trenches to form discrete metal line islands in contact with the underlying metal layer. The method also includes forming a solder bump in electrical connection to the plurality of metal line islands.

Semiconductor package, semiconductor device, electronic device, and method for producing semiconductor package

An insulating layer (3) having an opening portion (3a) at a position conformable to an electrode pad (2) is formed. Next, a resin projection portion (4) is formed on the insulating layer (3). Thereafter, a resist film is formed which has opening portions made in regions conformable to the opening portion (3a), the resin projection portion (4) and the region sandwiched therebetween. A Cu plating layer (6) is formed by electrolytic copper plating, using the resist film as a mask.

Halbleiterbauteil und Verfahren zu dessen Herstellung

Halbleiterbauteil (21) mit mehreren auf einem Halbleiterchip angeordneten Elektroden (8) für Verbindung nach außen, mit: - auf dem Halbleiterchip befindlichen Elektroden (2); - Harzelementen (5), die gesondert voneinander entsprechend den mehreren Elektroden (8) für Verbindung nach außen vorhanden sind und die an beliebigen Stellen angeordnet sind mit Ausnahme von solchen Stellen, an denen die auf dem Halbleiterchip befindlichen Elektroden (2) angeordnet sind; und - Zwischenverbindungen (6), von denen jede eine Elektrode (2) auf dem Halbleiterchip mit einer entsprechenden Elektrode (8) für Verbindungen nach außen verbindet, auf einem entsprechenden Harzelement (5) ausgebildet ist und mindestens einen Abschnitt mit einer Mehrschichtstruktur aus mindestens zwei Arten von Materialien aufweist, - wobei die auf dem Halbleiterchip befindlichen Elektroden (2) außerhalb der Elektroden (8) für Verbindung nach außen angeordnet sind und - wobei, betrachtet in Richtung parallel zu Hauptoberflächen ...

Semiconductor component used in e.g. mobile phone, mobile information unit, has intermediate connection which couples electrodes on semiconductor component to connection electrodes of resin component

Number of electrodes (2) are arranged on a semiconductor chip (1). A resin component (5) with the connection electrodes is provided and separated from the electrodes on the semiconductor chip. The electrodes on the semiconductor chip are connected to the connection electrodes of the resin component via an intermediate connection (6). An Independent claim is also included for a semiconductor component manufacturing method.

Halbleiterbauelement mit einem Beanspruchungspuffer

Eine integrierte Schaltung enthält eine erste Oberfläche, konfiguriert zum Montieren an einen Träger, einen aktiven Bereich der integrierten Schaltung, von der ersten Oberfläche beabstandet, ein Bondpad, über dem aktiven Bereich angeordnet und in elektrischer Kommunikation damit und eine keramische anorganische beanspruchungspuffernde Schicht, zwischen dem aktiven Bereich und dem Bondpad angeordnet.

Pufferschicht(en) auf einer gestapelten Struktur mit einer Durchkontaktierung

Eine Struktur umfasst ein erstes und zweites Substrat, eine erste und zweite Spannungspufferschicht und eine Post Passivation Interconnect-(PPI-)Struktur. Das erste und zweite Substrat umfassen ein erstes und zweites Halbleitersubstrat und eine erste und zweite Verbindungsstruktur auf dem ersten bzw. zweiten Halbleitersubstrat. Die zweite Verbindungsstruktur liegt auf einer ersten Seite des zweiten Halbleitersubstrats. Das erste Substrat ist an einer Bond-Grenzfläche an das zweite Substrat gebondet. Eine Durchkontaktierung erstreckt sich zumindest durch das zweite Halbleitersubstrat in die zweite Verbindungsstruktur. Die erste Spannungspufferschicht liegt auf einer zweiten Seite des zweiten Halbleitersubstrats gegenüber der ersten Seite des zweiten Halbleitersubstrats. Die PPI-Struktur liegt auf der ersten Spannungspufferschicht und ist elektrisch mit der Durchkontaktierung gekoppelt. Die zweite Spannungspufferschicht liegt auf der PPI-Struktur und der ersten Spannungspufferschicht.

METHOD FOR PRODUCING CONTACTS AND PRINTED CIRCUIT PACKAGES

APPARATUS WITH COMPLIANT ELECTRICAL TERMINALS, AND METHODS FOR FORMING SAME

An apparatus is disclosed including an electrical conductor and an electrically conductive, compliant bump formed on the electrical conductor. The compliant bump includes an electrically conductive, solderable capping layer and an electrically conductive, compliant body positioned between the solderable capping layer and the electrical conductor . The compliant body electrically couples the solderable capping layer to the electrical conductor. The electrical conductor may be, for example, an input/output (I/0) pad of the apparatus, and the compliant bump may form an electrical terminal of the apparatus. The compliant body forms a mechanically flexible, electrically conductive path between the solderable capping layer and the electrical conductor. The compliant bump deforms elastically when subjected to a force exerted between the solderable capping layer and the electrical conductor, allowing the compliant bump to form a highly reliable connection between the apparatus and an external element ...

COMPONENT OF CONNECTION PROVIDED With INSERTS WITH COMPENSATION HOLDS.

반도체 패키지

... 반도체 패키지를 제공한다. 반도체 패키지는, 기판 패드를 포함하는 회로 기판, 회로 기판과 마주하며 이격되어 배치되며, 칩 패드를 포함하는 반도체 칩 및 회로 기판 및 반도체 칩을 전기적으로 연결하는 연결 패턴을 포함한다. 반도체 칩은, 상기 반도체 칩 내에, 반도체 칩의 상면에 대하여 수직하게 배치되는 다수의 제1 회로 패턴들과, 칩 패드 및 제1 회로 패턴들을 전기적으로 연결하는 제1 비아를 포함한다. 칩 패드는, 연결 패턴이 접촉되는 제1 영역 및 제1 영역의 외각의 제2 영역을 포함하되, 제1 비아는 상기 제2 영역에 연결된다.

METHOD FOR FORMING C4 CONNECTIONS ON INTEGRATED CIRCUIT CHIPS AND THE RESULTING DEVICES

A method for forming preferably Pb-lead C4 connections or capture pads 37 with ball limiting metallization on an integrated circuit chip 30 by using a damascene process and preferably Cu metallization 32 in the chip 30 and in the ball limiting metallization for compatibility. In two one embodiment, the capture pad 52 is formed in the top insulating layer 51 and it also serves as the final level of metallization in the chip.

Compensating for warpage of a flip chip package by varying heights of a redistribution layer on an integrated circuit chip

Structures and methods of making a flip chip package that employ polyimide pads of varying heights at a radial distance from a center of an integrated circuit (IC) chip for a flip chip package. The polyimide pads may be formed under electrical connectors, which connect the IC chip to a chip carrier of the flip chip package, so that electrical connectors formed on polyimide pads of greater height are disposed at a greater radial distance from the center of the IC chip, while electrical connectors formed on polyimide pads of a lesser height are disposed more proximately to the center of the IC chip. Electrical connectors of a greater relative height to the IC chip's surface may compensate for a gap, produced by heat-induced warpage during the making of the flip chip package, that separates the electrical connectors on the IC chip from flip chip attaches on the chip carrier.

CONDUCTIVE CONTACTS HAVING VARYING WIDTHS AND METHOD OF MANUFACTURING SAME

A bump structure includes a contact element formed on a substrate and a passivation layer overlying the substrate. The passivation layer includes a passivation opening exposing the contact element. The bump structure also includes a polyimide layer overlying the passivation layer and an under bump metallurgy (UBM) feature electrically coupled to the contact element. The polyimide layer has a polyimide opening exposing the contact element, and the under bump metallurgy feature has a UBM width. The bump structure further includes a copper pillar on the under bump metallurgy feature. A distal end of the copper pillar has a pillar width, and the UBM width is greater than the pillar width. 1. A method comprising:forming a contact element over a substrate;forming one or more insulating layers over the contact element;patterning an opening in the one or more insulating layers to expose the contact element;electrically coupling an under bump metallurgy (UBM) feature with the contact element; andforming a conductive pillar on an opposing side of the UBM feature as the contact element, wherein the conductive pillar continuously decreases in diameter from a top surface of the UBM feature to a top surface of the conductive pillar, and wherein sidewalls of the conductive pillar are non-perpendicular to a major surface of the substrate.2. The method of further comprising disposing a solder joint on the top surface of the conductive pillar.3. The method of further comprising bonding the solder joint to a substrate trace of a semiconductor device.4. The method of claim 2 , wherein a distance between the conductive pillar and an adjacent conductive pillar measured at the UBM feature is less than a distance between the conductive pillar and the adjacent conductive pillar measured at a surface of the conductive pillar distal to the UBM feature.5. The method of claim 1 , wherein electrically coupling the UBM feature comprises disposing at least a portion of the UBM feature in the ...

Gehäusestruktur

Die Erfindung betrifft eine Struktur eines Waferebene-Gehäuses. Die Struktur umfaßt eine erste strukturierte Isolierschicht, eine leitende Schicht und eine zweite strukturierte Isolierschicht. Die erste strukturierte Isolierschicht ist mit einer Passivierungsschicht einer integrierten Schaltung (IC - "Integrated Circuit") gebildet. Die leitende Schicht ist mit einem Kurven- oder Wicklungs-Leitungsmuster konfiguriert. die zweite strukturierte Isolierschicht ist über der leitenden Schicht mit mehreren Öffnungen gebildet, und Kontaktmetallkugeln können in den Öffnungen gebildet werden, um mit einer Leiterplatte elektrisch verbunden zu werden.

Verfahren zur Herstellung einer Einpressdiode und Einpressdiode

Die Erfindung betrifft ein Verfahren zur Herstellung einer Einpressdiode, die einen Sockel, einen Kopfdraht und einen zwischen den Sockel und den Kopfdraht gelöteten Halbleiterchip aufweist Zunächst wird ein Halbleiterchip bereitgestellt, auf dessen Ober- und Unterseite jeweils eine bleifreie Legierung mit niedrigem Schmelzpunkt abgeschieden ist. Anschließend erfolgt ein Verbinden des Halbleiterchips mit dem Sockel und dem Kopfdraht mittels Diffusionslöten. Des Weiteren weist die Einpressdiode vorzugsweise elastisch und/oder plastisch verformbare Funktionsschichten auf, die im Betrieb durch Temperaturdifferenzen bedingte Beschädigungen des Halbleiterchips und des Lotes verhindern.

Method for producing contacts and printed circuit packages

Semiconductor device

SEMICONDUCTOR DEVICE AND ITS PRODUCING METHOD

METAL BUMP AND METHOD OF MANUFACTURING SAME

Metal line in semiconductor device and method for forming the same

Metal line in a semiconductor device and method for forming the same is provided. The method includes the steps of forming a buffer lower metal line on a semiconductor substrate for absorbing an external impact, forming pre-metal-dielectric which covers the buffer lower metal line, the pre-metal-dielectric having a via hole formed therein to expose a portion of the buffer lower metal line, forming a seed layer on a surface of the pre-metal-dielectric having the via hole formed therein, forming polyimide which exposes the via hole and the seed layer formed on the pre-metal-dielectric in the vicinity of the via hole, growing an upper metal line by using the seed layer exposed thus, subjecting the semiconductor substrate having the upper metal line formed thereon to thermal process, removing the polyimide by dry etching, and bonding a bonding portion onto the upper metal line.

Semiconductor device and method of manufacturing the same

An insulating film is formed such that the insulating film covers a source electrode and a gate electrode, and an opening portion exposing a portion of the source electrode and an opening portion exposing a portion of the gate electrode are formed in the insulating film. A plated layer is formed over the source electrode exposed in the opening portion, and a plated layer is formed over the gate electrode exposed in the opening portion. A source pad is formed of the portion of the source electrode exposed in the opening portion, and the plated layer, and a gate pad is formed of the portion of the gate electrode exposed in the opening portion, and the plated layer. An area of the opening portion for the gate pad is smaller than an area of the opening portion for the source pad, and a thickness of the plated layer over the gate electrode is greater than a thickness of the plated layer over the source electrode.

INTERCONNECT STRUCTURE FOR A SEMICONDUCTOR DEVICE WITH A RESILIENT STRESS ABSORBER AND RELATED METHOD OF MANUFACTURE

A semiconductor device (50) having a device substrate (102) is provided The semiconductor device (50) comprises an electrically conductive pad (110) formed overlying the device substrate (102) an electrically conductive platform (160) formed overlying the electrically conductive pad (110) and a pillar interconnect (180) formed on the electrically conductive platform (160) the electrically conductive platform (160) having a perimeter portion (162) extending away from the electrically conductive pad (110) and a capping portion (170) atop the perimeter portion (162), wherein the electrically conductive platform (160) encloses a cavity located between the capping portion (170), the perimeter portion (162) and the electrically conductive pad (110), a cushioning material (140) being disposed in the cavity, the cushioning material (140) being intended to act as a resilient stress absorber upon application of force on the pillar interconnect (180).

Thermal stable low elastic modulus material and device using the same

The present invention provides a thermal stable low elastic modulus material, which has high thermal stability, is little in change in dynamic characteristics such as coefficient of thermal expansion and elastic modulus within a temperature of -50° C. to 300° C., has an elastic modulus at room temperature of 2-0.01 GPa and is high in reliability of electric insulation regardless of a temperature fluctuation, and provides a semiconductor device using the same.The present invention also provides a thermal stable low elastic modulus resin composition obtained by heat-curing a mixture containing a polyimide, polyamide-imide or polyamide resin or resin precursor, whose cured product has an elastic modulus measured at -50° C. of 2-0.01 GPa, and an oligomer of an organosilicon compound having a functional group capable of causing addition reaction with an NH and/or COOH group.

Semiconductor device, method of manufacturing thereof, circuit board and electronic apparatus

A semiconductor device is provided comprising: a semiconductor element including a plurality of electrodes; first wirings coupled to the electrodes and directed toward a center of the semiconductor element from a portion coupled to the electrodes; second wirings coupled between the first wirings and external terminals, the second wirings being directed to an outer area of the semiconductor element relative to the center; and at least one resin layer formed between the first wirings and the second wirings.

SEMICONDUCTOR DEVICE CAPABLE OF DISPERSING STRESSES

A semiconductor device includes a semiconductor substrate including a circuit layer disposed therein, a bonding pad disposed on the semiconductor substrate, the bonding pad being electrically connected to the circuit layer, and a metal layer electrically connected to the bonding pad. The metal layer includes a first via electrically connected to the bonding pad, the first via providing an electrical path between the metal layer and the circuit layer, and a second via protruding toward the semiconductor substrate, the second via supporting the metal layer on the semiconductor substrate.

Stress buffer structures in a mounting structure of a semiconductor device

A mounting structure for a semiconductor device includes a stepwise stress buffer layer under a likewise stepwise UBM structure.

Halbleiterbauteil

Bei einem Halbleiterbauteil sind Anschlusselektroden (8) auf einem Halbleitersubstrat (1) platziert. Ein Verdrahtungsmuster (6) zum Verbinden einer jeweiligen Chipelektrode (2) mit einer entsprechenden Anschlusselektrode ist in der Nähe der Anschlusselektrode in einer Richtung geführt, in der der Effekt thermischer Spannungen nach der Montage des Halbleitersubstrats klein ist. Genauer gesagt, ist das Verdrahtungsmuster so geführt, dass die Führungsrichtung nicht mit derjenigen Richtung übereinstimmt, die die Mitte (11) des Halbleitersubstrates mit der Anschlusselektrode verbindet, entlang der die größten thermischen Spannungen zu erwarten sind. Demgemäß ist die Belastung verringert, wie die im Verdrahtungsmuster nach dem Montieren des Halbleitersubstrats an einer Montageplatte auftritt. Nachteilige Effekte von Spannungsbelastungen können verhindert werden, ohne dass die Anschlussleiterbahnen verbreitert werden.

Semiconductor package, semiconductor device, electronic device, and method of manufacturing semiconductor package

A metal line of semiconductor device and method of forming the same

A method includes forming a buffer lower metal line over a semiconductor substrate for absorbing an external impact, forming a pre-metal-dielectric layer which covers the buffer lower metal line, the pre-metal-dielectric layer having a via hole formed therein to expose a portion of the buffer lower metal line, forming a seed layer over a surface of the pre-metal-dielectric layer having the via hole formed therein, forming polyimide which exposes the via hole and the seed layer formed over the pre-metal-dielectric layer in the vicinity of the via hole, growing an upper metal line over the exposed seed layer, subjecting the semiconductor substrate having the upper metal line formed thereon to a thermal process, removing the polyimide by dry etching, and bonding a bonding portion onto the upper metal line.

집적회로 칩 및 이의 제조방법과 집적회로 칩을 구비하는 플립 칩 패키지 및 이의 제조방법

... 범프 구조물을 갖는 집적회로 칩에 있어서, 다수의 도전성 구조물 및 배선라인을 구비하는 집적회로 구조물의 패드 영역 및 의사 패드 영역의 각각에 제1 및 제2 패드 전극이 배치된다. 제1 전극패드의 상면을 노출하는 제1 개구 및 배선라인으로부터 이격된 제2 전극패드의 주변부를 노출하는 적어도 하나의 제2 개구를 구비하는 보호막 패턴이 집적회로 구조물의 상면에 배치된다. 제1 개구를 통하여 제1 전극패턴과 전기적으로 접속하는 제1 범프 구조물 및 제2 개구를 통하여 제2 전극패턴과 전기적으로 접속하는 제2 범프 구조물이 상기 보호막 패턴 상에 배치된다. 상기 제2 범프 구조물의 하부에 배치된 배선라인에 대한 응력집중을 방지할 수 있다.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Semiconductor package

MICROELECTRONIC DEVICE, STACKED DIE PACKAGE AND COMPUTING SYSTEM CONTAINING SAME, METHOD OF MANUFACTURING A MULTI¬ CHANNEL COMMUNICATION PATHWAY IN SAME, AND METHOD OF ENABLING ELECTRICAL COMMUNICATION BETWEEN COMPONENTS OF A STACKED-DIE PACKAGE

A microelectronic device comprises a first surface (110, 710), a second surface (120, 720), and a passageway (130, 730) extending from the first surface to the second surface. The passageway contains a plurality of electrically conductive channels (131, 132, 231, 232) separated from each other by an electrically insulating material (133, 1 133).

CONNECTION COMPONENT PROVIDED WITH INSERTS COMPRISING COMPENSATING BLOCKS

The invention relates to a component comprising, on one face, a set of conductive inserts to be electrically connected to conductive buried regions of another component, said inserts resting on conductive blocks advantageously produced from a deformable material and positioned at the surface of the component. The surface of the block, which is to come into contact with the insert, has at least one dimension larger than that of the buried region.

Solderless interconnection structure and method of forming same

An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.

Ladder Bump Structures and Methods of Making Same

An embodiment ladder bump structure includes an under bump metallurgy (UBM) feature supported by a substrate, a copper pillar mounted on the UBM feature, the copper pillar having a tapering curved profile, which has a larger bottom critical dimension (CD) than a top critical dimension (CD) in an embodiment, a metal cap mounted on the copper pillar, and a solder feature mounted on the metal cap.

Semiconductor device, method of manufacturing thereof, circuit board and electronic apparatus

A semiconductor device is provided comprising: a semiconductor element including a plurality of electrodes; first wirings coupled to the electrodes and directed toward a center of the semiconductor element from a portion coupled to the electrodes; second wirings coupled between the first wirings and external terminals, the second wirings being directed to an outer area of the semiconductor element relative to the center; and at least one resin layer formed between the first wirings and the second wirings.

HYBRID BONDING MECHANISMS FOR SEMICONDUCTOR WAFERS

The embodiments of diffusion barrier layer described above provide mechanisms for forming a copper diffusion barrier layer to prevent device degradation for hybrid bonding of wafers. The diffusion barrier layer(s) encircles the copper-containing conductive pads used for hybrid bonding. The diffusion barrier layer can be on one of the two bonding wafers or on both bonding wafers.

SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THEREOF, CIRCUIT BOARD AND ELECTRONIC APPARATUS

A semiconductor device is provided comprising: a semiconductor element including a plurality of electrodes; first wirings coupled to the electrodes and directed toward a center of the semiconductor element from a portion coupled to the electrodes; second wirings coupled between the first wirings and external terminals, the second wirings being directed to an outer area of the semiconductor element relative to the center; and at least one resin layer formed between the first wirings and the second wirings.

SEMICONDUCTOR DEVICE, SEMICONDUCTOR SUBSTRATE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To solve the problem that if a solder ball is mounted far out of a center of a metal layer in forming a bump on an electrode metal layer of a semiconductor substrate, the solder ball is not centered to the center of the metal layer even if reflow is applied by heat treatment. SOLUTION: When a metal layer 41 is formed on an electrode pad 2 of a semiconductor substrate 1, a plurality of groove portions 42 are formed so as to radially extend from the center of the metal layer 41 toward the outer periphery thereof, and in addition, so that the width thereof tapers down toward the outer periphery. By utilizing the groove portion 42 formed in the metal layer 41 as a guide, even in the case where a solder ball 6 is mounted far out of the center of the metal layer 41, if reflow is applied by heat treatment, the solder ball 6 can be surely centered to the center of the metal layer 41. COPYRIGHT: (C)2011,JPO&INPIT ...

Microelectronic device, stacked die package and computing system containing same, method of manufacturing a multi-channel communication pathway in same

BUMP STRUCTURE AND METHOD OF FORMING SAME

... 실시형태 BOT(bump on trace) 구조는, 집적회로에 의해 지지되는 콘택트 엘리먼트; 상기 콘택트 엘리먼트에 전기적으로 연결되는 UBM(under bump metallurgy) 피쳐; UBM 피쳐 상에 있는 메탈 범프; 및 기판 상의 기판 트레이스를 포함하고, 기판 트레이스는 금속간 화합물과 솔더 조인트를 통해 메탈 범프에 연결되고, 솔더 조인트의 제2 단면적에 대한 금속간 화합물의 제1 단면적의 비율은 40% 보다 크다.

METHODS AND APPARATUS FOR SOLDER CONNECTIONS

솔더 연결들을 위한 방법들 및 장치가 개시된다. 장치는 표면 상에 도전성 단자를 갖는 기판; 기판의 표면 및 도전성 단자 위에 놓이는 패시베이션 층; 도전성 단자의 일부를 노출시키는 상기 패시베이션 층 내의 개구; 개구내의 도전성 단자에 본딩되고 기판의 표면에 수직인 방향으로 연장하는 적어도 하나의 스터드 범프(stud bump); 및 개구내의 도전성 단자 상에 형성되고 적어도 하나의 스터드 범프를 둘러싸는 솔더 연결(solder connection)을 포함한다. 솔더 연결을 형성하기 위한 방법들이 개시된다. Methods and apparatus for solder connections are disclosed. The apparatus includes a substrate having a conductive terminal on a surface; A passivation layer overlying the surface of the substrate and the conductive terminal; An opening in the passivation layer exposing a portion of the conductive terminal; At least one stud bump bonded to the conductive terminal in the opening and extending in a direction perpendicular to the surface of the substrate; And a solder connection formed on the conductive terminals in the opening and surrounding at least one stud bump. Methods for forming a solder connection are disclosed.

Semiconductor device and method of forming micro-vias partially through insulating material over bump interconnect conductive layer for stress relief

A semiconductor device has a semiconductor die and first insulating layer formed over the semiconductor die. A plurality of first micro-vias can be formed in the first insulating layer. A conductive layer is formed in the first micro-openings and over the first insulating layer. A second insulating layer is formed over the first insulating layer and conductive layer. A portion of the second insulating layer is removed to expose the conductive layer and form a plurality of second micro-openings in the second insulating layer over the conductive layer. The second micro-openings can be micro-vias, micro-via ring, or micro-via slots. Removing the portion of the second insulating layer leaves an island of the second insulating layer over the conductive layer. A bump is formed over the conductive layer. A third insulating layer is formed in the second micro-openings over the bump. The second micro-openings provide stress relief.

Semiconductor structure having a patterned surface structure and semiconductor chips including such structures

SEMICONDUCTOR COMPONENTS AND SYSTEMS HAVING ENCAPSULATED THROUGH WIRE INTERCONNECTS (TWI) AND WAFER LEVEL METHODS OF FABRICATION

A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) attached to the substrate contact The through wire interconnect provides a multi level interconnect having contacts on opposing first and second sides of the semiconductor substrate The through wire interconnect includes a via through the substrate contact and the substrate, a wire in the via having a bonded connection with the substrate contact, a first contact on the wire proximate to the first side, and a second contact on the wire proximate to the second side The through wire interconnect also includes a polymer layer which partially encapsulates the through wire interconnect while leaving the first contact exposed The semiconductor component can be used to fabricate stacked systems module systems and test systems A method for fabricating the semiconductor component can include a film assisted molding process for forming the polymer layer.

SEMICONDUCTOR DEVICE WITH CONNECTION PADS PROVIDED WITH INSERTS

A semiconductor device includes an integrated circuit and external electrical connection pads. Each pad includes cavities that are at least partially filled with a material different from the material forming the pads, so as to form inserts.

Bonding pad structure and integrated circuit comprising a plurality of bonding pad structures

A bonding pad structure positioned on an integrated circuit includes a connecting pad, an insulation layer and a gold bump. The connecting pad is formed on the integrated circuit. The insulation layer is formed on the connecting pad, where the insulation layer has only one opening and a shape of the opening includes at least a bend. The gold bump is formed on the insulation layer, where the gold bump is electrically connected to the connecting pad through the opening of the insulation layer.

Semiconductor chip and flip-chip package comprising the same

A semiconductor chip includes stress-relief to mitigate the effects of differences in coefficients of thermal expansion (CTE) between a printed circuit board (PCB) and a semiconductor chip and a flip-chip package including the semiconductor chip. The semiconductor chip includes a stress-relief buffer coupling a bump and a semiconductor chip pad.

Methods of manufacturing stress buffer structures in a mounting structure of a semiconductor device

A mounting structure for a semiconductor device is formed to include a stepwise stress buffer layer under a stepwise UBM structure.

Semiconductor Device and Method of Forming RDL Under Bump for Electrical Connection to Enclosed Bump

A semiconductor device has a semiconductor wafer with a plurality of semiconductor die. A first conductive layer is formed over a surface of the wafer. A first insulating layer is formed over the surface of the wafer and first conductive layer. A second conductive layer has first and second segments formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A UBM layer is formed over the second insulating layer and the first segment of the second conductive layer. A first bump is formed over the UBM layer. The first bump is electrically connected to the second segment and electrically isolated from the first segment of the second conductive layer. A second bump is formed over the surface of the wafer and electrically connected to the first segment of the second conductive layer.

Semiconductor package

Provided is a semiconductor package including a circuit substrate including a substrate pad, a semiconductor chip spaced apart from and facing the circuit substrate, the semiconductor chip including a chip pad, and a connection pattern electrically connecting the circuit substrate with the semiconductor chip. The semiconductor chip may include a plurality of first circuit patterns extending substantially perpendicular toward a top surface of the semiconductor chip and at least one first via electrically connecting the chip pad to the first circuit patterns. The chip pad may include a first region in contact with the connection pattern and a second region outside the first region, and the first via may be connected to the second region of the chip pad.

Method for fabricating a through wire interconnect (twi) on a semiconductor substrate having a bonded connection and an encapsulating polymer layer

A method for fabricating a through wire interconnect for a semiconductor substrate having a substrate contact includes the steps of: forming a via through the semiconductor substrate from a first side to a second side thereof; placing a wire in the via having a first end with a bonded connection to the substrate contact and a second end proximate to the second side; forming a first contact on the wire proximate to the first side; forming a second contact on the second end of the wire; and forming a polymer layer on the first side at least partially encapsulating the wire while leaving the first contact exposed.

Bump Structure and Method of Forming Same

An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal bump on the under bump metallurgy feature, and a substrate trace on a substrate, the substrate trace coupled to the metal bump through a solder joint and intermetallic compounds, a ratio of a first cross sectional area of the intermetallic compounds to a second cross sectional area of the solder joint greater than forty percent.

Metal Bump and Method of Manufacturing Same

An embodiment bump structure includes a contact element formed on a substrate, a passivation layer overlying the substrate, the passivation layer having a passivation opening exposing the contact element a polyimide layer overlying the passivation layer, the polyimide layer having a polyimide opening exposing the contact element an under bump metallurgy (UMB) feature electrically coupled to the contact element, the under bump metallurgy feature having a UBM width, and a copper pillar on the under bump metallurgy feature, a distal end of the copper pillar having a pillar width, the UBM width greater than the pillar width.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A groove is formed between an inner peripheral edge of an opening of a pad electrode and an outer peripheral edge of a bonding region located inside the pad electrode in plan view. 1. A semiconductor device comprising:a pad electrode;a surface protective film covering the pad electrode and having an opening exposing a part of the pad electrode;a bonding region located inside the opening in plan view; anda first groove formed between an inner peripheral edge of the opening and an outer peripheral edge of the bonding region in plan view.2. The semiconductor device according to claim 1 , whereinthe first groove surrounds a periphery of the bonding region such that along the inner peripheral edge of the opening in plan view.3. The semiconductor device according to claim 2 , whereinthe pad electrode is a first laminated film in which a first metal film, a second metal film, and a third metal film are laminated in this order,the second metal film is made of a material containing aluminum as a main component, andthe first metal film and the third metal film are made of materials containing titanium nitride as a main component.4. The semiconductor device according to claim 3 , whereinthe third metal film is removed in the opening andthe first groove penetrates the second metal film and reaches an upper surface of the first metal film.5. The semiconductor device according to claim 4 , whereina width of the first groove is 2 μm or more and 10 μm or less.6. The semiconductor device according to claim 3 , whereinthe third metal film is removed in the opening, andthe first groove reaches the second metal film and does not reach an upper surface of the first metal film.7. The semiconductor device according to claim 6 , whereina depth of the first groove is ½ or more and ⅔ or less of a thickness of the second metal film.8. The semiconductor device according to claim 2 , whereinthe surface protective film is a silicon oxide film or a silicon nitride film.9. The semiconductor device ...

Buffer layer(s) on a stacked structure having a via

A structure includes first and second substrates, first and second stress buffer layers, and a post-passivation interconnect (PPI) structure. The first and second substrates include first and second semiconductor substrates and first and second interconnect structures on the first and second semiconductor substrates, respectively. The second interconnect structure is on a first side of the second semiconductor substrate. The first substrate is bonded to the second substrate at a bonding interface. A via extends at least through the second semiconductor substrate into the second interconnect structure. The first stress buffer layer is on a second side of the second semiconductor substrate opposite from the first side of the second semiconductor substrate. The PPI structure is on the first stress buffer layer and is electrically coupled to the via. The second stress buffer layer is on the PPI structure and the first stress buffer layer.

Semiconductor Device and Method for Forming Openings and Trenches in Insulating Layer by First LDA and Second LDA for RDL Formation

A semiconductor device has a semiconductor die with an encapsulant deposited over the semiconductor die. A first insulating layer having high tensile strength and elongation is formed over the semiconductor die and encapsulant. A first portion of the first insulating layer is removed by a first laser direct ablation to form a plurality of openings in the first insulating layer. The openings extend partially through the first insulating layer or into the encapsulant. A second portion of the first insulating layer is removed by a second laser direct ablation to form a plurality of trenches in the first insulating layer. A conductive layer is formed in the openings and trenches of the first insulating layer. A second insulating layer is formed over the conductive layer. A portion of the second insulating layer is removed by a third laser direct ablation. Bumps are formed over the conductive layer.

SEMICONDUCTOR PACKAGES

A semiconductor package includes a plurality of semiconductor chips. At least one of the semiconductor chips includes a semiconductor substrate including a semiconductor layer and a passivation layer having a third surface, a backside pad on the third surface, and a through-via penetrating through the semiconductor substrate. The backside pad includes an electrode pad portion, on the third surface, and a dam structure protruding on one side of the electrode pad portion and surrounding a side surface of the through-via. The dam structure is spaced apart from the side surface of the through-via. 1. A semiconductor package comprising:a plurality of semiconductor chips electrically connected to each other and stacked in a first direction, a semiconductor substrate including a semiconductor layer having a first surface and a second surface that are opposite each other;', 'a passivation layer on the first surface and having a third surface that is opposite the first surface;', 'a circuit structure on the second surface;', 'a frontside pad on the circuit structure;', 'a backside pad on the third surface; and', 'a through-via in the semiconductor substrate and extending between the second surface and the third surface to be electrically connected to the backside pad and the frontside pad,, 'wherein at least one of the plurality of semiconductor chips includeswherein the backside pad includes an electrode pad portion, on the third surface, and a dam structure protruding toward the first surface on one side of the electrode pad portion and surrounding a side surface of the through-via, andwherein the dam structure is spaced apart from the side surface of the through-via.2. The semiconductor package of claim 1 ,wherein the dam structure penetrates the third surface of the passivation layer,wherein a ratio of a height of the dam structure in the first direction to a maximum thickness of the passivation layer is within a range of about 0.5:1 to about 0.8:1,wherein the through- ...

Semiconductor Device and Method

A semiconductor device and method of manufacturing is provided, whereby a support structure is utilized to provide additional support for a conductive element in order to eliminate or reduce the formation of a defective surface such that the conductive element may be formed to have a thinner structure without suffering deleterious structures. 1. A device comprising:a first redistribution layer over a substrate;a protective layer over the first redistribution layer; anda first conductive feature having a first region and a second region, the first region over the protective layer, the second region extending through the protective layer to be connected to the first redistribution layer, the second region disposed around a support structure portion of the protective layer in a top-down view, the support structure portion of the protective layer disposed between the first region and the first redistribution layer, a first top surface of the first region and a second top surface of the second region each disposed further from the substrate than a third top surface of the protective layer.2. The device of claim 1 , wherein the first conductive feature has a convex surface comprising the first top surface of the first region and the second top surface of the second region.3. The device of claim 1 , wherein the first conductive feature comprises:a seed layer; anda conductive layer over the seed layer, the conductive layer having a first thickness over the protective layer of less than about 3 μm.4. The device of claim 1 , wherein the second region of the first conductive feature is a donut shaped region disposed around the support structure portion of the protective layer in the top-down view.5. The device of claim 1 , wherein the second region of the first conductive feature is a plurality of vias disposed around the support structure portion of the protective layer in the top-down view.6. The device of further comprising:a first passivation layer between the protective ...

DISPLAY DEVICE AND METHOD FOR MANUFACTURING DISPLAY DEVICE

A display panel comprising a display substrate having a display area and a pad area disposed around the display area. A connection wire is disposed on the pad area of the display substrate. A signal wire is disposed on the connection wire. A supporter is disposed between the display substrate and the connection wire. The connection wire directly contacts the supporter. 1. A display panel comprising:a display substrate having a display area and a pad area disposed around the display area;a connection wire disposed on the pad area of the display substrate;a signal wire disposed on the connection wire; anda supporter disposed between the display substrate and the connection wire,wherein the connection wire directly contacts the supporter.2. The display panel of claim 1 , wherein:a planar size of the connection wire is greater than a planar size of the supporter; andthe connection wire covers the supporter.3. The display panel of claim 2 , wherein:a planar size of the signal wire is greater than the planar size of the connection wire; andthe signal wire directly contacts the connection wire.4. The display panel of claim 1 , further comprising an insulating layer disposed between the display substrate and the signal wire claim 1 ,wherein the insulating layer covers a side surface of the connection wire and exposes an upper surface thereof.5. The display panel of claim 4 , wherein the signal wire directly contacts an upper surface of the insulating layer.6. The display panel of claim 1 , wherein a cross-sectional shape of the supporter includes a trapezoidal shape claim 1 , a triangular shape claim 1 , a pentagonal shape claim 1 , a semicircular shape claim 1 , a semi-elliptical shape claim 1 , and/or a quadrangular shape.7. The display panel of claim 1 , wherein the supporter includes a plurality of patterns extending along a long-side direction of the signal wire andspaced apart from each other along a short-side direction of the signal wire.8. The display panel of ...

MICROELECTRONIC DEVICES AND APPARATUSES HAVING A PATTERNED SURFACE STRUCTURE

A connector structure and a manufacturing method thereof are provided. The connector structure includes a semiconductor substrate, a metal layer, a passivation layer, and a conductive structure. The metal layer is over the semiconductor substrate. The passivation layer is over the metal layer and includes an opening. The conductive structure is in contact with the metal layer in a patterned surface structure of the conductive structure through the opening of the passivation layer. 1. A microelectronic device , comprising:a metal material comprising a single material over and in contact with a base material;a passivation material over the metal material;a patterned surface structure comprising portions of the passivation material located in at least one opening of the passivation material; anda conductive structure comprising a solder material located over the patterned surface structure and in direct contact with the metal material through the at least one opening of the passivation material, portions of the conductive structure extending through the at least one opening of the passivation material and substantially conforming to surfaces of the patterned surface structure.2. The microelectronic device of claim 1 , wherein the passivation material comprises a single material in direct contact with each of the metal material and the conductive structure.3. The microelectronic device of claim 1 , wherein the at least one opening is bounded by a vertical sidewall of the passivation material claim 1 , the patterned surface structure comprising multiple laterally spaced portions of the passivation material located directly on the metal material in the at least one opening of the passivation material.4. The microelectronic device of claim 3 , wherein a portion of the conductive structure extending above the passivation material exhibits a lateral boundary substantially coincident with the vertical sidewall of the passivation material.5. The microelectronic device of claim ...

Semiconductor composite layer structure and semiconductor packaging structure having the same thereof

A semiconductor composite layer structure disposed on a substrate having an electronic circuit structure and a first conductive layer is disclosed. The semiconductor composite layer structure comprises a plurality of dielectric layers, a first wetting layer, a stiff layer and a second wetting layer. The dielectric layers are disposed on the substrate separately. The first wetting layer is disposed on the dielectric layer and the substrate between the dielectric layers. The stiff layer is disposed on the first wetting layer. The second wetting layer is disposed on stiff layer, for contacting with a second conductive layer.

REDISTRIBUTION LAYER (RDL) STRUCTURE, SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

The present disclosure provides a redistribution layer (RDL) structure, a semiconductor device and manufacturing method thereof. The semiconductor device comprising an RDL structure that may include a substrate, a first conductive layer, a reinforcement layer and, and a second conductive layer. The first conductive layer may be formed on the substrate and has a first bond pad area. The reinforcement layer may be formed on a surface of the first conductive layer facing away from the substrate and located in the first bond pad area. The second conductive layer may be formed on the reinforcement layer and an area of the first conductive layer not covered by the reinforcement layer. The reinforcement layer has a material strength greater than those of the first conductive layer and the second conductive layer. The semiconductor device and the manufacturing method provided by the present disclosure may improve the performance of the semiconductor device. 1. A redistribution layer (RDL) structure , comprising:a substrate;a first conductive layer formed on the substrate and having a first bond pad area;a reinforcement layer formed on a surface of the first conductive layer not adjacent to the substrate and located in the first bond pad area; anda second conductive layer formed on the reinforcement layer and an area of the first conductive layer not covered by the reinforcement layer,wherein the reinforcement layer has a material strength greater than those of the first conductive layer and the second conductive layer and the reinforcement layer is conductive.2. The RDL structure according to claim 1 , wherein the reinforcement layer has at least one first through via claim 1 , and the second conductive layer fills the at least one first through via and is connected to the first conductive layer.3. The RDL structure according to claim 2 , wherein the at least one first through via comprises a plurality of first through vias distributed at intervals along an annular track.4. ...

Semiconductor device with bump stop structure

A method for manufacturing semiconductor devices is provided. In the method, a conductive pad and a metal protrusion pattern are formed in a metallization layer. A passivation layer is conformally deposited over the metallization, and a protection layer is conformally deposited over the passivation layer. Further, a post-passivation interconnect structure (PPI) is conformally formed on the protection layer, and the PPI structure includes a landing pad region, a protrusion pattern over at least a portion of the landing pad region and a connection line electrically connected to the conductive pad. A solder bump is then placed on the landing pad region in contact with the protrusion pattern of PPI structure. A to semiconductor device with bum stop structure is also provided.

Package with Solder Regions Aligned to Recesses

A method includes forming a passivation layer over a portion of a metal pad, forming a polymer layer over the passivation layer, and exposing the polymer layer using a photolithography mask. The photolithography mask has an opaque portion, a transparent portion, and a partial transparent portion. The exposed polymer layer is developed to form an opening, wherein the metal pad is exposed through the opening. A Post-Passivation Interconnect (PPI) is formed over the polymer layer, wherein the PPI includes a portion extending into the opening to connect to the metal pad. 1. An integrated circuit structure comprising:a substrate;a dielectric layer over the substrate, wherein the dielectric layer comprises a top surface; a first portion over and contacting the top surface of the dielectric layer; and', 'a plurality of second portions extending from the top surface of the dielectric layer into the dielectric layer; and, 'a conductive pad comprisinga solder region overlying and contacting the conductive pad.2. The integrated circuit structure of claim 1 , wherein the first portion of the conductive pad encircles the second portions of the conductive pad.3. The integrated circuit structure of claim 1 , wherein the solder region overlaps the first portion and the plurality of second portions of the conductive pad.4. The integrated circuit structure of claim 1 , wherein the second portions of the conductive pad have substantially planar bottom surfaces and slanted sidewalls.5. The integrated circuit structure of claim 1 , wherein the solder region further overlaps a portion of the dielectric layer claim 1 , and the portion of the dielectric layer is between two of the plurality of second portions of the conductive pad.6. The integrated circuit structure of claim 1 , wherein the plurality of second portions of the conductive pad extend to an intermediate level of the dielectric layer claim 1 , with the intermediate level being between the top surface and a bottom surface of the ...

SEMICONDUCTOR DEVICES HAVING CRACK-INHIBITING STRUCTURES

Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-κ dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include (a) a metal lattice extending laterally between the bond pad and the semiconductor substrate and (b) barrier members extending vertically between the metal lattice and the bond pad. 1. A semiconductor device , comprising:a substrate including circuit elements; and an insulating material;', 'a bond pad exposed from the insulating material and electrically coupled to at least one of the circuit elements; and', 'a crack-inhibiting structure including (a) a metal lattice extending laterally between the bond pad and the substrate and (b) barrier members extending vertically between the metal lattice and the bond pad., 'a metallization structure over the substrate, wherein the metallization structure includes—'}2. The semiconductor device of wherein the crack-inhibiting structure is not electrically coupled to any of the circuit elements.3. The semiconductor device of wherein the metal lattice defines a plurality of openings claim 1 , and wherein the insulating material is in the openings.4. The semiconductor device of wherein the openings have a rectilinear cross-sectional shape.5. The semiconductor device of wherein the metal lattice includes a first surface facing the bond pad claim 1 , and wherein the first surface includes first lanes extending ...

Package with Solder Regions Aligned to Recesses

A method includes forming a passivation layer over a portion of a metal pad, forming a polymer layer over the passivation layer, and exposing the polymer layer using a photolithography mask. The photolithography mask has an opaque portion, a transparent portion, and a partial transparent portion. The exposed polymer layer is developed to form an opening, wherein the metal pad is exposed through the opening. A Post-Passivation Interconnect (PPI) is formed over the polymer layer, wherein the PPI includes a portion extending into the opening to connect to the metal pad.

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE

Some example embodiments relate to a semiconductor device and a semiconductor package. The semiconductor package includes a substrate including a conductive layer, an insulating layer coating the substrate, the insulating layer including an opening exposing at least part of the conductive layer, and an under-bump metal layer electrically connected to the at least part of the conductive layer exposed through the opening, wherein the insulating layer includes at least one recess adjacent to the opening, and the under-bump metal layer fills the at least one recess. The semiconductor device and the semiconductor package may have improved drop test characteristics and impact resistance. 1. A semiconductor device comprising:a substrate including a first insulating layer and a conductive layer;a second insulating layer coating the substrate, the second insulating layer including an opening exposing at least part of the conductive layer and two or more recesses encircling the opening, each of sidewalls of the opening and the recesses being slanted at an obtuse angle with regard to bottoms of the opening and the recesses;an under-bump metal layer electrically connected to the at least part of the conductive layer;a via physically contacting both the under-bump metal layer and the at least part of the conductive layer; anda solder bump on the under-bump metal layer,wherein the two or more recesses are not physically in contact with the conductive layer,wherein a depth of the two or more recesses is about 10% to about 90% of a height of the via, andwherein the two or more recesses are circular trenches surrounding the opening, and a sidewall of the under-bump metal layer is disposed farther from the center of the opening than the sidewalls of the recesses.2. The semiconductor device of claim 1 , wherein the sidewall and a bottom of the recess do not have an interface therebetween.3. The semiconductor device of claim 1 , wherein the conductive layer includes a first conductive ...

Solderless Interconnection Structure and Method of Forming Same

An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion. 1. A device comprising:a substrate trace extending along a first substrate, the substrate trace having a first shape in a plan view; anda metal ladder bump extending from an integrated circuit, the metal ladder bump having a second shape in the plan view, the second shape being different from the first shape,wherein the metal ladder bump and the substrate trace are physically and electrically coupled together through direct metal-to-metal bonds, an interface between the metal ladder bump and the substrate trace being free from solder.2. The device of claim 1 , wherein the substrate trace has a first length claim 1 , the metal ladder bump has a second length claim 1 , and the first length is greater than the second length claim 1 , the first length and the second length each being measured in a direction parallel to a longitudinal axis of the substrate trace.3. The device of claim 1 , wherein the second shape is a quadrilateral.4. The device of claim 1 , wherein the second shape is a circle.5. The device of claim 1 , wherein the metal ladder bump and the substrate trace are copper claim 1 , and wherein the interface between the metal ladder bump and the substrate trace is free from intermetallic compounds.6. The device of claim 1 , wherein the substrate trace has a first end proximate the first substrate and a second end distal the first substrate claim 1 , the first end having a greater width than the second end. ...

用于控制半导体芯片封装相互作用的应变补偿填充图案

本发明涉及一种用于控制半导体芯片封装相互作用的应变补偿填充图案，一般来说，本文所披露的主题涉及到复杂的半导体芯片，其在比如倒装芯片或3D芯片装配之类的半导体芯片封装操作期间较不易有白凸点的发生。本文所披露的一个说明性的半导体芯片包括，除其它外，接合垫和在接合垫下方的金属化层，其中金属化层是由接合垫下方的接合垫区域和围绕接合垫区域的空旷区域所构成。此外，半导体器件还包括在金属化层中的多个器件特征，其中所述多个器件特征具有在接合垫区域中的第一特征密度和在空旷区域中小于第一特征密度的第二特征密度。

Semiconductor device having resin members provided separately corresponding to externally connecting electrodes

반도체 칩 상에 배치된 복수의 외부 접속 전극(8)을 구비한 반도체 디바이스는 온-칩(on-chip) 전극(2), 상호 분리되어 형성되고 복수의 외부 접속 전극(8)에 대응하여 제공되는 수지 부재(5), 및 대응 온-칩 전극(2)과 대응 외부 접속 전극(8)을 접속시키는 배선(6)을 포함한다. 외부 접속 전극(8)에 대해 이렇게 분리되어 형성된 수지 부재(5)는 외부 접속 전극(8)에 발생되는 열 응력을 완화시킨다. A semiconductor device having a plurality of external connection electrodes 8 disposed on a semiconductor chip is formed on the on-chip electrode 2, separated from each other, and provided correspondingly to the plurality of external connection electrodes 8. The resin member 5 which becomes, and the wiring 6 which connects the corresponding on-chip electrode 2 and the corresponding external connection electrode 8 are included. The resin member 5 formed in such a manner as to be separated from the external connection electrode 8 relieves thermal stress generated in the external connection electrode 8.

Semiconductor components having encapsulated through wire interconnects (TWI)

A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) attached to the substrate contact. The through wire interconnect provides a multi level interconnect having contacts on opposing first and second sides of the semiconductor substrate. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a wire in the via having a bonded connection with the substrate contact, a first contact on the wire proximate to the first side, and a second contact on the wire proximate to the second side. The through wire interconnect (TWI) also includes a polymer layer which partially encapsulates the through wire interconnect (TWI) while leaving the first contact exposed. The semiconductor component can be used to fabricate stacked systems, module systems and test systems. A method for fabricating the semiconductor component can include a film assisted molding process for forming the polymer layer.

Attachment structure and manufacture method thereof

本发明公开了一种连接结构及其制造方法。该连接结构包含半导体基板、金属层、钝化层以及导电结构。金属层位于半导体基板的上方。钝化层位于金属层的上方，且包含一个开口。导电结构具有图案化表面结构，图案化表面结构通过钝化层的开口与金属层接触。借此，本发明的连接结构及其制造方法，其中连接结构的图案化表面结构，可改善在回焊期间的晶片翘曲，以避免晶片破裂并增加可靠性，还降低整体的翘曲级。

Bonding process for CMOS image sensor

本发明提供了一种用于CMOS图像传感器的结合处理。本发明还提供了一种制造集成电路(IC)的方法。该方法包括：在衬底的前侧上形成电器件；在衬底的前侧上形成顶部金属焊盘，该顶部金属焊盘连接至电器件；在衬底的前侧上形成钝化层，顶部金属焊盘被嵌入钝化层中；在钝化层中形成开口，使顶部金属焊盘暴露；在衬底中形成深沟槽；将导电材料填充在深沟槽和开口中，得到深沟槽中的晶圆通孔(TWV)部件和开口中的焊盘-TWV部件，其中，顶部金属焊盘通过焊盘-TWV部件连接至TWV部件；以及进行抛光处理以去除多余的导电材料，形成基本平坦的表面。

Semiconductor device and method for manufacturing thereof

The semiconductor device and manufacturing method thereof are provided to improve speed and the integration of the semiconductor device by using the interlayer insulating film as the low-K dielectric layer in forming the copper wiring. The semiconductor device comprises the semiconductor substrate(10), the first insulation layer(20), the first interconnection trench(41), the first pad trench(45), the first metal wiring(51), the first pad(55), the second insulation layer, the second wiring trench(82), the second pad trench(85), the second pad(95). The semiconductor substrate comprises the cell region(A) and pad area(B). The first insulation layer is formed in the semiconductor substrate. The first interconnection trench is formed in the first insulation layer of the cell region and has the first width. The first pad trench has the second width which is broader than the first breadth and is formed in the first insulation layer of the pad area. The first pad is formed inside of the first metal wiring and the first pad trench formed inside of the first interconnection trench. The second insulation layer is formed on the first insulation layer. The second wiring trench is formed in the second insulation layer in order to expose the first metal wiring. The second pad trench exposes the first pad trench and is formed in the second insulation layer to have the same location and width of the first pad trench. The second pad is formed in the second metal wiring and the second pad trench formed in the second wiring trench.

Semiconductor device

Semiconductor Device and Manufacturing Method Thereof

본 발명에서는 재배선층 중 UBM이 형성되는 접속 영역 및 접속 영역을 제외한 다른 영역의 너비를 모두 동일하게 형성함으로써, 재배선층 경로 설계시 공간의 확보가 용이한 반도체 디바이스 및 그 제조 방법이 개시된다. 일 예로, 다수의 본드 패드가 형성된 반도체 다이; 상기 반도체 다이의 상부에 형성되며 일단부가 상기 본드 패드와 전기적으로 연결되는 재배선층; 상기 재배선층의 타단부에 형성되며 상기 재배선층과 전기적으로 연결되는 UBM; 및 상기 UBM과 접속하는 범프를 포함하고, 상기 재배선층은 상기 UBM이 형성되는 접속 영역 및 상기 접속 영역을 제외한 다른 영역의 너비가 동일하게 형성되는 반도체 디바이스가 개시된다. The present invention discloses a semiconductor device and a manufacturing method thereof, in which space is easily secured in designing a rewiring layer path by forming the same widths of regions other than the connection region and the connection region where the UBMs are formed in the rewiring layer. As an example, a semiconductor die having a plurality of bond pads formed therein; A re-wiring layer formed on the semiconductor die and having one end electrically connected to the bond pad; A UBM formed at the other end of the re-distribution layer and electrically connected to the re-distribution layer; And a bump connected to the UBM, wherein the re-wiring layer is formed such that the connection area where the UBM is formed and the other area except the connection area are formed to have the same width.

Semiconductor device

The method and application of silicon chip and molybdenum sheet welding in a kind of semiconductor devices

本发明公开了一种半导体器件中硅片和钼片焊接的方法，所述方法包括以下步骤：a.在钼片上设置第一银层；b.在硅片的阳极上设置第二银层；c.将第三银层设置于第一银层和第二银层之间；d.通过第一银层、第二银层和第三银层的焊接，从而将硅片与钼片焊接在一起。该方法工艺简单，成品率高，焊接强度高、焊接层空洞率低，变形量小，可大大的提高产品的性能。本发明还涉及上述方法制得的硅片/钼片焊接产品的应用。

Semiconductor light emitting diode and semiconductor light emitting diode package using the same

본 발명은 제1 및 제2 전극이 배치된 제1 면과 상기 제1 면의 반대에 위치한 제2면을 갖는 발광다이오드 칩; 상기 제1 및 제2 전극의 본딩 영역들이 노출되도록 상기 발광다이오드 칩의 표면에 배치된 패시베이션층; 상기 본딩 영역들에 각각 배치되며 각각 분리된 복수의 영역을 갖는 복수의 솔더 패드; 상기 본딩 영역들에 각각 배치되며, 각각 상기 솔더 패드의 상기 분리된 복수의 영역을 덮는 복수의 솔더 범프;를 포함하여, 솔더 패드와 솔더 범프 사이의 계면이 손상되어 분리되는 것을 효과적으로 차단할 수 있다. The present invention includes a light emitting diode chip having a first surface on which first and second electrodes are disposed and a second surface opposite to the first surface; A passivation layer disposed on the surface of the LED chip to expose bonding regions of the first and second electrodes; A plurality of solder pads disposed on the bonding areas and each having a plurality of separated areas; Including a plurality of solder bumps disposed on the bonding regions, each covering the separated plurality of regions of the solder pad, it is possible to effectively block separation due to damage to the interface between the solder pad and the solder bump.

Semiconductor device and manufacturing method the same and mounting structure of semiconductor device

본 발명의 목적은 언더필이 불필요한 플립 칩 접속을 가능하게 하는 반도체 장치를 실현하는 데 있다. An object of the present invention is to realize a semiconductor device which enables flip chip connection without underfilling. 본 발명은, 복수의 회로 전극이 배열되며, 보호막이 피복된 회로면을 구비한 반도체 소자와, 상기 반도체 소자의 회로면의 보호막 상에 상기 회로 전극을 노출시켜 형성되고, 경화된 열가소성 수지로 이루어지며, 엣지부에 경사를 형성한 응력 완화층과, 상기 회로 전극의 각각에 접속되어 그 회로 전극으로부터 상기 응력 완화층의 엣지부를 통해서 응력 완화층의 표면의 원하는 개소까지 전기적으로 연결되어 배치되는 복수의 배선으로 이루어지는 배선층과, 그 위의 표면 보호막과, 외부 접속 단자를 포함하여 구성된 반도체 장치이다. The present invention comprises a semiconductor element having a plurality of circuit electrodes arranged thereon and having a circuit surface coated with a protective film, and formed by exposing the circuit electrode on a protective film of the circuit surface of the semiconductor element and cured thermoplastic resin. And a plurality of stress relaxation layers each having an inclined edge portion, and electrically connected to each of the circuit electrodes and electrically connected from the circuit electrode to a desired portion of the surface of the stress relaxation layer through an edge portion of the stress relaxation layer. A semiconductor device including a wiring layer made of wiring, a surface protective film thereon, and an external connection terminal.

SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD

L'invention propose un dispositif à semi-conducteur dans lequel plusieurs substrats semi-conducteurs portant chacun des éléments semi-conducteurs sont liés ensemble. Sur chaque substrat semi-conducteur (1, 2), est déposée une couche isolante (7, 8) à travers laquelle est formé un câblage de connexion (5, 6) traversant la couche isolante de façon à être connecté à la couche d'interconnexion de l'élément semi-conducteur. Sur la surface de jonction d'au moins un des substrats semi-conducteurs (1, 2) est formée une couche électriquement conductrice (9, 10) faite d'un matériau électriquement conducteur, dans laquelle une ouverture est percée en association avec le câblage de connexion (5, 6). Les substrats semi-conducteurs sont liés ensemble par la technique de liaison du type état solide afin d'interconnecter les câblages de connexion formés sur chaque substrat semi-conducteur.

Semiconductor device

In the semiconductor device, externally connecting electrodes are placed on a semiconductor substrate. A rewiring pattern for connecting each on-chip electrode to corresponding external connecting electrode is routed, in the vicinity of the externally connecting electrode, in a direction where the effect of strain after mounting of the semiconductor substrate is small. Specifically, the rewiring pattern is routed such that the routing direction will not match the direction coupling the center of the semiconductor substrate to the externally connecting electrode along which large thermal stress is expected. Accordingly, strain that will occur at the rewiring pattern after mounting the semiconductor substrate to the mounting board is reduced. Adverse effects of the strain stress can be prevented without widening the externally connecting interconnection.

METHOD FOR PRODUCING AN INTEGRATED CIRCUIT BY DIRECT COLLAGEING OF SUBSTRATES COMPRISING SURFACE PORTIONS OF COPPER AND DIELECTRIC MATERIAL

Procédé de réalisation d'un circuit intégré par collage direct d'un premier (201) et d'un second (301) substrats, comprenant les étapes suivantes consistant à a) former un premier et un second substrats munis chacun d'une surface comportant au moins une portion d'un premier matériau (205, 305) et des portions d'au moins un deuxième matériau (203, 303), une région de barrière (209, 309) en un troisième matériau étant disposée en surface entre chaque portion du premier matériau et le deuxième matériau; et b) mettre en contact la surface du premier substrat avec la surface du second substrat avec un désalignement maximum donné, la largeur de la région de barrière formée à l'étape a) étant choisie de sorte qu'elle soit supérieure au désalignement maximum. A method of making an integrated circuit by directly bonding a first (201) and a second (301) substrate, comprising the steps of a) forming first and second substrates each having a surface comprising at least a portion of a first material (205, 305) and portions of at least one second material (203, 303), a barrier region (209, 309) of a third material being disposed at the surface between each portion the first material and the second material; and b) contacting the surface of the first substrate with the surface of the second substrate with a given maximum misalignment, the width of the barrier region formed in step a) being chosen such that it is greater than the maximum misalignment.

Semiconductor device and method for manufacturing the same and semiconductor device-mounted structure

A semiconductor device is provided which enables a flip chip connection without use of underfill. The semiconductor device includes a semiconductor element having circuit electrodes and a circuit surface coated with a protecting film. A stress relaxation layer is provided by coating a cured thermoplastic resin onto the protecting film of the circuit surface in a manner which leaves the circuit electrodes exposed and curing it and having an inclination in the edge portion thereof. A wiring layer with wirings is connected to each of the circuit electrodes and disposed so as to make an electrical connection from the circuit electrodes, via the edge portion of the stress relaxation layer, and to a desired portion on the surface of the stress relaxation layer. A protecting film is provided thereon, and an external connection terminal is also provided.

Chip size package and the manufacturing method

본 발명은 웨이퍼 레벨의 칩 사이즈 패키지 및 그 제조방법에 관한 것으로서, 본 발명은 소정 위치에 칩패드가 형성된 웨이퍼칩과, 상기 칩패드의 상면이 노출되도록 상기 웨이퍼칩의 상측에 형성된 절연유전층과, 상기 절연유전층의 상면에 국부적으로 형성된 로우 모듈러스 폴리머층(이하, LMP층이라 함)과, 상기 LMP층과 칩패드를 전기적으로 연결하도록 상기 절연유전층의 상측에 형성된 금속배선층과, 상기 LMP층의 상측에 위치된 금속배선층의 상면이 노출되도록 상기 금속배선층의 상측에 형성된 솔더마스크용 폴리머층과, 상기 LMP층 상측의 금속배선층 상면에 접합된 솔더볼을 포함한 웨이퍼 레벨의 칩 사이즈 패키지 및 이를 제조하기 위한 제조방법을 함께 제공함으로써 웨이퍼칩과 회로기판 사이에서 열팽창 계수의 차이로 인해 발생되는 열응력을 흡수하기 위해 솔더볼 하측에 형성된 LMP층을 기존과 같이 웨이퍼칩의 전면에 형성시키지 않고 필요한 부분에만 국부적으로 형성시켜 공정성과 솔더조인트의 신뢰성이 동시에 향상되도록 한 것이다. The present invention relates to a wafer-level chip size package and a method of manufacturing the same. The present invention relates to a wafer chip having a chip pad formed at a predetermined position, an insulating dielectric layer formed on an upper side of the wafer chip to expose an upper surface of the chip pad, A low modulus polymer layer (hereinafter referred to as an LMP layer) formed locally on an upper surface of the insulating dielectric layer, a metal wiring layer formed on an upper side of the insulating dielectric layer so as to electrically connect the LMP layer and the chip pad, and an upper side of the LMP layer. A wafer-level chip size package including a solder mask polymer layer formed on the upper surface of the metal wiring layer so that the upper surface of the metal wiring layer positioned on the upper surface of the metal wiring layer, and solder balls bonded to the upper surface of the metal wiring layer on the upper side of the LMP layer, and fabricated therein By providing a method, thermal stress caused by the difference in coefficient of thermal expansion between the wafer chip and the circuit board To a locally formed in only where needed, without forming a front surface of the wafer chip, as the existing LMP layer formed on the lower side solder balls to absorb it to the improved reliability and fairness of the solder joint at the same time.

Strain-compensating fill patterns for controlling semiconductor chip package interactions

Generally, the subject matter disclosed herein relates to sophisticated semiconductor chips that may be less susceptible to the occurrence of white bumps during semiconductor chip packaging operations, such as flip-chip or 3D-chip assembly, and the like. One illustrative semiconductor chip disclosed herein includes, among other things, a bond pad and a metallization layer below the bond pad, wherein the metallization layer is made up of a bond pad area below the bond pad and a field area surrounding the bond pad area. Additionally, the semiconductor device also includes a plurality of device features in the metallization layer, wherein the plurality of device features has a first feature density in the bond pad area and a second feature density in the field area that is less than the first feature density.

Metal bump and method of manufacturing same

本发明提供了一种凸块结构的实施例，包括：形成在衬底上的接触元件；覆盖衬底的钝化层，钝化层具有露出接触元件的钝化开口；覆盖钝化层的聚酰亚胺层，聚酰亚胺层具有露出接触元件的聚酰亚胺开口；电连接至接触元件的凸块下金属化层（UBM）部件，凸块下金属化层部件具有UBM宽度；以及位于凸块下金属化层部件上的铜柱，铜柱的远端具有铜柱宽度，并且UMB宽度大于铜柱宽度。本发明还提供了一种形成凸块结构的方法。

Bond pad structure

本发明涉及一种接合垫结构。集成电路晶片的接合垫结构中，有一应力缓冲层介于接合垫层与最上层内连线层的金属层之间，以避免晶圆的探针测试与封装撞击对接合垫所造成的破坏。该应力缓冲层为一导电材料，其杨氏模数、硬度、强度或坚韧度大于最上层内连线层的金属层或该接合垫层的杨氏模数、硬度、强度或坚韧度。为改善粘合与接合的强度，可将应力缓冲层的底部修改为各种不同形式，如嵌于保护层的环状、网状或连锁栅格结构，在应力缓冲层中可以有多个孔洞，其由接合垫层将之填满。本发明所述接合垫结构，提供较佳的机械完整性。可避免应力造成的失效与接垫剥离的问题，而大大增加接合的可靠度。

Bump structure and forming the same

本發明提供一種凸塊結構，包括：一凸塊下方金屬化(UBM)特徵結構位於一基板之上；一銅柱位於該凸塊下方金屬化(UBM)特徵結構之上，其中該銅柱具有一梯形彎曲化剖面(taping curved profile)；一金屬蓋設置於該銅柱之上；以及一焊料特徵結構設置於該金屬蓋之上。

Method for producing contacts and printed circuit packages

The invention concerns a method for producing electrical contact connections for at least an component integrated to a support material which includes a first surface zone, at least a connecting contact being arranged at least partly in said first surface zone for each component. The method is characterized in that a covering element is placed on the first surface zone and at least a contact channel extends in the support material perpendicular to the first surface zone. To form at least a contact point in a second surface zone to be prepared, at least an electrical contact connection is established via respective contact channels between the contact point and at least one of the connecting contacts. Very advantageously, a contact point of this type can be produced on the surface of the support material opposite the connecting contact and thus on the surface of the support material opposite the active surface a contact point electrically connected to the connecting contact. Said technique replaces the prior technique whereby the trenches extend along the support material and the contacts are established laterally around a component.

Pad structure, semiconductor die using the same and manufacturing method thereof

一種接墊結構、應用其之半導體晶片及其製造方法。接墊結構形成在三五族基板上。接墊結構包括第一導電層、介電層、第二導電層及電路。介電層形成在第一導電層上且具有貫穿孔，貫穿孔露出第一導電層。第二導電層包括鉚合部及接墊部，鉚合部填滿貫穿孔並連接於第一導電層，而接墊部形成在介電層上方。

Semiconductor device

Method of manufacturing semiconductor device including forming inter-layer insulating film on semiconductor substrate. First metal film is formed on inter-layer insulating film. First resist is formed on first metal film and patterned. Anisotropic etching performed on first metal film using first resist as mask. First resist is removed and second metal film is formed on inter-layer insulating film to cover remaining first metal film. Second resist is formed on second metal film in area where first metal film exists on inter-layer insulating film and part of area where first metal film does not exist. Anisotropic etching is performed on second metal film using second resist as mask and bonding pad having first metal film and second metal film, and upper layer wiring having second metal film and not first metal film. Second resist is removed. Surface protection film covering bonding pad is formed. Pad opening is formed on bonding pad.

Redistribution layer (rdl) structure, semiconductor device and manufacturing method thereof

The present disclosure provides a redistribution layer (RDL) structure, a semiconductor device and manufacturing method thereof. The semiconductor device comprises an RDL structure that may include a substrate, a first conductive layer, a reinforcement layer and a second conductive layer. The first conductive layer may be formed on the substrate and has a first bond pad area. The reinforcement layer may be formed on a surface of the first conductive layer facing away from the substrate and located in the first bond pad area. The second conductive layer may be formed on the reinforcement layer and an area of the first conductive layer not covered by the reinforcement layer. The reinforcement layer has a material strength greater than those of the first conductive layer and the second conductive layer. The semiconductor device and the manufacturing method provided by the present disclosure may improve the performance of the semiconductor device.

SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND ELECTRONIC DEVICE

Semiconductor package, semiconductor device, electronic device, and method for producing semiconductor package

An insulating layer (3) having an opening portion (3a) at a position conformable to an electrode pad (2) is formed. Next, a resin projection portion (4) is formed on the insulating layer (3). Thereafter, a resist film is formed which has opening portions made in regions conformable to the opening portion (3a), the resin projection portion (4) and the region sandwiched therebetween. A Cu plating layer (6) is formed by electrolytic copper plating, using the resist film as a mask.

Semiconductor component manufacturing method, involves separating insulating layer on semiconductor substrate and producing connection strip conductor connected with strip conductor layer of semiconductor elements in layer.

The method involves separating an insulating layer on a semiconductor substrate and producing a connection strip conductor connected with a strip conductor layer of the semiconductor elements in the layer. An electrically leading layer is produced with an inlet formed by structuring in agreement with the connection strip conductor. The substrates are connected with each other in order to connect the conductor strips on every substrate.

Semiconductor device and method of manufacturing the same

A semiconductor device is provided. The semiconductor device includes an electrode pad provided above a semiconductor substrate; and a wire bonded on the electrode pad and including copper. The electrode pad includes an electrode layer including aluminum and a support layer harder than the wire and the electrode layer. The wire is in contact with the electrode layer and the support layer.

Semiconductor device

반도체장치에서, 외부접속전극(8)은 반도체기판(1)상에 위치한다. 각각의 온칩(on-chip)전극(2)을 대응하는 외부접속전극(8)에 접속하기 위한 재배선 패턴(6)은, 외부접속전극(8)의 주변에서, 반도체기판(1)의 설치 후 왜곡의 효과가 적은 방향으로 배선된다. 특히, 재배선 패턴(6)은, 배선방향이 반도체기판(1)의 중심(11)을 큰 열응력이 기대되는 외부접속전극(8)에 연결하는 방향과 일치하지 않도록 배선된다. 따라서, 반도체기판(1)을 실장 기판에 설치한 후 재배선 패턴(6)에서 발생하는 왜곡은 줄어든다. 왜곡응력의 악영향은, 외부접속배선의 폭을 넓히지 않고 방지될 수 있다. In the semiconductor device, the external connection electrode 8 is located on the semiconductor substrate 1. The redistribution pattern 6 for connecting each on-chip electrode 2 to the corresponding external connection electrode 8 is provided with the semiconductor substrate 1 around the external connection electrode 8. Afterwards, the effect of distortion is wired in a lesser direction. In particular, the redistribution pattern 6 is wired so that the wiring direction does not coincide with the direction connecting the center 11 of the semiconductor substrate 1 to the external connection electrode 8 where large thermal stress is expected. Therefore, the distortion generated in the redistribution pattern 6 after the semiconductor substrate 1 is provided on the mounting substrate is reduced. The adverse effect of the distortion stress can be prevented without widening the width of the external connection wiring.

Semiconductor package

본 발명의 일 실시예는, 복수의 반도체 칩들 중 적어도 하나의 반도체 칩은, 반도체 층 및 제3 면을 갖는 패시베이션층을 포함하는 반도체 기판, 제3 면 상에 배치되는 후면 패드, 및 반도체 기판을 관통하는 관통 비아를 포함하고, 후면 패드는 제3 면 상에 배치되는 전극 패드부 및 전극 패드부의 일측에서 돌출되며 관통 비아의 측면을 둘러싸는 댐(dam) 구조를 포함하고, 댐 구조는 관통 비아의 측면과 이격되는 반도체 패키지를 제공한다.

Bonding process for cmos image sensor

The present disclosure provides a method of making an integrated circuit (IC). The method includes forming an electric device on a front side of a substrate; forming a top metal pad on the front side of the substrate, the top metal pad being coupled to the electric device; forming a passivation layer on the front side of the substrate, the top metal pad being embedded in the passivation layer; forming an opening in the passivation layer, exposing the top metal pad; forming a deep trench in the substrate; filling a conductive material in the deep trench and the opening, resulting in a though-wafer via (TWV) feature in the deep trench and a pad-TWV feature in the opening, where the top metal pad being connected to the TWV feature through the pad-TWV feature; and applying a polishing process to remove excessive conductive material, forming a substantially planar surface.

Semiconductor device and its manufacturing method, circuit board and electronic equipment

【課題】 大型チップに対応し、細密配線によって多数の外部端子が形成可能で、かつ接続信頼性の高い半導体装置等を提供する。 【解決手段】 複数の電極９を有する半導体素子２に、１又は複数の樹脂層と、電極９に電気的に接続する複数の配線４と、該配線４に電気的に接続する複数の外部端子７が形成された半導体装置１であって、複数の配線４の一部又は全部が、電極９と接続される部分から半導体素子２の中心１０方向に向かう第１の配線部４ａと、該第１の配線部４ａと接続され、半導体素子２の中心１０方向から外側に向かって外部端子７と接続される第２の配線部４ｂとから形成され、第１の配線部４ａと第２の配線部４ｂの間に、少なくとも１つの樹脂層が形成されているものである。 【選択図】 図１

Die attach material for TBGA or flexible circuitry

An attachment material is provided between the die and the solder balls of a TBGA or other flexible circuitry package that is sufficiently compliant to absorb pressure between the two, so as not to apply stress to the solder balls. The attachment material is also sufficiently rigid, with a low coefficient of thermal expansion (CTE), so that the material does not excessively expand and contract during thermal cycling relative to the die. More preferably, the attachment material has a CTE close to that of the die to prevent breakage of the tape at the junction between the tape and the die.

Semiconductor device and semiconductor device manufacturing method

【課題】半導体装置の特性を向上させる。【解決手段】配線Ｍ１上に形成され、開口部ＯＡ１を有する保護膜ＰＲＯ１と、開口部ＯＡ１内に形成されためっき膜ＯＰＭ１とを有するように半導体装置を構成する。そして、開口部ＯＡ１の側面には、スリットＳＬが設けられ、このスリットＳＬ内にもめっき膜ＯＰＭ１が配置されている。このように、開口部ＯＡ１の側面に、スリットＳＬを設け、その内部にもめっき膜ＯＰＭ１を成長させることにより、以降のめっき膜の形成時において、めっき液の侵入経路が長くなる。このため、配線（パッド領域ＰＤ）Ｍ１に腐食部が生じにくくなる。また、腐食部が生じた場合でも、スリットＳＬの部分が、配線（パッド領域ＰＤ）Ｍ１より先に犠牲となって腐食するため、配線（パッド領域ＰＤ）Ｍ１まで腐食部が進行することを抑制することができる。【選択図】図１

Bonding process for CMOS image sensor

本发明提供了一种用于CMOS图像传感器的结合处理。本发明还提供了一种制造集成电路(IC)的方法。该方法包括：在衬底的前侧上形成电器件；在衬底的前侧上形成顶部金属焊盘，该顶部金属焊盘连接至电器件；在衬底的前侧上形成钝化层，顶部金属焊盘被嵌入钝化层中；在钝化层中形成开口，使顶部金属焊盘暴露；在衬底中形成深沟槽；将导电材料填充在深沟槽和开口中，得到深沟槽中的晶圆通孔(TWV)部件和开口中的焊盘-TWV部件，其中，顶部金属焊盘通过焊盘-TWV部件连接至TWV部件；以及进行抛光处理以去除多余的导电材料，形成基本平坦的表面。

Method for manufacturing an interconnect structure for stacked semiconductor device

In a multi-layer interconnection structure, the wiring length is to be reduced, and the interconnection is to be straightened, at the same time as measures need to be taken against radiation noise. To this end, there is disclosed a semiconductor device in which plural semiconductor substrates, each carrying semiconductor elements, are bonded together. On each semiconductor substrate is deposited an insulating layer through which is formed a connection wiring passed through the insulating layer so as to be connected to the interconnection layer of the semiconductor element. On a junction surface of at least one of the semiconductor substrates is formed an electrically conductive layer of an electrically conductive material in which an opening is bored in association with the connection wiring. The semiconductor substrates are bonded together by the solid state bonding technique to interconnect the connection wirings formed on each semiconductor substrate.

Pad structure, semiconductor die using the same and manufacturing method thereof

一種接墊結構、應用其之半導體晶片及其製造方法。接墊結構形成在三五族基板上。接墊結構包括第一導電層、介電層、第二導電層及電路。介電層形成在第一導電層上且具有貫穿孔，貫穿孔露出第一導電層。第二導電層包括鉚合部及接墊部，鉚合部填滿貫穿孔並連接於第一導電層，而接墊部形成在介電層上方。

Semiconductor process, semiconductor element and package having semiconductor element

The present invention relates to a semiconductor process, a semiconductor element and a package having a semiconductor element. The semiconductor element includes a base material and at least one through via structure. The base material has a first surface, a second surface, at least one groove and at least one foundation. The groove opens at the first surface, and the foundation is disposed on the first surface. The through via structure is disposed in the groove of the base material, and protrudes from the first surface of the base material. The foundation surrounds the through via structure. Whereby, the foundation increases the strength of the through via structure, and prevents the through via structure from cracking.

Method and device for solder joints

Verfahren und Bauelement für Lötverbindungen. Ein Bauelement enthält ein Substrat mit einem leitfähigen Anschluss auf einer Fläche; eine Passivierungsschicht, die über der Oberfläche des Substrats und des leitfähigen Anschlusses liegt; eine Öffnung in der Passivierungsschicht, die einen Abschnitt des leitfähigen Anschlusses frei legt; mindestens einen Stud-Bondhügel, der an den leitfähigen Anschluss in der Öffnung gebondet ist und sich in einer Richtung senkrecht zur Substratoberfläche erstreckt; und eine Lötverbindung, die an dem leitfähigen Anschluss in der Öffnung ausgebildet ist und den mindestens einen Stud-Bondhügel umschließt. Verfahren zum Ausbilden der Lötverbindungen werden offenbart. Method and device for solder joints. A device includes a substrate having a conductive terminal on a surface; a passivation layer overlying the surface of the substrate and the conductive terminal; an opening in the passivation layer exposing a portion of the conductive terminal; at least one stud bump bonded to the conductive port in the opening and extending in a direction perpendicular to the substrate surface; and a solder joint formed on the conductive terminal in the opening and enclosing the at least one stud bump. Methods for forming the solder joints are disclosed.

Method for fabrication of wafer level package incorporating dual compliant layers

A method is provided for forming wafer level package that incorporates dual compliant layers and a metal cap layer on top of I/O pads. The wafer level package includes a plurality of metal cap layers formed on top of a plurality of I/O pads to function as stress buffering and avoiding sharp corners in metal traces formed on top of the metal cap layers. A first compliant layer and a second compliant layer are formed under the metal trace to provide the necessary standoff and to accommodate differences in coefficients of thermal expansion of the various materials on an IC die. The wafer level package is particularly suitable for copper devices or in devices wherein copper lines are used.

Semiconductor device structure

A semiconductor device includes a conductive layer with a plurality of wires, and a bonding pad formed in a region overlapping with the plurality of wires of the conductive layer. One of the wires is connected to the bonding pad, and an insulating protective film is formed between the remaining wires and the bonding pad. The protective film is bridged between adjacent wires at least in a region overlapping with the bonding pad. As a result, the protective film on the wires forms a bridge structure, which is effective in preventing cracking at a lower portion of the protective film. Further, a void formed underneath the bridged portion serves as an air spring to prevent damage to the structural elements, such as the wires, formed under the protective film. Further, because a polyimide film, which serves as a shock absorber, is not required, working efficiency can be improved and chip cost can be reduced.

Electronic component and method for producing the same

An aspect of the invention is an electronic component including a semiconductor substrate 11 that has an electrode pad 12 , a first resin layer 14 and a third resin layer 15 that are located above the semiconductor substrate, a second resin layer 16 that is formed such that at least portions of the second resin layer are located on the first resin layer and the third resin layer, a resin projection 17 that includes the first to third resin layers and is higher than the first resin layer, and a wiring layer 24 that is electrically connected to the electrode pad and lies above the resin projection.

Semiconductor module system having stacked components with encapsulated through wire interconnects (TWI)

A semiconductor module system includes a module substrate and first and second semiconductor components stacked on the module substrate. The stacked semiconductor components include through wire interconnects that form an internal signal transmission system for the module system. Each through wire interconnect includes a via, a wire in the via and first and second contacts on the wire.

Semiconductor chip and semiconductor device

In this semiconductor chip 3 , a table electrode 13 is interposed between a bump electrode 14 and an electrode pad 6 . The table electrode 13 is formed by forming a plurality of cores 15 having a smaller Young's modulus than the bump electrode 14 , on the electrode pad 6 , and then covering the surfaces of the cores 15 with a conductive electrode 16 . When the semiconductor chip 3 is flip-chip mounted, the bump electrode 14 is plastically deformed and the table electrode 13 is elastically deformed appropriately, thereby obtaining a good conductive state.

The production method of wafer bonding structure and wafer bonding structure

本申请提供一种晶圆键合结构及其形成方法。所述晶圆键合结构包括：第一晶圆；第一介质层，位于所述第一晶圆上；金属互连结构，位于所述第一介质层中，且所述金属互连结构被分隔成至少两个局部连通的子金属互连结构。所述的晶圆键合结构以及形成方法，将所述金属互连结构的表面分隔为至少两个局部连通的子金属互连结构，不仅实现了个子金属互连结构之间的电连接，还减小了进行键合时键合面的表面积，提高了晶圆之间的电连接质量。

Semiconductor device with bump structure on an interconncet structure

A semiconductor device includes a post-passivation interconnect (PPI) structure having a landing pad region. A polymer layer is formed on the PPI structure and patterned with a first opening and a second opening to expose portions of the landing pad region. The second opening is a ring-shaped opening surrounding the first opening. A bump structure is formed on the polymer layer to electrically connect the landing pad region through the first opening and the second opening.

Integrated circuit chip and flip chip package having the integrated circuit chip

In an integrated circuit (IC) chip and a flip chip package having the same, no wiring line is provided and the first electrode pad does not make contact with the wiring line in a pad area of the IC chip. Thus, the first bump structure makes contact with the first electrode regardless of the wiring line in the pad area. The second electrode pad makes contact with the wiring line in a pseudo pad area of the IC chip. Thus, the second bump structure in the pseudo pad area makes contact with an upper surface of the second electrode at a contact point(s) spaced apart from the wiring line under the second electrode.

Photosensitive resin composition, method for producing patterned cured film, semiconductor element and electronic device

Wafer level chip scale package, method of manufacturing the same, and semiconductor chip module including the wafer level chip scale package

Provided are a wafer level chip scale package in which a redistribution process is applied at a wafer level, a manufacturing method thereof, and a semiconductor chip module including the wafer level chip scale package. The wafer level chip scale package includes a semiconductor chip having a bonding pad, a first insulating layer disposed on the semiconductor chip so as to expose the bonding pad, a redistribution line disposed on the exposed bonding pad and the first insulating layer, a sacrificial layer disposed below a redistribution pad of the redistribution line, a second insulating layer disposed on the redistribution line so as to expose the redistribution pad and including a crack inducement hole disposed beside the sacrificial layer, and an external connection terminal attached to the redistribution pad.

Semiconductor device and method of manufacturing same

Semiconductor device, method of manufacturing thereof, circuit board and electronic apparatus

A semiconductor device is provided comprising: a semiconductor element including a plurality of electrodes; first wirings coupled to the electrodes and directed toward a center of the semiconductor element from a portion coupled to the electrodes; second wirings coupled between the first wirings and external terminals, the second wirings being directed to an outer area of the semiconductor element relative to the center; and at least one resin layer formed between the first wirings and the second wirings.

Semiconductor device and fabricating method thereof

A semiconductor device and a fabrication method thereof are provided. An electrically conductive elastic member is formed on a semiconductor die, and a conductive bump is formed on the elastic member. Accordingly, since the conductive bump is formed on the elastic member, or to protrude from a top surface of the elastic member, the height and thus diameter of the conductive bump is reduced allowing a fine pitch to be realized. Further, the elastic member is elastic and thus mitigates external impacts from being transferred from the conductive bump to the semiconductor die.

Semiconductor device and method of manufacturing thereof

The object of the invention disclosed here is the provision of a semiconductor device, which can correspond to a large size chip and be provided with many external terminals with fine wiring with high reliable connection. A semiconductor device (1) comprises a semiconductor element (2) including a plurality of electrodes (9); a single or a plurality of resin layers, a plurality of wirings (4) electrically connected to the electrode (9), and a plurality of external terminals (7) electrically connected to the wirings (4). A part of or all of the plurality of wirings (4) comprises a first wiring (4a) directed to the center (10) of the semiconductor element (2) from a portion coupled to the electrodes (9); and a second wiring (4b) which is directed to an outer area from the center (10) of the semiconductor element (2) and coupled to the external terminals (7). At least one resin layer is formed between the first wiring (4a) and the second wiring (4b).

Stress buffering package for a semiconductor component

The present invention relates to a stress buffering package for a semiconductor component, wherein a stress buffering means comprises individual stress buffering elements that do not influence the stress buffering effect from each other. Furthermore the invention relates a method for manufacturing a stress buffering package for a semiconductor component.

Dielectric cover for a through silicon via

An approach to creating a semiconductor structure for a dielectric layer over a void area includes determining a location of a void area of the topographical semiconductor feature. A second dielectric layer is deposited on a first dielectric layer and a top surface of a topographical semiconductor feature. The second dielectric layer is patterned to one or more portions, wherein at least one portion of the patterned second dielectric layer is over the location of the void area of the topographical semiconductor feature. A first metal layer is deposited over the second dielectric layer, at least one portion of the first dielectric layer, and a portion of the top surface of the topographical semiconductor feature. A chemical mechanical polish of the first metal layer is performed, wherein the chemical mechanical polish reaches the top surface of at least one of the one or more portions of the second dielectric layer.

Semiconductor package

本发明提供一种半导体封装。上述半导体封装包括半导体芯片；第一导电凸块和第二导电凸块，分别设置于上述半导体芯片上，其中上述第一导电凸块和上述第二导电凸块的上视面积比值大于1且小于或等于3。本发明提出的半导体封装因导电凸块的面积不同而提高热传导率并降低电阻性，从而改善半导体封装的热电特性。

Semiconductor package

본 발명의 기술적 사상에 의한 반도체 패키지는, 반도체 기판, 반도체 기판 상에 형성되며 중심부 및 주변부를 포함하고 주변부에 제1 패턴을 갖는 전극 패드, 반도체 기판 및 전극 패드 상에 형성되며, 전극 패드의 중심부를 노출하는 개구부 및 제1 패턴 상에 제2 패턴을 갖는 패시베이션막, 전극 패드 및 패시베이션막 상에 형성되며 제2 패턴 상에 제3 패턴을 갖는 시드층, 및 시드층 상에 형성되며 전극 패드와 전기적으로 연결되는 범프를 포함하고, 범프 하부의 가장자리 아래의 제3 패턴 주위에 언더컷이 형성되어 있는 것을 특징으로 한다.

Power device

Semiconductor device with supporting structure for isolation and passivation layers

Conductions and vias between different, stacked metallic layers of a semiconductor device may be mechanically damaged by mechanical strain. According to an exemplary embodiment of the present invention, this mechanical strain may be transferred through the layer structure to the substrate by a grid of grounding structures and isolation and passivation layers which are connected by the grounding structures. This may provide for an enhancement of the lifetime of the semiconductor devices.

Process for making contact with and housing integrated circuits

본 발명은 기판 물질내에 집적되는 적어도 하나의 소자에 대한 전기적 컨택 접속부를 형성하기 위한 공정을 제안하는 것으로, 상기 기판 물질은 제 1 표면 영역을 가지며, 적어도 하나의 단자 컨택이 각 소자의 상기 제 1 표면 영역에 적어도 부분적으로 배치되며, 상기 단자 컨택은 상기 제 1 표면 영역에 대한 커버링의 도포와 상기 기판 물질에서 상기 제 1 표면 영역에 대해 가로로 진행하는 적어도 하나의 컨택 통로의 형성에 의해 특별히 구별되는데, 상기 공정에서, 제공될 제 2 표면 영역에 적어도 하나의 컨택 위치를 형성하기 위해, 상기 컨택 위치에서 부터 적어도 하나의 단자 컨택까지 적어도 하나의 전기적 컨택 접속부가 상기 각각의 컨택 통로를 통하여 형성된다. 대단히 유리하게, 이러한 방식으로, 컨택 위치가 상기 단자 컨택[sic] 상에 형성될 수 있어, 단자 컨택에 전기적으로 접속되는 컨택 위치는 상기 활성 표면으로부터 멀리 떨어진 상기 기판 물질의 한 면 상에 형성될 수 있으며, 상기 기판 물질을 따라 진행하는 트렌치와 종래의 기술에 따라 소자주위에 이어지는 측방 컨택 둘다를 분배하는 것도 가능하다. The present invention proposes a process for forming electrical contact connections for at least one device integrated within a substrate material, wherein the substrate material has a first surface area, and at least one terminal contact comprises the first of each device. Disposed at least partially in a surface area, the terminal contacts being specifically distinguished by the application of a covering to the first surface area and the formation of at least one contact passage running transversely to the first surface area in the substrate material In the process, at least one electrical contact connection is formed through each contact passage from the contact location to at least one terminal contact to form at least one contact location in the second surface area to be provided. . In a very advantageous way, in this way, a contact position can be formed on the terminal contact [sic] such that a contact position electrically connected to the terminal contact can be formed on one side of the substrate material remote from the active surface. It is also possible to dispense both trenches running along the substrate material and lateral contacts leading around the device according to conventional techniques. 집적회로, 컨택, 하우징, 칩 스택, 센서 칩 Integrated Circuits, Contacts, Housings, Chip Stacks, Sensor Chips

Reduced bottom roughness of stress buffering element of a semiconductor component

The present invention relates to a stress buffering package ( 49 ) for a semiconductor component, with a semiconductor substrate ( 52 ); an I/O pad ( 54 ), electrically connected to the semiconductor substrate ( 52 ); a stress buffering element ( 74 ) for absorbing stresses, electrically connected to the I/O pad ( 54 ); an underbump metallization ( 70 ), electrically connected to the stress buffering element ( 74 ); a solder ball ( 60 ), electrically connected to the underbump metallization ( 70 ); a metal element ( 61 ) between the solder ball ( 60 ) and the semiconductor substrate ( 52 ); a passivation layer ( 56, 58 ), which protects the semiconductor substrate ( 52 ) and the metal element ( 61 ) and which at least partially exposes the I/O pad ( 54 ); characterized in that a roughness of an interface between the stress buffering element ( 74 ) and the passivation layer ( 56, 58 ) is lower than a roughness of an interface between the metal element ( 61 ) and the passivation layer ( 56, 58 ). Furthermore the invention relates a method for manufacturing a stress buffering package ( 49 ) for a semiconductor component.

Interconnect structure for a semiconductor device

A semiconductor device having a device substrate is provided. The semiconductor device includes an electrically-conductive pad formed overlying the device substrate, and an electrically-conductive platform formed overlying the electrically-conductive pad and enclosing a cavity. The electrically-conductive platform has a perimeter portion extending away from the electrically-conductive pad and a capping portion atop the perimeter portion. The semiconductor device also includes a cushioning material disposed in the cavity.

Method for fabricating thermal compliant semiconductor chip wiring structure for chip scale packaging

A new method to form an integrated circuit device is achieved. The method comprises providing a substrate. A sacrificial layer is formed overlying the substrate. The sacrificial layer is patterned to form temporary vertical spacers where conductive bonding locations are planned. A conductive layer is deposited overlying the temporary vertical spacers and the substrate. The conductive layer is patterned to form conductive bonding locations overlying the temporary vertical spacers. The temporary vertical spacers are etched away to create voids underlying the conductive bonding locations.

System and Method for Improving Reliability of Integrated Circuit Packages

An integrated circuit package includes a die, a bump, an underbump metallization layer formed between the bump and the die, a portion of the underbump metallization layer under the bump having a first radius, and a redistribution layer formed between the underbump metallization layer and the die. The redistribution layer has a pad positioned under the underbump metallization layer. The pad has a second radius, and makes contact with the underbump metallization layer. The second radius is less than or equal to the first radius. The integrated circuit package also includes a first dielectric layer disposed between the die and the redistributing layer.

Be electrically connected mat structure and include the integrated circuit of multiple electric connection mat structure

本发明公开一种电性连接垫结构及包含有多个电性连接垫结构的集成电路。其中设置于该集成电路上的电性连接垫结构包含有一连接垫、一绝缘层以及一金凸块，其中该连接垫设置于该集成电路上；该绝缘层设置于该连接垫上方，其中该绝缘层仅具有一开口部，且该开口部的形状包含有至少一条状弯折处；该金凸块设置于该绝缘层上方，其中该金凸块可以通过该绝缘层的该开口部与该连接垫电连接。

Semiconductor device and manufacturing method thereof

A stacked MCM is manufactured at reduced cost without using expensive apparatus. A first wiring and a second wiring are formed on a surface of a semiconductor chip of a first semiconductor device through an insulation film. A glass substrate having an opening to expose the second wiring is bonded to the surface of the semiconductor chip on which the first wiring and the second wiring are formed. A third wiring is disposed on a back surface and a side surface of the semiconductor chip through an insulation film and connected to the first wiring. And a conductive terminal of another semiconductor device is connected to the second wiring through the opening.

Semiconductor device and fabrication process thereof

반도체 장치는, 복수의 배선이 형성된 도체층과, 도체층의 복수의 배선과 겹치는 영역에 형성된 본딩 패드를 구비한다. 배선의 일부가 본딩 패드와 접합되는 한편, 배선의 다른 부분과 본딩 패드 사이에 절연성 보호막이 형성된다. 적어도 본딩 패드와 겹치는 영역 내의 상기 배선 상의 보호막은, 인접하는 배선 상의 보호막과 교가된다. 이에 의해 배선 상의 보호막이 브릿지 형상이 되므로, 보호막의 하부에 크랙이 발생되기 어려워진다. 또한, 교가되는 부분의 아래에 형성되는 공공부가 공기 스프링으로서 기능하기 때문에, 보호막의 아래에 형성되는 배선 등의 구성요소가 손상되는 것을 방지할 수 있다. 또한, 충격완충재로서의 폴리이미드막이 필요없어지기 때문에, 작업효율의 저하나 칩 비용의 상승을 방지할 수 있다. A semiconductor device is provided with the conductor layer in which the some wiring was formed, and the bonding pad formed in the area | region which overlaps with the some wiring of the conductor layer. A portion of the wiring is bonded to the bonding pad, while an insulating protective film is formed between the other portion of the wiring and the bonding pad. The protective film on the wiring at least in the region overlapping the bonding pads alternates with the protective film on the adjacent wiring. As a result, the protective film on the wiring becomes a bridge shape, so that cracks are less likely to occur in the lower portion of the protective film. In addition, since the cavities formed below the intersecting portions function as air springs, it is possible to prevent components such as wirings formed under the protective film from being damaged. Moreover, since the polyimide membrane as an impact buffer material is not needed, the fall of work efficiency and the raise of a chip cost can be prevented. 반도체 장치 Semiconductor devices