Dreidimensionale integrierte Schaltungsstruktur und Verfahren zu deren Herstellung

Es wird eine dreidimensionale integrierte Schaltungsstruktur bereitgestellt, die ein erstes Dia, eine Trägerschichtdurchkontaktierung und ein Verbindungselement enthält. Das erste Die ist an ein zweites Die mit einer ersten dielektrischen Schicht des ersten Dies und einer zweiten dielektrischen Schicht des zweiten Dies gebunden, wobei eine erste Passivierungsschicht zwischen der ersten dielektrischen Schicht und einer ersten Trägerschicht des ersten Dies liegt und ein erstes Testpad in der ersten Passivierungsschicht eingebettet ist. Die Trägerschichtdurchkontaktierung durchdringt das erste Die und ist elektrisch mit dem zweiten Die verbunden. Das Verbindungselement ist elektrisch mit dem ersten Die und dem zweiten Die durch die Trägerschichtdurchkontaktierung verbunden.

PROCEDURE FOR SOLDERING ELECTRONIC ELEMENTS WITH SOLDERING PEAKS ON A SUBSTRATE

SOLDERING PEAK MANUFACTURING PROCESS AND STRUCTURES WITH A TITANIUM BARRIER LAYER

Superconducting bump bonds

A device (100) includes a first chip (104) having a first circuit element (112), a first interconnect pad (116) in electrical contact (118) with the first circuit element, and a barrier layer (120) on the first interconnect pad, a superconducting bump bond (106) on the barrier layer, and a second chip (102) joined to the first chip by the superconducting bump bond, the second chip having a quantum circuit element (108), in which the superconducting bump bond provides an electrical connection between the first circuit element and the quantum circuit element.

SUPERCONDUCTING BUMP BONDS

A device (100) includes a first chip (104) having a first circuit element (112), a first interconnect pad (116) in electrical contact (118) with the first circuit element, and a barrier layer (120) on the first interconnect pad, a superconducting bump bond (106) on the barrier layer, and a second chip (102) joined to the first chip by the superconducting bump bond, the second chip having a quantum circuit element (108), in which the superconducting bump bond provides an electrical connection between the first circuit element and the quantum circuit element.

TRANSFER METHOD PROVIDING THERMAL EXPANSION MATCHED DEVICES

A method of transferring an integrated circuit (IC) onto an alternative substrate is provided at a wafer level to enable coefficient of thermal expansion (CTE) matching for a circuit layer to a different material. The method is executable relative to a wafer (11) with a circuit layer (12), a first major surface (121), a second major surface (122) opposite the first major surface, and a substrate (13) affixed to the first major surface. The method includes temporarily bonding a handle (14) to the second major surface, removing a majority of the substrate to expose the first major surface and bonding a second substrate (16) to the first major surface with deposited bonding material (15).

Integrated circuit structure

An integrated circuit structure includes a first work piece and a second work piece. The first work piece includes a semiconductor substrate, and a copper bump over the semiconductor substrate. The second work piece includes a bond pad. A solder is between and adjoining the first work piece and the second work piece, wherein the solder electrically connects the copper bump to the bond pad. The solder includes palladium. The invention improves the reliability of solder obviously.

For flip chip package structure

DEVICE OF CONNECTION AND PROCESS OF CONNECTION

ELECTRONICS COMPONENT HAS CONNECTIONS BY BALLS DECOUPLEES MECHANICALLY.

Composant électronique comportant au moins une puce et/ou un support, la puce étant destinée à être reportée sur le support et reliée, au niveau d'au moins un emplacement de connexion (102) de la puce formé par au moins une portion (108) d'une couche (104) de la puce, à au moins un emplacement de connexion du support formé par au moins une portion d'une couche du support, par au moins une bille, la puce et/ou le support comprenant des moyens de découplage mécanique de l'emplacement de connexion (102) de la puce et/ou du support par rapport à la puce et/ou au support, formés par au moins une cavité (110) réalisée dans la couche de la puce et/ou du support, sous l'emplacement de connexion de la puce et/ou du support, et au moins une tranchée (114), réalisée dans la couche de la puce et/ou du support, communiquant avec ladite cavité.

Method for assembling e.g. two components in face to face manner, involves depositing volume of welding material on surface, where welding material comprises melting point, which is higher than that of another welding material

Un procédé d'assemblage face contre face d'un premier et d'un deuxième composants (34, 42), consiste : ▪ à réaliser entre les composants : o des colonnes (30, 38, 46) ayant un volume (38) de premier matériau de soudure; o des calles (36, 40) de hauteur inférieure à celle colonnes (30, 38, 46), et ayant une température de fusion supérieure à celle des colonnes ; et ▪ à appliquer un premier chauffage aux colonnes (30, 38, 46) à une température supérieure à la température de fusion des colonnes de soudure et inférieure à la température de fusion des calles (36, 40), La réalisation d'une calle (36, 40) consiste à : ▪ à réaliser une surface mouillable (36) sur le premier ou le deuxième composant (34); ▪ à déposer un volume (40) de deuxième matériau de soudure sur la surface mouillable (36), de température de fusion supérieure à celle des colonnes ; et ▪ à appliquer un deuxième chauffage au volume (40) de deuxième matériau à une température supérieure à la température de fusion du deuxième matériau ...

Integrated circuit device having through-silicon via structure and method of manufacturing the same

마주보는（ＦＡＣＥ­ＴＯ­ＦＡＣＥ, Ｆ2Ｆ） 하이브리드 구조를 갖는 집적 회로(ＩＣ), ＩＣ 조립체, ＩＣ 제품 및 이들을 제조하는 방법, 그리고 이를 위한 컴퓨터-판독가능 매체

... 재분배 층(RDL)을 포함하는 집적 회로(IC) 제품이 제공되며, 재분배 층(RDL)은 IC 내에서 전기적 정보를 하나의 위치로부터 또 하나의 위치로 분배하도록 구성된 적어도 하나의 전도성 층을 갖는다. RDL은 또한 복수의 와이어 본드 패드들 및 복수의 솔더 패드들을 포함한다. 복수의 솔더 패드들 각각은 RDL과 직접적으로 전기적 통신을 하는 솔더 가용성 물질을 포함한다.

PROCESS FOR PRODUCTION OF ELECTRONIC DEVICE, ELECTRONIC DEVICE, AND DEVICE FOR PRODUCTION OF ELECTRONIC DEVICE

FLIP CHIP MOUNTING METHOD AND BUMP FORMING METHOD

A solder resin composition (6) including a solder powder (5a) and a resin (4) is placed on a first electronic component (2), and a connecting terminal (3) of the first electronic component (2) and an electrode terminal (7) of a second electronic component (8) are arranged to face each other. The first electronic component (2) and the solder resin composition are heated to have a gas spouted from a gas generating source (1) included in the first electronic component (2), and the gas (9a) is permitted to flow in a convective manner in the solder resin composition (6). Thus, the solder powder (5a) is flowed in the solder resin composition (6), self-collected on the connecting terminal (3) and the electrode terminal (7), and the connecting terminal (3) and the electrode terminal (7) are electrically connected. The flip chip mounting method by which the electrode terminal of the semiconductor chip wired at a narrow pitch and the connecting terminal of the circuit board can be connected with ...

Preparation method of semiconductor device, and semiconductor device

Package carrier and bonding structure

A package carrier including a substrate, at least a under bump metallurgic (UBM) layer and at least a conductive bump is provided. The substrate has a conductive structure and at least a pad connected with the conductive structure, wherein the region of the pad connected with the conductive structure is a signal source region. The UBM layer is disposed on the pad. The UBM layer includes a first conductive pattern and a second conductive pattern. The side wall of the second conductive pattern is directly connected to the side wall of the first conductive pattern, and the second pattern is disposed near the signal source region, wherein the conductivity of the second conductive pattern is smaller than the conductivity of the first conductive pattern. The conductive bump is disposed on the UBM layer.

Semiconductor device and method of forming pad layout for flipchip semiconductor die

A semiconductor device has a semiconductor die with a die pad layout. Signal pads in the die pad layout are located primarily near a perimeter of the semiconductor die, and power pads and ground pads are located primarily inboard from the signal pads. The signal pads are arranged in a peripheral row or in a peripheral array generally parallel to an edge of the semiconductor die. Bumps are formed over the signal pads, power pads, and ground pads. The bumps can have a fusible portion and non-fusible portion. Conductive traces with interconnect sites are formed over a substrate. The bumps are wider than the interconnect sites. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surfaces of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate.

Thin NiB or CoB capping layer for non-noble metallic bonding landing pads

The invention relates to a substrate having at least one main surface comprising at least one non-noble metallic bonding landing pad covered by a capping layer thereby shielding the non-noble metallic bonding landing pad from the environment. This capping layer comprises an alloy, the alloy being NiB or CoB and containing an atomic concentration percentage of boron in the range of 10% to 50%.

Method for forming the package structure

A method for forming the package structure is provided. The method includes forming a die structure over a first surface of a first substrate, and forming a plurality of electrical connectors below a second surface of the first substrate. The method also includes forming a first protruding structure below the second surface of the first substrate, and the electrical connectors are surrounded by the first protruding structure. The method further includes forming a second protruding structure over a second substrate, and bonding the first substrate to the second substrate. The electrical connectors are surrounded by the second protruding structure, and the first protruding structure does not overlap with the second protruding structure.

Filter structures and methods of forming same and method of filtering signal

SEMICONDUCTOR DEVICE PACKAGE AND MANUFACTURING METHOD THEREOF

Semiconductor device and method of depositing encapsulant along sides and surface edge of semiconductor die in embedded wlcsp

SEMICONDUCTOR DEVICE AND METHOD OF FORMING ATHIN WAFER WITHOUT A CARRIER

Abstract SEMICONDUCTOR DEVICE AND METHOD OFFORMING A THIN WAFER WITHOUT A CARRIERA semiconductor device has a conductive via in a first surface of a substrate. A first interconnect structure is formed over the first surface of the substrate. A first bump is formed over the first interconnect structure. The first bump is formed over or offset from the conductive via. An encapsulant is deposited over the first bump and first interconnect structure. A portion of the encapsulant is removed to expose the first bump. A portion of a second surface of the substrate is removed to expose theconductive via. The encapsulant provides structural support and eliminates the need for a separate carrier wafer when thinning the substrate. A second interconnect structure is formed over the second surface of the substrate. A second bump is formed over the first bump. A plurality of semiconductor devices can be stacked and electrically connected through the conductive via.(Figure 5) ...

Semiconductor device and method of fabricating the same

A semiconductor device includes a semiconductor substrate and an array of protruding electrodes arranged at a pitch X1. Each of the protruding electrodes has a height X3 and is formed on a barrier metal base of diameter X2 coupled to an electrode arranged on the semiconductor substrate so as to satisfy the relations (X1/2) <= X2 <= (3*X1/4) and (X1/2) <= X3 <= (3*X1/4).

Semiconductor device and method of forming an embedded sop fan-out package

IC chip with improved pillar bumps

An IC chip with improved pillar bumps is disclosed. The chip has a plurality of bond pads on its active surface. A plurality of under bump metallurgy pads (UBM pad) are boned on the bond pads for connecting pillar bumps. A high wettability solder layer is formed between the pillar bumps and the UBM pads so as to melt and wet bottom surface of the pillar bumps through reflowing for improving bonding strength of the pillar bumps.

Semiconductor device with low cte substrates

METHODS AND SYSTEM FOR ATTACHING SUBSTRATES USING SOLDER STRUCTURES

A first substrate is attached to a second substrate by providing solder structures that include a first portion adjacent the second substrate that has a first melting point, and a second portion adjacent the first substrate that has a second melting point that is lower than the first melting point. The solder structures then are heated to a first temperature that is at or above the second melting point but below the first melting point, to melt the second portions. Simultaneous with the heating of the solder structures to the first temperature, the first substrate is attached to the second substrate while the second portions are melted. Finally, the solder structures are heated to a second temperature that is above the first temperature, to alloy at least some of the first portions and the second portions. Accordingly, low temperature joining and/or positioning of the first substrate relative to the second substrate may be performed, followed by conversion of at least part of the solder ...

Laminated solder column

A method for forming solder balls and an apparatus and method for forming solder columns on the electrical contact pads of an electronic package in order to establish a more reliable electrical and mechanical connection between an electronic package and a printed circuit board. In one embodiment, solder balls are formed on the electrical contact pads of a package by placing solder cylinders over the electrical contact pads and then passing the package through a reflow furnace where the solder cylinders take the form of spheres and are wetted onto the pads. In a second embodiment, a laminated solder column is formed that is resistant to collapse during the manufacturing process. The laminated solder column comprises a solder cylinder being clad on its top and bottom surfaces with a solder material having a lower melting temperature than that of the center solder cylinder. When attaching the solder column to a package or a printed circuit board reflow temperatures are maintained above the ...

Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect

A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.

3D packaging with low-force thermocompression bonding of oxidizable materials

Methods and systems for low-force, low-temperature thermocompression bonding. The present application teaches new methods and structures for three-dimensional integrated circuits, in which cold thermocompression bonding is used to provide reliable bonding. To achieve this, reduction and passivation steps are preferably both used to reduce native oxide on the contact metals and to prevent reformation of native oxide, preferably using atmospheric plasma treatments. Preferably the physical compression height of the elements is set to be only enough to reliably achieve at least some compression of each bonding element pair, compensating for any lack of flatness. Preferably the thermocompression bonding is performed well below the melting point. This not only avoids the deformation of lower levels which is induced by reflow techniques, but also provides a steep relation of force versus z-axis travel, so that a drastically-increasing resistance to compression helps to regulate the degree of thermocompression ...

Semiconductor package with improved redistribution layer design and fabricating method thereof

A semiconductor package with improved redistribution layer design and fabricating method thereof are disclosed and may include a semiconductor die comprising bond pads, a first redistribution layer (RDL) formed on the semiconductor die. The first RDL has a first end coupled to a bond pad and a second end coupled to a solder bump via under bump metal layers. A second RDL is formed in a same plane of the semiconductor die as the first RDL and is electrically isolated from the first RDL. A first end of the second RDL may be coupled to a bond pad and the second RDL may pass underneath, but be electrically isolated from, the solder bump. A passivation layer may be formed on the first and second RDLs exposing the second end of the first RDL. The under bump metal layers may be formed on the second end of the first RDL exposed by the passivation layer.

Method of forming a temporary test structure for device fabrication

A method of forming a temporary test structure for device fabrication is provided. The method is particularly useful for electrically testing conductive interconnects during controlled collapse chip connections (C4) fabrication and/or through-silicon vias (TSVs) during interposer fabrication. The method includes providing a substrate containing a plurality of electrically conductive interconnects extending vertically to top surface of the substrate. A temporary test structure is formed to connect the plurality of interconnects and for electrical testing. The suitable material for the temporary test structure is TiW for a single layer structure, or Cu or Cu alloy over Ti or TiW for a bilayer structure with thickness in a range of about 20 nm to 1200 nm. Excimer laser ablation can be used to form the temporary test structure. Electrical testing is performed on the substrate by probing at different test locations on the temporary test structure. All or part of the temporary test structure ...

INTERCONNECT LAYER CONTACT AND METHOD FOR IMPROVED PACKAGED INTEGRATED CIRCUIT RELIABILITY

Packaged photosensor ICs are made by fabricating an integrated circuit (IC) with multiple bondpads; forming vias from IC backside through semiconductor to expose a first layer metal; depositing conductive metal plugs in the vias; depositing interconnect metal; depositing solder-mask dielectric over the interconnect metal and openings therethrough; forming solder bumps on interconnect metal at the openings in the solder-mask dielectric; and bonding the solder bumps to conductors of a package. The photosensor IC has a substrate; multiple metal layers separated by dielectric layers formed on a first surface of the substrate into which transistors are formed; multiple bondpad structures formed of at least a first metal layer of the metal layers; vias with metal plugs formed through a dielectric over a second surface of the semiconductor substrate, interconnect metal on the dielectric forming connection shapes, and shapes of the interconnect layer coupled to each conductive plug and to solder ...

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device includes a wiring substrate including wiring layers, a semiconductor chip including electrode pads and mounted on the wiring substrate, and a first capacitor including a first electrode and a second electrode, and mounted on the wiring substrate. The wiring layers include a first wiring layer including a first terminal pad electrically connected with the first electrode of the first capacitor and a second terminal pad electrically connected with the second electrode of the first capacitor; and a second wiring layer on an inner side by one layer from the first wiring layer of the wiring substrate and including a first conductor pattern having a larger area than each of the first terminal pad and the second terminal pad. The first conductor pattern includes a first opening in a region overlapping with each of the first terminal pad and the second terminal pad in the second wiring layer.

Semiconductor device comprising a chip substrate, a mold, and a buffer layer

A semiconductor device and a method of manufacturing the semiconductor device are disclosed. The semiconductor device includes a chip substrate, a mold, and a buffer layer. The mold is disposed over the chip substrate. The buffer layer is externally embedded between the chip substrate and the mold. The buffer layer has an elastic modulus or a coefficient of thermal expansion less than that of the mold. The method includes disposing a buffer layer at least covering scribe lines of a substrate, forming a mold over the substrate and covering the buffer layer, and cutting along the scribe lines and through the mold, the buffer layer and the substrate.

ADHESIVE FOR SEMICONDUCTOR, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SAID DEVICE

Disclosed is a method for manufacturing a semiconductor device which includes: a semiconductor chip; a substrate and/or another semiconductor chip; and an adhesive layer interposed therebetween. This method comprises the steps of: heating and pressuring a laminate having: the semiconductor chip; the substrate; the another semiconductor chip or a semiconductor wafer; and the adhesive layer by interposing the laminate with pressing members for temporary press-bonding to thereby temporarily press-bond the substrate and the another semiconductor chip or the semiconductor wafer to the semiconductor chip; and heating and pressuring the laminate by interposing the laminate with pressing members for main press-bonding, which are separately prepared from the pressing members for temporary press-bonding, to thereby electrically connect a connection portion of the semiconductor chip and a connection portion of the substrate or the another semiconductor chip.

Semiconductor device and manufacturing method thereof

A semiconductor device and manufacturing method thereof improving moisture resistance of a FeRAM. After a probe test using a pad, a metal film is formed to cover the pad in an opening of a protective film and a region from the pad to an opening outer periphery of the protective film. On the metal film, a metal bump is formed. The metal film is formed to have a two-layer structure of the first and second metal films. Materials of the lower and upper layers are selected mainly in consideration of adhesion to the protective film and adhesion to the metal bump, respectively. Film formation conditions thereof are set to provide metal films with a desired quality and thickness. Thus, penetration of moisture from the pad or the periphery into a ferroelectric capacitor can be prevented and therefore, occurrence of potential inversion abnormalities due to penetrated moisture can be effectively suppressed.

Interconnect structure comprising fine pitch backside metal redistribution lines combined with vias

A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through-silicon vias (TSVs) and using a “plate through resist” type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and polish stop layer during the process flow.

Substrate Stand-Offs for Semiconductor Devices

Substrate stand-offs for use with semiconductor devices are provided. Active pillars and dummy pillars are formed on a first substrate such that the dummy pillars may have a height greater than a height of the active pillars. The dummy pillars act as stand-offs when joining the first substrate to a second substrate, thereby creating greater uniformity. In an embodiment, the dummy pillars may be formed simultaneously as the active pillars by forming a patterned mask having openings with a smaller width for the dummy pillars than for the active pillars. When an electro-plating process of the like is used to form the dummy and active pillars, the smaller width of the dummy pillar openings in the patterned mask causes the dummy pillars to have a greater height than the active pillars.

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure includes a first substrate; a second substrate, disposed over the first substrate; a die, disposed over the second substrate; a via, extending through the second substrate and electrically connecting to the die; a redistribution layer (RDL) disposed between the first substrate and the second substrate, including a dielectric layer, a first conductive structure electrically connecting to the via, and a second conductive structure surrounding the first conductive structure, wherein the second conductive structure extends along an edge of the dielectric layer and penetrates through the dielectric layer; and a first underfill material, disposed between the first substrate and the RDL, wherein one end of the second conductive structure exposed through the dielectric layer is entirely in contact with the first underfill material.

Semiconductor device having wire studs as vertical interconnect in FO-WLP

A semiconductor device has a substrate and semiconductor die disposed over a first surface of the substrate. A wire stud is attached to the first surface of the substrate. The wire stud includes a base portion and stem portion. A bonding pad is formed over a second surface of the substrate. An encapsulant is deposited over the substrate, semiconductor die, and wire stud. A portion of the encapsulant is removed by LDA to expose the wire stud. A portion of the encapsulant is removed by LDA to expose the substrate. An interconnect structure is formed over the encapsulant and electrically connected to the wire stud and semiconductor die. A bump is formed over the interconnect structure. A semiconductor package is disposed over the encapsulant and electrically connected to the substrate. A discrete semiconductor device is disposed over the encapsulant and electrically connected to the substrate.

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a heat dissipation plate including a first region and a second region, a first element disposed on the heat dissipation plate in the first region, and a second element disposed on the heat dissipation plate in the second region. The first element includes a first substrate, the second element includes a second substrate, the first substrate includes a material different from a material of the second substrate, the first substrate contacts the heat dissipation plate, and the second element is bonded to the heat dissipation plate in a flip-chip bonding manner.

Method for fabricating a chip scale package using wafer level processing

Channels are formed that pass through an active surface of a semiconductor substrate to provide isolation between adjacent active surface regions defining individual die locations. Bond pads on the substrate are bumped with intermediate conductive elements, after which a material used to encapsulate the active surface is applied, filling the channels and covering exposed peripheral edges of the active surface integrated circuitry. The encapsulant is then planarized to expose the ends of the bumps. External conductive elements such as solder balls are then formed on the exposed bump ends. The semiconductor wafer is diced in alignment with the channels to singulate the semiconductor devices, the encapsulant in the channels keeping the edges of the integrated circuitry substantially hermetically sealed.

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

A semiconductor package includes a support member having a concave portion formed in one surface thereof. A semiconductor chip is accommodated in the concave portion so that a circuit formation surface of the semiconductor chip is exposed on a side of the one surface of the support member. A wiring structure including a wiring layer electrically connected to the semiconductor chip is formed on the circuit formation surface of the semiconductor chip and the one surface of the support member. A portion of the support member including the one surface is made of silicon or borosilicate glass.

Semiconductor device and method comprising redistribution layers

A method of making a semiconductor package can include forming a plurality of redistribution layer (RDL) traces disposed over active surfaces of a plurality of semiconductor die and electrically connected to contact pads on the plurality of semiconductor die. The method can include disposing an encapsulant material over the active surfaces, contacting at least four side surfaces of each of the plurality of semiconductor die, and disposed over the plurality of RDL traces. The method can also include forming a via through the encapsulant material to expose at least one of the plurality of RDL traces, forming an electrical interconnect disposed within the via and coupled to the at least one RDL trace, and singulating the plurality of semiconductor packages through the encapsulant material to leave an offset of 30-140 μm of the encapsulant material disposed around a periphery of each of the plurality of semiconductor die.

Packaging Process Tools and Packaging Methods for Semiconductor Devices

Packaging process tools and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging process tool for semiconductor devices includes a mechanical structure including a frame. The frame includes a plurality of apertures adapted to retain a plurality of integrated circuit dies therein. The frame includes at least one hollow region.

SEMICONDUCTOR PACKAGE

A semiconductor package includes a first semiconductor chip having a first chip substrate, the first chip substrate having a first upper surface and a first lower surface opposite to each other, a first through-silicon via (TSV), a lower connection pad and a first lower passivation layer on the first lower surface of the first chip substrate, the first lower passivation layer exposing a portion of the lower connection pad, an upper connection pad and a first upper passivation layer on the first upper surface of the first chip substrate, the first upper passivation layer including a first upper inorganic material layer, and a second semiconductor chip connected to the first semiconductor chip, the second semiconductor chip including a second TSV, wherein the first lower passivation layer has a stacked structure of a first lower inorganic material layer and a lower organic material layer.

Semiconductor Package

A semiconductor device is disclosed. The semiconductor device comprises a first die, a second die, and a redistribution structure. The first die and the second die are electrically connected to the redistribution structure. There are no solder bumps between the first die and the redistribution structure. There are no solder bumps between the second die and the redistribution structure. The first die and the second die have a shift with regard to each other from a top view.

SEMICONDUCTOR PACKAGING AND MANUFACTURING METHOD THEREOF

The present disclosure provides a semiconductor package includes a contact pad, a device external to the contact pad and a solder bump on the contact pad. The device has a conductive contact pad corresponding to the contact pad. The solder bump connects the contact pad with the conductive contact pad. The solder bump comprises a height from a top of the solder bump to the contact pad; and a width which is a widest dimension of the solder bump in a direction perpendicular to the height. A junction portion of the solder bump in proximity to the contact pad comprises an hourglass shape.

Wiring substrate

A wiring substrate includes a substrate body, a first wiring, and a second wiring. The first wiring and the second wiring are located on an upper surface of the substrate body. The wiring substrate further includes a solder resist layer that covers the first wiring and the second wiring. The solder resist layer includes a first opening that partially exposes the second wiring and a missing portion that partially exposes the first wiring. The wiring substrate further includes an insulation coating that covers an inner wall of the missing portion, the first wiring exposed by the missing portion, and at least a portion of an upper surface of the solder resist layer. The insulation coating includes a second opening that is in communication with the first opening and partially exposes the second wiring.

FLIP CHIP PACKAGED DEVICES WITH THERMAL PAD

In a described example, an apparatus includes: a first package substrate having a die mount surface; a semiconductor die flip chip mounted to the first package substrate on the die mount surface, the semiconductor die having post connects having proximate ends on bond pads on an active surface of the semiconductor die, and extending to distal ends away from the semiconductor die having solder bumps, wherein the solder bumps form solder joints to the package substrate; a second package substrate having a thermal pad positioned with the thermal pad over a backside surface of the semiconductor die, the thermal pad comprising a thermally conductive material; and a mold compound covering a portion of the first package substrate, a portion of the second package substrate, the semiconductor die, and the post connects, thermal pad having a surface exposed from the mold compound.

SEMICONDUCTOR PACKAGE

A semiconductor package includes a first package substrate, a first semiconductor chip provided on the first package substrate, an interposer provided on the first semiconductor chip, and a vertical conductive structure provided on the first package substrate and a side surface of the first semiconductor chip, and connecting the first package substrate and the interposer, the interposer includes a first recess vertically overlapping the first semiconductor chip in a lower portion of the interposer, and a lower surface of the interposer defining the first recess is higher than an upper surface of the vertical conductive structure.

Halbleitervorrichtung mit Nachpassivierung-Zwischenverbindungsstruktur und Verfahren zu ihrer Bildung

Halbleitervorrichtung mit Nachpassivierungs-Zwischenverbindungsstruktur, umfassend: – eine auf einem Halbleitersubstrat (10) ausgebildete Schaltungsanordnung (12) mit elektrische Vorrichtungen überlagernden dielektrischen Schichten und dazwischenliegend ausgebildeten Metallschichten; – eine dielektrische Zwischenschicht (14) aufgetragen durch plasmaunterstützte chemische Gasphasenabscheidung mit mehreren dielektrischen Schichten und darin ausgebildeten Kontakten zum Kontaktieren der Schaltungsanordnung (12); – mehrere dielektrische Zwischenmetallschichten (16) aufgetragen durch chemische Gasphasenabscheidung mit hochdichtem Plasma mit zugeordneten Metallisierungsschichten, die der dielektrischen Zwischenschicht (14) überlagert sind, wobei die Metallisierungsschichten mittels Ätzprozess unter Verwendung von Ätzstoppschichten aufgetragen durch plasmaunterstützte chemische Gasphasenabscheidung Metallleitungen (18) und Durchkontakte (19) zum Zusammenschalten der Schaltungsanordnung (12) schaffen ...

Forming raised bumps on substrate pad using bonding tool

Process for forming a raised bump (contact metallising) on a pad (connecting face) of a substrate using a wire bonding device with a bonding tool, in which a wire end guided out of a mouthpiece is connected to the pad using the bonding tool and then the wire end connected to the pad is sepd. from excess contact material wire, is novel through the following steps: (a) joining the free end of the wire end (29) and the pad (11) to form a first joint area (21); (b) joining a continuous end of the wire end (29) connected to the excess contact material (13) and the pad (11) or a part of the wire end (29) already connected to the pad (11) with one end to form a second joint area (22) such that a defined wire region (19) is formed between the first (21) and second (22) joint areas, and the joint areas (21, 22) together with the wire region (19) form a contact material volume (25); and (c) melting of the contact material volume (25) formed on the pad (11) to form the raised bump. Also claimed is ...

Selektive Ätzung von TiW für C4-Herstellung

Supercomputer using wafer scale integration

SEMICONDUCTOR DEVICE WITH BUILT-UP LOW RESISTANCE CONTACT

Lead frame, semiconductor device, and method for manufacturing lead frame

The present invention provides a lead frame which can reduce oxidization of the lead frame, a semiconductor device and a method for manufacturing the lead frame. The lead frame includes a plurality of leads defined by an opening extending in a thickness direction, and an insulating resin layer which fills the opening to entirely cover side surfaces of each lead and to support the leads. A first surface of each lead is exposed from a first surface of the insulating resin layer.

Integrated circuit element and packaging component

The invention provides an integrated circuit element and a packaging component. The integrated circuit element comprises a semiconductor substrate, a conductive column which is disposed on the semiconductor substrate and has a side wall surface and an upper surface, a boss lower metal layer which is disposed between the semiconductor substrate and the conductive column and has a surface area which is adjacently connected to the side wall surface of the conductive column and extends from the side wall surface, and a protection structure which is disposed on the side wall surface of a copper column and on the surface area of the boss lower metal layer. The protection structure is made of metal materials and the conductive column is composed by copper layers. The side wall protection structure covers at least a part of the side wall surface of the boss structure, and the protection structures disposed on the copper column side wall and on the surface area of the boss lower metal layer are ...

Method for eliminating aluminum terminal pad material in semiconductor devices

A method for far back end of line (FBEOL) semiconductor device formation includes forming a terminal copper pad in an upper level of a semiconductor wafer, forming an insulating stack over the terminal copper pad, and patterning and opening a terminal via within a portion of the insulating stack so as to leave a bottom cap layer of the insulating stack protecting the terminal copper pad. An organic passivation layer is formed and patterned over the top of the insulating stack, and the bottom cap layer over the terminal copper pad is removed. A ball limiting metallurgy (BLM) stack is depositedover the organic passivation layer and terminal copper pad, and a solder ball connection is formed on a patterned portion of the BLM stack.

Assembly with bumps wafer-level chip size packaging device

MANUFACTORING PROCESS OF TWO SUBSTRATES CONNECT BY AT LEAST A MECHANICAL CONNECTION AND ELECTRICALLY CONDUCTING OBTAINED

A METHOD OF JOINING TWO ELECTRONIC COMPONENT, FLIP-CHIP TYPE, OBTAINED BY THE ASSEMBLY METHOD.

L'invention concerne un procédé d'assemblage de deux composants électroniques l'un à l'autre, lesdits composants comportant chacun une face d'assemblage, selon lequel on rapproche les deux faces d'assemblage l'une de l'autre selon une direction X dite d'assemblage et on applique une force donnée F à l'un et/ou l'autre des composants, l'une et/ou l'autre face(s) d'assemblage comportant: - des inserts de connexion en matériau rigide présentant une forme longitudinale allongée selon la direction X d'assemblage; - des pistes de connexion en matériau de dureté inférieure à celle des inserts et de forme longitudinale allongée transversalement à la direction X d'assemblage. procédé selon lequel: - on aligne les inserts en regard des pistes correspondantes de manière à ce que les inserts et les pistes forment deux à deux, après assemblage, au moins une intersection sensiblement transversale, - on applique la force F pour faire pénétrer les inserts dans les pistes jusqu'à obtenir l'assemblage.

INTERCONNECT STRUCTURE COMPRISING FINE PITCH BACKSIDE METAL REDISTRIBUTION LINES COMBINED WITH VIAS

접착제 조성물, 반도체 장치의 제조 방법 및 반도체 장치

... 본 발명은, 반도체칩 및 배선 회로 기판의 각각의 접속부가 서로 전기적으로 접속된 반도체 장치 또는 복수의 반도체칩의 각각의 접속부가 서로 전기적으로 접속된 반도체 장치에서 접속부를 밀봉하는 접착제 조성물로서, 에폭시 수지와, 경화제와, 아크릴계 표면 처리 충전재를 함유하는 접착제 조성물에 관한 것이다.

A COMMON BALL-LIMITING METALLURGY FOR I/O SITES

앵커 인터커넥트

... 실시예는, 하부 및 상부 금속 층들 사이의 복수의 금속 층들을 포함하는 백엔드 부분 - 상부 금속 층은 제1 및 제2의 대향하는 측벽 표면들 및 측벽 표면들을 서로 결합하는 상부 표면을 갖는 상부 금속 층 부분을 포함함 -; 상부 표면에 직접적으로 접촉하는 절연체 층; 및 상부 금속 층 부분에 접촉 범프를 결합하는 비아를 포함하며; 백엔드 부분에 결합되는 기판에 직교하는 제1 수직 축이 접촉 범프, 질화물 층, 비아, 및 상부 금속 층 부분을 가로지르는 반도체 구조체를 포함한다. 다른 실시예들이 본 명세서에 설명된다.

Semiconductor device comprising TSV(Through Silicon Via), and semiconductor package comprising the same

SEMICONDUCTOR DEVICE INSTALLED ON MAIN CIRCUIT BOARD AND PRODUCING METHOD THEREOF

PURPOSE: A semiconductor device installed on a main circuit board is provided to substitute an insulating layer, a rewiring circuit, and an insulating film for an auxiliary circuit board for minimizing the size of the semiconductor device and for reducing production cost. CONSTITUTION: An activated surface of a semiconductor chip(10) is covered by an insulating layer(100). And a rewiring circuit(120) is formed on the insulating layer. Herein, a hole is formed in the insulating film for locating the electrode of the semiconductor chip to connect the rewiring circuit with the electrode of the semiconductor chip. Also, an insulating film(160) is bonded on the surface of the insulating layer around the rewiring circuit continuously. Therefore, an inner bump(140) formed on a conductive pad(122) is inserted to a hole(180) arranged in the insulating film. Also, an outer bump(200) is formed in the location corresponding to the hole of the insulating film for the upper part of the outer bump projected ...

Board for electronic component package, electronic component package, and method of manufacturing board for electronic component package

Semiconductor device and manufacturing method thereof

A semiconductor device includes a substrate including a surface, a plurality of pads disposing on the surface of the substrate, the plurality of pads includes a non-solder mask defined (NSMD) pad and a solder mask defined (SMD) pad, and the NSMD pad is arranged at a predetermined location. Further, a method of manufacturing a semiconductor device includes providing a substrate, disposing a plurality of pads on a surface of the substrate, disposing a solder mask over the surface of the substrate and the plurality of pads, forming a first recess in the solder mask to surround one of the plurality of pads, and forming a second recess in the solder mask and above one of the plurality of pads.

Semiconductor structure and manufacturing method thereof

A semiconductor structure includes a substrate, a conductive interconnection exposed from the substrate, a passivation covering the substrate and a portion of the conductive interconnection, an under bump metallurgy (UBM) pad disposed over the passivation and contacted with an exposed portion of the conductive interconnection, and a conductor disposed over the UBM pad, wherein the conductor includes a top surface, a first sloped outer surface extended from the top surface and including a first gradient, and a second sloped outer surface extended from an end of the first sloped outer surface to the UBM pad and including a second gradient substantially smaller than the first gradient.

Surface mounting semiconductor component, chip scale semiconductor package assembly, and surface mounting method

A surface mounting semiconductor component includes a semiconductor device, a circuit board, a number of first solder bumps, and a number of second solder bumps. The semiconductor device included a number of die pads. The circuit board includes a number of contact pads. The first solder bumps are configured to bond the semiconductor device and the circuit board. Each of the first solder bumps connects at least two die pads with a corresponding contact pad. Each of the second solder bumps connects a die pad with a corresponding contact pad. A method of forming a surface mounting component or a chip scale package assembly wherein the component or assembly has at least two different types of solder bumps.

Semiconductor device and method of forming SIP module over film layer

A semiconductor device has a semiconductor die or component, including an IPD, disposed over an attach area of a penetrable film layer with a portion of the semiconductor die or component embedded in the penetrable film layer. A conductive layer is formed over a portion of the film layer within the attach area and over a portion of the film layer outside the attach area. An encapsulant is deposited over the film layer, conductive layer, and semiconductor die or component. The conductive layer extends outside the encapsulant. An insulating material can be disposed under the semiconductor die or component. A shielding layer is formed over the encapsulant. The shielding layer is electrically connected to the conductive layer. The penetrable film layer is removed. The semiconductor die or component disposed over the film layer and covered by the encapsulant and shielding layer form an SIP module without a substrate.

Semiconductor device and method for forming the same

A method includes receiving a first design for conductive bumps on a first surface of an interposer, the conductive bumps in the first design having a same cross-section area; grouping the conductive bumps in the first design into a first group of conductive bumps in a first region of the first surface and a second group of conductive bumps in a second region of the first surface, where a bump pattern density of the second region is lower than that of the first region; forming a second design by modifying the first design, where modifying the first design includes modifying a cross-section area of the second group of conductive bumps in the second region; and forming the conductive bumps on the first surface of the interposer in accordance with the second design, where after being formed, the first group of conductive bumps and the second group of conductive bumps have different cross-section areas.

Package structure and methods for forming the same

A structure and a formation method of a package structure are provided. The method includes forming one or more solder elements over a substrate. The one or more solder elements surround a region of the substrate. The method also includes disposing a semiconductor die structure over the region of the substrate. The method further includes dispensing a polymer-containing liquid onto the region of the substrate. The one or more solder elements confine the polymer-containing liquid to being substantially inside the region. In addition, the method includes curing the polymer-containing liquid to form an underfill material.

Semiconductor device and method of forming SIP module over film layer

A semiconductor device has a semiconductor die or component, including an IPD, disposed over an attach area of a penetrable film layer with a portion of the semiconductor die or component embedded in the penetrable film layer. A conductive layer is formed over a portion of the film layer within the attach area and over a portion of the film layer outside the attach area. An encapsulant is deposited over the film layer, conductive layer, and semiconductor die or component. The conductive layer extends outside the encapsulant. An insulating material can be disposed under the semiconductor die or component. A shielding layer is formed over the encapsulant. The shielding layer is electrically connected to the conductive layer. The penetrable film layer is removed. The semiconductor die or component disposed over the film layer and covered by the encapsulant and shielding layer form an SIP module without a substrate.

Electronic component package and electronic device including the same

Semiconductor device and method of forming conductive vias through interconnect structures and encapsulant of wlcsp

INTERCONNECT SYSTEM AND METHOD OF FABRICATION

Embodiments of the present invention relate generally to interconnect systems. One embodiment relates to an interconnect system (11) having a first substrate (10), and a standoff (20) that extends from said first substrate. The interconnect system further includes a cap (22), intended for subsequent reflow attachment, that covers a first end of the standoff and does not cover the sides of the standoff. The interconnect system further includes a nonwettable surface layer (24) on the sides of the standoff such that the cap is prevented from substantially wetting the sides of the standoff when the cap is in a fluid state. The interconnect system may further include a second substrate (28) attached to the cap where substantially all of the cap is located at the first end of the standoff. Another embodiment of the present inventions relates to a method of fabricating the interconnect system.

METHODS AND STRUCTURES FOR A VERTICAL PILLAR INTERCONNECT

In wafer-level chip-scale packaging and flip-chip packaging and assemblies, a solder cap is formed on a vertical pillar. In one embodiment, the vertical pillar overlies a semiconductor substrate. A solder paste, which may be doped with at least one trace element, is applied on a top surface of the pillar structure. A reflow process is performed after applying the solder paste to provide the solder cap.

SEMICONDUCTOR CHIP WITH SOLDER BUMP AND METHOD OF FRABRICATING THE SAME

A semiconductor chip having a solder bump and a method of fabricating the same are provided. The semiconductor chip includes at least one under bump metal (UBM) layer formed on an electrode pad of the semiconductor chip, an adhesion enhance layer (AEL) formed on the UBM layer and having at least one concavo-convex portion on a top surface thereof, and the solder bump formed on the AEL. Thereby, adhesive force between the UBM layer and the solder bump is increased, and thereby the reliability of the semiconductor chip can be improved. Further, it is possible to prevent tin (Sn) in the solder bump from being diffused due to the AEL.

BUMP I/O CONTACT FOR SEMICONDUCTOR DEVICE

A bump contact electrically connects a conductor on a substrate (72) and a contact pad (54) on a semiconductor device (50) mounted to the substrate. The first end of an electrically conductive pillar (60) effects electrical contact and mechanical attachment of the pillar to the contact pad with the pillar projecting outwardly from the semiconductor device. A solder crown (64) ref lowable at a predetermined temperature into effecting electrical, contact and mechanical attachment with the conductor is positioned in axial alignment with the second end of the pillar. A diffusion barrier (62) electrically and mechanically joins the solder bump to the second end of the pillar and resists electro-migration into the first end of the solder crown of copper from the pillar. One diffusion barrier takes the form of a 2-20 micrometer thick control layer of nickel, palladium,.titanium- tungsten, nickel -vanadium, or tantalum nitride positioned between the pillar and the solder crown.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A method of manufacturing a semiconductor device includes the steps of forming barrier metals on first electrodes provided on a chip of the semiconductor device, implementing a predetermined test on the semiconductor device by applying a signal to the semiconductor device via at least one of the barrier metals, and forming second protruded electrodes on the barrier metals. The predetermined tests are implemented before forming second protruded electrodes on the barrier metals.

Radiate under-bump metallization structure for semiconductor devices

An under-bump metallization (UBM) structure for a semiconductor device is provided. The UBM structure has a center portion and extensions extending out from the center portion. The extensions may have any suitable shape, including a quadrangle, a triangle, a circle, a fan, a fan with extensions, or a modified quadrangle having a curved surface. Adjacent UBM structures may have the respective extensions aligned or rotated relative to each other. Flux may be applied to a portion of the extensions to allow an overlying conductive bump to adhere to a part of the extensions.

Semiconductor Device and Method of Stacking Semiconductor Die in Mold Laser Package Interconnected By Bumps and Conductive Vias

A semiconductor wafer contains a plurality of first semiconductor die. The semiconductor wafer is mounted to a carrier. A channel is formed through the semiconductor wafer to separate the first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. An encapsulant is deposited over the carrier and first semiconductor die and into the channel while a side portion and surface portion of the second semiconductor die remain exposed from the encapsulant. A first conductive via is formed through the encapsulant in the channel. A second conductive via is formed through the encapsulant over a contact pad of the first semiconductor die. A conductive layer is formed over the encapsulant between the first and second conductive vias. An insulating layer is formed over the conductive layer and encapsulant. The carrier is removed. An interconnect structure is formed over the first conductive via.

Wiring substrate and semiconductor device

A wiring substrate includes a first wiring structure and a second wiring structure. The first wiring structure includes a first insulating layer, which covers a first wiring layer, and a via wiring. A first through hole of the first insulating layer is filled with the via wiring. The second wiring structure includes a second wiring layer and a second insulating layer. The second wiring layer is formed on an upper surface of the first insulating layer and an upper end surface of the via wiring. The second wiring layer partially includes a roughened surface. The second insulating layer is stacked on the upper surface of the first insulating layer and covers the second wiring layer. The second wiring structure has a higher wiring density than the first wiring structure. The roughened surface of the second wiring layer has a smaller surface roughness than the first wiring layer.

Dummy conductive structures for EMI shielding

A semiconductor device has a first conductive layer and a second conductive layer. A first portion of the first conductive layer is aligned with a first portion of the second conductive layer. An insulating layer is deposited over the first conductive layer and second conductive layer. A third conductive layer includes a first portion of the third conductive layer vertically aligned with the first portion of the first conductive layer and the first portion of the second conductive layer. An electrical component is disposed over the first conductive layer and second conductive layer. An encapsulant is deposited over the first conductive layer, second conductive layer, and electrical component. A cut is made through the encapsulant, first conductive layer, and second conductive layer. A fourth conductive layer is deposited over side surfaces of the first conductive layer, second conductive layer, and encapsulant.

Microelectronic spring contact elements

Spring contact elements are fabricated by depositing at least one layer of metallic material into openings defined in masking layers deposited on a surface of a substrate which may be an electronic component such as an active semiconductor device. Each spring contact element has a base end, a contact end, and a central body portion. The contact end is offset in the z-axis (at a different height) and in at least one of the x and y directions from the base end. In this manner a plurality of spring contact elements are fabricated in a prescribed spatial relationship with one another on the substrate. The spring contact elements make temporary (i.e., pressure) or permanent (e.g., joined by soldering or brazing or with a conductive adhesive) connections with terminals of another electronic component to effect electrical connections therebetween. In an exemplary application, the spring contact elements are disposed on a semiconductor devices resident on a semiconductor wafer so that temporary ...

3D interconnect component for fully molded packages

A method of making a semiconductor component package can include providing a substrate comprising conductive traces, soldering a surface mount device (SMD) to the substrate with solder, encapsulating the SMD on the substrate with a first mold compound over and around the SMD to form a component assembly, and mounting the component assembly to a temporary carrier with a first side of the component assembly oriented towards the temporary carrier. The method can further include mounting a semiconductor die comprising a conductive interconnect to the temporary carrier adjacent the component assembly, encapsulating the component assembly and the semiconductor die with a second mold compound to form a reconstituted panel, and exposing the conductive interconnect and the conductive traces at the first side and the second side of the component assembly with respect to the second mold compound.

Single mask package apparatus and method

Disclosed herein is a single mask package apparatus on a device comprising a first substrate having a land disposed on a first surface, a stud disposed on the land and a protective layer disposed over the first surface of the first substrate and around the stud. The protective layer may optionally have a thickness of at least 3 m. A PPI may be disposed over the protective layer and in electrical contact with the stud, with a first portion of the PPI extending laterally from the stud. An interconnect may be disposed on and in electrical contact with the first portion of the PPI, and a second substrate mounted on the interconnect. A molding compound may be disposed over the PPI and around the interconnect. The stud may be a substantially solid material having a cylindrical cross section and may optionally be wirebonded to the land.

Thermocompression Bonding with Passivated Gold Contacting Metal

Methods and systems for low-force, low-temperature thermocompression bonding. The present application teaches new methods and structures for three-dimensional integrated circuits, in which cold thermocompression bonding is used to provide reliable bonding. To achieve this, reduction and passivation steps are preferably both used to reduce native oxide on the contact metals and to prevent reformation of native oxide, preferably using atmospheric plasma treatments. Preferably the physical compression height of the elements is set to be only enough to reliably achieve at least some compression of each bonding element pair, compensating for any lack of flatness. Preferably the thermocompression bonding is performed well below the melting point. This not only avoids the deformation of lower levels which is induced by reflow techniques, but also provides a steep relation of force versus z-axis travel, so that a drastically-increasing resistance to compression helps to regulate the degree of thermocompression ...

Mechanically anchored backside C4 pad

The present invention relates generally to flip chip technology and more particularly, to a method and structure for fabricating a mechanically anchored controlled collapse chip connection (C4) pad on a semiconductor structure. In an embodiment, a method is disclosed that may include forming a bonding pad having one or more anchor regions that extend into a semiconductor structure and may inhibit the bonding pad from physically separating from the TSV during temperature fluctuations.

Pop devices and methods of forming the same

PoP devices and methods of forming the same are disclosed. A PoP device includes a first package structure and a second package structure. The first package structure includes a first chip, and a plurality of active through integrated fan-out vias and a plurality of dummy through integrated fan-out vias aside the first chip. The second package structure includes a plurality active bumps bonded to the plurality of active through integrated fan-out vias, and a plurality of dummy bumps bonded to the plurality of dummy through integrated fan-out vias. Besides, a total number of the active through integrated fan-out vias and the dummy through integrated fan-out vias at a first side of the first chip is substantially the same as a total number of the active through integrated fan-out vias and the dummy through integrated fan-out vias at a second side of the first chip.

Adhesive for semiconductor, fluxing agent, manufacturing method for semiconductor device, and semiconductor device

An adhesive for a semiconductor, comprising an epoxy resin, a curing agent, and a compound having a group represented by the following formula (1): wherein R1represents an electron-donating group.

Semiconductor chip stack and method for manufacturing semiconductor chip stack

A semiconductor chip stack includes a first semiconductor chip, a second semiconductor chip, and a connection via which the first electrode and the second electrode are electrically connected to each other. The connection includes a first column and a second column. The first column is constituted by a material having a higher degree of activity with respect to heat than a material that constitutes the second column and is smaller in volume than the second column. Further, the connection has an aspect ratio of 0.5 or higher in a height direction.

Double molded chip scale package

Chip scale semiconductor packages and methods for making and using the same are described. The chip scale semiconductor packages (CSPs) contain a die with an integrated circuit device, a patterned plating layer, and a second interconnect structure formed from a Cu etched substrate that has a portion of an upper surface connected to the patterned plating layer, a side surface, and a bottom surface. The die can be attached to the patterned plating layer by a first interconnect structure that uses wirebonding or that uses a flip chip attachment process. The CSP contains a double molded structure where a first molding layer encapsulates the die, the patterned plating layer, the first interconnect structure, and the upper surface of the second interconnect structure. The second molding layer encapsulates the side surface of the second interconnect structure without encapsulating the bottom surface of the second interconnect structure. With such a configuration, the second molding layer helps control warpage during the manufacturing process and no printed circuit board (PCB) substrate is needed when the package is used in an electronic device since the signal routing is performed by the second interconnect structure. Other embodiments are described.

Semiconductor Device and Method of Forming RDL Wider than Contact Pad along First Axis and Narrower than Contact Pad Along Second Axis

A semiconductor device has a semiconductor die and first conductive layer formed over a surface of the semiconductor die. A first insulating layer is formed over the surface of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. An opening is formed in the second insulating layer over the first conductive layer. A second conductive layer is formed in the opening over the first conductive layer and second insulating layer. The second conductive layer has a width that is less than a width of the first conductive layer along a first axis. The second conductive layer has a width that is greater than a width of the first conductive layer along a second axis perpendicular to the first axis. A third insulating layer is formed over the second conductive layer and first insulating layer.

Semiconductor device and manufacturing method thereof

Semiconductor devices of embodiments include a plurality of solder bumps electrically connected on a plurality of electrode pads disposed on a semiconductor substrate in parallel at a pitch of 40 μm or less via under bump metals. The ratio of the diameter (the top diameter) of the portion of each solder bump most away from the semiconductor substrate and the diameter (the bottom diameter) of the bottom side of each solder bump is 1:1 to 1:4.

Package carrier

A package carrier including a substrate, at least an under bump metallurgic (UBM) layer and at least a conductive bump is provided. The substrate has a conductive structure and at least a pad connected with the conductive structure. A region of the pad connected with the conductive structure is a signal source region. The UBM layer is disposed on the pad and includes a first conductive pattern and a second conductive pattern. A side wall of the second conductive pattern is directly connected to a side wall of the first conductive pattern, and the second conductive pattern is disposed close to the signal source region. The conductivity of the second conductive pattern is smaller than the conductivity of the first conductive pattern. The conductive bump is disposed on the UBM layer.

Mechanisms for resistivity measurement of bump structures

The embodiments described above provide mechanisms for bump resistivity measurement. By using designated bumps on one or more corners of dies, the resistivity of bumps may be measured without damaging devices and without a customized probing card. In addition, bump resistivity may be collected across the entire wafer. The collected resistivity data may be used to monitor the stability and/or health of processes used to form bumps and their underlying layers.

Semiconductor Device and Method of Forming an Inductor Within Interconnect Layer Vertically Separated from Semiconductor Die

A semiconductor device has an adhesive layer formed over a carrier. A semiconductor die has bumps formed over an active surface of the semiconductor die. The semiconductor die is mounted to the carrier with the bumps partially disposed in the adhesive layer to form a gap between the semiconductor die and adhesive layer. An encapsulant is deposited over the semiconductor die and within the gap between the semiconductor die and adhesive layer. The carrier and adhesive layer are removed to expose the bumps from the encapsulant. An insulating layer is formed over the encapsulant. A conductive layer is formed over the insulating layer in a wound configuration to exhibit inductive properties and electrically connected to the bumps. The conductive layer is partially disposed within a footprint of the semiconductor die. The conductive layer has a separation from the semiconductor die as determined by the gap and insulating layer.

Semiconductor Device and Method of Forming Narrow Interconnect Sites on Substrate with Elongated Mask Openings

A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the semiconductor die. A plurality of conductive traces is formed over a surface of the substrate with interconnect sites. A masking layer is formed over the surface of the substrate. The masking layer has a plurality of parallel elongated openings each exposing at least two of the conductive traces and permitting a flow of bump material along a length of the plurality of conductive traces within the plurality of elongated openings while preventing the flow of bump material past a boundary of the plurality of elongated openings. One of the conductive traces passes beneath at least two of the elongated openings. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate.

Semiconductor Device and Method of Forming a Wafer Level Package Structure Using Conductive Via and Exposed Bump

A semiconductor device has a carrier. A semiconductor wafer including a semiconductor die is mounted to the carrier with an active surface of the semiconductor die facing away from the carrier. A plurality of bumps is formed over the active surface of the semiconductor die. An opening is formed in a periphery of the semiconductor die. An encapsulant is deposited over the carrier and semiconductor die, in the opening, and around the plurality of bumps such that an exposed portion of the plurality of bumps is devoid of encapsulant. A conductive via is formed through the encapsulant, within the opening, and extends to the carrier. A conductive layer is formed over the encapsulant and electrically connects to the conductive via and the exposed portion of the plurality of bumps. The carrier is removed to expose an end of the conductive via.

Spherical solder reflow method

The present disclosure relates to methods of making solder balls having a uniform size. More particularly, the disclosure relates to improved solder ball formation processes that prevent or reduce bridging/merging of two or more solder balls during reflow. The processes of the instant disclosure are desirable because they do not require a sifting step to obtain uniformly-sized solder balls.

Semiconductor Device and Method of Making a Semiconductor Device

A semiconductor device and a method of manufacturing a semiconductor device are disclosed. An embodiment comprises forming a bump on a die, the bump having a solder top, melting the solder top by pressing the solder top directly on a contact pad of a support substrate, and forming a contact between the die and the support substrate.

Semiconductor chip and flip-chip package comprising the same

A semiconductor chip includes stress-relief to mitigate the effects of differences in coefficients of thermal expansion (CTE) between a printed circuit board (PCB) and a semiconductor chip and a flip-chip package including the semiconductor chip. The semiconductor chip includes a stress-relief buffer coupling a bump and a semiconductor chip pad.

Semiconductor Device and Method of Forming Interposer Frame Electrically Connected to Embedded Semiconductor Die

A semiconductor device has an interposer frame mounted over a carrier. A semiconductor die has an active surface and bumps formed over the active surface. The semiconductor die can be mounted within a die opening of the interposer frame or over the interposer frame. Stacked semiconductor die can also be mounted within the die opening of the interposer frame or over the interposer frame. Bond wires or bumps are formed between the semiconductor die and interposer frame. An encapsulant is deposited over the interposer frame and semiconductor die. An interconnect structure is formed over the encapsulant and bumps of the first semiconductor die. An electronic component, such as a discrete passive device, semiconductor die, or stacked semiconductor die, is mounted over the semiconductor die and interposer frame. The electronic component has an I/O count less than an I/O count of the semiconductor die.

Semiconductor Device and Method of Forming Interposer Frame Over Semiconductor Die to Provide Vertical Interconnect

A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.

Post-passivation interconnect structure and method of forming the same

A semiconductor device includes a conductive layer formed on the surface of a post-passivation interconnect (PPI) structure by an immersion tin process. A polymer layer is formed on the conductive layer and patterned with an opening to expose a portion of the conductive layer. A solder bump is then formed in the opening of the polymer layer to electrically connect to the PPI structure.

Test Structure and Method of Testing Electrical Characteristics of Through Vias

A method and apparatus for testing the electrical characteristics, such as electrical continuity, is provided. A substrate, such as a wafer or an interposer, having a plurality of through vias (TVs) is provided. Along one side of the substrate, a conductive layer electrically couples two or more of the TVs. Thereafter, the electrical characteristics of the TVs may be test by, for example, a probe card in electrical contact with the TVs on the other side of the substrate. During testing, current passes through a first TV from a first side of the substrate, to the conductive layer on a second side of the substrate, to a second TV, and back to the first side of the substrate through the second TV.

Semiconductor Device and Method of Forming RDL Under Bump for Electrical Connection to Enclosed Bump

A semiconductor device has a semiconductor wafer with a plurality of semiconductor die. A first conductive layer is formed over a surface of the wafer. A first insulating layer is formed over the surface of the wafer and first conductive layer. A second conductive layer has first and second segments formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A UBM layer is formed over the second insulating layer and the first segment of the second conductive layer. A first bump is formed over the UBM layer. The first bump is electrically connected to the second segment and electrically isolated from the first segment of the second conductive layer. A second bump is formed over the surface of the wafer and electrically connected to the first segment of the second conductive layer.

Packaging Process Tools and Systems, and Packaging Methods for Semiconductor Devices

Packaging process tools and systems, and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging process tool for semiconductor devices includes a mechanical structure for supporting package substrates or integrated circuit die during a packaging process for the integrated circuit die. The mechanical structure includes a low thermal conductivity material disposed thereon.

Method of processing solder bump by vacuum annealing

A method includes vacuum annealing on a substrate having at least one solder bump to reduce voids at an interface of the at least one solder bump. A die is mounted over the substrate.

Mechanisms of forming connectors for package on package

The described embodiments of mechanisms of forming connectors for package on package enable smaller connectors with finer pitch, which allow smaller package size and additional connections. The conductive elements on one package are partially embedded in the molding compound of the package to bond with contacts or metal pads on another package. By embedding the conductive elements, the conductive elements may be made smaller and there are is gaps between the conductive elements and the molding compound. A pitch of the connectors can be determined by adding a space margin to a maximum width of the connectors. Various types of contacts on the other package can be bonded to the conductive elements.

Flip-chip packaging techniques and configurations

Embodiments of the present disclosure flip-chip packaging techniques and configurations. An apparatus may include a package substrate having a plurality of pads formed on the package substrate, the plurality of pads being configured to receive a corresponding plurality of interconnect structures formed on a die and a fluxing underfill material disposed on the package substrate, the fluxing underfill material comprising a fluxing agent configured to facilitate formation of solder bonds between individual interconnect structures of the plurality of interconnect structures and individual pads of the plurality of pads and an epoxy material configured to harden during formation of the solder bonds to mechanically strengthen the solder bonds. Other embodiments may also be described and/or claimed.

Lead frame, semiconductor device, and method for manufacturing lead frame

A lead frame includes a plurality of leads defined by an opening extending in a thickness direction. An insulating resin layer fills the opening to entirely cover side surfaces of each lead and to support the leads. A first surface of each lead is exposed from a first surface of the insulating resin layer.

Cleaning Methods and Compositions

Methods and chemical solvents used for cleaning residues on metal contacts during a semiconductor device packaging process are disclosed. A chemical solvent for cleaning a residue formed on a metal contact may comprise a reactive inorganic component and a reactive organic component. The method may comprise spraying a semiconductor device with a chemical solvent at a first pressure, and spraying the semiconductor device with the chemical solvent at a second pressure less than the first pressure.

Semiconductor Device and Method of Forming Guard Ring Around Conductive TSV Through Semiconductor Wafer

A semiconductor device has a plurality of conductive vias formed into a semiconductor wafer. An insulating lining is formed around the conductive vias and a conductive layer is formed over the insulating lining. A portion of the semiconductor wafer is removed so the conductive vias extend above a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and conductive vias. A first portion of the first insulating layer is removed and a second portion of the first insulating layer remains as guard rings around the conductive vias. A conductive layer is formed over the conductive vias. A second insulating layer is formed over the surface of the semiconductor wafer, guard rings, and conductive vias. A portion of the second insulating layer is removed to expose the conductive vias and a portion of the guard rings.

Cte adaption in a semiconductor package

A device such as a wafer-level package (WLP) device is proposed in which a dielectric layer is disposed between a surface of a semiconductor device and a surface of a redistribution layer (RDL). The dielectric layer may have at least one interconnect extending through the dielectric layer. The dielectric layer may have a coefficient of thermal expansion (CTE) value in a direction perpendicular to the surface of the semiconductor device that is less than a threshold value, and a Young's modulus that is greater than another threshold value. The dielectric layer may have a CTE value in a direction parallel to the surface of the semiconductor device at a surface of the dielectric layer facing the RDL that is greater than another threshold value

Semiconductor chip with expansive underbump metallization structures

Methods and apparatus to protect fragile dielectric layers in a semiconductor chip are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first polymer layer over a conductor pad of a semiconductor chip where the conductor pad has a first lateral dimension. An underbump metallization structure is formed on the first polymer layer and in ohmic contact with the conductor pad. The underbump metallization structure has a second lateral dimension greater than the first lateral dimension. A second polymer layer is formed on the first polymer layer with a first opening exposing at least a portion of the underbump metallization structure.

Microelectric package utilizing multiple bumpless build-up structures and through-silicon vias

A microelectronic package having a first bumpless build-up layer structure adjacent an active surface and sides of a microelectronic device and a second bumpless build-up layer structure adjacent a back surface of the microelectronic device, wherein conductive routes are formed through the first bumpless build-up layer from the microelectronic device active surface to conductive routes in the second bumpless build-up layer structure and wherein through-silicon vias adjacent the microelectronic device back surface and extending into the microelectronic device are electrically connected to the second bumpless build-up layer structure conductive routes.

Methods and Apparatus of Packaging Semiconductor Devices

Methods and apparatuses for wafer level packaging (WLP) semiconductor devices are disclosed. A redistribution layer (RDL) is formed on a first passivation layer in contact with a conductive pad over a surface of a die. The RDL layer is on top of a first region of the first passivation layer. A second passivation layer is formed on the RDL layer with an opening to expose the RDL layer, and over the first passivation layer. An under bump metallization (UBM) layer is formed over the second passivation layer in contact with the exposed RDL layer. A second region of the first passivation layer disjoint from the first region is determined by projecting an outer periphery of a solder ball or other connector onto the surface.

Methods and Apparatus for Package on Package Structures

A package-on-package (“PoP”) structure and a method of forming are provided. The PoP structure may be formed by forming a first set of electrical connections on a first substrate. A first material may be applied to the first set of electrical connections. A second substrate may be provided having a second set of electrical connections formed thereon. The first set of electrical connections of the first substrate having the epoxy flux applied may be contacted to the second electrical connections of the second substrate. A reflow process may be performed to electrically connect the first substrate to the second substrate. The epoxy flux applied to the first electrical connections of the first substrate may prohibit electrical bridges or shorts from forming during the reflow process.

Bump Structure and Method of Forming Same

An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal bump on the under bump metallurgy feature, and a substrate trace on a substrate, the substrate trace coupled to the metal bump through a solder joint and intermetallic compounds, a ratio of a first cross sectional area of the intermetallic compounds to a second cross sectional area of the solder joint greater than forty percent.

Metal Bump and Method of Manufacturing Same

An embodiment bump structure includes a contact element formed on a substrate, a passivation layer overlying the substrate, the passivation layer having a passivation opening exposing the contact element a polyimide layer overlying the passivation layer, the polyimide layer having a polyimide opening exposing the contact element an under bump metallurgy (UMB) feature electrically coupled to the contact element, the under bump metallurgy feature having a UBM width, and a copper pillar on the under bump metallurgy feature, a distal end of the copper pillar having a pillar width, the UBM width greater than the pillar width.

Method and apparatus for manufacturing array device

A method for manufacturing an array device includes a placing step of providing a plurality of elements in an array on a first surface of a substrate, an element separating step of separating a plurality of element chips from one another so that each element chip includes one or more elements, an inspecting step of inspecting the plurality of elements, a removing step of removing any element chip of the plurality of element chips from the surface of the substrate on the basis of a result of the inspecting step, and a mounting step of, after the removing step, mounting an element of at least the elements other than an element of the element chip thus removed onto a mounting substrate by transfer from the substrate, the mounting substrate being different from the substrate.

Semiconductor Device and Method of Forming Build-Up Interconnect Structures Over a Temporary Substrate

A semiconductor device has a first build-up interconnect structure formed over a substrate. The first build-up interconnect structure includes an insulating layer and conductive layer formed over the insulating layer. A vertical interconnect structure and semiconductor die are disposed over the first build-up interconnect structure. The semiconductor die, first build-up interconnect structure, and substrate are disposed over a carrier. An encapsulant is deposited over the semiconductor die, first build-up interconnect structure, and substrate. A second build-up interconnect structure is formed over the encapsulant. The second build-up interconnect structure electrically connects to the first build-up interconnect structure through the vertical interconnect structure. The substrate provides structural support and prevents warpage during formation of the first and second build-up interconnect structures. The substrate is removed after forming the second build-up interconnect structure. A portion of the insulating layer is removed exposing the conductive layer for electrical interconnect with subsequently stacked semiconductor devices. 1. A method of making a semiconductor device , comprising:providing a substrate;forming a first interconnect structure over the substrate;disposing a first semiconductor die over the first interconnect structure;disposing the substrate over a carrier with the first semiconductor die oriented away from the carrier;depositing an encapsulant over the carrier, substrate, and first semiconductor die;forming a second interconnect structure over the encapsulant and semiconductor die; andremoving the substrate to expose the first interconnect structure after forming the second interconnect structure.2. The method of claim 1 , further including forming a conductive column over the first interconnect structure.3. The method of claim 2 , wherein the conductive column extends from the first interconnect structure to the second interconnect structure ...

Metal pad modification

The present invention provides a structure. In an exemplary embodiment, the structure includes a base material, at least one metal pad, where a first surface of the metal pad is in contact with the base material, and a metal pedestal, where the metal pedestal is in contact with the metal pad, where a radial alignment of the metal pad is shifted by an offset distance, with respect to the metal pedestal, such that the metal pad is shifted towards a center axis of the base material, where a first dimension of the metal pad is smaller than a second dimension of the metal pad, where the second dimension is orthogonal to a line running from a center of the metal pad to the center axis of the base material, where the first dimension is parallel to the line.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, a first metal layer located on the first semiconductor substrate, a second metal layer located on the second semiconductor substrate, a third metal layer, a first alloy layer, and a second alloy layer. The third metal layer extends between the first metal layer and the second metal layer. The first alloy layer comprises components of the first and third metal layers, and is provided between the first metal layer and the third metal layer. The second alloy layer comprises components of the second and third metal layers, and is provided between the second metal layer and the third metal layer. At least one of the first metal the second metal layers projects into the third metal layer at a circumferential edge portion thereof. 1. A semiconductor device comprising:a first semiconductor substrate;a second semiconductor substrate facing the first semiconductor substrate;a first pad electrode disposed on a surface of the first semiconductor substrate facing the second semiconductor substrate;a second pad electrode disposed on a surface of the second semiconductor substrate facing the first semiconductor substrate;a first insulating layer disposed on an edge portion of the first pad electrode and the first semiconductor substrate;a second insulating layer disposed on an edge portion of the second pad electrode and the second semiconductor substrate;a first metal layer disposed over the first pad electrode and facing the second semiconductor substrate;a second metal layer disposed over the second pad electrode and facing the first semiconductor substrate;a third metal layer disposed between the first metal layer and the second metal layer;a first alloy layer disposed between the first metal layer and the third metal layer and comprising a component of the first metal layer and a component of the third metal layer; anda second alloy layer disposed between the second metal layer ...

Semiconductor Device and Method of Depositing Encapsulant Along Sides and Surface Edge of Semiconductor Die in Embedded WLCSP

A semiconductor device has a semiconductor wafer including a plurality of semiconductor die. An insulating layer is formed over the semiconductor wafer. A portion of the insulating layer is removed by LDA to expose a portion of an active surface of the semiconductor die. A first conductive layer is formed over a contact pad on the active surface of the semiconductor die. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is disposed over a carrier with the active surface of the semiconductor die offset from the carrier. An encapsulant is deposited over the semiconductor die and carrier to cover a side of the semiconductor die and the exposed portion of the active surface. An interconnect structure is formed over the first conductive layer. Alternatively, a MUF material is deposited over a side of the semiconductor die and the exposed portion of the active surface. 1. A method of making a semiconductor device , comprising:providing a substrate;disposing a semiconductor die over the substrate;depositing a first encapsulant over the substrate and semiconductor die; andsingulating the first encapsulant.2. The method of claim 1 , further including:depositing a second encapsulant over the semiconductor die; andsingulating the second encapsulant and substrate prior to depositing the first encapsulant.3. The method of claim 2 , further including depositing the second encapsulant between the semiconductor die and substrate.4. The method of claim 1 , further including removing a portion of the first encapsulant to form a recess in the first encapsulant adjacent to the substrate prior to singulating the first encapsulant.5. The method of claim 4 , further including removing the portion of the first encapsulant using laser direct ablation (LDA).6. The method of claim 1 , further including depositing a mold underfill between the semiconductor die and substrate.7. The method of claim 1 , further including disposing an interconnect ...

Package assembly

In some embodiments, the present disclosure relates to a package assembly having a bump on a first substrate. A molding compound is on the first substrate and contacts sidewalls of the bump. A no-flow underfill layer is on a conductive region of a second substrate. The no-flow underfill layer and the conductive region contact the bump. A mask layer is arranged on the second substrate and laterally surrounds the no-flow underfill layer. The no-flow underfill layer contacts the substrate between the conductive region and the mask layer.

Bump Structures for Multi-Chip Packaging

A multi-chip package includes a substrate having a plurality of first bump structures. A pitch between first bump structures of the plurality of first bump structures is uniform across a surface of the substrate. The multi-chip package includes a first chip bonded to the substrate and a second chip bonded to the substrate. The first chip includes a plurality of second bump structures, and the plurality of second bump structures are bonded to a first set of first bump structures of the plurality of first bump structures. The second chip includes a plurality of third bump structures, and the plurality of third bump structures are bonded to a second set of first bump structures of the plurality of first bump structures. A pitch between second bump structures of the plurality of second bump structures is different from a pitch between third bump structures of the plurality of third bump structures. 1. A method of forming a multi-chip package , the method comprising:bonding a first chip to a substrate, wherein the substrate has a plurality of first bump structures, wherein the first chip comprises a plurality of second bump structures, and bonding the first chip to the substrate comprises covering at least two first bump structures of the plurality of first bump structures with a second bump structure of the plurality of second bump structures, each of the plurality of first bump structures being coupled to different contact pads; andbonding a second chip to the substrate, wherein the second chip comprises a plurality of third bump structures, and bonding the second chip to the substrate comprises bonding the plurality of third bump structures to corresponding ones of a set of first bump structures of the plurality of first bump structures.2. The method of claim 1 , wherein bonding the first chip to the substrate comprises covering an entirety of each sidewall of the at least two first bump structures.3. The method of claim 1 , wherein the at least two first bump ...

CONDUCTIVE CONNECTIONS, STRUCTURES WITH SUCH CONNECTIONS, AND METHODS OF MANUFACTURE

A solder connection may be surrounded by a solder locking layer () and may be recessed in a hole () in that layer. The recess may be obtained by evaporating a vaporizable portion () of the solder connection. Other features are also provided. 1. A manufacturing method comprising: one or more first components each of which comprises solder and a material sublimatable or vaporizable when the solder is melted; and', 'a first layer comprising a top surface and one or more holes in the top surface, each hole containing at least a segment of a corresponding first component;, 'obtaining a first structure comprisingheating each first component to sublimate or vaporize at least part of each sublimatable or vaporizable material and provide an electrically conductive connection at a location of each first component;wherein in the heating operation at least part of each first component recedes down from the top surface to provide or increase a recess in each hole at the top surface.2. The method of wherein each hole is a through-hole.3. The method of wherein each hole's sidewall is a dielectric sidewall.4. The method of wherein the first layer is dielectric.5. The method of wherein the first layer is formed by molding.6. The method of further comprising:obtaining a second structure with one or more protruding conductive posts; andinserting each conductive post into a corresponding recess provided or increased in the heating operation, and forming a solder bond in each recess between the corresponding conductive post and the corresponding electrically conductive connection.7. The method of wherein before the heating operation claim 1 , at least a segment of each first component either:comprises of a solder core coated with the sublimatable or vaporizable material; orconsists of the sublimatable or vaporizable material.8. The method of wherein in obtaining the first structure claim 7 , the one or more first components are formed before the first layer.9. The method of wherein in ...

Wiring substrate and semiconductor package

A wiring substrate includes an insulating layer and a wiring layer buried in the insulating layer at a first surface of the insulating layer. The wiring layer includes a first portion and a second portion. The first portion is narrower and thinner than the second portion. The first portion includes a first surface exposed at the first surface of the insulating layer. The second portion includes a first surface exposed at the first surface of the insulating layer and a second surface partly exposed in an opening formed in the insulating layer. The opening is open at a second surface of the insulating layer opposite to the first surface thereof.

SURFACE FINISHES FOR INTERCONNECTION PADS IN MICROELECTRONIC STRUCTURES

A surface finish may be formed in a microelectronic structure, wherein the surface finish may include a multilayer interlayer structure. Thus, needed characteristics, such as compliance and electro-migration resistance, of the interlayer structure may be satisfied by different material layers, rather attempting to achieve these characteristics with a single layer. In one embodiment, the multilayer interlayer structure may comprises a two-layer structure, wherein a first layer is formed proximate a solder interconnect and comprises a material which forms a ductile joint with the solder interconnect, and a second layer comprising a material having strong electro-migration resistance formed between the first layer and an interconnection pad. In a further embodiment, third layer may be formed adjacent the interconnection pad comprising a material which forms a ductile joint with the interconnection pad. 125.-. (canceled)26. A microelectronic structure , comprising:an interconnection pad;a surface finish on the interconnection pad, wherein the surface finish comprises a multilayer interlayer structure including at least one ductile layer and at least one electro-migration resistant layer; anda solder interconnect on the surface finish.27. The microelectronic structure of claim 26 , wherein the at least one ductile layer comprises a nickel material having phosphorus content of between about 2% and 10% by weight.28. The microelectronic structure of claim 26 , wherein the at least one electro-migration resistant layer comprises a nickel material having phosphorus content of between about 11% and 20% by weight.29. The microelectronic structure of claim 26 , wherein the at least one electro-migration resistant layer comprises a high atomic weight metal.30. The microelectronic structure of claim 29 , wherein the high atomic weight metal is selected from the group consisting of nickel claim 29 , cobalt claim 29 , and iron.31. The microelectronic structure of claim 26 , wherein ...

PACKAGE WITH METAL-INSULATOR-METAL CAPACITOR AND METHOD OF MANUFACTURING THE SAME

A package includes a chip formed in a first area of the package and a molding compound formed in a second area of the package adjacent to the first area. A first polymer layer is formed on the chip and the molding compound, a second polymer layer is formed on the first polymer layer, and a plurality of interconnect structures is formed between the first polymer layer and the second polymer layer. A metal-insulator-metal (MIM) capacitor is formed on the second polymer layer and electrically coupled to at least one of the plurality of interconnect structures. A metal bump is formed over and electrically coupled to at least one of the plurality of interconnect structures. 1. A package comprising:a chip and a molding compound adjacent to each other;a first polymer layer and a second polymer layer that are stacked on the chip and the molding compound, wherein the second polymer layer overlies the first polymer layer;a first interconnect structure between the first and second polymer layers;a capacitor on the second polymer layer and protruding through the second polymer layer to the first interconnect structure, wherein the capacitor comprises a lower electrode, a dielectric layer overlying the lower electrode, and an upper electrode overlying the dielectric layer;a barrier layer overlying and independent of the upper electrode, wherein the barrier layer is conductive;a metal layer overlying the barrier layer, wherein the capacitor, the barrier layer, and the metal layer collectively define a first common sidewall and collectively define a second common sidewall on an opposite side of the capacitor as the first common sidewall;an isolation coating covering the first and second polymer layers and the metal layer, wherein the isolation coating directly contacts a top surface of the metal layer continuously from the first common sidewall to the second common sidewall; anda conductive bump in an opening defined by the isolation coating and level with the capacitor.2. The ...

System, Structure, and Method of Manufacturing a Semiconductor Substrate Stack

A method of manufacturing a semiconductor substrate structure for use in a semiconductor substrate stack system is presented. The method includes a semiconductor substrate which includes a front-face, a backside, a bulk layer, an interconnect layer that includes a plurality of inter-metal dielectric layers sandwiched between conductive layers, a contact layer that is between the bulk layer and the interconnect layer, and a TSV structure commencing between the bulk layer and the contact layer and terminating at the backside of the substrate. The TSV structure is electrically coupled to the interconnect layer and the TSV structure is electrically coupled to a bonding pad on the backside.

3D Semiconductor Package Interposer with Die Cavity

Disclosed herein is a method of forming a device, comprising mounting a plurality of first interconnects on one or more first integrated circuit dies. One or more second integrated circuit dies are mounted on a first side of an interposer. The interposer is mounted at a second side to the first integrated circuit dies, the plurality of first interconnects disposed outside of the interposer. The interposer is mounted to a first side of a substrate by attaching the first interconnects to the substrate, the substrate in signal communication with one or more of the first integrated circuit dies through the first interconnects. 1. A device , comprising:a substrate having a top surface;an interposer over the top surface of the substrate, the interposer being connected to the substrate by first interconnects;a first integrated circuit die connected to a first side of the interposer by first connectors;a second integrated circuit die connected to a second side of the interposer opposite the first side by second connectors, the second integrated circuit die having a smaller footprint than the interposer; anda fan-out structure disposed over a top surface of the interposer and extending beyond outermost edges of the interposer, wherein the fan-out structure is electrically connected to second interconnects, the second interconnects in contact with the top surface of the substrate.2. The device of claim 1 , further comprising third connectors connecting the fan-out structure to the second integrated circuit die.3. The device of claim 1 , further comprising a cavity in the top surface of the substrate claim 1 , wherein the first integrated circuit die extends into the cavity.4. The device of claim 1 , further comprising:a first molding compound on sidewalls of the interposer, the first interconnects, and the second interconnects; anda second molding compound on the first molding compound, the fan-out structure, and the second integrated circuit die.5. The device of claim 1 , ...

Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP

A semiconductor device has an encapsulant deposited over a first surface of the semiconductor die and around the semiconductor die. A first insulating layer is formed over a second surface of the semiconductor die opposite the first surface. A conductive layer is formed over the first insulating layer. An interconnect structure is formed through the encapsulant outside a footprint of the semiconductor die and electrically connected to the conductive layer. The first insulating layer includes an optically transparent or translucent material. The semiconductor die includes a sensor configured to receive an external stimulus passing through the first insulating layer. A second insulating layer is formed over the first surface of the semiconductor die. A conductive via is formed through the first insulating layer outside a footprint of the semiconductor die. A plurality of stacked semiconductor devices is electrically connected through the interconnect structure.

Wiring substrate, semiconductor package and method of manufacturing wiring substrate

A second wiring layer is connected to a first wiring layer via an insulating layer. The second wiring layer comprises pad structures. Each pad structure includes a first metal layer formed on the insulating layer, a second metal layer formed on the first metal layer, and a third metal layer formed on the second metal layer. The pad structures comprises a first pad structure and a second pad structure. A via-wiring diameter of the first pad structure is different from a via-wiring diameter of the second pad structure. A distance from an upper surface of the insulating layer to an upper surface of the second metal layer of the first pad structure is the same as a distance from the upper surface of the insulating layer to an upper surface of the second metal layer of the second pad structure.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device includes a wiring substrate including wiring layers, a semiconductor chip including electrode pads and mounted on the wiring substrate, and a first capacitor including a first electrode and a second electrode, and mounted on the wiring substrate. The wiring layers include a first wiring layer including a first terminal pad electrically connected with the first electrode of the first capacitor and a second terminal pad electrically connected with the second electrode of the first capacitor; and a second wiring layer on an inner side by one layer from the first wiring layer of the wiring substrate and including a first conductor pattern having a larger area than each of the first terminal pad and the second terminal pad. The first conductor pattern includes a first opening in a region overlapping with each of the first terminal pad and the second terminal pad in the second wiring layer. 1. A semiconductor device comprising:a wiring substrate including a plurality of wiring layers;a semiconductor chip including a plurality of electrode pads and mounted on the wiring substrate; anda first capacitor including a first electrode and a second electrode, and mounted on the wiring substrate, a first wiring layer including a first terminal pad electrically connected with the first electrode of the first capacitor and a second terminal pad electrically connected with the second electrode of the first capacitor, and', 'a second wiring layer positioned on an inner side by one layer from the first wiring layer of the wiring substrate, and including a first conductor pattern having a larger area than each of the first terminal pad and the second terminal pad, and, 'wherein the plurality of wiring layers haswherein, in the second wiring layer, the first conductor pattern includes a first opening portion formed in a region overlapping with each of the first terminal pad and the second terminal pad.2. The semiconductor device according to claim 1 ,wherein the ...

Semiconductor Devices and Methods of Forming Thereof

In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a contact layer over a first major surface of a substrate. The substrate includes device regions separated by kerf regions. The contact layer is disposed in the kerf region and the device regions. A structured solder layer is formed over the device regions. The contact layer is exposed at the kerf region after forming the structured solder layer. The contact layer and the substrate in the kerf regions are diced.

Bump structural designs to minimize package defects

A method of forming a chip package includes providing a chip with a plurality of first bumps, wherein the plurality of first bumps has a first height. The method further includes providing a substrate with a plurality of second bumps, wherein the plurality of second bumps has a second height. The method further includes bonding the plurality of first bumps to the plurality of second bumps to form a first bump structure of the chip package, wherein the first bump structure has a standoff, wherein a ratio of a sum of the first height and the second height to the standoff is equal to or greater than about 0.6 and less than 1.

Semiconductor device and method of forming a curved image sensor

A semiconductor device has a semiconductor die containing a base material having a first surface and a second surface with an image sensor area. A masking layer with varying width openings is disposed over the first surface of the base material. The openings in the masking layer are larger in a center region of the semiconductor die and smaller toward edges of the semiconductor die. A portion of the first surface of the base material is removed by plasma etching to form a first curved surface. A metal layer is formed over the first curved surface of the base material. The semiconductor die is positioned over a substrate with the first curved surface oriented toward the substrate. Pressure and temperature is applied to assert movement of the base material to change orientation of the second surface with the image sensor area into a second curved surface.

DIRECT BOND METHOD PROVIDING THERMAL EXPANSION MATCHED DEVICES

A method of transferring an integrated circuit (IC) onto an alternative substrate is provided at a wafer level to enable coefficient of thermal expansion (CTE) matching for a circuit layer to a different material. The method is executable relative to a wafer with a circuit layer, a first major surface, a second major surface opposite the first major surface, and a substrate affixed to the first major surface. The method includes temporarily bonding a handle to the second major surface, removing a majority of the substrate to expose the first major surface and bonding a second substrate to the first major surface with deposited bonding material. 1. A wafer level integrated circuit (IC) transfer enabling structure , comprising:a circuit layer having a first major surface and a second major surface opposite the first major surface;a substrate remainder, which is substantially thinner than the circuit layer, affixed to the first major surface;a handle temporarily bonded to the second major surface; anda Sapphire substrate bonded to the first major surface and the substrate remainder with a deposited and polished bonding oxide.2. The structure according to claim 1 , wherein a thermoplastic adhesive temporarily bonds the handle to the second major surface.3. The structure according to claim 1 , wherein the circuit layer is approximately 10 μm thick.4. The structure according to claim 1 , wherein the circuit layer is approximately 10 μm thick and the Sapphire substrate is approximately 1500 μm thick. This application is a divisional of U.S. application Ser. No. 15/331,149 titled “DIRECT BOND METHOD PROVIDING THERMAL EXPANSION MATCHED DEVICES”, which was filed Oct. 21, 2016. The entire contents of U.S. application Ser. No. 15/331,149 are incorporated by reference herein.The present disclosure relates to a direct bond method and to a direct bond method that provides for thermal expansion matched devices for true heterogeneous three-dimensional integration.Many currently used ...

Stacked Integrated Circuit Structure and Method of Forming

A semiconductor device, and a method of forming the device, are provided. The semiconductor device includes a first die having a first plurality of contact pads and a second die having a second plurality of contact pads. A substrate is bonded to a first contact pad of the first plurality of contact pads and a first contact pad of the second plurality of contact pads in a face-to-face orientation with the first die and the second die. A first through via extends through the substrate. Molding material is interposed between the first die, the second die and the substrate, the molding material extending along sidewalls of the first die, the second die, and the substrate. A second through via is positioned over a second contact pad of the first plurality of contact pads, the second through via extending through the molding material. 1. A method comprising:positioning a first die and a second die on a carrier substrate;bonding a first substrate to the first die and the second die, the first substrate being connected in a face-to-face connection with the first die and the second die, the first substrate comprising a first through-substrate via;forming a molding material along sidewalls of the first die, the second die, and the first substrate, the molding material covering the first substrate;after forming the molding material, forming an opening in the molding material over the first die;forming a first through-mold via in the opening, wherein the first through-mold via extends through the molding material to the first die, surfaces of the first through-mold via, the molding material, the first substrate, and the first through-substrate via being planar after forming the first through-mold via;forming a first external connector over and directly contacting the first through-mold via, the first external connector comprising a first solder portion; andforming a second external connector over and directly contacting the first through-substrate via, the second external ...

Semiconductor device and semiconductor package

The present disclosure relates to bonding structures useful in semiconductor packages. In an embodiment, a semiconductor device includes a semiconductor element, two pillar structures, and an insulation layer. The semiconductor element has a surface and includes at least one bonding pad disposed adjacent to the surface. The two pillar structures are disposed on a single bonding pad. The insulation layer is disposed adjacent to the surface of the semiconductor element. The insulation layer defines an opening, the opening exposes a portion of the single bonding pad, and the two pillar structures are disposed in the opening.

PRINTED CIRCUIT BOARD (PCB), METHOD OF MANUFACTURING THE PCB, AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE USING THE PCB

Provided are a printed circuit board (PCB) capable of blocking introduction of impurities during a molding process so as to reduce damage on a semiconductor package, a method of manufacturing the PCB, and a method of manufacturing a semiconductor package by using the PCB. An embodiment includes an apparatus comprising: a substrate body comprising an active area and a dummy area on an outer portion of the active area, the substrate body extending lengthwise in a first direction; a plurality of semiconductor units mounted on the active area; and a barrier formed on the dummy area, wherein the barrier extends in the first direction. 1. An apparatus , comprising:a substrate body comprising an active area and a dummy area on an outer portion of the active area, the substrate body extending lengthwise in a first direction;a plurality of semiconductor units mounted on the active area; anda barrier formed on the dummy area,wherein the barrier extends in the first direction.2. The apparatus of claim 1 , wherein the barrier comprises at least one row of solder balls disposed on the dummy area.3. The apparatus of claim 1 , wherein the barrier comprises at least two rows of solder balls claim 1 , and solder balls of one of the at least two rows are offset in the first direction from solder balls in at least one other row of the at least two rows.4. The apparatus of claim 1 , wherein the barrier comprises at least two rows of solder balls claim 1 , and solder balls of one of the at least two rows are larger than solder balls in at least one other row of the at least two rows.5. The apparatus of claim 1 , wherein the barrier has a structure comprising at least one continuous wall or at least one row of separated walls.6. The apparatus of claim 1 , wherein:the barrier comprises at least one row of first solder balls; andthe substrate body further comprises second solder balls disposed on the active area; andheights of the first solder balls from an upper surface of the substrate ...

CHIP CARRIER AND METHOD THEREOF

A method may include providing a chip carrier having a chip supporting region to support a chip, and a chip contacting region having at least one contact pad, the chip carrier being thinner in the chip contacting region such that a first thickness of the chip carrier at the at least one contact pad is smaller than a second thickness of the chip carrier in the chip supporting region. A disposing of the chip, having at least one contact protrusion, over the chip carrier, such that the at least one contact protrusion is arranged over the at least one contact pad may be included. In addition, a pressing of the chip against the chip carrier such that the at least one contact protrusion extends at least partially into the chip contacting region and is electrically contacted to the at least one contact pad may be included. 1. A method , comprising: a chip supporting region configured to support a chip, and', 'a chip contacting region having at least one contact pad configured to electrically contact the chip,', 'the chip carrier being thinner in the chip contacting region such that a first thickness of the chip carrier at the at least one contact pad is smaller than a second thickness of the chip carrier in the chip supporting region;, 'providing a chip carrier, the chip carrier including'}disposing the chip including at least one contact protrusion over the chip carrier, such that the at least one contact protrusion is arranged over the at least one contact pad; andpressing the chip against the chip carrier such that the at least one contact protrusion extends at least partially into the chip contacting region and is electrically contacted to the at least one contact pad.2. The method of claim 1 ,wherein pressing the chip against the chip carrier includes displacing the at least one contact pad by deforming the chip carrier to form a recess for receiving the at least one contact protrusion.3. The method of claim 1 ,wherein pressing the chip against the chip carrier is ...

SEMICONDUCTOR DEVICE AND METHOD OF FORMING WLCSP

A semiconductor substrate contains a plurality of semiconductor die with a saw street between the semiconductor die. A plurality of bumps is formed over a first surface of the semiconductor die. An insulating layer is formed over the first surface of the semiconductor die between the bumps. A portion of a second surface of the semiconductor die is removed and a conductive layer is formed over the remaining second surface. The semiconductor substrate is disposed on a dicing tape, the semiconductor substrate is singulated through the saw street while maintaining position of the semiconductor die, and the dicing tape is expanded to impart movement of the semiconductor die and increase a space between the semiconductor die. An encapsulant is deposited over the semiconductor die and into the space between the semiconductor die. A channel is formed through the encapsulant between the semiconductor die to separate the semiconductor die. 1. A method of making a semiconductor device , comprising:providing a semiconductor substrate including a plurality of semiconductor die with a saw street between the semiconductor die;forming a plurality of bumps over a first surface of the semiconductor die;forming an insulating layer over the first surface of the semiconductor die between the bumps;singulating the semiconductor substrate through removing substrate material through an entire thickness of the semiconductor substrate in the saw street;moving the semiconductor die to increase a space between the semiconductor die;depositing an encapsulant over the semiconductor die and into the space between the semiconductor die; andforming a channel through the encapsulant between the semiconductor die to separate the semiconductor die.2. The method of claim 1 , wherein removing the substrate material further comprises removing the substrate material using a saw blade.3. The method of claim 1 , further including depositing the encapsulant over a portion of the first surface of the ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

In a semiconductor device (SP) according to an embodiment, a solder resist film (first insulating layer, SR) which is in contact with the base material layer, and a resin body (second insulating layer, ) which is in contact with the solder resist film and the semiconductor chip, are laminated in between the base material layer (CR) of a wiring substrate and a semiconductor chip (). In addition, a linear expansion coefficient of the solder resist film is equal to or larger than a linear expansion coefficient of the base material layer, and the linear expansion coefficient of the solder resist film is equal to or smaller than a linear expansion coefficient of the resin body. Also, the linear expansion coefficient of the base material layer is smaller than the linear expansion coefficient of the resin body. According to the above-described configuration, damage of the semiconductor device caused by a temperature cyclic load can be suppressed, and thereby reliability can be improved. 1. A semiconductor device comprising:a wiring substrate including a base material layer, a terminal formed on a first surface of the base material layer, and an insulating layer formed on the first surface such that the insulating film covers a first portion of the terminal, and such that the insulating film exposes a second portion of the terminal;a semiconductor chip including a front surface, a bonding pad formed on the front surface, and a projecting electrode formed on the bonding pad, and mounted over the wiring substrate such that the front surface faces the first surface of the wiring substrate via the projecting electrode;a solder material located between the second portion of the terminal and the projecting electrode; anda resin body located between the wiring substrate and the semiconductor chip, and sealing a connection part between the projecting electrode and the terminal,wherein the insulating film has an opening in which the second portion of the terminal is exposed,wherein, ...

Imaging apparatus, imaging display system, and display apparatus

An imaging apparatus includes: a substrate; and a plurality of device sections each including a photoelectric converter and disposed on the substrate to be spaced from one another and to collectively form a concave shape.

Semiconductor package and method of fabricating the same

Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a first redistribution substrate and a first semiconductor device on the first redistribution substrate. The first redistribution substrate includes a first dielectric layer that includes a first hole, an under-bump that includes a first bump part in the first hole and a second bump part that protrudes from the first bump part onto the first dielectric layer, an external connection terminal on a bottom surface of the first dielectric layer and connected to the under-bump through the first hole, a wetting layer between the external connection terminal and the under-bump, and a first barrier/seed layer between the under-bump and the first dielectric layer and between the under-bump and the wetting layer.

Semiconductor package

A semiconductor package includes a redistribution substrate having a semiconductor chip mounted on a top surface thereof with and a connection terminal between the semiconductor chip and the redistribution substrate. The redistribution substrate includes a first redistribution pattern on a bottom surface of the connection terminal and comprising a first via and a first interconnection on the first via, a pad pattern between the first redistribution pattern and the connection terminal and comprising a pad via and a pad on the pad via, and a second redistribution pattern between the first redistribution pattern and the pad pattern and comprising a second via and a second interconnection on the second via with a recess region where a portion of a top surface of the second interconnection is recessed. A bottom surface of the recess region is located at a lower level than a topmost surface of the second interconnection.

INTEGRATED CIRCUIT PACKAGE COMPRISING SURFACE CAPACITOR AND GROUND PLANE

Many aspects of an IC package are disclosed. The IC package includes a substrate, an integrated circuit die, a vertical capacitor and a conductive layer. The substrate includes a first plurality of substrate pads. The integrated circuit die is coupled to the first plurality of substrate pads embedded in a first layer of the substrate. The vertical capacitor has a first electrode, a second electrode and a first resistive layer. The first electrode is coupled to the first resistive layer. The first resistive layer is coupled to a first substrate pad embedded in the first layer of the substrate. The conductive layer is formed over a first surface and the second electrode of the vertical capacitor. The conductive layer encapsulates the vertical capacitor. The first and second electrodes are parallel to each other and perpendicular to a planar surface of the substrate. 1. A method for manufacturing an integrated circuit package comprising:providing a substrate having a plurality of build-up layers;providing a vertical capacitor;attaching a first electrode of the vertical capacitor to a first substrate pad embedded in a first layer of the plurality of build-up layers of the substrate;forming a conductive layer on a portion of the first layer of the plurality of build-up layers of the substrate and on a second electrode of the vertical capacitor, wherein the conductive layer encapsulates the vertical capacitor; andattaching an integrated circuit die to a first plurality of substrate pads embedded in the first layer of the substrate.2. The method of claim 1 , wherein the first and second electrodes of the vertical capacitor are perpendicularly located to a planar surface of the substrate.3. The method of claim 1 , wherein the substrate has a thickness range of 160-190 microns.4. The method of claim 1 , wherein the substrate has a thickness of 176 microns.5. The method of claim 1 , wherein the vertical capacitor has a width of 0.5 millimeter and a thickness range of 0.1-0.2 ...

Semiconductor device including tsv and semiconductor package including the same

Provided are a semiconductor device, a method of manufacturing the same, and a semiconductor package including the same. The semiconductor device includes: a substrate having a recess region in a predetermined portion of a back side of the substrate; a wiring part disposed on a front side of the substrate and including at least one wiring layer; an insulating layer disposed on the back side of the substrate and including a first portion filling in the recess region and a second portion covering the back side of the substrate of a non-recess region other than the recess region; and a through silicon via (TSV) provided in plurality of and penetrating the first portion to be electrically connected to the at least one wiring layer.

Chip packages and methods of manufacture thereof

Chip packages and methods of manufacture thereof are described. In an embodiment, a method for manufacturing a chip package may include: providing a support structure including: a base; and a stage pivotably attached to the base, the stage having a surface facing away from the base; attaching a first die having at least one second die disposed thereon to the surface of the stage; pivotably tilting the stage; and after the pivotably tilting, dispensing an underfill over the first die and adjacent to the least one second die, the underfill flowing through a first standoff gap disposed between the first die and the at least one second die.

Semiconductor chip, display panel, and electronic device

A semiconductor chip, a display device or an electronic device includes a substrate, one or more conductive pads disposed on the substrate, and one or more bumps electrically connected to the one or more conductive pads, in which the one or more bumps includes a metal core, a polymer layer disposed over a surface of the metal core, and a conductive coating layer disposed over a surface of the polymer layer and electrically connected to the one or more conductive pads.

Chip carrier, a device and a method

According to various embodiments, a chip carrier may include: a chip supporting region configured to support a chip; a chip contacting region including at least one contact pad for electrically contacting the chip; wherein the chip carrier is thinned in the chip contacting region such that a first thickness of the chip carrier at the at least one contact pad is smaller than a second thickness of the chip carrier in the chip supporting region.

Semiconductor Device and Method of Forming Interconnect Structure and Mounting Semiconductor Die in Recessed Encapsulant

A semiconductor device has conductive pillars formed over a carrier. A first semiconductor die is mounted over the carrier between the conductive pillars. An encapsulant is deposited over the first semiconductor die and carrier and around the conductive pillars. A recess is formed in a first surface of the encapsulant over the first semiconductor die. The recess has sloped or stepped sides. A first interconnect structure is formed over the first surface of the encapsulant. The first interconnect structure follows a contour of the recess in the encapsulant. The carrier is removed. A second interconnect structure is formed over a second surface of the encapsulant and first semiconductor die. The first and second interconnect structures are electrically connected to the conductive pillars. A second semiconductor die is mounted in the recess. A third semiconductor die is mounted over the recess and second semiconductor die. 1. A semiconductor device , comprising:a first semiconductor die;a first interconnect structure;an encapsulant deposited over the first semiconductor die and first interconnect structure; anda second interconnect structure disposed over the first semiconductor die, encapsulant, and first interconnect structure.2. The semiconductor device of claim 1 , wherein the first interconnect structure extends through the encapsulant.3. The semiconductor device of claim 1 , further including a second semiconductor die disposed over the first semiconductor die with the second semiconductor die electrically connected to the second interconnect structure through the first interconnect structure.4. The semiconductor device of claim 1 , wherein the first semiconductor die includes an electrical component and a mechanical component.5. The semiconductor device of claim 1 , wherein the first interconnect structure includes a conductive pillar or conductive via.6. The semiconductor device of claim 1 , further including a conductive layer formed over the first ...

Structure and formation method of chip package with fan-out feature

A package structure and a formation method of a package structure are provided. The method includes forming a conductive structure over a carrier substrate and disposing a semiconductor die over the carrier substrate. The method also includes forming a protective layer to surround the conductive structure and the semiconductor die. The method further includes forming an insulating layer over the protective layer. The insulating layer has an opening exposing a portion of the conductive structure. In addition, the method includes forming a conductive layer over the insulating layer. The conductive layer fills the opening, and the conductive layer has a substantially planar top surface.

Semiconductor package

A semiconductor package including a package substrate, a semiconductor chip on a top surface of the package substrate, a connection terminal between the package substrate and the semiconductor chip, the connection terminal connecting the package substrate to the semiconductor chip, a non-conductive film (NCF) between the package substrate and semiconductor chip, the NCF surrounding the connection terminal and bonding the semiconductor chip to the package substrate, and a side encapsulation material covering a side surface of the semiconductor chip, contacting the package substrate, and including a first portion between a bottom surface of the semiconductor chip and the top surface of the package substrate may be provided. At least a portion of the NCF includes a second portion that horizontally protrudes from the semiconductor chip when viewed, and a portion of the side encapsulation material is in contact with the bottom surface of the semiconductor chip.

Bonded assembly and display device including the same

A bonded assembly including: a first electronic component including a first substrate and a plurality of first electrodes disposed in a pressed area at a first height from a surface of the first substrate; a second electronic component including a second substrate and a plurality of second electrodes disposed at a second height from a surface of the second substrate, a second electrode overlapping with a corresponding first electrode to face the first electrode; a conductive bonding layer disposed between the first electrode and the second electrode overlapped with each other to bond the first electrode and the second electrode; and at least one spacer disposed between the first substrate and the second substrate to overlap the pressed area, the at least one spacer having a thickness that is greater than a value obtained by summing the first height and the second height.

Semiconductor Device and Method of Self-Confinement of Conductive Bump Material During Reflow Without Solder Mask

A semiconductor device has a semiconductor die with a die bump pad and substrate with a trace line and integrated bump pad. Conductive bump material is deposited on the substrate bump pad or die bump pad. The semiconductor die is mounted over the substrate so that the bump material is disposed between the die bump pad and substrate bump pad. The bump material is reflowed without a solder mask around the die bump pad or substrate bump pad to form an interconnect. The bump material is self-confined within a footprint of the die bump pad or substrate bump pad. The bump material can be immersed in a flux solution prior to reflow to increase wettability. Alternatively, the interconnect includes a non-fusible base and fusible cap. The volume of bump material is selected so that a surface tension maintains self-confinement of the bump material within the bump pads during reflow.

Die-on-Interposer Assembly with Dam Structure and Method of Manufacturing the Same

A semiconductor package includes an interposer chip having a frontside, a backside, and a corner area on the backside defined by a first corner edge and a second corner edge of the interposer chip. A die is bonded to the frontside of the interposer chip. At least one dam structure is formed on the corner area of the backside of the interposer chip. The dam structure includes an edge aligned to at least one the first corner edge and the second corner edge of the interposer chip. 1. A package comprising:a substrate having a frontside and a backside, the substrate comprising four corner areas;a die bonded to the frontside of the substrate by a first set of conductive connectors;a molding layer on the frontside of the substrate and surrounding sidewalls of the die;a dam structure in each of the four corner areas on the backside of the substrate, each of the dam structures being at least a part of a circle in a plane parallel to the backside of the substrate; anda second set of conductive connectors on the backside of the substrate.2. The package of further comprising:a through via extending through the substrate, at least one of the second set of conductive connectors being electrically coupled to the through via; andan interconnect structure formed on the frontside of the substrate and electrically coupled to the through via, the die being electrically coupled to the interconnect structure.3. The package of claim 1 , wherein each of the dam structures comprise an edge aligned with an outer edge of the substrate.4. The package of claim 1 , wherein the dam structures comprise a polymer material.5. The package of claim 1 , wherein the molding layer comprises a polymer.6. The package of claim 1 , wherein the dam structures are not electrically coupled to the through via.7. The package of claim 1 , wherein a first corner area of the four corner areas is defined by a first corner edge and a second corner edge of the substrate claim 1 , an intersection of the first corner ...

STRUCTURE FOR STACKED LOGIC PERFORMANCE IMPROVEMENT

In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a plurality of interconnect layers within an inter-level dielectric (ILD) structure disposed along a front-side of a substrate. A dielectric layer is arranged along a back-side of the substrate and a conductive bond pad is separated from the substrate by the dielectric layer. A back-side through-substrate-via (BTSV) extends through the substrate and the dielectric layer. A conductive bump is arranged over the conductive bond pad. The conductive bond pad has a substantially planar lower surface extending from over the BTSV to below the conductive bump. A BTSV liner separates sidewalls of the BTSV from the substrate. The sidewalls of the BTSV directly contact sides of both the BTSV liner and the dielectric layer. 1. An integrated chip , comprising:a plurality of interconnect layers within an inter-level dielectric (ILD) structure disposed along a front-side of a substrate;a dielectric layer arranged along a back-side of the substrate;a conductive bond pad separated from the substrate by the dielectric layer;a back-side through-substrate-via (BTSV) extending through the substrate and the dielectric layer;a conductive bump arranged over the conductive bond pad, wherein the conductive bond pad has a substantially planar lower surface extending from over the BTSV to below the conductive bump; anda BTSV liner separating sidewalls of the BTSV from the substrate, wherein the sidewalls of the BTSV directly contact sides of both the BTSV liner and the dielectric layer.2. The integrated chip of claim 1 , wherein the sidewalls of the BTSV directly contact the sides of both the BTSV liner and the dielectric layer at positions that are vertically between the back-side of the substrate and the substantially planar lower surface of the conductive bond pad.3. The integrated chip of claim 1 ,wherein the plurality of interconnect layers comprise a first interconnect wire and a ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device includes a substrate, a package, first conductors and second conductors. The substrate includes a first surface and a second surface opposite to the first surface. The package is disposed over the substrate. The first conductors are disposed over the substrate. The second conductors are disposed over the substrate, wherein the first conductors and the second conductors are substantially at a same tier, and a width of the second conductor is larger than a width of the first conductor. 1. A semiconductor device , comprising:a substrate including a first surface and a second surface opposite to the first surface;a package over the substrate;a plurality of first conductors over the substrate;a plurality of second conductors over the substrate, wherein the plurality of first conductors and the plurality of the second conductors are substantially at a same tier, and a width of a second conductor of the plurality of second conductors is larger than a width of a first conductor of the plurality of first conductors;a plurality of first bonding pads on the substrate and configured to receive and electrically connect to the plurality of first conductors, respectively;a plurality of second bonding pads on the substrate and configured to receive and electrically connect to the plurality of second conductors, respectively; anda passivation layer over the substrate, wherein the passivation layer includes a plurality of first recesses exposing the plurality of first bonding pads respectively, and a plurality of second recesses exposing the plurality of second bonding pads respectively, and a width of the first recess is wider than a width of the second recess, wherein the first conductor is apart from an edge of the respective first recess, and the second conductor is in contact with an edge of the respective second recess.2. The semiconductor device of claim 1 , wherein a volume of a second conductor of the plurality of second conductors is substantially ...

Semiconductor Device and Method of Forming a POP Device with Embedded Vertical Interconnect Units

A semiconductor device has a substrate. A plurality of conductive vias is formed through the substrate. A conductive layer is formed over the substrate. An insulating layer is formed over conductive layer. A portion of the substrate is removed to expose the conductive vias. A plurality of vertical interconnect structures is formed over the substrate. A first semiconductor die is disposed over the substrate. A height of the vertical interconnect structures is less than a height of the first semiconductor die. An encapsulant is deposited over the first semiconductor die and the vertical interconnect structures. A first portion of the encapsulant is removed from over the first semiconductor die while leaving a second portion of the encapsulant over the vertical interconnect structures. The second portion of the encapsulant is removed to expose the vertical interconnect structures. A second semiconductor die is disposed over the first semiconductor die. 1. A semiconductor device , comprising:a substrate including a conductive via formed through the substrate;a modular interconnect unit including a vertical interconnect structure disposed over the substrate;a first semiconductor die disposed over the substrate adjacent to the modular interconnect unit; andan encapsulant deposited around the first semiconductor die and over modular interconnect unit with an opening in the encapsulant extending to the modular interconnect unit.2. The semiconductor device of claim 1 , further including a second semiconductor die disposed over the first semiconductor die with a bump of the second semiconductor die within the opening of the encapsulant to contact the vertical interconnect structure.3. The semiconductor device of claim 1 , further including a first interconnect structure disposed between the substrate and modular interconnect unit.4. The semiconductor device of claim 3 , further including a second interconnect structure disposed between the first interconnect structure and ...

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A mechanism of a semiconductor structure with composite barrier layer under redistribution layer is provided. A semiconductor structure includes a substrate comprising a top metal layer on the substrate; a passivation layer over the top metal layer having an opening therein exposing the top metal layer; a composite barrier layer over the passivation layer and the opening, the composite barrier layer includes a center layer, a bottom layer, and an upper layer, wherein the bottom layer and the upper layer sandwich the center layer; and a redistribution layer (RDL) over the composite barrier layer and electrically connecting the underlying top metal layer. 1. A semiconductor structure comprising:a metal layer;a passivation layer over the metal layer;a composite barrier layer in a recess that extends into the metal layer through the passivation layer; anda redistribution layer (RDL) over the composite barrier layer.2. The semiconductor structure of claim 1 , wherein the composite barrier layer comprises:a bottom layer in contact with metal layer; anda center layer over the bottom layer.3. The semiconductor structure of claim 2 , wherein the composite barrier layer further comprises an upper layer over the center layer.4. The semiconductor structure of claim 2 , wherein the bottom layer includes a first portion claim 2 , a second portion above the first portion claim 2 , and a third portion between the first and second portions.5. The semiconductor structure of claim 1 , wherein an external portion of the composite barrier layer is in contact with a surface of the passivation layer outside of the recess.6. The semiconductor structure of claim 5 , wherein the external portion of the composite barrier layer is between the RDL and the passivation layer.7. The semiconductor structure of claim 1 , wherein the metal layer comprises a different material than the RDL.8. A semiconductor structure comprising:a passivation layer having a recess therein; a bottom layer; and', 'a ...

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure includes a substrate including a first surface and a second surface opposite to the first surface; a dielectric layer disposed over the second surface or below the first surface; a polymeric layer disposed over or below the dielectric layer; an isolation layer surrounding and contacted with the substrate, the dielectric layer and the polymeric layer; a die disposed over the polymeric layer; a first conductive bump disposed below the first surface of the substrate; and a second conductive bump disposed between the second surface of the substrate and the die. 1. A semiconductor structure , comprising:a substrate including a first surface and a second surface opposite to the first surface;a dielectric layer disposed over the second surface or below the first surface;a polymeric layer disposed over or below the dielectric layer;an isolation layer surrounding and contacted with the substrate, the dielectric layer and the polymeric layer;a die disposed over the polymeric layer;a first conductive bump disposed below the first surface of the substrate; anda second conductive bump disposed between the second surface of the substrate and the die.2. The semiconductor structure of claim 1 , wherein the isolation layer surrounds and contacts with sidewalls of the substrate claim 1 , the dielectric layer and the polymeric layer.3. The semiconductor structure of claim 2 , wherein the isolation layer entirely covers the sidewalls of the substrate claim 2 , the dielectric layer and the polymeric layer.4. The semiconductor structure of claim 2 , wherein the sidewalls of the substrate claim 2 , the dielectric layer and the polymeric layer are substantially coplanar with each other.5. The semiconductor structure of claim 1 , wherein an interface between the isolation layer claim 1 , the substrate claim 1 , the dielectric layer and the polymeric layer is substantially orthogonal to the first surface or the second surface of the substrate.6. The semiconductor ...

PACKAGE STRUCTURE AND METHODS OF FORMING THE SAME

Embodiments relate to packages and methods of forming packages. A package includes a package substrate, a first device die, first electrical connectors, an encapsulant, a redistribution structure, and a second device die. The first device die is attached to a side of the package substrate, and the first electrical connectors are mechanically and electrically coupled to the side of the package substrate. The encapsulant at least laterally encapsulates the first electrical connectors and the first device die. The redistribution structure is on the encapsulant and the first electrical connectors. The redistribution structure is directly coupled to the first electrical connectors. The first device die is disposed between the redistribution structure and the package substrate. The second device die is attached to the redistribution structure by second electrical connectors, and the second electrical connectors are directly coupled to the redistribution structure. 1. A package comprising:a first redistribution structure disposed on a front side of a substrate;a first semiconductor device disposed on the first redistribution structure, the first semiconductor device electrically connected to the first redistribution structure;a first encapsulant laterally surrounding the first semiconductor device;a second redistribution structure over and physically contacting a top surface of the first semiconductor device;an electrical connector extending through the first encapsulant from the first redistribution structure to the second redistribution structure, wherein a top surface of the electrical connector is level with the top surface of the first semiconductor device; anda second semiconductor device disposed on the second redistribution structure, the second semiconductor device electrically connected to the second redistribution structure.2. The package of claim 1 , further comprising a third semiconductor device disposed on the second redistribution structure claim 1 , the ...

Three-dimensional memory device having bonding structures connected to bit lines and methods of making the same

Three-dimensional memory devices in the form of a memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack, in which each of the memory stack structures includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. Bit lines are electrically connected to an end portion of a respective one of the vertical semiconductor channels. Bump connection via structures contact a top surface of a respective one of the bit lines, in which each of the bump connection via structures has a greater lateral dimension along a lengthwise direction of the bit lines than along a widthwise direction of the bit lines. Metallic bump structures of another semiconductor die contact respective ones of the bump connection via structures to make respective electrical connections between the two dies.

POST-PASSIVATION INTERCONNECT STRUCTURE

A semiconductor device includes a semiconductor substrate, a passivation layer overlying the semiconductor substrate, and an interconnect structure overlying the passivation layer. The interconnect structure includes a landing pad region and a dummy region electrically separated from each other. A protective layer is formed on the interconnect structure and has a first opening exposing a portion of the landing pad region and a second opening exposing a portion of the dummy region. A metal layer is formed on the exposed portion of landing pad region and the exposed portion of the dummy region. A bump is formed on the metal layer overlying the landing pad region. 1. A semiconductor device , comprising:a semiconductor substrate comprising circuitry and a plurality of metal layers formed between dielectric layers operable to route electrical signals formed therein;a passivation layer overlying the semiconductor substrate;an interconnect structure overlying and interfacing a top surface of the passivation layer,the interconnect structure comprising a landing pad conductive element and a plurality of dummy conductive elements, wherein the landing pad conductive element and the dummy conductive elements are electrically separated;a protective layer overlying the interconnect structure and comprising a first opening exposing a portion of the landing pad conductive element and a second opening exposing a portion of each of the plurality of dummy conductive elements;a metal layer comprising a first portion on a topmost surface of the protective layer and on the exposed portion of the landing pad conductive element and a plurality of second portions on the topmost surface of the protective layer and on the exposed portion of the dummy conductive element, the plurality of second portions of the metal layer being electrically separated from the semiconductor substrate and from the first portion of the metal layer; anda single bump on the first portion of the metal layer ...

Semiconductor Device with Encapsulant Deposited Along Sides and Surface Edge of Semiconductor Die in Embedded WLCSP

A semiconductor device has a semiconductor wafer including a plurality of semiconductor die. An insulating layer is formed over the semiconductor wafer. A portion of the insulating layer is removed by LDA to expose a portion of an active surface of the semiconductor die. A first conductive layer is formed over a contact pad on the active surface of the semiconductor die. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is disposed over a carrier with the active surface of the semiconductor die offset from the carrier. An encapsulant is deposited over the semiconductor die and carrier to cover a side of the semiconductor die and the exposed portion of the active surface. An interconnect structure is formed over the first conductive layer. Alternatively, a MUF material is deposited over a side of the semiconductor die and the exposed portion of the active surface. 1. A method of making a semiconductor device , comprising:providing a semiconductor die;forming a redistribution layer over the semiconductor die; anddepositing an encapsulant over the semiconductor die and redistribution layer after forming the redistribution layer.2. The method of claim 1 , further including depositing the encapsulant over a side surface of the semiconductor die.3. The method of claim 1 , further including depositing the encapsulant over a back surface of the semiconductor die.4. The method of claim 1 , further including disposing a solder bump on the redistribution layer after depositing the encapsulant.5. The method of claim 1 , further including:disposing the semiconductor die on a carrier with the redistribution layer oriented toward the carrier; anddepositing the encapsulant over the semiconductor die and carrier.6. The method of claim 1 , further including singulating through the encapsulant to form a wafer-level chip scale package including the semiconductor die.7. A method of making a semiconductor device claim 1 , comprising:providing ...

Package on package structure and method of manufacturing the same

A package on package structure includes a first substrate having a first region and a second region, a bump formed on the first region of the first substrate, a first semiconductor die bonded to the second region of the first substrate, and a semiconductor die package bonded to the first substrate. The bump includes a metallic structure and a plurality of minor elements dispersed in the metallic structure. The semiconductor die package includes a connector bonded to the bump, and the first semiconductor die is between the semiconductor die package and the first substrate.

SEMICONDUCTOR DEVICE

A semiconductor device includes a substrate, a plurality of pads disposed over the substrate, and a solder mask disposed over the substrate. The substrate includes a pair of first edges parallel to each other, a pair of second edges orthogonal to the pair of first edges, and a center point. The solder mask includes four recess portions exposing an entire top surface and sidewalls of four of the pads in four corners of the regular array, and a plurality of second recess portions exposing a portion of a top surface of other pads in the regular array. A pad size of the four pads in the four corners of the regular array exposed through the first recess portions and a pad size of the other pads exposed through the second recess portions are the same. 2. The semiconductor device of claim 1 , wherein the plurality of pads comprise four non-solder mask defined (NSMD) pads in the four corners of the regular array and a plurality of solder mask defined (SMD) pads disposed away from the four corners of the regular array.3. The semiconductor of claim 2 , wherein each of the four NSMD pads is adjacent to one of the SMD pads in a same horizontal row and another one of the SMD pads in a same vertical column.4. The semiconductor device of claim 1 , wherein the first vertical distances are similar to the second vertical distances.5. The semiconductor device of claim 1 , wherein the first vertical distances are different from the second vertical distances.6. The semiconductor device of claim 1 , wherein a first distance is defined as a distance between the center point and each of the four first recess portions claim 1 , and the first distance is greater than at least one of the first vertical distance and the second vertical distance.7. The semiconductor device of claim 6 , wherein a second distance is defined as a distance between the center point and each of the second recess portions claim 6 , and the second distance is less than the first vertical distance and the second ...

Wafer level integration including design/co-design, structure process, equipment stress management and thermal management

A multi-layer wafer and method of manufacturing such wafer are provided. The method comprises applying at least one stress compensating polymer layer to at least one of two heterogeneous wafers and low temperature bonding the two heterogeneous wafers to bond the stress compensating polymer layer to the other of the two heterogeneous wafers to form a multi-layer wafer pair. The multi-layer wafer comprises two heterogeneous wafers, at least one of the heterogeneous wafers having a stress compensating polymer layer. The two heterogeneous wafers are low temperature bonded together to bond the stress compensating polymer layer to the other of the two heterogeneous wafers.

Semiconductor structure and manufacturing method thereof

A semiconductor structure includes a substrate; a pad disposed over the substrate; a first passivation disposed over the substrate, partially covering the pad, and including a protrusion protruded from the first passivation and away from the substrate; a conductive layer disposed over the first passivation and a portion of the pad exposed from the first passivation; and a second passivation disposed over the conductive layer, wherein the conductive layer disposed over the protrusion is exposed from the second passivation.

SEMICONDUCTOR DEVICE

A semiconductor device includes a substrate including a surface, a plurality of pads disposing on the surface of the substrate, the plurality of pads includes a non-solder mask defined (NSMD) pad and a solder mask defined (SMD) pad, and the NSMD pad is arranged at a predetermined location. Further, a method of manufacturing a semiconductor device includes providing a substrate, disposing a plurality of pads on a surface of the substrate, disposing a solder mask over the surface of the substrate and the plurality of pads, forming a first recess in the solder mask to surround one of the plurality of pads, and forming a second recess in the solder mask and above one of the plurality of pads. 2. The semiconductor device of claim 1 , wherein the plurality of pads are arranged in a regular array including a plurality of horizontal rows and a plurality of vertical columns.3. The semiconductor device of claim 1 , wherein the plurality of pads comprise a plurality of non-solder mask defined (NSMD) pads and a plurality of solder mask defined (SMD) pads.4. The semiconductor of claim 3 , wherein the first recess portion entirely exposes one of the NSMD pads claim 3 , and the second recess portion partially exposes one of the SMD pads.5. The semiconductor device of claim 1 , wherein first recess portion is disposed on a corner of the semiconductor device and the second recess portion is disposed away from the corner of the semiconductor device.6. The semiconductor device of claim 1 , wherein the first distance between the central point and the first edge is greater than a fourth distance between the central point and the second recess portion claim 1 , and the second distance between the central point and the second edge is greater than the fourth distance between the central point and the second recess portion.7. A semiconductor device claim 1 , comprising:a substrate comprising a pair of first edges parallel to each other, a pair of second edges orthogonal to the first edge, ...

WAFER LEVEL INTEGRATION INCLUDING DESIGN/CO-DESIGN, STRUCTURE PROCESS, EQUIPMENT STRESS MANAGEMENT AND THERMAL MANAGEMENT

A multi-layer wafer and method of manufacturing such wafer are provided. The method comprises creating under bump metallization (UMB) pads on each of the two heterogeneous wafers; applying a conductive means above the UMB pads on at least one of the two heterogeneous wafers; and low temperature bonding the two heterogeneous wafers to adhere the UMB pads together via the conductive means. At least one stress compensating polymer layer may be applied to at least one of two heterogeneous wafers. The multi-layer wafer comprises two heterogeneous wafers, each of the heterogeneous wafer having UMB pads and at least one of the heterogeneous wafers having a stress compensating polymer layer and a conductive means applied above the UMB pads on at least one of the two heterogeneous wafers. The two heterogeneous wafers low temperature bonded together to adhere the UMB pads together via the conductive means. 115-. (canceled)16. A multi-layer wafer comprising:two heterogeneous wafers, each of the heterogeneous wafer having under bump metallization pads and at least one of the heterogeneous wafers having one of a stress compensating or adhesive polymer layer; anda conductive means applied above the under bump metallization pads on at least one of the two heterogeneous wafers;the two heterogeneous wafers low temperature bonded together to adhere the under bump metallization pads together via the conductive means to form a multi-layer wafer pair.17. The multi-layer wafer of claim 16 , wherein the conductive means is one of solder balls claim 16 , conductive paste claim 16 , or solder topped copper pillars.18. The multi-layer wafer of claim 16 , wherein the conductive means is formed from one of In claim 16 , InSn claim 16 , InBi claim 16 , Sn alloys claim 16 , other high Sn solder alloys claim 16 , Pb claim 16 , PbSn claim 16 , other high lead alloys claim 16 , Cu claim 16 , Ni claim 16 , Au claim 16 , Ag claim 16 , Pt claim 16 , Pd claim 16 , or combinations therein that can be ...

SHAPED AND ORIENTED SOLDER JOINTS

The present description relates to the field of fabricating microelectronic assemblies, wherein a microelectronic device may be attached to a microelectronic substrate with a plurality of shaped and oriented solder joints. The shaped and oriented solder joints may be substantially oval, wherein the major axis of the substantially oval solder joints may be substantially oriented toward a neutral point or center of the microelectronic device. Embodiments of the shaped and oriented solder joint may reduce the potential of solder joint failure due to stresses, such as from thermal expansion stresses between the microelectronic device and the microelectronic substrate. 1. An apparatus , comprising:a microelectronic device; anda plurality of interconnects disposed on the microelectronic device, wherein the plurality of interconnects includes a plurality of substantially oval solder bumps which are radially oriented by a major axis thereof toward a neutral point of the microelectronic device, wherein the plurality of interconnects includes a plurality conductive pillars and wherein the substantially oval solder bumps are disposed on the plurality of conductive pillars.2. The apparatus of claim 1 , wherein the plurality of conductive pillars comprises a copper-containing material.3. The apparatus of claim 1 , wherein the microelectronic device includes a microelectronic die and wherein the plurality of substantially oval solder bumps reside outside a periphery of the microelectronic die.4. The apparatus of claim 1 , wherein the substantially oval solder bumps comprises a lead/tin solder.5. The apparatus of claim 1 , wherein the substantially oval solder bumps comprise a lead-free solder.6. An apparatus claim 1 , comprising:a microelectronic device; anda plurality of interconnects disposed on the microelectronic device, wherein the plurality of interconnect includes a plurality of substantially oval solder bumps which are grouped into zones, wherein each of the substantially ...

Semiconductor package and method of manufacturing the semiconductor package

Embodiments of the inventive concept include a semiconductor package having a plurality of stacked semiconductor chips. A multi-layered substrate includes a central insulation layer, an upper wiring layer disposed on an upper surface of the central insulation layer, and a first lower wiring layer disposed on a lower surface of the central insulation layer. The stacked semiconductor chips are connected to the multi-layered substrate and/or each other using various means. The semiconductor package is capable of high performance operation, like a semiconductor package based on flip-ship bonding, and also meets the need for large capacity by overcoming a limitation caused by a single semiconductor chip. Embodiments of the inventive concept also include methods of manufacturing the semiconductor package.

Semiconductor device and method of forming micro interconnect structures

A semiconductor device has a first semiconductor die and second semiconductor die with a conductive layer formed over the first semiconductor die and second semiconductor die. The second semiconductor die is disposed adjacent to the first semiconductor die with a side surface and the conductive layer of the first semiconductor die contacting a side surface and the conductive layer of the second semiconductor die. An interconnect, such as a conductive material, is formed across a junction between the conductive layers of the first and second semiconductor die. The conductive layer may extend down the side surface of the first semiconductor die and further down the side surface of the second semiconductor die. An extension of the side surface of the first semiconductor die can interlock with a recess of the side surface of the second semiconductor die. The conductive layer extends over the extension and into the recess.

Semiconductor device and method of forming cantilevered protrusion on a semiconductor die

A semiconductor device has a first semiconductor die with a base material. A covering layer is formed over a surface of the base material. The covering layer can be made of an insulating material or metal. A trench is formed in the surface of the base material. The covering layer extends into the trench to provide the cantilevered protrusion of the covering layer. A portion of the base material is removed by plasma etching to form a cantilevered protrusion extending beyond an edge of the base material. The cantilevered protrusion can be formed by removing the base material to the covering layer, or the cantilevered protrusion can be formed within the base material under the covering layer. A second semiconductor die is disposed partially under the cantilevered protrusion. An interconnect structure is formed between the cantilevered protrusion and second semiconductor die.

Semiconductor Device and Method of Forming Patterned Repassivation Openings Between RDL and UBM to Reduce Adverse Effects of Electro-Migration

A semiconductor device has a semiconductor wafer with a first conductive layer formed over a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and first conductive layer. A second conductive layer is formed over the first insulating layer and first conductive layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A plurality of openings is formed in the second insulating layer in a bump formation area of the semiconductor wafer to expose the second conductive layer and reduce adverse effects of electro-migration. The openings are separated by portions of the second insulating layer. A UBM layer is formed over the openings in the second insulating layer in the bump formation area electrically connected to the second conductive layer. A bump is formed over the UBM layer.

FLUX, SOLDER PASTE, AND METHOD FOR FORMING SOLDER BUMP

A flux includes a rosin resin, an activator, a thixotropic agent, and a solvent. The solvent includes 30% by mass or more and 60% by mass or less monovalent alcohol with respect to a total mass amount of the flux. The monovalent alcohol has 18 or more and 24 or less of carbon atoms in one molecule. 1. A flux comprising:a rosin resin;an activator;a thixotropic agent; anda solvent including 30% by mass or more and 60% by mass or less monovalent alcohol with respect to a total mass amount of the flux, the monovalent alcohol having 18 or more and 24 or less of carbon atoms in one molecule.2. The flux according to claim 1 , wherein the carbon atoms contained in the one molecule of the monovalent alcohol is 18 or more and 20 or less.3. The flux according to claim 1 , wherein the monovalent alcohol is a branched alcohol or an unsaturated alcohol.4. The flux according to claim 2 , wherein the monovalent alcohol is a branched alcohol or an unsaturated alcohol.5. The flux according to claim 1 , wherein the monovalent alcohol is at least one selected from the group consisting of oleyl alcohol claim 1 , isostearyl alcohol claim 1 , isoeicosanol claim 1 , 2-octyldodecanol claim 1 , and 2-decyltetradecanol.6. The flux according to claim 2 , wherein the monovalent alcohol is at least one selected from the group consisting of oleyl alcohol claim 2 , isostearyl alcohol claim 2 , isoeicosanol claim 2 , 2-octyldodecanol claim 2 , and 2-decyltetradecanol.7. The flux according to claim 3 , wherein the monovalent alcohol is at least one selected from the group consisting of oleyl alcohol claim 3 , isostearyl alcohol claim 3 , isoeicosanol claim 3 , 2-octyldodecanol claim 3 , and 2-decyltetradecanol.8. The flux according to claim 4 , wherein the monovalent alcohol is at least one selected from the group consisting of oleyl alcohol claim 4 , isostearyl alcohol claim 4 , isoeicosanol claim 4 , 2-octyldodecanol claim 4 , and 2-decyltetradecanol.9. The flux according to claim 1 , wherein a ...

Semiconductor package

A semiconductor package includes a first package substrate, a first semiconductor chip on the first package substrate, a plurality of first chip connection units to connect the first package substrate to the first semiconductor chip, an interposer on the first semiconductor chip, the interposer having a width greater than a width of the first semiconductor chip in a direction parallel to an upper surface of the first package substrate, and an upper filling layer including a center portion and an outer portion, the center portion being between the first semiconductor chip and the interposer, and the outer portion surrounding the center portion and having a thickness greater than a thickness of the center portion in a direction perpendicular to the upper surface of the first package substrate.

SEMICONDUCTOR DEVICE WITH IMPROVED THERMAL DISSIPATION AND MANUFACTURING METHODS

A semiconductor device includes a semiconductor die, a redistribution structure, a interconnection structure, and a thermal path structure. The redistribution structure includes an insulation layer over a first surface of the semiconductor die and a conductive trace separated from the first surface by the insulation layer. The conductive trace extends laterally over the first surface from a first end toward a second end that is electrically coupled to a bond pad on the first surface of the semiconductor die. The interconnection structure is coupled to the first end of the conductive trace. The thermal path structure provides a thermal path between the semiconductor die and the interconnection structure. In some embodiment, the thermal path structure comprises a thermal pad that passes through the insulation layer. In other embodiments, the thermal path structure comprises a dummy pad on the first surface of the semiconductor die. 1. (canceled)2. The semiconductor device of claim 21 , wherein:the thermal path structure comprises a thermal pad that passes through the insulation layer and provides the first thermal path; andthe thermal pad has a higher thermal conductivity than the insulation layer.3. The semiconductor device of claim 21 , wherein the thermal path structure comprises a dielectric material having a higher thermal conductivity than the insulation layer.46-. (canceled)7. The semiconductor device of claim 21 , wherein the interconnection structure comprises a solder ball.8. The semiconductor device of claim 21 , wherein the thermal path structure is in direct contact with the first end of the conductive trace.9. The semiconductor device of claim 21 , further comprising:a passivation layer between the insulation layer and the first surface of the semiconductor die,wherein the passivation layer comprises an opening through which the bond pad is coupled to the second end of the conductive trace.10. The semiconductor device of claim 9 , wherein:the thermal ...

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor chip includes forming a masking member including an opening on a wiring substrate including a chip mounting region so as to align the opening with the chip mounting region, forming an uncured sealing resin on at least the chip mounting region of the wiring substrate, wherein a support film is formed on the uncured sealing resin, removing the support film from the uncured sealing resin, removing the masking member from the wiring substrate so that the uncured sealing resin remains on the chip mounting region, and flip-chip mounting a semiconductor chip onto the chip mounting region with the uncured sealing resin arranged in between. The uncured sealing resin has a higher temperature when removing the masking member than when removing the support film.

BAND STOP FILTER STRUCTURE AND METHOD OF FORMING

A filter structure includes a capacitive device and an inductive device. The capacitive device includes a ground plane in a first metal layer of an integrated circuit (IC) package, a plate in a second metal layer of the IC package, and a dielectric layer between the ground plane and the plate. The inductive device includes first and second conductive paths in a third metal layer of the IC package, each of the first and second conductive paths is electrically connected to the plate and has a width w, the first and second conductive paths are separated by a spacing s, and a ratio s/w has a value ranging from 1 to 2. 1. A filter structure comprising: a ground plane in a first metal layer of an integrated circuit (IC) package;', 'a plate in a second metal layer of the IC package; and', 'a dielectric layer between the ground plane and the plate; and, 'a capacitive device comprisingan inductive device comprising first and second conductive paths in a third metal layer of the IC package, each of the first and second conductive paths is electrically connected to the plate and has a width w,', 'the first and second conductive paths are separated by a spacing s, and', 'a ratio s/w has a value ranging from 1 to 2., 'wherein'}2. The filter structure of claim 1 , wherein each of the first and second conductive paths is electrically connected to the plate through a single via extending between the second and third metal layers of the IC package.3. The filter structure of claim 2 , wherein the via extends through an opening in the ground plane.4. The filter structure of claim 1 , whereinthe capacitive device is a first capacitive device,the inductive device is a first inductive device, and the ground plane;', 'another plate in a fourth metal layer of the IC package; and', 'another dielectric layer between the ground plane and the another plate; and, 'a second capacitive device comprising, 'the filter structure further comprisesa second inductive device comprising third and fourth ...

Method of forming a temporary test structure for device fabrication

A method of forming a temporary test structure for device fabrication is provided. The method allows for electrically testing conductive interconnects during controlled collapse chip connections (C4) fabrication and/or through-silicon vias (TSVs) during interposer fabrication. The method includes providing a substrate containing a plurality of electrically conductive interconnects extending vertically to top surface of the substrate. A temporary test structure is formed to connect the plurality of interconnects for electrical testing. Electrical testing is performed on the substrate by probing at different test locations on the temporary test structure. All or part of the temporary test structure is removed so as not to affect product performance. The temporary test structure can contain electrical test pads which provide a way to make temporary connections to small interconnect landings or features at extreme tight pitch to fan them out to testable pads sizes and pitches.

Semiconductor structure and manufacturing method thereof

A semiconductor structure includes a substrate including a first surface, a second surface opposite to the first surface, a first sidewall substantially orthogonal to the first surface and the second surface; an isolation layer surrounding and contacted with the first sidewall of the substrate; a die disposed over the second surface of the substrate; a first conductive bump disposed at the first surface of the substrate; and a second conductive bump disposed between the substrate and the die.

Semiconductor device and manufacturing method thereof

A method of manufacturing a semiconductor structure includes receiving a substrate including a die pad disposed thereon; disposing a passivation over the substrate and around the die pad; disposing a polymer over the passivation; forming a post passivation interconnect (PPI) including an elongated portion and a via portion contacting with the die pad; depositing a metallic paste on the elongated portion of the PPI by a stencil; disposing a conductive bump over the metallic paste; and disposing a molding over the PPI and around the metallic paste and the conductive bump.

Semiconductor Device with Encapsulant Deposited Along Sides and Surface Edge of Semiconductor Die in Embedded WLCSP

A semiconductor device has a semiconductor wafer including a plurality of semiconductor die. An insulating layer is formed over the semiconductor wafer. A portion of the insulating layer is removed by LDA to expose a portion of an active surface of the semiconductor die. A first conductive layer is formed over a contact pad on the active surface of the semiconductor die. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is disposed over a carrier with the active surface of the semiconductor die offset from the carrier. An encapsulant is deposited over the semiconductor die and carrier to cover a side of the semiconductor die and the exposed portion of the active surface. An interconnect structure is formed over the first conductive layer. Alternatively, a MUF material is deposited over a side of the semiconductor die and the exposed portion of the active surface. 1. A semiconductor device , comprising:a substrate;a semiconductor die disposed over the substrate;a first encapsulant deposited over the substrate and semiconductor die and between the substrate and semiconductor die, wherein a side surface of the first encapsulant and a side surface of the substrate are coplanar; anda second encapsulant deposited over the substrate, semiconductor die, and first encapsulant, wherein the second encapsulant covers the side surface of the first encapsulant and the side surface of the substrate.2. The semiconductor device of claim 1 , further including a conductive bump disposed over the substrate opposite the semiconductor die.3. The semiconductor device of claim 1 , further including a recess formed in a front surface of the second encapsulant around the substrate.4. The semiconductor device of claim 1 , wherein the second encapsulant contacts a top surface of the first encapsulant.5. The semiconductor device of claim 1 , wherein the second encapsulant is electrically insulating.6. The semiconductor device of claim 1 , further ...

Thin 3D Fan-Out Embedded Wafer Level Package (EWLB) for Application Processor and Memory Integration

A semiconductor device has a plurality of first semiconductor die with an encapsulant deposited over a first surface of the first semiconductor die and around the first semiconductor die. An insulating layer is formed over the encapsulant and over a second surface of the first semiconductor die opposite the first surface. The insulating layer includes openings over the first semiconductor die. A first conductive layer is formed over the first semiconductor die within the openings. A second conductive layer is formed over the first conductive layer to form vertical conductive vias. A second semiconductor die is disposed over the first semiconductor die and electrically connected to the first conductive layer. A bump is formed over the second conductive layer outside a footprint of the first semiconductor die. The second semiconductor die is disposed over an active surface or a back surface of the first semiconductor die. 1. A method of making a semiconductor device , comprising:providing a first semiconductor die;depositing an encapsulant around the first semiconductor die;forming a plurality of insulating layers over the first semiconductor die and encapsulant;forming a conductive via through the plurality of insulating layers and extending to an active surface of the first semiconductor die;providing a second semiconductor die including a first interconnect structure formed over an active surface of the second semiconductor die; anddisposing the second semiconductor die over the first semiconductor die with the conductive via extending to the first interconnect structure.2. The method of claim 1 , wherein the conductive via extends in a linear path directly from the active surface of the first semiconductor die to the first interconnect structure of the second semiconductor die.3. The method of claim 1 , wherein forming the conductive via includes:forming a first insulating layer of the plurality of insulating layers including an opening in the first insulating ...