Package-Struktur und Verfahren

In einer Ausführungsform umfasst eine Vorrichtung: ein Substrat mit einer ersten Seite und einer zweiten Seite gegenüber der ersten Seite; eine Verbindungsstruktur benachbart zu der ersten Seite des Substrats; und eine IC-Vorrichtung, welche an der Verbindungsstruktur befestigt ist; eine Durchkontaktierung, welche sich von der ersten Seite des Substrats bis zu der zweiten Seite des Substrats erstreckt, wobei die Durchkontaktierung mit der IC-Vorrichtung elektrisch verbunden ist; eine Under-Bump-Metallurgie (UBM) benachbart zu der zweiten Seite des Substrats und die Durchkontaktierung kontaktierend; einen leitfähigen Höcker auf der UBM, wobei es sich bei dem leitfähigen Höcker und der UBM um ein durchgängiges leitfähiges Material handelt, wobei der leitfähige Höcker von der Durchkontaktierung seitlich versetzt ist; und eine Unterfüllung, welche die UBM und den leitfähigen Höcker umgibt.

INTEGRIERTES SCHALTUNGSPACKAGE UND VERFAHREN

In einer Ausführungsform weist eine Struktur Folgendes auf: einen ersten integrierten Schaltungsdie, der erste Die-Anschlüsse aufweist; eine erste Dielektrikumsschicht auf den ersten Die-Anschlüssen; erste leitfähige Durchkontaktierungen, die sich durch die erste Dielektrikumsschicht hindurch erstrecken, wobei die ersten leitfähigen Durchkontaktierungen an eine erste Untergruppe der ersten Die-Anschlüsse angeschlossen sind; einen zweiten integrierten Schaltungsdie, der an eine zweite Untergruppe der ersten Die-Anschlüsse mit ersten aufschmelzbaren Anschlüssen gebondet ist; ein erstes Verkapselungsmaterial, das den zweiten integrierten Schaltungsdie und die ersten leitfähigen Durchkontaktierungen umgibt, wobei das erste Verkapselungsmaterial und der erste integrierte Schaltungsdie seitlich angrenzend sind; zweite leitfähige Durchkontaktierungen benachbart zu dem ersten integrierten Schaltungsdie; ein zweites Verkapselungsmaterial, das die zweiten leitfähigen Durchkontaktierungen, das erste ...

ELEKTRONISCHE INTEGRIERTE SCHALTUNG MIT MINDESTENS EINEM ELEKTRONISCHEN BAUELEMENT

Verfahren zum Herstellen einer Halbleitervorrichtung

Verfahren zum Herstellen einer Halbleitervorrichtung mit: einem Ausnehmungsbildungsschritt des Bildens von Ausnehmungen (11) in einem Substratausgangsmaterial (10), das Halbleiterschaltungen (2) und Elektroden (3) aufweist, die auf einer Oberfläche desselben ausgebildet sind, einem Einbettungselektroden-Bildungsschritt des Füllens eines leitenden Materials in die Ausnehmungen (11) zum Bilden von eingebetteten Elektroden (7a), die Durchdringungselektroden (7) bilden, einem Verbindungsschritt des elektrischen Verbindens der Elektroden (3) auf dem Substratausgangsmaterial (10) und der eingebetteten Elektroden (7a) miteinander, einem Schritt des Bildens eines organischen Films (14) auf der einen Oberfläche des Substratausgangsmaterials (10), einem Klebeschritt des Klebens eines Stützelementes (16, 21), das die mechanische Stabilität des Substratausgangsmaterials (10) unterstützt, auf den organischen Film (14), einem Halbleitersubstrat-Bildungsschritt des Abtragens einer Rückseite des Substratausgangsmaterials ...

Halbleiter-Bauelement und Verfahren

Ein Halbleiter-Bauelement weist Folgendes auf: ein Substrat; eine erste Umverteilungsschicht (RDL) über einer ersten Seite des Substrats; eine oder mehrere Halbleiter-Dies, die über der ersten RDL angeordnet sind und mit dieser elektrisch verbunden sind; und ein Verkapselungsmaterial über der ersten RDL und um den einen oder die mehreren Halbleiter-Dies. Das Halbleiter-Bauelement weist weiterhin Anschlüsse auf, die an einer zweiten Seite des Substrats befestigt sind, die der ersten Seite gegenüberliegt, wobei die Anschlüsse elektrisch mit der ersten RDL verbunden sind. Das Halbleiter-Bauelement weist weiterhin eine Polymerschicht auf der zweiten Seite des Substrats auf, wobei die Anschlüsse von der Polymerschicht her über eine erste Oberfläche der Polymerschicht überstehen, die von dem Substrat entfernt ist. Ein erster Teil der Polymerschicht, der die Anschlüsse kontaktiert, hat eine erste Dicke, und ein zweiter Teil der Polymerschicht zwischen benachbarten Anschlüssen hat eine zweite Dicke ...

Gehäuse eines integrierten Schaltkreises und Verfahren zum Bilden desselben

Eine Ausführungsform einer Gehäuse-auf-Gehäuse(PoP)-Vorrichtung umfasst eine Gehäusestruktur, einen Gehäuseträger und eine Vielzahl von Anschlüssen, die die Gehäusestruktur mit dem Gehäuseträger verbinden. Die Gehäusestruktur umfasst einen Logikchip, der mit einem Speicherchip verbunden ist, eine Formmasse, die den Speicherchip umschließt und eine Vielzahl leitfähiger Stifte, die sich durch die Formmasse hindurch erstrecken. Die Vielzahl der leitfähigen Stifte ist an Kontaktpolstern auf dem Logikchip befestigt.

ABSCHIRMLÖSUNGEN FÜR DIRECT-CHIP-ATTACHKONNEKTIVITÄTSMODULPACKUNGSSTRUKTUREN

Es werden Verfahren zum Ausbilden von Packungsstrukturen und Strukturen, die dadurch ausgebildet werden, beschrieben. Diese Verfahren/Strukturen können eine Abschirmstruktur aufweisen, die auf einer Oberfläche einer Packungsstruktur angeordnet ist, wobei die Abschirmstruktur eine Folie, ein leitfähiges Material, das auf einer Oberfläche der Folie angeordnet ist, und mehrere leitfähige Stäbe aufweist, wobei jeder individuelle leitfähige Stab der mehreren leitfähigen Stäbe durch die Folie angeordnet ist und zumindest ein Anteil der mehreren leitfähigen Stäbe physikalisch mit Erdungsbahnen verkoppelt ist, die auf der Oberfläche der Packungsstruktur angeordnet sind.

Mikroelektronikgehäuse, das eine erhöhte Speicherkomponentendichte bereitstellt

Hier beschriebene Beispiele umfassen eine Mikroelektronikgehäuseanordnung eines Solid-State-Laufwerks, die ein Substrat und eine Vielzahl von Mikroelektronikkomponenten umfasst, die an das Substrat angeschlossen sind. Die Vielzahl von Mikroelektronikkomponenten kann durch eine Komponentenlücke durchgängig voneinander getrennt sein. Das Mikroelektronikgehäuse kann außerdem ein Die-Bauelement umfassen, das an das Substrat angeschlossen ist, wobei sich das Die-Bauelement über die Komponentenlücke erstreckt und vertikal zwischen der Vielzahl von Mikroelektronikkomponenten und dem Substrat angeordnet ist. Bei einigen Beispielen sind die Mikroelektronikkomponenten und das Die-Bauelement jeweils mithilfe einer Vielzahl von Verbindungskomponenten (z.B. einer Lötkugelmatrix) an das Substrat angeschlossen. Die Vielzahl von Verbindungskomponenten kann auf den Mikroelektronikkomponenten so angeordnet sein, dass sie einen oder mehrere offene Bereiche definieren, die frei von Verbindungskomponenten sind ...

Lötverfahren und Schaltung

Vorgeschlagen wird ein Lötverfahren zum Verbinden eines Halbleiterchips (1) mit einer Leiterplatte (2) über wenigstens einen Lötkontakt (7) und zum Herstellen einer Schaltung (14), wobei der Halbleiterchip wenigstens ein elektrisch leitendes Pad (5) aufweist und die Leiterplatte wenigstens einen Leiterbahnabschnitt (9) zur Kontaktierung mit wenigstens einem der Pads des Halbleiterchips umfasst, umfassend: eine Auftragung von Lötpaste (10) auf den wenigstens einen Leiterbahnabschnitt, einen Bondingprozess, bei dem ein Höcker (7) auf wenigstens einem Materialabschnitt (6) auf wenigstens eines der Pads gebondet wird, einen Bestückungsvorgang, bei dem die Leiterplatte so mit wenigstens einem der Halbleiterchips bestückt wird, dass wenigstens einer der Lötkontakte mit der Lötpaste in Berührung kommt, einen Heizprozess, bei dem eine elektrisch leitende Verbindung zwischen dem Leiterbahnabschnitt und dem Pad hergestellt wird. Zur Verbesserung des Lötverfahrens wird als Lötkontakt ausschließlich ...

Substrate for integrated circuit devices including multi-layer glass core and methods of making the same

Reconstituted device including die and functional material

Dies from a wafer are reassembled with passive components and encapsulated to form a reconstituted electronic device 10 comprising a die 11, a passive, functioning component 13 and a metallic redistribution layer 15 which defines an electronic component in an area at least partially above the functioning material. The electronic component may be a metal-oxide-metal capacitor, an inductor or an antenna. The functioning material may be ceramic or it may be a ferrite. The functioning material may surround the die. In one embodiment the functioning material is a ceramic body with a metallic coating 110 (figure 10) on a face opposite that of the surface of the substrate on which the die and functioning material are embedded, a metallic via 102 (figure 9) is included through the ceramic body to contact the metal coating, the redistribution layer/ceramic body/metal coating structure forms a capacitor. In another embodiment the functioning material may be a metal carrier 120 (figure 11) with an ...

Semiconductor application method and product

MANUFACTURING PROCESS FOR A MATRIXFÖRMIGEN RADIATION DETECTOR AS WELL AS PROCEDURE FOR THE CHANGE OF INDIVIDUAL DETECTION MODULES IN THIS MATRIX

MULTILEVEL FOIL FOR SHARPENING A DISK BACK

PROCEDURE FOR the VERSCHWEIßEN OF TWO PARTS WITH THE HELP OF a SOLDERING MATERIAL

Method for stapling with contact element on a chip with a functional layer with openings for the chip substrate provided contact elements

Die vorliegende Erfindung betrifft ein Verfahren zum Heften von Chips (4) auf ein Substrat (1) an auf einer Oberfläche (1o) des Substrats (1) verteilten Chippositionen (1c) mit folgenden Schritten, insbesondere folgendem Ablauf: -Ausbildung oder Aufbringung einer a) an den Chippositionen (1c) zumindest im Bereich von Kontakten (2) durch Strukturierung freigelegten oder b) durch Freilegung von an der Oberfläche (1o) jeweils an den Chippositionen (1c) zumindest im Bereich der Kontakte (2) nach Ausbildung oder Aufbringung der Funktionsschicht (7) freigelegten Funktionsschicht (7) auf das Substrat (1), -Heften von Chips (4) auf eine Chipkontaktseite (7o) der Funktionsschicht (7) an den Chippositionen (1c) und Kontaktierung der Kontakte (2) über Kontaktelemente (3).

Method for stapling with contact element on a chip with a functional layer with openings for the chip substrate provided contact elements

Die vorliegende Erfindung betrifft ein Verfahren zum Heften von Chips (4) auf ein Substrat (1) an auf einer Oberfläche (1o) des Substrats (1) verteilten Chippositionen ( 1 c) mit folgenden Schritten, insbesondere folgendem Ablauf: Ausbildung oder Aufbringung einer a) an den Chippositionen (lc) zumindest im Bereich von Kontakten (2) durch Strukturierung freigelegten oder b) durch Freilegung von an der Oberfläche (lo) jeweils an den Chippositionen (1c) zumindest im Bereich der Kontakte (2) nach Ausbildung oder Aufbringung der Funktionsschicht (7) freigelegten Funktionsschicht (7) auf das Substrat ( 1 ), Heften von Chips (4) auf eine Chipkontaktseite (7o) der Funktionsschicht (7) an den Chippositionen (1 c) und Kontaktierung der Kontakte (2) über Kontaktelemente (3).

ELECTRONIC CIRCUIT DEVICE AND PORDUCTION METHOD THEREFOR

ELECTRONIC BOARD INCORPORATING A HEATER WIRE

L'invention porte sur une carte électronique (1) comportant une zone (20) formant support de composant (10) électronique de type BGA, une résistance (25A) chauffante électrique au droit de ladite zone, ladite résistance étant susceptible de fournir une quantité de chaleur pour le brasage du composant sur la plaque, caractérisé par le fait que la carte comporte une pluralité de couches (21, 23, 25,...) conductrices en alternance avec des couches (22, 24, 26) isolantes électriquement, ladite résistance (25A) formant une des couches conductrices immédiatement sous jacentes de la couche de surface (21). La carte comporte le cas échéant un drain thermique. L'invention porte aussi sur une installation de mise en oeuvre du procédé. Elle permet aussi la réparation d'une carte électronique par remplacement des éléments défectueux sans risque de débraser ou d'endommager les éléments voisins.

SEMICONDUCTOR DEVICE

A semiconductor device (100) is provided with a BGA substrate (110), a semiconductor chip (101), bumps (106) and an underfill (108) applied around the bumps (106). An interlayer insulating film (104) of the semiconductor chip (101) is composed of a low dielectric constant film. The bumps (106) are composed of a lead-free solder. The underfill (108) is composed of a resin material having an elastic modulus of 150MPa or more but not more than 800MPa, and a linear expansion coefficient of the BGA substrate (110) in a substrate planar direction is less than 14ppm/~C.

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND ADHESIVE FOR MOUNTING FLIP CHIP

A purpose of the present invention is to provide a method for manufacturing a semiconductor device that can suppress voids and achieve high reliability. An additional purpose of the present invention is to provide an adhesive which is for mounting a flip chip and is used in the method for manufacturing the semiconductor device. The method for manufacturing the semiconductor devices has: a step 1 for positioning a semiconductor chip, having formed thereon a protruding electrode having a tip part formed from solder, on a substrate via an adhesive; a step 2 for heating the semiconductor chip to a temperature at or above the solder melting point, fusion bonding the protruding electrode of the semiconductor chip and an electrode part of the substrate, and also temporarily bonding with the adhesive; and a step 3 for eliminating voids by heating the adhesive in a pressurized atmosphere. The adhesive has an activation energy ?E found by differential scanning calorimetry and the Ozawa method of ...

Underfill encapsulant for wafer packaging and method for its application

A curable underfill encapsulant composition that is applied directly onto semiconductor wafers before the wafers are diced into individual chips. The composition comprises a thermally curable epoxy resin, a solvent, an imidazole-anhydride curing agent, fluxing agents, and optionally, wetting agents. Various other additives, such as defoaming agents, adhesion promoters, flow additives and rheology modifiers may also be added as desired. The underfill encapsulant is B-stageable to provide a coating on the wafer that is smooth, non-tacky and will allow the wafer to be cleanly diced into individual chips. A method for producing an electronic package containing the B-stageable material may also utilize an unfilled liquid curable fluxing material on the substrate to which the chip is to be attached.

DUAL SOLDER METHODOLOGIES FOR ULTRAHIGH DENSITY FIRST LEVEL INTERCONNECTIONS

半导体装置及其制造方法、电子设备及其制造方法

... 一种半导体装置，在载体基板(11)背面所设的连接盘(12a)上，形成熔点比突出电极(24)还低的突出电极(17)，通过在比突出电极(24)的熔点还低、比突出电极(17)的熔点还高的温度下进行回流焊处理，可以使突出电极(17)接合在母基板(31)的连接盘(32)上。这样，可以防止在载体基板的2次安装时突出电极的融解。 ...

Semiconductor chip assembly and method for manufacturing the same

Wafer level system packaging method and packaging structure

Method of manufacturing semiconductor device and semiconductor device

Semiconductor device manufacturing method and semiconductor device

In a state wherein a plurality of protruding electrodes (4) on a semiconductor chip (1) abut a plurality of electrodes (13), which are formed on a semiconductor substrate (11), with a plurality of solder sections therebetween, the solder sections are melted, and a plurality of solder bonding sections (7), which are bonded to the protruding electrodes (4) of the semiconductor chip (1) and the electrodes (13) of the semiconductor substrate (11), are formed. Then, the interval (A) between a part of the semiconductor chip (1) and the semiconductor substrate (11) is made larger than the interval (B) between another part of the semiconductor chip (1) and the semiconductor substrate (11), and at least some solder bonding sections among the solder bonding sections (7) are stretched. Consequently, variance in the height of the solder bonding sections (7) is generated. Then, a hole (8) is formed in at least the solder bonding section (7a) having the maximum height among the solder bonding sections ...

Semiconductor package and method of manufacturing thereof

With low thermal resistance bump on the lead frame for semiconductor package

Curable flux composition and method of soldering

A lead frame package structure and manufacturing method thereof

Semiconductor device

Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper surface of a semiconductor substrate (1), a passivation layer (3) so formed on the upper surface of the semiconductor substrate (1) as to overlap a part of the electrode pad portion (2) and having a first opening portion (3a) where the upper surface of the electrode pad portion (2) is exposed, a barrier metal layer (5) formed on the electrode pad portion (2), and a solder bump (6) formed on the barrier metal layer (5). The barrier metallayer (5) is formed such that an outer peripheral end (5b) lies within the first opening portion (3a) of the passivation layer (3) when viewed in plan.

Interconnection [...] structure and method

For flip chip package structure

PROCESS FOR the REALIZATION Of a MATRIX OF RADIATIONS ELECTROMAGNETIC AND METHOD FOR REPLACING an ELEMENTARY MODULE Of SUCH a MATRIX OF DETECTION.

A METHOD OF JOINING TWO ELECTRONIC COMPONENTS, FLIP-BY ANNEALING THE UV, OBTAINED ASSEMBLY

Electronic card for aeronautical applications, has electronic layer provided with electrical heating resistance at right of support zone, where resistance provides heat quantity for soldering electronic component on plate

L'invention porte sur une carte électronique (1) comportant une zone (20) formant support de composant (10) électronique de type BGA. La carte est caractérisée par le fait qu'elle comprend une résistance (25) chauffante électrique au droit de ladite zone, ladite résistance étant susceptible de fournir une quantité de chaleur pour le brasage du composant sur la plaque. La carte comporte le cas échéant un drain thermique. L'invention porte aussi sur une installation de mise en oeuvre du procédé. Elle permet aussi la réparation d'une carte électronique par remplacement des éléments défectueux sans risque de débraser ou d'endommager les éléments voisins.

A METHOD OF JOINING TWO ELECTRONIC COMPONENTS, FLIP UV BY ANNEALING, RESULTING ASSEMBLY

L'invention concerne un procédé d'assemblage de type Flip-Chip, entre un premier (1) et un deuxième (2) composants comportant chacun des plots de connexion (11, 21) sur une de leurs faces, dites faces d'assemblage, selon lequel on reporte les composants l'un sur l'autre par leurs faces d'assemblage de sorte à réaliser des interconnexions électriques entre les plots du premier et ceux du deuxième composant. Selon l'invention, on réalise une transformation de l'oxyde de cuivre en cuivre par recuit UV, très localement dans l'espacement entre composants au moins autour des zones au droit des plots de connexion. Le procédé selon l'invention peut être utilisé pour n'importe quel composant transparent aux UV, y compris pour des substrats en matière plastique tels que des substrats en PEN ou en PET.

METHOD OF ASSEMBLING ELECTRICAL CONNECTORS

PROCESS OF WELDING OF TWO ELEMENTS BETWEEN THEM BY MEANS OF A MATERIAL OF BRAZING

Method for assembling integrated circuits for forming integrated three-dimensional structure, involves fusing alloy layer at low melting point to form conducting connection between metal lines of two integrated circuits

Structure intégrée tridimensionnelle, et procédé de fabrication correspondant, comprenant un assemblage d'un premier circuit intégré (CI1) et d'un deuxième circuit intégré (CI2), ledit premier circuit intégré comportant une face avant(F11), une face arrière (F12), au moins une ligne métallique (LM1) d'un niveau de métallisation disposée au voisinage de sa face avant et un pilier conducteur (PC) saillant d'une de ses faces et électriquement connecté avec ladite ligne métallique (LM1) du premier circuit intégré, ledit pilier conducteur étant recouvert à son extrémité d'une couche (SAC) d'un alliage à basse température de fusion, ledit deuxième circuit intégré (CI2) comportant une face avant (F21), une face arrière, au moins une ligne métallique (LM2) disposée au voisinage de sa face avant et une cavité (CV) sur sa face arrière (F22) débouchant sur ladite ligne métallique du deuxième circuit intégré, ladite face du premier circuit intégré d'où saille ledit pilier conducteur (PC) et la face ...

Method for making three-dimensional integrated structures, involves thinning substrates of integrated circuits by holding resin layer, and forming electrically conductive through-connection in thinned substrates

Procédé de réalisation de structures intégrées tridimensionnelles comprenant : a) un assemblage sur plusieurs premiers circuits intégrés (IC1) réalisés au sein d'une plaque semi-conductrice de plusieurs deuxièmes circuits intégrés (IC2) ; b) un dépôt d'une couche de résine encapsulant les deuxièmes circuits intégrés (IC2) et comblant les espaces latéraux entre les deuxièmes circuits intégrés (IC2) ; c) un amincissement des substrats des premiers (IC1) ou des deuxièmes circuits intégrés (IC2) en utilisant comme poignée de maintien la couche de résine ou le substrat des premiers circuits intégrés ; d) une réalisation d'au moins une liaison traversante électriquement conductrice dans le substrat de chaque circuit intégré aminci ; et e) une découpe des assemblages des premiers (IC1) et deuxièmes circuits intégrés (IC2) de manière à former les structures intégrées tridimensionnelles.

Method for assembling e.g. two components in face to face manner, involves depositing volume of welding material on surface, where welding material comprises melting point, which is higher than that of another welding material

Un procédé d'assemblage face contre face d'un premier et d'un deuxième composants (34, 42), consiste : ▪ à réaliser entre les composants : o des colonnes (30, 38, 46) ayant un volume (38) de premier matériau de soudure; o des calles (36, 40) de hauteur inférieure à celle colonnes (30, 38, 46), et ayant une température de fusion supérieure à celle des colonnes ; et ▪ à appliquer un premier chauffage aux colonnes (30, 38, 46) à une température supérieure à la température de fusion des colonnes de soudure et inférieure à la température de fusion des calles (36, 40), La réalisation d'une calle (36, 40) consiste à : ▪ à réaliser une surface mouillable (36) sur le premier ou le deuxième composant (34); ▪ à déposer un volume (40) de deuxième matériau de soudure sur la surface mouillable (36), de température de fusion supérieure à celle des colonnes ; et ▪ à appliquer un deuxième chauffage au volume (40) de deuxième matériau à une température supérieure à la température de fusion du deuxième matériau ...

INDUCTANCE DEVICE AND METHOD OF MAKING SAME

HYBRID ELECTRONIC DEVICE PROTECTED AGAINST MOISTURE AND METHOD FOR MOISTURE PROOFING OF A HYBRID ELECTRONIC DEVICE

플립 칩형 반도체 이면용 필름, 다이싱 테이프 일체형 반도체 이면용 필름, 반도체 장치의 제조 방법 및 플립 칩형 반도체 장치

... 본 발명은, 피착체 상에 플립 칩-접속된 반도체 소자의 이면에 형성하기 위한 플립 칩형 반도체 이면용 필름으로서, 파장 532nm 또는 1064nm에서의 광선 투과율이 20% 이하이고, 레이저 마킹한 후의 마킹부와 마킹부 이외 부분 간의 콘트라스트가 20% 이상인 플립 칩형 반도체 이면용 필름에 관한 것이다.

ＴＳＶ를 가지는 인터포저를 포함하는 반도체 패키지 및 그 제조 방법

... 본 발명은, 상면과 하면을 포함하는 하부 기저 기판; 하부 기저 기판의 하면에 접촉하게 형성된 외부 연결 부재들, 하부 기저 기판의 상면 상에 위치하고 TSV(through silicon via)를 가지는 인터포저, 인터포저 상에 실장되고 인터포저에 전기적으로 연결된 하부 반도체 칩, 및 하부 반도체 칩을 밀봉하는 하부 몰딩 부재를 포함하는 하부 반도체 패키지; 하부 반도체 패키지 상에 위치하고, 상부 반도체 칩 및 상부 반도체 칩을 몰딩하는 상부 몰딩 부재를 포함하는 상부 반도체 패키지; 인터포저 상에 위치하고, 상부 반도체 패키지와 인터포저를 전기적으로 연결하는 패키지 연결 부재들; 하부 기저 기판의 상면으로부터 상부 반도체 패키지의 하면으로 연장되면서 인터포저를 밀봉하는 외측 몰딩 부재; 및 상기 상부 반도체 패키지와 상기 하부 반도체 패키지 사이에 위치하는 공기 간극을 포함하되, 상기 하부 몰딩 부재는 상기 하부 반도체 칩의 상면을 노출하면서 상기 패키지 연결 부재들이 위치하는 개구부를 포함한다.

마주보는（ＦＡＣＥ­ＴＯ­ＦＡＣＥ, Ｆ2Ｆ） 하이브리드 구조를 갖는 집적 회로(ＩＣ), ＩＣ 조립체, ＩＣ 제품 및 이들을 제조하는 방법, 그리고 이를 위한 컴퓨터-판독가능 매체

... 재분배 층(RDL)을 포함하는 집적 회로(IC) 제품이 제공되며, 재분배 층(RDL)은 IC 내에서 전기적 정보를 하나의 위치로부터 또 하나의 위치로 분배하도록 구성된 적어도 하나의 전도성 층을 갖는다. RDL은 또한 복수의 와이어 본드 패드들 및 복수의 솔더 패드들을 포함한다. 복수의 솔더 패드들 각각은 RDL과 직접적으로 전기적 통신을 하는 솔더 가용성 물질을 포함한다.

핫 스팟 열 관리 특징부를 갖춘 3ＤＩＣ 패키징

... 패키지는 전도성 층을 갖는 기판을 포함하며, 전도성 층은 노출된 부분을 포함한다. 다이 스택은 기판 위에 배치되며, 전도성 층에 전기적으로 접속된다. 고 열전도성 재료가 기판 위에 배치되며 전도성 층의 노출된 부분과 접촉한다. 패키지는 또한, 고 열전도성 재료 위에 있고 고 열전도성 재료와 접촉하는 콘투어 링을 포함한다.

ADHESIVE FILM, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE

COMPONENT MOUNTING METHOD, AND COMPONENT MOUNTING APPARATUS

ELECTRONIC DEVICE

개선된 인터커넥트 대역폭을 갖는 적층된 반도체 디바이스 패키지

... 본 개시는 적층된 반도체 디바이스 패키지 및 연관 기술들 및 구성들의 실시예들을 설명한다. 패키지는, 인터커넥트들, 및 일 측면에 부착되는 제 1 반도체 디바이스 및 대향 측면에 부착되는 제 2 반도체 디바이스를 갖는 패키징 기판을 포함할 수 있다. 디바이스들은, 패드 측면들이 기판의 대향하는 측면들 상에서 서로를 향하는 플립 칩 구성으로 부착될 수 있다. 디바이스들은 인터커넥트들에 의해 전기적으로 커플링될 수 있다. 디바이스들은 기판 상의 팬아웃 패드들에 전기적으로 커플링될 수 있다. 유전체 층은 기판의 제 2 측면에 커플링되고 제 2 디바이스를 캡슐화할 수 있다. 비아들은 전기 신호들을, 유전체 층을 통해 팬아웃 영역으로부터 그리고 유전체 층에 커플링된 재분배 층으로 라우팅할 수 있다. 다른 실시예들이 설명 및/또는 주장될 수 있다.

LEAD-FREE SEMICONDUCTOR PACKAGE

A package substrate (4) includes die solder pads (3) and pin solder fillets (5). The pin solder fillets (5) might comprise between approximately 90 wt % to approximately 99 wt % tin and approximately 10 wt % to 1 wt % antimony. The die solder pads (3) might comprise between approximately 4 wt % to approximately 8 wt % bismuth, approximately 2 wt % to approximately 4 wt % silver, approximately 0 wt % to approximately 0.7 wt % copper, and approximately 87 wt % to approximately 92 wt % tin. The die solder pads (3) might comprise between approximately 7 wt % to approximately 20 wt % indium, between approximately 2 wt % to approximately 4.5 wt % silver, between approximately 0 wt % to approximately 0.7 wt % copper, between approximately 0 wt % to approximately 0.5 wt % antimony, and between approximately 74.3 wt % to approximately 90 wt % tin. © KIPO & WIPO 2008 ...

Method Of Forming Bump And Semiconductor device including The Same

RFID CHIP MODULE

SEMICONDUCTOR DEVICE WITH A SOLDER BUMP AND METHODS FOR MANUFACTURING THE SEMICONDUCTOR DEVICE AND A WIRING SUBSTRATE

PURPOSE: A semiconductor device and methods for manufacturing the same and a wiring substrate are provided to precisely form a solder layer on a desirable area of a wiring pad by forming the solder layer using a patterned photoresist layer. CONSTITUTION: An electrode pad(9) is formed on a semiconductor substrate(5). A passivation film(6) covers the semiconductor substrate and the periphery of the electrode pad. A contact layer(7) and a seed metal layer(8) are formed on the electrode pad in order. A barrier metal layer(2) and a solder layer(3) are formed on the seed metal layer in order. A stopper film(4) is formed on the upper part of the barrier metal layer. COPYRIGHT KIPO 2013 ...

METHOD FOR CHIP TO WAFER BONDING

집적 회로 패키지 기판

... 본 개시 내용의 실시예는 이중 표면 마감 패키지 기판 어셈블리를 위한 기술 및 구성에 관한 것이다. 일 실시예에서, 방법은 패키지 기판의 제1 측부 상에 제1 라미네이션층을 증착 및 패키지 기판의 제2 측부 상에 배치된 하나 이상의 전기 콘택트 상에 제1 표면 마감재를 증착하고, 패키지 기판의 제1 측부로부터 제1 라미네이션층을 제거하고, 패키지 기판의 제2 측부 상에 제2 라미네이션층을 증착 및 패키지 기판의 제1 측부 상에 배치된 하나 이상의 전기 콘택트 상에 제2 표면 마감재를 증착하고, 패키지 기판의 제2 측부로부터 제2 라미네이션층을 제거하는 것을 포함한다. 다른 실시예들이 기술되고/되거나 청구될 수 있다.

MULTI-CHIP BALL GRID ARRAY IC PACKAGES

PURPOSE: A multiple chip ball grid array package is provided to increase the I/O density by mounting active chips in the standoff space on the underside of the substrate inside the ball grid array. CONSTITUTION: State of the art IC chips can be made thin enough that they can be mounted in the space between the board(16) and the substrate(12). For convenience in this description this space will be referred to herein as the "BGA gap". A BGA package designed, where the IC chip is designated(21) and is die bonded to interconnect substrate(22). Bond pads(23) on the IC chip are interconnected to bond pads(24) on the interconnect substrate by wire bonds(25). The substrate(22) is interconnected to motherboard(26), by solder balls(27) and BGA bond pads(28). Attached to the underside of the substrate(22), in the BGA gap, is an array of IC chips(31-34). Each of the array of IC chips is flip-chip bonded to the underside of substrate(22) using solder bumps(35). Solder bumps(35) are typically provided ...

플래쉬 램프 및 마스크를 이용하여 복수의 칩을 솔더링하기 위한 장치 및 방법

... (예를 들어, 상이한 치수(표면적 및/또는 두께), 열용량(CI, C2), 흡열율, 전도율, 솔더링 접합부들의 갯수 및/또는 크기 등에 의해 유발되는) 상이한 열 특성들을 가진 둘 이상의 상이한 칩들(1a, 1b)과 기판(3)이 제공된다. 기판(3)과 칩들(1a, 1b) 사이에는 솔더링 재료(2)가 배치된다. 플래쉬 램프(5)는 칩들(1a, 1b)을 가열하는 광 펄스(6)를 발생시키고, 솔더링 재료(2)는 가열된 칩들(1a, 1b)과의 접촉에 의해서 적어도 부분적으로 용융된다. 칩들(1a, 1b)과 플래쉬 램프(5) 사이에는 마스킹 기구(7)가 배치되어, 마스킹 기구(7)를 통과하는 광 펄스(6)의 상이한 부위들(6a, 6b)에서 상이한 광 강도들(Ia, Ib)을 유발하고, 이로써 상이한 광 강도들(Ia, Ib)로 칩들(1a, 1b)을 가열하게 된다. 이것은 상기 상이한 열 특성들을 보상하여, 광 펄스(6)에 의한 가열의 결과로서 칩들(1a, 1b) 간의 온도 스프레드가 감소된다. 상기 칩들(1a, 1b)은 기판(3) 상에 배치되기 전에 기판(3)과 플래쉬 램프(5) 사이에 배치된 칩 캐리어에 의하여 분리가능하게 보유될 수 있고, 상기 마스킹 기구(7)에 의하여 투과된 광 펄스(6)의 빛(6a, 6b)은 칩들(1a, 1b)의 가열을 위하여 칩 캐리어에 의해 보유된 칩들(1a, 1b) 상으로 투사되어 칩들(1a, 1b)이 칩 캐리어로부터 분리되어 기판(3)으로 전달되게 하며, 상기 가열된 칩들(1a, 1b)은 기판(3)과 칩들(1a, 1b) 사이의 솔더링 재료(2)의 용융을 유발해서 칩들(1a, 1b)이 기판(3)에 부착되게 한다.

CURE CATALYST, COMPOSITION, ELECTRONIC DEVICE AND ASSOCIATED METHOD

A cure catalyst is provided. The cure catalyst may include a Lewis acid and one or both of a nitrogen-containing molecule or a non-tertiary phosphine. The nitrogen-containing molecule may include a mono amine or a heterocyclic aromatic organic compound. A curable composition may include the cure catalyst. An electronic device may include the curable composition. Methods associated with the foregoing are provided also. © KIPO & WIPO 2008 ...

보호 테이프 및 반도체 장치의 제조 방법

... 웨이퍼의 치핑을 억제함과 더불어, 반도체 칩의 실장 시에서의 땜납 접합성을 양호하게 한다. 돌기 전극(22)이 형성된 웨이퍼(21)면에, 접착제층(11)과, 열가소성 수지층(12)과, 기재 필름층(13)을 이 순서로 갖는 보호 테이프(10)를 부착하는 공정과, 웨이퍼(21)의 보호 테이프(10) 부착면의 반대면을 그라인드하는 공정과, 웨이퍼(21)의 그라인드면에 점착 테이프(30)를 부착하는 공정과, 접착제층(11)을 남기고 보호 테이프(10)를 박리하여, 다른 층을 제거하는 공정과, 점착 테이프(30)가 부착된 웨이퍼(21)를 다이싱하여, 개편의 반도체 칩을 얻는 공정과, 다이싱 전에 접착제층(11)을 경화시키는 공정을 가지며, 경화 후의 접착제층(11)의 저장 전단 탄성률이 3.0E+08Pa~5.0E+09Pa이고, 부착 전의 보호 테이프(10)의 접착제층(11)의 두께와 돌기 전극(22)의 높이의 비(부착 전의 접착제층의 두께/돌기 전극의 높이)가 1/30~1/6이다.

ELECTRONIC DEVICE AND METHOD OF MANUFACTURING SAME

The device of the invention comprises a semiconductor element, a first connection element, a first patterned electrically conductive layer and a second patterned electrically conductive layer. The device is further provided with an encapsulation that encapsulates all except the first conductive layer, which is part of the substrate. The device can be suitably made in that the second conductive layer is provided, in pre-patterned form, with a permeable isolating layer as a foil. © KIPO & WIPO 2007 ...

반도체 패키지 및 이의 제조 방법

... 본 발명의 기술적 사상에 따른 반도체 패키지는, 반도체 칩, 반도체 칩의 측면을 감싸는 몰딩부, 반도체 칩의 아래에 반도체 칩과 연결되고 반도체 칩에서 수직 방향으로 멀어질수록 폭이 좁아지는 컨택 플러그를 가지는 패시베이션, 및 패시베이션의 아래에 반도체 칩과 외부 접속 단자를 전기적으로 연결하는 재배선부를 포함하되, 재배선부는 상부에 컨택 플러그와 연결되는 상부 패드 및 상부 패드와 동일한 레벨에 위치하는 미세 패턴, 몸체부에 재배선 및 반도체 칩에서 수직 방향으로 멀어질수록 폭이 넓어지는 비아 플러그, 및 하부에 외부 접속 단자와 연결되고 외부로 노출되는 하부 패드를 포함한다.

BONDING DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE

SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD

PURPOSE: To prevent a α-ray soft error of a semiconductor device wherein a solder bump is connected to a Cu wiring formed on an Al wiring. CONSTITUTION: A bump-land 6 connecting with the solder bump 10A and the Cu wiring 10 formed together with it in one-piece, consists of a stacked-layer film of a Cu film and a Ni film formed on its upper portion. The film thickness of the stacked-layer film is larger than film thickness of each of a photosensitive polyimide resin film 11 formed on the lower layers of the Cu wiring 10 and the bump-land 10A, an inorganic passivation film 26, a third Al wiring 25, the bump-pad BP, and a second inter-layer insulating film 24. That is, the bump-land 10A is constructed by film thickness larger than those of an insulating component and wiring component which are interposed between a MISFET (n- channel-type MISFETQn and p-channel-type MISFETQp) and the bump-land 10A. © KIPO & JPO 2003 ...

Semiconductor device and method of manufacturing semiconductor device

A semiconductor device includes a semiconductor element; a pad electrode that is formed on the semiconductor element; an alignment mark that is formed on the semiconductor element; a connection electrode that is formed on the pad electrode; and an underfill resin that is formed to cover the connection electrode. The height of the alignment mark from the semiconductor element is greater than that of the connection electrode.

Package structure and manufacturing method thereof

A package structure and a manufacturing method thereof are provided. The package structure includes a chip, a substrate and a solder. The chip includes a bump disposed on the surface of the chip. The substrate includes a pad and a solder resistor layer. The pad is disposed on the surface of the substrate corresponding to the bump and the solder resistor layer is disposed on the surface of the substrate. The solder resistor layer has an opening for exposing the pad. The ratio of the width of the opening to the diameter of the bump is 1 to 1.5. The solder is disposed in the opening around the bump. The solder, the bump and the pad are welded with each other for electrically connecting the chip and the substrate.

Semiconductor package and method of manufacturing the same

A semiconductor package of an embodiment includes: a semiconductor chip having a signal input terminal and a signal output terminal; and a cap unit that is formed on the semiconductor chip. The cap unit includes a concave portion forming a hollow structure between the semiconductor chip and the cap unit, a first through electrode electrically connected to the signal input terminal, and a second through electrode electrically connected to the signal output terminal. Of the inner side surfaces of the concave portion, a first inner side surface and a second inner side surface facing each other are not parallel to each other.

Method and system for packing optimization of semiconductor devices

Provided is a disclosure for optimizing the number of semiconductor devices on a wafer/substrate. The optimization comprises laying out, cutting, and packaging the devices efficiently.

Method of forming semiconductor structure

Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.

SEMICONDUCTOR DEVICE PACKAGE AND MANUFACTURING METHOD THEREOF

Semiconductor device and method of manufacture

Printed wiring board with a pin for mounting a component and an electronic device using the same

Solder-coated ball and method for manufacturing same

Film for flip chip type semiconductor back surface, and its use

Semiconductor device, method of manufacturing the same, and method of manufacturing wiring board

FLUX COMPOSITION, FORMING METHOD OF ELECTRICAL CONNECTING STRUCTURE, ELECTRICAL CONNECTING STRUCTURE AND SEMICONDUCTOR DEVICE

Chip package

A chip package including a die, a package substrate, and multiple bumps is provided. The die has an active surface, multiple die pads, and a first passivation layer. The die pads are disposed on the active surface. The first passivation layer is disposed on the active surface and has multiple first openings exposing the die pads respectively. The package substrate has a substrate surface, multiple substrate pads, and a second passivation layer. The substrate pads are disposed on the substrate surface. The second passivation layer is disposed on the substrate surface and has a second opening exposing the substrate pads and part of the substrate surface. The bumps are disposed on the die pads respectively. Each bump is connected to one of the substrate pads by a compression bonding process. The die is electrically connected to the package substrate via the bumps. The distance from the first passivation layer to the substrate pads is smaller than 50 micrometer.

Flip-attached and underfilled semiconductor device and method

Trace design for bump-on-trace (bot) assembly

METHOD OF MAKING AN ELECTRONIC DEVICE HAVING A LIQUID CRYSTAL POLYMER SOLDER MASK AND RELATED DEVICES

A method of making an electronic device includes forming a circuit layer on a liquid crystal polymer (LCP) substrate and having at least one solder pad. The method also includes forming an LCP solder mask having at least one aperture therein alignable with the at least one solder pad. The method further includes aligning and laminating the LCP solder mask and the LCP substrate together, then positioning solder paste in the at least one aperture. At least one circuit component may then be attached to the at least one solder pad using the solder paste.

FLIP-CHIP MODULE AND METHOD FOR THE PRODUCTION THEREOF

The invention relates to a flip-chip module comprising a semiconductor chip provided with contact columns, which are electrically and mechanically connected to a substrate. A spacer is provided between the substrate and the semiconductor chip and mechanically coupled with the substrate and/or the chip. Thermal stresses in the flip chip module are absorbed by the spacer and are kept away from the semiconductor chip. Said invention also relates to a method for producing a flip chip module consisting in placing the spacer between the semiconductor chip and the substrate and in soldering the contact columns with the substrate contact points. The use of the spacer makes it possible to accurately adjust the distance between the semiconductor chip and the substrate, thereby improving the quality of the soldering points.

SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR

Provided is a production method for a semiconductor device in which the respective connecting sections of a semiconductor chip and a wiring circuit board are electrically connected to each other, or for a semiconductor device in which the respective connecting sections of a plurality of semiconductor chips are electrically connected to each other. The production method for a semiconductor comprises a step in which at least one portion of the connecting section is sealed using an adhesive for semiconductors that contains a compound comprising the group represented by formula (1). [In formula (1), R1 indicates an electron-donating group.] ...

SEMICONDUCTOR CHIP WITH STAIR ARRANGEMENT BUMP STRUCTURES

Various semiconductor chip input/output structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first conductor structure on a first side of a semiconductor chip and forming a second conductor structure in electrical contact with the first conductor structure. The second conductor structure is adapted to be coupled to a solder structure and includes a stair arrangement that has at least two treads.

METHOD OF MANUFACTURING PRINTED WIRING BOARD

... [PROBLEMS] To provide a method of manufacturing a printed wiring board capable of surely forming a high solder bump on a small diameter connection pad provided in the opening of a solder resist. [MEANS FOR SOLVING THE PROBLEMS] A solder ball (77) is molten by reflowing to form a high solder bump (78U) from the solder ball (77) installed in the upper surface opening (71). Since a distance between the solder ball (77) installed in the opening (71) and the connection pad (158P) is reduced by adjusting the thickness of a solder resist layer (70), the solder bump (78U) can be surely connected to the connection pad (158P) when the solder ball (77) is molten by reflowing.

STABLE GOLD BUMP SOLDER CONNECTIONS

A metallic interconnect structure (200) for connecting a gold bump (205) and a copper pad (212), as used for example in semiconductor flip-chip assembly. A first region (207) of binary AuSn2 intermetallic is adjacent to the gold bump. A region (208) of binary AuSn4 intermetallic is adjacent to the first AuSn2 region. Then, a region (209) of binary gold-tin solid solution is adjacent to the AuSn4 region, and a second region (210) of binary AuSn2 intermetallic is adjacent to the solid solution region. The second AuSn2 region is adjacent to a nickel layer (213) (preferred thickness about 0.08 μm), which covers the copper pad. The nickel layer insures that the gold/tin intermetallic s and solutions remain substantially free of copper and thus avoid ternary compounds, providing stabilized gold bump/solder connections.

SEMICONDUCTOR FLIP-CHIP PACKAGE AND METHOD FOR THE FABRICATION THEREOF

A simplified process for flip-chip attachment of a chip (10) to a substrate (20) is provided by pre-coating the chip (10) with an encapsulant underfill material (22) having discrete solder columns therein to eliminate the conventional capillary flow underfill process. Such a structure permits incorporation of remeltable layers for rework, test, or repair. It also allows incorporation of electrical redistribution layers. In one aspect, the chip (10) and pre-coated encapsulant are placed at an angle to the substrate and brought into contact with the pre-coated substrate, then the chip (10) and pre-coated encapsulant are pivoted about the first point of contact, expelling any gas therebetween until the solder bumps (14) on the chip are fully in contact with the substrate (20). There is provided a flip-chip configuration having a compliant solder/flexible encapsulant understructure that deforms generally laterally with the substrate (20) as the substrate (20) undergoes expansion and contraction ...

Semiconductor device and manufacturing method therefor

A semiconductor device is obtained, in which excellent characteristics are achieved, the reliability is improved, and an SiC wafer can also be used for the fabrication. A plurality of Schottky-barrier-diode units 10 is formed on an SiC chip 9, and each of the units 10 has an external output electrode 4 independently of each other. Bumps 11 (the diameter is from several tens to several hundreds of m) are formed only on the external output electrodes 4 of non-defective units among the units 10 formed on the SiC chip 9, meanwhile bumps are not formed on the external output electrodes 4 of defective units in which the withstand voltage is too low, or the leakage current is too much. Because the bumps are not formed on the defective units, Schottky-barrier-side electrodes 3 are connected in parallel to the exterior of the device through the bumps 11, and a wiring layer 13 and an external lead 13a of a wiring substrate 12; thus, only the external output electrodes 4 of the non-defective units ...

Method and device for electrically contacting terminal faces of two substrates by laser soldering using a gaseous flux medium

A method for electrically contacting terminal faces of two substrates, such as a chip and a carrier substrate, includes two successive phases. In a first phase, the chip is positioned with its terminal faces against terminal faces of the substrate and laser energy is applied to the chip at the rear. In a second phase, a flux medium is applied and laser energy is applied to the rear of the chip to cause reflow. The device for performing the second phase of the method comprises a carrier table and a housing, which form a housing interior with a top side of the carrier table which receives the component arrangement, and a laser light source, which is oriented so that the laser radiation impinges on the rear side of the first substrate.

METHOD FOR FASTENING CHIPS WITH A CONTACT ELEMENT ONTO A SUBSTRATE PROVIDED WITH A FUNCTIONAL LAYER HAVING OPENINGS FOR THE CHIP CONTACT ELEMENTS

A method for tacking of chips onto a substrate at chip positions which are distributed on a surface of the substrate. The method includes the following steps: formation or application of a function layer onto the substrate, removing the function layer from the substrate at the chip positions at least in the region of contacts to uncover the contacts, tacking chips onto one chip contact side of the function layer at the chip positions and contacting the chips with the contacts via contact elements.

Electronic device, method for manufacturing the electronic device, and electronic apparatus

An electronic device includes: a first circuit board; a second circuit board located above a first region of the first circuit board; a first semiconductor element located above a second region of the first circuit board, which is different from the first region, and above a third region of the second circuit board; a first connection interposed between the first semiconductor element and the second region so as to electrically interconnect the first semiconductor element and the first circuit board; and a second connection interposed between the first semiconductor element and the third region so as to electrically interconnect the first semiconductor element and the second circuit board.

Metal Bump Joint Structure and Methods of Forming

A structure comprises a first semiconductor chip with a first metal bump and a second semiconductor chip with a second metal bump. The structure further comprises a solder joint structure electrically connecting the first semiconductor chip and the second semiconductor chip, wherein the solder joint structure comprises an intermetallic compound region between the first metal bump and the second metal bump, wherein the intermetallic compound region is with a first height dimension and a surrounding portion formed along exterior walls of the first metal bump and the second metal bump, wherein the surrounding portion is with a second height dimension, and wherein the second height dimension is greater than the first height dimension.

Wiring board and method for manufacturing the same

A wiring board including a first insulation layer, a conductive pattern formed on the first insulation layer, a second insulation layer formed on the conductive pattern and the first insulation layer and having an opening portion exposing at least a portion of the conductive pattern, and a connection conductor formed in the opening portion of the second insulation layer such that the connection conductor is positioned on the portion of the conductive pattern. The connection conductor has a tip portion which protrudes from a surface of the second insulation layer and which has a tapered side surface tapering toward an end of the tip portion.

Microelectronic packages with dual or multiple-etched flip-chip connectors

A packaged microelectronic element includes a microelectronic element having a front surface and a plurality of first solid metal posts extending away from the front surface. A substrate has a major surface and a plurality of conductive elements exposed at the major surface and joined to the first solid metal posts. In particular examples, the conductive elements can be bond pads or can be second posts having top surfaces and edge surfaces extending at substantial angles away therefrom. Each first solid metal post includes a base region adjacent the microelectronic element and a tip region remote from the microelectronic element, the base region and tip region having respective concave circumferential surfaces. Each first solid metal post has a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region.

Conductive Sidewall for Microbumps

Electromigration in microbump connections causes voids in the microbumps, which reduces the lifetime of an integrated circuit containing the microbump. Electromigration lifetime may be increased in microbumps by forming a copper shell around the solder. The copper shell of one microbump contacts the copper shell of a second microbump to enclose the solder of the microbump connection. The copper shell allows higher current densities through the microbump. Thus, smaller microbumps may be manufactured on a smaller pitch without suffering failure from electromigration. Additionally, the copper shell reduces shorting or bridging between microbump connections on a substrate.

Film for flip chip type semiconductor back surface, dicing tape-integrated film for semiconductor back surface, process for producing semiconductor device, and flip chip type semiconductor device

The present invention relates to a film for flip chip type semiconductor back surface to be formed on a back surface of a semiconductor element flip chip-connected onto an adherend, in which the film for flip chip type semiconductor back surface before thermal curing has, at the thermal curing thereof, a volume contraction ratio within a range of 23° C. to 165° C. of 100 ppm/° C. to 400 ppm/° C.

Integrated circuit packaging system with warpage control and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit device having chip interconnects; applying an attachment layer directly on the integrated circuit device; attaching a device stiffener to the integrated circuit device with the attachment layer; attaching a chip carrier to the chip interconnects with the device stiffener attached to the integrated circuit device for controlling warpage of the integrated circuit device to prevent the warpage from causing some of the chip interconnects to separate from the chip carrier during attachment of the chip interconnects to the chip carrier; and applying an underfill between the chip carrier and the integrated circuit device for controlling connectivity of all the chip interconnects to the chip carrier.

Electronic element unit and reinforcing adhesive agent

It is an object of the present invention to provide an electronic element unit and a reinforcing adhesive agent in which a bonding strength can be improved between an electronic element and a circuit board and a repairing work can be carried out without giving a thermal damage to the electronic element or the circuit board. In an electronic element unit ( 1 ) including an electronic element ( 2 ) having a plurality of connecting terminals ( 12 ) on a lower surface thereof, a circuit board ( 3 ) having a plurality of electrodes ( 22 ) corresponding to the connecting terminals ( 12 ) on an upper surface thereof. The connecting terminals ( 12 ) and the electrodes ( 22 ) are connected by solder bumps ( 23 ), and the electronic element ( 2 ) and the circuit board ( 3 ) are partly bond by a resin bond part ( 24 ) made of a thermosetting material of a thermosetting resin, and a metal powder ( 25 ) is included in the resin bond parts ( 24 ) in a dispersed state. The metal powder ( 25 ) has a melting point lower than a temperature at which the resin bond parts ( 24 ) are heated when a work (a repairing work) is carried out for removing the electronic element ( 2 ) from the circuit board ( 3 ).

Semiconductor device and assembling method thereof

A semiconductor device and an assembling method thereof are provided. The semiconductor device includes a chip, a carrier, a plurality of first conductive elements and a plurality of second conductive elements. The chip has a plurality of first pads. The carrier has a plurality of second pads. The second pads correspond to the first pads. Each first conductive element is disposed between one of the first pads and one of the second pads. Each second conductive element is disposed between one of the first pads and one of the second pads. A volume ratio of intermetallic compound of the second conductive elements is greater than a volume ratio of intermetallic compound of the first conductive elements.

Direct Edge Connection for Multi-Chip Integrated Circuits

The present invention allows for direct chip-to-chip connections using the shortest possible signal path.

Solder, soldering method, and semiconductor device

A solder includes Sn (tin), Bi (bismuth) and Zn (zinc), wherein the solder has a Zn content of 0.01% by weight to 0.1% by weight.

Semiconductor Device and Method of Forming Narrow Interconnect Sites on Substrate with Elongated Mask Openings

A semiconductor device has a semiconductor die with a plurality of bumps formed over a surface of the semiconductor die. A plurality of conductive traces is formed over a surface of the substrate with interconnect sites. A masking layer is formed over the surface of the substrate. The masking layer has a plurality of parallel elongated openings each exposing at least two of the conductive traces and permitting a flow of bump material along a length of the plurality of conductive traces within the plurality of elongated openings while preventing the flow of bump material past a boundary of the plurality of elongated openings. One of the conductive traces passes beneath at least two of the elongated openings. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate.

High-frequency module manufacturing method

In a method of manufacturing a high-frequency module, a resin substrate with a high frequency circuit including an electronic component mounted thereon is placed so that the electronic component faces a resin bath. A resin which is in a non-flowable state in the resin bath is softened until the resin becomes flowable, and air in space formed between the resin substrate and the resin is sucked. The resin substrate is brought into contact with a liquid surface of the resin. The resin is pressurized and allowed to flow into a gap between the resin substrate and the electronic component. The resin is cured so that a resin portion is formed on the resin substrate. A shield metal film is formed on a surface of the resin portion.

Layered chip package and method of manufacturing same

A layered chip package includes a main body and wiring. The main body includes: a main part having a top surface and a bottom surface and including three or more layer portions stacked on one another; a plurality of first terminals disposed on the top surface of the main part; and a plurality of second terminals disposed on the bottom surface of the main part. Each layer portion includes a semiconductor chip having first and second surfaces, and a plurality of electrodes electrically connected to the wiring. The plurality of electrodes are disposed on a side of the first surface of the semiconductor chip. A first layer portion located closest to the top surface of the main part and a second layer portion located closest to the bottom surface of the main part are arranged so that the second surfaces of their respective semiconductor chips face toward each other. The plurality of first terminals are formed by using the plurality of electrodes of the first layer portion. The plurality of second terminals are formed by using the plurality of electrodes of the second layer portion.

Enhanced Bump Pitch Scaling

An integrated circuit (IC) device is provided. In an embodiment the IC device includes an IC die configured to be bonded onto an IC routing member and a first plurality of pads that is located on a surface of the IC die, each pad being configured to be coupled to a respective pad of a second plurality of pads that is located on a surface of the IC routing member. A pad of the first plurality of pads is offset relative to a respective pad of the second plurality of pads such that the pad of the first plurality of pads is substantially aligned with the respective pad of the second plurality of pads after the IC die is bonded to the IC routing member.

Bump-on-trace (bot) structures

A bump-on-trace (BOT) structure is described. The BOT structure includes a first work piece with a metal trace on a surface of the first work piece, wherein the metal trace has a first axis. The BOT structure further includes a second work piece with an elongated metal bump, wherein the elongated metal bump has a second axis, wherein the second axis is at a non-zero angle from the first axis. The BOT structure further includes a metal bump, wherein the metal bump electrically connects the metal trace and the elongated metal bump. A package having a BOT structure and a method of forming the BOT structure are also described.

Adhesive film for semiconductor device, film for backside of flip-chip semiconductor, and dicing tape-integrated film for backside of semiconductor

Provided is an adhesive film for a semiconductor device that is capable of having the same physical properties as these at the time of manufacture even after it is stored for a long time. The adhesive film for a semiconductor device of the present invention contains a thermosetting resin, and in which the amount of reaction heat generated in a temperature range of ±80° C. of a reaction heat peak temperature measured by a differential scanning calorimeter after the adhesive film is stored at 25° C. for 4 weeks is 0.8 to 1 time the amount of reaction heat generated before storage.

Integrated circuit package including a direct connect pad, a blind via, and a bond pad electrically coupled to the direct connect pad

An integrated circuit package including a semiconductor die and a flexible circuit (flex circuit), and a method for forming the integrated circuit package. The flex circuit can include a direct connect pad which is not electrically coupled to an active trace, a blind via electrically coupled to the direct connect pad, and a semiconductor die having a bond pad which is electrically coupled to the direct connect pad using a conductor. The bond pad, the conductor, the direct connect pad, and the blind via can all be vertically aligned, each with the other.

Bump-On-Leadframe Semiconductor Package With Low Thermal Resistance

In a bump-on-leadframe semiconductor package a metal bump formed on a integrated circuit die is used to facilitate the transfer of heat generated in a semiconductor substrate to a metal heat slug and then to an external mounting surface. A structure including arrays of thermal vias may be used to transfer the heat from the semiconductor substrate to the metal bump

Semiconductor Devices and Methods of Manufacturing and Packaging Thereof

Semiconductor devices and methods of manufacturing and packaging thereof are disclosed. In one embodiment, a semiconductor device includes an integrated circuit and a plurality of copper pillars coupled to a surface of the integrated circuit. The plurality of copper pillars has an elongated shape. At least 50% of the plurality of copper pillars is arranged in a substantially centripetal orientation.

Curable Amine, Carboxylic Acid Flux Composition And Method Of Soldering

A curable flux composition is provided, comprising, as initial components: a resin component having at least two oxirane groups per molecule; a carboxylic acid; and, an amine fluxing agent represented by formula I: and, optionally, a curing agent. Also provided is a method of soldering an electrical contact using the curable flux composition.

Semiconductor package including an integrated waveguide

Methods and apparatus are disclosed for wirelessly communicating among integrated circuits and/or functional modules within the integrated circuits. A semiconductor device fabrication operation uses a predetermined sequence of photographic and/or chemical processing steps to form one or more functional modules onto a semiconductor substrate. The functional modules are coupled to an integrated waveguide that is formed onto the semiconductor substrate and/or attached thereto to form an integrated circuit. The functional modules communicate with each other as well as to other integrated circuits using a multiple access transmission scheme via the integrated waveguide. One or more integrated circuits may be coupled to an integrated circuit carrier to form Multichip Module. The Multichip Module may be coupled to a semiconductor package to form a packaged integrated circuit.

Power management applications of interconnect substrates

Various applications of interconnect substrates in power management systems are described.

Semiconductor device having multiple bump heights and multiple bump diameters

A semiconductor die includes a first contact stack including a first UBM pad on a first die pad, a second contact stack including a second UBM pad on a second die pad, and a third contact stack including a third UBM pad on a third die pad. The second UBM pad perimeter is shorter than the first UBM pad perimeter, and the third UBM pad perimeter is longer than the second UBM pad perimeter. A first solder bump is on the first UBM pad, a second solder bump is on the second UBM pad, and a third solder bump is on the third UBM pad. The first solder bump, second solder bump and third solder bump all have different sizes.

Methods of manufacturing stress buffer structures in a mounting structure of a semiconductor device

A mounting structure for a semiconductor device is formed to include a stepwise stress buffer layer under a stepwise UBM structure.

System in package process flow

A method comprises connecting a substrate having a plurality of integrated circuit (IC) dies to a package substrate, so that the package substrate extends beyond at least two edges of the substrate, leaving first and second edge portions of the package substrate having exposed contacts. The first and second edge portions meet at a first corner of the package substrate. At least a first upper die package is placed over the substrate, so that first and second edge portions of the first upper die package extend beyond the at least two edges of the substrate. Pads on the first and second edge portions of the first upper die package are connected to the contacts of the first and second edge portions of the package substrate.

Packaging Process Tools and Systems, and Packaging Methods for Semiconductor Devices

Packaging process tools and systems, and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging process tool for semiconductor devices includes a mechanical structure for supporting package substrates or integrated circuit die during a packaging process for the integrated circuit die. The mechanical structure includes a low thermal conductivity material disposed thereon.

Method of processing solder bump by vacuum annealing

A method includes vacuum annealing on a substrate having at least one solder bump to reduce voids at an interface of the at least one solder bump. A die is mounted over the substrate.

Semiconductor chips including passivation layer trench structure

An integrated circuit including an active region a passive region and a cut line in the passive region includes a passivation layer that includes an outer nitride layer over an oxide layer. The integrated circuit also includes a crack stop below the passivation layer and in the passive region, and a solder ball in the active region. The passivation layer has a trench formed therein in a location that is further from the active region than the crack stop and closer to the active region than the cut line, the trench passing completely through the outer nitride layer and a least a portion of the way through the oxide layer.

Mechanisms of forming connectors for package on package

The described embodiments of mechanisms of forming connectors for package on package enable smaller connectors with finer pitch, which allow smaller package size and additional connections. The conductive elements on one package are partially embedded in the molding compound of the package to bond with contacts or metal pads on another package. By embedding the conductive elements, the conductive elements may be made smaller and there are is gaps between the conductive elements and the molding compound. A pitch of the connectors can be determined by adding a space margin to a maximum width of the connectors. Various types of contacts on the other package can be bonded to the conductive elements.

Flip-chip packaging techniques and configurations

Embodiments of the present disclosure flip-chip packaging techniques and configurations. An apparatus may include a package substrate having a plurality of pads formed on the package substrate, the plurality of pads being configured to receive a corresponding plurality of interconnect structures formed on a die and a fluxing underfill material disposed on the package substrate, the fluxing underfill material comprising a fluxing agent configured to facilitate formation of solder bonds between individual interconnect structures of the plurality of interconnect structures and individual pads of the plurality of pads and an epoxy material configured to harden during formation of the solder bonds to mechanically strengthen the solder bonds. Other embodiments may also be described and/or claimed.

Method and system for ultra miniaturized packages for transient voltage suppressors

A method of forming a silicon carbide transient voltage suppressor (TVS) assembly and a system for a transient voltage suppressor (TVS) assembly are provided. The transient voltage suppressor (TVS) assembly includes a semiconductor die including a contact surface on a single side of the die, the die further including a substrate comprising a layer of at least one of an electrical insulator material, a semi-insulating material, and a first wide band gap semiconductor having a conductivity of a first polarity, at least a TVS device including a plurality of wide band gap semiconductor layers formed on the substrate; a first electrode coupled in electrical contact with the TVS device and extending to the contact surface, and a second electrode electrically coupled to the substrate extending to the contact surface.

Method of manufacturing a semiconductor integrated circuit device

The TSV technology has been popular as one of stacking technologies of a plurality of semiconductor chips. It has however been revealed by the present inventors that when TSV is formed using a so-called first via process, via middle process, front-via via last process, or the like, there is a possibility of defects such as gate breakdown occurring due to electrostatic breakdown in the subsequent process. In order to overcome the above problem, the present invention provides a method of manufacturing a semiconductor integrated circuit device, in which a through via electrode is formed by forming a hole in a semiconductor substrate, forming an insulating member in the hole, and burying a conductive member in the resulting hole while covering a portion of the hole except for the bottom portion with the insulating member.

Bump-on-Trace Interconnect

Disclosed herein is a bump-on-trace interconnect with a wetted trace sidewall and a method for fabricating the same. A first substrate having conductive bump with solder applied is mounted to a second substrate with a trace disposed thereon by reflowing the solder on the bump so that the solder wets at least one sidewall of the trace, with the solder optionally wetting between at least half and all of the height of the trace sidewall. A plurality of traces and bumps may also be disposed on the first substrate and second substrate with a bump pitch of less than about 100 μm, and volume of solder for application to the bump calculated based on at least one of a joint gap distance, desired solder joint width, predetermined solder joint separation, bump geometry, trace geometry, minimum trace sidewall wetting region height and trace separation distance.

Method and structure of sensors and mems devices using vertical mounting with interconnections

A method and structure for fabricating sensor(s) or electronic device(s) using vertical mounting with interconnections. The method includes providing a resulting device including at least one sensor or electronic device, formed on a die member, having contact region(s) with one or more conductive materials formed thereon. The resulting device can then be singulated within a vicinity of the contact region(s) to form one or more singulated dies, each having a singulated surface region. The singulated die(s) can be coupled to a substrate member, having a first surface region, such that the singulated surface region(s) of the singulated die(s) are coupled to a portion of the first surface region. Interconnections can be formed between the die(s) and the substrate member with conductive adhesives, solder processes, or other conductive bonding processes.

Production method for polyamide acid particles, production method for polyimide particles, polyimide particles and bonding material for electronic component

An object of the present invention is to provide a method for producing polyamide acid particles which is used as a raw material for polyimide particles with a small average particle diameter having high heat resistance. Other objects of the present invention are to provide a method for producing polyimide particles using the method for producing polyamide acid particles, and polyimide particles produced by the method for producing polyimide particles. Yet another object of the present invention is to provide a bonding material for an electronic component, which has a low linear expansion coefficient and a low elastic modulus after being cured in the temperature range equal to or less than the glass transition temperature, so that a joined body with high reliability can be produced. The present invention is a method for producing polyamide acid particles having a step of preparing a solution having a diamine compound dissolved, and a step of precipitating polyamide acid particles by adding a tetracarboxylic anhydride in a non-solution state to the solution having a diamine compound dissolved while applying a physical impact thereto.

Shaped and oriented solder joints

The present description relates to the field of fabricating microelectronic assemblies, wherein a microelectronic device may be attached to a microelectronic substrate with a plurality of shaped and oriented solder joints. The shaped and oriented solder joints may be substantially oval, wherein the major axis of the substantially oval solder joints may be substantially oriented toward a neutral point or center of the microelectronic device. Embodiments of the shaped and oriented solder joint may reduce the potential of solder joint failure due to stresses, such as from thermal expansion stresses between the microelectronic device and the microelectronic substrate.

Bonding apparatus

A bonding apparatus includes: a bonding head including a bonding tool, on which a suction surface for a chip is formed, and a heating unit; a chip supply unit; a bonding stage on which a substrate is arranged; a head movement unit configured to move the bonding head between a chip supply position by the chip supply unit and a bonding position on the bonding stage; and a cooling unit configured to cool the bonding tool. The bonding tool is configured such that the chip is supplied at the chip supply position, then is heated and bonded on the substrate at the bonding position, and is then cooled by the cooling unit. The cooling is performed by making the suction surface come in contact with a cooling surface of the cooling unit.

Simultaneous wafer bonding and interconnect joining

Disclosed are a microelectronic assembly of two elements and a method of forming same. A microelectronic element includes a major surface, and a dielectric layer and at least one bond pad exposed at the major surface. The microelectronic element may contain a plurality of active circuit elements. A first metal layer is deposited overlying the at least one bond pad and the dielectric layer. A second element having a second metal layer deposited thereon is provided, and the first metal layer is joined with the second metal layer. The assembly may be severed along dicing lanes into individual units each including a chip.

Electrical module for being received by automatic placement machines by means of generating a vacuum

The invention relates to an electrical module ( 100 ) for being received by automatic placement machines by means of generating a vacuum, comprising a carrier substrate ( 10 ), at least one component ( 20, 21 ) disposed on the carrier substrate ( 10 ), and a cover element ( 30 ) disposed above the at least one component ( 20, 21 ). A fixing component ( 40 ) by which the cover element ( 30 ) is attached to the at least one component ( 21 ) is disposed between the cover element ( 30 ) and the at least one component ( 21 ). The cover element can be implemented as a dimensionally stable, flat film by means of which it is possible to suction the module by means of vacuum for a placement method, and to place said module at a position on a circuit board.

Heatsink attachment module

An assembly process for a heatsink attachment module for a chip packaging apparatus is provided and includes attaching a semiconductor chip to a substrate to form a module subassembly, placing a load frame and shim in a fixture, dispensing adhesive to the load frame and loadably placing the module subassembly chip face down in the fixture.

Heterostructure containing ic and led and method for fabricating the same

A heterostructure containing IC and LED and a method of fabricating. An IC and an LED are established with the IC having a first electric-conduction block and a first connection block. The IC electrically connects to the first electric-conduction block. A first face of the LED has a second electric-conduction block and a second connection block. The LED is electrically connected to the second electric-conduction block. The first electric-conduction block and the first connection block are respectively joined to the second electric-conduction block and the second connection block, and the first electric-conduction block are electrically connected with the second electric-conduction block to form a heterostructure. The heterostructure provides functions of heat radiation and electric communication for IC and LED.

Semiconductor device and method for manufacturing the same

A semiconductor device includes a first semiconductor chip including a first surface and a plurality of first electrodes disposed on the first surface; a second semiconductor chip including a second surface which faces the first surface, a plurality of second electrodes each of which includes at least one end disposed on the second surface, and a plurality of first protrusions each of which surrounds the one end of each of the second electrodes on an electrode by electrode basis; a plurality of conductive joint materials each of which joins a third electrode included in the first electrodes to the one end of an electrode which faces the third electrode among the second electrodes; and a plurality of first underfill resins each of which is disposed inside one of the first protrusions and covers one of the conductive joint materials on a material by material basis.

Packaging Structures and Methods with a Metal Pillar

A package component is free from active devices therein. The package component includes a substrate, a through-via in the substrate, a top dielectric layer over the substrate, and a metal pillar having a top surface over a top surface of the top dielectric layer. The metal pillar is electrically coupled to the through-via. A diffusion barrier is over the top surface of the metal pillar. A solder cap is disposed over the diffusion barrier.

Die connections using different underfill types for different regions

Die connections are described using different underfill types for different regions. In one example, a first electrically-non-conductive underfill paste (NCP) type is applied to an I/O region of a first die. A second NCP type is applied outside the I/O region of the first die, the second NCP type having more filler than the first NCP type, and the second die is bonded to a first die using the NCP.

Lead-free solder alloy, solder joining material, electronic circuit mounting substrate, and electronic control device

A lead-free solder alloy includes 2.0% by mass or more and 4.0% by mass or less of Ag, 0.3% by mass or more and 0.7% by mass or less of Cu, 1.2% by mass or more and 2.0% by mass or less of Bi, 0.5% by mass or more and 2.1% by mass or less of In, 3.0% by mass or more and 4.0% by mass or less of Sb, 0.001% by mass or more and 0.05% by mass or less of Ni, 0.001% by mass or more and 0.01% by mass or less of Co, and the balance being Sn.

Semiconductor Device And Bump Formation Process

A semiconductor device includes a solder bump overlying and electrically connected to a pad region, and a metal cap layer formed on at least a portion of the solder bump. The metal cap layer has a melting temperature greater than the melting temperature of the solder bump. 1. A method of forming a packaging assembly , the method comprising disposing a bump structure between a semiconductor substrate and a package substrate , the bump structure electrically connecting the semiconductor substrate to the package substrate , wherein the bump structure comprises a solder bump and a metal cap layer covering at least a portion of the solder bump while a top portion of the solder bump remains exposed , and the metal cap layer has a melting temperature greater than a melting temperature of the solder bump.2. The method of claim 1 , wherein disposing the bump structure comprises the metal cap layer comprising at least one of nickel claim 1 , palladium and gold.3. The method of claim 2 , wherein disposing the bump structure further comprises the metal cap layer comprising copper.4. The method of claim 2 , wherein disposing the bump structure comprises the solder bump comprising a lead-free solder material.5. The method of claim 2 , further comprising forming the metal cap layer on a middle sidewall surface of the solder bump.6. The method of claim 2 , further comprising forming the metal cap layer on a lower sidewall surface of the solder bump and covering a bottom portion of the solder bump.7. A method of forming a semiconductor device claim 2 , the method comprising:forming a solder material layer over a semiconductor substrate, the solder material layer comprising a substantially homogenous material;forming a metal cap layer conformally over the solder material layer;removing a portion of the metal cap layer to expose at least a top portion of the solder material layer, while a remaining portion of the metal cap layer covers at least a portion of the solder material layer; ...

PACKAGING DEVICE AND METHOD OF MAKING THE SAME

The present disclosure relates to an integrated chip packaging device. In some embodiments, the packaging device has a first package component. A metal trace is arranged on a surface of the first package component. The metal trace has an undercut. A molding material fills the undercut of the metal trace and has a sloped outermost sidewall with a height that monotonically decreases from a position below a top surface of the metal trace to the surface of the first package component. A solder region is arranged over the metal trace. 1. An integrated chip packaging device , comprising:a first package component;a metal trace arranged on a surface of the first package component, wherein the metal trace comprises an undercut;a molding material that fills the undercut of the metal trace and that has a sloped outermost sidewall with a height that monotonically decreases from a position below a top surface of the metal trace to the surface of the first package component; anda solder region arranged over the metal trace.2. The device of claim 1 , wherein a top surface of the molding material is arranged between a top surface of the metal trace and the surface of the first package component.3. The device of claim 1 , further comprising:a second metal trace arranged on the surface of the first package component and comprising a second undercut, wherein the molding material fills the second undercut but does not continuously extend over the surface between the metal trace and the second metal trace.4. The device of claim 1 , wherein the solder region surrounds a top surface of the metal trace and sidewalls of the metal trace above the molding material.5. The device of claim 4 , wherein the solder region contacts the sidewalls of the metal trace above the molding material.6. The device of claim 4 , further comprising:a metal pillar arranged between the solder region and a metal pad on a surface of a second package component, wherein the second package component is disposed over ...

METHODS OF ATTACHING ELECTRONIC COMPONENTS

A method of attaching an electronic component to a metal substrate, wherein the electronic component comprises solder provided on an exposed solder region. The method comprising: forming a metal-based compound layer on the substrate; placing the electronic component on the metal substrate such that the solder region is in contact with a contact region of the metal-based compound layer; and heating the solder region such that the contact region of the metal-based compound layer dissolves and the solder region forms an electrical connection between the electronic component and the metal substrate. The metal-based compound layer can have a minimum thickness of 10 nm. 1. A method of attaching an electronic component to a metal substrate , wherein the electronic component comprises solder provided on an exposed solder region , the method comprising:forming a metal-based compound layer on the substrate, wherein the metal-based compound layer has a minimum thickness of 10 nm;placing the electronic component on the metal substrate such that the solder region is in contact with a contact region of the metal-based compound layer; andheating the solder region such that the contact region of the metal-based compound layer dissolves and the solder region forms an electrical connection between the electronic component and the metal substrate.2. The method of claim 1 , wherein the metal-based compound layer has a maximum thickness of 50 nm.3. The method of claim 1 , wherein the step of forming the metal-based compound layer on the substrate comprises exposing the metal substrate to a reactive gas.4. The method of claim 3 , wherein forming the metal-based compound layer on the substrate comprises exposing the metal substrate to the reactive gas at a temperature in the range of about 150° C. to about 250° C.5. The method of claim 3 , wherein forming the metal-based compound layer on the substrate comprises exposing the metal substrate to a reactive gas for a predetermined period of ...

Multi-die semiconductor structure with intermediate vertical side chip and semiconductor package for same

Semiconductor multi-die structures having intermediate vertical side chips, and packages housing such semiconductor multi-die structures, are described. In an example, a multi-die semiconductor structure includes a first main stacked dies (MSD) structure having a first substantially horizontal arrangement of semiconductor dies. A second MSD structure having a second substantially horizontal arrangement of semiconductor dies is also included. An intermediate vertical side chip (i-VSC) is disposed between and electrically coupled to the first and second MSD structures.

Foam composite

Devices and methods disclosed herein can include a conductive foam having pores disposed within the conductive foam. The conductive foam can be compressible between an uncompressed thickness and a compressed thickness. The compressed thickness can be ninety-five percent or less of the uncompressed thickness. In one example, a filler can be disposed in the pores of the conductive foam. The filler can include a first thermal conductivity. The first thermal conductivity can be greater than a thermal conductivity of air.

Planar integrated circuit package interconnects

Generally discussed herein are systems, methods, and apparatuses that include conductive pillars that are about co-planar. According to an example, a technique can include growing conductive pillars on respective exposed landing pads of a substrate, situating molding material around and on the grown conductive pillars, removing, simultaneously, a portion of the grown conductive pillars and the molding material to make the grown conductive pillars and the molding material about planar, and electrically coupling a die to the conductive pillars.

Bumped land grid array

A semiconductor package and methods for producing the same are described. One example of the semiconductor package is described to include a substrate having a first face and an opposing second face. The package is further described to include a plurality of solderable surfaces formed on the first face of the substrate, a first solderable surface in the plurality of solderable surfaces having a pattern plating structure on an outward facing surface of the first solderable surface. There may also be an amount of solder bonded to the outward facing surface of the first solderable surface, where the pattern plating structure on the outward facing surface of the first solderable surface causes the amount of solder to have a first thickness at its ends, a second thickness at its center, and a discrete transition between the first thickness and the second thickness.

ENHANCED CLEANING FOR WATER-SOLUBLE FLUX SOLDERING

An approach to provide an electronic assembly process that includes receiving at least one electronic assembly after a solder reflow process using a Sn-containing solder and a water-soluble flux. The approach includes baking the at least one electronic assembly in an oxygen containing environment and, then cleaning the at least one electronic assembly in an aqueous cleaning process. 1. A method for an electronic assembly process comprising:receiving at least one electronic assembly after a solder reflow process using a Sn-containing solder and a water-soluble flux;baking the at least one electronic assembly in an oxygen containing environment, andcleaning the at least one electronic assembly in an aqueous cleaning process.2. The method of claim 1 , further comprising baking the at least one electronic assembly in the oxygen containing environment within a range of temperatures from 40° Celsius to 180° Celsius.3. The method of claim 1 , further comprising baking the at least one electronic assembly in the oxygen containing environment for at least one of 60° Celsius for thirty minutes and 120° Celsius for three hours.4. The method of claim 1 , further comprising baking the at least one electronic assembly for a range of temperatures from 60° Celsius to 120° Celsius for a corresponding range of bake times from thirty minutes to three hours.5. The method of claim 1 , further comprising baking the at least one electronic assembly in an oxygen containing environment for a time less than thirty minutes with a baking temperature more than 120° Celsius.6. The method of claim 1 , further comprising baking the at least one electronic assembly in an oxygen containing environment for a time more than one hundred and eighty minutes with a baking temperature less than 60° Celsius.7. The method of claim 1 , wherein the water-soluble flux is any suitable water-soluble flux used in an electronic packaging assembly.8. The method of claim 1 , further comprises the water-soluble flux ...

Semiconductor assemblies including vertically integrated circuits and methods of manufacturing the same

Semiconductor assemblies including thermal management configurations for reducing heat transfer between vertically stacked devices and associated systems and methods are disclosed herein. In some embodiments, the semiconductor assemblies comprise at least one memory device mounted over a logic device with a thermally conductive layer, a thermal-insulator interposer, or a combination thereof disposed between the memory device and the logic device. The thermally conductive layer includes a structure configured to transfer the thermal energy across a horizontal plane. The thermal-insulator interposer includes a structure configured to reduce heat transfer between the logic device and the memory device.

Semiconductor Package and Method

In an embodiment, a device includes: a back-side redistribution structure including: a metallization pattern on a first dielectric layer; and a second dielectric layer on the metallization pattern; a through via extending through the first dielectric layer to contact the metallization pattern; an integrated circuit die adjacent the through via on the first dielectric layer; a molding compound on the first dielectric layer, the molding compound encapsulating the through via and the integrated circuit die; a conductive connector extending through the second dielectric layer to contact the metallization pattern, the conductive connector being electrically connected to the through via; and an intermetallic compound at the interface of the conductive connector and the metallization pattern, the intermetallic compound extending only partially into the metallization pattern.

Electronic circuit device and method of manufacturing electronic circuit device

The electronic circuit device according to the present invention including the wiring layer 13 including a plurality of the metal wirings, the photosensitive resin layer 21 made of the photosensitive resin arranged on the wiring layer 13, and the first electronic circuit element 33 arranged in the photosensitive resin layer 21. In this electronic circuit device, a plurality of opening 41 for exposing a part of the wiring layer 13 is formed on the photosensitive resin layer 21, and further, together with three-dimensionally connected to the first electronic circuit element 33, the re-distribution layer 42 on the first electronic circuit element including a plurality of the metal wirings which is three-dimensionally connected via a plurality of openings to a part of the wiring layer 13, and the first external connection terminal 51 connected to the re-distribution layer 42 are formed.

Multi-Stacked Package-on-Package Structures

A multi-stacked package-on-package structure includes a method. The method includes: adhering a first die and a plurality of second dies to a substrate, the first die having a different function from each of the plurality of second dies; attaching a passive device over the first die; encapsulating the first die, the plurality of second dies, and the passive device; and forming a first redistribution structure over the passive device, the first die, and the plurality of second dies, the passive device connecting the first die to the first redistribution structure.

Semiconductor Device Package and Method

In an embodiment, a method includes: stacking a plurality of first dies to form a device stack; revealing testing pads of a topmost die of the device stack; testing the device stack using the testing pads of the topmost die; and after testing the device stack, forming bonding pads in the topmost die, the bonding pads being different from the testing pads.

Multi-Chip Structure and Method of Forming Same

A device includes a first chip is embedded in a molding compound layer, wherein the first chip is shifted toward a first direction, a second chip over the first chip and embedded in the molding compound layer, wherein the second chip is shifted toward a second direction opposite to the first direction and a plurality of bumps between the first chip and the second chip. 1. A device comprising:a first chip is embedded in a molding compound layer, wherein the first chip is shifted toward a first direction;a second chip over the first chip and embedded in the molding compound layer, wherein the second chip is shifted toward a second direction opposite to the first direction; anda plurality of bumps between the first chip and the second chip.2. The device of claim 1 , further comprising:a redistribution layer over the molding compound layer;a dielectric layer over the redistribution layer;an under bump metallization structure over the dielectric layer; anda solder ball over the under bump metallization structure.3. The device of claim 2 , wherein:the first chip comprises a plurality of logic circuits, wherein the first chip comprise a plurality of through vias connected to the redistribution layer; andthe second chip comprises a plurality of memory dies stacked together, wherein the second chip is electrically connected to the first chip through the plurality of bumps.4. The device of claim 2 , wherein:the redistribution layer extends beyond at least one outmost edge of the first chip.5. The device of claim 2 , wherein:the second chip and the redistribution layer are separated by the molding compound layer.6. The device of claim 1 , wherein:a top surface of the second chip is exposed outside the molding compound layer.7. The device of claim 1 , wherein:a first sidewall of the first chip is exposed outside the molding compound layer;a second sidewall of the first chip is covered by the molding compound layer and underneath the second chip;a first sidewall of the second ...

Through-silicon via pillars for connecting dice and methods of assembling same

Reduced-profile semiconductor device apparatus are achieved by thinning a semiconductive device substrate at a backside surface to expose a through-silicon via pillar, forming a recess to further expose the through-silicon via pillar, and by seating an electrical bump in the recess to contact both the through-silicon via pillar and the recess. In an embodiment, the electrical bump contacts a semiconductor package substrate to form a low-profile semiconductor device apparatus. In an embodiment, the electrical bump contacts a subsequent die to form a low-profile semiconductor device apparatus.

MICROELECTRONIC DEVICE INTERCONNECT STRUCTURE

A microelectronic device is formed including two or more structures physically and electrically engaged with one another through coupling of conductive features on the two structures. The conductive features may be configured to be tolerant of bump thickness variation in either of the structures. Such bump thickness variation tolerance can result from a contact structure on a first structure including a protrusion configured to extend in the direction of the second structure and to engage a deformable material on that second structure. 1. A microelectronic device , comprising:a first interconnect structure comprising first multiple contact structures on a first surface; a respective first portion with a first lateral dimension proximate a dielectric structure of the second interconnect structure, and', 'a protrusion extending from the respective first portion in a direction toward the first interconnect structure, the protrusion having a second portion with a second lateral dimension less than the first lateral dimension of the first portion of the contact structure; and, 'a second interconnect structure comprising second multiple contact structures on a second surface in positions to be coupled to respective first multiple contact structures, the second multiple contact structures each having,'}a deformable material establishing electrical and mechanical contact between the first multiple contact structures of the first interconnect structure and respective second multiple contact structures of the second interconnect structure.2. The microelectronic device of claim 1 , wherein a first plurality of the second multiple contact structures each include a bond pad having a planar contact surface forming the first portion claim 1 , and wherein the protrusion extends relative to the planar contact surface.3. The microelectronic device of claim 1 , wherein the first multiple contact structures comprise:a first plurality of contact structures, each of a first lateral ...

Fan-Out Package with Cavity Substrate

Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.

3D Packaging Method for Semiconductor Components

The present disclosure relates to a method for bonding semiconductor components. A semiconductor component comprising microbumps on a planar bonding surface is prepared for bonding by applying a photosensitive polymer layer on the bonding surface. The average thickness of the initial polymer layer in between the microbumps is similar to the average height of the microbumps. In a lithography process, the polymer is removed from the upper surface of the microbumps and from areas around the microbumps. The polymer is heated to a temperature at which the polymer flows, resulting in a polymer layer that closely adjoins the microbumps, without exceeding the microbump height. The closely adjoining polymer layer may have a degree of planarity substantially similar to a planarized layer.

Metal pad modification

The present invention provides a structure. In an exemplary embodiment, the structure includes a base material, at least one metal pad, where a first surface of the metal pad is in contact with the base material, and a metal pedestal, where the metal pedestal is in contact with the metal pad, where a radial alignment of the metal pad is shifted by an offset distance, with respect to the metal pedestal, such that the metal pad is shifted towards a center axis of the base material, where a first dimension of the metal pad is smaller than a second dimension of the metal pad, where the second dimension is orthogonal to a line running from a center of the metal pad to the center axis of the base material, where the first dimension is parallel to the line.

LEAD-FREE SOLDER JOINING OF ELECTRONIC STRUCTURES

A method and structure for joining a semiconductor device and a laminate substrate or two laminate substrates where the joint is formed with lead free solders and lead free compositions. The various lead free solders and lead free compositions are chosen so that there is a sufficient difference in liquidus temperatures such that some components may be joined to, or removed from, the laminate substrate without disturbing other components on the laminate substrate. 1. A method of joining a semiconductor structure comprising:forming a first low melting temperature lead free solder having a liquidus temperature less than 230° C. on a first substrate;placing a lead free ball comprising copper and tin having a liquidus temperature greater than 250° C. on the first low melting temperature lead free solder;reflowing the first low melting temperature lead free solder at a temperature lower than the liquidus temperature of the lead free ball;annealing at a temperature of 140 to 165° C. to convert the first low melting temperature lead free solder into a higher melting temperature lead free solder having a liquidus temperature of 240 to 250° C.;placing a second low melting temperature lead free solder having a liquidus temperature of 220° C. or less on a second substrate;placing the lead free ball in direct contact with the second low melting temperature lead free solder; andheating at 240 to 260° C. the semiconductor structure to cause the second low melting temperature lead free solder to reflow and join with the lead free ball.2. The method of wherein the first low melting temperature lead free solder and the second low melting temperature lead free solder each comprise an alloy of tin claim 1 , silver and copper.3. The method of wherein the lead free ball has a liquidus temperature of 250-280 C.4. The method of wherein the lead free ball is an alloy comprising tin/silver/nickel/copper/gold having the composition claim 1 , in weight percent claim 1 , of 0.01 to 6% copper ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, a first metal layer located on the first semiconductor substrate, a second metal layer located on the second semiconductor substrate, a third metal layer, a first alloy layer, and a second alloy layer. The third metal layer extends between the first metal layer and the second metal layer. The first alloy layer comprises components of the first and third metal layers, and is provided between the first metal layer and the third metal layer. The second alloy layer comprises components of the second and third metal layers, and is provided between the second metal layer and the third metal layer. At least one of the first metal the second metal layers projects into the third metal layer at a circumferential edge portion thereof. 1. A semiconductor device comprising:a first semiconductor substrate;a second semiconductor substrate facing the first semiconductor substrate;a first pad electrode disposed on a surface of the first semiconductor substrate facing the second semiconductor substrate;a second pad electrode disposed on a surface of the second semiconductor substrate facing the first semiconductor substrate;a first insulating layer disposed on an edge portion of the first pad electrode and the first semiconductor substrate;a second insulating layer disposed on an edge portion of the second pad electrode and the second semiconductor substrate;a first metal layer disposed over the first pad electrode and facing the second semiconductor substrate;a second metal layer disposed over the second pad electrode and facing the first semiconductor substrate;a third metal layer disposed between the first metal layer and the second metal layer;a first alloy layer disposed between the first metal layer and the third metal layer and comprising a component of the first metal layer and a component of the third metal layer; anda second alloy layer disposed between the second metal layer ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

According to one embodiment, a method of manufacturing a semiconductor device includes forming a metal bump on a first surface side of a semiconductor chip, positioning the semiconductor chip so the metal bump contacts a pad of an interconnection substrate, and applying a first light from a second surface side of the semiconductor chip and melting the metal bump with the first light. After the melting, the melted metal bump is allowed to resolidify by stopping or reducing the application of the first light. The semiconductor chip is then pressed toward the interconnection substrate. A second light is then applied from the second surface side of the semiconductor chip while the semiconductor chip is being pressed toward the interconnection substrate to melt the metal bump. After the melting, the melted metal bump is allowed to resolidify by the stopping or reducing of the application of the second light. 1. A method of manufacturing a semiconductor device , the method comprising:forming a metal bump on a first surface side of a semiconductor chip;positioning the semiconductor chip so the metal bump contacts a pad of an interconnection substrate;applying a first light from a second surface side of the semiconductor chip and melting the metal bump with the first light;allowing the melted metal bump to resolidify by stopping or reducing the application of the first light;pressing the semiconductor chip toward the interconnection substrate after the stopping or reducing of the application of the first light;applying a second light from the second surface side of the semiconductor chip while pressing the semiconductor chip toward the interconnection substrate to melt the metal bump; andallowing the melted metal bump to resolidify by stopping or reducing the application of the second light.2. The method according to claim 1 , wherein the application of the second light is stopped or reduced when the pressing is stopped.3. The method according to claim 1 , whereinthe ...

BRIDGE INTERCONNECT WITH AIR GAP IN PACKAGE ASSEMBLY

Embodiments of the present disclosure are directed towards techniques and configurations for a bridge interconnect assembly that can be embedded in a package assembly. In one embodiment, a package assembly includes a package substrate configured to route electrical signals between a first die and a second die and a bridge embedded in the package substrate and configured to route the electrical signals between the first die and the second die, the bridge including a bridge substrate, one or more through-hole vias (THVs) formed through the bridge substrate, and one or more traces disposed on a surface of the bridge substrate to route the electrical signals between the first die and the second die. Routing features including traces and a ground plane of the bridge interconnect assembly may be separated by an air gap. Other embodiments may be described and/or claimed. 119-. (canceled)20. A method , comprising:forming a sacrificial layer on a surface of a bridge substrate comprising a glass, ceramic, or a semiconductor material;forming an electrically conductive layer on the sacrificial layer, the electrically conductive layer being coupled with the surface of the bridge substrate through the sacrificial layer by an electrically conductive material; andremoving material of the sacrificial layer to provide an air gap between the surface of the bridge substrate and the electrically conductive layer.21. The method of claim 20 , further comprising:prior to forming the sacrificial layer, forming electrical routing features through the bridge substrate and on the surface of the bridge substrate, the electrical routing features including through-hole vias, traces, and pads.22. The method of claim 20 , wherein forming the sacrificial layer comprises depositing silicon oxide (SiO).23. The method of claim 21 , further comprising:prior to forming the electrically conductive layer, forming openings in the sacrificial layer to expose one or more of the electrical routing features; ...

Electronic apparatus and method for fabricating the same

An electronic apparatus includes a first electronic part with a first terminal, a second electronic part with a second terminal opposite the first terminal, and a joining portion which joins the first terminal and the second terminal. The joining portion contains a pole-like compound extending in a direction in which the first terminal and the second terminal are opposite to each other. The joining portion contains the pole-like compound, so the strength of the joining portion is improved. When the first terminal and the second terminal are joined, the temperature of one of the first electronic part and the second electronic part is made higher than that of the other. A joining material is cooled and solidified in this state. By doing so, the pole-like compound is formed.

Thin Wafer Handling and Known Good Die Test Method

A method of attaching a microelectronic element to a substrate can include aligning the substrate with a microelectronic element, the microelectronic element having a plurality of spaced-apart electrically conductive bumps each including a bond metal, and reflowing the bumps. The bumps can be exposed at a front surface of the microelectronic element. The substrate can have a plurality of spaced-apart recesses extending from a first surface thereof. The recesses can each have at least a portion of one or more inner surfaces that are non-wettable by the bond metal of which the bumps are formed. The reflowing of the bumps can be performed so that at least some of the bond metal of each bump liquefies and flows at least partially into one of the recesses and solidifies therein such that the reflowed bond material in at least some of the recesses mechanically engages the substrate. 1. A method of attaching a microelectronic element to a substrate , comprising:aligning the substrate with a microelectronic element, the microelectronic element having a plurality of spaced-apart electrically conductive bumps each including a bond metal, the bumps exposed at a front surface of the microelectronic element, the substrate having a plurality of spaced-apart recesses extending from a first surface thereof, the recesses each having at least a portion of one or more inner surfaces that are non-wettable by the bond metal of which the bumps are formed; andreflowing the bumps so that at least some of the bond metal of each bump liquefies and flows at least partially into one of the recesses and solidifies therein such that the reflowed bond material in at least some of the recesses mechanically engages the substrate.2. The method as claimed in claim 1 , wherein the substrate is a handling substrate claim 1 , and all of the inner surfaces of at least some of the recesses are non-wettable by the bond metal of which the bumps are formed.3. The method as claimed in claim 1 , wherein the ...

Self-Alignment for Redistribution Layer

An apparatus comprising a substrate with multiple electronic devices. An interconnect structure formed on a first side of the substrate interconnects the electronic devices. Dummy TSVs each extend through the substrate and form an alignment mark on a second side of the substrate. Functional TSVs each extend through the substrate and electrically connect to the electronic devices. A redistribution layer (RDL) formed on the second side of the substrate interconnects ones of the dummy TSVs with ones of the functional TSVs. Step heights of the RDL over the functional TSVs are less than a predetermined value, whereas step heights of the RDL over the dummy TSVs are greater than the predetermined value. 1. A method comprising:forming a functional through via (TV) within a die area of a substrate, the functional TV having a first protruding portion extending above a first surface of the substrate by a first height;forming an alignment mark within a die street region of the substrate, the die street region of the substrate surrounding the die area of the substrate, the alignment mark comprising a dummy TV, the dummy TV having a second protruding portion extending above the first surface of the substrate by a second height, the second height being equal to the first height;reducing the first height of the first protruding portion of the functional TV by a first amount; andreducing the second height of the second protruding portion of the dummy TV by a second amount, the second amount being less than the first amount.2. The method of claim 1 , further comprising:before reducing the first height of the first protruding portion of the functional TV and the second height of the second protruding portion of the dummy TV, forming a dielectric layer over the first surface of the substrate, the first protruding portion of the functional TV and the second protruding portion of the dummy TV; andbefore reducing the first height of the first protruding portion of the functional TV and ...

Semiconductor Devices, Methods of Manufacture Thereof, and Semiconductor Device Packages

Semiconductor devices, methods of manufacture thereof, and semiconductor device packages are disclosed. In one embodiment, a semiconductor device includes an insulating material layer having openings on a surface of a substrate. One or more insertion bumps are disposed over the insulating material layer. The semiconductor device includes signal bumps having portions that are not disposed over the insulating material layer. 1. A method of manufacturing a semiconductor device , the method comprising:forming a insulating material layer over a first substrate;removing a first portion of the insulating material layer to expose a contact pad at a top surface of the first substrate;forming one or more first insertion bumps over the insulating material layer; andwhile forming the one or more first insertion bumps, forming a first signal bump extending through the insulating material layer and electrically connected to the contact pad.2. The method according to claim 1 , wherein forming the one or more first insertion bumps and forming the first signal bump comprises:patterning a mask to form a first opening over the contact pad on the top surface of the first substrate, and to form one or more second openings over one or more areas of the insulating material layer over which the one or more first insertion bumps will be formed;performing a first plating process with a first conductive material to deposit the first conductive material in the first opening and the one or more second openings; andremoving the mask.3. The method according to claim 2 , further comprising:before removing the mask, performing a second plating process with a second conductive material to deposit the second conductive material in the first opening of the mask and the one or more second openings of the mask, wherein the second conductive material is different than the first conductive material.4. The method according to claim 2 , further comprising patterning the insulating material layer to remove ...

MULTI TERMINAL CAPACITOR WITHIN INPUT OUTPUT PATH OF SEMICONDUCTOR PACKAGE INTERCONNECT

A semiconductor package, e.g., wafer, chip, interposer, etc. includes a multi terminal capacitor within an input output (IO) path. The multi terminal capacitor is electrically attached directly upon a first IO contact of the semiconductor package. There is no inductance between the multi terminal capacitor and an interconnect that electrically connects the first IO contact with a second IO contact of a second semiconductor package and no inductance between the multi terminal capacitor and the first IO contact. The multi terminal capacitor may serve as a power source to cycle the turning on and off of the various circuits within a semiconductor chip associated with the semiconductor package. Because the distance between the multi terminal capacitor and semiconductor chip is reduced, inductance within the system is resultantly reduced. The multi terminal capacitor may be a decoupling capacitor that decouples one part of semiconductor chip from another part of semiconductor chip. 1. A semiconductor device fabrication method comprising:forming a solder mask upon a lower surface of a semiconductor chip carrier;forming a first opening and a neighboring second opening in the solder mask to expose a first input output (IO) contact and a neighboring second IO contact of the semiconductor chip carrier;attaching a multi terminal capacitor to the semiconductor chip carrier such that a first terminal contacts the first IO contact and a second terminal contacts the second IO contact; andinterconnecting the semiconductor chip carrier with a carrier interposer with solder interconnects such that a first solder interconnect directly contacts the first terminal and the first IO contact and a second solder interconnect directly contacts the second terminal and the second IO contact.2. The semiconductor device fabrication method of claim 1 , wherein there is no inductance between the first solder interconnect and the first terminal and between the first solder interconnect and the ...

Semiconductor Device and Method of Forming PoP Semiconductor Device with RDL Over Top Package

A PoP semiconductor device has a top semiconductor package disposed over a bottom semiconductor package. The top semiconductor package has a substrate and a first semiconductor die disposed over the substrate. First and second encapsulants are deposited over the first semiconductor die and substrate. A first build-up interconnect structure is formed over the substrate after depositing the second encapsulant. The top package is disposed over the bottom package. The bottom package has a second semiconductor die and modular interconnect units disposed around the second semiconductor die. A second build-up interconnect structure is formed over the second semiconductor die and modular interconnect unit. The modular interconnect units include a plurality of conductive vias and a plurality of contact pads electrically connected to the conductive vias. The I/O pattern of the build-up interconnect structure on the top semiconductor package is designed to coincide with the I/O pattern of the modular interconnect units.

Package assembly

In some embodiments, the present disclosure relates to a package assembly having a bump on a first substrate. A molding compound is on the first substrate and contacts sidewalls of the bump. A no-flow underfill layer is on a conductive region of a second substrate. The no-flow underfill layer and the conductive region contact the bump. A mask layer is arranged on the second substrate and laterally surrounds the no-flow underfill layer. The no-flow underfill layer contacts the substrate between the conductive region and the mask layer.

Thermal transfer structures for semiconductor die assemblies

Several embodiments of the present technology are described with reference to a semiconductor die assembly and processes for manufacturing the assembly. In some embodiments of the present technology, a semiconductor die assembly includes a stack of semiconductor dies attached to a thermal transfer structure (also known as a “heat spreader,” “lid,” or “thermal lid”). The thermal transfer structure conducts heat away from the stack of semiconductor dies. Additionally, the assembly can include molded walls fabricated with molding material to support the thermal transfer structure.

METHODS OF FORMING BONDED SEMICONDUCTOR STRUCTURES, AND SEMICONDUCTOR STRUCTURES FORMED BY SUCH METHODS

Methods of forming bonded semiconductor structures include providing a first semiconductor structure including a device structure, bonding a second semiconductor structure to the first semiconductor structure below about 400° C., forming a through wafer interconnect through the second semiconductor structure and into the first semiconductor structure, and bonding a third semiconductor structure to the second semiconductor structure on a side thereof opposite the first semiconductor structure. In additional embodiments, a first semiconductor structure is provided. Ions are implanted into a second semiconductor structure. The second semiconductor structure is bonded to the first semiconductor structure. The second semiconductor structure is fractured along an ion implant plane, a through wafer interconnect is formed at least partially through the first and second semiconductor structures, and a third semiconductor structure is bonded to the second semiconductor structure on a side thereof opposite the first semiconductor structure. Bonded semiconductor structures are formed using such methods. 1. A method of forming a bonded semiconductor structure , comprising: providing a first semiconductor structure comprising at least one device structure;bonding a second semiconductor structure to the first semiconductor structure at a temperature or temperatures below about 400° C.;forming at least one through wafer interconnect through the second semiconductor structure and into the first semiconductor structure to the at least one device structure; andbonding the second semiconductor structure on a side thereof opposite the first semiconductor structure to a third semiconductor structure.2. The method of claim 1 , wherein bonding the second semiconductor structure to the first semiconductor structure comprises:bonding a relatively thicker semiconductor structure to the first semiconductor structure; andthinning the relatively thicker semiconductor structure to form the second ...

Interconnect structures for assembly of semiconductor structures including superconducting integrated circuits

A multi-layer semiconductor structure includes a first semiconductor structure and a second semiconductor structure, with at least one of the first and second semiconductor structures provided as a superconducting semiconductor structure. The multi-layer semiconductor structure also includes one or more interconnect structures. Each of the interconnect structures is disposed between the first and second semiconductor structures and coupled to respective ones of interconnect pads provided on the first and second semiconductor structures. Additionally, each of the interconnect structures includes a plurality of interconnect sections. At least one of the interconnect sections includes at least one superconducting and/or a partially superconducting material.

NON-DESTRUCTIVE TESTING OF INTEGRATED CIRCUIT CHIPS

Semiconductor devices and electronics packaging methods include integrated circuit chips having redundant signal bond pads along with signal bond pads connected to the same signal port for non-destructive testing of the integrated circuit chips prior to packaging. Electrical testing is made via the redundant signal bond after which qualified integrated circuit chips can be attached to a pristine and bumped final interposer or printed circuit board to provide increased reliability to the assembled electronic package. 110-. (canceled)12. The integrated circuit chip of claim 11 , wherein the at least one redundant signal bond pad and the at least one final signal bond pad are different sizes.13. The integrated circuit chip of claim 11 , wherein the test fixture comprises a probe and the at least one redundant signal bond pad has square-shape claim 11 , circular-shape claim 11 , or asymmetrical shape.14. The integrated circuit chip of claim 11 , wherein the at least one redundant signal bond pad and the at least one signal bond pad on the chip are formed of a superconducting material.15. The integrated circuit chip of claim 11 , wherein the test fixture comprises a probe and the at least one redundant signal bond pad is located such that the probe does not has square-shape claim 11 , circular-shape claim 11 , or asymmetrical shape.1619-. (canceled)20. A semiconductor device comprising:an integrated circuit chip comprising a first signal bond pad and a second signal bond pad connected to the same signal port, wherein the first signal bond pad has a greater lateral width than the second signal bond pad and is configured for testing the chip prior to packaging, and wherein the second signal bond pad is configured for packaging with an interposer or a printed circuit board.21. The semiconductor device of claim 20 , wherein the first signal bond pad and the second signal bond pad are of different sizes.22. The semiconductor device of claim 20 , wherein the first signal bond ...

NON-DESTRUCTIVE TESTING OF INTEGRATED CIRCUIT CHIPS

Semiconductor devices and electronics packaging methods include integrated circuit chips having redundant signal bond pads along with signal bond pads connected to the same signal port for non-destructive testing of the integrated circuit chips prior to packaging. Electrical testing is made via the redundant signal bond after which qualified integrated circuit chips can be attached to a pristine and bumped final interposer or printed circuit board to provide increased reliability to the assembled electronic package. 1. A method of testing an integrated circuit chip , the method comprising:fabricating an integrated circuit chip comprising at least one redundant signal bond pad and at least one final signal bond pad, wherein the at least one redundant signal bond pad and at the least one final signal bond pad are connected to the same signal port;contacting the at least one redundant signal bond pad to a test fixture in electrical communication with electrical evaluation equipment; andelectrically testing the chip with the electrical evaluation equipment.2. The method of further comprising selecting out qualified ones of the integrated circuit chips; and coupling the at least one final signal bond pad of the qualified ones to a final interposer or printed circuit board claim 1 , wherein the final signal bond pad is pristine and has not been previously bonded to a bump or reworked.3. The method of claim 1 , wherein the test fixture comprises a probe.4. The method of claim 1 , wherein the test fixture comprises a wirebond.5. The method of claim 1 , wherein the test fixture comprises a test interposer comprising a test socket coupled to an electrical conductive pad claim 1 , wherein a solder bump is formed on the electrically conductive pad and configured to contact the at least one redundant signal bond pad claim 1 , wherein the test socket is in electrical communication with electrical evaluation equipment.6. The method of claim 2 , wherein selecting out the qualified ...

WIRING BOARD, ELECTRONIC DEVICE, AND WIRING BOARD MANUFACTURING METHOD

A wiring board includes: an insulating layer that includes a first surface over which an electronic component is mounted and a second surface opposite to the first surface; a conductive layer that is disposed on the second surface; a via that is provided inside a first through-hole that penetrates a portion between the first surface and the second surface of the insulating layer; an electrode that is disposed on the first surface and connected to the via; and a glass plate that is not contact with the conductive layer and is disposed on the first surface and includes a second through-hole through which the electrode is disposed. 1. A wiring board comprising:an insulating layer that includes a first surface over which an electronic component is mounted and a second surface opposite to the first surface;a conductive layer that is disposed on the second surface;a via that is provided inside a first through-hole that penetrates a portion between the first surface and the second surface of the insulating layer;an electrode that is disposed on the first surface and connected to the via; anda glass plate that is not contact with the conductive layer and is disposed on the first surface and includes a second through-hole through which the electrode is disposed.2. The wiring board of claim 1 ,wherein the electrode is smaller than an opening of the second through-hole in a planar view.3. The wiring board of claim 1 ,wherein the second through-hole includes an annular convex portion protruding in a tapered shape on an inner side of the opening along the opening so as to be an opening diameter smaller than those of the first opening and the second opening between a first opening in the first surface and a second opening in the second surface.4. The wiring board of claim 1 ,wherein the second through-hole has a truncated cone shape in which the first opening in the first surface is greater than the second opening in the second surface or the first opening in the first surface is ...

CONDUCTIVE BALL AND ELECTRONIC DEVICE

A conductive ball includes a copper ball, a nickel layer formed with being patterned on an outer surface of the copper ball, and a tin-based solder covering each outer surface of the copper ball and the nickel layer. 1. A conductive ball comprising:a copper ball;a nickel layer formed with being patterned on an outer surface of the copper ball; anda tin-based solder covering each outer surface of the copper ball and the nickel layer.2. The conductive ball according to claim 1 , wherein an area of the copper ball exposed from the nickel layer is adjusted so that copper in the copper ball is diffused into the tin-based solder and a copper concentration in the tin-based solder becomes 0.7 wt % to 3 wt % when reflow heating the tin-based solder.3. The conductive ball according to claim 1 , wherein the nickel layer has at least one opening region and the outer surface of the copper ball is exposed from the opening region of the nickel layer.4. An electronic device comprising:a lower electronic member having a first connection pad;an upper electronic member arranged above the lower electronic member and having a second connection pad; anda conductive ball configured to interconnect the first connection pad of the lower electronic member and the second connection pad of the upper electronic member,wherein the conductive ball comprises:a copper ball,a nickel layer formed with being patterned on an outer surface of the copper ball, anda tin-based solder covering each outer surface of the copper ball and the nickel layer.5. The electronic device according to claim 4 ,{'sub': 6', '5, 'b': '14', 'wherein a (Cu, Ni)Snlayer is formed between the nickel layer and the tin-based solder () of the conductive ball, and'}{'sub': 3', '6', '5, 'wherein a CuSn layer and a (Cu, Ni)Snlayer are formed in order from below between the copper ball exposed from the nickel layer of the conductive ball and the tin-based solder.'}6. The electronic device according to claim 4 , wherein each surface of ...

CONDUCTIVE BALL AND ELECTRONIC DEVICE

A conductive ball includes a copper ball, a nickel layer covering an outer surface of the copper ball, a copper layer covering an outer surface of the nickel layer, and a tin-based solder covering an outer surface of the copper layer. A copper weight of the copper layer relative to a summed weight of the tin-based solder and the copper layer is 0.7 wt % to 3 wt %. 1. A conductive ball comprising:a copper ball;a nickel layer covering an outer surface of the copper ball;a copper layer covering an outer surface of the nickel layer, anda tin-based solder covering an outer surface of the copper layer,wherein a copper weight of the copper layer relative to a summed weight of the tin-based solder and the copper layer is 0.7 wt % to 3 wt %.2. The conductive ball according to claim 1 , wherein a concentration of copper in the copper layer claim 1 , which is to diffuse into the tin-based solder when the tin-based solder is reflow heated claim 1 , is 0.7 wt % to 3 wt %.3. The conductive ball according to claim 1 , wherein the tin-based solder is one of a tin/bismuth solder claim 1 , a tin/silver solder claim 1 , and a tin/bismuth/nickel solder.4. An electronic device comprising:a lower electronic member having a first connection pad;an upper electronic member arranged above the lower electronic member and having a second connection pad; anda conductive ball configured to interconnect the first connection pad of the lower electronic member and the second connection pad of the upper electronic member, a copper ball,', 'a nickel layer covering an outer surface of the copper ball, and', 'a tin-based solder covering an outer surface of the nickel layer, and, 'wherein the conductive ball comprises{'sub': 6', '5, 'wherein a (Cu, Ni)Snlayer is formed between the nickel layer and the tin-based solder.'}5. The electronic device according to claim 4 , wherein each surface of the first connection pad and the second connection pad is a nickel layer or a copper layer claim 4 , and{'sub': 6 ...

Tall and fine pitch interconnects

Representative implementations of devices and techniques provide interconnect structures and components for coupling various carriers, printed circuit board (PCB) components, integrated circuit (IC) dice, and the like, using tall and/or fine pitch physical connections. Multiple layers of conductive structures or materials are arranged to form the interconnect structures and components. Nonwettable barriers may be used with one or more of the layers to form a shape, including a pitch of one or more of the layers.

METHOD FOR PRODUCING SEMICONDUCTOR CHIP

A method for producing a semiconductor chip is a method for producing a semiconductor chip that includes a substrate, a conductive portion formed on the substrate, and a microbump formed on the conductive portion, which includes a smooth surface formation process of forming a smooth surface on the microbump, and the smooth surface formation process includes a heating process of causing a reducing gas to flow in an inert atmosphere into a space where the semiconductor chips are arranged and heated at or higher than a temperature of a melting point of the microbump, and in the heating process, a pressure application member is mounted on the microbump and among principal surfaces of the pressure application member, a principal surface that contacts the microbump is a flat surface. 1. A method for producing a semiconductor chip that includes a substrate , a conductive portion formed on the substrate , and a microbump formed on the conductive portion , comprising:a smooth surface formation process of forming a smooth surface on the microbump, andthe smooth surface formation process includes a heating process of causing a reducing gas to flow in an inert atmosphere into a space where the semiconductor chips are arranged and heated at or higher than a temperature of a melting point of the microbump, andin the heating process, a pressure application member is mounted on the microbump andamong principal surfaces of the pressure application member, a principal surface that contacts the microbump is a flat surface.2. A method for producing a semiconductor chip according to claim 1 , wherein in the heating process claim 1 , a pressure application member is mounted on a plurality of the microbumps claim 1 , andamong principal surfaces of the pressure application member, a principal surface that contacts a plurality of microbumps is a flat surface.3. A method for producing a semiconductor chip according to claim 1 , wherein as the reducing gas claim 1 , carboxylic acid is applied ...

Substrate design for semiconductor packages and method of forming same

A device includes a first die, a second die, one or more redistribution layers (RDLs) electrically connected to the first die, a plurality of connectors on a surface of the one or more RDLs and a package substrate electrically connected to the first die and the second die. The package substrate is electrically connected to the first die through the one or more RDLs and the plurality of connectors. The package substrate comprises a cavity, and the second die is at least partially disposed in the cavity.

Substrate Pad Structure

A method includes forming a plurality of vias in a dielectric layer and over a package substrate and forming a plurality of top pads over the dielectric layer, each of the plurality of top pads being connected to a respective via of the plurality of vias, wherein the plurality of top pads includes a first group, a second group, a third group and a fourth group, wherein the first group is separated from the fourth group by a first pad line, wherein the first group is separated from the second group by a second pad line, the first pad line comprising a plurality of first elongated pads, the second pad line comprising a plurality of second elongated pads, the second pad line being orthogonal to the first pad line. 1. A method comprising:forming a plurality of first elongated pads in a package substrate comprising active circuits;forming a plurality of vias over the plurality of first elongated pads and connected to respective first elongated pads; andforming a plurality of second elongated pads over the vias, wherein the plurality of second elongated pads includes a first group, a second group, a third group and a fourth group separated by a first pad line and a second pad line, and wherein a longitudinal axis of a first elongated pad of the first group is orthogonal to a longitudinal axis of a second elongated pad of the third group.2. The method of claim 1 , wherein:longitudinal axes of the second elongated pads of the first group and longitudinal axes of the second elongated pads of the third group are oriented in a first direction; andlongitudinal axes of the second elongated pads of the second group and longitudinal axes of the second elongated pads of the fourth group are oriented in a second direction.3. The method of claim 2 , wherein:the first direction is orthogonal to the second direction.4. The method of claim 1 , wherein:the first pad line is orthogonal to the second pad line.5. The method of claim 1 , wherein:the plurality of second elongated pads is over ...

LED MODULE AND METHOD FOR FABRICATING THE SAME

Disclosed is a method for fabricating an LED module. The method includes: constructing a chip-on-carrier including a chip retainer having a horizontal bonding plane and a plurality of LED chips in which electrode pads are bonded to the bonding plane of the chip retainer; and transferring the plurality of LED chips in a predetermined arrangement from the chip retainer to a substrate by transfer printing. The transfer printing includes: primarily section-wise exposing a transfer tape to reduce the adhesive strength of the transfer tape such that bonding areas are formed at predetermined intervals on the transfer tape; and pressurizing the transfer tape against the LED chips on the chip retainer to attach the LED chips to the corresponding bonding areas of the transfer tape and detaching the electrode pads of the LED chips from the chip retainer to pick up the chips. 1. A micro LED display module comprising;a substrate;a plurality of electrode patterns formed on the substrate, each of which includes a first individual electrode pad, a second individual electrode pad, a third individual electrode pad and a common electrode pad; anda plurality of groups of LED chips arranged in a matrix on the substrate and each of the groups of LED chips comprise a first LED chip, a second LED chip and a third LED chip arrayed in a line, and the first LED chip bonded the first individual electrode pad and the common electrode pad, the second LED chip bonded the second individual electrode pad and the common electrode pad, and the third LED chip bonded the third individual electrode pad and the common electrode pad,wherein the plurality of groups of LED chips included a first interval formed between the first LED chip and the second LED chip and a second interval formed between the second LED chip and the third LED chip,wherein the first interval and the second interval is same in the lengthwise direction.2. The micro LED display module according to claim 1 , wherein distances of the LED ...

SEMICONDUCTOR PACKAGE

A semiconductor package includes a substrate, a first chip on the substrate, a second chip on the substrate and arranged side-by-side with the first chip, and a support structure on the second chip. A width of the support structure is equal to or greater than a width of the second chip. 1. A semiconductor package , comprising:a substrate;at least one first chip on an upper surface of the substrate;a second chip on the upper surface of the substrate and located beside the at least one first chip as viewed in a plan view; anda support structure on the second chip,wherein a width of the support structure, in a direction parallel to the upper surface of the substrate, is equal to or greater than a width of the second chip in said direction.2. The semiconductor package of claim 1 , wherein a distance from the upper surface of the substrate to a top surface of the support structure is substantially the same as a distance from the upper surface of the substrate to a top surface of an uppermost one the at least one first chip.3. The semiconductor package of claim 1 , wherein the support structure comprises a block of insulating material claim 1 , a dummy chip claim 1 , or a memory chip.4. The semiconductor package of claim 1 , wherein the support structure comprises silicon (Si).5. The semiconductor package of claim 1 , wherein each said at least one first chip is a memory chip claim 1 , andthe second chip is a logic chip.6. The semiconductor package of claim 1 , wherein the at least one first chip is wire-bonded to the substrate claim 1 , andthe second chip is flip-chip bonded to the substrate.7. The semiconductor package of claim 5 , wherein the at least one first chip comprises a stack of first chips.8. The semiconductor package of claim 1 , further comprising at least one third chip on the at least one first chip and the second chip.9. The semiconductor package of claim 1 , further comprising at least one third chip on the at least one first chip and the support ...

Semiconductor Device and Method

In an embodiment, a device includes: a first reflective structure including first doped layers of a semiconductive material, alternating ones of the first doped layers being doped with a p-type dopant; a second reflective structure including second doped layers of the semiconductive material, alternating ones of the second doped layers being doped with a n-type dopant; an emitting semiconductor region disposed between the first reflective structure and the second reflective structure; a contact pad on the second reflective structure, a work function of the contact pad being less than a work function of the second reflective structure; a bonding layer on the contact pad, a work function of the bonding layer being greater than the work function of the second reflective structure; and a conductive connector on the bonding layer.

FLIP CHIP BONDING ALLOYS

A method of bonding a plurality of die having first and second metal layers on a die surface to a board, comprising placing a first die onto a board comprising one of a ceramic or substrate board or metal lead frame having a solderable surface and placing the first die and the board into a reflow oven. The method includes reflowing at a first reflow temperature for a first period until the first metal board layer and at least one of the first and second metal die layers of the first die form an alloy to adhere the first die to the board. The newly formed alloy has a higher melting temperature than the first reflow temperature. Accordingly, additional die may be reflowed and attached to the board without causing the bonding of the first die to the board to fail if the same reflow temperature is used. 1. A method for flip chip mounting at least one die to a board , comprising:forming a plurality of solderable bond pads on a first die having at least one metal layer;depositing one of a solderable paste or bump on at least one of the plurality bond pads on the first die or on a plurality of matching bond pads on the board, each of the plurality of matching bond pads of the board having at least two metal layers;performing a first reflow at a first reflow temperature to burn off at least one of flux and impurities and to melt the solderable paste or bump to form a first alloy;flip chip mounting the first die onto the board;performing a second reflow at a second reflow temperature to melt at least a portion of the first alloy to form a second alloy having a melting temperature that is higher than the first and second reflow temperatures, the second alloy including metal from bond pads of at least one of the die and the board; andsubsequently flip chip mounting a second die to the board and subjecting the first and second die and the board to the first and second reflow temperatures, thereby mounting the second die onto the board.2. The method of wherein the first die ...

METHOD AND PROCESS FOR EMIB CHIP INTERCONNECTIONS

A method for attaching an integrated circuit (IC) to an IC package substrate includes forming a solder bump on a bond pad of an IC die, forming a solder-wetting protrusion on a bond pad of an IC package substrate, and bonding the solder bump of the IC die to the solder-wetting protrusion of the IC package substrate. 125-. (canceled)26. A method for attaching an integrated circuit (IC) to an IC package substrate , the method comprising:forming a solder bump on a bond pad of an IC die;forming a solder-wetting protrusion on a bond pad of an IC package substrate; andbonding the solder bump of the IC die to the solder-wetting protrusion of the IC package substrate.27. The method of claim 26 , wherein forming a solder-wetting protrusion on the bond pad of the IC package substrate includes laser direct deposition of the solder-wetting protrusion onto the bond pad of the IC package substrate.28. The method of claim 27 , wherein laser direct deposition of the solder-wetting protrusion includes:arranging a film of solder-wetting material opposite the bond pad of the IC package substrate; andapplying laser energy to the film of solder-wetting material to transfer the solder-wetting material to the bond pad of the IC package substrate.29. The method of claim 27 , wherein laser direct deposition of the solder-wetting protrusion includes:arranging, opposite the bond pad of the IC package substrate, a film having solder-wetting material on one side and a transparent material on the other side, and applying laser energy to the transparent side of the film.30. The method of claim 28 , wherein arranging a film of solder-wetting material includes arranging the film of solder-wetting material opposite a plurality of bond pads of one or more IC package substrates claim 28 , and wherein applying laser energy includes scanning a laser energy source to positions on the film of solder-wetting material opposite the plurality of bond pads and applying pulses of laser energy to the film of ...

ELECTRONIC PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF

An electronic package structure includes: a substrate having an upper surface; a solder mask layer disposed on the upper surface of the substrate, at least one outer side of the solder mask layer being aligned with at least one outer side of the substrate; an electronic component with a first surface provided on the upper surface of the substrate; and a cavity located between the electronic component and the solder mask layer. A first surface of the cavity is formed by the first surface of the electronic component. 1. An electronic package structure , comprising:a substrate having an upper surface;a solder mask layer, disposed on the upper surface of the substrate, wherein at least one outer side of the solder mask layer is aligned with at least one outer side of the substrate;an electronic component, disposed on the upper surface of the substrate, wherein the electronic component has a first surface; anda cavity, located between the electronic component and the solder mask layer, wherein a first surface of the cavity is formed by the first surface of the electronic component.2. The electronic package structure according to further comprising a molding compound covering the electronic component and at least a part of the solder mask layer.3. The electronic package structure according to claim 1 , wherein the first surface of the electronic component is in direct contact with the solder mask layer.4. The electronic package structure according to claim 1 , wherein a gap is provided between the first surface of the electronic component and the solder mask layer.5. The electronic package structure according to claim 1 , wherein one side of the cavity is formed by the solder mask layer.6. The electronic package structure according to claim 1 , wherein a second surface of the cavity is formed by at least a part of the upper surface of the substrate or formed by at least a part of the solder mask layer.7. The electronic package structure according to claim 1 , wherein the ...

Semiconductor device package and method of manufacturing the same

The present disclosure provides a semiconductor device package. The semiconductor device package includes a first substrate and a second substrate. The first substrate has a first surface and a second surface opposite to the first surface of the first substrate. The second substrate has a first surface facing the first substrate and a second surface opposite to the first surface of the second substrate. The semiconductor device package also includes a first electronic component disposed on the first surface of the second substrate and electrically connected to the first surface of the second substrate. The semiconductor device package also includes a first encapsulant and a second encapsulant between the first substrate and the second substrate. The first encapsulant is different from the second encapsulant. A method of manufacturing a semiconductor device package is also disclosed.

Package-on-Package Structure

A method comprises forming a plurality of interconnect structures including a dielectric layer, a metal line and a redistribution line over a carrier, attaching a semiconductor die on a first side of the plurality of interconnect structures, forming an underfill layer between the semiconductor die and the plurality of interconnect structures, mounting a top package on the first side the plurality of interconnect structures, wherein the top package comprises a plurality of conductive bumps, forming an encapsulation layer over the first side of the plurality of interconnect structures, wherein the top package is embedded in the encapsulation layer, detaching the carrier from the plurality of interconnect structures and mounting a plurality of bumps on a second side of the plurality of interconnect structures. 1. A method comprising:forming a plurality of interconnect structures including a dielectric layer, a metal line and a redistribution line over a carrier;attaching a semiconductor die on a first side of the plurality of interconnect structures;forming an underfill layer between the semiconductor die and the plurality of interconnect structures;mounting a top package on the first side the plurality of interconnect structures, wherein the top package comprises a plurality of conductive bumps;forming an encapsulation layer over the first side of the plurality of interconnect structures, wherein the top package is embedded in the encapsulation layer;detaching the carrier from the plurality of interconnect structures; andmounting a plurality of bumps on a second side of the plurality of interconnect structures.2. The method of claim 1 , wherein:the top package comprises a plurality of second bumps, and wherein a second bump of the plurality of second bumps and a corresponding redistribution line of the plurality of interconnect structures form a joint structure between the top package and the plurality of interconnect structures.3. The method of claim 1 , further ...

CONDUCTIVE CONNECTIONS, STRUCTURES WITH SUCH CONNECTIONS, AND METHODS OF MANUFACTURE

A solder connection may be surrounded by a solder locking layer () and may be recessed in a hole () in that layer. The recess may be obtained by evaporating a vaporizable portion () of the solder connection. Other features are also provided. 1. A manufacturing method comprising: one or more first components each of which comprises solder and a material sublimatable or vaporizable when the solder is melted; and', 'a first layer comprising a top surface and one or more holes in the top surface, each hole containing at least a segment of a corresponding first component;, 'obtaining a first structure comprisingheating each first component to sublimate or vaporize at least part of each sublimatable or vaporizable material and provide an electrically conductive connection at a location of each first component;wherein in the heating operation at least part of each first component recedes down from the top surface to provide or increase a recess in each hole at the top surface.2. The method of wherein each hole is a through-hole.3. The method of wherein each hole's sidewall is a dielectric sidewall.4. The method of wherein the first layer is dielectric.5. The method of wherein the first layer is formed by molding.6. The method of further comprising:obtaining a second structure with one or more protruding conductive posts; andinserting each conductive post into a corresponding recess provided or increased in the heating operation, and forming a solder bond in each recess between the corresponding conductive post and the corresponding electrically conductive connection.7. The method of wherein before the heating operation claim 1 , at least a segment of each first component either:comprises of a solder core coated with the sublimatable or vaporizable material; orconsists of the sublimatable or vaporizable material.8. The method of wherein in obtaining the first structure claim 7 , the one or more first components are formed before the first layer.9. The method of wherein in ...

Wiring substrate and semiconductor package

A wiring substrate includes an insulating layer and a wiring layer buried in the insulating layer at a first surface of the insulating layer. The wiring layer includes a first portion and a second portion. The first portion is narrower and thinner than the second portion. The first portion includes a first surface exposed at the first surface of the insulating layer. The second portion includes a first surface exposed at the first surface of the insulating layer and a second surface partly exposed in an opening formed in the insulating layer. The opening is open at a second surface of the insulating layer opposite to the first surface thereof.

Substrate for semiconductor package and process for manufacturing

A semiconductor package substrate includes a core portion, an upper circuit layer and a plurality of pillars. The pillars are disposed on and project upward from the upper circuit layer. Top surfaces of the pillars are substantially coplanar. The pillars provide an electrical interconnect to a semiconductor die. Solder joint reliability as between the substrate and the semiconductor die is improved.

Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices

Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed. In one embodiment, a method for forming a microelectronic device includes attaching a microelectronic die to a support member by forming an attachment feature on at least one of a back side of the microelectronic die and the support member. The attachment feature includes a volume of solder material. The method also includes contacting the attachment feature with the other of the microelectronic die and the support member, and reflowing the solder material to join the back side of the die and the support member via the attachment feature. In several embodiments, the attachment feature is not electrically connected to internal active structures of the die.

METHOD FOR FORMING BUMP STRUCTURE

Methods for forming semiconductor structures are provided. The method for forming a semiconductor structure includes forming a metal pad over a first substrate and forming a resist layer having an opening over the metal layer. The method for forming a semiconductor structure further includes forming a conductive pillar and a solder layer over the conductive pillar in the opening of the resist layer and removing the resist layer. The method for forming a semiconductor structure further includes removing a portion of the conductive pillar so that the conductive pillar has an angled sidewall. 1. A method for forming a semiconductor structure , comprising:forming a metal pad over a first substrate;forming a resist layer having an opening over the metal layer;forming a conductive pillar and a solder layer over the conductive pillar in the opening of the resist layer;removing the resist layer; andremoving a portion of the conductive pillar so that the conductive pillar has an angled sidewall.2. The method for forming a semiconductor structure as claimed in claim 1 , wherein the angled sidewall includes a first sidewall at a top portion of the conductive pillar and a second sidewall at a bottom portion of the conductive pillar claim 1 , and the first sidewall is in a first direction and the second sidewall is in a second direction different from the first direction.3. The method for forming a semiconductor structure as claimed in claim 2 , further comprising:reflowing the solder layer after the removing the portion of the conductive pillar to form the angled sidewall.4. The method for forming a semiconductor structure as claimed in claim 3 , wherein an inter-metal compound is formed partially covering the first sidewall of the top portion of the conductive pillar after reflowing the solder layer.5. The method for forming a semiconductor structure as claimed in claim 1 , further comprising:forming a seed layer over the metal pad before the conductive pillar is formed, ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE THEREOF

A semiconductor device includes a board having a solder resist layer with first and second openings on a first surface, and a first electrode on the first surface, a portion thereof exposed in the first opening and electrically connected to the board. A second electrode is located on the first surface having a portion exposed in the second opening and electrically connected to the board. A portion of the second electrode is covered by the solder resist layer. A first solder bump is on the first electrode and covers a side surface. A second solder bump is on the second electrode. A semiconductor chip has a first region and a second region facing the first surface. A third electrode is in the first region and electrically connected to the first solder bump. A fourth electrode is in the second region and electrically connected to the second solder bump. 1. A semiconductor device , comprising:a board having a first surface;a solder resist layer on the first surface, the solder resist layer comprising a first opening and a second opening;a first electrode on the first surface and having a side surface exposed in the first opening, the first electrode electrically connected to the board;a second electrode, having an outer perimeter, on the first surface, wherein the second electrode electrically connected to the board and at least a portion of the outer perimeter of the second electrode covered by the solder resist layer;a first solder hump on the first electrode, the first solder bump covering the side surface of the first electrode;a second solder bump on the second electrode; anda semiconductor chip comprising a second surface facing the first surface, the second surface comprising a first region and a second region, wherein a third electrode in the first region of the semiconductor chip is electrically connected to the first solder bump, and a fourth electrode in the second region of the semiconductor chip is electrically connected to the second solder bump, ...