Method for forming channel hole in three-dimensional memory device using nonconformal sacrificial layer.

Method for forming channel hole in three-dimensional memory device using nonconformal sacrificial layer

Номер патента: EP3821465B1
Опубликовано: 06-03-2024
Автор(ы): Baoyou Chen, GuanPing WU, Hai Hui Huang, Hongbin Zhu, Weihua Cheng, Yu Qi Wang, Zhuqing Huang
Принадлежит: Yangtze Memory Technologies Co Ltd
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Рисунок 1. Взаимосвязь патентов (ближайшие 20).

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Three-dimensional memory device with finned support pillar structures and method of forming the same

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Multi-tier three-dimensional memory device containing differential etch rate field oxides and method of making the same

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Contact structures for three-dimensional memory device

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Three-dimensional memory device containing alternating stack of source layers and drain layers and vertical gate electrodes

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Three-dimensional memory device including backside trench support structures and methods of forming the same

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Three dimensional memory device containing dummy word lines and p-n junction at joint region and method of making the same

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On-pitch drain select level isolation structure for three-dimensional memory device and method of making the same

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On-pitch drain select level isolation structure for three-dimensional memory device and method of making the same

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On-pitch drain select level isolation structure for three-dimensional memory device and method of making the same

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Three-dimensional memory, the manufacturing method for the same, and memory system

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Three-dimensional memory device and manufacturing method thereof

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Trench and pier architectures for three-dimensional memory arrays

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Three-dimensional memory, chip packaging structure, and electronic device

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Support structures for three dimensional memory arrays

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Merged cavities and buried etch stops for three-dimensional memory arrays

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Fabrication method for a three-dimensional memory array of thin-film ferroelectric transistors formed with an oxide semiconductor channel

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Structures for word line multiplexing in three-dimensional memory arrays

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Channel structures for three-dimensional memory devices and methods for forming the same

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Through-silicon via (TSV) crack sensors for detecting TSV cracks in three-dimensional (3D) integrated circuits (ICs) (3DICs), and related methods and systems

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Three-dimensional memory device with high contact via density and methods of forming the same

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Three-dimensional memory devices and fabricating methods thereof

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Three-dimensional memory device containing dual-depth drain-select-level isolation structures and methods for forming the same

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Three-dimensional memory device containing dual-depth drain-select-level isolation structures and methods for forming the same

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Three-dimensional memory device containing iii-v compound semiconductor channel and contacts and method of making the same

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Three-dimensional memory array with dual-level peripheral circuits and methods for forming the same

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Three-dimensional memory and formation method thereof

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Three-dimensional memory array with dual-level peripheral circuits and methods for forming the same

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Three-dimensional memory device containing peripheral circuit with fin and planar field effect transistors and method of making thereof

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THROUGH-SILICON VIA (TSV) CRACK SENSORS FOR DETECTING TSV CRACKS IN THREE-DIMENSIONAL (3D) INTEGRATED CIRCUITS (ICs) (3DICs), AND RELATED METHODS AND SYSTEMS

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Word line structures for three-dimensional memory arrays

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Word line structures for three-dimensional memory arrays

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Word line structures for three-dimensional memory arrays

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Word line decoder circuitry under a three-dimensional memory array

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Three-dimensional memory device including a source structure surrounded by inner sidewalls of vertical semiconductor channels and methods of forming the same

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Three-dimensional memory device and manufacturing method therefor, and three-dimensional memory

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Three-dimensional memory devices and manufacturing methods thereof and three-dimensional memories

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Non-volatile three-dimensional memory cell, storage method, and chip assembly

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Three-dimensional memory arrays with layer selector transistors

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Three-dimensional memory device having bonding structures connected to bit lines and methods of making the same

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Three-dimensional memory devices and fabricating methods thereof

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Multiple transistor architecture for three-dimensional memory arrays

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Decoder architectures for three-dimensional memory devices

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Bonded structure including a performance-optimized support chip and a stress-optimized three-dimensional memory chip and method for making the same

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Method for fabricating three-dimensional memory

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Three-dimensional memory device containing bit line switches

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Three-dimensional memory devices and fabricating methods thereof

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Three-dimensional memory array with local line selector

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Three-dimensional memory array with local line selector

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Three-dimensional memory array with local line selector

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Three-dimensional memory array with local line selector

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Three-dimensional memory device containing bridges for enhanced structural support and methods of forming the same

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Three-dimensional memory device containing iii-v compound semiconductor channel and contacts and method of making the same

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Multi-division staircase structure of three-dimensional memory device and method for forming the same

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Three-dimensional memory and method for manufacturing the same

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Three-dimensional memory devices and methods for forming the same

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Openings layout of three-dimensional memory device

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Memory cell protective layers in a three-dimensional memory array

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Three-dimensional memory device containing discrete charge storage elements and methods for forming the same

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