Substrat-Bondingstruktur und Substrat-Bondingverfahren

Eine Vorrichtung (2) ist auf einer Hauptoberfläche eines Substrats (1) ausgebildet. Die Hauptoberfläche des Substrats (1) ist über das Bonding-Bauteil (11, 12, 13) in einem hohlen Zustand an die Unterseite des Gegensubstrats (14) gebondet. Eine Schaltung (17) und eine Höckerstruktur (26) sind auf der Oberseite des Gegensubstrats (14) ausgebildet. Die Höckerstruktur (26) ist in einem Bereich positioniert, der zumindest dem Bonding-Bauteil (11, 12, 13) entspricht, und weist eine größere Höhe als diejenige der Schaltungsstruktur (17) auf.

반도체 패키지 및 반도체 패키지 모듈

... 범프를 통하여 회로 기판과 연결되는 반도체 패키지가 제공된다. 본 발명의 일 실시예에 따른 반도체 패키지는, 복수개의 접속 패드가 노출되도록 형성된 반도체 칩; 상기 각 접속 패드 상에 형성되며, 제1 필라부 및 상기 제1 필라부 상측에 형성되는 제1 솔더부를 포함하는 연결용 범프들; 상기 접속 패드 주변에서 상기 접속 패드의 상부 표면 보다 높은 위치에 형성되며, 솔더 유도부가 형성되어 있는 제2 필라부 및 상기 제2 필라부 상측에 형성되는 제2 솔더부를 포함하는 지지용 범프들;을 포함한다.

BUMP STRESS MITIGATION LAYER FOR INTEGRATED CIRCUITS

An apparatus comprises a semiconductor substrate having a device layer, a plurality of metallization layers, a passivation layer, and a metal bump formed on the passivation layer that is electrically coupled to at least one of the metallization layers. The apparatus further includes a solder limiting layer formed on the passivation layer that masks an outer edge of the top surface of the metal bump, thereby making the outer edge of the top surface non-wettable to a solder material.

Metal Bump Joint Structure and Methods of Forming

A structure comprises a first semiconductor chip with a first metal bump and a second semiconductor chip with a second metal bump. The structure further comprises a solder joint structure electrically connecting the first semiconductor chip and the second semiconductor chip, wherein the solder joint structure comprises an intermetallic compound region between the first metal bump and the second metal bump, wherein the intermetallic compound region is with a first height dimension and a surrounding portion formed along exterior walls of the first metal bump and the second metal bump, wherein the surrounding portion is with a second height dimension, and wherein the second height dimension is greater than the first height dimension.

Semiconductor substrate with conductive bumps having a stress relief buffer layer formed of an electrically insulating organic material

A microelectronic structure is provided having a semi-conducting substrate comprising circuits therein and a top surface, and at least one first conductive bump situated on the top surface. The conductive bump provides electrical communication to the circuits. The at least one conductive bump has a stress relief buffer layer formed of an electrically insulating organic material. The portions of the at least one conductive bump other than the stress relief buffer layer are a unitary structure. The top surface of the conductive bump is uncovered and directly exposed to its surroundings.

Stacking semiconductor devices, particularly memory chips

High density packaging of semiconductor devices on an interconnection substrate is achieved by stacking bare semiconductor devices atop one another so that an edge portion of a semiconductor device extends beyond the semiconductor device that it is stacked atop. Elongate interconnection elements extend from the bottommost one of the semiconductor devices, and from the exposed edge portions of the semiconductor devices stacked atop the bottommost semiconductor device. Free-ends of the elongate interconnection elements make electrical contact with terminals of an interconnection substrate, such as a PCB. The elongate interconnection elements extending from each of the semiconductor devices are sized so as to reach the terminals of the PCB, which may be plated through holes. The elongate interconnection elements are suitably resilient contact structures, and may be composite interconnection elements comprising a relatively soft core (e.g., a gold wire) and a relatively hard overcoat (e.g., ...

Method of forming a temporary test structure for device fabrication

A method of forming a temporary test structure for device fabrication is provided. The method is particularly useful for electrically testing conductive interconnects during controlled collapse chip connections (C4) fabrication and/or through-silicon vias (TSVs) during interposer fabrication. The method includes providing a substrate containing a plurality of electrically conductive interconnects extending vertically to top surface of the substrate. A temporary test structure is formed to connect the plurality of interconnects and for electrical testing. The suitable material for the temporary test structure is TiW for a single layer structure, or Cu or Cu alloy over Ti or TiW for a bilayer structure with thickness in a range of about 20 nm to 1200 nm. Excimer laser ablation can be used to form the temporary test structure. Electrical testing is performed on the substrate by probing at different test locations on the temporary test structure. All or part of the temporary test structure ...

Chip Scale Package

A novel semiconductor chip scale package encapsulates a semiconductor chip on the device side, the non-device side, and the four edges with a mold compound. One process to fabricate such a semiconductor chip scale package involves forming trenches on the surface of a wafer around the chips and filling the trenches and covering the device side of the chips with a first mold compound. The wafer is subsequently thinned from the non-device side until the bottom portion of the trenches and the mold compound in the portion are also removed. The thinning process creates a plane that contains the back side of the chips and the mold compound exposed in the trench. This plane is subsequently covered with a second mold compound.

Substrate Stand-Offs for Semiconductor Devices

Substrate stand-offs for use with semiconductor devices are provided. Active pillars and dummy pillars are formed on a first substrate such that the dummy pillars may have a height greater than a height of the active pillars. The dummy pillars act as stand-offs when joining the first substrate to a second substrate, thereby creating greater uniformity. In an embodiment, the dummy pillars may be formed simultaneously as the active pillars by forming a patterned mask having openings with a smaller width for the dummy pillars than for the active pillars. When an electro-plating process of the like is used to form the dummy and active pillars, the smaller width of the dummy pillar openings in the patterned mask causes the dummy pillars to have a greater height than the active pillars.

Electrode arrays and methods of fabricating the same using printing plates to arrange particles in an array

Electrode arrays and methods of fabricating the same using a printing plate to arrange conductive particles in alignment with an array of electrodes are provided. In one embodiment, a semiconductor device comprises: a semiconductor topography comprising an array of electrodes disposed upon a semiconductor substrate; a dielectric layer residing upon the semiconductor topography; and at least one conductive particle disposed in or on the dielectric layer in alignment with at least one of the array of electrodes.

Mechanisms for forming hybrid bonding structures with elongated bumps

Embodiments of mechanisms for forming a package structure are provided. The package structure includes a semiconductor die and a substrate. The package structure includes a pillar bump and an elongated solder bump bonded to the semiconductor die and the substrate. A height of the elongated solder bump is substantially equal to a height of the pillar bump. The elongated solder bump has a first width, at a first horizontal plane passing through an upper end of a sidewall surface of the elongated solder bump, and a second width, at a second horizontal plane passing through a midpoint of the sidewall surface. A ratio of the second width to the first width is in a range from about 0.5 to about 1.1.

Packaging Process Tools and Packaging Methods for Semiconductor Devices

Packaging process tools and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging process tool for semiconductor devices includes a mechanical structure including a frame. The frame includes a plurality of apertures adapted to retain a plurality of integrated circuit dies therein. The frame includes at least one hollow region.

SEMICONDUCTOR PACKAGE

A semiconductor package includes a first semiconductor chip having a first chip substrate, the first chip substrate having a first upper surface and a first lower surface opposite to each other, a first through-silicon via (TSV), a lower connection pad and a first lower passivation layer on the first lower surface of the first chip substrate, the first lower passivation layer exposing a portion of the lower connection pad, an upper connection pad and a first upper passivation layer on the first upper surface of the first chip substrate, the first upper passivation layer including a first upper inorganic material layer, and a second semiconductor chip connected to the first semiconductor chip, the second semiconductor chip including a second TSV, wherein the first lower passivation layer has a stacked structure of a first lower inorganic material layer and a lower organic material layer.

Flip Chip Bonding Arrangement

A flip-chip bonding arrangement for use with for example, a GaAs monolithic microwave integrated circuit (MMIC) 42, or an opto-electronic device, has one or more metal under-bump portions 44 attached to a first substrate 40. Corresponding bump portions 52 of an interconnecting metal are attached to the surface of the under bump portions 44 remote from the first substrate. The arrangement is characterised in that the sides of the under-bump portions are non-wettable by the interconnecting metal, and the height of the under-bump portion substantially determines the overall separation between the first and a second substrates when the two are bonded. The under bump portions 44 may be made from nickel or copper, and have a height of at least 10 žm, and of at most 100 žm. A method of providing a flip-chip bonding arrangement uses a seed layer, photoresist, under bumps and bumps formed in openings in the photoresist (Figures 5a-5g). A further method of bonding two substrates uses a plurality ...

Method for forming superconducting structures

A superconducting structure (10) includes a first superconducting device (12) having a plurality of first superconducting contact pads (16) disposed on a top side of a first superconducting device, a second superconducting device (22) having a plurality of second superconducting contact pads (26) disposed on a bottom side of a second superconducting device, and a plurality of superconducting bump structures (30) with a given bump structure coupling respective superconducting contact pads of the plurality of first superconducting contact pads and the second plurality of superconducting pads to one another to bond the first superconducting device to the second superconducting device. Each superconducting bump structure includes a first under bump metallization (UBM) layer (18) disposed on the top surface of a given superconducting contact pad, a second UBM layer (28) disposed on the top surface of a given superconducting contact pads, and a superconducting metal layer (20) coupling the first ...

Stacked semiconductor devices, particularly memory chips

Conductive bump, method for producing the same, and electronic component mounted structure

Disclosed is a conductive bump formed on an electrode surface of an electronic component. This conductive bump is composed of a plurality of photosensitive resin layers having different conductive filler contents. Consequently, this conductive bump is able to realize apparently conflicting functions, namely improvement in adhesion strength with the electrode and reduction of contact resistance.

Integrated circuit element and packaging component

The invention provides an integrated circuit element and a packaging component. The integrated circuit element comprises a semiconductor substrate, a conductive column which is disposed on the semiconductor substrate and has a side wall surface and an upper surface, a boss lower metal layer which is disposed between the semiconductor substrate and the conductive column and has a surface area which is adjacently connected to the side wall surface of the conductive column and extends from the side wall surface, and a protection structure which is disposed on the side wall surface of a copper column and on the surface area of the boss lower metal layer. The protection structure is made of metal materials and the conductive column is composed by copper layers. The side wall protection structure covers at least a part of the side wall surface of the boss structure, and the protection structures disposed on the copper column side wall and on the surface area of the boss lower metal layer are ...

MANUFACTORING PROCESS OF TWO SUBSTRATES CONNECT BY AT LEAST A MECHANICAL CONNECTION AND ELECTRICALLY CONDUCTING OBTAINED

A first substrate provided with a receiving area made from a first metallic material is supplied. A second substrate provided with an insertion area comprising a base surface and at least two bumps made from a second metallic material is arranged facing the first substrate. The bumps are salient from the base surface. A pressure is applied between the first substrate and the second substrate so as to make the bumps penetrate into the receiving area. The first metallic material reacts with the second metallic material so as to form a continuous layer of an intermetallic compound having a base formed by the first and second metallic materials along the interface between the bumps and the receiving area.

A METHOD OF JOINING TWO ELECTRONIC COMPONENT, FLIP-CHIP TYPE, OBTAINED BY THE ASSEMBLY METHOD.

L'invention concerne un procédé d'assemblage de deux composants électroniques l'un à l'autre, lesdits composants comportant chacun une face d'assemblage, selon lequel on rapproche les deux faces d'assemblage l'une de l'autre selon une direction X dite d'assemblage et on applique une force donnée F à l'un et/ou l'autre des composants, l'une et/ou l'autre face(s) d'assemblage comportant: - des inserts de connexion en matériau rigide présentant une forme longitudinale allongée selon la direction X d'assemblage; - des pistes de connexion en matériau de dureté inférieure à celle des inserts et de forme longitudinale allongée transversalement à la direction X d'assemblage. procédé selon lequel: - on aligne les inserts en regard des pistes correspondantes de manière à ce que les inserts et les pistes forment deux à deux, après assemblage, au moins une intersection sensiblement transversale, - on applique la force F pour faire pénétrer les inserts dans les pistes jusqu'à obtenir l'assemblage.

Semiconductor structure and manufacturing method thereof

A semiconductor structure includes a substrate, a conductive interconnection exposed from the substrate, a passivation covering the substrate and a portion of the conductive interconnection, an under bump metallurgy (UBM) pad disposed over the passivation and contacted with an exposed portion of the conductive interconnection, and a conductor disposed over the UBM pad, wherein the conductor includes a top surface, a first sloped outer surface extended from the top surface and including a first gradient, and a second sloped outer surface extended from an end of the first sloped outer surface to the UBM pad and including a second gradient substantially smaller than the first gradient.

Package structure and methods for forming the same

A structure and a formation method of a package structure are provided. The method includes forming one or more solder elements over a substrate. The one or more solder elements surround a region of the substrate. The method also includes disposing a semiconductor die structure over the region of the substrate. The method further includes dispensing a polymer-containing liquid onto the region of the substrate. The one or more solder elements confine the polymer-containing liquid to being substantially inside the region. In addition, the method includes curing the polymer-containing liquid to form an underfill material.

Electrical connecting element and method for manufacturing the same

SEMICONDUCTOR PACKAGE

A semiconductor package including a first semiconductor chip having a first thickness, a second semiconductor chip on the first semiconductor chip and having a second thickness, the second thickness being smaller than the first thickness, a third semiconductor chip on the second semiconductor chip and having a third thickness, the third thickness being smaller than the second thickness, a fourth semiconductor chip on the third semiconductor chip and having a fourth thickness, the fourth thickness being greater than the third thickness, and a fifth semiconductor chip disposed on the fourth semiconductor chip and having a fifth thickness, the fifth thickness being greater than the fourth thickness may be provided.

Microelectronic spring contact elements

Spring contact elements are fabricated by depositing at least one layer of metallic material into openings defined in masking layers deposited on a surface of a substrate which may be an electronic component such as an active semiconductor device. Each spring contact element has a base end, a contact end, and a central body portion. The contact end is offset in the z-axis (at a different height) and in at least one of the x and y directions from the base end. In this manner a plurality of spring contact elements are fabricated in a prescribed spatial relationship with one another on the substrate. The spring contact elements make temporary (i.e., pressure) or permanent (e.g., joined by soldering or brazing or with a conductive adhesive) connections with terminals of another electronic component to effect electrical connections therebetween. In an exemplary application, the spring contact elements are disposed on a semiconductor devices resident on a semiconductor wafer so that temporary ...

Manufacturing method of mounting part of semiconductor light emitting element, manufacturing method of light emitting device, and semiconductor light emitting element

A manufacturing method of a mounting part of a semiconductor light emitting element comprising: preparing a semiconductor light emitting element including an electrode which has a surface, and a board which has a surface; forming a plurality of bump material bodies on at least one of the surface of the electrode and the surface of the board by shaping bump material into islands, wherein the bump material is paste in which metal particles are dispersed, a top surface and a bottom surface of the bump material bodies have different areas, and the top surface is practically flat; solidifying the bump material bodies by thermally processing the bump material bodies; and fixing the semiconductor light emitting element and the board through the bumps.

Semiconductor chip with post-passivation scheme formed over passivation layer

The invention provides a semiconductor chip comprising an interconnecting structure over said passivation layer. The interconnecting structure comprises a first contact pad connected to a second contact pad exposed by an opening in a passivation layer. A metal bump is on the first contact pad and over multiple semiconductor devices, wherein the metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.

Double-sided package for power module

An electronic semiconductor package is described. The package has a wide band gap electronic semiconductor device requiring heat removal. On one side of the electronic semiconductor device is a first, thermally-conductive, electrically-insulative substrate having a predetermined electrically-conductive wire pattern affixed thereto. On the other side of the electronic semiconductor device is a second, thermally-conductive, electrically-insulative substrate. A heat removal device is mechanically-coupled to the second substrate. The heat removal device is made of a graphite-metal or metal-matrix composite material and a fin array structure of the same material. The coefficients of thermal expansion of the heat removal device and the first and second substrates are matched to minimize internal and external stresses.

Semiconductor chip stack and method for manufacturing semiconductor chip stack

A semiconductor chip stack includes a first semiconductor chip, a second semiconductor chip, and a connection via which the first electrode and the second electrode are electrically connected to each other. The connection includes a first column and a second column. The first column is constituted by a material having a higher degree of activity with respect to heat than a material that constitutes the second column and is smaller in volume than the second column. Further, the connection has an aspect ratio of 0.5 or higher in a height direction.

SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor package device includes a first conductive structure, a second conductive structure and a dielectric layer. The first conductive structure has a tapered portion. The second conductive structure surrounds the tapered portion of the first conductive structure and is in direct contact with a side wall of the tapered portion of the first conductive structure. The dielectric layer surrounds the tapered portion of the first conductive structure and is in direct contact with the side wall of the tapered portion of the first conductive structure.

SEMICONDUCTOR MODULE, DISPLAY DEVICE, AND SEMICONDUCTOR MODULE MANUFACTURING METHOD

Resin covers a side surface and a back surface of a blue LED and holds the blue LED level. An electrode is disposed between a top surface of a wiring substrate and a back surface of the blue LED, extends through the resin, and electrically connects the wiring substrate and the blue LED to each other. A light-outgoing surface (top-surface) of the blue LED is exposed without being covered with the resin, and the light-outgoing surface (top-surface) is flush with a top surface of the resin.

TRANSIENT LIQUID PHASE MATERIAL BONDING AND SEALING STRUCTURES AND METHODS OF FORMING SAME

A method of forming a bonding element including a first transient liquid phase (TLP) bonding element including a first material and a second material, the first material having a higher melting point than the second material, a ratio of a quantity of the first material and the second material in the first TLP bonding element having a first value, and a second TLP bonding element including the first material and the second material, a ratio of a quantity of the first material and the second material in the second TLP bonding element having a second value different from the first value.

Bond pads for low temperature hybrid bonding

Various chip stacks and methods and structures of interconnecting the same are disclosed. In one aspect, an apparatus is provided that includes a first semiconductor chip that has a first glass layer and plural first groups of plural conductor pads in the first glass layer. Each of the plural first groups of conductor pads is configured to bumplessly connect to a corresponding second group of plural conductor pads of a second semiconductor chip to make up a first interconnect of a plurality interconnects that connect the first semiconductor chip to the second semiconductor chip. The first glass layer is configured to bond to a second glass layer of the second semiconductor chip.

Chip package with redistribution layers

A chip package is provided. The chip package includes a semiconductor substrate having an edge and a protective layer surrounding the semiconductor substrate. The chip package also includes a conductive line over the protective layer and the semiconductor substrate. The conductive line has a first portion and a second portion in direct contact with the first portion, and the second section at least partially covers the edge. In a top view of the conductive layer, line widths of the first portion and the second portion are different from each other.

Semiconductor device

The invention relates to a semiconductor device. The top surface of a semiconductor substrate is provided with at least one bonding pad. A passivation layer is located on the top surface of the semiconductor substrate. At least one opening located within the passivation layer exposes the bonding pad. A metal layer is stacked on the bonding pad.

VIBRATION DEVICE, ELECTRONIC APPARATUS, AND VEHICLE

FLIP CHIP ASSEMBLY METHOD COMPRISING PRE-COATING THE INTERCONNECTING MEMBERS

Ce procédé d'assemblage d'un premier et d'un second composants électroniques (50, 52), comporte : ▪ la réalisation d'éléments de connexion sur une face d'assemblage du premier composant (50) et la réalisation d'éléments de connexion sur une face d'assemblage du second composant (52) ; ▪ le dépôt d'une couche liquide de matériau durcissable et électriquement isolant (70) sur la face d'assemblage du premier et/ou du second composant ; ▪ le report des premier et second composants (50, 52) l'un sur l'autre de manière à mettre les éléments de connexion du second composant en face des éléments de connexion du premier composant ; ▪ l'application d'une force selon une direction prédéterminée (A) sur le premier et/ou le second des composants (50, 52) de manière à créer des interconnexions électriques constituées chacune d'un élément de connexion (56) du premier composant (50) et d'un élément de connexion (58) du second composant (52); ▪ et le durcissement du matériau durcissable (70). Les éléments ...

반도체 장치, 반도체 패키지 및 반도체 패키지의 제조 방법

... 반도체 장치가 개시된다. 반도체 장치는, 기판 상에 형성된 도전 성분(conductive component); 상기 기판 상에 형성되며 개구부를 구비하는 패시베이션층으로서, 상기 개구부가 상기 도전 성분의 적어도 일부분을 노출하는, 상기 패시베이션층; 및 상기 패시베이션층 상에서 상기 개구부를 채우며, 상기 도전 성분과 전기적으로 연결되는 패드 구조물을 포함한다. 상기 패드 구조물은 상기 개구부의 내벽 상에 및 상기 개구부 주위의 상기 패시베이션층 상면 상에 콘포말하게 형성되며, 순서대로 적층된 도전 배리어층, 제1 시드층, 식각 정지층 및 제2 시드층을 포함하는 하부 도전층, 상기 하부 도전층 상에 형성되며, 상기 개구부를 적어도 부분적으로 채우는 제1 패드층, 및 상기 제1 패드층 상에 형성되며, 상기 패시베이션층의 상기 상면 상에 배치되는 상기 하부 도전층의 외주 부분과 접촉하는 제2 패드층을 포함한다.

SEMICONDUCTOR CHIP AND MANUFACTURING METHOD FOR THE SAME

PURPOSE: To provide a semiconductor chip in which a pad for external connection is hardly corroded regardless of the connection condition of a wire. CONSTITUTION: An opening 17B is made in a surface protection film 16 around the periphery of a master chip 1 so that an inner wiring 15 is partly exposed over the surface protection film 16, and an outer connection pad 15B is formed thereby. A wire connection part 12 using the same oxidation resistant metallic material as a bump BM is formed projecting over the external connection pad 15B so as to connect a bonding wire. © KIPO & JPO 2002 ...

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure includes a substrate, a conductive interconnection part exposed from the substrate, a passivation part covering the substrate and a portion of the conductive interconnection part, an under bump metallurgy (UBM) pad disposed on the upper side of the passivation part and touching an exposed portion of the conductive interconnection part, and a conductor disposed on the upper side of the UBM pad. The conductor includes a top surface, a first sloped outer surface extended from the top surface and including a first gradient, and a second sloped outer surface extended from an end of the first sloped outer surface to the UBM pad and including a second gradient substantially smaller than the first gradient. COPYRIGHT KIPO 2016 (AA) W_conductor (BB) W_lower end (CC) W_upper end (DD) W_protrusion (EE) H_protrusion (FF) H_conductor ...

METAL BUMP JOINT STRUCTURE

BUMP STRESS MITIGATION LAYER FOR INTEGRATED CIRCUITS

Integrated circuit devices and packaging assembly

A sidewall protection structure is provided for covering at least a portion of a sidewall surface of a bump structure, in which a protection structure on the sidewall of a Cu pillar and a surface region of an under-bump-metallurgy (UBM) layer is formed of at least one non-metal material layers, for example a dielectric material layer, a polymer material layer, or combonations thereof.

Conductive bump and electroless Pt plating bath

The present invention provides a bump that can prevent diffusion of a metal used as a base conductive layer of the bump into a surface of an Au layer or an Ag layer. A conductive bump of the present invention is s conductive bump formed on a substrate. The conductive bump comprises, at least in order from the substrate: a base conductive layer; a Pd layer; a Pt layer; and an Au layer or an Ag layer having directly contact with the Pd layer, wherein a diameter of the conductive bump is 20 [mu]m or less.

IMAGING DEVICE AND MANUFACTURING METHOD FOR SAME

An imaging device (1) is provided with a light receiving element unit (2), a processing unit (3), a first connection body (4) and a second connection body (5). The first connection body (4) electrically connects: a first electrode (11) of the light receiving element unit (2); and a second electrode (21) that corresponds to the processing unit (3). The first connection body (4) contains: an indium-containing solder portion (29) placed between the first electrode (11) and the second electrode (21); and a barrier layer (30) for reducing alloying of the first electrode (11) and the second electrode (21) with the solder portion (29). The second connection body (5) has a melting point at least as high as the melting point of the first connection body, and contains an alloy portion (33) formed by alloying with solder containing a material of greater hardness than the first connection body.

COMPONENT MAGNETIC SHIELDING FOR MICROELECTRONIC DEVICES

A microelectronic device may include a substrate, a component, a first plate, a second plate, and a shield. The component may be disposed at least partially within the substrate. The first plate may be disposed on a first side of the component. The second plate may be disposed on a second side of the component. The shield may be disposed around at least a portion of a periphery of the component.

Chip package and method for fabricating the same

A chip package includes a semiconductor substrate, a first metal pad over the semiconductor substrate, and a second metal pad over the semiconductor substrate. In a case, the first metal pad is tape automated bonded thereto, and the second metal pad is solder bonded thereto. In another case, the first metal pad is tape automated bonded thereto, and the second metal pad is wirebonded thereto. In another case, the first metal pad is solder bonded thereto, and the second metal pad is wirebonded thereto. In another case, the first metal pad is bonded to an external circuitry using an anisotropic conductive film, and the second metal pad is solder bonded thereto. In another case, the first metal pad is bonded to an external circuitry using an anisotropic conductive film, and the second metal pad is wirebonded thereto.

Microelectronic packages and methods therefor

A microelectronic package includes a microelectronic element having a first face including contacts, and a flexible substrate having a first surface and a second surface, conductive posts projecting from the first surface and conductive terminals accessible at the second surface, at least some of the conductive terminals and the conductive posts being electrically interconnected and at least some of the conductive terminals being offset from the conductive posts. The first surface of the flexible substrate is juxtaposed with the first face of the microelectronic element so that the conductive posts project from the flexible substrate toward the first face of the microelectronic element. The conductive posts are electrically interconnected with the contacts of the microelectronic element and at least some of the conductive terminals are movable relative to the microelectronic element.

Process of producing semiconductor chip with surface interconnection at bump

A semiconductor chip including a bump projecting from a surface protective film thereof and a surface interconnection having a smaller height than the bump. The surface interconnection may project from the surface protective film or may be flush with the surface protective film. The surface interconnection may be connected to the bump. The bump may include a peripheral bump configured as surrounding a device formation region of the chip. The peripheral bump may be connected to the ground or a power source.

Magnetische Komponentenabschirmung für mikroelektronische Bauelemente

Ein mikroelektronisches Bauelement kann ein Substrat, eine Komponente, eine erste Platte, eine zweite Platte und eine Abschirmung umfassen. Die Komponente kann zumindest teilweise innerhalb des Substrats angeordnet sein. Die erste Platte kann auf einer ersten Seite der Komponente angeordnet sein. Die zweite Platte kann auf einer zweiten Seite der Komponente angeordnet sein. Die Abschirmung kann um zumindest einen Abschnitt einer Peripherie der Komponente herum angeordnet sein.

Flip-chip bonding arrangement

Integrated circuit chip using top post-passivation technology and bottom structure technology

INTEGRATED CIRCUIT CHIP USING TOP POST-PASSIVATION TECHNOLOGY AND BOTTOM STRUCTURE TECHNOLOGY

MULTI-CHIP PACKAGE AND MANUFACTURE METHOD THEREOF

A multi-chip package and a manufacturing method thereof are provided. The multi-chip package includes: an interposer including a dielectric body, a plurality of semiconductor bodies separated by the dielectric body, a through via penetrating through the dielectric body, and a wiring structure located in each of the plurality of semiconductor bodies; a plurality of semiconductor chips located side by side on a first surface of the interposer and electrically connected to the wiring structure; an encapsulant located on the first surface of the interposer and encapsulating at least a portion of the plurality of semiconductor chips; and a redistribution circuit structure located on a second surface of the interposer opposite to the first surface of the interposer and electrically connected to the plurality of semiconductor chips through the through via.

Implantable microelectronic device and method of manufacture

An implantable hermetically sealed microelectronic device, and method of manufacture are disclosed. The microelectronic device of the present invention is hermetically encased in a insulator, such as alumina formed by ion bean assisted deposition (“IBAD”), with a stack of biocompatible conductive layers extending from a contact pad on the device to an aperture in the hermetic layer. In a preferred embodiment, one or more patterned titanium layers are formed over the device contact pad, and one or more platinum layers are formed over the titanium layers, such that the top surface of the upper platinum layer defines an external, biocompatible electrical contact for the device. Preferably, the bottom conductive layer is larger than the contact pad on the device, and a layer in the stack defines a shoulder.

Semiconductor device package and method of manufacturing the same

A semiconductor packaging device includes a first patterned insulation layer, a patterned conductive layer, a semiconductor device and an encapsulant. The first patterned insulation layer has a first surface, a second surface opposite the first surface, and an island portion having the first surface. The first patterned insulation layer defines a tapered groove surrounding the island portion. The patterned conductive layer is disposed on the first surface of the island portion. The semiconductor device electrically connects to the patterned conductive layer. The encapsulant encapsulates the semiconductor device, the first patterned insulation layer and the patterned conductive layer.

Stack-type semiconductor package

According to example embodiments, a stack-type semiconductor package includes a lower semiconductor package, an upper semiconductor package, connection pads, and a metal layer pattern. The lower semiconductor package includes a lower semiconductor chip on a top surface of a lower package substrate, lower lands on the lower package substrate, and an encapsulant on the top surface of the lower package substrate. The encapsulant defines via holes that expose the lower lands. The upper semiconductor package is on the encapsulant. Upper solder balls are connected to a bottom surface of the upper semiconductor package. The connection pads are on the via holes and the encapsulant. The connection pads electrically connect the lower semiconductor package to the upper semiconductor package. The metal layer pattern is between the lower package substrate and the upper semiconductor package. The metal layer pattern surrounds the connection pads and is isolated from the connection pads.

CONDUCTIVE BUMP, METHOD FOR PRODUCING THE SAME, AND ELECTRONIC COMPONENT MOUNTED STRUCTURE

A conductive bump formed on an electrode surface of an electronic component. This conductive bump is composed of a plurality of photosensitive resin layers having different conductive filler contents. Consequently, this conductive bump is able to realize conflicting functions, namely, improvement in adhesion strength with the electrode and reduction of contact resistance.

METHOD OF FORMING A TEMPORARY TEST STRUCTURE FOR DEVICE FABRICATION

A method of forming a temporary test structure for device fabrication is provided. The method allows for electrically testing conductive interconnects during controlled collapse chip connections (C4) fabrication and/or through-silicon vias (TSVs) during interposer fabrication. The method includes providing a substrate containing a plurality of electrically conductive interconnects extending vertically to top surface of the substrate. A temporary test structure is formed to connect the plurality of interconnects for electrical testing. Electrical testing is performed on the substrate by probing at different test locations on the temporary test structure. All or part of the temporary test structure is removed so as not to affect product performance. The temporary test structure can contain electrical test pads which provide a way to make temporary connections to small interconnect landings or features at extreme tight pitch to fan them out to testable pads sizes and pitches.

FILMSCHEMA ZUR KONTAKTHÖCKERBILDUNG

Eine Kontakthöckerstruktur mit einer Sperrschicht und ein Verfahren zur Herstellung der Kontakthöckerstruktur werden bereitgestellt. In einigen Ausführungsformen umfasst die Kontakthöckerstruktur eine leitfähige Kontaktinsel, einen leitfähigen Kontakthöcker und eine Sperrschicht. Die leitfähige Kontaktinsel umfasst ein Kontaktinselmaterial. Der leitfähige Kontakthöcker liegt über der leitfähigen Kontaktinsel und umfasst eine untere Kontakthöckerschicht und eine obere Kontakthöckerschicht, die die untere Kontakthöckerschicht bedeckt. Die Sperrschicht ist dafür konfiguriert, die Bewegung des Kontaktinselmaterials von der leitfähigen Kontaktinsel zu der oberen Kontakthöckerschicht entlang Seitenwänden der unteren Kontakthöckerschicht zu blockieren. In einigen Ausführungsformen ist die Sperrschicht ein Abstandshalter, der die Seitenwände der unteren Kontakthöckerschicht auskleidet. In anderen Ausführungsformen befindet sich die Sperrschicht zwischen der Sperrschicht und der leitfähigen Kontaktinsel ...

Flip-chip bonding arrangement

Methods for optimized fabrication of a structure to be assembled by hybridization and a device comprising such a structure

Transfer substrate for forming metal wiring and method for forming metal wiring using the transfer substrate

본 발명은 기판과, 상기 기판 상에 형성된 하나 이상의 금속 배선 소재와, 상기 기판과 상기 금속 배선 소재 사이에 형성된 하지 금속막(underlying metal film)으로 이루어지며, 상기 금속 배선 소재를 피전사물에 전사시키기 위한 전사용 기판으로서, 상기 금속 배선 소재는, 순도 99.9 중량% 이상, 평균 입자경 0.01 ㎛~1.0 ㎛인 금 분말 등을 소결하여 이루어지는 성형체이며, 상기 하지 금속막은, 금 등의 금속 또는 합금 등으로 이루어지는 전사용 기판이다. 이 전사용 기판은, 피전사물의 가열온도를 80~300℃로 하더라도 금속 배선 소재를 피전사물에 전사할 수 있다. The present invention comprises a substrate, at least one metal wiring material formed on the substrate, and an underlying metal film formed between the substrate and the metal wiring material to transfer the metal wiring material to the transfer object. The metal wiring material is a molded body obtained by sintering a gold powder having a purity of 99.9% by weight or more and an average particle diameter of 0.01 μm to 1.0 μm, and the base metal film is made of a metal or an alloy such as gold, or the like. It is a transfer substrate. The transfer substrate can transfer the metal wiring material to the transfer object even when the heating temperature of the transfer object is 80 to 300 ° C.

TRANSFER SUBSTRATE FOR FORMING METAL WIRING LINE AND METHOD FOR FORMING METAL WIRING LINE BY MEANS OF SAID TRANSFER SUBSTRATE

IC chip and an IC chip manufacturing method thereof

An IC chip and an IC chip manufacturing method thereof are provided. The IC chip has a body and at least a bump. The body has at least a conducting area on the surface. The bump is formed on the conducting area. The bump includes a plurality of protrusions and at least a conducting material. The plurality of protrusions protrude out of the conducting area separately. The conducting material covers the protrusions and electrically couples to the conducting area. The method includes: (A)providing a body, wherein the body has a conducting area on the surface; (B) forming a plurality of protrusions on the body, wherein the plurality of protrusions protrude out of the conducting area separately; and (C) forming at least a conducting material, wherein the conducting material covers the protrusions and electrically couples to the conducting area.

Film scheme for bumping

A bump structure with a barrier layer, and a method for manufacturing the bump structure, are provided. In some embodiments, the bump structure comprises a conductive pad, a conductive bump, and a barrier layer. The conductive pad comprises a pad material. The conductive bump overlies the conductive pad, and comprises a lower bump layer and an upper bump layer covering the lower bump layer. The barrier layer is configured to block movement of the pad material from the conductive pad to the upper bump layer along sidewalls of the lower bump layer. In some embodiments, the barrier layer is a spacer lining the sidewalls of the lower bump layer. In other embodiments, the barrier layer is between the barrier layer and the conductive pad, and spaces the sidewalls of the lower bump layer from the conductive pad.

Integrated circuit contactor, and method and apparatus for production of integrated circuit contactor

An integrated circuit contactor includes a base of an insulating material, the base being elastically deformable. A plurality of pads of a first conductive material are bonded to the base at positions corresponding to positions of terminals on an integrated circuit. A plurality of contacts of a second conductive material are bonded to the plurality of pads, respectively, the terminals of the integrated circuit being electrically connected to the contacts only when a pressure is exerted onto the contacts by the terminals of the integrated circuit, each contact having a projecting edge with a roughness produced by pulling a wire of the second conductive material apart from a corresponding one of the plurality of pads after the wire is bonded to the corresponding pad.

Structure and formation method of chip package with redistribution layers

Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a protective layer surrounding the semiconductor die. The chip package also includes an interface between the semiconductor die and the protective layer. The chip package further includes a conductive layer over the protective layer and the semiconductor die, and the conductive layer has a first portion and a second portion. The first portion is closer to an inner portion of the semiconductor die than the second portion. The first portion is in direct contact with the second portion. The second portion extends across the interface, and the second portion has a line width greater than that of the first portion.

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

A method for manufacturing a semiconductor device includes following operations. A first substrate with a conductive pad is received. A connector is disposed over the conductive pad. A second substrate including a conductive land is provided. A position of the first substrate or the second substrate is adjusted thereby a geometric center of the conductive land is deviated from a geometric center of the connector in a deviated distance. The connector is bonded with the conductive land. A temperature of the semiconductor device is adjusted so as to control elongation of the first substrate and the second substrate, thereby the geometric center of the connector is substantially aligned with the geometric center of the conductive land.

WAFER LEVEL INTEGRATION INCLUDING DESIGN/CO-DESIGN, STRUCTURE PROCESS, EQUIPMENT STRESS MANAGEMENT AND THERMAL MANAGEMENT

A multi-layer wafer and method of manufacturing such wafer are provided. The method comprises creating under bump metallization (UMB) pads on each of the two heterogeneous wafers; applying a conductive means above the UMB pads on at least one of the two heterogeneous wafers; and low temperature bonding the two heterogeneous wafers to adhere the UMB pads together via the conductive means. At least one stress compensating polymer layer may be applied to at least one of two heterogeneous wafers. The multi-layer wafer comprises two heterogeneous wafers, each of the heterogeneous wafer having UMB pads and at least one of the heterogeneous wafers having a stress compensating polymer layer and a conductive means applied above the UMB pads on at least one of the two heterogeneous wafers. The two heterogeneous wafers low temperature bonded together to adhere the UMB pads together via the conductive means. 115-. (canceled)16. A multi-layer wafer comprising:two heterogeneous wafers, each of the heterogeneous wafer having under bump metallization pads and at least one of the heterogeneous wafers having one of a stress compensating or adhesive polymer layer; anda conductive means applied above the under bump metallization pads on at least one of the two heterogeneous wafers;the two heterogeneous wafers low temperature bonded together to adhere the under bump metallization pads together via the conductive means to form a multi-layer wafer pair.17. The multi-layer wafer of claim 16 , wherein the conductive means is one of solder balls claim 16 , conductive paste claim 16 , or solder topped copper pillars.18. The multi-layer wafer of claim 16 , wherein the conductive means is formed from one of In claim 16 , InSn claim 16 , InBi claim 16 , Sn alloys claim 16 , other high Sn solder alloys claim 16 , Pb claim 16 , PbSn claim 16 , other high lead alloys claim 16 , Cu claim 16 , Ni claim 16 , Au claim 16 , Ag claim 16 , Pt claim 16 , Pd claim 16 , or combinations therein that can be ...

Metal Bump Joint Structure and Methods of Forming

A structure comprises a first semiconductor chip with a first metal bump and a second semiconductor chip with a second metal bump. The structure further comprises a solder joint structure electrically connecting the first semiconductor chip and the second semiconductor chip, wherein the solder joint structure comprises an intermetallic compound region between the first metal bump and the second metal bump, wherein the intermetallic compound region is with a first height dimension and a surrounding portion formed along exterior walls of the first metal bump and the second metal bump, wherein the surrounding portion is with a second height dimension, and wherein the second height dimension is greater than the first height dimension.

Verfahren zur Herstellung von optoelektronischen Bauelementen und optoelektronisches Bauelement

Es wird ein Verfahren zur Herstellung von optoelektronischen Bauelementen (1) angegeben, bei dem eine Mehrzahl von Halbleiterkörpern (2) mit jeweils einer Halbleiterschichtenfolge bereitgestellt wird. Weiterhin wird ein Bauelementträgerverbund (30) mit einer Mehrzahl von Anschlussflächen (35) bereitgestellt. Die Halbleiterkörper (2) werden relativ zum Bauelementträgerverbund (30) positioniert. Zwischen den Anschlussflächen (35) und den zugeordneten Halbleiterkörpern (2) wird eine elektrisch leitende Verbindung hergestellt und die Halbleiterkörper werden an dem Bauelementträgerverbund (30) befestigt. Die optoelektronischen Bauelemente (2) werden fertig gestellt, wobei für jedes optoelektronische Bauelement (1) ein Bauelementträger (30) aus dem Bauelementträgerverbund (3), auf dem die Halbleiterkörper (2) befestigt sind, ausgebildet wird. Ferner wird ein optoelektronisches Bauelement angegeben.

Implantable microelectronic device and method of manufacture

반도체 장치

... 반도체 장치가 제공된다. 반도체 장치는 기판, 기판 상에 배치되는 보호막으로, 보호막을 관통하는 트렌치를 포함하는 보호막, 트렌치의 적어도 일부를 채우는 제1 부분과, 보호막 상에 배치되는 제2 부분을 포함하는 하부 범프 및 하부 범프 상에 배치되는 상부 범프를 포함하고, 보호막은, 트렌치의 측벽을 포함하는 제1 부분 및 제2 부분을 포함하고, 기판의 상면으로부터 상기 보호막의 제1 부분의 상면까지의 제1 높이는, 기판의 상면으로부터 상기 보호막의 제2 부분의 상면까지의 제2 높이보다 크다.

Substrate holder and plating apparatus

The present invention is to provide a substrate holder which can effect a more complete sealing with a sealing member and makes it possible to take a substrate out of the substrate holder easily and securely, and also a plating apparatus provided with the substrate holder. The substrate holder includes: a fixed holding member and a movable holding member for holding a substrate therebetween; a sealing member mounted to the fixed holding member or the movable holding member; and a suction pad for attracting a back surface of the substrate held between the fixed holding member and the movable holding member.

METHOD OF SOLDER BUMPING A CIRCUIT COMPONENT AND CIRCUIT COMPONENT FORMED THEREBY

A circuit component and method by which degradation of a solder connection by electromigration can be prevented or reduced. The component generally includes an interconnect pad on a surface of the component, a metallic multilayer structure overlying the interconnect pad and having a solderable surface layer, and a solder material on the multilayer structure. According to a preferred aspect of the component and method, a stud is wire-bonded to the solderable surface layer of the multilayer structure and encased by the solder material to provide a low electrical resistance path through the solder material.

Wafer level integration including design/co-design, structure process, equipment stress management and thermal management

A method of manufacturing a multi-layer wafer is provided. Under bump metallization (UMB) pads are created on each of two heterogeneous wafers. A conductive means is applied above the UMB pads on at least one of the two heterogeneous wafers. The two heterogeneous wafers are low temperature bonded to adhere the UMB pads together via the conductive means. At least one stress compensating polymer layer may be applied to at least one of two heterogeneous wafers. The stress compensating polymer layer has a polymer composition of a molecular weight polymethylmethacrylate polymer at a level of 10-50% with added liquid multifunctional acrylates forming the remaining 50-90% of the polymer composition.

Structure and method of making capped chips having vertical interconnects

Capped chips and methods of forming a capped chip are provided in which electrical interconnects are made by conductive elements which extend from bond pads of a chip at least partially through a plurality of through holes of a cap. The electrical interconnects may be solid, so as to form seals extending across the through holes. In some cases, stud bumps extend from the bond pads, forming parts of the electrical interconnects. In some cases, a fusible conductive medium forms a part of the electrical interconnects.

Electrochemical deposition method

The present invention is to provide a substrate holder which can effect a more complete sealing with a sealing member and makes it possible to take a substrate out of the substrate holder easily and securely, and also a plating apparatus provided with the substrate holder. The substrate holder includes: a fixed holding member and a movable holding member for holding a substrate therebetween; a sealing member mounted to the fixed holding member or the movable holding member; and a suction pad for attracting a back surface of the substrate held between the fixed holding member and the movable holding member.

Voltage regulator integrated with semiconductor chip

The present invention reveals a semiconductor chip structure and its application circuit network, wherein the switching voltage regulator or converter is integrated with a semiconductor chip by chip fabrication methods, so that the semiconductor chip has the ability to regulate voltage within a specific voltage range. Therefore, when many electrical devices of different working voltages are placed on a Printed Circuit Board (PCB), only a certain number of semiconductor chips need to be constructed. Originally, in order to account for the different demands in voltage, power supply units of different output voltages, or a variety of voltage regulators need to be added. However, using the built-in voltage regulator or converter, the voltage range can be immediately adjusted to that which is needed. This improvement allows for easier control of electrical devices of different working voltages and decreases response time of electrical devices.

SUBSTRATE HOLDER AND PLATING APPARATUS

본 발명은 밀봉부재로 보다 완벽한 밀봉을 실행할 수 있고, 기판홀더로부터 기판을 용이하면서도 확실하게 떼어낼 수 있도록 하는 기판홀더를 제공하며, 또한 상기 기판홀더가 제공된 도금장치도 제공한다. 기판홀더(18)는, 그 사이에 기판(W)을 유지시키는 고정유지부재(54)와 가동유지부재(58); 상기 고정유지부재(54) 또는 가동유지부재(58)에 장착된 밀봉부재(68); 및 상기 고정유지부재(54)와 가동유지부재(58) 사이에 유지된 기판(W)의 뒷면을 끌어당기는 흡입패드(94)를 포함하는 것을 특징으로 한다. The present invention provides a substrate holder which can perform a more perfect sealing with a sealing member and can easily and reliably detach a substrate from the substrate holder, and also provides a plating apparatus provided with the substrate holder. The substrate holder 18 includes a fixed holding member 54 and a movable holding member 58 for holding the substrate W therebetween; A sealing member 68 mounted to the fixed holding member 54 or the movable holding member 58; And a suction pad 94 which pulls the rear surface of the substrate W held between the fixed holding member 54 and the movable holding member 58.

METHOD FOR PRODUCING OPTOELECTRONIC COMPONENTS, AND OPTOELECTRONIC COMPONENT

프리-코팅 상호연결 요소를 포함하는 플립-칩 조립 방법

... 본 발명은, 제1 및 제2 전자 구성요소(50 및 52)를 조립하는 방법으로서, ■ 상기 제1 구성요소(50)의 조립 표면 상에 연결 요소를 형성하고, 상기 제2 구성요소(52)의 조립 표면 상에 연결 요소를 형성하는 단계; ■ 상기 제1 및/또는 상기 제2 구성요소의 조립 표면 상에 전기-절연 경화성 소재(70)의 액체 층을 퇴적하는 단계; ■ 상기 제1 및 상기 제2 구성요소(50 및 52)를 서로의 위에 배치하여, 상기 제1 구성요소의 연결 요소 앞에 상기 제2 구성요소의 연결 요소를 놓는 단계; ■ 상기 제1 및/또는 상기 제2 구성요소(50 및 52) 상에서 미리 결정된 방향(A)을 따라 힘을 적용하여, 전기 상호연결부 - 각각의 상호연결부는 상기 제1 구성요소(50)의 연결 요소(56)와 상기 제2 구성요소(52)의 연결 요소(58)로 형성됨 - 를 만드는 단계; 및 ■ 상기 경화성 소재(70)를 경화시키는 단계를 포함하는, 방법에 관한 것이다. 상기 제1 구성요소(50)의 연결 요소(56)는 개방 단부를 갖는 공동 인서트(hollow inserts)이고, 상기 제2 구성요소(52)의 연결 요소(58)는 상기 인서트(56)보다 더 작은 경도를 갖는 고체 요소이며, 힘의 적용이 결국 상기 공동 요소(56)가 상기 고체 요소(58) 내에 삽입되게 한다. 상기 인서트(56)의 기하학적 모양 및 상기 고체 요소(58)의 기하학적 모양 및/또는 삽입 동안의 그 상대적인 위치 지정이 삽입 동안 상기 인서트(56)의 개방 단부의 일부분을 노출시키도록 선택된다. 상기 경화성 소재(70)는 탈산 플럭스(deoxidizing flux)를 포함하지 않는다.

SEMICONDUCTOR PACKAGE DEVICE FOR PREVENTING THE INTERFERENCE BETWEEN SOLDER BALLS

PURPOSE: A semiconductor package device is provided to produce an ultra-fine pitch of a package connection solder ball by leading a solder ball so that the package connection solder ball is formed to be long in upper and lower directions. CONSTITUTION: A first semiconductor package(10) comprises a first semiconductor chip, a first substrate, a first terminal, and a first signal transfer medium. A second semiconductor package(20) comprises a second semiconductor chip, a second substrate, a second terminal, and a second signal transfer medium. A package connection solder ball(30) is installed between the first terminal and the second terminal so that the first terminal and the second terminal are connected electrically. A first solder ball guide member(41) comprises a first guide side which guides a shape of the package connection solder ball. COPYRIGHT KIPO 2013 ...

LEAD-FREE SOLDER BALL

Transfer substrate for forming metallic wiring and method for forming metallic wiring with the use of the transfer substrate

METHOD FOR PRODUCING OPTOELECTRONIC COMPONENTS, AND OPTOELECTRONIC COMPONENT

A method for producing optoelectronic components (1) is specified, in which a plurality of semiconductor bodies (2) each having a semiconductor layer sequence are provided. A component carrier assemblage (30) having a plurality of connection pads (35) is also provided. The semiconductor bodies (2) are positioned relative to the component carrier assemblage (30). An electrically conductive connection is produced between the connection pads (35) and the associated semiconductor bodies (2), and the semiconductor bodies are fastened to the component carrier assemblage (30). The optoelectronic components (2) are completed, wherein a component carrier (3) is formed for each optoelectronic component (1) from the component carrier assemblage (30) on which the semiconductor bodies (2) are fastened. An optoelectronic component is also specified.

GOLD BONDING IN SEMICONDUCTOR DEVICES USING POROUS GOLD

A method of manufacturing comprising providing a semiconductor layer having metal adhesion layer on a planar surface of the semiconductor layer and an alloy layer on the metal adhesion layer, the alloy layer comprising an alloy of gold and a non-gold metal. The method comprises removing a portion of the non-gold metal from the alloy layer to form a porous gold layer. The method comprises applying pressure between the porous gold layer and a metal layer to form a bond between the semiconductor layer and the metal layer.

Electrochemical deposition method

The present invention is to provide a substrate holder which can effect a more complete sealing with a sealing member and makes it possible to take a substrate out of the substrate holder easily and securely, and also a plating apparatus provided with the substrate holder. The substrate holder includes: a fixed holding member and a movable holding member for holding a substrate therebetween; a sealing member mounted to the fixed holding member or the movable holding member; and a suction pad for attracting a back surface of the substrate held between the fixed holding member and the movable holding member.

ELECTROCHEMICAL DEPOSITION METHOD

The present invention is to provide a substrate holder which can effect a more complete sealing with a sealing member and makes it possible to take a substrate out of the substrate holder easily and securely, and also a plating apparatus provided with the substrate holder. The substrate holder includes: a fixed holding member and a movable holding member for holding a substrate therebetween; a sealing member mounted to the fixed holding member or the movable holding member; and a suction pad for attracting a back surface of the substrate held between the fixed holding member and the movable holding member.

Hybridverbindungs-Bauelement und Verfahren

Bei einer Ausführungsform weist ein Verfahren die folgenden Schritte auf: Herstellen einer Verbindung, die Wellenleiter und leitfähige Strukturelemente umfasst, die in mehreren dielektrischen Schichten angeordnet sind, wobei die leitfähigen Strukturelemente leitfähige Leitungen und Durchkontaktierungen umfassen, die Wellenleiter aus einem ersten Material mit einer ersten Brechzahl bestehen und die dielektrischen Schichten aus einem zweiten Material mit einer zweiten Brechzahl bestehen, die kleiner als die erste Brechzahl ist; Bonden mehrerer Dies an eine erste Seite der Verbindung, wobei die Dies elektrisch durch die leitfähigen Strukturelemente verbunden werden und optisch durch die Wellenleiter verbunden werden; und Herstellen mehrerer leitfähiger Verbindungselemente auf einer zweiten Seite der Verbindung, wobei die leitfähigen Verbindungselemente durch die leitfähigen Strukturelemente elektrisch mit den Dies verbunden werden.

Implantable microelectronic device and method of manufacture

Method of fabricating bump structure

MANUFACTORING PROCESS OF TWO SUBSTRATES CONNECT BY AT LEAST A MECHANICAL CONNECTION AND ELECTRICALLY CONDUCTING OBTAINED

Un premier substrat (2) muni d'une zone d'accueil (1) en premier matériau métallique est fourni. Un second substrat (4) muni d'une zone d'insertion (3) comportant une surface de base (6) et au moins un plot (7) en un second matériau métallique est disposé en face du premier substrat (2). Le plot (7) fait sailli depuis la surface de base (6). Une pression est appliquée entre le premier substrat (2) et le second substrat (4) de manière à faire pénétrer le plot (7) à l'intérieur de la zone d'accueil (1). Le premier matériau métallique (5) réagit avec le second matériau métallique de manière à former une couche continue d'un composé intermétallique (5) à base des premier et second matériaux métalliques le long de l'interface entre le plot (7) et la zone d'accueil (1).

PROCESS FOR CONNECTING INTERCOMPOSANTS DENSITY OPTIMIZED

L'invention concerne un procédé de connexion électrique par hybridation d'un premier composant (100) à un deuxième composant (200). Le procédé comportant les étapes suivantes : formation de plots en matériau ductile (111, 121) en contact respectif des zones de connexion (110, 120) du premier composant (100) ; formation d'inserts (211, 221) en matériau conducteur en contact de des zones de connexion (210, 220) du deuxième composant (200) ; formation de barrières d'hybridation (212, 222) disposées entre les inserts (211, 221) et isolées électriquement l'une de l'autre, lesdites première et deuxième barrière d'hybridation (212, 222) pour faire office de barrière en contenant la déformation des plots en matériau ductile (111, 121) lors de la connexion des zones de connexion (210, 220) du premier composant (100) avec celles du deuxième composant (200). L'invention concerne en outre un ensemble (1) de deux composants (100, 200) connectés ...

SEMICONDUCTOR DEVICE HAVING SOLDER JOINT AND FORMING METHOD THEREOF

The present invention relates to a semiconductor device having a high-reliability solder joint. A high-temperature solder is formed on a conductive pad. A low-temperature solder having a lower melting point than the high-temperature solder is formed on the high-temperature solder. A barrier layer is formed between the high-temperature solder and the low-temperature solder. A Sn content of the high-temperature solder is higher than a Sn content of the low-temperature solder. COPYRIGHT KIPO 2016 ...

Semiconductor assembly and semiconductor package including a solder channel

Semiconductor packages connecting a semiconductor chip to an external device by bumps are provided. The semiconductor packages may include a connection pad on a semiconductor chip, a connecting bump on and configured to be electrically connected to the connection pad and a supporting bump on the semiconductor chip and configured to be electrically isolated from the connection pad. The connection bump may include a first pillar and a first solder ball and the supporting bump may include a second pillar and a second solder ball. The semiconductor packages may further include a solder channel in the second pillar configured to allow a portion of the second solder ball to extend into the solder channel along a predetermined direction.

Electrode arrays and methods of fabricating the same using printing plates to arrange particles in an array

Electrode arrays and methods of fabricating the same using a printing plate to arrange conductive particles in alignment with an array of electrodes are provided. In one embodiment, a semiconductor device comprises: a semiconductor topography comprising an array of electrodes disposed upon a semiconductor substrate; a dielectric layer residing upon the semiconductor topography; and at least one conductive particle disposed in or on the dielectric layer in alignment with at least one of the array of electrodes.

Test Structure and Method of Testing Electrical Characteristics of Through Vias

A method and apparatus for testing the electrical characteristics, such as electrical continuity, is provided. A substrate, such as a wafer or an interposer, having a plurality of through vias (TVs) is provided. Along one side of the substrate, a conductive layer electrically couples two or more of the TVs. Thereafter, the electrical characteristics of the TVs may be test by, for example, a probe card in electrical contact with the TVs on the other side of the substrate. During testing, current passes through a first TV from a first side of the substrate, to the conductive layer on a second side of the substrate, to a second TV, and back to the first side of the substrate through the second TV.

Packaging Process Tools and Systems, and Packaging Methods for Semiconductor Devices

Packaging process tools and systems, and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging process tool for semiconductor devices includes a mechanical structure for supporting package substrates or integrated circuit die during a packaging process for the integrated circuit die. The mechanical structure includes a low thermal conductivity material disposed thereon.

Cleaning Methods and Compositions

Methods and chemical solvents used for cleaning residues on metal contacts during a semiconductor device packaging process are disclosed. A chemical solvent for cleaning a residue formed on a metal contact may comprise a reactive inorganic component and a reactive organic component. The method may comprise spraying a semiconductor device with a chemical solvent at a first pressure, and spraying the semiconductor device with the chemical solvent at a second pressure less than the first pressure.

Semiconductor chip with expansive underbump metallization structures

Methods and apparatus to protect fragile dielectric layers in a semiconductor chip are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first polymer layer over a conductor pad of a semiconductor chip where the conductor pad has a first lateral dimension. An underbump metallization structure is formed on the first polymer layer and in ohmic contact with the conductor pad. The underbump metallization structure has a second lateral dimension greater than the first lateral dimension. A second polymer layer is formed on the first polymer layer with a first opening exposing at least a portion of the underbump metallization structure.

CONDUCTIVE CONNECTIONS, STRUCTURES WITH SUCH CONNECTIONS, AND METHODS OF MANUFACTURE

A solder connection may be surrounded by a solder locking layer () and may be recessed in a hole () in that layer. The recess may be obtained by evaporating a vaporizable portion () of the solder connection. Other features are also provided. 1. A manufacturing method comprising: one or more first components each of which comprises solder and a material sublimatable or vaporizable when the solder is melted; and', 'a first layer comprising a top surface and one or more holes in the top surface, each hole containing at least a segment of a corresponding first component;, 'obtaining a first structure comprisingheating each first component to sublimate or vaporize at least part of each sublimatable or vaporizable material and provide an electrically conductive connection at a location of each first component;wherein in the heating operation at least part of each first component recedes down from the top surface to provide or increase a recess in each hole at the top surface.2. The method of wherein each hole is a through-hole.3. The method of wherein each hole's sidewall is a dielectric sidewall.4. The method of wherein the first layer is dielectric.5. The method of wherein the first layer is formed by molding.6. The method of further comprising:obtaining a second structure with one or more protruding conductive posts; andinserting each conductive post into a corresponding recess provided or increased in the heating operation, and forming a solder bond in each recess between the corresponding conductive post and the corresponding electrically conductive connection.7. The method of wherein before the heating operation claim 1 , at least a segment of each first component either:comprises of a solder core coated with the sublimatable or vaporizable material; orconsists of the sublimatable or vaporizable material.8. The method of wherein in obtaining the first structure claim 7 , the one or more first components are formed before the first layer.9. The method of wherein in ...

DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF

A display device includes: a flexible substrate having a display area for displaying an image and a peripheral area outside the display area; a first pad electrode in the peripheral area of the flexible substrate; and a driver connected to the first pad electrode. The driver includes: a circuit board including a driving circuit; a second pad electrode on one side of the circuit board and facing the first pad electrode; a convex structure on one side of the second pad electrode and having an oval cross-section; and a bump electrode on one side of the convex structure and connected to the first pad electrode. The bump electrode includes a column covering the convex structure and a convex portion extending from one side of the column and protruding to the first pad electrode. 1. A display device comprising:a flexible substrate having a display area for displaying an image and a peripheral area outside the display area;a first pad electrode in the peripheral area of the flexible substrate; and a circuit board comprising a driving circuit;', 'a second pad electrode on one side of the circuit board and facing the first pad electrode;', 'a convex structure on one side of the second pad electrode and having an oval cross-section; and', 'a bump electrode on one side of the convex structure and connected to the first pad electrode, the bump electrode comprising a column covering the convex structure and a convex portion extending from one side of the column and protruding to the first pad electrode., 'a driver connected to the first pad electrode, the driver comprising2. The display device of claim 1 , wherein the convex structure protrudes to the first pad electrode.3. The display device of claim 2 , further comprising a contact auxiliary electrode on the first pad electrode claim 2 ,wherein the convex portion contacts the contact auxiliary electrode.4. The display device of claim 3 , wherein the convex structure comprises solder or a polymer material.5. The display device ...

CONDUCTIVE BUMP AND ELECTROLESS Pt PLATING BATH

The present invention provides a bump that can prevent diffusion of a metal used as a base conductive layer of the bump into a surface of an Au layer or an Ag layer. A conductive bump of the present invention is a conductive bump formed on a substrate. The conductive bump comprises, at least in order from the substrate: a base conductive layer; a Pd layer; a Pt layer; and an Au layer or an Ag layer having directly contact with the Pd layer, wherein a diameter of the conductive bump is 20 μm or less.

SEMICONDUCTOR DEVICES

A semiconductor device includes a substrate, a protection layer on the substrate that includes a trench that penetrates therethrough, a lower bump that includes a first part that fills at least a portion of the trench and a second part on the protection layer; and an upper bump on the lower bump. The protection layer includes a first part that surrounds the trench and a second part that surrounds the first part. A first height from an upper surface of the substrate to an upper surface of the first part of the protection layer is greater than a second height from the upper surface of the substrate to an upper surface of the second part of the protection layer. 1. A semiconductor device , comprising:a substrate;a protection layer on the substrate, the protection layer including a trench that penetrates therethrough;a lower bump that includes a first part that fills at least a portion of the trench and a second part on the protection layer, wherein an upper surface of the first art of the lower bump is curved downward toward the substrate; andan upper bump on the lower bump,wherein the protection layer includes a first part that surrounds the trench and a second part that surrounds the first part, anda first height from an upper surface of the substrate to an upper surface of the first part of the protection layer is greater than a second height from the upper surface of the substrate to an upper surface of the second part of the protection layer.2. The semiconductor device according to claim 1 , wherein the lower bump includes a recess claim 1 , andthe upper bump includes a first part in the recess and a second part on the first part.3. The semiconductor device according to claim 1 , wherein an upper surface of the first part of the lower bump includes a second point spaced apart by a first distance from a first point on a sidewall of the trench in a first direction parallel to the upper surface of the substrate and a third point spaced apart by a second distance from ...

Package on Package Devices and Methods of Packaging Semiconductor Dies

Package on package (PoP) devices and methods of packaging semiconductor dies are disclosed. A PoP device includes a first packaged die and a second packaged die coupled to the first packaged die. Metal stud bumps are disposed between the first packaged die and the second packaged die. The metal stud bumps include a stick region, a first ball region coupled to a first end of the stick region, and a second ball region coupled to a second end of the stick region. The metal stud bumps include a portion that is partially embedded in a solder joint. 1. A semiconductor device , comprising:a first substrate;a second substrate coupled to the first substrate;a plurality of metal stud bumps disposed between the first substrate and the second substrate, wherein each of the plurality of metal stud bumps includes a stick region, a first ball region coupled to a first end of the stick region, and a second ball region coupled to a second end of the stick region, the first ball region, the second ball region, and the stick region being a single continuous material, wherein the first ball region and the second ball region have a larger width than the stick region; andsolder joints extending from the second substrate to the first substrate, each of the solder joints extending along a corresponding one of the plurality of metal stud bumps.2. The semiconductor device according to claim 1 , wherein the first ball region and the second ball region of the plurality of metal stud bumps comprise a width of about 1.2 to 3.0 times a width of the stick region of the plurality of metal stud bumps.3. The semiconductor device according to claim 2 , wherein the first ball region and the second ball region of the plurality of metal stud bumps have a height of about 50 to 150 μm.4. The semiconductor device according to claim 1 , wherein the stick region of the plurality of metal stud bumps comprises a width of about 1 to 10 mils.5. The semiconductor device according to claim 4 , wherein the first ...

Elongated Bump Structures in Package Structure

A package structure includes a chip attached to a substrate. The chip includes a bump structure including a conductive pillar having a length (L) measured along a long axis of the conductive pillar and a width (W) measured along a short axis of the conductive pillar. The substrate includes a pad region and a mask layer overlying the pad region, wherein the mask layer has an opening exposing a portion of the pad region. The chip is attached to the substrate to form an interconnection between the conductive pillar and the pad region. The opening has a first dimension (d) measured along the long axis and a second dimension (d) measured along the short axis. In an embodiment, L is greater than d, and W is less than d 1. A method of forming a package structure , comprising:placing a conductive structure over an opening through a masking layer, the opening exposing a conductive element; andreflowing a portion of the conductive structure to bond the conductive structure to the conductive element, wherein after the reflowing the portion of the conductive structure the conductive structure extends in a first direction further than the opening and extends in a second direction less than the opening, the first direction being perpendicular to the second direction.2. The method of claim 1 , wherein the conductive structure comprises a first length along a first axis and a first width along a second axis perpendicular to the first axis claim 1 , the first length being longer than the first width.3. The method of claim 2 , wherein the first length is between about 70 μm and about 150 μm.4. The method of claim 3 , wherein the first width is between about 40 and about 100 μm.5. The method of claim 2 , wherein a ratio between the first length and the first width is between about 1.75 and about 1.5.6. The method of claim 1 , further comprising a molding compound located adjacent to the conductive structure.7. The method of claim 1 , wherein there is no molding compound adjacent to ...

Semiconductor chip, display panel, and electronic device

A semiconductor chip, a display device or an electronic device includes a substrate, one or more conductive pads disposed on the substrate, and one or more bumps electrically connected to the one or more conductive pads, in which the one or more bumps includes a metal core, a polymer layer disposed over a surface of the metal core, and a conductive coating layer disposed over a surface of the polymer layer and electrically connected to the one or more conductive pads.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a first carrier including a first pad, a second carrier including a second pad disposed opposite to the first pad, a joint coupled with and standing on the first pad, a joint encapsulating the post and bonding the first pad with the second pad, a first entire contact interface between the first pad and the joint, a second entire contact interface between the first pad and the post, and a third entire contact interface between the joint and the second pad. The first entire contact interface, the second entire contact interface and the third entire contact interface are flat surfaces. A distance between the first entire contact interface and the third entire contact interface is equal to a distance between the second entire contact interface and the third entire contact interface. The second entire contact interface is a continuous surface. 1. A semiconductor device , comprising:a silicon substrate;a carrier;a first pad on the silicon substrate;a second pad on the carrier;a post on a surface of the first pad, wherein the post consists of a metal or a metal alloy;a joint disposed between the silicon substrate and the carrier, contacted with the first pad and the second pad, and encapsulating the post;a first entire contact interface between the first pad and the joint;a second entire contact interface between the first pad and the post; anda third entire contact interface between the joint and the second pad,wherein an outer surface of the joint is concaved and curved towards the post, and a height of the post is greater than or equal to ⅓ of a height of the joint between the first pad and the second pad, the first entire contact interface, the second entire contact interface and the third entire contact interface are flat surfaces, wherein a distance between the first entire contact interface and the third entire contact interface is equal to a distance between the second entire contact interface and the third entire contact interface, ...

Design Scheme for Connector Site Spacing and Resulting Structures

A system and method for preventing cracks in a passivation layer is provided. In an embodiment a contact pad has a first diameter and an opening through the passivation layer has a second diameter, wherein the first diameter is greater than the second diameter by a first distance of about 10 μm. In another embodiment, an underbump metallization is formed through the opening, and the underbump metallization has a third diameter that is greater than the first diameter by a second distance of about 5 μm. In yet another embodiment, a sum of the first distance and the second distance is greater than about 15 μm. In another embodiment the underbump metallization has a first dimension that is less than a dimension of the contact pad and a second dimension that is greater than a dimension of the contact pad. 1. A device comprising:a first contact pad on a first substrate, the first contact pad having a first line of symmetry and a second line of symmetry, the first line of symmetry being perpendicular to the second line of symmetry, the first contact pad having a first width along the first line of symmetry, the first contact pad having a second width along the second line of symmetry;a first underbump metallization on the first contact pad; anda first conductive bump on the first underbump metallization, the first conductive bump, having a third line of symmetry and a fourth line of symmetry, the third line of symmetry being perpendicular to the fourth line of symmetry, the first conductive bump having a third width along the third line of symmetry, the first conductive bump having a fourth width along the fourth line of symmetry, the third width being greater than the first width, the fourth width being less than the second width.2. The device of claim 1 , wherein the first width is equal to the second width.3. The device of claim 1 , wherein the first width is different from the second width.4. The device of further comprising:a second contact pad on the first substrate; ...

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

Provided is a semiconductor package and a method of making same, including a first package substrate; a first semiconductor chip mounted on the first package substrate and having a first pad and a second pad, wherein the first pad is provided on a top of the first semiconductor chip and the second pad is provided on a bottom of the first semiconductor chip, the bottom being an opposite surface of the top; and a clad metal provided on the first pad and electrically connecting the first semiconductor chip to one of a second semiconductor chip and second package substrate provided on the top of the first semiconductor chip. 1. A semiconductor package comprising:a first package substrate;a first semiconductor chip mounted on the first package substrate and having a first pad and a second pad, wherein the first pad is provided on a top of the first semiconductor chip and the second pad is provided on a bottom of the first semiconductor chip, the bottom being an opposite surface of the top; anda clad metal provided on the first pad and electrically connecting the first semiconductor chip to one of a second semiconductor chip and a second package substrate provided on the top of the first semiconductor chip.2. The semiconductor package of claim 1 , wherein the clad metal comprises at least a first layer of metal and a second layer of metal claim 1 , the first layer of metal with which the clad metal is in contact with the first pad being formed of a same type of metal as the first pad.3. The semiconductor package of claim 2 , further comprising a solder ball provided between the second layer of metal and a second pad of the one of the second semiconductor chip and the second package substrate connected thereto.4. The semiconductor package of claim 3 , wherein a recess is formed in the second layer of metal being in contact with the solder ball.5. The semiconductor package of claim 2 , wherein the clad metal and the first semiconductor chip are connected by ultrasonic ...

METHOD FOR FORMING SUPERCONDUCTING STRUCTURES

A superconducting structure includes a first superconducting device having a plurality of first superconducting contact pads disposed on a top side of a first superconducting device, a second superconducting device having a plurality of second superconducting contact pads disposed on a bottom side of a second superconducting device, and a plurality of superconducting bump structures with a given bump structure coupling respective superconducting contact pads of the plurality of first superconducting contact pads and the second plurality of superconducting pads to one another to bond the first superconducting device to the second superconducting device. Each superconducting bump structure includes a first under bump metallization (UBM) layer disposed on the top surface of a given superconducting contact pad, a second UBM layer disposed on the top surface of a given superconducting contact pads, and a superconducting metal layer coupling the first UBM layer to the second UBM layer. 1. A method of forming a superconducting structure , the method comprising:performing a first cleaning process on a top surface of a plurality of first superconducting contact pads disposed on a top side of a first superconducting device;depositing a first under bump metallization (UBM) layer on the top surface of each of the plurality of first superconducting contact pads;depositing a superconducting metal layer on each of the first UBM layers;performing a second cleaning process on a top surface of each of the superconducting metal layers;performing a third cleaning process on a top surface of a plurality of second superconducting contact pads disposed on a bottom side of a second superconducting device;depositing a second UBM layer on the top surface of each of the plurality of second superconducting contact pads; andperforming a bonding process to connect the first superconducting device and the second superconducting device by coupling the superconducting metal layers of the first ...

Wafer level integration including design/co-design, structure process, equipment stress management and thermal management

A multi-layer wafer and method of manufacturing such wafer are provided. The method comprises applying at least one stress compensating polymer layer to at least one of two heterogeneous wafers and low temperature bonding the two heterogeneous wafers to bond the stress compensating polymer layer to the other of the two heterogeneous wafers to form a multi-layer wafer pair. The multi-layer wafer comprises two heterogeneous wafers, at least one of the heterogeneous wafers having a stress compensating polymer layer. The two heterogeneous wafers are low temperature bonded together to bond the stress compensating polymer layer to the other of the two heterogeneous wafers.

Stack-type semiconductor package

According to example embodiments, a stack-type semiconductor package includes a lower semiconductor package, an upper semiconductor package, connection pads, and a metal layer pattern. The lower semiconductor package includes a lower semiconductor chip on a top surface of a lower package substrate, lower lands on the lower package substrate, and an encapsulant on the top surface of the lower package substrate. The encapsulant defines via holes that expose the lower lands. The upper semiconductor package is on the encapsulant. Upper solder balls are connected to a bottom surface of the upper semiconductor package. The connection pads are on the via holes and the encapsulant. The connection pads electrically connect the lower semiconductor package to the upper semiconductor package. The metal layer pattern is between the lower package substrate and the upper semiconductor package. The metal layer pattern surrounds the connection pads and is isolated from the connection pads.

Method of forming a temporary test structure for device fabrication

A method of forming a temporary test structure for device fabrication is provided. The method allows for electrically testing conductive interconnects during controlled collapse chip connections (C4) fabrication and/or through-silicon vias (TSVs) during interposer fabrication. The method includes providing a substrate containing a plurality of electrically conductive interconnects extending vertically to top surface of the substrate. A temporary test structure is formed to connect the plurality of interconnects for electrical testing. Electrical testing is performed on the substrate by probing at different test locations on the temporary test structure. All or part of the temporary test structure is removed so as not to affect product performance. The temporary test structure can contain electrical test pads which provide a way to make temporary connections to small interconnect landings or features at extreme tight pitch to fan them out to testable pads sizes and pitches.

Biocompatible Bonding Method and Electronics Package Suitable for Implantation

The invention is directed to a method of bonding a hermetically sealed electronics package to an electrode or a flexible circuit and the resulting electronics package, that is suitable for implantation in living tissue, such as for a retinal or cortical electrode array to enable restoration of sight to certain non-sighted individuals. The hermetically sealed electronics package is directly bonded to the flex circuit or electrode by electroplating a biocompatible material, such as platinum or gold, effectively forming a studbump connection, which bonds the flex circuit to the electronics package. The resulting electronic device is biocompatible and is suitable for long-term implantation in living tissue. 1. A method of making an implantable electronic device comprising:forming a hermetic electronics control unit including a contact,forming a flexible circuit including a first thin film flexible electrically insulating substrate, an electrically conducting metal layer deposited on the first insulating layer, a second thin film flexible electrically insulating substrate deposited on the electrically conducting metal layer, at least one bond pad defining a through hole entirely through the flexible circuit;providing weldable material which is electrically conductive and biocompatible;aligning the weldable material, bond pad, and the contact; andwielding the weldable material, bond pad and contact together; andcutting the weldable material.2. The method according to claim 1 , wherein the weldable material is a wire.3. The method according to claim 1 , wherein the weldable materials is a ribbon claim 1 ,4. The method according to claim 1 , wherein the weldable material is a sheet.5. The method according to claim 1 , wherein the step of welding is by a parallel gap welder.6. The method according to claim 1 , wherein the weldable materials is a wire claim 1 , the step of welding is by a parallel gap welder and the parallel gap welder pushes the wire into the through hole.7. ...

CHIP PACKAGE WITH REDISTRIBUTION LAYERS

A chip package is provided. The chip package includes a semiconductor substrate having an edge and a protective layer surrounding the semiconductor substrate. The chip package also includes a conductive line over the protective layer and the semiconductor substrate. The conductive line has a first portion and a second portion in direct contact with the first portion, and the second section at least partially covers the edge. In a top view of the conductive layer, line widths of the first portion and the second portion are different from each other 1. A chip package , comprising:a semiconductor substrate having an edge;a protective layer surrounding the semiconductor substrate; anda conductive line over the protective layer and the semiconductor substrate, wherein the conductive line has a first portion and a second portion in direct contact with the first portion, the second section at least partially covers the edge, and in a top view of the conductive layer, line widths of the first portion and the second portion are different from each other.2. The chip package as claimed in claim 1 , wherein in the top view of the conductive layer claim 1 , the first portion has a first line width claim 1 , the second portion has a second line width claim 1 , and the second line width is greater than the first line width.3. The chip package as claimed in claim 1 , wherein:at least a part of the edge extends along a first elongation direction observed from a top view of the semiconductor substrate and the protective layer,the second portion extends along a second elongation direction observed from the top view of the conductive layer, andthe first elongation direction is perpendicular to the second elongation direction.4. The chip package as claimed in claim 1 , wherein:at least a part of the edge extends along a first elongation direction observed from a top view of the semiconductor substrate and the protective layer,the second portion extends along a second elongation ...

Semiconductor package structures, semiconductor device packages and methods of manufacturing the same

A semiconductor package structure includes a first substrate, a second substrate, a first redistribution layer, and a first reconnection layer. The first substrate may have a first surface. The second substrate can be spaced apart from the first substrate with a gap and may have a second surface. The first redistribution layer can be disposed between the first redistribution layer and the gap. The first substrate can be electrically connected to the second substrate via the first reconnection layer.

Mechanisms for Forming Hybrid Bonding Structures with Elongated Bumps

Embodiments of mechanisms for forming a package structure are provided. The package structure includes a semiconductor die and a substrate. The package structure includes a pillar bump and an elongated solder bump bonded to the semiconductor die and the substrate. A height of the elongated solder bump is substantially equal to a height of the pillar bump. The elongated solder bump has a first width, at a first horizontal plane passing through an upper end of a sidewall surface of the elongated solder bump, and a second width, at a second horizontal plane passing through a midpoint of the sidewall surface. A ratio of the second width to the first width is in a range from about 0.5 to about 1.1. 1. A package structure , comprising:a first substrate;a second substrate;a pillar bump bonded to the first substrate and the second substrate, the pillar bump being electrically coupled to the first substrate and the second substrate, wherein the pillar bump comprises a pillar and a bonding layer, the pillar is a non-solder material having a higher reflow temperature than the bonding layer, the bonding layer is between the pillar and the second substrate, and the pillar includes a linear sidewall profile; andan elongated solder bump bonded to the first substrate and the second substrate, wherein a height of the elongated solder bump is substantially equal to a height of the pillar bump, wherein the elongated solder bump and the bonding layer are formed of a solder.2. The package structure of claim 1 , wherein the first substrate comprises a semiconductor die.3. The package structure of claim 2 , wherein the bonding layer is interposed between the pillar and the second substrate.4. The package structure of claim 1 , wherein the elongated solder bump has convex sidewalls.5. The package structure of claim 1 , wherein the elongated solder bump has a solder portion having a first width at a first horizontal plane passing through an upper end of a sidewall surface of the elongated ...

REACTIVE BONDING OF A FLIP CHIP PACKAGE

An array of bonding pads including a set of reactive materials is provided on a first substrate. The set of reactive materials is selected to be capable of ignition by magnetic heating induced by time-dependent magnetic field. The magnetic heating can be eddy current heating, hysteresis heating, and/or heating by magnetic relaxation processes. An array of solder balls on a second substrate is brought to contact with the array of bonding pads. A reaction is initiated in the set of magnetic materials by an applied magnetic field. Rapid release of heat during a resulting reaction of the set of reactive materials to form a reacted material melts the solder balls and provides boding between the first substrate and the second substrate. Since the magnetic heating can be localized, the heating and warpage of the substrate can be minimized during the bonding process. 1. A structure for bonding substrates comprising a substrate having an array of bonding pads thereupon , wherein each of said bonding pads comprises at least one unit reactive-material-including stack that includes a set of reactive materials including a first material and a second material that , upon ignition , react spontaneously to form an alloy or a composite of said first material and said second material , wherein a magnetic material is present within each of said bonding pads as said first material , said second material , or an additional metal.2. The structure of claim 1 , further comprising another substrate bonded to an array of solder balls and overlying or underlying said substrate claim 1 , wherein said array of solder balls is oriented in a direction that faces said array of bonding pads.3. The structure of claim 2 , wherein said array of solder balls contacts said array of bonding pads.4. The structure of claim 2 , further comprising an apparatus for generating a time-varying magnetic field claim 2 , said apparatus oriented such that a magnetic field is applied to said array of bonding pads ...

WAFER LEVEL INTEGRATION INCLUDING DESIGN/CO-DESIGN, STRUCTURE PROCESS, EQUIPMENT STRESS MANAGEMENT AND THERMAL MANAGEMENT

A method of manufacturing a multi-layer wafer is provided. The method comprises creating under bump metallization (UMB) pads on each of the two heterogeneous wafers; applying a conductive means above the UMB pads on at least one of the two heterogeneous wafers; and low temperature bonding the two heterogeneous wafers to adhere the UMB pads together via the conductive means. At least one stress compensating polymer layer may be applied to at least one of two heterogeneous wafers. The multi-layer wafer comprises two heterogeneous wafers, each of the heterogeneous wafer having UMB pads and at least one of the heterogeneous wafers having a stress compensating polymer layer and a conductive means applied above the UMB pads on at least one of the two heterogeneous wafers. The two heterogeneous wafers low temperature bonded together to adhere the UMB pads together via the conductive means. 1. A method of manufacturing a multi-layer wafer comprising:creating under bump metallization pads on each of the two heterogeneous wafers;applying a conductive means above the under bump metallization pads on at least one of the two heterogeneous wafers; andlow temperature bonding the two heterogeneous wafers to adhere the under bump metallization pads together via the conductive means to form a multi-layer wafer pair.2. The method of claim 1 , further comprising:applying at least one stress compensating polymer and/or adhesive layer to at least one of two heterogeneous wafers3. The method of claim 1 , wherein each of the two heterogeneous wafers are formed from at least one of: complementary metal-oxide semiconductor (CMOS) and GaN on Si claim 1 , CMOS and glass claim 1 , CMOS and sapphire claim 1 , CMOS and SiC on Si claim 1 , CMOS and diamond on Si claim 1 , or CMOS and sapphire on Si.4. The method of claim 1 , wherein the stress compensating polymer layer is formed on the at least one heterogeneous wafer by:applying a liquid polymer to the at least one of the two heterogeneous ...

SEMICONDUCTOR DEVICE

Airtightness of a hollow portion is maintained, and yield and durability are improved. A semiconductor device includes a device substrate a semiconductor circuit a sealing frame a cap substrate via portions electrodes and and a bump portion or the like. A hollow portion in which the semiconductor circuit is housed in an airtight state is provided between the device substrate and the cap substrate The bump portion connects all the via portions and the cap substrate Thus, the via portions can be reinforced using the bump portion A. 1. A semiconductor device comprising:a device substrate having a front surface and a back surface;a semiconductor circuit provided on the front surface of the device substrate;a sealing frame bonded to the front surface of the device substrate and surrounding the semiconductor circuit;a cap substrate including a substrate having a front surface and a back surface, wherein the front surface of the substrate is bonded to the whole perimeter of the sealing frame while covering the semiconductor circuit to form a hollow part provided between the device substrate and the cap substrate and housing the semiconductor circuit in an airtight state;a plurality of via portions formed of a conductive material for connecting the semiconductor circuit to outside parts, and penetrating the device substrate, and connected to the semiconductor circuit; anda plurality of bump portions respectively provided at all positions of the via portions in the hollow part and connecting the via portions to the cap substrate.2. The semiconductor device according to claim 1 , wherein at least part of the bump portions is formed of a conductive material claim 1 , anda conductive film is provided on the front surface of the cap substrate and covers the front surface of the cap substrate while being insulated from some of the part of the bump portions not grounded via the via portions.3. The semiconductor device according to claim 1 , wherein at least part of the bump ...

Copper pillar bump having annular protrusion

A copper pillar bump for an electrode pad of a semiconductor chip includes a first copper layer, a first metal layer formed directly on the first copper layer, a second copper layer formed directly on the first metal layer, and a second metal layer formed directly on the second copper layer, wherein the first metal layer and the second metal layer are made of a metal having a different etching rate than copper, wherein an outer perimeter ring of the first metal layer protrudes beyond a lateral surface of the first copper layer, and wherein an outer perimeter ring of the second metal layer protrudes beyond a lateral surface of the second copper layer.

MULTIPLE PLATED VIA ARRAYS OF DIFFERENT WIRE HEIGHTS ON SAME SUBSTRATE

Apparatus(es) and method(s) relate generally to via arrays on a substrate. In one such apparatus, the substrate has a conductive layer. First plated conductors are in a first region extending from a surface of the conductive layer. Second plated conductors are in a second region extending from the surface of the conductive layer. The first plated conductors and the second plated conductors are external to the first substrate. The first region is disposed at least partially within the second region. The first plated conductors are of a first height. The second plated conductors are of a second height greater than the first height. A second substrate is coupled to first ends of the first plated conductors. The second substrate has at least one electronic component coupled thereto. A die is coupled to second ends of the second plated conductors. The die is located over the at least one electronic component. 1. An apparatus , comprising:a first substrate having a conductive layer;first plated conductors in a first region extending from a surface of the conductive layer;second plated conductors in a second region extending from the surface of the conductive layer;wherein the first plated conductors and the second plated conductors are external to the first substrate;wherein the first region is disposed at least partially within the second region;wherein the first plated conductors are of a first height;wherein the second plated conductors are of a second height greater than the first height;a second substrate coupled to first ends of the first plated conductors;the second substrate having at least one electronic component coupled thereto;a die coupled to second ends of the second plated conductors; andthe die located over the at least one electronic component.2. The apparatus according to claim 1 , wherein the at least one electronic component includes a discrete passive component.3. The apparatus according to claim 2 , wherein the second substrate includes a ...

Semiconductor device package and method of manufacturing the same

A semiconductor packaging device includes a first patterned insulation layer, a patterned conductive layer, a semiconductor device and an encapsulant. The first patterned insulation layer has a first surface, a second surface opposite the first surface, and an island portion having the first surface. The first patterned insulation layer defines a tapered groove surrounding the island portion. The patterned conductive layer is disposed on the first surface of the island portion. The semiconductor device electrically connects to the patterned conductive layer. The encapsulant encapsulates the semiconductor device, the first patterned insulation layer and the patterned conductive layer.

Packaging Methods for Semiconductor Devices

Packaging methods for semiconductor devices are disclosed. A method of packaging a semiconductor device includes providing a workpiece including a plurality of packaging substrates. A portion of the workpiece is removed between the plurality of packaging substrates. A die is attached to each of the plurality of packaging substrates. 1. A method comprising:forming a first packaging substrate and a second packaging substrate in a workpiece, wherein a separation region is interposed between the first packaging substrate and the second packaging substrate;removing a top portion of the separation region to form a top trench in the workpiece;removing a bottom portion of the separation region to form a bottom trench in the workpiece, wherein the top trench and the bottom trench are vertically aligned, and wherein at least a portion of the separation region is interposed between a bottom of the top trench and a bottom of the bottom trench; andbonding a die to each of the first packaging substrate and the second packaging substrate.2. The method of claim 1 , wherein the top trench extends into the workpiece to a first depth claim 1 , and wherein the first depth is less than about 100 μm.3. The method of claim 2 , wherein the top trench has a width greater than about 20 μm.4. The method of claim 1 , wherein removing the top portion of the separation region comprises performing an etch process on the separation region.5. The method of claim 1 , wherein the top portion of the separation region is removed by a laser or a die saw.6. The method of claim 1 , further comprising forming a molding compound over the workpiece claim 1 , wherein the molding compound fills the top trench.7. The method of claim 1 , further comprising performing a singulation process on the workpiece at the separation region.8. A method comprising:forming a first packaging substrate and a second packaging substrate in a workpiece, wherein a separation region is interposed between the first packaging ...

SENSOR SYSTEMS AND METHODS FOR PROVIDING SENSOR SYSTEMS

A sensor assembly includes a die substrate and a metalized layer formed on the die substrate. The metalized layer is formed of a first metal material and includes a bonding pad to facilitate electrically coupling the sensor assembly to a sensor system. A re-metalized bump is formed on the bonding pad of a second metal material and is electrically coupled to the metalized layer. An adhesive is applied to the re-metalized bump and facilitates mechanically coupling the sensor assembly to the sensor system. 1. A sensor assembly comprising:a die substrate;a metalized layer formed on said die substrate, said metalized layer formed of a first metal material and comprising a bonding pad to facilitate electrically coupling said sensor assembly to a sensor system;a re-metalized bump formed on said bonding pad, said re-metalized bump formed of a second metal material and electrically coupled to said metalized layer; andan adhesive applied to said re-metalized bump, wherein said adhesive facilitates mechanically coupling said sensor assembly to the sensor system.2. The sensor assembly of claim 1 , wherein said adhesive comprises at least one of a non-conductive adhesive and an anisotropic conductive adhesive layer claim 1 , said adhesive formed of at least one of a film claim 1 , a liquid claim 1 , and a paste.3. The sensor assembly of claim 1 , wherein said adhesive comprises a conductive adhesive.4. The sensor assembly of further comprising a lid coupled to said die substrate claim 1 , said lid substantially covering said die substrate and exposing said bonding pad.5. The sensor assembly of claim 1 , wherein said metalized layer comprises an oxidized surface layer covering the first metal material claim 1 , and wherein said re-metalized bump extends from the first metal material through the oxidized surface layer.6. The sensor assembly of claim 1 , wherein the first metal material is aluminum claim 1 , and wherein the second metal material is at least one of aluminum claim 1 ...

Semiconductor package structure and semiconductor process

The disclosure relates to a semiconductor bonding structure and process and a semiconductor chip. The semiconductor bonding structure includes a first pillar, a first interface, an intermediate area, a second interface and a second pillar in sequence. The first pillar, the second pillar and the intermediate area include a first metal. The first interface and the second interface include the first metal and an oxide of a second metal. The content percentage of the first metal in the first interface and the second interface is less than that of the first metal in the intermediate area.

SEMICONDUCTOR CHIP WITH REDUCED PITCH CONDUCTIVE PILLARS

Various semiconductor chips and packages are disclosed. In one aspect, an apparatus is provided that includes a semiconductor chip that has a side, and plural conductive pillars on the side. Each of the conductive pillars includes a pillar portion that has an exposed shoulder facing away from the semiconductor chip. The shoulder provides a wetting surface to attract melted solder. The pillar portion has a first lateral dimension at the shoulder. A solder cap is positioned on the pillar portion. The solder cap has a second lateral dimension smaller than the first lateral dimension. 1. An apparatus , comprising: a semiconductor chip having a side; plural conductive pillars on the side , each of the conductive pillars including a pillar portion having an exposed shoulder facing away from the semiconductor chip , the shoulder providing a wetting surface to attract melted solder , the pillar portion having a first lateral dimension at the shoulder; and a solder cap positioned on the pillar portion , the solder cap having a second lateral dimension smaller than the first lateral dimension.2. The apparatus of claim 1 , wherein the pillar portion includes a pillar base portion and a pillar barrier layer positioned on the pillar base portion claim 1 , the solder cap being positioned on the pillar barrier layer.3. The apparatus of claim 2 , comprising an underbump metallization (UBM) seed layer positioned beneath the pillar base portion.4. The apparatus of claim 2 , wherein the pillar base portion has the exposed shoulder.5. The apparatus of claim 1 , wherein the pillar portion comprises a pillar base portion and pillar pedestal portion projecting away from the pillar base portion claim 1 , the pillar base portion having the exposed shoulder.6. The apparatus of claim 5 , wherein the pillar portion and the pillar pedestal comprise the same material.7. The apparatus of claim 1 , comprising a circuit board claim 1 , the semiconductor being mounted on the circuit board.8. An ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A method of manufacturing a semiconductor device includes providing a carrier, disposing a first pad on the carrier, forming a post on the first pad, and disposing a joint adjacent to the post and the first pad to form a first entire contact interface between the first pad and the joint and a second entire contact interface between the first pad and the post. The first entire contact interface and the second entire contact interface are flat surfaces. 1. A method of manufacturing a semiconductor device , comprising:providing a first carrier;disposing a first pad on the first carrier;forming a post on the first pad; anddisposing a joint adjacent to the post and the first pad to form a first entire contact interface between the first pad and the joint and a second entire contact interface between the first pad and the post, wherein the first entire contact interface and the second entire contact\ interface are flat surfaces.2. The method of manufacturing the semiconductor device of claim 1 , wherein the disposing of the joint is performed by pasting a solder over the post and the first pad through a stencil.3. The method of manufacturing the semiconductor device of claim 1 , further comprising providing a second carrier and disposing a second pad on the second carrier.4. The method of manufacturing the semiconductor device of claim 3 , wherein a height of the post is greater than or equal to ⅓ of a distance between the first pad and the second pad.5. The method of manufacturing the semiconductor device of claim 3 , further comprising disposing the joint between the first pad and the second pad to bond the first pad with the second pad and to form a third entire contact interface between the joint and the second pad claim 3 , wherein the third entire contact interface is a flat surface.6. The method of manufacturing the semiconductor device of claim 5 , further comprising disposing a pre-soldering bump on the second pad prior to disposing the joint between the first ...

PACKAGING ASSEMBLY AND METHOD OF MAKING THE SAME

A packaging assembly includes a semiconductor device. The semiconductor device includes a conductive pad having a first width, and an under-bump metallization (UBM) layer on the conductive pad, wherein the UBM layer has a second width greater than the first width. The semiconductor device further includes a conductive pillar on the UBM layer, and a cap layer over the conductive pillar, wherein the cap layer exposes sidewalls of the UBM layer. The packaging assembly further includes a substrate. The substrate includes a conductive region, and a mask layer overlying the substrate and exposing a portion of the conductive region. The packaging assembly further includes a joint solder structure between the conductive pillar and the conductive region. 1. A packaging assembly , comprising: a conductive pad having a first width,', 'an under-bump metallization (UBM) layer on the conductive pad, wherein the UBM layer has a second width greater than the first width,', 'a conductive pillar on the UBM layer, and', 'a cap layer over the conductive pillar, wherein the cap layer exposes sidewalls of the UBM layer;, 'a semiconductor device comprising a conductive region, and', 'a mask layer overlying the substrate and exposing a portion of the conductive region; and, 'a substrate comprisinga joint solder structure between the conductive pillar and the conductive region.2. The packaging assembly of claim 1 , wherein the mask layer has a mask opening exposing a portion of the conductive region claim 1 , and the width of the mask opening is smaller than and the second width.3. The packaging assembly of claim 2 , wherein a ratio between the width of the mask opening and the second width ranges from about 0.7 and about 0.8.4. The packaging assembly of claim 1 , wherein the conductive pillar comprises a copper pillar claim 1 , and the conductive region is a copper trace.5. The packaging assembly of claim 1 , wherein the mask layer is a solder resist layer.6. A packaging assembly claim 1 , ...

Display device including a reinforcing member

A display device includes a flexible base layer including a first portion and a second portion. A display unit is disposed on a first surface of the first portion. The display unit includes a light emitting element. A driving circuit is disposed on a first surface of the second portion. The driving circuit includes a driving chip. A first support member is disposed on a second surface of the first portion opposite the first surface. A second support member is disposed on a second surface of the second portion. The second support member includes a first opening overlapping the driving circuit. The second surface of the second portion is on an opposite side of the second portion from the first surface of the second portion. A first reinforcing member is disposed in the first opening. The first reinforcing member includes a different material from the second support member.

Stack type semiconductor package

A stack type semiconductor package includes a lower semiconductor package including a lower package substrate and at least one lower semiconductor chip disposed on the lower package substrate; an upper semiconductor package including an upper package substrate larger than the lower package substrate and at least one upper semiconductor chip disposed on the upper package substrate; an inter-package connector connecting an upper surface of the lower package substrate to a lower surface of the upper package substrate; and a filler filling in between the lower package substrate and the upper package substrate while substantially surrounding the inter-package connector.

Wafer level integration including design/co-design, structure process, equipment stress management and thermal management

A method of manufacturing a multi-layer wafer is provided. The method comprises applying at least one stress compensating polymer layer to at least one of two heterogeneous wafers and low temperature bonding the two heterogeneous wafers to bond the stress compensating polymer layer to the other of the two heterogeneous wafers to form a multi-layer wafer pair. The multi-layer wafer comprises two heterogeneous wafers, at least one of the heterogeneous wafers having a stress compensating polymer layer. The two heterogeneous wafers are low temperature bonded together to bond the stress compensating polymer layer to the other of the two heterogeneous wafers.

SEMICONDUCTOR PACKAGE

A semiconductor package includes a first semiconductor chip having a first chip substrate, the first chip substrate having a first upper surface and a first lower surface opposite to each other, a first through-silicon via (TSV), a lower connection pad and a first lower passivation layer on the first lower surface of the first chip substrate, the first lower passivation layer exposing a portion of the lower connection pad, an upper connection pad and a first upper passivation layer on the first upper surface of the first chip substrate, the first upper passivation layer including a first upper inorganic material layer, and a second semiconductor chip connected to the first semiconductor chip, the second semiconductor chip including a second TSV, wherein the first lower passivation layer has a stacked structure of a first lower inorganic material layer and a lower organic material layer. 1. A semiconductor package , comprising: a first chip substrate, the first chip substrate having a first upper surface and a first lower surface opposite to each other,', 'a first through-silicon via (TSV),', 'a lower connection pad and a first lower passivation layer on the first lower surface of the first chip substrate, the first lower passivation layer exposing a portion of the lower connection pad,', 'an upper connection pad and a first upper passivation layer on the first upper surface of the first chip substrate, the first upper passivation layer including a first upper inorganic material layer; and, 'a first semiconductor chip includinga second semiconductor chip connected to the first semiconductor chip, the second semiconductor chip including a second TSV,wherein the first lower passivation layer has a stacked structure of a first lower inorganic material layer and a lower organic material layer.2. The semiconductor package as claimed in claim 1 , wherein the first lower inorganic material layer is on the first lower surface of the first chip substrate claim 1 , and the ...

Assembly Method, of the Flip-Chip Type, for Connecting Two Electronic Components, Assembly Obtained by the Method

The invention relates to an assembly method for connecting two electronic components together, said components each having an assembly face, wherein the two assembly faces are moved together in what is known as an assembly direction X, and a given force F is applied to one and/or the other of the components, one and/or the other assembly face(s) having: —connection inserts made of rigid material having an elongate longitudinal shape in the assembly direction X; —connection tracks made of material having a hardness less than that of the inserts and having an elongate longitudinal shape transversely to the assembly direction X, wherein, in said method: —the inserts are aligned opposite corresponding tracks such that the inserts and the tracks form in pairs, after assembly, at least one approximately transverse intersection, —the force F is applied so as make the inserts penetrate into the tracks until the assembly is produced.

SEMICONDUCTOR PACKAGE

A semiconductor package includes a substrate, a first semiconductor chip and a second semiconductor chip adjacent to each other on the substrate, and a plurality of bumps on lower surfaces of the first and second semiconductor chips. The first and second semiconductor chips have facing first side surfaces and second side surfaces opposite to the first side surfaces. The bumps are arranged at a higher density in first regions adjacent to the first side surfaces than in second regions adjacent to the second side surfaces. 120.-. (canceled)21. A semiconductor package , comprising:a substrate;at least two semiconductor chips on the substrate;a plurality of bumps on lower surfaces of respective ones of the at least two semiconductor chips, the plurality of bumps being arranged at a higher density in adjacent regions of the at least two semiconductor chips than in other regions of the at least two semiconductor chips; andat least one insulating layer between the substrate and each of the at least two semiconductor chips to fill between the plurality of bumps, the at least one insulating layer having a volume in a region between the at least two semiconductor chips that is smaller than a volume in a region outside non-adjacent side surfaces of the at least two semiconductor chips.22. The semiconductor package as claimed in claim 21 , wherein the at least one insulating layer protrudes outward from the non-adjacent side surfaces of the at least two semiconductor chips farther than from adjacent side surfaces of the at least two semiconductor chips.23. The semiconductor package as claimed in claim 22 , wherein the at least one insulating layer protrudes from other side surfaces of the at least two semiconductor chips connecting respective ones of the adjacent side surfaces and the non-adjacent side surfaces claim 22 , anda protrusion distance from the other side surfaces of the at least two semiconductor chips is greater than a protursion distance from the adjacent side ...

SEMICONDUCTOR PACKAGE

A semiconductor package includes a semiconductor chip that includes a first region and a second region spaced apart from the first region; a plurality of connection bumps disposed under the first region of the semiconductor chip; and a protection layer that covers a bottom surface of the semiconductor chip in the second region, wherein the protection layer does not cover the bottom surface of the semiconductor chip in the first region and is not disposed between the plurality of connection bumps. The semiconductor chip of the semiconductor package is protected by the protection layer. 1. A semiconductor package comprising:a semiconductor chip comprising a first region and a second region spaced apart from the first region;a plurality of connection bumps disposed under the first region of the semiconductor chip; anda protection layer that covers a bottom surface of the semiconductor chip in the second region,wherein the protection layer does not cover the bottom surface of the semiconductor chip in the first region and is not disposed between the plurality of connection bumps.2. The semiconductor package of claim 1 , wherein the semiconductor chip further comprises a third region between the first region and the second region claim 1 , none of the plurality of connection bumps are disposed under the third region of the semiconductor chip claim 1 , and the protection layer does not to cover the third region of the semiconductor chip.3. The semiconductor package of claim 2 , wherein the third region of the semiconductor chip surrounds the first region of the semiconductor chip claim 2 , and the second region of the semiconductor chip surrounds the third region of the semiconductor chip.4. The semiconductor package of claim 1 , wherein the first region of the semiconductor chip is positioned at a center portion of the semiconductor chip and the second region of the semiconductor chip is positioned at an edge portion of the semiconductor chip.5. A semiconductor package ...

Light emitting device package

A light emitting device package according to an embodiment may include a first package body including first and second openings passing through the upper surface and lower surface thereof; a second package body disposed on the first package body and including a third opening passing through the upper surface and lower surface thereof; a light emitting device disposed in the third opening; a first resin disposed between the upper surface of the first package body and the light emitting device; and a second resin disposed in the third opening. According to the embodiment, the upper surface of the first package body may be coupled to the lower surface of the second package body, the first package body may include a recess recessed from the upper surface of the first package body to the lower surface of the first package body, the first resin may be disposed in the recess, the first resin and the second resin include materials different from each other, and the first resin may be in contact with the light emitting device and the second resin.

Variable temperature solders for multi-chip module packaging and repackaging

Various methods of mounting semiconductor chips on a substrate are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a first plurality of solder interconnect structures to a first semiconductor chip. The first solder interconnect structures have a first melting point. The first semiconductor chip may be tested. If the first semiconductor chip passes the testing, then a second semiconductor chip is coupled to the first semiconductor chip using a second plurality of solder interconnect structures that have a second melting point lower than the first melting point.

FILM SCHEME FOR BUMPING

A bump structure with a barrier layer, and a method for manufacturing the bump structure, are provided. In some embodiments, the bump structure comprises a conductive pad, a conductive bump, and a barrier layer. The conductive pad comprises a pad material. The conductive bump overlies the conductive pad, and comprises a lower bump layer and an upper bump layer covering the lower bump layer. The barrier layer is configured to block movement of the pad material from the conductive pad to the upper bump layer along sidewalls of the lower bump layer. In some embodiments, the barrier layer is a spacer lining the sidewalls of the lower bump layer. In other embodiments, the barrier layer is between the barrier layer and the conductive pad, and spaces the sidewalls of the lower bump layer from the conductive pad. 1. An integrated circuit comprising:a conductive pad comprising a pad material;a dielectric structure overlying the conductive pad;a metal bump that extends through the dielectric structure from the conductive pad and is devoid of copper, wherein the metal bump comprises a first metal layer and a second metal layer, that respectively comprise different metals, wherein the second metal layer overlies the first metal layer and is at a topmost surface of the metal bump, and wherein a width of the metal bump is continuous from the conductive pad to the topmost surface; anda conductive spacer having a pair of spacer segments, wherein the metal bump is between and directly contacts the spacer segments, and wherein the conductive spacer is configured to block movement of the pad material from the conductive pad to the second metal layer.2. The integrated circuit according to claim 1 , wherein a top of the dielectric structure has a recess within which the metal bump is arranged claim 1 , and wherein the metal bump extends through a recessed surface of the dielectric structure that is in the recess and that is recessed relative to a top surface of the dielectric structure. ...

Selective wetting process to increase solder joint standoff

One embodiment of the invention sets forth a packaging system, which includes a first package substrate, an electrically conductive pad formed on a surface of the first package substrate, and a supporting structure formed on the electrically conductive pad. The supporting structure has a top surface and a side surface, and only the top surface of the supporting structure is coupled to a solder joint to establish an electrical connection between the first package substrate and an adjacent, parallel second package substrate. By having the solder joint connected only to the top surface of the supporting structure, the resulting solder joint structure is narrower and taller. Therefore, even if solder joints are placed at a finer pitch, a standoff height between the first and second package substrates can be maintained at a desired height to accommodate a fixed-size IC chip that is disposed between the first and second package substrates.

Cold-welded flip chip interconnect structure

In an embodiment, a quantum device includes a first set of protrusions formed on a substrate and a second set of protrusions formed on a qubit chip. In the embodiment, the quantum device includes a set of bumps formed on an interposer, the set of bumps formed of a material having above a threshold ductility at a room temperature range, wherein a first subset of the set of bumps is configured to cold weld to the first set of protrusions and a second subset of the set of bumps is configured to cold weld to the second set of protrusions.

Semiconductor device and manufacturing method for the same

A semiconductor substrate provided with an integrated circuit is polished by CMP or the like, and the semiconductor substrate is made into a thin film by forming an embrittlement layer in the semiconductor substrate and separating a part of the semiconductor substrate; thus, semiconductor chips such as IC chips and LSI chips which are thinner than ever are obtained. Moreover, such thinned LSI chips are stacked and electrically connected through wirings penetrating through the semiconductor substrate; thus, a three dimensional semiconductor integrated circuit with improved packing density is obtained.

Three-Dimensional Chip Stack and Method of Forming the Same

A three-dimensional chip stack includes a first chip bonded to a second chip to form an electrical interconnection therebetween. The bonded interconnection includes a first conductive pillar overlying a first substrate of the first chip, a second conductive pillar overlying a second substrate of the second chip, and a joint structure between the first conductive pillar and the second conductive pillar. The joint structure includes a first IMC region adjacent to the first conductive pillar, a second IMC region adjacent to the second conductive pillar, and a metallization layer between the first IMC region and the second IMC region.

Semiconductor chip and semiconductor package including the same

A semiconductor package may include a package substrate, a first semiconductor chip on the package substrate, and a second semiconductor chip on the first semiconductor chip. The first semiconductor chip comprises a chip substrate including a first surface and a second surface opposite to the first surface, a plurality of first chip pads between the package substrate and the chip substrate, and electrically connecting the first semiconductor chip to the package substrate, a plurality of second chip pads disposed on the second surface and between the second semiconductor chip and the second surface, and a plurality of redistribution lines on the second surface, the redistribution lines electrically connecting to the second semiconductor chip, and a plurality of bonding wires electrically connecting the redistribution lines to the package substrate.

Multiple bond via arrays of different wire heights on a same substrate

Apparatuses relating generally to a substrate are disclosed. In such an apparatus, first wire bond wires (“first wires”) extend from a surface of the substrate. Second wire bond wires (“second wires”) extend from the surface of the substrate. The first wires and the second wires are external to the substrate. The first wires are disposed at least partially within the second wires. The first wires are of a first height. The second wires are of a second height greater than the first height for coupling of at least one electronic component to the first wires at least partially disposed within the second wires.

ELECTROCHEMICAL DEPOSITION METHOD

The present invention is to provide a substrate holder which can effect a more complete sealing with a sealing member and makes it possible to take a substrate out of the substrate holder easily and securely, and also a plating apparatus provided with the substrate holder. The substrate holder includes: a fixed holding member and a movable holding member for holding a substrate therebetween; a sealing member mounted to the fixed holding member or the movable holding member; and a suction pad for attracting a back surface of the substrate held between the fixed holding member and the movable holding member. 1. A substrate holder for holding a substrate having a surface to be electroplated , said substrate holder comprising:a fixed holding member and a movable holding member for holding the substrate therebetween, the movable holding member having a sealing member; andat least one pair of conductors for detecting a liquid leak, the at least one pair of conductors extending along an entire circumference of the sealing member and being located inside the sealing member when the substrate is held between the movable holding member and the fixed holding member, the at least one pair of conductors being configured to short-circuit via a leaked plating solution when a plating solution leaks to aback side of the substrate held between the movable holding member and the fixed holding member.2. An electroplating apparatus comprising:{'claim-ref': {'@idref': 'CLM-00001', 'claim 1'}, 'a substrate holder according to .'} The present invention relates to a substrate holder for use in a plating apparatus for plating a to-be-plated surface of a substrate, especially a plating apparatus for forming a plated film in fine interconnect trenches or holes, or resist openings provided in a surface of a semiconductor wafer, or for forming bumps (protruding electrodes), which are to be electrically connected to electrodes, or the like, of a package, on a surface of a semiconductor wafer, and ...

Lead-Free Solder Ball

Provided is a process for mounting a BGA (Ball Grid Array) or CSP (Chip Size Package) on a printed circuit board. The process includes melting and fusing together solder paste and a solder ball. The solder ball has a solder composition that includes 0.5-1.1 mass % of Ag, 0.7-0.8 mass % of Cu, 0.05-0.08 mass % of Ni, and a remainder of Sn. In the process, the solder ball is placed on an electrode of the BGA or CSP substrate and the solder paste is applied onto an opposing electrode of the printed circuit board. 1. A process for mounting a BGA or CSP on a printed circuit board , the process comprising:melting and fusing together solder paste and a solder ball which has a solder composition comprising 0.5-1.1 mass % of Ag, 0.7-0.8 mass % of Cu, 0.05-0.08 mass % of Ni, and a remainder of Sn,wherein the solder ball is placed on an electrode of the BGA or CSP substrate and the solder paste is applied onto an opposing electrode of the printed circuit board.2. The process according to claim 1 , wherein the solder composition comprises 0.9-1.1 mass % of Ag claim 1 , 0.7-0.8 mass % of Cu claim 1 , 0.05-0.08 mass % of Ni claim 1 , and a remainder of Sn.3. The process according to claim 1 , wherein the solder composition comprises 1.0 mass % of Ag claim 1 , 0.75 mass % of Cu claim 1 , 0.07 mass % of Ni claim 1 , and a remainder of Sn.4. The process according to claim 1 , wherein the solder composition further comprises at least one element selected from Fe claim 1 , Co claim 1 , and Pt in a total amount of 0.003-0.1 mass %.6. The process according to claim 1 , wherein the solder composition further comprises at least one element selected from Bi claim 1 , In claim 1 , Sb claim 1 , P claim 1 , and Ge in a total amount of 0.003-0.1 mass %.7. The process according to claim 1 , wherein the solder ball has a diameter of at least 0.1 mm.8. The process according to claim 1 , wherein the solder ball has a diameter of at least 0.3 mm.9. The process according to claim 1 , wherein the ...

Conductive particle, and connection material, connection structure, and connecting method of circuit member

There is provided a conductive particle including a core particle containing a resin material, and a surface layer that covers a surface of the core particle and contains a solder material, in which a melting point of the solder material is equal to or lower than a softening point of the resin material.

Additively Manufactured Flexible Interposer

A semiconductor device assembly and method of providing a semiconductor device assembly. The method includes providing a flexible interposer, providing a first redistribution layer on the flexible interposer, and providing a second redistribution layer on a portion of the first redistribution layer. The second redistribution layer is provided by additive manufacturing. The first redistribution layer may be deposited in a clean room environment. The first redistribution layer may be deposited via chemical deposition or physical deposition. A semiconductor device is attached to the first redistribution layer. The flexible interposer may be attached to a board with the semiconductor device being electrically connected to the board via the first redistribution layer, the flexible interposer, and the second redistribution layer. The flexible interposer may be attached to a flexible hybrid electronic (FHE) board. The flexible nature of the flexible interposer and/or the FHE board may redistribute stress on the semiconductor device assembly.

Flip-chip assembly process comprising pre-coating interconnect elements

A method of assembling a first and a second electronic components includes forming connection elements on an assembly surface of the first component and forming connection elements on an assembly surface of the second component. The method also includes depositing a liquid layer of electrically-insulating curable material on the assembly surface of the first and/or of the second component and arranging the first and second components on each other to place the connection elements of the second component in front of the connection elements of the first component. The method further includes applying a force along a predetermined direction and the first and/or the second components to create electric interconnects each formed of a connection element of the first component and of a connection element of the second component and curing the curable material.

SEMICONDUCTOR PACKAGE INCLUDING BUMP

A semiconductor device includes a semiconductor chip having a pad which is exposed through a passivation layer, a bump pillar formed over the passivation layer adjacent to the pad, but not overlapping with the pad. The semiconductor chip also has a solder layer including a solder bump portion which is formed over the bump pillar and a solder fillet portion which is formed at one side of the bump pillar facing the pad to cover the pad and electrically couples the bump pillar and the pad. 1. A semiconductor device comprising:a semiconductor chip having a pad which is exposed through a passivation layer;a bump pillar formed over the passivation layer adjacent to the pad, but not overlapping with the pad; anda solder layer including a solder bump portion which is formed over the bump pillar and a solder fillet portion which is formed at one side of the bump pillar facing the pad to cover the pad and electrically couples the bump pillar and the pad.2. The semiconductor device according to claim 1 , further comprising:a seed layer interposed between the passivation layer and the bump pillar and between the pad and the solder fillet portion.3. The semiconductor device according to claim 2 , further comprising:a barrier layer interposed between the passivation layer and the seed layer and between the pad and the seed layer.4. The semiconductor device according to claim 1 , further comprising:a seed layer interposed between the passivation layer and the bump pillar.5. The semiconductor device according to claim 4 , further comprising:a barrier layer interposed between the seed layer and the passivation layer.6. The semiconductor device according to claim 4 , wherein the seed layer comprises the same material as the bump pillar.7. The semiconductor device according to claim 6 , wherein the seed layer and the bump pillar comprise at least any one among copper claim 6 , nickel claim 6 , gold claim 6 , silver claim 6 , platinum and alloys thereof.8. The semiconductor device ...

SEMICONDUCTOR CHIP WITH REDUCED PITCH CONDUCTIVE PILLARS

Various semiconductor chips and packages are disclosed. In one aspect, an apparatus is provided that includes a semiconductor chip that has a side, and plural conductive pillars on the side. Each of the conductive pillars includes a pillar portion that has an exposed shoulder facing away from the semiconductor chip. The shoulder provides a wetting surface to attract melted solder. The pillar portion has a first lateral dimension at the shoulder. A solder cap is positioned on the pillar portion. The solder cap has a second lateral dimension smaller than the first lateral dimension. 1. An apparatus , comprising:a semiconductor chip having a side;plural conductive pillars on the side, each of the conductive pillars including a pillar portion having an exposed shoulder facing away from the semiconductor chip, the shoulder providing a wetting surface to attract melted solder, the pillar portion having a first lateral dimension at the shoulder; anda solder cap positioned on the pillar portion, the solder cap having a second lateral dimension smaller than the first lateral dimension.2. The apparatus of claim 1 , wherein the pillar portion includes a pillar base portion and a pillar barrier layer positioned on the pillar base portion claim 1 , the solder cap being positioned on the pillar barrier layer.3. The apparatus of claim 2 , wherein the pillar barrier layer has a central portion and a ring portion separated from the central portion by a gap claim 2 , the ring portion having the exposed shoulder claim 2 , the gap providing a space to attract the melted solder.4. The apparatus of claim 2 , wherein the pillar base portion has the exposed shoulder.5. The apparatus of claim 1 , wherein the pillar portion comprises a pillar base portion and pillar pedestal portion projecting away from the pillar base portion claim 1 , the pillar base portion having the exposed shoulder.6. The apparatus of claim 5 , wherein the pillar portion and the pillar pedestal comprise the same ...

SEMICONDUCTOR CHIP STACK AND METHOD FOR MANUFACTURING SEMICONDUCTOR CHIP STACK

A semiconductor chip stack includes a first semiconductor chip, a second semiconductor chip, and a connection via which the first electrode and the second electrode are electrically connected to each other. The connection includes a first column and a second column. The first column is constituted by a material having a higher degree of activity with respect to heat than a material that constitutes the second column and is smaller in volume than the second column. Further, the connection has an aspect ratio of 0.5 or higher in a height direction. 1. A semiconductor chip stack comprising:a first semiconductor chip having a first electrode;a second semiconductor chip having a second electrode; anda connection via which the first electrode and the second electrode are electrically connected to each other,the first semiconductor chip and the second semiconductor chip being stacked,wherein the connection includes a first column and a second column that are lined up along a direction in which the first semiconductor chip and the second semiconductor chip are stacked,the first column is constituted by a material having a higher degree of activity with respect to heat than a material that constitutes the second column and is smaller in volume than the second column, andthe connection has an aspect ratio of 0.5 or higher in a height direction.2. The semiconductor chip stack according to claim 1 , wherein the connection has a cross-sectional size of 1 to 100 μm claim 1 ,the first column has a height of 5 to 5000 nm, andthe second column has a height of 0.5 to 200 μm.3. The semiconductor chip stack according to claim 1 , wherein the connection has a cross-sectional size of 1 to 20 μm claim 1 ,the first column has a height of 5 to 5000 nm, andthe second column has a height of 0.5 to 40 μm.4. The semiconductor chip stack according to claim 1 , wherein the material that constitutes the first column has a smaller crystal grain size than the material that constitutes the second ...

Structure and formation method of chip package with conductive support elements

A package structure and a formation method of a package structure are provided. The method includes placing a semiconductor die over a redistribution structure and placing a conductive feature over the redistribution structure. The conductive feature has a support element and a solder element. The solder element extends along surfaces of the support element. The method also includes stacking an interposer substrate over the redistribution structure. The interposer substrate extends across the semiconductor die. The method further includes forming a protective layer to surround the conductive feature and the semiconductor die.

Semiconductor device and method for fabricating the same

반도체 장치가 제공된다. 반도체 장치는, 대향되는 제1 면과 제2 면을 포함하는 제1 반도체 칩, 대향되는 제3 면과 제4 면을 포함하는 제2 반도체 칩으로, 상기 제3 면은 상기 제2 면과 마주보는 제2 반도체 칩, 상기 제1 면과 상기 제2 면 사이로 연장되는 제1 관통 전극 및 제2 관통 전극, 상기 제3 면과 상기 제4 면 사이로 연장되고, 상기 제1 관통 전극과 연결되는 제3 관통 전극 및 상기 제3 면과 상기 제4 면 사이로 연장되고, 상기 제2 관통 전극과 연결되는 제4 관통 전극을 포함하고, 상기 제2 면에서, 상기 제1 관통 전극의 말단은 제1 자기 극성을 갖고, 상기 제2 면에서, 상기 제2 관통 전극의 말단은 상기 제1 자기 극성과 반대인 제2 자기 극성을 갖는다. A semiconductor device is provided. The semiconductor device includes a first semiconductor chip including opposing first and second surfaces, and a second semiconductor chip including opposing third and fourth surfaces, wherein the third surface faces the second surface a second semiconductor chip, a first through electrode and a second through electrode extending between the first surface and the second surface, a second through electrode extending between the third surface and the fourth surface, and connected to the first through electrode a third through electrode and a fourth through electrode extending between the third surface and the fourth surface and connected to the second through electrode, wherein in the second surface, an end of the first through electrode has a first magnetic field polarity, and in the second surface, an end of the second through electrode has a second magnetic polarity opposite to the first magnetic polarity.

Cleaning methods and compositions

Methods and chemical solvents used for cleaning residues on metal contacts during a semiconductor device packaging process are disclosed. A chemical solvent for cleaning a residue formed on a metal contact may comprise a reactive inorganic component and a reactive organic component. The method may comprise spraying a semiconductor device with a chemical solvent at a first pressure, and spraying the semiconductor device with the chemical solvent at a second pressure less than the first pressure.

Test structure and method of testing electrical characteristics of through vias

A method and apparatus for testing the electrical characteristics, such as electrical continuity, is provided. A substrate, such as a wafer or an interposer, having a plurality of through vias (TVs) is provided. Along one side of the substrate, a conductive layer electrically couples two or more of the TVs. Thereafter, the electrical characteristics of the TVs may be test by, for example, a probe card in electrical contact with the TVs on the other side of the substrate. During testing, current passes through a first TV from a first side of the substrate, to the conductive layer on a second side of the substrate, to a second TV, and back to the first side of the substrate through the second TV.

包括贯穿基底过孔的半导体器件

公开了一种半导体器件。所述半导体器件包括：基底；第一贯穿基底过孔，被构造为至少部分地穿透基底，第一贯穿基底过孔具有第一高宽比；以及第二贯穿基底过孔，被构造为至少部分地穿透基底。第二贯穿基底过孔具有大于第一高宽比的第二高宽比，并且第一贯穿基底过孔和第二贯穿基底过孔中的每个包括第一导电层和第二导电层。第一贯穿基底过孔的第一导电层在竖直方向上的厚度小于第二贯穿基底过孔的第一导电层在竖直方向上的厚度。

발광소자 패키지

실시 예에 따른 발광소자 패키지는, 상면과 하면을 관통하는 제1 및 제2 개구부를 포함하는 제1 패키지 몸체; 제1 패키지 몸체 상에 배치되고, 상면과 하면을 관통하는 제3 개구부를 포함하는 제2 패키지 몸체; 제3 개구부 내에 배치되는 발광소자; 제1 패키지 몸체의 상면과 발광소자 사이에 배치된 제1 수지; 및 제3 개구부 내에 배치되는 제2 수지; 를 포함할 수 있다. 실시 예에 의하면, 제1 패키지 몸체의 상면은 제2 패키지 몸체의 하면과 결합되고, 제1 패키지 몸체는 제1 패키지 몸체의 상면에서 제1 패키지 몸체의 하면으로 오목한 리세스를 포함하고, 제1 수지는 리세스에 배치되고, 제1 수지와 제2 수지는 서로 다른 물질을 포함하고, 제1 수지는 발광소자 및 제2 수지와 접촉될 수 있다.

Electrical interconnection structures and methods for fabricating the same

본 발명은 전기적 연결 구조 및 그 제조방법에 관한 것으로, 본딩패드를 갖는 기판, 상기 기판 상에 배치되어 상기 본딩패드를 개방하는 보호막, 상기 본딩패드와 전기적으로 연결되는 솔더볼, 상기 본딩패드 상에 배치되어 상기 솔더볼이 채워지는 내부 영역을 제공하는 솔더볼 지지막, 그리고 상기 본딩패드와 상기 솔더볼 지지막 사이에 배치되고 상기 본딩패드를 구성하는 금속에 비해 이온화경향이 작은 금속을 포함하는 금속막을 형성하는 것을 포함할 수 있다. The present invention relates to an electrical connection structure and a method of manufacturing the same, and more particularly, to an electrical connection structure and a method of manufacturing the same, which includes a substrate having a bonding pad, a protective film disposed on the substrate to open the bonding pad, a solder ball electrically connected to the bonding pad, A solder ball supporting film for providing an inner region filled with the solder ball and a metal film disposed between the bonding pad and the solder ball supporting film and including a metal having a lower ionization tendency than a metal constituting the bonding pad .

기판 관통 비아들을 포함하는 반도체 소자 및 그 제조 방법

반도체 소자가 제공된다. 기판, 상기 기판을 적어도 부분적으로 관통하며 제1 종횡 비를 가지는 제1 기판 관통 비아(through substrate via), 및 상기 기판을 적어도 부분적으로 관통하며 상기 제1 종횡비보다 큰 제2 종횡비를 가지는 제2 기판 관통 비아를 포함하고, 상기 제1 기판 관통 비아 및 상기 제2 기판 관통 비아 각각은 제1 전도성 층 및 제2 전도성 층을 포함하고, 상기 제2 기판 관통 비아의 상기 제1 전도성 층의 평균 입자 크기는 상기 제2 기판 관통 비아의 상기 제2 전도성 층의 평균 입자 크기와 상이하고, 상기 제1 기판 관통 비아의 상기 제1 전도성 층의 수직 방향으로의 두께는 상기 제2 기판 관통 비아의 상기 제1 전도성 층의 상기 수직 방향으로의 두께보다 작을 수 있다.

Semiconductor devices having through vias and methods for fabricating the same

본 발명은 관통전극을 갖는 반도체 소자 및 그 제조방법에 관한 것으로, 상면과 그 반대면인 하면을 포함하는 기판과, 상기 기판을 관통하여 상기 기판의 하면 밖으로 돌출된 관통전극과, 상기 기판의 하면을 덮는 하부절연막과, 그리고 상기 하부절연막의 일부가 함몰되어 정의된 정렬 키를 포함한다. 상기 정렬 키의 모서리는 라운딩된 것일 수 있다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a through electrode, and a method of manufacturing the same, comprising: a substrate including a top surface and a bottom surface opposite to the top surface; And a lower insulating layer covering the portion and an alignment key defined by recessing a portion of the lower insulating layer. The corner of the alignment key may be rounded.

Bump structures in semiconductor device and packaging assembly

一种位于半导体衬底或封装组件中的凸块结构包括：形成在半导体衬底的导电焊盘上方的凸块下金属化(UBM)层。UBM层的宽度大于导电焊盘的宽度。

Packaging part, semiconductor device package and its manufacturing method is laminated in semiconductor devices

半导体器件层叠封装件(PoP)包括：第一封装件；第二封装件；中介层；第一模塑层和第二模塑层。第一封装件包括第一衬底和第一衬底上的第一半导体芯片。第二封装件布置在第一封装件上，并包括第二衬底和第二衬底上的第二半导体芯片。中介层布置在第一封装件和第二封装件之间，并连接第一封装件和第二封装件。第一模塑层填充第一封装件和中介层之间的空间。第二模塑层覆盖中介层的上表面。

Semiconductor structure and manufacturing method thereof

本发明的实施例提供了一种半导体结构，包括衬底，从衬底暴露的导电互连件，覆盖衬底和导电互连件的部分的钝化件，设置在钝化件上方并且与导电互连件的暴露部分接触的凸块下金属(UBM)焊盘，以及设置在UBM焊盘上方的导体，其中，导体包括顶面、从顶面延伸并且包括第一倾斜度的第一倾斜外表面和从第一倾斜外表面的端部延伸至UBM焊盘并且包括第二倾斜度的第二倾斜外表面，第二倾斜度基本上小于第一倾斜度。本发明的实施例还涉及半导体结构及其制造方法。

Semiconductor devices, semiconductor packages, and method of manufacturing the Semiconductor devices

반도체 장치가 개시된다. 반도체 장치는, 기판 상에 형성된 도전 성분(conductive component); 상기 기판 상에 형성되며 개구부를 구비하는 패시베이션층으로서, 상기 개구부가 상기 도전 성분의 적어도 일부분을 노출하는, 상기 패시베이션층; 및 상기 패시베이션층 상에서 상기 개구부를 채우며, 상기 도전 성분과 전기적으로 연결되는 패드 구조물을 포함한다. 상기 패드 구조물은 상기 개구부의 내벽 상에 및 상기 개구부 주위의 상기 패시베이션층 상면 상에 콘포말하게 형성되며, 순서대로 적층된 도전 배리어층, 제1 시드층, 식각 정지층 및 제2 시드층을 포함하는 하부 도전층, 상기 하부 도전층 상에 형성되며, 상기 개구부를 적어도 부분적으로 채우는 제1 패드층, 및 상기 제1 패드층 상에 형성되며, 상기 패시베이션층의 상기 상면 상에 배치되는 상기 하부 도전층의 외주 부분과 접촉하는 제2 패드층을 포함한다. A semiconductor device is disclosed. A semiconductor device includes: a conductive component formed on a substrate; a passivation layer formed on the substrate and having an opening, the opening exposing at least a portion of the conductive component; and a pad structure that fills the opening on the passivation layer and is electrically connected to the conductive component. The pad structure is conformally formed on an inner wall of the opening and on an upper surface of the passivation layer around the opening, and includes a conductive barrier layer, a first seed layer, an etch stop layer and a second seed layer stacked in order. a lower conductive layer formed on the lower conductive layer, the first pad layer at least partially filling the opening, and the lower conductive layer formed on the first pad layer and disposed on the upper surface of the passivation layer and a second pad layer in contact with a peripheral portion of the layer.

Semiconductor package

본 발명의 실시예에 따른 반도체 패키지는, 기판, 기판 상에 서로 인접하게 배치되며, 서로 마주하는 측면인 제1 면 및 제1 면에 대향하는 제2 면을 각각 갖는 제1 반도체 칩 및 제2 반도체 칩, 제1 반도체 칩 및 제2 반도체 칩의 하면에 배치되며, 제1 면에 인접한 제1 영역들에서, 제2 면에 인접한 제2 영역들에서보다 높은 밀도로 배열되는 복수의 범프들을 포함한다. A semiconductor package according to an embodiment of the present invention includes a substrate, a first semiconductor chip disposed adjacent to each other on the substrate, and a first semiconductor chip and a second surface each having a first surface that is opposite to each other and a second surface that is opposite to the first surface a plurality of bumps disposed on lower surfaces of the semiconductor chip, the first semiconductor chip, and the second semiconductor chip, the bumps being arranged at a higher density in first regions adjacent to the first surface than in second regions adjacent to the second surface; do.

Multiple bond via arrays of different wire heights on a same substrate

An apparatus relating generally to a substrate is disclosed. In such an apparatus, a first bond via array has first wires extending from a surface of the substrate. A second bond via array has second wires extending from the surface of the substrate. The first bond via array is disposed at least partially within the second bond via array. The first wires of the first bond via array are of a first height. The second wires of the second bond via array are of a second height greater than the first height for coupling of at least one die to the first bond via array at least partially disposed within the second bond via array.

Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects

An apparatus relating generally to a die stack is disclosed. In such an apparatus, a substrate is included. A first bond via array includes first wires each of a first length extending from a first surface of the substrate. An array of bump interconnects is disposed on the first surface. A die is interconnected to the substrate via the array of bump interconnects. A second bond via array includes second wires each of a second length different than the first length extending from a second surface of the die.

Multiple bond via arrays of different wire heights on a same substrate

Apparatuses relating generally to a substrate are disclosed. In such an apparatus, first wire bond wires (“first wires”) extend from a surface of the substrate. Second wire bond wires (“second wires”) extend from the surface of the substrate. The first wires and the second wires are external to the substrate. The first wires are disposed at least partially within the second wires. The first wires are of a first height. The second wires are of a second height greater than the first height for coupling of at least one electronic component to the first wires at least partially disposed within the second wires.

Conductive bump, method for producing the same, and electronic component mounted structure

본 발명은 전자 부품의 전극면에 형성된 도전성 범프로서, 도전성 범프가, 상이한 도전 필러 함유율을 갖는 복수의 감광성 수지층으로 이루어지는 구성을 갖는다. 이에 의해, 전극과 도전성 범프의 접착 강도의 향상과 접속 저항의 저감이라는 상반되는 기능을 구비한 도전성 범프를 실현할 수 있다. This invention is a conductive bump formed in the electrode surface of an electronic component, Comprising: A conductive bump has the structure which consists of several photosensitive resin layer which has a different conductive filler content rate. Thereby, the conductive bump with the opposite function of the improvement of the adhesive strength of an electrode and a conductive bump, and reduction of connection resistance can be implement | achieved.

Design scheme for connector site spacing and resulting structures

提供了一种用于防止钝化层中的裂纹的系统和方法。在一实施例中，接触焊盘具有第一直径并且穿过钝化层的开口具有第二直径，其中第一直径比第二直径大第一距离，该第一距离为约10μm。在另一实施例中，形成穿过开口的凸块下金属化层，该凸块下金属化层具有第三直径，第三直径比第一直径大第二距离，该第二距离为约5μm。在又一实施例中，第一距离和第二距离之和大于约15μm。本发明公开了连接件位点间隔的设计方案及得到的结构。

Semiconductor package apparatus

본 발명은 반도체 패키지 장치에 관한 것으로서, 제 1 반도체 칩, 제 1 기판, 제 1 단자 및 제 1 신호 전달 매체를 포함하는 제 1 반도체 패키지; 제 2 반도체 칩, 제 2 기판, 제 2 단자 및 2 신호 전달 매체를 포함하는 제 2 반도체 패키지; 상기 제 1 단자와 제 2 단자 사이에 설치되는 적어도 하나의 패키지 연결 솔더볼; 및 상기 패키지 연결 솔더볼의 형상을 안내하는 제 1 안내면이 형성되는 제 1 솔더볼 가이드 부재;를 포함할 수 있다. A semiconductor package device comprising: a first semiconductor package including a first semiconductor chip, a first substrate, a first terminal, and a first signal transmission medium; A second semiconductor package including a second semiconductor chip, a second substrate, a second terminal, and a second signal transmission medium; At least one package-connecting solder ball installed between the first terminal and the second terminal; And a first solder ball guide member having a first guide surface for guiding the shape of the package connection solder ball.

Forming Method for Concave Solder Bump Structure of Flip Chip Package

본 발명은 플립 칩 패키지의 오목형 솔더 범프 구조 형성 방법에 관한 것으로서, 가운데가 오목한 오목형 솔더 범프 구조는 칩과 기판 사이의 언더필 공정이 가능할 만큼의 범프 높이를 가지면서 솔더 범프의 크기나 솔더 범프간 거리의 영향을 받지 않으므로 미세 피치의 플립 칩 패키지를 구현할 수 있다. 본 발명에 따르면, 반도체 칩의 칩 패드 위에 금속 기둥을 형성하고 금속 기둥의 표면에 솔더를 도금한 후, 솔더가 미리 도포된 기판의 기판 패드 위에 솔더가 도금된 금속 기둥을 위치시키고 솔더를 리플로우하면, 용융 솔더의 표면 장력에 의하여 가운데가 오목한 형태의 오목형 솔더 범프가 형성된다. The present invention relates to a method of forming a concave solder bump structure of a flip chip package, wherein the concave concave solder bump structure in the center has a bump height sufficient to allow an underfill process between the chip and the substrate, and the size of the solder bumps or the solder bumps. Since it is not affected by the distance, a fine pitch flip chip package can be implemented. According to the present invention, after forming a metal pillar on the chip pad of the semiconductor chip and plating the solder on the surface of the metal pillar, the solder-plated metal pillar is placed on the substrate pad of the solder-coated substrate and the solder is reflowed. The concave solder bumps having a concave shape in the middle are formed by the surface tension of the molten solder. 플립 칩(flip chip), 솔더 범프(solder bump), 언더필(underfill), 미세 피치(fine pitch), 표면 장력(surface tension) Flip chip, solder bump, underfill, fine pitch, surface tension

Solder bump having cored structure and production method therefor

유심 구조 땜납 범프 및 그 제조 방법을 제공한다. 땜납 범프의 제조에 있어서, 미리, 범프의 중심 부분에 심용 페이스트를 인쇄 도포하고, 땜납 금속의 리플로우 처리 온도 근방 또는 그 이하에 이하의 온도에서 심용 페이스트를 소결함으로써 소결심을 형성하고, 이어서, 이 소결심의 주위에 땜납 금속을 인쇄법으로 도포하고, 이 땜납 금속을 리플로우 처리함으로써, 땜납 범프의 내부에, 수직인 방향으로 연장되는 소결심이 형성된 유심 구조 땜납 범프를 얻는다. A cored structure solder bump and a method of manufacturing the same are provided. In the production of the solder bump, a sintered core is formed by previously applying a core paste to the central portion of the bump and sintering the core paste at a temperature below or below the reflow treatment temperature of the solder metal, and then, By applying a solder metal around the sintered core by a printing method and reflowing the solder metal, a cored structure solder bump having a sintered core extending in a vertical direction is formed inside the solder bump.

Substrate holder and plating apparatus

本发明提供了一种基片保持装置，其能够利用密封元件实现更完全的密封，并且可以更容易和可靠地取出基片；本发明还提供了一种包含该基片保持装置的电镀设备。根据本发明的一种基片保持装置(18)包括：一个固定保持元件(54)和一个可移动保持元件(58)，它们用于将一个基片(W)保持在它们之间；一个密封元件(68)，其安装在固定保持元件(54)或可移动保持元件(58)上；以及一个吸力垫(94)，其用于吸附所述保持在固定保持元件(54)和可移动保持元件(58)之间的基片(W)的背侧表面。

Nuclear material, semiconductor package and bump electrode forming method

이 핵재료는 Sn과 Bi를 포함하는 (Sn-Bi)계 땜납 합금을 핵(12)의 표면에 도금 피막한 핵재료에 있어서, 땜납 도금층(16) 중의 Bi는 소정 범위의 농도비로 땜납 도금층 중에 분포하고 있는 핵재료이고, Bi의 농도비는 91.7 내지 106.7％의 소정 범위 내에서 땜납 도금층 중에 분포하고 있는 핵재료이다. 땜납 도금층 중의 Bi는 균질이므로, 땜납 도금층 중의 내주측, 외주측을 포함하여 그 전체 영역에 걸쳐서 Bi 농도비가 소정 범위 내에 있다. 이로 인해, 내주측이 외주측보다 빠르게 용융하고, 내주측과 외주측에서 체적 팽창차가 발생하여 핵재료가 튀어 날아가는 사태는 발생하지 않는다. 또한 땜납 도금층 전체가 거의 균일하게 용융하기 때문에, 용융 타이밍의 어긋남에 의해 발생한다고 생각되는 핵재료의 위치 어긋남은 발생하지 않으므로, 위치 어긋남 등에 수반하는 전극간의 단락 등의 우려는 없다.

Semiconductor device and its manufacturing method

本发明包括一种半导体装置及其制造方法，该半导体装置包括：一第一基材，具有一第一内连线结构；以及一第二基材，具有一第二内连线结构，该第一内连线结构连接该第二内连线结构，该第一内连线结构的第一宽度与该第二内连线结构的第二宽度不同。本发明提供一种用于使一基材与另一基材接合的凸块结构。一导电柱体形成于第一基材上，以使此导电柱体具有与一第二基材的接触表面不同的宽度。在一实施例中，第一基材的导电柱体为梯形或具有锥形侧壁，因而提供底部部分较顶部部分宽的导电柱体。所述基材均可为集成电路芯片、转接板、印刷电路板、高密度内连线或其类似物。本发明可减低关于交界处应力所产生的脱层问题。

Semiconductor eevice and manufacturing method thereof

本发明包括一种半导体装置及其制造方法，该半导体装置包括：一第一基材，具有一第一内连线结构；以及一第二基材，具有一第二内连线结构，该第一内连线结构连接该第二内连线结构，该第一内连线结构的第一宽度与该第二内连线结构的第二宽度不同。本发明提供一种用于使一基材与另一基材接合的凸块结构。一导电柱体形成于第一基材上，以使此导电柱体具有与一第二基材的接触表面不同的宽度。在一实施例中，第一基材的导电柱体为梯形或具有锥形侧壁，因而提供底部部分较顶部部分宽的导电柱体。所述基材均可为集成电路芯片、转接板、印刷电路板、高密度内连线或其类似物。本发明可减低关于交界处应力所产生的脱层问题。

INTERCOMPONENT CONNECTION PROCESS WITH OPTIMIZED DENSITY

L'invention concerne un procédé de connexion électrique par hybridation d'un premier composant (100) à un deuxième composant (200). Le procédé comportant les étapes suivantes : formation de plots en matériau ductile (111, 121) en contact respectif des zones de connexion (110, 120) du premier composant (100) ; formation d'inserts (211, 221) en matériau conducteur en contact de des zones de connexion (210, 220) du deuxième composant (200) ; formation de barrières d'hybridation (212, 222) disposées entre les inserts (211, 221) et isolées électriquement l'une de l'autre, lesdites première et deuxième barrière d'hybridation (212, 222) pour faire office de barrière en contenant la déformation des plots en matériau ductile (111, 121) lors de la connexion des zones de connexion (210, 220) du premier composant (100) avec celles du deuxième composant (200). L'invention concerne en outre un ensemble (1) de deux composants (100, 200) connectés The invention relates to a method of electrically connecting by hybridizing a first component (100) to a second component (200). The method comprising the following steps: forming pads of ductile material (111, 121) in respective contact with the connection zones (110, 120) of the first component (100); forming inserts (211, 221) of conductive material in contact with connection areas (210, 220) of the second component (200); formation of hybridization barriers (212, 222) disposed between the inserts (211, 221) and electrically isolated from each other, said first and second hybridization barrier (212, 222) to act as a barrier in containing the deformation of the pads of ductile material (111, 121) during the connection of the connection zones (210, 220) of the first component (100) with those of the second component (200). The invention further relates to an assembly (1) of two components (100, 200) connected

METHOD FOR ASSEMBLING TWO ELECTRONIC COMPONENTS

A method of self-aligned connection of a structure to a support, device obtained from such a method, and the structure and support implemented by such a method

L’invention concerne un procédé de connexion par hybridation d’une structure semiconductrice (100) sur un support (200). Le procédé comprend les étapes de : fourniture d’une structure semiconductrice (100) comprenant au moins un deux organes primaires de connexion comprenant chacun un premier élément d’alignement magnétique (122, 126) comprenant un matériau ferromagnétique ; fourniture du support (200), le support (200) comprenant au moins deux organes secondaires de connexion (221, 225) comprenant chacun un deuxième élément d’alignement magnétique (222, 226) comprenant un matériau ferromagnétique, au moins les uns parmi les premier élément d’alignement magnétique (122, 126) et le deuxièmes éléments d’alignement magnétique (222, 226) sont des aimants permanents ; et le placement et libération de la structure semiconductrice (100) à distance du support (200) pour obtenir un alignement des premiers éléments d’alignement magnétique (122, 126) avec les deuxièmes éléments d’alignement magnétique (222, 226) correspondant. Figure pour l’abrégé : figure 1C The invention relates to a method of connection by hybridization of a semiconductor structure (100) on a support (200). The method includes the steps of: providing a semiconductor structure (100) comprising at least one of two primary connection members each comprising a first magnetic alignment element (122, 126) comprising a ferromagnetic material; provision of the support (200), the support (200) comprising at least two secondary connection members (221, 225) each comprising a second magnetic alignment element (222, 226) comprising a ferromagnetic material, at least one of first magnetic alignment element (122, 126) and second magnetic alignment element (222, 226) are permanent magnets; and placing and releasing the semiconductor structure (100) away from the support (200) to obtain alignment of the first magnetic alignment elements (122, 126) with the corresponding second magnetic alignment elements (222, 226). Figure ...

Interconnection structure including a metal post encapsulated by solder joint having a concave outer surface

A semiconductor device includes a carrier, an under bump metallurgy (UBM) pad on the carrier, and a post on a surface of the UBM pad. In some embodiments, a height of the post to a longest length of the UBM pad is between about 0.25 and about 0.7. A method of manufacturing a semiconductor device includes providing a carrier, disposing a UBM pad on the carrier and forming a post on the UBM pad.

Semiconductor chip and production process therefor

A semiconductor chip including a bump projecting from a surface protective film thereof and a surface interconnection having a smaller height than the bump. The surface interconnection may project from the surface protective film or may be flush with the surface protective film. The surface interconnection may be connected to the bump. The bump may include a peripheral bump configured as surrounding a device formation region of the chip. The peripheral bump may be connected to the ground or a power source.

Implantable microelectronic device and method of manufacture

Semiconductor chip and Semiconductor package including the same

본 발명의 실시에에 따른 반도체 패키지는 패키지 기판 및 상기 패키지 기판 상의 제 1 반도체 칩을 포함하되, 상기 제 1 반도체 칩은, 서로 대향하는 제 1 면 및 제 2 면을 포함하는 기판 및 상기 기판의 상기 제 2 면 상에 배치되는 재배선들을 포함하고, 상기 기판의 상기 제 2 면 상에 배치된 제 2 반도체 칩, 상기 제 2 반도체 칩과 상기 재배선들 사이를 전기적으로 연결하는 연결부들 및 상기 재배선들과 상기 패키지 기판 사이를 전기적으로 연결하는 본딩 와이어들을 포함할 수 있다.

Microelectronic packages and methods therefor

A microelectronic package includes a microelectronic element having a first face including contacts, and a flexible substrate having a first surface and a second surface, conductive posts projecting from the first surface and conductive terminals accessible at the second surface, at least some of the conductive terminals and the conductive posts being electrically interconnected and at least some of the conductive terminals being offset from the conductive posts. The first surface of the flexible substrate is juxtaposed with the first face of the microelectronic element so that the conductive posts project from the flexible substrate toward the first face of the microelectronic element. The conductive posts are electrically interconnected with the contacts of the microelectronic element and at least some of the conductive terminals are movable relative to the microelectronic element.

Method for contacting a power semiconductor device on a substrate

The invention relates to a method for contacting a power semiconductor device (2) on a substrate (4). In order to achieve improved switching behaviour and a higher maximum current density, according to the invention the power semiconductor device (2) has, on a side (8) facing the substrate (4), at least two contact regions (10, 12) which are electrically isolated from one another, and the at least two contact regions (10, 12) of the power semiconductor device (2) which are electrically isolated from from one another are integrally bonded to the substrate (4) by means of a structured, in particular metal, connecting layer (26) which comprises at least two substantially closed sintered layers (20, 24, 36).