Verfahren zum Herstellen einer Lötverbindung und Schaltungsbauteil

Die Erfindung betrifft ein Verfahren zum Herstellen einer Lötverbindung (20), bei dem auf ein Trägerelement (10) zwei Schichten (21; 21a, 22; 22a) aufgebracht werden, wobei die erste Schicht (21; 21a) zumindest Metallpartikel und Zusatzstoffe, insbesondere Flussmittel, und die zweite Schicht (22; 22a) zumindest Lotmittel aufweist, und wobei das Trägerelement (10) und die beiden Schichten (21; 21a, 22; 22a) anschließend einer Wärmebehandlung unterzogen werden, bei der die zweite Schicht (22; 22a) verflüssigt wird und in Wirkverbindung mit der ersten Schicht (21; 21a) gelangt. Erfindungsgemäß ist es vorgesehen, dass zur Ausbildung der ersten Schicht (21; 21a) und/oder der zweiten Schicht (22; 22a) wenigstens ein vorgefertigtes Element (31, 32) verwendet wird.

ARRANGEMENT FOR THE REDUCTION OF PIEZOELECTRIC EFFECTS IN AT LEAST A IN OF AN ACTIVE SEMICONDUCTOR MATERIAL LAYER ARRANGEMENT PIEZOELECTRIC EFFECT-SENSITIVE, ELECTRICAL ELEMENT

Method and system for extending die size and packaged semiconductor devices incorporating the die

ASSEMBLING AN INTEGRATED CIRCUIT DIE AND A PLATE

CYLINDRICAL PACKAGE WHICH CAN BE APPLIED TO AN ELECTRONIC PRODUCT HAVING CURVATURE, AND AN ELECTRONIC DEVICE USING THE SAME AND A MANUFACTURING METHOD THEREOF

PURPOSE: A cylindrical package and electronic device and a manufacturing method thereof are provided to reduce residual stress by accepting essential bending of a semiconductor chip and increase design freedom. CONSTITUTION: A cylindrical substrate has a hollow part in inside. The cylindrical substrate is a flexible substrate. One or more semiconductor chips(200, 202, 204) are mounted along the outer circumference of the cylindrical substrate. A wire(160) interlinks a chip pad of the semiconductor chip and a substrate pad of the cylindrical substrate. An adhesive(150) bonds the outer circumference of the cylindrical substrate and the bottom of the semiconductor chip. An interconnection part electrically interlinks the chip pad of the semiconductor chip and the substrate pad of the cylindrical substrate. COPYRIGHT KIPO 2012 ...

Semiconductor device and method of manufacture

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

A semiconductor package includes a package substrate, an interposer on the package substrate, and a first semiconductor device and a second semiconductor device on the interposer, the first and second semiconductor devices connected to each other by the interposer, wherein at least one of the first semiconductor device and the second semiconductor device includes an overhang portion protruding from a sidewall of the interposer.

SEMICONDUCTOR PACKAGING AND MANUFACTURING METHOD THEREOF

The present disclosure provides a semiconductor package includes a contact pad, a device external to the contact pad and a solder bump on the contact pad. The device has a conductive contact pad corresponding to the contact pad. The solder bump connects the contact pad with the conductive contact pad. The solder bump comprises a height from a top of the solder bump to the contact pad; and a width which is a widest dimension of the solder bump in a direction perpendicular to the height. A junction portion of the solder bump in proximity to the contact pad comprises an hourglass shape.

Method of forming a dummy die of an integrated circuit having an embedded annular structure

An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.

Multi-chip package structure having chip interconnection bridge which provides power connections between chip and package substrate

Multi-chip package structure having chip interconnection bridge which provides power connections between chip and package substrate

Multi-chip package structures and methods for constructing multi-chip package structures are provided, which utilize chip interconnection bridge devices that are designed to provide high interconnect density between adjacent chips (or dies) in the package structure, as well as provide vertical power distribution traces through the chip interconnection bridge device to supply power (and ground) connections from a package substrate to the chips connected to the chip interconnection bridge device.

Silicon photonic interposer with two metal redistribution layers

ELECTRONIC DEVICE, METHOD OF MANUFACTURING THE SAME, AND CAMERA

A method of manufacturing an electronic device, comprising fixing a first wafer on a second wafer to form a space theirbetween, via a surrounding member configured to surround the space, forming an opening on a bottom side of the first wafer to expose a conductive member included in the first wafer, and then forming an electrode connected to the conductive member, wherein, in the fixing, the first wafer includes a trench intersecting the surrounding member, on an upper side of the first surface, and, in the forming, the electrode is formed under a condition that the space communicates with an external space via the trench. 1. A method of manufacturing an electronic device , comprising:fixing a first wafer and a second wafer to each other via a surrounding member, such that the first wafer and the second wafer face each other via a space and the surrounding member surrounds the space, the first wafer including a semiconductor substrate and a wiring structure arranged on the semiconductor substrate; andforming an opening on a side of a second surface of the first wafer on an opposite side of a first surface on a side of the second wafer so as to expose a conductive member of the wiring structure, and then forming an electrode connected to the conductive member exposed via the opening,wherein in the fixing, the first wafer includes, on a side of the first surface, a trench that intersects the surrounding member in a planar view of the first surface, andin the forming, the electrode is formed under a condition that the space communicates with an external space via the trench.2. The method according to claim 1 , wherein in the fixing claim 1 , a cover member is arranged between the surrounding member and the trench at a position where the surrounding member intersects the trench in the planar view.3. The method according to claim 2 , wherein the cover member extends up to a position where the surrounding member does not intersect the trench in the planar view claim 2 , ...

Electronic device

An electronic device includes a substrate, a plurality of micro semiconductor structure, a plurality of conductive members, and a non-conductive portion. The substrate has a first surface and a second surface opposite to each other. The micro semiconductor structures are distributed on the first surface of the substrate. The conductive members electrically connect the micro semiconductor structures to the substrate. Each conductive member is defined by an electrode of one of the micro semiconductor structures and a corresponding conductive pad on the substrate. The non-conductive portion is arranged on the first surface of the substrate. The non-conductive portion includes one or more non-conductive members, and the one or more non-conductive members are attached to the corresponding one or more conductive members of the one or more micro conductive structures.

UNIVERSAL ELECTRICALLY INACTIVE DEVICES FOR INTEGRATED CIRCUIT PACKAGES

Elektronische Vorrichtung und Verfahren zum Herstellen einer Elektronischen Vorrichtung

Ein Verfahren zum Herstellen einer elektronischen Vorrichtung umfasst ein gleichzeitiges Befestigen eines ersten und eines zweiten Halbleiterchips mithilfe eines Übertragungselements auf einem Träger, wobei das Befestigen des ersten Halbleiterchips ein erstes Befestigungsverfahren umfasst und wobei das Befestigen des zweiten Halbleiterchips ein zweites Befestigungsverfahren umfasst, das verschieden ist von dem ersten Befestigungsverfahren.

Lötschicht und Substrat bzw. Submount zum Kontaktieren von elektronischen Bauelementen unter Verwendung derselben

Es werden eine Lötschicht und ein elektronisches Bauelement kontaktierendes Substrat unter Verwendung der Schicht geschaffen, die verhindern, dass sich Eigenschaften des zu kontaktierenden elektronischen Bauelements verschlechtern. Eine Lötschicht 14, bleifrei und auf einem Substrat 11 ausgebildet, oder jene Lötschicht 14 bei einem elektronische Bauelemente kontaktierenden Substrat 10 weist einen spezifischen Widerstand von nicht mehr als 0,4 Omega . µm auf. Das elektronische Bauelement kontaktierende Substrat 10 kann einen Wärmeleitwiderstand von nicht mehr als 0,5 K/W und eine Dicke von nicht mehr als 10 µm aufweisen. Dann weisen Hohlräume, die in der Lötschicht 14 enthalten sind, einen maximalen Durchmesser von nicht mehr als 0,5 µm auf, und das Substrat kann ein Submount-Substrat sein.

Semiconductor package

Power semiconductor device

ASSEMBLING A INTEGRATED CIRCUIT DIE AND A PLATE

L'invention concerne un assemblage d'une puce (3) de circuits intégrés et d'une plaque (5), dans lequel au moins un canal (15) disposé entre la puce et la plaque s'étend d'un bord à un autre bord de la plus petite de la puce ou de la plaque, et est délimité par des parois latérales métalliques (17) s'étendant au moins partiellement d'une face de la puce à une face en regard de la plaque.

Chip carrier, a device and a method

According to various embodiments, a chip carrier may include: a chip supporting region configured to support a chip; a chip contacting region including at least one contact pad for electrically contacting the chip; wherein the chip carrier is thinned in the chip contacting region such that a first thickness of the chip carrier at the at least one contact pad is smaller than a second thickness of the chip carrier in the chip supporting region.

ELECTRONIC COMPONENT MOUNTING STRUCTURE

An electronic component mounting structure includes: an electronic component including a plurality of bump electrodes that includes a base resin provided on an active face of the electronic component and a plurality of conductive films that cover a part of a surface of the base resin, expose an area excluding the part of the surface, and are electrically coupled to a plurality of electrode terminals provided on the active face; and a substrate including a plurality of terminals. In the structure, the electronic component is mounted on the substrate, and the base resin includes: a first opening surrounding the plurality of the electrode terminals; a connection portion in which a part of one ends of the plurality of the conductive films that are drawn out on the surface of the base resin is disposed, the other ends of the conductive films being coupled to the electrode terminals; and a bonding portion that is bonded to the substrate, and is formed in an area excluding the first opening and ...

Semiconductor device, manufacturing method of semiconductor device, stack type semiconductor device, and manufacturing method of stack type semiconductor device

A semiconductor device capable mounting semiconductor elements having different functions without increasing the area of the semiconductor device, and its manufacturing method are presented. A part of wiring 104 is formed al so at the side surface of a semiconductor element 101, and bump electrodes 102 formed so as to be nearly on a same plane as the wiring 104 formed at the side surface of the semiconductor element 101, at least a part of ball electrodes 103 is formed so as to connect electrically to the wiring 104 at the side surface of the semiconductor element, the side surface of the semiconductor element is sealed with resin exposing the wiring 104, and the confronting surface of the circuit forming surface is sealed with resin.

EPOXY RESIN COMPOSITION, METHOD FOR PRODUCING COMPOSITE UNIT USING THE EPOXY RESIN COMPOSITION, AND COMPOSITE UNIT

An epoxy resin composition having excellent connection reliability and transparency, a method for manufacturing a composite unit using the epoxy resin composition, and the composite unit, are disclosed. The manufacturing method includes an attaching step of attaching an epoxy resin composition (2) containing a novolak phenolic curing agent, an acrylic elastomer composed of a copolymer containing dimethylacrylamide and hydroxylethyl methacrylate, an epoxy resin and not less than 5 parts by weight to not more than 20 parts by weight of an inorganic filler to 100 parts by weight of the epoxy resin, to a printed circuit board (1) in the form of a sheet. The manufacturing method also includes a temporary loading step of temporarily loading a semiconductor chip (3) and capacitors (4a) to (4d) on the epoxy resin composition (2) and an ultimate pressure bonding step of pressuring the semiconductor chip (3) and capacitors (4a) to (4d) by a thermal bonding head (20) in situ to ultimately pressure ...

Die Attach Methods and Semiconductor Devices Manufactured based on Such Methods

A method includes providing a carrier, depositing a die attach material on the carrier, and arranging a semiconductor die on the die attach material, wherein a main surface of the semiconductor die facing the die attach material at least partly contacts the die attach material, wherein immediately after arranging the semiconductor die on the die attach material, a first maximum extension of the die attach material over edges of the main surface is less than about 100 micrometers. 1. A method , comprising:providing a carrier;depositing a die attach material on the carrier; andarranging a semiconductor die on the die attach material,wherein a main surface of the semiconductor die facing the die attach material at least partly contacts the die attach material,wherein immediately after arranging the semiconductor die on the die attach material, a first maximum extension of the die attach material over edges of the main surface is less than about 100 micrometers.2. The method of claim 1 , further comprising:forming a fillet of the die attach material at a side surface of the semiconductor die, wherein forming the fillet is based on a creeping of the die attach material along the side surface of the semiconductor die.3. The method of claim 2 , wherein the creeping of the die attach material is based on an adhesive force between the die attach material and the semiconductor die.4. The method of one of claim 1 , further comprising:after arranging the semiconductor die on the die attach material, further extending the die attach material over the edges of the main surface,wherein a second maximum extension of the die attach material over the edges of the main surface is less than about 200 micrometers.5. The method of claim 1 , further comprising:curing the die attach material at a curing time in a range from about 10 minutes to about 3 hours and a curing temperature in a range from about 100 degrees Celsius to about 300 degrees Celsius.6. The method of claim 1 , wherein a ...

Semiconductor Device Assembly Including a Chip Carrier, Semiconductor Wafer and Method of Manufacturing a Semiconductor Device

A semiconductor device includes a chip carrier and a semiconductor die with a semiconductor portion and a conductive structure. A soldered layer mechanically and electrically connects the chip carrier and the conductive structure at a soldering side of the semiconductor die. At the soldering side an outermost surface portion along an edge of the semiconductor die has a greater distance to the chip carrier than a central surface portion. The conductive structure covers the central surface portion and at least a section of an intermediate surface portion tilted to the central surface portion. Solder material is effectively prevented from coating such semiconductor surfaces that are prone to damages and solder-induced contamination is significantly reduced.

IMAGING DEVICE, MANUFACTURING METHOD, AND ELECTRONIC DEVICE

Verfahren zur Herstellung einer leistungselektronischen Schalteinrichtung und leistungselektronische Schalteinrichtung

Es wird ein Verfahren zur Herstellung einer leistungselektronische Schalteinrichtung vorgestellt. Hierbei wird ein Leistungshalbleiterbauelement auf einem ersten Bereich einer Leiterbahn eines Substrats oder auf einem ersten Abschnitt einer Verbindungseinrichtung angeordnet. Anschließend wird ein Isolierstoff, der dazu eingerichtet ist im Rahmen eines Umformungsprozesses eine adhäsive Kontaktfläche auszubilden, auf einem zweite Bereich des Substrats, der dafür vorgesehen ist unmittelbar an einer Seitenfläche eines zugeordneten Leistungshalbleiterbauelements anzuschließen oder auf einem zweiten Abschnitt der Verbindungseinrichtung, der dafür vorgesehen ist an der Seitenfläche eines zugeordneten Leistungshalbleiterbauelements zu liegen zu kommen, angeordnet. Danach wird die Verbindungseinrichtung bündig zum Substrat angeordnet; danach wird die leistungselektronischen Schalteinrichtung mit einer Temperatur von 110°C bis 400°C und einem Druck von 5 MPa bis 50 MPa beaufschlagt, wobei gleichzeitig ...

For semiconductor package in which a reduced die to the die bottom of the interval of the filling material flow control

描述了用于半导体封装中的减小的管芯到管芯间隔的底部填充材料流控制和所得的半导体封装。在一示例中，半导体装置包括第一和第二半导体管芯，每个半导体管芯具有其上有集成电路的表面，所述集成电路通过多个导电接触耦合于公共半导体封装衬底的最上面金属化层的接触盘，该第一和第二板导体管芯分开一间隔。阻挡层结构位于第一半导体管芯和公共半导体封装衬底之间并且至少部分地在第一半导体管芯之下。底部填充材料层与第二半导体管芯接触并且与阻挡层结构接触，但是不与第一半导体管芯接触。

Semiconductor package and manufacturing method thereof

A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and a method of manufacturing thereof, that comprises a first semiconductor die, a plurality of adhesive regions spaced apart from each other on the first semiconductor die, and a second semiconductor die adhered to the plurality of adhesive regions.

Strain-tolerant die attach with improved thermal conductivity, and method of fabrication

A mechanically-stable and thermally-conductive interface device between a semiconductor die and a package for the die, and related method of fabrication, comprising: a semiconductor die; a package for the die; a surface area-enhancing pattern on the package and/or the die; and die attach materials between the die and the package, the die attach materials attaching the die to the package through an interface provided by the die attach materials; wherein: an effective bonding area between the die attach materials and the package and/or the die is greater with the pattern than without the pattern; and the increase of the effective bonding area simultaneously increases the surface area for thermal transport between the package and/or the die, and the die attach materials; and increases the surface area for stably attaching the at least one of the package and the die to the die attach materials.

ANORDNUNG ZUR VERMINDERUNG VON PIEZOEFFEKTEN IN MINDESTENS EINEM IN EINER AKTIVEN HALBLEITERMATERIALSCHICHT ANGEORDNETEN PIEZOEFFEKT-EMPFINDLICHEN, ELEKTRISCHEN BAUELEMENT

STAPEL ELEKTRISCHER BAUELEMENTE UND VERFAHREN ZUR HERSTELLUNG DESSELBEN

Ein Stapel elektrischer Bauelemente hat ein erstes elektrisches Bauelement mit einer ersten Oberfläche, einer zweiten Oberfläche, die der ersten Oberfläche entgegengesetzt ist, und einer Seitenfläche, die sich zwischen der ersten Oberfläche und der zweiten Oberfläche befindet; ein zweites elektrisches Bauelement mit einer dritten Oberfläche, auf die das erste elektrische Bauelement montiert ist, wobei die dritte Oberfläche der zweiten Oberfläche gegenüberliegt und einen Eckbereich zwischen der dritten Oberfläche und der Seitenfläche bildet; eine Klebeschicht, die das erste elektrische Bauelement an das zweite elektrische Bauelement bindet, wobei die Klebeschicht einen ersten Abschnitt umfasst, der zwischen der zweiten Oberfläche und der dritten Oberfläche gelegen ist, und einen gekrümmten zweiten Abschnitt umfasst, der den Eckbereich ausfüllt; und eine leitende Schicht, die sich auf einer Seite der Seitenfläche erstreckt, entlang des zweiten Abschnitts gekrümmt ist und sich zur dritten ...

Verfahren zur Niedertemperatur Drucksinterverbindung zweier Verbindungspartner und hiermit hergestellte Anordnung

Die Anmeldung betrifft eine Anordnung und ein Verfahren zu deren Herstellung. Diese weist einen ersten und einem zweiten Verbindungspartner auf, die mittels einer Niedertemperatur-Drucksinterverbindung miteinander stoffschlüssig mittels einer Sintermetallschicht verbunden sind. Die Verfahrensschritte sind: Bereitstellen eines ersten Verbindungspartners mit einer ersten Kontaktfläche. Aufbringen einer Schicht aus einer Sinterpaste, bestehend aus Sintermetallpartikeln und einem Lösungsmittel, auf die erste Kontaktfläche. Temperaturbeaufschlagung der Sinterpaste und Austreiben des Lösungsmittels unter Bildung der Sinterschicht. Aufbringen einer Flüssigkeit auf der Sinterschicht. Anordnen des zweiten Verbindungspartners. Anordnen eines Adhäsionsmittels im Randbereich der Sinterschicht und des zweiten Verbindungspartners mit Kontakt zum ersten Verbindungspartner zur Fixierung der Verbindungspartner zueinander. Weitere Beaufschlagung der Anordnung mit Temperatur und Druck zur Ausbildung der stoffschlüssigen ...

반도체 장치의 제조 방법

본원의 발명과 관련되는 반도체 장치는, 실장 기판과, 상기 실장 기판에 도포된 접착제와, 상기 접착제에 의해 하면이 상기 실장 기판과 접착된 디바이스를 구비하고, 상기 디바이스의 측면 상부는 상기 디바이스의 측면 하부보다 표면 거칠기가 작은 것을 특징으로 한다.

Semiconductor apparatus and method for manufacturing semiconductor apparatus

A semiconductor apparatus according to the present invention includes a mounting substrate, adhesive applied on the mounting substrate, and a device attached to the mounting substrate in the underside of the device by the adhesive, wherein an upper portion of a side surface of the device has a surface roughness smaller than that of a lower portion of the side surface of the device.

Hermetically sealed MEMS device and its fabrication

In described examples, a hermetic package of a microelectromechanical system (MEMS) structure includes a substrate having a surface with a MEMS structure of a first height. The substrate is hermetically sealed to a cap forming a cavity over the MEMS structure. The cap is attached to the substrate surface by a vertical stack of metal layers adhering to the substrate surface and to the cap. The stack has a continuous outline surrounding the MEMS structure while spaced from the MEMS structure by a distance. The stack has: a first bottom metal seed film adhering to the substrate and a second bottom metal seed film adhering to the first bottom metal seed film; and a first top metal seed film adhering to the cap and a second top metal seed film adhering to the first top metal seed film.

CHIP PACKAGE WITH INTERPOSER SUBSTRATE

A chip package is provided. The chip package includes a redistribution structure including an insulating layer and a wiring layer. The wiring layer is in the insulating layer. The chip package includes a chip over the redistribution structure and electrically connected to the wiring layer. The chip package includes an interposer substrate over the redistribution structure and the chip, wherein a portion of the chip is in the interposer substrate. The chip package includes a conductive structure between the interposer substrate and the redistribution structure and electrically connected to the wiring layer. The conductive structure includes a conductive bump or a conductive pillar. The chip package includes a molding layer surrounding the interposer substrate and the conductive structure. The molding layer is partially between the interposer substrate and the redistribution structure and partially between the interposer substrate and the chip.

WINDOW BALL GRID ARRAY (WBGA) PACKAGE AND METHOD FOR MANUFACTURING THE SAME

A WBGA package and a method of manufacturing a WBGA package are provided. The WBGA package includes a first substrate having a first through hole and a second substrate having a second through hole over the first through hole of the first substrate. The WBGA package also includes an electronic component having an active surface over the second through hole of the second substrate.

Method for low temperature pressure interconnection of two connection partners and assembly manufactured using same

Die Anmeldung betrifft eine Anordnung und ein Verfahren zu deren Herstellung. Diese weist einen ersten und einem zweiten Verbindungspartner auf, die mittels einer Niedertemperatur-Drucksinterverbindung miteinander stoffschlüssig mittels einer Sintermetallschicht verbunden sind. Die Verfahrensschritte sind: Bereitstellen eines ersten Verbindungspartners mit einer ersten Kontaktfläche. Aufbringen einer Schicht aus einer Sinterpaste, bestehend aus Sintermetallpartikeln und einem Lösungsmittel, auf die erste Kontaktfläche. Temperaturbeaufschlagung der Sinterpaste und Austreiben des Lösungsmittels unter Bildung der Sinterschicht. Aufbringen einer Flüssigkeit auf der Sinterschicht. Anordnen des zweiten Verbindungspartners. Anordnen eines Adhäsionsmittels im Randbereich der Sinterschicht und des zweiten Verbindungspartners mit Kontakt zum ersten Verbindungspartner zur Fixierung der Verbindungspartner zueinander. Weitere Beaufschlagung der Anordnung mit Temperatur und Druck zur Ausbildung der stoffschlüssigen ...

Verfahren zur Herstellung einer leistungselektronischen Schalteinrichtung und leistungselektronische Schalteinrichtung

Verfahren zur Herstellung einer leistungselektronische Schalteinrichtung (1) mit einem Substrat (2), einem hierauf angeordneten Leistungshalbleiterbauelement (24) und einer flächigen Verbindungseinrichtung (3), die Verbindungspartner der leistungselektronischen Schalteinrichtung (1) ausbilden, mit den Verfahrensschrittena) Bereitstellen des Substrats (2) mit ersten gegeneinander elektrisch isolierten Leiterbahnen (22), des Leistungshalbleiterbauelements (24) und der Verbindungseinrichtung (3);b) Anordnen des Leistungshalbleiterbauelements (24) auf einem ersten Bereich (220) einer zugeordneten Leiterbahn (22) des Substrats (2) oder einem dafür vorgesehenen ersten Abschnitt (320) der Verbindungseinrichtung (3);c) Anordnen eines Isolierstoffes (5), der im Rahmen eines Umformungsprozesses eine adhäsive Kontaktfläche (52) ausbildet, auf einem zweite Bereich (250) des Substrats (2), der unmittelbar an einer Seitenfläche (242) eines zugeordneten Leistungshalbleiterbauelements (24) anschließt, dabei auch einen direkt hieran angrenzender Randbereich der Oberfläche dieses Leistungshalbleiterbauelements (24) überdeckt,;d) Anordnen der Verbindungseinrichtung (3) bereichsweise bündig zum Substrat (2);e) Beaufschlagung der leistungselektronischen Schalteinrichtung (1) mit einer Temperatur von 110°C bis 400°C und einem Druck von 5 MPa bis 50 MPa, wobei gleichzeitig mindestens zwei Verbindungspartner miteinander stoffschlüssig verbunden werden und ein Umformprozess stattfindet, wodurch der Isolierstoff (5) adhäsiv stoffschlüssig, mit einem dritten Abschnitt (360) der Verbindungseinrichtung (3) und einem dritten Bereich (260) des Substrats (2) verbunden wird. Method for producing a power electronic switching device (1) with a substrate (2), a power semiconductor component (24) arranged thereon and a flat connecting device (3), which form connection partners of the power electronic switching device (1), with the method steps a) providing the substrate (2) ) with first mutually ...

Semiconductor device and method thereof

本发明涉及半导体装置及其方法。该方法包括提供具有第一主表面和第二主表面的半导体芯片。以半导体芯片的第一主表面面向承载件的形式，将半导体芯片放置在承载件上。在第一主表面和承载件之间设置焊料材料的第一层。以第一接触区域面向半导体芯片的第二主表面的方式，将包括第一接触区域的接触夹放置在半导体芯片上。在第一接触区域和第二主表面之间设置焊料材料的第二层。其后，将热量施加于焊料材料的第一层和第二层，从而在承载件、半导体芯片和接触片之间形成扩散焊料结合。

UNDERFILL FILM FOR PRINTED WIRING ASSEMBLIES

A self supported underfill film (18) adhesively bonds surface mount integrated circuit packages (14) to a printed circuit board (10). The printed circuit board has conductive traces (12) and exposed conductive pads (13) on the surface. A film adhesive is strategically positioned on the printed circuit board near the conductive pads, and the surface mount integrated circuit package is then placed on the board so that the conductive pads (16) on the package align with the conductive pads on the board. The film adhesive softens when the package is soldered to the board, and the film ultimately serves as an underfill to increase the mechanical integrity of the solder joints. © KIPO & WIPO 2007 ...

Semiconductor device and manufacturing method of semiconductor device

The manufacturing method of a semiconductor device includes applying a conductive paste containing metal particles to a specified area in an electrode plate including a recess in a surface of the electrode plate, the specified area being adjacent to the recess. The manufacturing method of a semiconductor device includes placing a semiconductor chip on the conductive paste so that an outer peripheral edge of the semiconductor chip is located above the recess. The manufacturing method of a semiconductor device includes hardening the conductive paste by heating the conductive paste while applying pressure to the semiconductor chip in a direction toward the electrode plate.

SEMICONDUCTOR DEVICE

A first chip including electrodes is mounted above an expanded semiconductor chip formed by providing an expanded portion at an outer edge of a second chip including chips. The electrodes of the first chip are electrically connected to the electrodes of the second chip by conductive members. A re-distribution structure is formed from a top of the first chip outside a region for disposing the conductive members along a top of the expanded portion. Connection terminals are provided above the expanded portion, and electrically connected to ones of the electrodes of the first chip via the re-distribution structure.

Semiconductor device, manufacturing method thereof, and electronic apparatus

A semiconductor device includes a substrate and a semiconductor element mounted on the top surface of the substrate. On the top surface of the substrate, one or more pads are disposed outside the mounted semiconductor element when seen in a plan view. Then, a protrusion is disposed on each of the pads. A heat sink is disposed above the semiconductor element and the protrusions, and then bonded to the substrate by an adhesive provided between the heat sink and the substrate. The adhesive is provided in such a manner as to be in contact with the protrusions on the substrate.

Semiconductor package and method for manufacturing the same

The present disclosure provides a semiconductor package that prevents a bump bridge from being formed between adjacent conductive bumps to realize a fine bump pitch when each unit circuit part is directly stacked without using a printed circuit board and a method for manufacturing the same. The semiconductor package includes a first semiconductor chip structure including a first unit circuit part, a first passivation layer disposed on the first unit circuit part, and a conductive bump electrically connected to the first unit circuit part, and a second semiconductor chip structure including a second unit circuit part, a second passivation layer having a stepped portion that is recessed inward and disposed on the second unit circuit part, and a bump pad provided in the stepped portion. The first semiconductor chip structure and the second semiconductor chip structure are stacked to allow the conductive bump to be bonded to the bump pad within the stepped portion.

CHIP CARRIER, A DEVICE AND A METHOD

According to various embodiments, a chip carrier may include: a chip supporting region configured to support a chip; a chip contacting region including at least one contact pad for electrically contacting the chip; wherein the chip carrier is thinned in the chip contacting region such that a first thickness of the chip carrier at the at least one contact pad is smaller than a second thickness of the chip carrier in the chip supporting region.

Halbleiterbauteil

Ein Halbleiterbauteil gemäß der vorliegenden Erfindung beinhaltet einen Halbleiterchip mit einer Halbleiterschicht, die eine erste Fläche an einer Chip-Bond-Seite hat, eine zweite Fläche an der gegenüberliegenden Seite der der ersten Fläche hat und eine endseitige Fläche hat, die sich in einer Richtung erstreckt, die die erste Fläche und die zweite Fläche kreuzt, wobei der Halbleiterchip eine erste Elektrode aufweist, die an der ersten Fläche gebildet ist und die eine Umfangskante an einer Position hat, die gegenüber der endseitigen Fläche nach innen beabstandet ist, und der eine zweite Elektrode aufweist, die an der zweiten Fläche gebildet ist, wobei das Halbleiterbauteil ein leitfähiges Substrat aufweist, auf das der Halbleiterchip chip-gebondet ist, wobei das Halbleiterbauteil ein leitfähiges Abstandselement aufweist, das eine ebenen Flächenbereich hat, der kleiner ist als jener der ersten Elektrode und der den Halbleiterchip an dem leitfähigen Substrat lagert, und das ein Kunstharzgehäuse ...

TSV들을 이용하는 통합된 마이크로폰 디바이스를 가진 다이

... 본 개시 내용의 실시예들은 TSV들 및 연관되는 기법들 및 구성을 이용하는 통합되는 마이크로폰 디바이스를 가진 다이를 기술한다. 일 실시예에서, 장치는 제1 측 및 제1 측에 대향하여 배치되는 제2 측을 갖는 반도체 기판, 반도체 기판의 제1 측상에 형성되는 인터커넥트 층, 반도체 기판을 관통해 형성되고 또한 반도체 기판의 제1 측과 반도체 기판의 제2 측 사이에서 전기 신호들의 경로를 설정하도록 구성되는 TSV, 및 반도체 기판의 제2 측상에 형성되고 또한 TSV와 전기적으로 결합되는 마이크로폰 디바이스로 구성되는 장치를 포함한다. 기타 실시예들이 설명 및/또는 청구될 수 있다.

PACKAGE STRUCTURE

A package structure, comprising: a substrate, having at least one conductive units provided at a first surface of the substrate; at least one first die, provided on a second surface of the substrate; a connecting layer; a second die, provided on the connecting layer, wherein the connecting layer comprises at least one bump for connecting the first die to the second die such that the first die and the second die are electrically connected; and at least one bonding wire, for electrically connecting the first die to the conductive units or the substrate.

DIE PACKAGE COMPONENT WITH JUMPER STRUCTURE AND MANUFACTURING METHOD THEREOF

A die package component with a jumper structure includes a first lead frame, a second lead frame, a die, a jumper structure and a package body. The first lead frame has a die connection surface. The second lead frame is separated to the first lead frame. The second lead frame has a lead frame connection groove which defines a thermal deformation tolerance allowable route. The jumper structure is thermally deformed in a thermal-variable environment. The jumper structure includes a die welding portion and a lead welding portion. The die welding portion is welded to the die. Upon meeting a thermal deformation, the lead welding portion would be movable welded along the thermal deformation tolerance allowable route to the lead frame connection groove.

BONDING HEAD AND METHOD FOR BONDING SEMICONDUCTOR PACKAGE, AND SEMICONDUCTOR PACKAGE

A method for bonding a semiconductor package includes loading a semiconductor chip on a substrate, and bonding the semiconductor chip to the substrate by using a bonding tool, the bonding tool including a pressing surface for pressing the semiconductor chip, and an inclined surface extending from one side of the pressing surface. Bonding the semiconductor chip to the substrate includes deforming a bonding agent disposed between the substrate and the semiconductor chip by pressing the bonding tool, and deforming the bonding agent includes generating a fillet by protruding a portion of the bonding agent beyond the semiconductor chip, and growing the fillet in such a way that a top surface of the fillet is grown in an extending direction of the inclined surface. 1. A method for bonding a semiconductor package , the method comprising:loading a semiconductor chip on a substrate; andbonding the semiconductor chip to the substrate by using a bonding tool, the bonding tool including a pressing surface for pressing the semiconductor chip, and an inclined surface extending from one side of the pressing surface,wherein bonding the semiconductor chip to the substrate includes deforming a bonding agent disposed between the substrate and the semiconductor chip by pressing the bonding tool, andwherein deforming the bonding agent includes generating a fillet by protruding a portion of the bonding agent beyond the semiconductor chip, and growing the fillet in such a way that a top surface of the fillet is grown in an extending direction of the inclined surface.2. The method as claimed in claim 1 , wherein the inclined surface is provided in plurality.3. The method as claimed in claim 1 , wherein bonding the semiconductor chip to the substrate further includes hardening the deformed bonding agent.4. The method as claimed in claim 3 , further comprising removing the bonding tool after hardening the deformed bonding agent.5. The method as claimed in claim 3 , wherein hardening the ...

HALBLEITEREINHEIT UND VERFAHREN ZUR HERSTELLUNG DERSELBEN

Eine Halbleitereinheit (1) weist Folgendes auf: ein Keramiksubstrat (21), das an beiden Oberflächen Leiterschichten (23) und (24) aufweist; ein Halbleiterelement (11), das mit der oberen Leiterschicht (23) des Keramiksubstrats (21) verbunden ist; ein Rahmenelement (61), das an der oberen Leiterschicht (23) so angeordnet ist, dass es eine seitliche Oberfläche des Halbleiterelements (11) umgibt; sowie eine Elektrode (41), die über eine zweite Befestigungsschicht (32) mit einem oberen Bereich des Halbleiterelements (11) verbunden ist und Anbringungsbereiche (42) an einer seitlichen Oberfläche der Elektrode aufweist. An einer Innenwand des Rahmenelements (61) sind Anbringungsbereiche (62), die an den Anbringungsbereichen (42) der Elektrode (41) anzubringen sind, sowie vier Positionierungsbereiche (63) ausgebildet, die sich von der Innenwand des Rahmenelements (61) zu den seitlichen Oberflächen der Elektrode (41) erstrecken.

반도체 장치의 제조 방법

배선 기판 위에, 평면으로 보았을 때 평면 사이즈가 다른 제1 반도체 칩과 제2 반도체 칩을, 접착재를 개재하여 각각 적층하는 반도체 장치의 제조 방법으로서, 상대적으로 평면 사이즈가 작은 제1 반도체 칩 위에 상대적으로 평면 사이즈가 큰 제2 반도체 칩을 탑재한다. 또한, 제1 및 제2 반도체 칩을 탑재한 후, 제1 및 제2 반도체 칩을 수지로 밀봉한다. 여기서, 제2 반도체 칩과 배선 기판의 간극은, 수지로 밀봉하기 전에, 제1 및 제2 반도체 칩을 탑재할 때 사용한 접착재로 미리 막혀 있는 것이다.

Semiconductor package bonding head and bonding method

PACKAGE WITH ISOLATION STRUCTURE

Embodiments are provided herein for a packaged semiconductor device that includes a semiconductor die; a redistribution layer (RDL) structure on an active side of the semiconductor die, the RDL structure including a plurality of contact pads on an outer surface of the RDL structure; a plurality of external connections attached to the plurality of contact pads; and an isolation structure on the outer surface of the RDL structure around one or more contact pads of the plurality of contact pads, wherein a height of the isolation structure is at least two thirds of a height of the external connections.

Semiconductor package

A semiconductor package includes a substrate, a first semiconductor chip and a second semiconductor chip adjacent to each other on the substrate, and a plurality of bumps on lower surfaces of the first and second semiconductor chips. The first and second semiconductor chips have facing first side surfaces and second side surfaces opposite to the first side surfaces. The bumps are arranged at a higher density in first regions adjacent to the first side surfaces than in second regions adjacent to the second side surfaces.

DISPLAY DEVICE

A display device invention includes a substrate on which a plurality of light emitting elements are disposed. A plurality of lines are disposed on an upper surface of the substrate. A plurality of upper pads are disposed on the upper surface of the substrate and electrically connected to the plurality of lines. A plurality of link lines are disposed on a lower surface of the substrate. A plurality of lower pads are disposed on the lower surface of the substrate and electrically connected to the plurality of link lines. A plurality of side lines electrically connect the plurality of upper pads and the plurality of lower pads. The plurality of side lines include a plurality of first side lines and a plurality of second side lines, and the plurality of first side lines and the plurality of second side lines are disposed on different layers.

Bindungsverfahren für Wafer und Struktur der Bindungsstelle

An der Oberfläche von Wafer 1 wird eine Festklebeschicht 4 gebildet, auf diese Festklebeschicht 4 wird eine Diffusionsverhinderungsschicht 7 aus einem Material geschichtet, das von AuSn schlecht benetzbar ist. Vom Rand der Diffusionsverhinderungsschicht 7 nach innen versetzt wird an der Oberfläche der Diffusionsverhinderungsschicht 7 eine Klebeschicht 8 ausgebildet, und an der Oberfläche des Wafers 1 wird eine Bindungsstelle 3 ausgeformt. An der Unterseite von Wafer 11 ist eine Bindungsstelle 13 vorgesehen, unter der Bindungsstelle 13 ist eine AuSn Lötzinnschicht 19 vorgesehen. Wafer 1 und Wafer 11 werden einander gegenübergestellt, AuSn Lötzinn 19 wird geschmolzen, und Bindungsstelle 3 und Bindungsstelle 13 werden durch AuSn Lötzinn 22 eutektisch miteinander verbunden.

Silicon photonic interposer with two metal redistribution layers

A first metallic trace of a redistribution layer 105 is coated by a dielectric layer 110 with contact openings 120, 125 for contacting a further conductive trace 115 and a bond pad. A first metallic barrier layer 116 is used to form an under bump metallization layer of the bond pad and also a layer of a second conductive trace. The second conductive trace contacts the first conductive trace of the redistribution layer through a via hole 120 formed in the dielectric layer 110. The IC may be a photonic IC.

Scalable package architecture and associated techniques and configurations

CHIP PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME

Stacked semiconductor package and manufacturing method thereof

A stacked semiconductor package and a manufacturing method thereof. For example and without limitation, various aspects of this disclosure provide a semiconductor package in which an upper interposer and/or package are electrically and mechanically coupled to a lower package utilizing an adhesive member comprising conductive particles.

SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE SAME

A semiconductor device package includes a carrier provided with a first conductive element, a second conductive element arranged on a semiconductor disposed on the carrier, and a second semiconductor device disposed on and across the first conductive element and the first semiconductor device, wherein the first conductive element having a surface that is substantially coplanar with a surface of the second conductive element.

SEMICONDUCTOR DEVICE

The long sides of a rectangular control chip and the long sides of a rectangular memory chip are arranged parallel with first sides of the upper surface of a wiring substrate in a BGA. A lid includes a pair of first brims and a pair of second brims, the widths of the second brims are formed wider than those of the first brims, and a mounting area for mounting chip parts and a junction base area for joining the lid are secured outside the short sides of the control chip mounted on the upper surface of the wiring substrate and outside the short sides of the memory chip mounted on the upper surface of the wiring substrate, which enables the wide-width second brims of the lid to be disposed on the junction base area. Hence, the mounting area of the BGA can be reduced.

SOLDER PASTE

A solder paste includes a flux and powder mixed with the flux, where the powder includes first powder and second powder mixed with each other. The first powder may be a tin (Sn) and at least one metal dissolved in the tin (Sn), and the second powder may be a copper (Cu) powder, the surface of which is coated with silver (Ag).

SEMICONDUCTOR DEVICE AND DICING METHOD

According to an embodiment, a semiconductor device includes a silicon substrate, a semiconductor layer, and a lower layer. The semiconductor layer is formed on an upper surface of the silicon substrate. The lower layer is formed on a lower surface of the silicon substrate and has a side surface connecting to a side surface of the silicon substrate. At least a pair of side surfaces of the semiconductor device has a curved shape widening from an upper side toward a lower side.

Semiconductor device and dicing method

According to an embodiment, a semiconductor device includes a silicon substrate, a device layer, and a lower layer. The device layer is formed on an upper surface of the silicon substrate. The lower layer is formed on a lower surface of the silicon substrate and has a side surface connecting to a side surface of the silicon substrate. At least a pair of side surfaces of the semiconductor device has a curved shape widening from an upper side toward a lower side.

Chip package structure with dummy bump and method for forming the same

A method for forming a chip package structure is provided. The method includes bonding a chip to a first surface of a first substrate. The method includes forming a dummy bump over a second surface of the first substrate. The first surface is opposite the second surface, and the dummy bump is electrically insulated from the chip. The method includes cutting through the first substrate and the dummy bump to form a cut substrate and a cut dummy bump. The cut dummy bump is over a corner portion of the cut substrate, a first sidewall of the cut dummy bump is substantially coplanar with a second sidewall of the cut substrate, and a third sidewall of the cut dummy bump is substantially coplanar with a fourth sidewall of the cut substrate.

SEMICONDUCTOR PACKAGE

A semiconductor package includes a first semiconductor chip, a chip stack on the first semiconductor chip, and a mold layer enclosing the chip stack, on the first semiconductor chip. The chip stack includes second semiconductor chips vertically stacked on the first semiconductor chip, a third semiconductor chip on the second semiconductor chips, and non-conductive layers filling spaces between adjacent ones of the second semiconductor chips. The mold layer fills spaces between the first semiconductor chip and the chip stack, which are spaced apart from each other by a first distance, and between the uppermost one of the second semiconductor chips and the third semiconductor chip, which are spaced apart from each other by a second distance. The second semiconductor chips are spaced apart from each other by a third distance that is smaller than the first distance and the second distance.

SEMICONDUCTOR DEVICE

A semiconductor device includes a base member, a semiconductor chip, and a conductive member. The base member includes a first surface, a second surface opposite to the first surface, and a protrusion at the second surface side. The semiconductor chip is mounted on the second surface of the base member. The semiconductor chip includes first and second electrodes, a control pad, and a semiconductor part. The semiconductor part has front and back surfaces; the first electrode is provided on the back surface; and the second electrode and the control pad are provided on the front surface. The conductive member bonded on the second electrode via a connection member. The connection member includes a side surface extending along a space between the second electrode and the control pad. The protrusion of the base member overlaps the second connection member and extends along the side surface of the connection member.

METHOD FOR SIMULTANEOUSLY BONDING TO AND INSULATING A POWER ELECTRONIC SEMICONDUCTOR COMPONENT ON AN ORGANIC AND/OR CERAMIC SUBSTRATE, AND CORREPONDING COMPOSITE UNIT

Multi-chip package structure having chip interconnection bridge which provides power connections between chip and package substrate

Die with integrated microphone device using through-silicon vias (TSVs)

LEAD FRAME HAVING A PERIMETER RECESS WITHIN PERIPHERY OF COMPONENT TERMINAL

Embodiments described herein relate to a packaged circuit including a lead frame having at least one recess pattern on an internal surface thereof. The at least one recess pattern includes a perimeter recess that defines a perimeter around one or more raised surfaces. The packaged circuit also includes a component having one or more terminals. One of the terminals is mounted to the one or more raised surfaces such that the terminal covers the perimeter recess, wherein the perimeter recess has a size and shape such that the recess is proximate a perimeter of the terminal. The packaged circuit also includes component attach adhesive between the single terminal of the component and the one or more raised surfaces of the lead frame.

NANOPARTICLE BACKSIDE DIE ADHESION LAYER

In described examples, a microelectronic device includes a microelectronic die with a die attach surface. The microelectronic device further includes a nanoparticle layer coupled to the die attach surface. The nanoparticle layer may be in direct contact with the die attach surface, or may be coupled to the die attach surface through an intermediate layer, such as an adhesion layer or a contact metal layer. The nanoparticle layer includes nanoparticles having adjacent nanoparticles adhered to each other. The microelectronic die is attached to a package substrate by a die attach material. The die attach material extends into the nanoparticle layer and contacts at least a portion of the nanoparticles. 1. A microelectronic device , comprising:a microelectronic die having a die attach surface;a nanoparticle layer coupled to the die attach surface, the nanoparticle layer including nanoparticles, wherein adjacent nanoparticles are adhered to each other;a package substrate; anda layer of a die attach material connecting the nanoparticle layer to the package substrate, wherein the die attach material extends into the nanoparticle layer and contacts at least a portion of the nanoparticles.2. The microelectronic device of claim 1 , further comprising a metal layer between the die attach surface and the nanoparticle layer claim 1 , wherein the metal layer contacts the die attach surface and contacts at least a portion of the nanoparticles.3. The microelectronic device of claim 1 , wherein at least a portion of the nanoparticles are electrically conductive.4. The microelectronic device of claim 1 , wherein at least a portion of the nanoparticles are electrically insulating.5. The microelectronic device of claim 1 , wherein the die attach material includes an adhesive material.6. The microelectronic device of claim 1 , wherein the die attach material includes solder.7. The microelectronic device of claim 1 , wherein the nanoparticle layer is patterned.8. The microelectronic ...

LEADFRAME DIE PAD WITH PARTIALLY-ETCHED GROOVE BETWEEN THROUGH-HOLE SLOTS

A leadframe includes a die pad for mounting a semiconductor die with its top side facing up using a die attach resin material including a resin, the leadframe having leads or lead terminals beyond the die pad. The die pad includes slots including a first slot and at least a second slot on at least a first side of the die pad that penetrate a full thickness of the die pad. At least one non-penetrating groove is in the die pad for providing a fluid connection including between the first and second slots for providing a flow channel for guiding the resin when received by the grooves after bleeding out from under the semiconductor die to flow to at least one of the first slot and the second slot.

Submount for Electronic Die Attach with Controlled Voids and Methods of Attaching an Electronic Die to a Submount Including Engineered Voids

A packaged electronic device includes a submount, a bonding pattern on the submount, and an electronic chip on the bonding pattern. A periphery of the electronic chip defines a die mounting region of the submount. The bonding pattern includes a bonding area within the die mounting region and at least one channel that extends from within the die mounting region to a region of the submount outside the die mounting region.

PACKAGE STRUCTURE

A package structure comprising: a substrate, having at least one conductive units provided at a first surface of the substrate; at least one first die, provided on a second surface of the substrate; a connecting layer, provided on the first die; a second die, provided on the connecting layer, wherein the connecting layer comprises at least one bump for connecting the first die; and at least one bonding wire. The connecting layer has a first touch side and a second touch side, the first touch side contacts a first surface of the first die and the second touch side contacts a second surface of the second die, an area of the first touch side is smaller than which for the first surface of the first die, and a size of the first die equals to which of the second die.

SEMICONDUCTOR MODULE COMPRISING A SEMICONDUCTOR AND COMPRISING A SHAPED METAL BODY THAT IS ELECTRICALLY CONTACTED BY THE SEMICONDUCTOR

Semiconductor module including a semiconductor and including a shaped metal body that is electrically contacted by the semiconductor, for forming a contact surface for an electrical conductor, wherein the shaped metal body is bent or folded. A method is also described for establishing electrical contacting of an electrical conductor on a semiconductor, said method including the steps of: fastening a bent or folded shaped metal body of a constant thickness to the semiconductor by means of a first fastening method and then fastening the electrical conductor to the shaped metal body by means of a second fastening method. 1. A semiconductor module comprising a semiconductor and comprising a shaped metal body that is electrically contacted by the semiconductor , for forming a contact surface for an electrical conductor ,whereinthe shaped metal body is bent or folded.2. The semiconductor module according to claim 1 , wherein the shaped metal body is bent multiple times or folded multiple times.3. The semiconductor module according to claim 1 , wherein the shaped metal body is corrugated.4. The semiconductor module according to claim 1 , wherein the shaped metal body consists of aluminum (Al) or copper (Cu).5. The semiconductor module according to claim 1 , wherein the shaped metal body is connected to the semiconductor by means of sintering.6. The semiconductor module according to claim 1 , wherein the shaped metal body is connected to the semiconductor by means of adhesive bonding.7. The semiconductor module according to claim 1 , wherein the shaped metal body is connected to the semiconductor by means of soldering.8. The semiconductor module according to claim 1 , wherein the shaped metal body is connected to the semiconductor by means of nanowires.9. The semiconductor module according to claim 1 , wherein the electrical conductor is a lead frame or a ribbon.10. The semiconductor module according to claim 1 , wherein the semiconductor is produced from silicon carbide ( ...

Semiconductor device and manufacturing method of the same

A semiconductor device includes a die pad (6), an SiC chip (1) mounted on the die pad (6), a porous first sintered Ag layer (16) bonding the die pad (6) and the SiC chip (1), and a reinforcing resin portion (17) covering a surface of the first sintered Ag layer (16) and formed in a fillet shape. The semiconductor device further includes a source lead (9) electrically connected to a source electrode of the SiC chip (1), a gate lead electrically connected to a gate electrode, a drain lead electrically connected to a drain electrode, and a sealing body (14) which covers the SiC chip (1), the first sintered Ag layer (16), and a part of the die pad (6), and the reinforcing resin (17) portion covers a part of a side surface (1c) of the SiC chip (1).

Structure of embedded component and manufacturing method thereof

THERMOCOMPRESSION BOND TIPS AND RELATED APPARATUS AND METHODS

A bond tip for thermocompression bonding a bottom surface includes a die contact area and a low surface energy material covering at least a portion of the bottom surface. The low surface energy material may cover substantially all of the bottom surface, or only a peripheral portion surrounding the die contact area. The die contact area may be recessed with respect to the peripheral portion a depth at least as great as a thickness of a semiconductor die to be received in the recessed die contact area. A method of thermocompression bonding is also disclosed. 1. A thermocompression-bonding apparatus , comprising: a planar die-contact area, a length and a width of the planar die-contact area substantially corresponding to a length and a width of a semiconductor die to be received on the planar die-contact area;', 'a planar peripheral portion surrounding the planar die-contact area, the planar peripheral portion oriented parallel to the planar die-contact area; and', 'a low-surface-energy material secured to the planar peripheral portion of the bottom surface., 'a bond tip having a bottom surface, the bottom surface comprising2. The thermocompression-bonding apparatus of claim 1 , wherein the planar die-contact area is coplanar with the planar peripheral portion.3. The thermocompression-bonding apparatus of claim 1 , wherein the planar peripheral portion is contiguous with the planar die-contact area.4. The thermocompression-bonding apparatus of claim 1 , wherein a thickness of the low-surface-energy material has an inner boundary comprising sidewalls of the thickness of the low-surface-energy material.5. The thermocompression-bonding apparatus of claim 4 , wherein the sidewalls are located and configured to contact sides of a semiconductor die when the semiconductor die is received on the planar die-contact area.6. The thermocompression-bonding apparatus of claim 1 , wherein the planar peripheral portion is recessed relative to the planar die-contact area.7. The ...

Anisotropic conductive adhesive with reduced migration

Illustrative embodiments of an anisotropic conductive adhesive (ACA) configured to be cured after being subjected to a magnetic field are disclosed. In at least one illustrative embodiment, the ACA may comprise a binder and a plurality of particles suspended in the binder. Each of the plurality of particles may comprise a ferromagnetic material coated with a layer of electrically conductive material and with a moisture barrier, such that the electrically conducting material forms electrically conductive and isolated parallel paths when the ACA is cured after being subjected to the magnetic field.

Verbundbauteil sowie Verfahren zum Herstellen eines Verbundbauteils

Es wird ein Verbundbauteil aus einem ersten Fügepartner, einem zweiten Fügepartner und einer zwischen den beiden Fügepartnern angeordneten Fügeschicht vorgeschlagen. Die Fügeschicht und/oder der erste Fügepartner weist bzw. weisen dabei eine Struktur auf, mittels welcher eine Sollbruchstelle in den ersten Fügepartner zum Abbau mechanischer Spannungen vordefiniert wird. Des Weiteren wird ein Verfahren zur Herstellung eines Verbundbauteils sowie eine elektrische Schaltungsbaugruppe umfassend ein solches Verbundbauteil vorgeschlagen.

Method for connecting mating face of substrate, electronic portion and mating face of electronic portion for electronic component, involves forming film between mating face(s) and adhering mating face(s) with intermediate film

Method for connecting mating face of substrate, electronic portion and mating face of electronic portion involves forming a film containing conductive precious metal, semiprecious metal or precious metal alloy between mating face (a) and mating face (b) and adhering mating face (a,b) with an intermediate film. The film comprises a nanoporous structure. An independent claim is included for electronic component.

INTEGRIERTES SCHALTUNGSPACKAGE UND VERFAHREN

In einer Ausführungsform weist ein Package Folgendes auf: einen Interposer, der eine erste Seite aufweist; eine erste integrierte Schaltungsvorrichtung, die an der ersten Seite des Interposers angebracht ist; eine zweite integrierte Schaltungsvorrichtung, die an der ersten Seite des Interposers angebracht ist; eine Unterfüllung, die unter der ersten integrierten Schaltungsvorrichtung und der zweiten integrierten Schaltungsvorrichtung angeordnet ist; und ein Einkapselungsmittel, das um die erste integrierte Schaltungsvorrichtung und die zweite integrierte Schaltungsvorrichtung herum angeordnet ist, wobei sich ein erster Abschnitt des Einkapselungsmittels durch die Unterfüllung hindurch erstreckt, wobei der erste Abschnitt des Einkapselungsmittels physisch zwischen der ersten integrierten Schaltungsvorrichtung und der zweiten integrierten Schaltungsvorrichtung angeordnet ist, wobei der erste Abschnitt des Einkapselungsmittels planar mit Rändern der Unterfüllung und Rändern der ersten und ...

Die package component with jumper structure and manufacturing method thereof

The invention provides a die package component with jumper structure and manufacturing method thereof. The die package component with jumper structure includes a first lead frame, a second lead frame, a die, a jumper structure and a package body. The first lead frame has a die connection surface. The second lead frame is separated with the first lead frame. The second lead frame has a lead frame connection groove which defines a thermal deformation tolerance allowable route. The jumper structure is thermally deformed in a heat-changing environment. The jumper structure includes a die welding portion and a lead welding portion. The die welding portion is welded to the die. The lead welding portion is movable welded along to the thermal deformation tolerance allowable route to the lead frame connection groove when been thermally deformed.

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

A method for manufacturing a semiconductor device in which a first semiconductor chip and a second semiconductor chip having different planar sizes in planar view are stacked on a wiring board with adhesive interposed therebetween, the second semiconductor chip having a relatively larger planar size being mounted on the first semiconductor chip having a relatively smaller planar size. After the first and second semiconductor chips are mounted, the first and second semiconductor chips are sealed by a resin. The gap between the second semiconductor chip and the wiring board is blocked in advance, before the sealing by the resin is performed, by the adhesive used when the first and second semiconductor chips are mounted.

Method of manufacture of a semiconductor device

In order to prevent cracks from occurring at the corners of semiconductor dies after the semiconductor dies have been bonded to other substrates, an opening is formed adjacent to the corners of the semiconductor dies, and the openings are filled and overfilled with a buffer material that has physical properties that are between the physical properties of the semiconductor die and an underfill material that is placed adjacent to the buffer material.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A semiconductor device includes an insulated circuit board in which a metal layer is formed on one surface of an insulating board and a semiconductor element having a polygonal shape when viewed in a plan view that is bonded to the metal layer via a bonding material. The metal layer of the insulated circuit board has a recess that exposes the insulating board at a position corresponding to at least one corner of the semiconductor element.

Semiconductor device package and method of manufacturing the same

A semiconductor device package includes a substrate, a semiconductor device, and an underfill. The semiconductor device is disposed on the substrate. The semiconductor device includes a first lateral surface. The underfill is disposed between the substrate and the semiconductor device. The underfill includes a first lateral surface. The first lateral surface of the underfill and the first lateral surface of the semiconductor device are substantially coplanar.

SCALABLE PACKAGE ARCHITECTURE AND ASSOCIATED TECHNIQUES AND CONFIGURATIONS

Embodiments of the present disclosure describe scalable package architecture of an integrated circuit (IC) assembly and associated techniques and configurations. In one embodiment, an integrated circuit (IC) assembly includes a package substrate having a first side and a second side disposed opposite to the first side, a first die having an active side coupled with the first side of the package substrate and an inactive side disposed opposite to the active side, the first die having one or more through-silicon vias (TSVs) configured to route electrical signals between the first die and a second die, and a mold compound disposed on the first side of the package substrate, wherein the mold compound is in direct contact with a sidewall of the first die between the active side and the inactive side and wherein a distance between the first side and a terminating edge of the mold compound that is farthest from the first side is equal to or less than a distance between the inactive side of the ...

ELECTRONIC DEVICE COMPRISING AT LEAST A CHIP ENCLOSED IN A PACKAGE AND A CORRESPONDING ASSEMBLY PROCESS

An electronic device is described comprising at least one chip enclosed in a package, in turn provided with a metallic structure or leadframe having a plurality of connection pins, this chip having at least one first contact realized on a first face and at least one second contact realized on a second and opposite face of this chip. The chip comprises at least one through via crossing the whole section of the chip as well as a metallic layer extending from the second contact arranged on the first face, along walls of the at least one through via up to the second and opposite face in correspondence with an additional pad. The electronic device comprises at least one interconnection layer for the electrical and mechanical connection between the chip and the metallic structure having at least one portion realized in correspondence with the at least one through via so as to bring the second contact placed on the second face of the chip back on its first face. An assembly process of such an ...

Strain-Tolerant Die Attach with Improved Thermal Conductivity, and Method of Fabrication

A mechanically-stable and thermally-conductive interface device between a semiconductor die and a package for the die, and related method of fabrication, comprising: a semiconductor die; a package for the die; a surface area-enhancing pattern on the package and/or the die; and die attach materials between the die and the package, the die attach materials attaching the die to the package through an interface provided by the die attach materials; wherein: an effective bonding area between the die attach materials and the package and/or the die is greater with the pattern than without the pattern; and the increase of the effective bonding area simultaneously increases the surface area for thermal transport between the package and/or the die, and the die attach materials; and increases the surface area for stably attaching the at least one of the package and the die to the die attach materials.

SEMICONDUCTOR DEVICE PACKAGES AND METHODS OF MANUFACTURING THE SAME

A semiconductor device package includes a redistribution layer, a first semiconductor device, a second semiconductor device, a first insulation body, and a second insulation body. The first semiconductor device can be disposed on the redistribution layer. The second semiconductor device can be stacked on the first semiconductor device. The first insulation body can be disposed between the first semiconductor device and the second semiconductor device. The first insulation body may have a number of first particles. The second insulation body can encapsulate the first insulation body and have a number of second particles. One of the number of first particles can have a flat surface.

Package systems and manufacturing methods thereof

A package system includes a first substrate and a second substrate. The second substrate is electrically coupled with the first substrate. The second substrate includes at least one first opening. At least one electrical bonding material is disposed between the first substrate and the second substrate. A first portion of the at least one electrical bonding material is at least partially filled in the at least one first opening.

Package systems and manufacturing methods thereof

A package system includes a first substrate. A second substrate is electrically coupled with the first substrate. At least one electrical bonding material is disposed between the first substrate and the second substrate. The at least one electrical bonding material includes a eutectic bonding material. The eutectic bonding material includes a metallic material and a semiconductor material. The metallic material is disposed adjacent to a surface of the first substrate. The metallic material includes a first pad and at least one first guard ring around the first pad.

SCALABLE PACKAGE ARCHITECTURE AND ASSOCIATED TECHNIQUES AND CONFIGURATIONS

Embodiments of the present disclosure describe scalable package architecture of an integrated circuit (IC) assembly and associated techniques and configurations. In one embodiment, an integrated circuit (IC) assembly includes a package substrate having a first side and a second side disposed opposite to the first side, a first die having an active side coupled with the first side of the package substrate and an inactive side disposed opposite to the active side, the first die having one or more through-silicon vias (TSVs) configured to route electrical signals between the first die and a second die, and a mold compound disposed on the first side of the package substrate, wherein the mold compound is in direct contact with a sidewall of the first die between the active side and the inactive side and wherein a distance between the first side and a terminating edge of the mold compound that is farthest from the first side is equal to or less than a distance between the inactive side of the first die and the first side. Other embodiments may be described and/or claimed. 111-. (canceled)12. A method for fabricating an integrated circuit (IC) assembly , comprising:providing a package substrate having a first side and a second side disposed opposite to the first side;coupling an active side of a first die with the first side of the package substrate, the first die including an inactive side disposed opposite to the active side and one or more through-silicon vias (TSVs) configured to route electrical signals between the first die and a second die; andforming a mold compound on the first side of the package substrate, wherein the mold compound is in direct contact with a sidewall of the first die between the active side and the inactive side and wherein a distance between the first side and a terminating edge of the mold compound that is farthest from the first side is equal to or less than a distance between the inactive side of the first die and the first side;mounting ...

Die Attach Methods and Semiconductor Devices Manufactured based on Such Methods

A semiconductor device includes a carrier, a power semiconductor die that includes first and second opposite facing main surfaces, a side surface extending from the first main surface to the second main surface, and first and second electrodes disposed on the first and second main surfaces, respectively, a die attach material arranged between the carrier and the first electrode, wherein the die attach material forms a fillet at the side surface of the power semiconductor die, wherein a fillet height of the fillet is less than about 95% of a height of the power semiconductor die, wherein the height of the power semiconductor die is a length of the side surface, and wherein a maximum extension of the die attach material over edges of a main surface of the power semiconductor die facing the die attach material is less than about 200 micrometers. 1. A semiconductor device , comprising:a carrier;a power semiconductor die that comprises first and second opposite facing main surfaces, a side surface extending from the first main surface to the second main surface, and first and second electrodes disposed on the first and second main surfaces, respectively;a die attach material arranged between the carrier and the first electrode,wherein the die attach material forms a fillet at the side surface of the power semiconductor die,wherein a fillet height of the fillet is less than about 95% of a height of the power semiconductor die,wherein the height of the power semiconductor die is a length of the side surface, andwherein a maximum extension of the die attach material over edges of a main surface of the power semiconductor die facing the die attach material is less than about 200 micrometers.2. The semiconductor device of claim 1 , wherein the height of the power semiconductor die is less than about 400 micrometers.3. The semiconductor device of claim 2 , wherein the height of the power semiconductor die is less than about 150 micrometers.4. The semiconductor device of claim ...

ELECTRONIC DEVICE HAVING AN UNDER-FILL ELEMENT, A MOUNTING METHOD OF THE SAME, AND A METHOD OF MANUFACTURING A DISPLAY APPARATUS HAVING THE ELECTRONIC DEVICE

A mounting method of an electronic device includes providing an electronic device which includes a semiconductor chip body including an upper surface, a lower surface opposite to the upper surface, and side surfaces connecting the upper surface and the lower surface, a plurality of bumps disposed on the lower surface, and an under-fill element disposed on at least one side surface. The method further includes mounting the electronic device on a printed circuit board including connecting pads formed thereon. The bumps of the semiconductor chip body are connected to the connecting pads. The method additionally includes heating the under-fill element to a predetermined temperature to form an under-fill layer between the lower surface of the semiconductor chip body and the printed circuit board. 1. An electronic device , comprising:a semiconductor chip body including an upper surface, a lower surface opposite to the upper surface, and side surfaces connecting the upper surface and the lower surface;a plurality of bumps disposed on the lower surface of the semiconductor chip body; andan under-fill element disposed on at least one side surface.2. The electronic device of claim 1 , wherein a plurality of grooves is formed on at least one side surface claim 1 , andthe under-fill element is disposed in the plurality of grooves.3. The electronic device of claim 2 , wherein each groove of the plurality of grooves extends along the side surface and towards the lower surface of the semiconductor chip body claim 2 , and the under-fill element disposed in each groove of the plurality of grooves is exposed from the lower surface.4. The electronic device of claim 3 , wherein each groove of the plurality of grooves and the under-fill element have a semi-cylindrical shape or a triangular prism shape.5. The electronic device of claim 4 , wherein each groove of the plurality of grooves is disposed between two bumps adjacent to each other in a side surface view.6. The electronic device ...

Semiconductor packages having an electric device with a recess

Embodiments are directed to a package that includes an electric device having a recess. In one embodiment, the electric device is a sensor and the recess reduces signal drift of the sensor caused by thermal expansion of the package. In another embodiment, the recess is substantially filled with adhesive material, thus increasing adhesion between the electric device and a substrate of the package while at the same time allowing for lower adhesive fillets.

CHIP CARRIER AND METHOD THEREOF

A method may include providing a chip carrier having a chip supporting region to support a chip, and a chip contacting region having at least one contact pad, the chip carrier being thinner in the chip contacting region such that a first thickness of the chip carrier at the at least one contact pad is smaller than a second thickness of the chip carrier in the chip supporting region. A disposing of the chip, having at least one contact protrusion, over the chip carrier, such that the at least one contact protrusion is arranged over the at least one contact pad may be included. In addition, a pressing of the chip against the chip carrier such that the at least one contact protrusion extends at least partially into the chip contacting region and is electrically contacted to the at least one contact pad may be included. 1. A method , comprising: a chip supporting region configured to support a chip, and', 'a chip contacting region having at least one contact pad configured to electrically contact the chip,', 'the chip carrier being thinner in the chip contacting region such that a first thickness of the chip carrier at the at least one contact pad is smaller than a second thickness of the chip carrier in the chip supporting region;, 'providing a chip carrier, the chip carrier including'}disposing the chip including at least one contact protrusion over the chip carrier, such that the at least one contact protrusion is arranged over the at least one contact pad; andpressing the chip against the chip carrier such that the at least one contact protrusion extends at least partially into the chip contacting region and is electrically contacted to the at least one contact pad.2. The method of claim 1 ,wherein pressing the chip against the chip carrier includes displacing the at least one contact pad by deforming the chip carrier to form a recess for receiving the at least one contact protrusion.3. The method of claim 1 ,wherein pressing the chip against the chip carrier is ...

Coplanar microfluidic manipulation

An apparatus includes a polymer base layer having a surface. A die that includes a fluid manipulation surface that is substantially coplanar with the surface of the polymer base layer. The die includes a control electrode to generate an electric field to perform microfluidic manipulation of fluid across the fluid manipulation surface of the die.

Semiconductor package structure and manufacturing method thereof

A semiconductor package structure including a circuit substrate, a redistribution layer, and at least two dies is provided. The circuit substrate has a first surface and a second surface opposite the first surface. The redistribution layer is located on the first surface. The redistribution layer is electrically connected to the circuit substrate. The spacing of the opposing sidewalls of the redistribution layer is less than the spacing of the opposing sidewalls of the circuit substrate. The redistribution layer is directly in contact with the circuit substrate. At least two dies are disposed on the redistribution layer. Each of the at least two dies has an active surface facing the circuit substrate. One of the at least two dies is electrically connected to the other of the at least two dies by the redistribution layer. A manufacturing method of a semiconductor package structure is also provided.

Semiconductor device and manufacturing method thereof

A semiconductor device according to an embodiment includes a lead frame, a semiconductor chip provided above the lead frame, and a bonding material including a sintered material containing a predetermined metal material and a predetermined resin, where the bonding material includes a first portion provided between the lead frame and the semiconductor chip, and a second portion provided on the lead frame around the semiconductor chip, where the bonding material bonds the lead frame and the semiconductor chip, wherein an angle formed by a lower face of the semiconductor chip and an upper face of the second portion adjacent to the lower face is 80 degrees or less.

Preform structure for soldering a semiconductor chip arrangement, a method for forming a preform structure for a semiconductor chip arrangement, and a method for soldering a semiconductor chip arrangement

A preform structure for soldering a semiconductor chip arrangement includes a carbon fiber composite sheet and a solder layer formed over the carbon fiber composite sheet.

Semiconductor device package

A semiconductor device package includes a substrate, a first electronic component, a second electronic component, a heat dissipation lid and a thermal isolation. The substrate has a surface. The first electronic component and the second electronic component are over the surface of the substrate and arranged along a direction substantially parallel to the surface. The first electronic component and the second electronic component are separated by a space therebetween. The heat dissipation lid is over the first electronic component and the second electronic component. The heat dissipation lid defines one or more apertures at least over the space between the first electronic component and the second electronic component. The thermal isolation is in the one or more apertures of the heat dissipation lid.

Semiconductor package

A semiconductor package includes a first package substrate, a first semiconductor chip on the first package substrate, a plurality of first chip connection units to connect the first package substrate to the first semiconductor chip, an interposer on the first semiconductor chip, the interposer having a width greater than a width of the first semiconductor chip in a direction parallel to an upper surface of the first package substrate, and an upper filling layer including a center portion and an outer portion, the center portion being between the first semiconductor chip and the interposer, and the outer portion surrounding the center portion and having a thickness greater than a thickness of the center portion in a direction perpendicular to the upper surface of the first package substrate.

Method for producing structure, and structure

This method for producing a structure wherein base materials are bonded by atomic diffusion comprises: a step for applying a liquid resin on the base material; a step for smoothing the surface of the liquid resin by surface tension; a step for forming a resin layer by curing; a step for forming a metal thin film on the resin layer; a step for forming a metal thin film on the base material; and a step for bringing the metal thin film of the base material and the metal thin film of the base material into close contact with each other, thereby bonding the metal thin film of the resin layer and the metal thin film of the base material with each other by atomic diffusion

BONDED BODY AND METHOD FOR MANUFACTURING SAME

A bonded body is provided including: a bonding layer containing Cu; and a semiconductor element bonded to the bonding layer. The bonding layer includes an extending portion laterally extending from a peripheral edge of the semiconductor element. In a cross-sectional view in a thickness direction, the extending portion rises from a peripheral edge of a bottom of the semiconductor element or from the vicinity of the peripheral edge of the bottom of the semiconductor element, and includes a side wall substantially spaced apart from a side of the semiconductor element. Preferably, the extending portion does not include any portion where the side wall and the side of the semiconductor element are in contact with each other. A method for manufacturing a bonded body is also provided.

Semiconductor packaging structure

A semiconductor packaging structure including a circuit board, a chip, and a paste is provided. The circuit board includes a base layer, a first circuit layer, and a second circuit layer. The base layer has a first surface, a second surface opposite to the first surface, and a recess located on the first surface. The first circuit layer is located on the first surface. The second circuit layer is located on the second surface. The chip is disposed on the first surface and is electrically connected to first circuit layer, where the recess is located on at least one side of the chip. The paste is filled between the chip and the first surface and filled in the recess, where the paste covers a side surface of the chip.

Semiconductor package, method for forming semiconductor package, and method for forming semiconductor assembly

A semiconductor package includes a first package component include a first side, a second side opposite to the first side, and a plurality of recessed corners over the first side. The semiconductor package further includes a plurality of first stress buffer structures disposed at the recessed corners, and each of the first stress buffer structures has a curved surface. The semiconductor package further includes a second package component connected to the first package component and a plurality of connectors disposed between the first package component and the second package component. The connectors are electrically coupled the first package component and the second package component. The semiconductor package further includes an underfill material between the first package component and the second package component, and at least a portion of the curved surface of the first stress buffer structures is in contact with and embedded in the underfill material.

Semiconductor Package

A semiconductor device is disclosed. The semiconductor device comprises a redistribution structure, a processor die, and a metal post. The metal post has a first end, and a second end. The metal post is connected to the redistribution structure at the first end. The first end has a first width. The second end has a second width. The metal post has a waist width. The first width is greater than the waist width. The second width is greater than the waist width. The metal post has a side surface. The side surface is inwardly curved or outwardly curved. 1. An electronic device , comprising:a redistribution structure, the redistribution structure having a front surface and a back surface;a plurality of metal pillars;a processor die, the processor die having an active side and a back side, the active side of the the processor die being connected to the front surface of the redistribution structure through the plurality of metal pillars;a molding material;a set of conductive posts, the set of conductive posts being placed beside the processor die, the molding material surrounding the set of conductive posts, the set of conductive posts being connected to the front surface of the redistribution structure; andan adhesive layer, wherein the adhesive layer is located on the back side of the processor die, the processor die comprises a passivation layer on the active side, the electronic device comprises an insulating layer on the passivation layer of the processor die, a recess is formed between the redistribution structure and the processor die, there is a horizontal shift between a die edge of the processor die and an outer edge of the insulating layer, and the molding material fills the recess;wherein the electronic device further comprises a capacitor, a first set of solder bumps, and a second set of solder bumps, the capacitor being connected to the back surface of the redistribution structure, the capacitor being within a vertical projection of the processor die, the ...

Semiconductor package

A semiconductor package includes: a lower semiconductor chip including a first semiconductor substrate, which includes a first semiconductor device on an active surface thereof and a protrusion defined by a recess region on an inactive surface thereof opposite to the active surface, a plurality of external connecting pads on a bottom surface of the first semiconductor substrate, and a plurality of through-electrodes electrically connected to the plurality of external connecting pads; and at least one upper semiconductor chip stacked on the protrusion of the lower semiconductor chip and electrically connected to the plurality of through-electrodes, the at least one upper semiconductor chip including a second semiconductor substrate which includes a second semiconductor device on an active surface thereof.

Stack of electrical components and method of producing the same

A stack of electrical components has a first electrical component having a first surface, a second surface that is opposite to the first surface and a side surface that is located between the first surface and the second surface; a second electrical component having a third surface on which the first electrical component is mounted, the third surface facing the second surface and forming a corner portion between the third surface and the side surface; an adhesive layer that bonds the first electrical component to the second electrical component, wherein the adhesive layer has a first portion that is located between the second surface and the third surface and a curved second portion that fills the corner portion; and a conductive layer that extends on a side of the side surface, curves along the second portion and extends to the third surface.

COPPER NANOROD-BASED THERMAL INTERFACE MATERIAL (TIM)

A copper nanorod thermal interface material (TIM) is described. The copper nanorod TIM includes a plurality of copper nanorods having a first end thermally coupled with a first surface, and a second end extending toward a second surface. A plurality of copper nanorod branches are formed on the second end. The copper nanorod branches are metallurgically bonded to a second surface. The first surface may be the back side of a die. The second surface may be a heat spread or a second die. The TIM may include a matrix material surrounding the copper nanorods. In an embodiment, the copper nanorods are formed in clusters. 1. A microelectronic package , comprising:a substrate;a die electrically coupled with the substrate;an integrated heat spreader overlying the die; and a plurality of copper nanorods, each having a first end thermally coupled with the back surface of the die and a second end extending toward the integrated heat spreader; and', 'a plurality of copper nanorod branches extending from each second end, wherein the copper nanorod branches are metallurgically bonded to the integrated heat spreader., 'a thermal interface material thermally coupling the integrated heat spreader with a back surface of the die, wherein the TIM comprises2. The microelectronic package of claim 1 , wherein a bond line thickness (BLT) between the back surface of the die and the integrated heat spreader is less than 50 μm.3. The microelectronic package of claim 1 , wherein the copper nanorods have a diameter less than 20 μm.4. The microelectronic package of claim 1 , wherein the thermal interface material further comprises a matrix material between the back surface of the first die and the integrated heat spreader.5. The microelectronic package of claim 1 , further comprising a copper layer formed over the back surface of the die claim 1 , wherein the first ends are metallurgically bonded with the copper layer.6. The microelectronic package of claim 1 , wherein the nanorods are clustered ...

Semiconductor Package

A semiconductor device is disclosed. The semiconductor device comprises a redistribution structure, a processor die, and a metal post. The metal post has a first end, and a second end. The metal post is connected to the redistribution structure at the first end. The first end has a first width. The second end has a second width. The metal post has a waist width. The first width is greater than the waist width. The second width is greater than the waist width. The metal post has a side surface. The side surface is inwardly curved or outwardly curved. 1. An electronic device , comprising:a redistribution structure, the redistribution structure having a front surface and a back surface, the redistribution structure comprising a set of metal layers and a set of insulating layers, at least a middle metal layer of the set of metal layers comprising a plurality of holes, at least a subset of the holes forming a mesh type area, at least a width of one of the holes being greater than a width of an inner line of the mesh type area;a processor die, the processor die having an active side and a back side, the active side of the processor die being connected to the front surface of the redistribution structure, the processor die comprising a passivation layer on the active side, the electronic device comprising an insulating layer on the passivation layer of the processor die;a molding material;a set of conductive posts, the set of conductive posts being placed beside the processor die, the molding material surrounding the set of conductive posts, the set of conductive posts being connected to the front surface of the redistribution structure;a first set of solder bumps, the first set of solder bumps being connected to the set of conductive posts;a second set of solder bumps, the second set of solder bumps being connected to the back surface of the redistribution structure; andan underfill material, the underfill material surrounding the first set of solder bumps;wherein a ...

METHOD AND APPARATUS FOR CREATING A BOND BETWEEN OBJECTS BASED ON FORMATION OF INTER-DIFFUSION LAYERS

The present disclosure provides a method of creating a bond between a first object and a second object. For example, at least one insert may be provided at a location in a space formed between the first object and the second object. In additional, a filler material may be provided proximal to the location. An inter-diffusion layer may be formed, wherein a first portion of the inter-diffusion layer is formed by diffusion between the filler material and the at least one insert, wherein a second portion of the inter-diffusion layer is formed between the filler material and the first object, wherein a third portion of the inter-diffusion layer is formed between the filler material and the second object, wherein the first portion is coadunate with each of the second portion and third portion. 1. An electronic module comprising:a substrate;at least one chip; a first set of inserts placed inside a space between the substrate and the at least one chip,', "wherein diffusion of the second set of inserts occurs into at least one of the following: the substrate's mating surface, the at least one chip's mating surface and the first set of inserts;", 'a second set of inserts placed inside a space formed by the substrate, the at least one chip and the first set of inserts,'}], 'a plurality of inserts comprisinga gap between the first set of the inserts and the substrate; and 'wherein the diffusion results in formation of at least one of the following: a coadunate inter-diffusion layer along at least one insert of the first set of inserts to the at least one chip and a coadunate inter-diffusion layer along at least one insert of the first set of the inserts to the substrate.', 'a gap between the first set of inserts and the at least one chip,'}21. The electronic module of lain , wherein the at least one insert of the first set of inserts is comprised in at least one of the substrate's mating surface and the chip's mating surface.3. The electronic module of claim 1 , wherein the at ...

RADAR DEVICE

A radar device includes: a substrate including multiple high-frequency conductor layers arranged on a front surface; a semiconductor component in contact with the high-frequency conductor layers via conductive members; and an adhesive that bonds the semiconductor component to the front surface of the substrate. The semiconductor component has a bottom surface and a first side surface facing in a first direction. All the multiple high-frequency conductor layers include at least high-frequency conductor layers bending in a plane of the front surface and thereby extend, on the front surface, from inside ends facing the bottom surface to outside ends positioned in the first direction from the first side surface. The adhesive is in contact with the front surface except for the sites of the multiple high-frequency conductor layers formed and in contact with the side surfaces of the semiconductor component. 1. A radar device comprising:a substrate including a plurality of conductor layers arranged on a front surface or a rear surface, the conductor layers comprising a plurality of high-frequency conductor layers for transferring a high frequency signal;a semiconductor component facing the front surface of the substrate, being in contact with the plurality of conductor layers on the substrate via conductive members, and configured to generate a high frequency signal; andan adhesive configured to bond the semiconductor component to the front surface of the substrate, whereinthe semiconductor component has a bottom surface and a plurality of side surfaces including a first side surface facing in a first direction from a central portion to an edge in a plane of the front surface or the rear surface,all the plurality of high-frequency conductor layers or a high-frequency conductor layer set included in the plurality of high-frequency conductor layers includes at least high-frequency conductor layers that bend in the plane of the front surface or the rear surface and thereby ...

Semiconductor laser device

This semiconductor laser device comprises: a semiconductor laser element; a switching element connected in series to the semiconductor laser element, the switching element having a gate electrode, a drain electrode, and a source electrode; capacitors connected in parallel to the semiconductor laser element and the switching element; first drive electroconductive parts to which first terminals of the capacitors are connected; a second drive electroconductive part positioned apart from the first drive electroconductive parts; first drive connection members that connect the first drive electroconductive parts and the source electrode; and a second drive connection member that connects the second drive electroconductive part and the source electrode.

Solenoid inductors within a multi-chip package

An exemplary multi-chip package includes one or more solenoid inductors. An exemplary enclosing IC package includes one or more electrical interconnections propagating throughout which can be arranged to form a first solenoid inductor situated within the exemplary multi-chip package. Moreover, the exemplary enclosing IC package can be connected to an exemplary enclosed IC package to form the exemplary multi-chip package. The exemplary enclosed IC package can include a second solenoid inductor formed therein. Furthermore, the exemplary enclosing IC package can include a first portion of a third solenoid inductor and the exemplary enclosed IC package can include a second portion of the third solenoid inductor. The exemplary enclosed IC package can be connected to the exemplary enclosing IC package to connect the first portion of the third solenoid inductor and the second portion of the third solenoid inductor to form the third solenoid inductor.

Underfill material flow control for reduced die-to-die spacing in semiconductor packages

Underfill material flow control for reduced die-to-die spacing in semiconductor packages and the resulting semiconductor packages are described. In an example, a semiconductor apparatus includes first and second semiconductor dies, each having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a common semiconductor package substrate by a plurality of conductive contacts, the first and second semiconductor dies separated by a spacing. A barrier structure is disposed between the first semiconductor die and the common semiconductor package substrate and at least partially underneath the first semiconductor die. An underfill material layer is in contact with the second semiconductor die and with the barrier structure, but not in contact with the first semiconductor die.

Semiconductor device

A semiconductor device includes a lead frame, a semiconductor chip soldered to the lead frame, and a metal bar. The metal bar is arranged inside a solder layer so as to extend along one side of the semiconductor chip. When viewed in a stacking direction of the lead frame and the semiconductor chip, the metal bar is arranged so that a part of the metal bar overlaps the semiconductor chip, and the rest of the metal bar does not overlap the semiconductor chip. Then, in a section of the metal bar in a plane perpendicular to a longitudinal direction of the metal bar, an outline of the metal bar on a side of a center of the semiconductor chip is curved so as to project on the side of the center of the semiconductor chip.

Semiconductor device and method of manufacturing semiconductor device

The present technology relates to a semiconductor device and a method of manufacturing the semiconductor device capable of suppressing warpage of the semiconductor device. A mold release agent 101 is applied to a side surface of an upper chip 11 . According to this, when a sealing resin 31 for protecting a bump 21 is applied, the bump 21 between the upper chip 11 and a lower chip 12 is protected and a fillet-shaped protruding portion does not adhere to the side surface of the upper chip 11 due to the mold release agent 101 , so that a gap 111 is formed. According to this, a stress to warp the lower chip 12 is not generated even when contraction associated with drying of the sealing resin 31 between the side surface of the upper chip 11 and an upper surface of the lower chip 12 occurs, so that it becomes possible to suppress the warpage. The present technology may be applied to the semiconductor device.

Copper nanorod-based thermal interface material (tim)

A copper nanorod thermal interface material (TIM) is described. The copper nanorod TIM includes a plurality of copper nanorods having a first end thermally coupled with a first surface, and a second end extending toward a second surface. A plurality of copper nanorod branches are formed on the second end. The copper nanorod branches are metallurgically bonded to a second surface. The first surface may be the back side of a die. The second surface may be a heat spread or a second die. The TIM may include a matrix material surrounding the copper nanorods. In an embodiment, the copper nanorods are formed in clusters.

Electronic structure and electronic package component for increasing the bonding strength between inside and outside electrodes

An electronic structure includes a substrate body, an electronic package structure and a conductive unit. The electronic package structure is disposed on the substrate body. The electronic package structure includes a first inner electrode portion, a second inner electrode portion, a first outer electrode portion electrically connected to the first inner electrode portion, and a second outer electrode portion electrically connected to the second inner electrode portion. The conductive unit includes a first conductive body and a second conductive body respectively electrically contacting the first and the second outer electrode portions. The electronic package structure has a first notch and a second notch, the first outer electrode portion is extended into the first notch to contact the top surface of the first inner electrode portion, and the second outer electrode portion is extended into the second notch to contact the top surface of the second inner electrode portion.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME

A semiconductor device includes a semiconductor chip having a front surface electrode, a metal lead frame having a bed portion on a front surface of which the semiconductor chip is mounted and a post portion disposed separately from the bed portion, a resin sealing portion formed so as to cover the semiconductor chip, and a metal connector. The metal connector includes a chip junction portion joined to the front surface of the semiconductor chip, a post junction portion joined to a front surface of the post portion of the lead frame, and a connecting portion connecting the chip junction portion and the post junction portion. The chip junction portion has a thickness larger than a thickness of each of the post junction portion and the connecting portion. At least a part of the chip junction portion is exposed from a front surface of the sealing part. 1. A semiconductor device , comprising:a semiconductor chip including a front surface electrode;a metal lead frame including a bed portion, on a front surface of which the semiconductor chip is mounted, and a post portion disposed separately from the bed portion;a resin sealing portion formed so as to cover the semiconductor chip; anda metal connector including a chip junction portion joined to the front surface of the semiconductor chip, a post junction portion joined to a front surface of the post portion of the lead frame, and a connecting portion connecting the chip junction portion and the post junction portion, the chip junction portion has a thickness larger than a thickness of each of the post junction portion and the connecting portion, and', 'at least a part of the chip junction portion is exposed through a front surface of the sealing part., 'wherein'}2. The device according to claim 1 , whereina limited wetting portion preventing wetting of a melted bonding material is formed in a part of the outer periphery of a junction surface between the post portion of the lead frame and the post junction portion of the ...

Hybrid backside thermal structures for enhanced ic packages

An integrated circuit (IC) die structure comprises a substrate material comprising silicon. Integrated circuitry is over a first side of the substrate material. A composite layer is in direct contact with a second side of the substrate material. The second side is opposite the first side. The composite layer comprises a first constituent material associated with a first linear coefficient of thermal expansion (CTE), and a first thermal conductivity exceeding that of the substrate. The composite layer also comprises a second constituent material associated with a second CTE that is lower than the first, and a second thermal conductivity exceeding that of the substrate.

SEMICONDUCTOR PACKAGE

A semiconductor package includes a substrate, a first semiconductor chip and a second semiconductor chip adjacent to each other on the substrate, and a plurality of bumps on lower surfaces of the first and second semiconductor chips. The first and second semiconductor chips have facing first side surfaces and second side surfaces opposite to the first side surfaces. The bumps are arranged at a higher density in first regions adjacent to the first side surfaces than in second regions adjacent to the second side surfaces. 120.-. (canceled)21. A semiconductor package , comprising:a substrate;at least two semiconductor chips on the substrate;a plurality of bumps on lower surfaces of respective ones of the at least two semiconductor chips, the plurality of bumps being arranged at a higher density in adjacent regions of the at least two semiconductor chips than in other regions of the at least two semiconductor chips; andat least one insulating layer between the substrate and each of the at least two semiconductor chips to fill between the plurality of bumps, the at least one insulating layer having a volume in a region between the at least two semiconductor chips that is smaller than a volume in a region outside non-adjacent side surfaces of the at least two semiconductor chips.22. The semiconductor package as claimed in claim 21 , wherein the at least one insulating layer protrudes outward from the non-adjacent side surfaces of the at least two semiconductor chips farther than from adjacent side surfaces of the at least two semiconductor chips.23. The semiconductor package as claimed in claim 22 , wherein the at least one insulating layer protrudes from other side surfaces of the at least two semiconductor chips connecting respective ones of the adjacent side surfaces and the non-adjacent side surfaces claim 22 , anda protrusion distance from the other side surfaces of the at least two semiconductor chips is greater than a protursion distance from the adjacent side ...

ELECTRONIC DEVICE HAVING AN UNDER-FILL ELEMENT, A MOUNTING METHOD OF THE SAME, AND A METHOD OF MANUFACTURING A DISPLAY APPARATUS HAVING THE ELECTRONIC DEVICE

A mounting method of an electronic device includes providing an electronic device which includes a semiconductor chip body including an upper surface, a lower surface opposite to the upper surface, and side surfaces connecting the upper surface and the lower surface, a plurality of bumps disposed on the lower surface, and an under-fill element disposed on at least one side surface. The method further includes mounting the electronic device on a printed circuit board including connecting pads formed thereon. The bumps of the semiconductor chip body are connected to the connecting pads. The method additionally includes heating the under-fill element to a predetermined temperature to form an under-fill layer between the lower surface of the semiconductor chip body and the printed circuit board. 1. An electronic device , comprising:a semiconductor chip body including an upper surface, a lower surface opposite to the upper surface, and side surfaces connecting the upper surface and the lower surface;a plurality of bumps disposed on the lower surface of the semiconductor chip body; andan under-fill element disposed on at least one side surface.2. The electronic device of claim 1 , wherein a plurality of grooves is formed on at least one side surface claim 1 , andthe under-fill element is disposed in the plurality of grooves.3. The electronic device of claim 2 , wherein each groove of the plurality of grooves extends along the side surface and towards the lower surface of the semiconductor chip body claim 2 , and the under-fill element disposed in each groove of the plurality of grooves is exposed from the lower surface.4. The electronic device of claim 3 , wherein each groove of the plurality of grooves and the under-fill element have a semi-cylindrical shape or a triangular prism shape.5. The electronic device of claim 4 , wherein each groove of the plurality of grooves is disposed between two humps adjacent to each other in a side surface view.6. The electronic device ...

Lead frame for improving adhesive fillets on semiconductor die corners

The present disclosure is directed to a lead frame including a die pad with cavities, and methods for attaching a semiconductor die to the lead frame. The cavities allow for additional adhesive to be formed on the die pad at the corners of the semiconductor die, and prevent the additional adhesive from overflowing on to active areas of the semiconductor die.

NANOPARTICLE BACKSIDE DIE ADHESION LAYER

In described examples, a microelectronic device includes a microelectronic die with a die attach surface. The microelectronic device further includes a nanoparticle layer coupled to the die attach surface. The nanoparticle layer may be in direct contact with the die attach surface, or may be coupled to the die attach surface through an intermediate layer, such as an adhesion layer or a contact metal layer. The nanoparticle layer includes nanoparticles having adjacent nanoparticles adhered to each other. The microelectronic die is attached to a package substrate by a die attach material. The die attach material extends into the nanoparticle layer and contacts at least a portion of the nanoparticles. 1. A method of forming a microelectronic device , the method comprising:providing a microelectronic substrate having a die attach surface; andforming a nanoparticle layer coupled to and covering a plurality of areas of the die attach surface, the nanoparticle layer including nanoparticles, wherein adjacent nanoparticles are adhered to each other;providing a package substrate having a substrate interface surface coupled to the nanoparticle layer;forming a layer of die attach material connecting the nanoparticle layer to the package substrate at the substrate interface surface, wherein the die attach material extends into the nanoparticle layer and contacts at least a portion of the nanoparticles in an interlocking configuration.2. The method of claim 1 , in which there is a gap extending through the nanoparticle layer and the die attach layer claim 1 , the gap extending from the die attach surface to the substrate interface surface.3. The method of claim 1 , further comprising singulating microelectronic die after forming the nanoparticle layer.4. The method of claim 1 , further comprising forming an intermediate layer on the die attach surface claim 1 , wherein the nanoparticle layer is formed on the intermediate layer to contact the die attach surface and to contact at ...

Anisotropic Conductive Adhesive with Reduced Migration

Illustrative embodiments of an anisotropic conductive adhesive (ACA) configured to be cured after being subjected to a magnetic field are disclosed. In at least one illustrative embodiment, the ACA may comprise a binder and a plurality of particles suspended in the binder. Each of the plurality of particles may comprise a ferromagnetic material coated with a layer of electrically conductive material and with a moisture barrier, such that the electrically conducting material forms electrically conductive and isolated parallel paths when the ACA is cured after being subjected to the magnetic field.

Methods for establishing thermal joints between heat spreaders or lids and heat sources

According to various aspects, exemplary embodiments are disclosed of thermal interface materials, electronic devices, and methods for establishing thermal joints between heat spreaders or lids and heat sources. In exemplary embodiments, a method of establishing a thermal joint for conducting heat between a heat spreader and a heat source of an electronic device generally includes positioning a thermal interface material (TIM 1 ) between the heat spreader and the heat source.

Electronic component and method of manufacturing the same

An electronic component has a circuit board with a main surface, a chip having a sensor facing the main surface, bump electrodes disposed between the main surface and the chip so as to be placed inside of the edges of the chip in a plan view of the main surface, a dam provided between the main surface and the chip so as to extend at least from the edges of the chip to outer positions of the bump electrodes in a plan view of the main surface, and an under-fill material provided at least in a clearance between the dam and the chip. Between the main surface and the sensor, a space is formed in a region enclosed by the bump electrodes in a plan view of the main surface. The under-fill material is disposed outside of the space in a plan view of the main surface.

Lead frame for improving adhesive fillets on semiconductor die corners

The present disclosure is directed to a lead frame including a die pad with cavities, and methods for attaching a semiconductor die to the lead frame. The cavities allow for additional adhesive to be formed on the die pad at the corners of the semiconductor die, and prevent the additional adhesive from overflowing on to active areas of the semiconductor die.

Semiconductor package using cavity substrate and manufacturing methods

A semiconductor package includes a cavity substrate, a semiconductor die, and an encapsulant. The cavity substrate includes a redistribution structure and a cavity layer on an upper surface of the redistribution structure. The redistribution structure includes pads on the upper surface, a lower surface, and sidewalls adjacent the upper surface and the lower surface. The cavity layer includes an upper surface, a lower surface, sidewalls adjacent the upper surface and the lower surface, and a cavity that exposes pads of the redistribution structure. The semiconductor die is positioned in the cavity. The semiconductor die includes a first surface, a second surface, sidewalls adjacent the first surface and the second surface, and attachment structures that are operatively coupled to the exposed pads. The encapsulant encapsulates the semiconductor die in the cavity and covers sidewalls of the redistribution structure.

Semiconductor device

According to an embodiment, a semiconductor device includes a first metal plate, a second metal plate, and two or more semiconductor units. The two or more semiconductor units are disposed on the first metal plate. The each of the two or more semiconductor units includes a first metal member, a second metal member, and a semiconductor element. The first metal member has a first connection surface connected to the first major surface. The second metal member has a second connection surface connected to the second major surface. The semiconductor element includes an active region having surfaces respectively opposing the first connection surface and the second connection surface. A surface area of the first connection surface is greater than a surface area of the surface of the active region opposing the first connection surface. A surface area of the second connection surface is greater than a surface area of the surface of the active region opposing the second connection surface.

WAFER STACKING FOR INTEGRATED CIRCUIT MANUFACTURING

A method of manufacturing integrated devices, and a stacked integrated device are disclosed. In an embodiment, the method comprises providing a substrate; mounting at least a first electronic component on the substrate; positioning a handle wafer above the first electronic component; attaching the first electronic component to the substrate via electrical connectors between the first electronic component and the substrate; and while attaching the first electronic component to the substrate, using the handle wafer to apply pressure, toward the substrate, to the first electronic component, to manage planarity of the first electronic component during the attaching. In an embodiment, a joining process is used to attach the first electronic component to the substrate via the electrical connectors. For example, thermal compression bonding may be used to attach the first electronic component to the substrate via the electrical connectors. 1. A method of manufacturing integrated devices , comprising:providing a substrate;mounting at least a first flat electronic component on the substrate, the first electronic component having a thickness less than about 20 μm;positioning a handle wafer above the at least a first electronic component;attaching the at least a first electronic component to the substrate via electrical connectors between the at least a first electronic component and the substrate; andwhile attaching the at least a first electronic component to the substrate, using the handle wafer to apply a pressure, toward the substrate, to the at least a first electronic component, for co-planarity management to prevent the at least a first electronic component, having the thickness less than about 20 μm, from bending and to keep the first electronic component flat during said attaching the at least a first electronic component to the substrate.2. The method according to claim 1 , wherein the attaching the at least a first electronic component to the substrate includes ...

Display device

A display device includes: a display panel; a driver integrated circuit (IC) including a first surface electrically connected to the display panel and a second surface opposing the first surface and electrically connected to the first surface; and a connecting structure including a first side portion electrically connected to the second surface of the driver IC, and a second side portion electrically connected to an external device.

Semiconductor device

A semiconductor device capable of inhibiting oxidation of a Cu wiring even in a high temperature operation. The semiconductor device includes a semiconductor substrate having a main surface, a Cu electrode which is selectively formed on a side of the main surface of the semiconductor substrate, an antioxidant film formed on an upper surface of the Cu electrode except an end portion thereof, an organic resin film which is formed on the main surface of the semiconductor substrate and covers a side surface of the Cu electrode and the end portion of the upper surface thereof, and a diffusion prevention film formed between the organic resin film and the main surface of the semiconductor substrate and between the organic resin film and the side surface and the end portion of the upper surface of the Cu electrode, being in contact therewith.

METHOD OF FABRICATING PACKAGE STRUCTURE WITH AN EMBEDDED ELECTRONIC COMPONENT

The present invention provides a package structure with an embedded electronic component and a method of fabricating the package structure. The method includes: forming a first wiring layer on a carrier; removing the carrier and forming the first wiring layer on a bonding carrier; disposing an electronic component on the first wiring layer; forming an encapsulating layer, a second wiring layer and an insulating layer on the first wiring layer; disposing a chip on the electronic component and the second wiring layer; and forming a covering layer that covers the chip. The present invention can effectively reduce the thickness of the package structure and the electronic component without using adhesives. 1. A method of fabricating a package structure with an embedded component , comprising:forming on a bonding carrier, a first wiring layer having opposing first and second surfaces, and disposing an electronic component on the bonding carrier, wherein the second surface of the first wiring layer is coupled to the bonding carrier;forming on the first wiring layer an encapsulating layer that encapsulates the electronic component and is formed with at least a first hole for exposing a portion of the first surface of the first circuit therefrom; andforming a second wiring layer on the encapsulating layer, in a manner that a portion of the second wiring is filled into the at least a first hole, so as for the second wiring layer to be electrically connected with the first wiring layer.2. The method of claim 1 , further comprising forming on the encapsulating layer a first insulating layer formed with at least a third hole claim 1 , for exposing the portion of the second wiring layer exposed from the at least a first hole.3. The method of claim 2 , wherein an end of the at least a first hole is flush with an end of the third hole.4. The method of claim 1 , further comprising removing the bonding carrier.5. The method of claim 4 , further comprising claim 4 , after the second ...

Integrated Circuit Packaging Method Using Pre-Applied Attachment Medium

A method of making an IC package having a die and a substrate that are to be attached at an attachment station including providing the die and substrate and, at a location remote from the attachment station, coating at least one of the die and a die attachment portion of the substrate with attachment medium.

Thermocompression bond tips and related apparatus and methods

A bond tip for thermocompression bonding a bottom surface includes a die contact area and a low surface energy material covering at least a portion of the bottom surface. The low surface energy material may cover substantially all of the bottom surface, or only a peripheral portion surrounding the die contact area. The die contact area may be recessed with respect to the peripheral portion a depth at least as great as a thickness of a semiconductor die to be received in the recessed die contact area. A method of thermocompression bonding is also disclosed.

Quantum dot led package and quantum dot led module including the same

A quantum dot LED package is disclosed. The quantum dot LED package includes: a heat dissipating reflector having a through cavity; a quantum dot plate accommodated in the upper portion of the through cavity; an LED chip accommodated in the lower portion of the through cavity and whose top surface is coupled to the lower surface of the quantum dot plate; electrode pads disposed on the lower surface of the LED chip and protruding more downward than the lower surface of the heat dissipating reflector; and a resin part formed in the through cavity to fix between the LED chip and the reflector and between the quantum dot plate and the reflector.

SEMICONDUCTOR PACKAGE USING CAVITY SUBSTRATE AND MANUFACTURING METHODS

A semiconductor package includes a cavity substrate, a semiconductor die, and an encapsulant. The cavity substrate includes a redistribution structure and a cavity layer on an upper surface of the redistribution structure. The redistribution structure includes pads on the upper surface, a lower surface, and sidewalls adjacent the upper surface and the lower surface. The cavity layer includes an upper surface, a lower surface, sidewalls adjacent the upper surface and the lower surface, and a cavity that exposes pads of the redistribution structure. The semiconductor die is positioned in the cavity. The semiconductor die includes a first surface, a second surface, sidewalls adjacent the first surface and the second surface, and attachment structures that are operatively coupled to the exposed pads. The encapsulant encapsulates the semiconductor die in the cavity and covers sidewalls of the redistribution structure. 1. A semiconductor package , comprising: a redistribution structure comprising a redistribution structure upper surface having a plurality of pads, a redistribution structure lower surface opposite the redistribution structure upper surface, and one or more redistribution structure sidewalls adjacent the redistribution structure upper surface and the redistribution structure lower surface; and', 'a cavity layer on the redistribution structure upper surface, the cavity layer comprising a cavity layer upper surface, a cavity layer lower surface opposite the cavity layer upper surface, one or more cavity layer sidewalls adjacent the cavity layer upper surface and the cavity layer lower surface, and a cavity in the cavity layer upper surface that exposes one or more pads of the plurality of contacts pads;, 'a cavity substrate includinga semiconductor die in the cavity of the cavity layer, the semiconductor die comprising a semiconductor die first surface, a semiconductor die second surface opposite the semiconductor die first surface, one or more semiconductor ...

Semiconductor device

A semiconductor device has a resistance element including a metal block, a resin layer disposed on the metal block, and a resistance film disposed on the resin layer and an insulated circuit board including an insulating plate and a circuit pattern disposed on the insulating plate and having a bonding area on a front surface thereof to which a back surface of the metal block of the resistance element is bonded. The area of the circuit pattern is larger in plan view than that of a front surface of the resistance element. The metal block has a thickness greater than that of the circuit pattern in a direction orthogonal to the back surface of the metal block. As a result, the metal block properly conducts heat generated by the resistance film of the resistance element to the circuit pattern.

SEMICONDUCTOR PACKAGE INCLUDING NON-CONDUCTIVE FILM AND METHOD FOR FORMING THE SAME

A semiconductor package includes a semiconductor chip on a substrate. The semiconductor chip includes an active region, and a scribe lane in continuity with an edge of the active region. A non-conductive film (NCF) is between the substrate and the semiconductor chip, the non-conductive film (NCF) at least partially defines a recess region overlapping with the scribe lane in plan view and extending on the active region. 1. A semiconductor package , comprising:a substrate; an active region, and', 'a scribe lane in continuity with an edge of the active region; and, 'a semiconductor chip on the substrate, the semiconductor chip including'}a non-conductive film (NCF) between the substrate and the semiconductor chip, the non-conductive film (NCF) at least partially defining a recess region,wherein the recess region overlaps with the scribe lane in plan view, and extends on the active region.2. The semiconductor package according to claim 1 , wherein the recess region is at least partially defined by a side surface of the non-conductive film (NCF).3. The semiconductor package according to claim 1 , wherein the non-conductive film (NCF) covers the active region in plan view while extending on the scribe lane.4. The semiconductor package according to claim 1 , wherein the non-conductive film (NCF) has a smaller horizontal width than the semiconductor chip.5. The semiconductor package according to claim 1 , wherein an outermost side of the semiconductor chip is exposed from the non-conductive film (NCF) in plan view.6. The semiconductor package according to claim 1 , wherein a top surface adjacent to the semiconductor chip, and', 'a bottom surface adjacent to the substrate; and, 'the non-conductive film (NCF) comprises'}a horizontal width of the top surface is greater than a horizontal width of the bottom surface.7. The semiconductor package according to claim 1 , wherein a top surface of the semiconductor chip has a greater horizontal width than a bottom surface of the ...

Package on package and method for manufacturing the same

본 발명은 적층형 반도체 패키지 및 이의 제조 방법에 관한 것으로서, 더욱 상세하게는 도전성 입자를 갖는 접착부재를 이용하여 하부 반도체 패키지와 인터포저 간의 본드라인 증대 및 접합력 향상을 도모할 수 있도록 한 적층형 반도체 패키지 및 이의 제조 방법에 관한 것이다. 즉, 본 발명은 도전성 입자를 포함하는 접착부재를 이용하여 하부 반도체 패키지와 인터포저 간을 도전 가능하게 연결하는 동시에 상호 접착시킬 수 있도록 함으로써, 하부 반도체 패키지와 인터포저 간의 전기적 신호 전달이 용이하게 이루어짐은 물론 하부 반도체 패키지와 인터포저 간의 본드라인 증대 및 접합력 향상을 도모할 수 있도록 한 적층형 반도체 패키지 및 이의 제조 방법을 제공하고자 한 것이다. The present invention relates to a stacked semiconductor package and a method of manufacturing the same, and more particularly, to a stacked semiconductor package and a stacked semiconductor package, which can increase the bond line and improve the bonding strength between the lower semiconductor package and the interposer by using an adhesive member having conductive particles. And a method for producing the same. That is, according to the present invention, the lower semiconductor package and the interposer can be electrically connected and bonded to each other by using the adhesive member including the conductive particles, so that the electrical signal transmission between the lower semiconductor package and the interposer is facilitated Layer semiconductor package and a method of manufacturing the same, which can increase the bond line and improve the bonding force between the lower semiconductor package and the interposer.

Semiconductor device and method of manufacturing a semiconductor device

FIELD: physics.SUBSTANCE: method of manufacturing a semiconductor device includes applying a conductive paste containing metal particles to a predetermined area in an electrode plate including a notch on the surface of the electrode plate, wherein the predetermined area is adjacent to the notch, placing the semiconductor chip on the conductive paste so that the outer peripheral edge of the semiconductor chip is located above the notch, placing the mandrel in a position above the notch and near the outer peripheral edge of the semiconductor chip to provide a gap between the mandrel and the outer peripheral part of the electrode plate, which is a part located further in the outer peripheral side than the notch, and solidifying the conductive paste by heating the conductive paste when pressure is applied to the semiconductor chip in the direction of the electrode plate.EFFECT: invention provides a reduction in thermal voltage acting near the outer peripheral edge of a semiconductor chip.1 cl, 9 dwg РОССИЙСКАЯ ФЕДЕРАЦИЯ (19) RU (11) (13) 2 678 509 C1 (51) МПК H01L 21/58 (2006.01) ФЕДЕРАЛЬНАЯ СЛУЖБА ПО ИНТЕЛЛЕКТУАЛЬНОЙ СОБСТВЕННОСТИ (12) ОПИСАНИЕ ИЗОБРЕТЕНИЯ К ПАТЕНТУ (52) СПК H01L 21/4875 (2018.08); H01L 23/492 (2018.08); H01L 24/29 (2018.08); H01L 24/32 (2018.08) (21)(22) Заявка: 2017145049, 21.12.2017 (24) Дата начала отсчета срока действия патента: (73) Патентообладатель(и): ТОЙОТА ДЗИДОСЯ КАБУСИКИ КАЙСЯ (JP) Дата регистрации: 29.01.2019 2014029897 A, 13.02.2014. US 20100025847 A1, 04.02.2010. JP 2015153966 A, 24.08.2015. WO 2015/060346 A1, 30.04.2015. RU 2013116743 A, 20.04.2014. 10.01.2017 JP 2017-001924 (45) Опубликовано: 29.01.2019 Бюл. № 4 2 6 7 8 5 0 9 R U (54) ПОЛУПРОВОДНИКОВОЕ УСТРОЙСТВО И СПОСОБ ИЗГОТОВЛЕНИЯ ПОЛУПРОВОДНИКОВОГО УСТРОЙСТВА (57) Реферат: Способ изготовления полупроводникового полупроводниковой микросхемы с обеспечением устройства включает в себя нанесение зазора между оправкой и внешней периферийной проводящей пасты, содержащей металлические ...

Semiconductor package

본 발명의 실시예에 따른 반도체 패키지는, 기판, 기판 상에 서로 인접하게 배치되며, 서로 마주하는 측면인 제1 면 및 제1 면에 대향하는 제2 면을 각각 갖는 제1 반도체 칩 및 제2 반도체 칩, 제1 반도체 칩 및 제2 반도체 칩의 하면에 배치되며, 제1 면에 인접한 제1 영역들에서, 제2 면에 인접한 제2 영역들에서보다 높은 밀도로 배열되는 복수의 범프들을 포함한다. A semiconductor package according to an embodiment of the present invention includes a substrate, a first semiconductor chip disposed adjacent to each other on the substrate, and a first semiconductor chip and a second surface each having a first surface that is opposite to each other and a second surface that is opposite to the first surface a plurality of bumps disposed on lower surfaces of the semiconductor chip, the first semiconductor chip, and the second semiconductor chip, the bumps being arranged at a higher density in first regions adjacent to the first surface than in second regions adjacent to the second surface; do.

Semiconductor device

고체 장치(2,22)와, 기능 소자(4)가 형성된 기능면(3a)을 갖고, 그 기능면을 상기 고체 장치의 표면에 대향시키고, 상기 고체 장치의 표면과의 사이에 소정 간격을 유지하여 접합된 반도체 칩(3)과, 상기 고체 장치의 상기 반도체 칩과의 대향면(2a, 22a)에 설치되고, 그 대향면을 수직으로 내려다 보는 평면시에 있어서, 상기 반도체 칩보다 큰 사이즈로 형성된 개구(6a)를 갖는 절연막(6)과, 상기 고체 장치와 상기 반도체 칩과의 사이를 봉지하는 봉지층(7)을 포함하는 반도체 장치(1, 21)이다. It has a solid apparatus 2 and 22, and the functional surface 3a in which the functional element 4 was formed, opposes the functional surface to the surface of the said solid apparatus, and maintains a predetermined space | interval with the surface of the said solid apparatus. Formed on the opposing faces 2a, 22a of the semiconductor chip 3 bonded to each other and the semiconductor chip of the solid apparatus, and having a size larger than that of the semiconductor chip in a plan view overlooking the opposing face vertically. Semiconductor devices 1 and 21 including an insulating film 6 having openings 6a formed therein, and an encapsulation layer 7 sealing between the solid device and the semiconductor chip.

Display device

표시 장치는 표시 패널, 구동 집적 회로 및 연결 구조를 포함할 수 있다. 상기 구동 집적 회로의 제1 면이 상기 표시 패널에 전기적으로 연결될 수 있다. 상기 연결 구조의 제1 측부는 상기 구동 집적 회로의 제1 면에 대향하는 제2 면에 전기적으로 연결될 수 있고, 상기 연결 구조의 제2 측부가 외부 장치와 전기적으로 연결될 수 있다. 상기 제1 면은 상기 제2 면과 전기적으로 연결될 수 있다. The display device may include a display panel, a driving integrated circuit, and a connection structure. A first surface of the driving integrated circuit may be electrically connected to the display panel. A first side of the connection structure may be electrically connected to a second surface opposite to the first surface of the driving integrated circuit, and a second side of the connection structure may be electrically connected to an external device. The first surface may be electrically connected to the second surface.

Semiconductor package

적층된 반도체 칩의 변형을 방지하고 반도체 패키지의 부피를 최소화할 수 있는 반도체 패키지를 제공한다. 본 발명에 따른 반도체 패키지는 패키지 베이스 기판, 베이스 칩 상에 적층되는 하부 칩, 하부 칩 상에 적층되는 상부 칩 및 상부 칩의 하면에 접착되고 하부 칩의 적어도 일부분을 감싸는 제1 다이 접착 필름을 포함하되, 제1 다이 접착 필름은 상부 칩의 하면에 접하는 제1 접착층과 제1 접착층 하부에 접착되어 하부 칩의 측면의 적어도 일부분을 감싸는 제2 접착층을 포함하는 다중 필름이다. It provides a semiconductor package that can prevent deformation of the stacked semiconductor chip and minimize the volume of the semiconductor package. The semiconductor package according to the present invention includes a package base substrate, a lower chip stacked on the base chip, an upper chip stacked on the lower chip, and a first die adhesive film bonded to the lower surface of the upper chip and surrounding at least a portion of the lower chip However, the first die adhesive film is a multi-film including a first adhesive layer contacting a lower surface of the upper chip and a second adhesive layer bonded to a lower portion of the first adhesive layer and surrounding at least a portion of the side surface of the lower chip.

Semiconductor packages

本发明提供一种半导体封装，包括第一芯片、绝缘保护层、第二芯片、多个第二导电凸块及底填胶。绝缘保护层配置于第一芯片的第一主动面上，绝缘保护层包括一凹槽。第一芯片的第一内接点在绝缘保护层上的投影位于凹槽的范围内，第一芯片的第一外接点在绝缘保护层上的投影位于凹槽的范围外。第二芯片配置于绝缘保护层的凹槽上且具有多个第二接点。各第一内接点分别通过对应的第二导电凸块与对应的第二接点电性连接。底填胶位在绝缘保护层的凹槽与第二芯片之间，底填胶包覆这些第二导电凸块。本发明可降低底填胶外溢到焊球接垫或焊球的机率。

Semiconductor devices and manufacturing method

为了防止在半导体管芯接合至其它衬底之后在半导体管芯的拐角处出现裂缝，邻近半导体管芯的拐角形成开口，并且用缓冲材料填充和过填充开口，其中，缓冲材料的物理特性介于半导体管芯和邻近缓冲材料放置的底部填充材料的物理特性之间。本发明实施例涉及一种半导体器件和制造方法。

UNDERFILL MATERIAL, UNDERFILL FILM, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME

Semiconductor package including molding layer

一种半导体封装件包括：第一半导体芯片，其具有安装区域和外伸区域；基板，其设置在第一半导体芯片的安装区域处的底表面上；以及模制层，其设置在基板上。模制层包括：第一模制图案，其设置在第一半导体芯片的外伸区域处的底表面上并且覆盖基板的侧壁；以及第二模制图案，其在第一模制图案上并且覆盖第一半导体芯片的侧壁。

Packaging heat dissipation

在实例中，一种半导体封装(200)包括：衬底(202)，其包含导电层(232)；导电柱(233)，其耦合到所述导电层；及半导体裸片(150)，其具有第一及第二相对表面。所述第一表面耦合到所述导电柱。所述封装还包含邻接所述半导体裸片的所述第二表面的裸片贴装膜(152)及邻接所述裸片贴装膜且具有背向所述裸片贴装膜的金属层表面的金属层(154)。所述金属层表面暴露于所述封装的外部。所述封装包含覆盖所述衬底的模制化合物层(203)。

Methods for establishing thermal joints between heat spreaders or lids and heat sources

According to various aspects, exemplary embodiments are disclosed of thermal interface materials, electronic devices, and methods for establishing thermal joints between heat spreaders or lids and heat sources. In exemplary embodiments, a method of establishing a thermal joint for conducting heat between a heat spreader and a heat source of an electronic device generally includes positioning a thermal interface material (TIM1) between the heat spreader and the heat source.

Bonding equipment and bonding method

Method for fabricating semiconductor package and semiconductor package using the same

One embodiment of the present invention provides a method for fabricating a semiconductor package capable of forming a thin semiconductor package, and a semiconductor package using the same. To this end, one embodiment of the present invention discloses the method including the following steps of: (A) forming an interposer on a wafer; (B) forming at least one conductive pad and at least one post on the interposer; (C) placing at least one semiconductor die on the interposer to be electrically connected with the conductive pad; (D) forming a cover layer on the exterior surface of the semiconductor die and the post; (E) encapsulating the post and the semiconductor die together on the interposer with an encapsulant; and (F) exposing the post to the exterior of the cover layer.

Semiconductor package and method of manufacturing semiconductor package

A semiconductor package includes a package substrate, an interposer provided on the package substrate, a plurality of semiconductor devices on the interposer to be spaced apart from each other, the semiconductor devices being electrically connected to the package substrate through the interposer, and a molding layer on the interposer covering the semiconductor devices and exposing upper surfaces of the semiconductor devices, the molding layer including at least one groove extending in one direction between the semiconductor devices, the groove having a predetermined depth from an upper surface of the molding layer.

Semiconductor package manufacturing method

Semiconductor devices

揭示一种半导体器件。所述半导体器件包括重分布结构、处理器芯片和金属柱。所述金属柱具有第一端和第二端。所述金属柱的第一端连接到所述重分布结构。所述第一端具有第一宽度。所述第二端具有第二宽度。所述金属柱具有腰部宽度。所述第一宽度大于所述腰部宽度。所述第二宽度大于所述腰部宽度。所述金属柱具有一侧表面。所述侧表面向内弯曲或向外弯曲。

Method for manufacturing semiconductor device

In a method of manufacturing a semiconductor device obtained by laminating a first semiconductor chip and a second semiconductor chip with different planar sizes when seen in a plan view on a wiring board via an adhesive material, the second semiconductor chip with a relatively larger planar size is mounted on the first semiconductor chip with a relatively smaller planar size. Also, after the first and second semiconductor chips are mounted, the first and second semiconductor chips are sealed with resin. Here, before sealing with the resin, a gap between the second semiconductor chip and the wiring board is previously sealed with the adhesive material used when the first and second semiconductor chips are mounted.

Semiconductor package

A semiconductor package includes a substrate, a first semiconductor chip and a second semiconductor chip adjacent to each other on the substrate, and a plurality of bumps on lower surfaces of the first and second semiconductor chips. The first and second semiconductor chips have facing first side surfaces and second side surfaces opposite to the first side surfaces. The bumps are arranged at a higher density in first regions adjacent to the first side surfaces than in second regions adjacent to the second side surfaces.

Die with integrated microphone device using through silicon via (TSV)

Electronic device and method for manufacturing electronic device

An electronic device which can suppress peeling off and damaging of the bonding material is provided. The electronic device includes an electronic component, a mounting portion, and a bonding material. The electronic component has an element front surface and an element back surface separated in the z-direction. The mounting portion has a mounting surface opposed to the element back surface on which the electronic component is mounted. The bonding material bonds the electronic component to the mounting portion. The bonding material includes a base portion and a fillet portion. The base portion is held between the electronic component and the mounting portion in the z-direction. The fillet portion is connected to the base portion and is formed outside the electronic component when seen in the z-direction. The electronic component includes two element lateral surface and ridges. The ridges are intersections of the two element lateral surface and extend in the z-direction. The fillet portion includes a ridge cover portion which covers at least a part of the ridges.

Package systems having a eutectic bonding material and manufacturing methods thereof

A package system includes a first substrate. A second substrate is electrically coupled with the first substrate. At least one electrical bonding material is disposed between the first substrate and the second substrate. The at least one electrical bonding material includes a eutectic bonding material. The eutectic bonding material includes a metallic material and a semiconductor material. The metallic material is disposed adjacent to a surface of the first substrate. The metallic material includes a first pad and at least one first guard ring around the first pad.

Semiconductor device and method for forming the same

A method for forming a semiconductor device is provided. The method includes providing a substrate. The method includes forming a mask layer over a surface of the substrate. The mask layer has an opening over a portion of the surface. The method includes depositing a conductive layer over the surface and the mask layer. The method includes removing the mask layer and the conductive layer over the mask layer. The conductive layer remaining after the removal of the mask layer and the conductive layer over the mask layer forms a conductive pad. The method includes bonding a device to the conductive pad through a solder layer. The conductive pad is embedded in the solder layer.

Scalable encapsulation architecture and the relevant technologies and configuration

本公开的实施例描述了集成电路(IC)组件的可缩放封装架构及相关技术和配置。在一个实施例中，集成电路(IC)组件包括具有第一侧以及与第一侧相对设置的第二侧的封装衬底，具有与封装衬底的第一侧耦合的有源侧和与有源侧相对设置的非有源侧的第一管芯，第一管芯具有被配置为在第一管芯和第二管芯之间路由电信号的一个或多个穿硅通孔(TSV)，以及被置于封装衬底的第一侧上的模塑复合物，其中模塑复合物在有源侧和非有源侧之间与第一管芯的侧壁直接接触，而其中第一侧和距离第一侧最远的模塑复合物的终端边缘之间的距离等于或小于第一管芯的非有源侧和第一侧之间的距离。其他实施例可被描述和/或要求保护。

Solder paste

실시 예는 플럭스 및 상기 플러스와 혼합되고, 제1 분말과 제2 분말을 포함하는 혼합 분말을 포함하며, 상기 제1 분말은 주석(Sn), 및 상기 주석(Sn)에 고용되는 적어도 하나의 금속 원소를 포함하고, 상기 제2 분말은 표면에 은(Ag)이 코팅된 구리(Cu) 분말이다.

Semiconductor device

According to an embodiment, a semiconductor device includes a first metal plate, a second metal plate, and two or more semiconductor units. The two or more semiconductor units are disposed on the first metal plate. The each of the two or more semiconductor units includes a first metal member, a second metal member, and a semiconductor element. The first metal member has a first connection surface connected to the first major surface. The second metal member has a second connection surface connected to the second major surface. The semiconductor element includes an active region having surfaces respectively opposing the first connection surface and the second connection surface. A surface area of the first connection surface is greater than a surface area of the surface of the active region opposing the first connection surface. A surface area of the second connection surface is greater than a surface area of the surface of the active region opposing the second connection surface.

Electronic device and method for manufacturing electronic device

提供一种能够抑制接合件的剥离、损坏的电子器件。该电子器件包括电子部件、装载部和接合件。所述电子部件具有在z方向上隔开间隔的元件主面和元件背面。所述装载部具有与所述元件背面相对的装载面，装载所述电子部件。所述接合件将所述电子部件接合于所述装载部。所述接合件包括基部和凸缘部。所述基部在z方向上被所述电子部件和所述装载部夹着。所述凸缘部与所述基部相连，并且在z方向上观察时形成于所述电子部件的外侧。所述电子部件包含2个元件侧面和棱。所述棱是所述2个元件侧面的交叉部分，在z方向延伸。所述凸缘部包括覆盖所述棱的至少一部分的棱覆盖部。

Electronic device, manufacturing method thereof, and camera

Method for manufacturing semiconductor package

The present invention relates to a method for manufacturing a semiconductor package, which performs vacuum lamination on a substrate, provided with a plurality of through-silicon vias and having a bump electrode formed thereon, by using a non-conductive film and then performs ultraviolet irradiation, thereby being capable of adjusting an increase in melt viscosity before and after photo-curing to be 30% or less. Accordingly, during thermocompression bonding, it is possible to perform bonding without a void, prevent a phenomenon where resin is stuck in the middle of a solder, and improve reliability by minimizing a fillet.

Scalable package architecture and associated techniques and configurations

Embodiments of the present disclosure describe scalable package architecture of an integrated circuit (IC) assembly and associated techniques and configurations. In one embodiment, an integrated circuit (IC) assembly includes a package substrate having a first side and a second side disposed opposite to the first side, a first die having an active side coupled with the first side of the package substrate and an inactive side disposed opposite to the active side, the first die having one or more through-silicon vias (TSVs) configured to route electrical signals between the first die and a second die, and a mold compound disposed on the first side of the package substrate, wherein the mold compound is in direct contact with a sidewall of the first die between the active side and the inactive side and wherein a distance between the first side and a terminating edge of the mold compound that is farthest from the first side is equal to or less than a distance between the inactive side of the first die and the first side. Other embodiments may be described and/or claimed.

Fine-pitch metal bump and reinforcing structure of semiconductor packaging substrate

本发明描述了半导体封装基板和处理顺序。在实施方案中，封装基板包括堆积结构和图案化金属接触层，该图案化金属接触层部分地嵌入该堆积结构内并从该堆积结构突出。该图案化金属接触层可包括位于芯片安装区域中的表面安装(SMT)金属凸块阵列、金属围堤结构或它们的组合。

Method for flip-chip bonding using anisotropic adhesive polymer

The present invention discloses flip-chip bonding method using an anisotropic adhesive polymer. The method includes applying an adhesive polymer solution containing metal particles dispersed therein onto a circuit substrate to form an adhesive polymer layer such that the adhesive polymer layer covers the metal particles; drying the adhesive polymer layer; and positioning an electronic element to be electrically connected to the circuit substrate on the dried adhesive polymer layer and causing dewetting of the polymer from the metal particles.

Micro LED display and manufacturing method with conductive film

A micro LED display manufacturing method according to various embodiments may include: a first operation of bonding an anisotropic conductive film including a plurality of conductive particles onto one surface of a prepared substrate, the one surface including a circuit part; a second operation of forming a bonding layer on the anisotropic conductive film; a third operation of positioning a plurality of micro LED chips above the bonding layer, the micro LED chips being arranged on a carrier substrate while being spaced a first distance apart from the substrate; a fourth operation of attaching the plurality of micro LED chips onto the bonding layer by means of laser transfer; and a fifth operation of forming a conductive structure for electrically connecting a connection pad to the circuit part through the conductive particles by means of heating and pressurizing.