Integrated circuit astable trigger stage - has two parallel sets of leakage compensating IGFETs in gate circuit of supply transistor
Номер патента: DE3027456A1
Опубликовано: 04-02-1982
Автор(ы): Joachim Dipl.-Phys. Kuhlmann, Karl Ing.(grad.) 7100 Heilbronn Schoppe
Принадлежит: Licentia Patent Verwaltungs GmbH
Опубликовано: 04-02-1982
Автор(ы): Joachim Dipl.-Phys. Kuhlmann, Karl Ing.(grad.) 7100 Heilbronn Schoppe
Принадлежит: Licentia Patent Verwaltungs GmbH
Реферат: The integrated circuit for an astable trigger circuit with a frequency independent of manufacturing leakages includes an insulated gate-FET (TD10) in series with parallel sets of IG-FET's (TD11,TD12) across the supply connections (UDD,USS). They are connected to the gate electrode of the supply transistor (Td7). The two sets of transistors (TD11,12) compensate for channel width faults and also fluctuations of the supply transistor. This transistor operates to charge the two capacitors (C1,C2) of the cross coupled enhancement transistors (TE2,4) for the astable trigger stage. These have load resistances formed by depletion transistors (TD1,3) with short circuit source/gate paths.
Semiconductor integrated circuit device capable of compensating for current leakage and method of operating the same
Номер патента: US11868153B2. Автор: Chang Ki Baek,Min Wook Oh. Владелец: SK hynix Inc. Дата публикации: 2024-01-09.