Scannable flip flop circuit and method of operating an integrated circuit
Номер патента: WO2000072444A9
Опубликовано: 26-07-2001
Автор(ы): Joseph A Hoffman, Joseph W Yoder
Принадлежит: Lockheed Corp
Опубликовано: 26-07-2001
Автор(ы): Joseph A Hoffman, Joseph W Yoder
Принадлежит: Lockheed Corp
Реферат: A scannable flip flop for space-based LSSD testable integrated circuits. A scannable register can be formed from the scannable flip flops. The scannable flip flops can be radiation hardened. Each scannable flip flop can include a 2:1 input multiplexer, a first latch and a second latch. The input multiplexer is coupled to the first latch by a pair of pass gates. The pass gates are gated by a first clock input signal. A second pass gate pair couples the first latch to the second latch. A second clock input signal gates the second pass gate pair. The first and second clock input signals are non-overlapping. The latch can be employed in edge triggered logic ECAD tools for designing IC. The resulting IC logic can be tested using LSSD test testing techniques and patterns.
Scannable flip flop circuit and method of operating an integrated circuit
Номер патента: WO2000072444A3. Автор: Joseph A Hoffman,Joseph W Yoder. Владелец: Lockheed Corp. Дата публикации: 2001-06-28.