СПОСОБ ФОРМИРОВАНИЯ СОЕДИНЕНИЯ В БИНАРНОЙ СИСТЕМЕ И СОЕДИНЕНИЕ, ПОЛУЧЕННОЕ ТАКИМ СПОСОБОМ

Package-Struktur und Verfahren

In einer Ausführungsform umfasst eine Vorrichtung: ein Substrat mit einer ersten Seite und einer zweiten Seite gegenüber der ersten Seite; eine Verbindungsstruktur benachbart zu der ersten Seite des Substrats; und eine IC-Vorrichtung, welche an der Verbindungsstruktur befestigt ist; eine Durchkontaktierung, welche sich von der ersten Seite des Substrats bis zu der zweiten Seite des Substrats erstreckt, wobei die Durchkontaktierung mit der IC-Vorrichtung elektrisch verbunden ist; eine Under-Bump-Metallurgie (UBM) benachbart zu der zweiten Seite des Substrats und die Durchkontaktierung kontaktierend; einen leitfähigen Höcker auf der UBM, wobei es sich bei dem leitfähigen Höcker und der UBM um ein durchgängiges leitfähiges Material handelt, wobei der leitfähige Höcker von der Durchkontaktierung seitlich versetzt ist; und eine Unterfüllung, welche die UBM und den leitfähigen Höcker umgibt.

Substrat-Bondingstruktur und Substrat-Bondingverfahren

Eine Vorrichtung (2) ist auf einer Hauptoberfläche eines Substrats (1) ausgebildet. Die Hauptoberfläche des Substrats (1) ist über das Bonding-Bauteil (11, 12, 13) in einem hohlen Zustand an die Unterseite des Gegensubstrats (14) gebondet. Eine Schaltung (17) und eine Höckerstruktur (26) sind auf der Oberseite des Gegensubstrats (14) ausgebildet. Die Höckerstruktur (26) ist in einem Bereich positioniert, der zumindest dem Bonding-Bauteil (11, 12, 13) entspricht, und weist eine größere Höhe als diejenige der Schaltungsstruktur (17) auf.

Leistungshalbleiterchip und Verfahren zur Herstellung eines Leistungshalbleiterchips und Leistungshalbleitereinrichtung

Leistungshalbleiterchip mit einem Halbleiterbauelementkörper (2) und mit einer auf dem Halbleiterbauelementkörper (2) angeordneten mehrschichtigen Metallisierung (10), die eine über dem Halbleiterbauelementkörper (2) angeordnete Nickelschicht (6) aufweist, wobei die Metallisierung (10) eine auf dem Halbleiterbauelementkörper (2) angeordnete, Aluminium aufweisende erste Metallschicht (3) aufweist, wobei die Nickelschicht (6) über der ersten Metallschicht (3) angeordnet ist, wobei die Metallisierung (10) eine zweite Metallschicht (4), die als Chromschicht ausgebildet ist und eine auf der zweiten Metallschicht (4) angeordnete Zwischenschicht (13), die aus Nickel besteht und eine auf der Zwischenschicht (13) angeordnete dritte Metallschicht (5), die als Silberschicht ausgebildet ist, aufweist, wobei die zweite Metallschicht (4) auf der ersten Metallschicht (3) angeordnet ist, wobei die Nickelschicht (6) auf der dritten Metallschicht (5) angeordnet ist, wobei die Nickelschicht (6) eine Dicke ...

Wafer metallization of high power semiconductor devices

A power semiconductor device for high current density applications, i.e. an insulated gate bipolar transistor (IGBT) or MOSFET, comprising: a plurality of semiconductor regions (201, 203, 204, figure 2) formed on top of one another and a contact layer (207) formed above a first surface of one of the semiconductor regions. The contact layer comprises a first portion placed in direct contact of said first surface of said one of the semiconductor regions and a second portion formed over an insulation region (209) formed in direct contact of said first surface of said one of the semiconductor regions. The device further comprises a first metal layer (230, 235) formed at least partly on the second portion of the contact layer; and a second metal layer 240 formed at least partly on the first metal layer. A gap or void present between the second metal layer and contact layer reduces pressure during fabrication. This structure is suitable for the pressure pack, double sided silver sintering or ...

Substrate bonding

A method of preparing a substrate for bonding includes forming a recess in the substrate 10. A dielectric layer 30 is formed on the substrate 10, having a surface for bonding with another substrate. A plug 40 is formed in the recess and makes electrical contact with the substrate 10. The plug volume is less than the recess volume. The plug extends past the dielectric layer bonding surface. The plug is then compressed by coining, until the plug surface is co-planar with the bonding surface. The plug may be a noble metal, e.g., gold, silver, copper, platinum. The dielectric layer may be a silicon compound. The substrate may have group III nitride LEDs or CMOS devices for use in an active matrix display. The bonding surface may be subjected to plasma activation and exposed to a solution of OH- hydroxide ions to increase bonding effectiveness through Van der Waals forces.

ELECTRONIC DEVICES UTILIZING CONTACT PADS WITH PROTRUSIONS AND METHODS FOR FABRICATION

An electronic device includes a substrate including a front side, a back side, a thickness between the front side and back side, one or more front- side vias extending from the front side into a part of the thickness, and an interconnect via extending from the back side toward the front side; a contact pad on the front side and including one or more protrusions extending through corresponding front- side vias and into the interconnect via; and an interconnect extending through the interconnect via and into contact with the protrusion(s).

Semiconductor package and method of manufacturing thereof

Interconnection [...] structure and method

Semiconductor structure and methods of forming semiconductor constructions

A METHOD FOR CARRYING OUT A STRUCTURE OF JOINING

La présente invention se rapporte à un processus de réalisation d'une structure de connexion (2200) dans un substrat semiconducteur (1000), et au substrat semiconducteur réalisé en conséquence. Le processus de la présente invention, le substrat semiconducteur (1000) comportant au moins une première surface et étant prévu pour une intégration 3D avec un second substrat (1700) le long de la première surface, dans lequel l'intégration 3D est sujette à un défaut latéral d'alignement dans au moins une dimension présentant une valeur de défaut d'alignement , peut inclure l'étape consistant à faire croître une structure de barrière de diffusion (2211) permettant d'empêcher la diffusion d'éléments en dehors d'une couche conductrice dans le reste du substrat semiconducteur, est caractérisé en ce qu'une première surface d'extrémité , représentant la surface la plus à l'extérieur de la structure de barrière de diffusion (2211), sensiblement parallèle à la première surface, le long d'une direction ...

METHOD FOR MAKING AN ELECTRICAL INTERCONNECT LEVEL

이미다졸 및 비스에폭사이드 화합물의 반응 산물을 함유하는 구리 전기도금조로부터 포토레지스트 정의된 특징부의 전기도금 방법

... 전기도금 방법은 실질적으로 균일한 형태를 갖는 포토레지스트 정의된 특징부의 도금을 가능케 한다. 전기도금 방법에는 포토레지스트 정의된 특징부를 전기도금하기 위해 이미다졸 및 비스에폭사이드의 반응 산물을 포함하는 구리 전기도금조가 포함된다. 이러한 특징부에는 기둥, 결합 패드 및 라인 스페이스 특징부가 포함된다.

SEMICONDUCTOR DEVICE WITH A SOLDER BUMP AND METHODS FOR MANUFACTURING THE SEMICONDUCTOR DEVICE AND A WIRING SUBSTRATE

PURPOSE: A semiconductor device and methods for manufacturing the same and a wiring substrate are provided to precisely form a solder layer on a desirable area of a wiring pad by forming the solder layer using a patterned photoresist layer. CONSTITUTION: An electrode pad(9) is formed on a semiconductor substrate(5). A passivation film(6) covers the semiconductor substrate and the periphery of the electrode pad. A contact layer(7) and a seed metal layer(8) are formed on the electrode pad in order. A barrier metal layer(2) and a solder layer(3) are formed on the seed metal layer in order. A stopper film(4) is formed on the upper part of the barrier metal layer. COPYRIGHT KIPO 2013 ...

High convective Flow-assisted dynamic dynamic seal for continuous-rotogravure plating

METHOD OF ELECTROPLATING PHOTORESIST DEFINED FEATURES FROM COPPER ELECTROPLATING BATHS CONTAINING REACTION PRODUCTS OF ALPHA AMINO ACIDS AND BISEPOXDES

Semiconductor product with interlocking metal-to-metal bonds and method for manufacturing thereof

Semiconductor device and method of manufacturing semiconductor device

A semiconductor device includes a semiconductor element; a pad electrode that is formed on the semiconductor element; an alignment mark that is formed on the semiconductor element; a connection electrode that is formed on the pad electrode; and an underfill resin that is formed to cover the connection electrode. The height of the alignment mark from the semiconductor element is greater than that of the connection electrode.

Semiconductor device, method of manufacturing the same, and method of manufacturing wiring board

Resin-encapsulated semiconductor device and method of manufacturing the same

The resin-encapsulated semiconductor device includes a bump electrode (2) formed on an element surface side of a semiconductor chip (1), a conductive layer (3) electrically connected to the bump electrode (2), and a resin encapsulation body (6) covering the semiconductor chip (1), the bump electrode (2), and the conductive layer (3). On a back surface of the semiconductor chip (1) that is flush with a back surface of the resin encapsulation body (6), a metal layer (4) and a laminated film (5) are formed. The laminated film (5) is formed on a front surface of the conductive layer (3). The external terminal (9) is arranged on an inner side of an outer edge of the semiconductor chip (1).

DIE BACKSIDE STANDOFF STRUCTURES FOR SEMICONDUCTOR DEVICES

Standoff structures that can be used on the die backside of semiconductor devices and methods for making the same are described. The devices contain a silicon substrate with an integrated circuit on the front side of the substrate and a backmetal layer on the backside of the substrate. Standoff structures made of Cu of Ni are formed on the backmetal layer and are embedded in a Sn-containing layer that covers the backmetal layer and the standoff structures. The standoff structures can be isolated from each other so that they are not connected and can also be configured to substantially mirror indentations in the leadframe that is attached to the Sn-containing layer. Other embodiments are described.

Metal Bump Joint Structure and Methods of Forming

A structure comprises a first semiconductor chip with a first metal bump and a second semiconductor chip with a second metal bump. The structure further comprises a solder joint structure electrically connecting the first semiconductor chip and the second semiconductor chip, wherein the solder joint structure comprises an intermetallic compound region between the first metal bump and the second metal bump, wherein the intermetallic compound region is with a first height dimension and a surrounding portion formed along exterior walls of the first metal bump and the second metal bump, wherein the surrounding portion is with a second height dimension, and wherein the second height dimension is greater than the first height dimension.

Interconnect structures for preventing solder bridging, and associated systems and methods

Semiconductor dies having interconnect structures formed thereon, and associated systems and methods, are disclosed herein. In one embodiment, an interconnect structure includes a conductive material electrically coupled to an electrically conductive contact of a semiconductor die. The conductive material includes a first portion vertically aligned with the conductive contact, and a second portion that extends laterally away from the conductive contact. A solder material is disposed on the second portion of the interconnect structure such that the solder material is at least partially laterally offset from the conductive contact of the semiconductor die. In some embodiments, an interconnect structure can further include a containment layer that prevents wicking or other undesirable movement of the solder material during a reflow process.

METHOD FOR REMOVING ELECTROPLATED METAL FACETS AND REUSING A BARRIER LAYER WITHOUT CHEMICAL MECHANICAL POLISHING

A method for avoiding using CMP for eliminating electroplated copper facets and reusing barrier layer in the back end of line (BEOL) manufacturing processes. Electropolishing is employed to remove the deposited surface metal, stopping at the barrier layer to form a smooth surface that may be utilized in subsequent steps. The method is suitable for the electropolishing of metal surfaces after formation of filled vias for through-silicon via processes employing metals such as copper, tungsten, aluminum, or alloys thereof. The remaining barrier layer may be reused to fabricate the redistribution layer.

Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect

A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.

SEMICONDUCTOR DEVICES

A semiconductor device includes a first conductive pattern at an upper portion of a first insulating interlayer on a first substrate, a first plurality of conductive nanotubes (CNTs) extending vertically, a second conductive pattern at a lower portion of a second insulating interlayer beneath a second substrate, and a second plurality of CNTs extending vertically. A lower surface of the second insulating interlayer contacts an upper surface of the first insulating interlayer. At least a portion of a sidewall of each of the first plurality of CNTs is covered by the first conductive pattern, and at least a portion of a sidewall of each of the second plurality of CNTs is covered by the second conductive pattern. The first and second conductive patterns vertically face each other, and at least one of the first plurality of CNTs and at least one of the second plurality of CNTs contact each other.

NON-DESTRUCTIVE TESTING OF INTEGRATED CIRCUIT CHIPS

Semiconductor devices and electronics packaging methods include integrated circuit chips having redundant signal bond pads along with signal bond pads connected to the same signal port for non-destructive testing of the integrated circuit chips prior to packaging. Electrical testing is made via the redundant signal bond after which qualified integrated circuit chips can be attached to a pristine and bumped final interposer or printed circuit board to provide increased reliability to the assembled electronic package.

Mechanisms for forming hybrid bonding structures with elongated bumps

Embodiments of mechanisms for forming a package structure are provided. The package structure includes a semiconductor die and a substrate. The package structure includes a pillar bump and an elongated solder bump bonded to the semiconductor die and the substrate. A height of the elongated solder bump is substantially equal to a height of the pillar bump. The elongated solder bump has a first width, at a first horizontal plane passing through an upper end of a sidewall surface of the elongated solder bump, and a second width, at a second horizontal plane passing through a midpoint of the sidewall surface. A ratio of the second width to the first width is in a range from about 0.5 to about 1.1.

Bond Structures and the Methods of Forming the Same

A method includes forming a first conductive feature and a second conductive feature, forming a metal pad over and electrically connected to the first conductive feature, and forming a passivation layer covering edge portions of the metal pad, with a center portion of a top surface of the metal pad exposed through an opening in the metal pad. A first dielectric layer is formed to cover the metal pad and the passivation layer. A bond pad is formed over the first dielectric layer, and the bond pad is electrically coupled to the second conductive feature. A second dielectric layer is deposited to encircle the bond pad. A planarization is performed to level a top surface of the second dielectric layer with the bond pad. At a time after the planarization is performed, an entirety of the top surface of the metal pad is in contact with dielectric materials.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

Object is to prevent a coupling failure between a rewiring and a coupling member for coupling to outside. A passivation film and a first polyimide film are formed so as to cover a wiring layer. A first opening portion is formed in the first polyimide film. A rewiring is formed on the first polyimide film so as to be coupled to the wiring layer via the first opening portion. A second polyimide film that covers the rewiring and has a second opening portion communicated with the rewiring is formed. A palladium film is formed as a barrier film by sputtering on a portion of the surface of the rewiring at which the second opening portion exists. A solder ball is coupled to the palladium film.

GaN power device with solderable back metal

A method for fabricating a vertical gallium nitride (GaN) power device can include providing a GaN substrate with a top surface and a bottom surface, forming a device layer coupled to the top surface of the GaN substrate, and forming a metal contact on a top surface of the vertical GaN power device. The method can further include forming a backside metal by forming an adhesion layer coupled to the bottom surface of the GaN substrate, forming a diffusion barrier coupled to the adhesion layer, and forming a protection layer coupled to the diffusion barrier. The vertical GaN power device can be configured to conduct electricity between the metal contact and the backside metal.

Vertical inductor for WLCSP

Embodiments of the invention include a microelectronic device and methods of forming a microelectronic device. In an embodiment the microelectronic device includes a semiconductor die and an inductor that is electrically coupled to the semiconductor die. The inductor may include one or more conductive coils that extend away from a surface of the semiconductor die. In an embodiment each conductive coils may include a plurality of traces. For example, a first trace and a third trace may be formed over a first dielectric layer and a second trace may be formed over a second dielectric layer and over a core. A first via through the second dielectric layer may couple the first trace to the second trace, and a second via through the second dielectric layer may couple the second trace to the third trace.

Semiconductor device and method comprising redistribution layers

A method of making a semiconductor package can include forming a plurality of redistribution layer (RDL) traces disposed over active surfaces of a plurality of semiconductor die and electrically connected to contact pads on the plurality of semiconductor die. The method can include disposing an encapsulant material over the active surfaces, contacting at least four side surfaces of each of the plurality of semiconductor die, and disposed over the plurality of RDL traces. The method can also include forming a via through the encapsulant material to expose at least one of the plurality of RDL traces, forming an electrical interconnect disposed within the via and coupled to the at least one RDL trace, and singulating the plurality of semiconductor packages through the encapsulant material to leave an offset of 30-140 μm of the encapsulant material disposed around a periphery of each of the plurality of semiconductor die.

Method of manufacturing semiconductor device and semiconductor device

Object is to prevent a coupling failure between a rewiring and a coupling member for coupling to outside. A passivation film and a first polyimide film are formed so as to cover a wiring layer. A first opening portion is formed in the first polyimide film. A rewiring is formed on the first polyimide film so as to be coupled to the wiring layer via the first opening portion. A second polyimide film that covers the rewiring and has a second opening portion communicated with the rewiring is formed. A palladium film is formed as a barrier film by sputtering on a portion of the surface of the rewiring at which the second opening portion exists. A solder ball is coupled to the palladium film.

Semiconductor device and manufacturing method thereof

An electronic device and a method of making an electronic device. As non-limiting examples, various aspects of this disclosure provide various methods of making electronic devices, and electronic devices made thereby, that utilize a film assist mold process.

Wafer backside structures having copper pillars

An integrated circuit structure includes a semiconductor substrate having a front side and a backside, and a conductive via penetrating the semiconductor substrate. The conductive via includes a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is on the backside of the semiconductor substrate and electrically connected to the back end of the conductive via. A passivation layer is over the RDL, with an opening in the passivation layer, wherein a portion of the RDL is exposed through the opening. A copper pillar has a portion in the opening and electrically connected to the RDL.

SEMICONDUCTOR PACKAGE WITH UNDER BUMP METALLIZATION ROUTING

A semiconductor package includes a semiconductor substrate a semiconductor substrate having source and drain regions formed therein, an intermediate routing structure to provide electrical interconnects to the source and drain regions, a dielectric layer formed over the intermediate routing structure, and an under-bump-metallization (UBM) stack. The intermediate routing structure includes an outermost conductive layer, and the dielectric layer has an opening positioned over a portion of the intermediate layer routing structure. The UBM stack includes a conductive base layer formed over the dielectric layer and electrically connected to the outermost conductive layer through the opening, and a thick conductive layer formed on the base layer. A conductive bump is positioned on the UBM stack and laterally spaced from the opening.

Multi-metal contact structure

A first conductive material having a first hardness is disposed within a recess or opening of a microelectronic component, in a first preselected pattern, and forms a first portion of an interconnect structure. A second conductive material having a second hardness different from the first hardness is disposed within the recess or opening in a second preselected pattern and forms a second portion of the interconnect structure.

Process for realising a connecting structure

The present invention relates to a process for realizing a connecting structure (2200) in a semiconductor substrate (1000), and the semiconductor substrate realized accordingly. The process of the present invention, the semiconductor substrate (1000) having at least a first surface, and being foreseen for a 3D integration with a second substrate (1700) along the first surface, wherein the 3D integration is subject to a lateral misalignment in at least one dimension having a misalignment value, can include the step of growing a diffusion barrier structure (2211) for preventing diffusion of elements out of a conductive layer into the rest of the semiconductor substrate, is characterized in that a first end surface, being the most outward surface of the diffusion barrier structure (2211) being substantially parallel to the first surface, along a direction perpendicular to the first surface and going from the substrate toward the first surface, of the diffusion barrier structure (2211) can ...

SUBSTRATE STRUCTURE AND SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To provide a substrate structure that is improved in bonding strength over the entire interface between a bump and UBM. SOLUTION: The substrate structure includes a semiconductor substrate 15, an electrode 14 formed on the semiconductor substrate 15, and an under-barrier metal layer 12 formed on the electrode 14. The under-barrier metal layer 12 has a plurality of fine recessed portions 12a. COPYRIGHT: (C)2011,JPO&INPIT ...

Silicon photonic interposer with two metal redistribution layers

Interconnection potential barrier structure and method

반도체 디바이스 패키지 제조 방법

... 반도체 소자 패키지 및 개선된 땜납 접합부 구조를 사용하여 이 패키지를 제조하는 방법이 개시되어 있다. 상기 패키지는 상부 부분보다 얇은 저부 부분을 갖는 땜납 접합부를 포함한다. 저부 부분은 몰딩 화합물에 의해 둘러싸이고, 상부 부분은 몰딩 화합물에 의해 둘러싸이지 않는다. 상기 방법은 이형 필름을 사용하여 중간 땜납 접합부 주위에 액체 몰딩 화합물을 증착 및 형성하는 것과, 그 다음에 몰딩 화합물을 감소된 높이로 에칭하는 것을 포함한다. 결과적인 땜납 접합부는 몰딩 화합물과 땜납 접합부의 인터페이스에서 웨이스트(waist)를 갖지 않는다. 몰딩 화합물을 에칭 후에, 형성 직후의 몰딩 화합물보다 약 3 미크론 더 큰 거칠기를 갖는다.

반도체 장치 및 이의 제조 방법

... 본 발명은 반도체 장치 및 이의 제조 방법을 제공한다. 이 반도체 장치에서는, 재배선 패턴들 사이에 유기 절연 패턴이 개재된다. 상기 재배선 패턴이 열에 의해 팽창될 경우 발생되는 물리적 스트레스를 상기 유기 절연 패턴이 흡수할 수 있다. 이로써 유연성을 증대시킬 수 있다. 재배선 패턴들 사이에 유기절연 패턴이 개재되므로, 재배선 패턴들 사이에 반도체 패턴이 개재되는 경우에 비해, 절연성을 증대시킬 수 있다. 또한 재배선 패턴과 유기 절연 패턴 사이 그리고 반도체 기판과 유기 절연 패턴 사이에 시드막 패턴이 개재되므로, 재배선 패턴의 접착력이 향상되어 박리 문제를 개선할 수 있다. 또한 재배선 패턴을 구성하는 금속이 유기 절연 패턴으로 확산되는 것을 시드막 패턴이 방지할 수 있다. 이로써, 신뢰성이 향상된 반도체 장치를 구현할 수 있다.

재료 제거를 위한 반도체 디바이스 프로세싱 방법

... 반도체 기판 위에 에칭 용액을 분배하여 재료의 층 상에 에칭 용액의 풀을 형성하는 단계 - 에칭 용액의 풀의 풋프린트는 반도체 기판의 풋프린트보다 더 작음 - 를 포함할 수 있는, 반도체 기판 위로부터 재료의 층의 적어도 일부분을 제거하는 방법이 개시된다. 에칭 용액의 풀 및 반도체 기판은 서로에 대해 이동될 수 있다. 에칭 용액의 풀의 풀 경계가 적어도 하나의 에어나이프로 반도체 기판 상에 한정되어, 에칭 용액의 풀이 에칭 용액의 풀의 풋프린트 내에서 반도체 기판 위의 재료의 층을 에칭하게 할 수 있다. 에칭 용액 및 에칭 용액에 의해 에칭되는 재료의 층의 적어도 일부분이 적어도 하나의 에어나이프로 제거될 수 있다.

ELECTROPLATING METHODS FOR SEMICONDUCTOR SUBSTRATES

A non-uniform initial metal film is non-uniformly deplated to provide a more uniform metal film on a substrate. Electrochemical deplating is performed by placing the substrate in a deplating bath formulated specifically for deplating, rather than for plating. The deplating bath has the throwing power of 0.3 or less or the bath conductivity of 1 to 250 mS/cm. A reverse current conducted through the deplating bath non-uniformly electro-etches or deplates the metal film. COPYRIGHT KIPO 2015 ...

MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE WHICH HAS A THROUGH-ELECTRODE

PURPOSE: A manufacturing method of a semiconductor device is provided to prevent substrate contamination during a manufacturing process by forming a through-electrode after performing a process for polishing the rear surface of a substrate. CONSTITUTION: A substrate(10) includes first and second surfaces facing to each other. A sacrificial film pattern is formed on a region for forming a through-electrode. An upper wiring layer which has a wire located on the sacrificial film pattern is formed on the first surface of the substrate. The sacrificial film pattern is exposed by partially eliminating the second surface of the substrate. An opening part(22) for exposing the wire is formed by eliminating the sacrificial film from the second surface of the substrate. A through-electrode(72) is electrically connected to the wire within the opening part. COPYRIGHT KIPO 2012 ...

Semiconductor device and manufacturing method thereof

A semiconductor device includes a substrate including a surface, a plurality of pads disposing on the surface of the substrate, the plurality of pads includes a non-solder mask defined (NSMD) pad and a solder mask defined (SMD) pad, and the NSMD pad is arranged at a predetermined location. Further, a method of manufacturing a semiconductor device includes providing a substrate, disposing a plurality of pads on a surface of the substrate, disposing a solder mask over the surface of the substrate and the plurality of pads, forming a first recess in the solder mask to surround one of the plurality of pads, and forming a second recess in the solder mask and above one of the plurality of pads.

Package structure

A package structure includes a chip, a selective-electroplating epoxy compound, a patterned circuit layer and a plurality of conductive vias. The chip includes a plurality of solder pads, an active surface and a back surface opposite to the active surface. The solder pads are disposed on the active surface. The selective-electroplating epoxy compound covers the chip and includes non-conductive metal complex. The patterned circuit layer is disposed directly on a surface of the selective-electroplating epoxy compound. The conductive vias are disposed directly at the selective-electroplating epoxy compound to electrically connect the solder pads and the patterned circuit layer.

Semiconductor structure and manufacturing method thereof

A semiconductor structure includes a substrate, a conductive interconnection exposed from the substrate, a passivation covering the substrate and a portion of the conductive interconnection, an under bump metallurgy (UBM) pad disposed over the passivation and contacted with an exposed portion of the conductive interconnection, and a conductor disposed over the UBM pad, wherein the conductor includes a top surface, a first sloped outer surface extended from the top surface and including a first gradient, and a second sloped outer surface extended from an end of the first sloped outer surface to the UBM pad and including a second gradient substantially smaller than the first gradient.

Three-dimensional integrated circuit structures

Three-dimensional integrated circuit structures are disclosed. A three-dimensional integrated circuit structure includes a first die, a second die and a device-free die. The first die includes a first device. The second die includes a second device and is bonded to the first die. The device-free die is located aside the second die and is bonded to the first die. The device-free die includes a conductive feature electrically connected to the first die and the second die.

SEMICONDUCTOR DEVICE AND METHOD OF FORMING PROTECTIVE STRUCTURE AROUND SEMICONDUCTOR DIE FOR LOCALIZED PLANARIZATION OF INSULATING LAYER

Abstract SEMICONDUCTOR DEVICE AND METHOD OF FORMING PROTECTIVE STRUCTURE AROUND SEMICONDUCTOR DIE FOR LOCALIZED PLANARIZATION OF INSULATING LAYERA semiconductor wafer contains a plurality of semiconductor die separated by a saw street. A contact pad is formed over an active surface of the semiconductor die. A protective pattern is formed over the active surface of the semiconductor die between the contact pad and saw street of the semiconductor die. The protective pattern includes a segmented metal layer or plurality of parallel segmented metal layers. An insulating layer is formed over the active surface, contact pad, and protective pattern. A portion of the insulating layer is removed to expose the contact pad. The protective pattern reduces erosion of the insulating layer between the contact pad and saw street of the semiconductor die. The protective pattern can be angled at corners of the semiconductor die or follow a contour of the contact pad. The protective pattern can be formed ...

Chip package and manufacturing method thereof

OPTOELECTRONIC COMPONENT WITH INTEGRATED PROTECTION DIODE AND METHOD FOR PRODUCING SAME

An optoelectronic component (10, 20) comprises an optoelectronic semiconductor chip (100) with a first surface (121), on which a first (130) and a second electrical contact (135) are arranged. The first surface (121) adjoins a moulded body (170). A first (160) and a second pin (165) are embedded in the moulded body (170) and are connected to the first (130) and the second contact (135) in an electrically conductive manner. A protection diode (140) is embedded in the moulded body and is connected to the first (130) and the second contact (135) in an electrically conductive manner.

Under bump metallurgy structural design for high reliability bumped packages

A method for creating an under bump metallization layer (37) is provided. In accordance with the method, a die (33) is provided which has a die pad (35) disposed thereon. A photo-definable polymer (51 or 71) is deposited on the die pad, and an aperture (66) is created in the photo-definable polymer. Finally, an under bump metallization layer (37) is deposited in the aperture. A die package is also provided comprising a die having a die pad (35) disposed thereon, and having an under bump metallization layer (37) disposed on the die pad. The structure has a depression or receptacle (57) therein and has a thickness of at least about 20 microns.

TEXTURED BOND PADS

In some examples, a package comprises a semiconductor die and a bond pad formed upon the semiconductor die. The bond pad has a protrusion on a top surface of the bond pad. The package also comprises a metal contact and a bond wire coupled to the protrusion and to the metal contact. 1. A package , comprising:a semiconductor die;a bond pad formed upon the semiconductor die, the bond pad having a protrusion on a top surface of the bond pad;a metal contact; anda bond wire coupled to the protrusion and to the metal contact.2. The package of claim 1 , wherein the protrusion comprises a rectangular prism.3. The package of claim 1 , wherein the bond pad has multiple protrusions on the top surface of the bond pad.4. The package of claim 3 , wherein a first protrusion of the multiple protrusions is positioned on top of a second protrusion of the multiple protrusions.5. The package of claim 1 , wherein the protrusion comprises a triangular prism.6. The package of claim 1 , wherein the protrusion is spherical.7. The package of claim 1 , wherein the protrusion has a thickness of between 0.01 microns and 0.1 microns claim 1 , inclusive.8. The package of claim 1 , wherein the protrusion occupies less than 50% of the top surface.9. The package of claim 1 , wherein the bond pad comprises:a first metal layer;a second metal layer on the first metal layer; anda third metal layer on the second metal layer, the third metal layer having the top surface having the protrusion;10. The package of claim 9 , wherein the first metal layer comprises copper claim 9 , the second metal layer comprises nickel claim 9 , and the third metal layer comprises palladium.11. The package of claim 1 , wherein the protrusion is part of a textured surface on the top surface.12. The package of claim 11 , wherein the bond pad comprises multiple metal layers.13. The package of claim 12 , wherein the multiple metal layers include a copper layer claim 12 , a palladium layer claim 12 , and a nickel layer positioned ...

Semiconductor device

Disclosed is a semiconductor device including a conductive pattern on a substrate, a passivation layer on the substrate and including an opening that partially exposes the conductive pattern, and a pad structure in the opening of the passivation layer and connected to the conductive pattern. The pad structure includes a first metal layer that fills the opening of the passivation layer and has a width greater than that of the opening, and a second metal layer on the first metal layer. The first metal layer has a first thickness at an outer wall of the first metal layer, a second thickness on a top surface of the passivation layer, and a third thickness on a top surface of the conductive pattern. The second thickness is greater than the first thickness, and the third thickness is greater than the second thickness.

Radiate under-bump metallization structure for semiconductor devices

An under-bump metallization (UBM) structure for a semiconductor device is provided. The UBM structure has a center portion and extensions extending out from the center portion. The extensions may have any suitable shape, including a quadrangle, a triangle, a circle, a fan, a fan with extensions, or a modified quadrangle having a curved surface. Adjacent UBM structures may have the respective extensions aligned or rotated relative to each other. Flux may be applied to a portion of the extensions to allow an overlying conductive bump to adhere to a part of the extensions.

Semiconductor Device and Method of Stacking Semiconductor Die in Mold Laser Package Interconnected By Bumps and Conductive Vias

A semiconductor wafer contains a plurality of first semiconductor die. The semiconductor wafer is mounted to a carrier. A channel is formed through the semiconductor wafer to separate the first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. An encapsulant is deposited over the carrier and first semiconductor die and into the channel while a side portion and surface portion of the second semiconductor die remain exposed from the encapsulant. A first conductive via is formed through the encapsulant in the channel. A second conductive via is formed through the encapsulant over a contact pad of the first semiconductor die. A conductive layer is formed over the encapsulant between the first and second conductive vias. An insulating layer is formed over the conductive layer and encapsulant. The carrier is removed. An interconnect structure is formed over the first conductive via.

Strong, heat stable junction

Provided among other things is an electrical device comprising: a first component that is a semiconductor or an electrical conductor; a second component that is an electrical conductor; and a strong, heat stable junction there between including an intermetallic bond formed of: substantially (a) indium (In), tin (Sn) or a mixture thereof, and (b) substantially nickel (Ni). The junction can have an electrical contact resistance that is small compared to the resistance of the electrical device.

Micro device metal joint process

Metal-to-metal adhesion joints are described as a manner to hold down micro devices to a carrier substrate within the context of a micro device transfer manufacturing process. In accordance with embodiments, the metal-to-metal adhesion joints must be broken in order to pick up the micro devices from a carrier substrate, resulting in micro devices with nubs protruding from bottom contacts of the micro devices. Once integrated, the micro devices are bonded to a receiving substrate, the nubs may be embedded in a metallic joint, or alternatively be diffused within the metallic joint as interstitial metallic material that is embedded within the metallic joint.

Method of forming an integrated crackstop

A method including forming a first dielectric layer above a conductive pad and above a metallic structure, the conductive pad and the metallic structure are each located within an interconnect level above a substrate, forming a first opening and a second opening in the first dielectric layer, the first opening is aligned with and exposes the conductive pad and the second opening is aligned with and exposes the metallic structure, and forming a metallic liner on the conductive pad, on the metallic structure, and above the first dielectric layer. The method may further include forming a second dielectric layer above the metallic liner, and forming a third dielectric layer above the second dielectric layer, the third dielectric layer is thicker than either the first dielectric layer or the second dielectric layer.

Redistribution Layers And Methods Of Fabricating The Same In Semiconductor Devices

A semiconductor structure includes a first passivation layer disposed over a metal line, a copper-containing RDL disposed over the first passivation layer, where the copper-containing RDL is electrically coupled to the metal line and where a portion of the copper-containing RDL in contact with a top surface of the first passivation layer forms an acute angle, and a second passivation layer disposed over the copper-containing RDL, where an interface between the second passivation layer and a top surface of the copper-containing RDL is curved. The semiconductor structure may further include a polymeric layer disposed over the second passivation layer, where a portion of the polymeric layer extends to contact the copper-containing RDL, a bump electrically coupled to the copper-containing RDL, and a solder layer disposed over the bump.

CURED FILM AND METHOD FOR MANUFACTURING SAME

Provided is a cured film of high elongation, low stress, and high adhesion to metal copper. The cured film is formed by curing a photosensitive resin composition, wherein the photosensitive resin comprises a polyhydroxyamide, and wherein the rate of ring-closure of the polyhydroxyamide in the cured film is not more than 10%.

Bond structures and the methods of forming the same

A method includes forming a first conductive feature and a second conductive feature, forming a metal pad over and electrically connected to the first conductive feature, and forming a passivation layer covering edge portions of the metal pad, with a center portion of a top surface of the metal pad exposed through an opening in the metal pad. A first dielectric layer is formed to cover the metal pad and the passivation layer. A bond pad is formed over the first dielectric layer, and the bond pad is electrically coupled to the second conductive feature. A second dielectric layer is deposited to encircle the bond pad. A planarization is performed to level a top surface of the second dielectric layer with the bond pad. At a time after the planarization is performed, an entirety of the top surface of the metal pad is in contact with dielectric materials.

CHIP PACKAGE AND METHOD FOR FORMING THE SAME

An embodiment of the invention provides a chip package which includes: a first chip; a second chip disposed on the first chip; a hole extending from a surface of the first chip towards the second chip; a conducting layer disposed on the surface of the first chip and extending into the hole and electrically connected to a conducting region or a doped region in the first chip; and a support bulk disposed between the first chip and the second chip, wherein the support bulk substantially and/or completely covers a bottom of the hole.

Semiconductor Device with Bond Pad Extensions Formed on Molded Appendage

A semiconductor device includes a semiconductor die having a main surface, a rear surface, outer edge sides extending between the main and rear surfaces, and a first conductive bond pad disposed on the main surface, an electrically insulating mold compound body formed around the outer edge sides of the semiconductor die with the main surface of the semiconductor die exposed from an upper surface of the mold compound body, a first metallization layer formed on the upper surface of the mold compound body and on the main surface of the semiconductor die, and a first bond pad extension formed in the first metallization layer. The first bond pad extension overlaps with the upper surface of the mold compound body. The first bond pad extension is conductively connected with the first conductive bond pad. The first bond pad extension is an externally accessible point of electrical contact of the device.

Electroless metal through silicon via

A method of making a substrate-through metal via having a high aspect ratio, in a semiconductor substrate, and a metal pattern on the substrate surface, includes providing a semiconductor substrate (wafer) and depositing poly-silicon on the substrate. The poly-silicon on the substrate surface is patterned by etching away unwanted portions. Then, Ni is selectively deposited on the poly-silicon by an electroless process. A via hole is made through the substrate, wherein the walls in the hole is subjected to the same processing as above. Cu is deposited on the Ni by a plating process. Line widths and spacings <10 μm are provided on both sides of the wafer.

Mechanically anchored backside C4 pad

The present invention relates generally to flip chip technology and more particularly, to a method and structure for fabricating a mechanically anchored controlled collapse chip connection (C4) pad on a semiconductor structure. In an embodiment, a method is disclosed that may include forming a bonding pad having one or more anchor regions that extend into a semiconductor structure and may inhibit the bonding pad from physically separating from the TSV during temperature fluctuations.

Semiconductor wafer structure and multi-chip stack structure

A semiconductor wafer structure comprises a first surface and a second surface opposite to the first surface, a plurality of chip areas formed on the first surface, a plurality of through-silicon holes formed in each of the plurality of chip areas connecting the first surface and the second surface, and a through-silicon-via (TSV) electrode structure formed in each through-silicon hole. Each through-silicon-via electrode structure comprises a dielectric layer formed on the inner wall of the through-silicon hole, a barrier layer formed on the inner wall of the dielectric layer and defining a vacancy therein, a filling metal layer filled into the vacancy, a first end of the filling metal layer being lower than the first surface forming a recess, and a soft metal cap connecting to and overlaying the first end of the filling metal layer, wherein a portion of the soft metal cap is formed in the recess and the soft metal cap protrudes out of the first surface. Hence, the reliability of multi-chip ...

Pre-resist island forming via method and apparatus

A packaging semiconductor device, such as a fan-out Wafer-Level Packaging (FOWLP) device, is fabricated by providing a semiconductor device (20) having conductive patterns (22) disposed on a first surface and then forming, on the conductive patterns, photoresist islands (24) having a first predetermined shape defined by a first critical width dimension and a minimum height dimension so that a subsequently-formed dielectric polymer layer (26) surrounds but does not cover each photoresist island (24), thereby allowing each photoresist island to be selectively removed from the one or more conductive patterns to form one or more via openings (28) in the dielectric polymer layer such that each via opening has a second predetermined shape which matches at least part of the first predetermined shape of the photoresist islands.

POWER SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING POWER SEMICONDUCTOR DEVICE

A power semiconductor device includes a semiconductor body and a first terminal at the semiconductor body. The first terminal has a first side for adjoining an encapsulation and a second side for adjoining the semiconductor body. The first terminal includes, at the first side, a top layer; and, at the second side, a base layer coupled with the top layer, wherein a sidewall of the top layer and/or a sidewall of the base layer is arranged in an angle smaller than 85° with respect to a plane.

SURFACE-MOUNTED CHIP

Halbleiterstruktur und dazugehöriges Herstellungsverfahren

Halbleiterstruktur, umfassend:einen leitenden Bump (101) zum Anordnen über einem Substrat (201); undein längliches ferromagnetisches Glied (102), das in seiner Längsrichtung eine zentrale Achse (102c) aufweist, die sich von einem ersten Ende (102a) zu einem zweiten Ende (102b) des länglichen ferromagnetischen Glieds (102) erstreckt, wobei das längliche ferromagnetische Glied (102) ein Verhältnis von Länge zu Breite von mindestens 1,5:1 hat;wobei das längliche ferromagnetische Glied (102) von dem leitenden Bump (101) umgeben ist und die zentrale Achse (102c) des länglichen ferromagnetischen Glieds (102) im Wesentlichen orthogonal zu dem Substrat (201) angeordnet ist; undeine leitende Spur (204) mit einem Schleifenabschnitt (204a) zum Erzeugen eines elektromagnetischen Felds und zum Ausrichten des leitenden Bumps (101) mit dem darin einschlossenen länglichen ferromagnetischen Glied (102) durch das von dem Schleifenabschnitt (204a) erzeugte elektromagnetische Feld.

Halbleitermodule und Verfahren zu deren Bildung

Gemäß einer Ausführungsform der vorliegenden Erfindung umfasst ein Halbleitermodul ein erstes Halbleitergehäuse, das einen ersten Halbleiterchip (50) aufweist, der in einem ersten Einkapselungsmittel (80) angeordnet ist. Eine Öffnung (100) ist im ersten Einkapselungsmittel (80) angeordnet. Ein zweites Halbleitergehäuse (150), das einen zweiten Halbleiterchip umfasst, ist in einem zweiten Einkapselungsmittel (180) angeordnet. Das zweite Halbleitergehäuse (150) ist wenigstens teilweise innerhalb der Öffnung (100) im ersten Einkapselungsmittel (80) angeordnet.

Verfahren zur Herstellung von Halbleiterbauelementen mit einer Metallisierungsschicht

Es wird ein Verfahren zur Herstellung von Halbleiterbauelementen (16) offenbart. In einer Ausführungsform wird ein Halbleitersubstrat (10) mit einer ersten Fläche (11), einer zweiten Fläche (12) gegenüber der ersten Fläche (11) und mehreren Halbleiterkomponenten (15) bereitgestellt. Das Halbleitersubstrat (10) hat eine Bauelementdicke. Mindestens eine Metallisierungsschicht (40) wird auf der zweiten Fläche (12) des Halbleitersubstrats (10) ausgebildet. Die Metallisierungsschicht (40) hat eine Dicke, die größer als die Bauelementdicke ist.

Verfahren zur Herstellung eines Halbleiterbauelements

Die Erfindung bezieht sich auf ein Verfahren zur Herstellung eines Halbleiterbauelements mit einer Durchelektrode in einem Substrat. Ein Halbleiterbauelementherstellungsverfahren der Erfindung umfasst, des Bildens einer Opferschichtstruktur in einem Bereich des Substrats, in dem eine Durchelektrode so gebildet wird, dass sie sich von einer ersten Oberfläche des Substrats in einer Dickenrichtung des Substrats erstreckt, des Bildens einer oberen Verdrahtungsschicht mit einer Verdrahtung (32) auf der Opferschichtstruktur, des teilweise Entfernens der zweiten Oberfläche des Substrats, um die Opferschichtstruktur freizulegen, des Entfernens der Opferschichtstruktur, um eine erste Öffnung zu bilden, welche die Verdrahtung freilegt, und des Bildens der Durchelektrode (72) in der ersten Öffnung, die mit der Verdrahtung elektrisch zu verbinden ist. Verwendung in der Halbleiterbauelementtechnologie.

BONDSTRUKTUREN UND VERFAHREN ZU IHRER HERSTELLUNG

Ein Verfahren weist die folgenden Schritte auf: Ausbilden einer ersten leitenden Struktur und einer zweiten leitenden Struktur; Ausbilden einer Metall-Kontaktstelle über und in elektrischer Verbindung mit der ersten leitenden Struktur; und Ausbilden einer Passivierungsschicht, die Randteile der Metall-Kontaktstelle bedeckt, wobei ein mittlerer Teil einer Oberseite der Metall-Kontaktstelle durch eine Öffnung in der Metall-Kontaktstelle freigelegt wird. Eine erste dielektrische Schicht wird so gebildet, dass sie die Metall-Kontaktstelle und die Passivierungsschicht bedeckt. Über der ersten dielektrischen Schicht wird eine Bondinsel gebildet, und die Bondinsel wird mit der zweiten leitenden Struktur elektrisch verbunden. Eine zweite dielektrische Schicht wird so abgeschieden, dass sie die Bondinsel umschließt. Eine Planarisierung wird durchgeführt, um eine Oberseite der zweiten dielektrischen Schicht auf gleiche Höhe mit der Bondinsel zu bringen. Nach der Durchführung der Planarisierung ist ...

Across a plurality of conductive columns of the planarized semiconductor construction and method

Electronic component, semiconductor package and electronic device

반도체 장치, 반도체 패키지 및 반도체 패키지의 제조 방법

... 반도체 장치가 개시된다. 반도체 장치는, 기판 상에 형성된 도전 성분(conductive component); 상기 기판 상에 형성되며 개구부를 구비하는 패시베이션층으로서, 상기 개구부가 상기 도전 성분의 적어도 일부분을 노출하는, 상기 패시베이션층; 및 상기 패시베이션층 상에서 상기 개구부를 채우며, 상기 도전 성분과 전기적으로 연결되는 패드 구조물을 포함한다. 상기 패드 구조물은 상기 개구부의 내벽 상에 및 상기 개구부 주위의 상기 패시베이션층 상면 상에 콘포말하게 형성되며, 순서대로 적층된 도전 배리어층, 제1 시드층, 식각 정지층 및 제2 시드층을 포함하는 하부 도전층, 상기 하부 도전층 상에 형성되며, 상기 개구부를 적어도 부분적으로 채우는 제1 패드층, 및 상기 제1 패드층 상에 형성되며, 상기 패시베이션층의 상기 상면 상에 배치되는 상기 하부 도전층의 외주 부분과 접촉하는 제2 패드층을 포함한다.

제1 및 제2 구성요소들의 조립 후에 금속 커넥터를 도금함으로써 마이크로전자 조립체를 형성하는 방법 및 대응하는 장치

... 마이크로전자 조립체들 및 이의 제조 방법들이 본 명세서에 개시된다. 일 실시예에서, 마이크로전자 조립체의 형성 방법은 제1 및 제2 구성요소(102, 128)들의 제1 주 표면(104, 130)들이 서로 대면하고 사전결정된 간격만큼 서로 이격되도록 제1 및 제2 구성요소(102, 128)들을 조립하는 단계로서, 제1 구성요소(102)는 반대편을 향하는 제1 및 제2 주 표면(104, 106)들, 제1 주 표면(104)과 제2 주 표면(106) 사이에서 제1 방향으로 연장되는 제1 두께, 및 제1 주 표면(104)에 있는 복수의 제1 금속 접속 요소(112)들을 구비하고, 제2 구성요소(128)는 제2 구성요소(128)의 제1 주 표면(130)에 있는 복수의 제2 금속 접속 요소(132)들을 구비하는, 상기 제1 및 제2 구성요소들을 조립하는 단계; 및 이어서 각자의 제1 접속 요소(112)와 각자의 제1 접속 요소(112)의 반대편의 대응하는 제2 접속 요소(132) 사이에서 각각 제1 방향으로 연속적으로 연장되어 접속하는 복수의 금속 커넥터 영역(146)들을 도금(전기 도금 또 무전해 도금)하는 단계를 포함한다. 제1 및 제2 금속 접속 요소(112, 132)들은 구성요소(102, 128)들 내의 금속 비아(116, 134)들 또는 구성요소(102, 128)들의 표면에 있는 금속 패드(118)들을 포함할 수 있는데, 금속 비아(116, 134)들 또는 금속 패드(118)들은 도금 금속 영역(114)들에 의해 덮인다. 제1 시드 층(126)이 도금 공정 전에 제1 구성요소(102)의 주 표면 위에 놓이게 형성될 수 있는데, 여기서 금속 커넥터 영역(146)들을 도금한 후에 제1 시드 층(126)의 덮이지 않은 부분들이 제거된다. 유사하게, 제2 시드 층(144)이 제2 구성요소(128)의 주 표면 위에 놓이게 형성될 수 있다. 복수의 장벽 영역(152)들이 금속 커넥터 영역(146)들, 제1 도금 금속 영역(114)들 또는 제2 도금 금속 영역들 중 적어도 하나의 ...

Bump structure and the method for fabricating the same

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure includes a substrate, a conductive interconnection part exposed from the substrate, a passivation part covering the substrate and a portion of the conductive interconnection part, an under bump metallurgy (UBM) pad disposed on the upper side of the passivation part and touching an exposed portion of the conductive interconnection part, and a conductor disposed on the upper side of the UBM pad. The conductor includes a top surface, a first sloped outer surface extended from the top surface and including a first gradient, and a second sloped outer surface extended from an end of the first sloped outer surface to the UBM pad and including a second gradient substantially smaller than the first gradient. COPYRIGHT KIPO 2016 (AA) W_conductor (BB) W_lower end (CC) W_upper end (DD) W_protrusion (EE) H_protrusion (FF) H_conductor ...

METAL BUMP JOINT STRUCTURE

Semiconductor device package and method for forming the same

Process for realising a connecting structure

The present invention relates to a process for realizing a connecting structure (2200) in a semiconductor substrate (1000), and the semiconductor substrate realized accordingly. The process of the present invention, the semiconductor substrate (1000) having at least a first surface, and being foreseen for a 3D integration with a second substrate (1700) along the first surface, wherein the 3D integration is subject to a lateral misalignment in at least one dimension having a misalignment value, can include the step of growing a diffusion barrier structure (2211) for preventing diffusion of elements out of a conductive layer into the rest of the semiconductor substrate, is characterized in that a first end surface, being the most outward surface of the diffusion barrier structure (2211) being substantially parallel to the first surface, along a direction perpendicular to the first surface and going from the substrate toward the first surface, of the diffusion barrier structure (2211) can ...

Multi chip package structure, wafer level chip package structure and manufacturing method thereof

A multi chip package structure includes a first chip, a second chip, a circuit layer, a plurality of first conductive bumps, a plurality of second conductive bumps and an underfill. The first chip has a chip connecting zone, a plurality of first inner pads and first outer pads. The circuit layer is disposed on the first chip and includes a plurality of insulating layers, having a groove, and at least one metal layer. The groove is disposed between the first inner pads and the first outer pads and surrounds the first inner pads. The first conductive bumps are disposed on the first outer pads. The second chip is flipped on the chip connecting zone. Each first inner pad is electrically connected to a second pad of the second chip through the second conductive bump. The underfill is disposed between the first and the second chips and covers the second conductive bumps.

Chip package and method for forming the same

A chip package including a substrate is provided. A sensing region or device region of the substrate is electrically connected to a conducting pad. A first insulating layer is disposed on the substrate. A redistribution layer is disposed on the first insulating layer. A first portion and a second portion of the redistribution layer are electrically connected to the conducting pad. A second insulating layer conformally extends on the first insulating layer, and covers side surfaces of the first portion and the second portion. A protection layer is disposed on the second insulating layer. A portion of the second insulating layer is located between the protection layer and the first insulating layer. A method of forming the chip package is also provided.

Semiconductor device

A semiconductor device of the present invention includes: a substrate; a heat generating part formed on the substrate; a cap substrate formed above the substrate so as to provide a hollow part between itself and the substrate; and a reflecting film, above the heat generating part, that reflects infrared light. This has the action of suppressing temperature increase on the cap substrate side by the reflecting film reflecting infrared light which is radiated to the cap substrate side via the hollow part due to temperature increase of the heat generating part. This action leads to an effect of suppressing temperature increase of mold resin even in the presence of the mold resin on the cap substrate.

REVERSE SIDE ENGINEERED III-NITRIDE DEVICES

Group III-nitride devices are described that include a stack of III-nitride layers, passivation layers, and conductive contacts. The stack includes a channel layer with a 2DEG channel, a barrier layer and a spacer layer. One passivation layer directly contacts a surface of the spacer layer on a side opposite to the channel layer and is an electrical insulator. The stack of III-nitride layers and the first passivation layer form a structure with a reverse side proximate to the first passivation layer and an obverse side proximate to the barrier layer. Another passivation layer is on the obverse side of the structure. Defected nucleation and stress management layers that form a buffer layer during the formation process can be partially or entirely removed.

Strain release contact system for integrated circuits

The problem of stress transmission from the outside of an integrated circuit package into the interior of the semiconductor has been significantly reduced by placing a micro-spring between the external solder ball and the interior tab. The process for manufacturing such a structure begins with a fully completed integrated circuit on whose surface freestanding metal posts are formed, each post being in contact with an I/O pad. Using a leveling plate at elevated temperature, the posts are given a permanent tilt relative to the surface and are then encapsulated in an elastomer. This subprocess may then be repeated as many times as desired with the direction in which the posts lean being changed by 90 degrees at each iteration. This results in the formation of an orthogonal spiral which acts as a coil spring to absorb stress originating at the solder ball.

METHOD OF MAKING A BUMP ON A SUBSTRATE USING MULTIPLE PHOTORESIST LAYERS

A method of forming a bump on a substrate such as a semiconductor wafer or flip chip. The method includes the step of providing a semiconductor device having a contact pad and an upper passivation layer and an opening formed in the upper passivation layer exposing a portion of the contact pad. An under bump metallurgy is deposited over the upper passivation layer and the contact pad. A first photoresist layer is deposited in a liquid state so that the first photoresist layer covers the under bump metallurgy. A second photoresist layer is deposited and the second photoresist layer is a dry film photoresist. The unexposed portions of the first photoresist layer are removed. The remaining portions of the first photoresist layers are removed. The electrically conductive material is reflown to provide a bump on the semiconductor device.

Semiconductor device with flip chip bonding pads and manufacture thereof

A semiconductor substrate is prepared which has a principal surface, an exposed pad made of conductive material being formed in a partial area of the principal surface, and the other area of the principal surface being covered with a first insulating film. A base conductive film is formed on the first insulating film and the pad. A photoresist film having a thickness of 50 mum or thicker is formed on the base conductive film. An opening is formed through the photoresist film in an area corresponding to the pad to expose a partial surface area of the base conductive film. A conductive bump electrode is deposited on the base conductive film exposed on a bottom of the opening. The photoresist film is removed. This method is suitable for making a fine pitch between bump electrodes.

INTEGRATED CIRCUIT SYSTEM WITH CARRIER CONSTRUCTION CONFIGURATION AND METHOD OF MANUFACTURE THEREOF

A method of manufacture of an integrated circuit system includes: providing a semiconductor wafer with a bond pad; attaching a detachable carrier to the semiconductor wafer, the detachable carrier including a carrier frame portion and a terminal structure; removing the carrier frame portion with the terminal structure attached to the semiconductor wafer; and forming an encapsulation encapsulating the semiconductor wafer, the bond pad, and the terminal structure.

Etchant and method for manufacturing semiconductor device using same

Disclosed are an etchant which is used for redistribution of a semiconductor substrate having an electrode and which is capable of selectively etching copper without etching nickel; and a method for manufacturing a semiconductor device using the same. Specifically disclosed are an etchant which is used for redistribution of a semiconductor substrate and which contains hydrogen peroxide and citric acid and has a content of hydrogen peroxide of from 0.75 to 12% by mass and a content of citric acid of from 1 to 20% by mass, with a molar ratio of hydrogen peroxide and citric acid being in the range of from 0.3 to 5; an etchant for selective etching of copper which is used for redistribution of a semiconductor substrate and which contains hydrogen peroxide and malic acid and has a content of hydrogen peroxide of from 0.75 to 12% by mass and a content of malic acid of from 1.5 to 25% by mass, with a molar ratio of hydrogen peroxide and malic acid being in the range of from 0.2 to 6; and a method ...

Conductive Sidewall for Microbumps

Electromigration in microbump connections causes voids in the microbumps, which reduces the lifetime of an integrated circuit containing the microbump. Electromigration lifetime may be increased in microbumps by forming a copper shell around the solder. The copper shell of one microbump contacts the copper shell of a second microbump to enclose the solder of the microbump connection. The copper shell allows higher current densities through the microbump. Thus, smaller microbumps may be manufactured on a smaller pitch without suffering failure from electromigration. Additionally, the copper shell reduces shorting or bridging between microbump connections on a substrate.

Conductive feature for semiconductor substrate and method of manufacture

A conductive feature on a semiconductor component is disclosed. A first passivation layer is formed over a substrate. A bond pad is formed over the first passivation layer. A second passivation layer overlies the first passivation layer and the bond pad. The second passivation layer has a first opening overlying the bond pad and a plurality of second openings exposing a top surface of the first passivation layer. A buffer layer overlies the second passivation layer and fills the plurality of second openings. The buffer layer has a third opening overlapping the first opening and together exposes a portion the bond pad. The combined first opening and third opening has sidewalls. An under bump metallurgy (UBM) layer overlies the sidewalls of the combined first opening and third opening, and contacts the exposed portion of the bond pad. A conductive feature overlies the UBM layer.

Method of manufacturing semiconductor device

A method of manufacturing a semiconductor device including the following steps: forming an insulator layer over a first conductor over a semiconductor substrate; forming a barrier layer to coat the surface of the insulator layer; forming a second conductor over the barrier layer; melting the second conductor in an atmosphere containing either hydrogen or carboxylic acid in a condition that the surface of the insulator layer over the first conductor is coated with the barrier layer; and removing the barrier layer partially from the surface of the insulator layer with the second conductor as a mask.

Semiconductor Device and Method of Forming an Inductor Within Interconnect Layer Vertically Separated from Semiconductor Die

A semiconductor device has an adhesive layer formed over a carrier. A semiconductor die has bumps formed over an active surface of the semiconductor die. The semiconductor die is mounted to the carrier with the bumps partially disposed in the adhesive layer to form a gap between the semiconductor die and adhesive layer. An encapsulant is deposited over the semiconductor die and within the gap between the semiconductor die and adhesive layer. The carrier and adhesive layer are removed to expose the bumps from the encapsulant. An insulating layer is formed over the encapsulant. A conductive layer is formed over the insulating layer in a wound configuration to exhibit inductive properties and electrically connected to the bumps. The conductive layer is partially disposed within a footprint of the semiconductor die. The conductive layer has a separation from the semiconductor die as determined by the gap and insulating layer.

Chip scale surface mounted semiconductor device package and process of manufacture

A semiconductor device package die and method of manufacture are disclosed. The device package die may comprise a device substrate having one or more front electrodes located on a front surface of the device substrate and electrically connected to one or more corresponding device regions formed within the device substrate proximate the front surface. A back conductive layer is formed on a back surface of the device substrate. The back conductive layer is electrically connected to a device region formed within the device substrate proximate a back surface of the device substrate. One or more conductive extensions are formed on one or more corresponding sidewalls of the device substrate in electrical contact with the back conductive layer, and extend to a portion of the front surface of the device substrate. A support substrate is bonded to the back surface of the device substrate.

Packaging substrate with conductive structure

A packaging substrate with conductive structure is provided, including a substrate body having at least one conductive pad on a surface thereof, a stress buffer metal layer disposed on the conductive pad and a thickness of the stress buffer metal layer being 1-20 μm, a solder resist layer disposed on the substrate body and having at least one opening therein for correspondingly exposing a portion of top surface of the stress buffer metal layer, a metal post disposed on a central portion of the surface of the stress buffer metal layer, and a solder bump covering the surfaces of the metal post. Therefore, a highly reliable conductive structure is provided, by using the stress buffer metal layer to release thermal stresses, and using the metal post and the solder bump to increase the height of the conductive structure.

Solder ball contact susceptible to lower stress

A solder ball contact and a method of making a solder ball contact includes: a first insulating layer with a via formed on an integrated circuit (IC) chip and a metal pad; an under bump metallurgy (UBM) structure disposed within the via and on a portion of the first insulating layer, surrounding the via; a second insulating layer formed on an upper surface of an outer portion of the UBM structure that is centered on the via; and a solder ball that fills the via and is disposed above an upper surface of an inner portion of the UBM structure that contacts the via, in which the UBM structure that underlies the solder ball is of a greater diameter than the solder ball.

Semiconductor package including an external circuit element

Circuit elements such as DC blocking capacitors used in communication such as a serial communication link between two or more electrical components are disposed in pre-existing openings in a support structure that supports at least one of the two electrical components. The openings may be plated and used for signal transmission from the one electrical component to a printed circuit board (PCB) supporting the substrate. The DC blocking capacitors may be oriented substantially vertically, and a non-conducting material may be disposed in each opening in the substrate such that the non-conducting material at least partially surrounds and fixes the orientation of the DC blocking capacitor disposed in the opening.

Semiconductor Device and Method of Forming Stacked Vias Within Interconnect Structure for FO-WLCSP

A semiconductor device has a semiconductor die mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A first insulating layer is formed over the encapsulant and semiconductor die. First vias are formed through the first insulating layer to expose contact pads of the semiconductor die. A first conductive layer is formed over the first insulating layer and into the first vias to electrically connect to the contact pads of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. Second vias are formed through the second insulating layer by laser direct ablation and aligned or offset with the first vias to expose the first conductive layer. A second conductive layer is formed over the second insulating layer and into the second vias. Conductive vias can be formed through the encapsulant.

Semiconductor Device and Method of Forming Interposer Frame Electrically Connected to Embedded Semiconductor Die

A semiconductor device has an interposer frame mounted over a carrier. A semiconductor die has an active surface and bumps formed over the active surface. The semiconductor die can be mounted within a die opening of the interposer frame or over the interposer frame. Stacked semiconductor die can also be mounted within the die opening of the interposer frame or over the interposer frame. Bond wires or bumps are formed between the semiconductor die and interposer frame. An encapsulant is deposited over the interposer frame and semiconductor die. An interconnect structure is formed over the encapsulant and bumps of the first semiconductor die. An electronic component, such as a discrete passive device, semiconductor die, or stacked semiconductor die, is mounted over the semiconductor die and interposer frame. The electronic component has an I/O count less than an I/O count of the semiconductor die.

Semiconductor Device and Method of Forming Interposer Frame Over Semiconductor Die to Provide Vertical Interconnect

A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.

Post-passivation interconnect structure and method of forming the same

A semiconductor device includes a conductive layer formed on the surface of a post-passivation interconnect (PPI) structure by an immersion tin process. A polymer layer is formed on the conductive layer and patterned with an opening to expose a portion of the conductive layer. A solder bump is then formed in the opening of the polymer layer to electrically connect to the PPI structure.

Semiconductor package, packaging substrate and fabrication method thereof

A packaging substrate and a semiconductor package using the packaging substrate are provided. The packaging substrate includes: a substrate body having a die attach area, a circuit layer formed around the die attach area and having a plurality of conductive traces each having a wire bonding pad, and a surface treatment layer formed on the wire bonding pads. Therein, only one of the conductive traces is connected to an electroplating line so as to prevent cross-talk that otherwise occurs between conductive traces due to too many electroplating lines in the prior art.

Semiconductor Processing Methods

Some embodiments include methods in which insulative material is simultaneously deposited across both a front side of a semiconductor substrate, and across a back side of the substrate. Subsequently, openings may be etched through the insulative material across the front side, and the substrate may then be dipped within a plating bath to grow conductive contact regions within the openings. The insulative material across the back side may protect the back side from being plated during the growth of the conductive contact regions over the front side. In some embodiments, plasma-enhanced atomic layer deposition may be utilized to for the deposition, and may be conducted at a temperature suitable to anneal passivation materials so that such annealing occurs simultaneously with the plasma-enhanced atomic layer deposition.

Magnet Assisted Alignment Method for Wafer Bonding and Wafer Level Chip Scale Packaging

A high-precision alignment method with high throughput is proposed, which can be used for wafer-to-wafer, chip-to-wafer or chip-to-chip bonding. The scheme implements pairing patterned magnets predetermined designed and made using wafer level process on two components (wafer or chip). The magnetization in patterned magnet can be set at predetermined configuration before bonding starts. When, the two components are bought to close proximity after a coarse alignment, the magnetic force will bring the magnet pairs together and aligned the patterned magnet on one component with its mirrored or complimentary patterned magnets on the other component to minimize the overall the magnetic energy of the pairing magnet. A few patterned magnet structures and materials, with their unique merits are proposed as examples for magnet pair for the self-alignment purpose. This method enables solid contact at the bonding interface via patterned magnets under the magnetic force, which avoid the wafer drafting due to the formation of the liquid phases.

Method to realize flux free indium bumping

A method to realize flux free indium bumping process includes several steps including substrate metallization, contact holes opening, underbump metallization (UBM) layer thickening, indium bump preparation and Ag layer coating. The method can be used in the occasion for some special application, e.g., the packaging of the photoelectric chip (with optical lens), MEMS and biological detection chip, where the usage of flux is prohibited.

Heterostructure containing ic and led and method for fabricating the same

A heterostructure containing IC and LED and a method of fabricating. An IC and an LED are established with the IC having a first electric-conduction block and a first connection block. The IC electrically connects to the first electric-conduction block. A first face of the LED has a second electric-conduction block and a second connection block. The LED is electrically connected to the second electric-conduction block. The first electric-conduction block and the first connection block are respectively joined to the second electric-conduction block and the second connection block, and the first electric-conduction block are electrically connected with the second electric-conduction block to form a heterostructure. The heterostructure provides functions of heat radiation and electric communication for IC and LED.

Semiconductor device

A semiconductor device includes a protective layer, a redistribution pattern, a pad pattern and an insulating polymer layer. The protective layer may be formed on a substrate. The redistribution pattern may be formed on the protective layer. An upper surface of the redistribution may be substantially flat. The pad pattern may be formed directly on the redistribution pattern. An upper surface of the pad pattern may be substantially flat. The insulating polymer layer may be formed on the redistribution pattern and the pad pattern. An upper surface of the insulating polymer layer may be lower than the upper surface of the pad pattern. The semiconductor device may have a high reliability.

Semiconductor Device and Method of Forming Build-Up Interconnect Structures Over a Temporary Substrate

A semiconductor device has a first build-up interconnect structure formed over a substrate. The first build-up interconnect structure includes an insulating layer and conductive layer formed over the insulating layer. A vertical interconnect structure and semiconductor die are disposed over the first build-up interconnect structure. The semiconductor die, first build-up interconnect structure, and substrate are disposed over a carrier. An encapsulant is deposited over the semiconductor die, first build-up interconnect structure, and substrate. A second build-up interconnect structure is formed over the encapsulant. The second build-up interconnect structure electrically connects to the first build-up interconnect structure through the vertical interconnect structure. The substrate provides structural support and prevents warpage during formation of the first and second build-up interconnect structures. The substrate is removed after forming the second build-up interconnect structure. A portion of the insulating layer is removed exposing the conductive layer for electrical interconnect with subsequently stacked semiconductor devices. 1. A method of making a semiconductor device , comprising:providing a substrate;forming a first interconnect structure over the substrate;disposing a first semiconductor die over the first interconnect structure;disposing the substrate over a carrier with the first semiconductor die oriented away from the carrier;depositing an encapsulant over the carrier, substrate, and first semiconductor die;forming a second interconnect structure over the encapsulant and semiconductor die; andremoving the substrate to expose the first interconnect structure after forming the second interconnect structure.2. The method of claim 1 , further including forming a conductive column over the first interconnect structure.3. The method of claim 2 , wherein the conductive column extends from the first interconnect structure to the second interconnect structure ...

DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME, DISPLAY DEVICE

The present disclosure provides a display substrate and a method of manufacturing the same, and a display device. The display substrate includes a base substrate; a driving circuit layer disposed on the base substrate; and a planarization layer disposed on a side of the driving circuit layer away from the base substrate and having a plurality of conductive pads therein, the plurality of conductive pads are respectively electrically coupled to electrodes in the driving circuit layer, and a surface of each of the plurality of conductive pads away from the base substrate is flush with a surface of the planarization layer away from the base substrate. 1. A display substrate , comprising:a base substrate;a driving circuit layer located on the base substrate; anda planarization layer located on a side of the driving circuit layer away from the base substrate,wherein the planarization layer has a plurality of conductive pads therein, and a surface of each of the plurality of conductive pads away from the base substrate is flush with a surface of the planarization layer away from the base substrate, andwherein the plurality of conductive pads are electrically coupled to electrodes in the driving circuit layer respectively.2. The display substrate of claim 1 , wherein a material of the planarization layer is photoresist.3. The display substrate of claim 2 , wherein a height tolerance d1 of the surface of the planarization layer away from the base substrate is in a range from −1 μm to 1 μm.4. The display substrate of claim 1 , wherein a height tolerance of a surface of the driving circuit layer away from the base substrate is d2 claim 1 , and a thickness D of the planarization layer in a direction perpendicular to a surface of the base substrate satisfies: |2.5*d2|≤D≤|4*d2|.5. The display substrate of claim 3 , wherein a height tolerance of a surface of the driving circuit layer away from the base substrate is d2 claim 3 , and a thickness D of the planarization layer in a ...

Metal pad modification

The present invention provides a structure. In an exemplary embodiment, the structure includes a base material, at least one metal pad, where a first surface of the metal pad is in contact with the base material, and a metal pedestal, where the metal pedestal is in contact with the metal pad, where a radial alignment of the metal pad is shifted by an offset distance, with respect to the metal pedestal, such that the metal pad is shifted towards a center axis of the base material, where a first dimension of the metal pad is smaller than a second dimension of the metal pad, where the second dimension is orthogonal to a line running from a center of the metal pad to the center axis of the base material, where the first dimension is parallel to the line.

SEMICONDUCTOR PACKAGE AND METHOD MANUFACTURING THE SAME

A semiconductor package including an insulating encapsulation, an integrated circuit component, and conductive elements is provided. The integrated circuit component is encapsulated in the insulating encapsulation, wherein the integrated circuit component has at least one through silicon via protruding from the integrated circuit component. The conductive elements are located on the insulating encapsulation, wherein one of the conductive elements is connected to the at least one through silicon via, and the integrated circuit component is electrically connected to the one of the conductive elements through the at least one through silicon via. 1. A semiconductor package , comprising:an insulating encapsulation;an integrated circuit component, encapsulated in the insulating encapsulation, wherein the integrated circuit component has at least one through silicon via protruding from the integrated circuit component; andconductive elements, located on the insulating encapsulation, wherein one of the conductive elements is connected to the at least one through silicon via, and the integrated circuit component is electrically connected to the one of the conductive elements through a portion of the at least one through silicon via protruding from the integrated circuit component.2. The semiconductor package as claimed in claim 1 , further comprising a plurality of conductive pillars arranged aside the integrated circuit component claim 1 , wherein the plurality of conductive pillars is electrically connected to the conductive elements claim 1 , respectively.3. The semiconductor package as claimed in claim 2 , further comprising a glue material covering a sidewall of the integrated circuit component and encapsulated in the insulating encapsulation claim 2 ,wherein an interface is between the glue material and the insulating encapsulation, and the plurality of conductive pillars penetrates and is in contact with the glue material, and the plurality of conductive pillars and ...

SEMICONDUCTOR DEVICE PROCESSING METHOD FOR MATERIAL REMOVAL

A method of removing at least a portion of a layer of material from over a semiconductor substrate that can include dispensing an etching solution over the semiconductor substrate to form a pool of etching solution on the layer of material, wherein a footprint of the pool of etching solution is less than a footprint of the semiconductor substrate. The pool of etching solution and the semiconductor substrate can be moved with respect to each other. A pool boundary of the pool of etching solution can be defined on the semiconductor substrate with at least one air-knife such that the pool of etching solution etches the layer of material over the semiconductor substrate within the footprint of the pool of etching solution. The etching solution and at least a portion of the layer of material etched by the etching solution can be removed with the at least one air-knife. 1. A method of removing material from a semiconductor device , comprising:providing a semiconductor substrate comprising a length L, a first surface, and a second surface opposite the first surface;forming a layer of material over the first surface of the semiconductor substrate;providing a conveyor;providing a first air-knife disposed over the conveyor;providing a second air-knife disposed over the conveyor and offset from the first air-knife by a distance D that is less than the length L of the semiconductor substrate;placing the semiconductor substrate on the conveyor with the layer of material oriented facing away from the conveyor, the semiconductor substrate being placed on the conveyor before the first air-knife and before the second air-knife;advancing the semiconductor substrate along the conveyor and under the first air-knife so that a portion of the semiconductor substrate is disposed between the first air-knife and the second air-knife;forming a pool of etching solution by dispensing an etching solution onto the layer of material over the portion of the semiconductor substrate disposed between ...

PRE-PLATED SUBSTRATE FOR DIE ATTACHMENT

A method for attaching a semiconductor die to a substrate includes providing a substrate that includes an attachment layer at a surface of the substrate. The attachment layer is covered by a protective flash plating layer. The protective flash plating layer has a reflow temperature less than or equal to a reflow temperature of the attachment layer. The method further includes preheating the substrate to a temperature greater than or equal to a reflow temperature of the attachment layer, attaching a semiconductor die to the attachment layer, and cooling the substrate and semiconductor die. 19-. (canceled)10. A method of preparing a substrate for attachment to a semiconductor die , the method comprising:providing a substrate;selectively forming an attachment layer on a surface of the substrate at one or more die attachment locations, the attachment layer having a reflow temperature; andcovering the attachment layer with a protective flash plating layer, the protective flash plating layer having a reflow temperature that is less than or equal to the reflow temperature of the attachment layer.11. The method of claim 10 , wherein the formation of the attachment layer includes selectively plating one or more attachment stacks to the surface of the substrate at the one or more die attachment locations.12. The method of claim 10 , wherein the formation of the attachment layer includes selectively stamping one or more attachment preforms onto the surface of the substrate at the one or more die attachment locations.13. The method of claim 10 , wherein the formation of the attachment layer includes spot welding one or more attachment preforms at diagonal corners of each of the one or more die attachment locations.14. The method of claim 10 , wherein the formation of the attachment layer includes hot rolling one or more attachment preforms onto the surface of the substrate at the one or more die attachment locations.15. The method of claim 10 , wherein the protective flash ...

SELF-ALIGNED UNDER BUMP METAL

An integrated circuit including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, with a solder ball formed on the self-aligned under bump metal pad. Processes of forming integrated circuits including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, by a process of forming one or more metal layers on the interconnect level and the dielectric layer, selectively removing the metal from over the dielectric layer, and subsequently forming a solder ball on the self-aligned under bump metal pad. Some examples include additional metal layers formed after the selective removal process, and may include an additional selective removal process on the additional metal layers. 1. A method of forming an integrated circuit , comprising;forming an interconnect region;forming a top interconnect level in the interconnect region, so that the top interconnect level includes a connection pad;forming a dielectric layer over the top interconnect level;forming a connection opening in the dielectric layer such that a portion of a top surface of the connection pad is exposed, while the dielectric layer overlaps a periphery of the connection pad, and such that a connection opening sidewall is formed at a boundary of the dielectric layer over the connection pad;forming an under bump metal layer on the exposed portion of the top surface of the connection pad and over the dielectric layer, such that the under bump metal layer contacts the connection opening sidewall;selectively removing material from the under bump metal layer over the dielectric layer so as to form a self-aligned under bump metal pad, such that the self-aligned under bump metal pad contacts the connection opening sidewall, and such that the self-aligned under bump metal pad does not contact a top surface of the dielectric layer; andforming a solder ball on a top surface of the self ...

Method for processing an electronic component and an electronic component

According to various embodiments an electronic component includes: at least one electrically conductive contact region; a contact pad including a self-segregating composition disposed over the at least one electrically conductive contact region; a segregation suppression structure disposed between the contact pad and the at least one electrically conductive contact region, wherein the segregation suppression structure includes more nucleation inducing topography features than the at least one electrically conductive contact region for perturbing a chemical segregation of the self-segregating composition by crystallographic interfaces of the contact pad defined by the nucleation inducing topography features.

MOUNTING STRUCTURE AND MOUNTING STRUCTURE MANUFACTURING METHOD

A mounting structure which reduces the mechanical stress added to a low-κ material due to warping caused by the difference in thermal expansion coefficients between a chip and a chip support during mounting. This mounting structure includes: a low-κ layer formed on top a semiconductor substrate; an electrode layer formed on the low-κ layer; a protective layer formed the low-κ layer and the electrode layer and having an opening reaching the electrode layer; a first solder layer filling the opening and formed on the electrode layer inside; a second solder layer formed on the first solder layer and having an elastic modulus smaller than the first solder layer; and a support layer connected to the second solder layer and supporting the semiconductor substrate. The protective layer has a greater elastic modulus and a smaller thermal expansion coefficient than an underfill layer formed between the protective layer and the support layer. 1. A mounting structure comprising:a low-κ layer formed on top of a semiconductor substrate;an electrode layer formed on top of the low-κ layer;a protective layer formed on top of the low-κ layer and the electrode layer and having an opening reaching the electrode layer;a first solder layer filling the opening and formed on top of the electrode layer inside the opening;a second solder layer formed on top of the first solder layer and having an elastic modulus smaller than the first solder layer; anda support layer connected to the second solder layer and supporting the semiconductor substrate;wherein the protective layer has a greater elastic modulus and a smaller thermal expansion coefficient than an underfill layer formed between the protective layer and the support layer.2. The mounting structure according to claim 1 , wherein the underfill layer is formed between the protective layer and the support layer.3. The mounting structure according to claim 1 , wherein the protective layer is made of a same material as the support layer.4. The ...

SEMICONDUCTOR STRUCTURES AND METHODS OF MANUFACTURE

Wire-bonded semiconductor structures using organic insulating material and methods of manufacture are disclosed. The method includes forming a metal wiring layer in an organic insulator layer. The method further includes forming a protective layer over the organic insulator layer. The method further includes forming a via in the organic insulator layer over the metal wiring layer. The method further includes depositing a metal layer in the via and on the protective layer. The method further includes patterning the metal layer with an etch chemistry that is damaging to the organic insulator layer. 1. A method , comprising:forming an organic insulator layer on an underlying substrate, using a spin on technique;forming a wiring layer in a patterned section of the organic insulator layer using an electroplating process;forming a protective layer over the organic insulator layer;forming a via in the organic insulator layer using an etching chemistry that minimizes damage to the organic insulator layer, the via being in alignment with the wiring layer;depositing an Al layer in the via and on the protective layer;patterning the Al layer with a chlorine etch chemistry to form at least a bond structure;forming an insulating layer over the bond structure; andforming a via structure to the patterned metal layer.2. The method of claim 1 , further comprising forming a layer over the wiring layer claim 1 , and under the organic insulator layer claim 1 , wherein:the Al layer is formed by a blanket deposition process; andthe forming of the via exposes the wiring layer.3. The method of claim 1 , wherein the organic insulator layer is one of polyimide claim 1 , BCB (Benzocyclobutene) and PBO (polybenzoxazole).4. The method of claim 1 , further comprising removing exposed portions of the protective layer using a fluorine based etching process that minimizes damage to the organic insulator layer claim 1 , after the patterning.5. The method of claim 4 , wherein the protective layer is a ...

Semiconductor product with interlocking metal-to-metal bonds and method for manufacturing thereof

A structure and method for performing metal-to-metal bonding in an electrical device. For example and without limitation, various aspects of this disclosure provide a structure and method that utilize an interlocking structure configured to enhance metal-to-metal bonding.

METHOD OF FORMING SEMICONDUCTOR DEVICE HAVING A DUAL MATERIAL REDISTRIBUTION LINE AND SEMICONDUCTOR DEVICE

A method of making a semiconductor device includes depositing a second conductive material over a first conductive material, wherein the second conductive material is different from the first conductive material, and the second conductive material defines a redistribution line (RDL). The method further includes depositing a passivation layer over the RDL, wherein depositing the passivation layer comprises forming a plurality of convex sidewalls, and each of the plurality of convex sidewalls extends beyond an edge of the RDL. 1. A method of making a semiconductor device , the method comprising:depositing a second conductive material over a first conductive material, wherein the second conductive material is different from the first conductive material, and the second conductive material defines a redistribution line (RDL); anddepositing a passivation layer over the RDL, wherein depositing the passivation layer comprises forming a plurality of convex sidewalls, and each of the plurality of convex sidewalls extends beyond an edge of the RDL.2. The method of claim 1 , wherein depositing the second conductive material comprises depositing aluminum.3. The method of claim 1 , further comprising depositing the first conductive material over an interconnect structure.4. The method of claim 3 , wherein depositing the first conductive material comprises depositing a copper containing material.5. The method of claim 1 , further comprising patterning the second conductive material to define the RDL.6. The method of claim 1 , wherein depositing the passivation layer comprises depositing the passivation layer to define a flat top surface of the passivation layer over the RDL.7. The method of claim 1 , wherein depositing the passivation layer comprises depositing the passivation layer to a thickness ranging from about 200 nanometers (nm) to about 2 claim 1 ,000 nm.8. A method of making a semiconductor device claim 1 , the method comprising:plating a first conductive material over ...

Strong, heat stable junction

Provided among other things is an electrical device comprising: a first component that is a semiconductor or an electrical conductor; a second component that is an electrical conductor; and a strong, heat stable junction there between including an intermetallic bond formed of: substantially (a) indium (In), tin (Sn) or a mixture thereof, and (b) substantially nickel (Ni). The junction can have an electrical contact resistance that is small compared to the resistance of the electrical device.

SEMICONDUCTOR DEVICES, SEMICONDUCTOR PACKAGES, AND METHODS OF MANUFACTURING THE SEMICONDUCTOR DEVICES

A semiconductor device includes a conductive component on a substrate, a passivation layer on the substrate and including an opening that exposes at least a portion of the conductive component, and a pad structure in the opening and located on the passivation layer, the pad structure being electrically connected to the conductive component. The pad structure includes a lower conductive layer conformally extending on an inner sidewall of the opening, the lower conductive layer including a conductive barrier layer, a first seed layer, an etch stop layer, and a second seed layer that are sequentially stacked, a first pad layer on the lower conductive layer and at least partially filling the opening, and a second pad layer on the first pad layer and being in contact with a peripheral portion of the lower conductive layer located on the top surface of the passivation layer. 1. A semiconductor device comprising:a conductive component on a substrate;a passivation layer on the substrate and including an opening therein, wherein the opening exposes at least a portion of the conductive component; and a lower conductive layer conformally extending on an inner sidewall of the opening and on a top surface of the passivation layer around the opening, the lower conductive layer including a conductive barrier layer, a first seed layer, an etch stop layer, and a second seed layer that are sequentially stacked,', 'a first pad layer on the lower conductive layer, the first pad layer at least partially filling the opening, and', 'a second pad layer on the first pad layer, the second pad layer laterally extending beyond the first pad layer to contact a peripheral portion of the lower conductive layer located on the top surface of the passivation layer., 'a pad structure on the passivation layer and in the opening, the pad structure electrically connected to the conductive component, the pad structure comprising2. The semiconductor device of claim 1 , wherein the second pad layer is ...

Bonded assembly containing oxidation barriers, hybrid bonding, or air gap, and methods of forming the same

At least one polymer material may be employed to facilitate bonding between the semiconductor dies. Plasma treatment, formation of a blended polymer, or formation of polymer hairs may be employed to enhance bonding. Alternatively, air gaps can be formed by subsequently removing the polymer material to reduce capacitive coupling between adjacent bonding pads.

Semiconductor Die Singulation and Structures Formed Thereby

An embodiment method includes providing a wafer including a first integrated circuit die, a second integrated circuit die, and a scribe line region between the first integrated circuit die and the second integrated circuit die. The method further includes forming a kerf in the scribe line region and after forming the kerf, using a mechanical sawing process to fully separate the first integrated circuit die from the second integrated circuit die. The kerf extends through a plurality of dielectric layers into a semiconductor substrate. 1. A method comprising:receiving a wafer comprising:a first integrated circuit die;a second integrated circuit die; anda scribe line region between the first integrated circuit die and the second integrated circuit die; andforming a kerf in the scribe line region, wherein the kerf extends through a plurality of dielectric layers into a semiconductor substrate, and wherein the kerf comprises:a first width at an interface between the plurality of dielectric layers and the semiconductor substrate; anda second width at a surface of the plurality of dielectric layers opposite the semiconductor substrate, wherein a ratio of the first width to the second width is at least about 0.6.2. The method of claim 1 , wherein an angle between a bottom surface of the kerf and a sidewall of the kerf is about 90° to about 135°.3. The method of further comprising after forming the kerf claim 1 , using a mechanical sawing process to fully separate the first integrated circuit die from the second integrated circuit die.4. The method of claim 3 , wherein the mechanical sawing process comprises using a saw blade having a third width claim 3 , wherein the third width is less than the first width.5. The method of claim 1 , wherein forming the kerf in the scribe line region comprises a laser ablation process.6. The method of claim 5 , wherein the laser ablation process further forms a recast region on a sidewall of the plurality of dielectric layers and a sidewall ...

Semiconductor structure and manufacturing method thereof

The present disclosure provides a semiconductor structure. The semiconductor structure comprises a semiconductive substrate and an interconnect structure over the semiconductive substrate. The semiconductor structure also comprises a bond pad in the semiconductive substrate and coupled to the metal layer. The bond pad comprises two conductive layers.

METHOD OF ELECTROPLATING PHOTORESIST DEFINED FEATURES FROM COPPER ELECTROPLATING BATHS CONTAINING REACTION PRODUCTS OF IMIDAZOLE AND BISEPOXIDE COMPOUNDS

Electroplating methods enable the plating of photoresist defined features which have substantially uniform morphology. The electroplating methods include copper electroplating baths with reaction products of imidazole and bisepoxides to electroplate the photoresist defined features. Such features include pillars, bond pads and line space features. 1. A method of electroplating photoresist defined features comprising:a) providing a substrate comprising a layer of photoresist, wherein the layer of photoresist comprises a plurality of apertures;b) providing a copper electroplating bath comprising one or more reaction products of one or more imidazole compounds and one or more bisepoxides; an electrolyte; one or more accelerators; and one or more suppressors;c) immersing the substrate comprising the layer of photoresist with the plurality of apertures in the copper electroplating bath; andd) electroplating a plurality of copper photoresist defined features in the plurality of apertures, the plurality of photoresist defined features comprise an average % TIR of 5% to 8%.2. The method of claim 1 , wherein a % WID of the plurality of photoresist defined features is from 5% to 12%.4. The method of claim 3 , wherein R claim 3 , Rand Rare independently chosen from hydrogen and (C-C)alkyl.6. The method of claim 1 , wherein the reaction product is in amounts of 0.25 ppm to 20 ppm.7. The method of claim 1 , wherein electroplating is done at a current density of 0.25 ASD to 40 ASD.8. The method of claim 1 , wherein the one or more copper photoresist defined features are pillars claim 1 , bond pads or line space features.9. An array of photoresist defined features on a substrate comprising an average % TIR of 5% to 8% and a % WID of 5% to 12%. The present invention is directed to a method of electroplating photoresist defined features from copper electroplating baths which include reaction products of imidazole and bisepoxide compounds. More specifically, the present invention is ...

METHOD OF ELECTROPLATING PHOTORESIST DEFINED FEATURES FROM COPPER ELECTROPLATING BATHS CONTAINING REACTION PRODUCTS OF ALPHA AMINO ACIDS AND BISEPOXIDES

Electroplating methods enable the plating of photoresist defined features which have substantially uniform morphology. The electroplating methods include copper electroplating baths with reaction products of α-amino acids and bisepoxides to electroplate the photoresist defined features. Such features include pillars, bond pads and line space features. 1. A method comprising:a) providing a substrate comprising a layer of photoresist, wherein the layer of photoresist comprises a plurality of apertures;b) providing a copper electroplating bath comprising one or more reaction products of one or more α-amino acids and one or more bisepoxides; an electrolyte; one or more accelerators; and one or more suppressors;c) immersing the substrate comprising the layer of photoresist with the plurality of apertures in the copper electroplating bath; andd) electroplating a plurality of copper photoresist defined features in the plurality of apertures, the plurality of photoresist defined features comprise an average % TIR of -5% to -1%.2. The method of claim 1 , wherein an average % WID of an array of copper photoresist defined features on the substrate is 12% to 15%.3. The method of claim 1 , wherein the one or more α-amino acids are chosen from arginine and lysine.6. The method of claim 1 , wherein the one or more reaction products are in amounts of 0.25 ppm to 20 ppm in the copper electroplating bath.7. The method of claim 1 , wherein electroplating is done at a current density of 0.25 ASD to 40 ASD.8. The method of claim 1 , wherein the one or more copper photoresist defined features are pillars claim 1 , bond pads or line space features.9. A plurality of photoresist defined features on a substrate comprising an average % TIR of −5% to −1% and an average % WID of 12% to 15%. The present invention is directed to a method of electroplating photoresist defined features from copper electroplating baths which include reaction products of α-amino acids and bisepoxides. More ...

SYSTEMS AND METHODS TO FABRICATE A RADIO FREQUENCY INTEGRATED CIRCUIT

To reduce radio frequency (RF) losses during operation of a radio frequency integrated circuit (RFIC) module, the RFIC module is fabricated such that at least one of an edge of the wirebond pad on the copper trace and a sidewall of the copper trace is free from high-resistivity plating material. The unplated portion provides a path for the RF current to flow around the high-resistivity material, which reduces the RF signal loss associated with the high resistivity plating material. 1. A method to fabricate a radio frequency integrated circuit (RFIC) module , the method comprising:plating a nickel layer over a portion of a top surface of a copper trace, the copper trace including at least a sidewall and formed on a substrate;plating a palladium layer over the nickel layer; andplating a gold layer over the palladium layer, the nickel, palladium, and gold layers forming a wire bonding pad that covers a plated portion of the copper trace leaving an unplated portion of the copper trace that is substantially parallel to the wire bonding pad along the sidewall, the unplated portion forming an unplated path along the copper trace and configured to conduct radio frequency (RF) current during operation of the RFIC module and reduce RF power loss.2. The method of wherein the nickel layer is between about 1 micron and about 10 microns.3. The method of wherein the palladium layer is between about 0.01 microns and about 1 micron.4. The method of wherein the gold layer is between about 0.01 microns and about 1 micron.5. The method of wherein the unplated portion of the copper trace is free from the nickel claim 1 , palladium claim 1 , and gold layers.6. The method of further comprising expanding a width of the copper trace to accommodate the wire bonding pad such that at least the sidewall of the copper trace is free from the nickel claim 1 , palladium claim 1 , and gold layers to maintain the unplated path on the copper trace to conduct the RF current.7. The method of further ...

METHOD OF ELECTROPLATING PHOTORESIST DEFINED FEATURES FROM COPPER ELECTROPLATING BATHS CONTAINING REACTION PRODUCTS OF PYRIDYL ALKYLAMINES AND BISEPOXIDES

Electroplating methods enable the plating of photoresist defined features which have substantially uniform morphology. The electroplating methods include copper electroplating baths with reaction products of pyridyl alkylamines and bisepoxides to electroplate the photoresist defined features. Such features include pillars, bond pads and line space features. 1. A method for electroplating photoresist defined features comprising:a) providing a substrate comprising a layer of photoresist, wherein the layer of photoresist comprises a plurality of apertures;b) providing a copper electroplating bath comprising one or more reaction products of one or more pyridyl alkylamines and one or more bisepoxides; an electrolyte; one or more accelerators; and one or more suppressors;c) immersing the substrate comprising the layer of photoresist with the plurality of apertures in the copper electroplating bath; andd) electroplating a plurality of copper photoresist defined features in the plurality of apertures, the plurality of photoresist defined features comprise an average % TIR of −5% to +12%.2. The method of claim 1 , wherein a % WID of the plurality of photoresist defined features is from 5% to 14%.6. The method of claim 1 , wherein the one or more reaction products are in amounts of 0.25 ppm to 20 ppm in the copper electroplating bath.7. The method of claim 1 , wherein the one or more photoresist defined features is chosen from a pillar claim 1 , bond pad and line space feature.8. The method of claim 1 , wherein a current density is from 0.25 ASD to 40 ASD.9. An array of photoresist defined features on a substrate comprising an average % TIR of −5% to +12% and a % WID of 5% to 14%. The present invention is directed to a method of electroplating photoresist defined features from copper electroplating baths which include reaction products of pyridyl alkylamines and bisepoxides. More specifically, the present invention is directed to a method of electroplating photoresist defined ...

Support structure for mems device with particle filter

Various embodiments of the present disclosure are directed towards a microphone including a support structure layer disposed between a particle filter and a microelectromechanical systems (MEMS) structure. A carrier substrate is disposed below the particle filter and has opposing sidewalls that define a carrier substrate opening. The MEMS structure overlies the carrier substrate and includes a diaphragm having opposing sidewalls that define a diaphragm opening overlying the carrier substrate opening. The particle filter is disposed between the carrier substrate and the MEMS structure. A plurality of filter openings extend through the particle filter. The support structure layer includes a support structure having one or more segments spaced laterally between the opposing sidewalls of the carrier substrate. The one or more segments of the support structure are spaced laterally between the plurality of filter openings.

SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor substrate and a metal film formed on the semiconductor substrate. The metal film includes a Ni base and a material having condensation energy higher than that of Ni. In a method of manufacturing a semiconductor device, a semiconductor substrate and a target, which is formed by melting P in Ni, are prepared, and sputtering is performed with the target while a portion of the semiconductor substrate where the metal film is to be formed is heated to a temperature of from 280° C. inclusive to 870° C. inclusive. 1. A semiconductor device comprising:a semiconductor substrate; anda metal film formed on the semiconductor substrate, whereinthe metal film includes a Ni base and a material having condensation energy higher than that of Ni.2. The semiconductor device according to claim 1 , whereinthe material having condensation energy higher than that of Ni is any of Sc, Ti, V, Cr, Fe, Co, Zr, Nb, Mo, Hf, Ta, W, B, and P.3. The semiconductor device according to claim 1 , wherein{'sub': x', 'y, 'the material having condensation energy higher than that of Ni is a stoichiometric material represented by NiP, where each of x and y is an integer.'}4. The semiconductor device according to claim 1 , wherein{'sub': '3', 'the material having condensation energy higher than that of Ni is a NiP particle.'}5. The semiconductor device according to claim 4 , wherein{'sub': '3', 'the NiP particle is uniformly distributed in the Ni base.'}6. The semiconductor device according to claim 1 , further comprising:another metal film made of Al or Cu and located between the semiconductor substrate and the metal film, the other metal film being in contact with the metal film.7. The semiconductor device according to claim 1 , further comprising:another metal film made of Ti and located between the semiconductor substrate and the metal film, the other metal film being in contact with the metal film.8. The semiconductor device according to claim 1 , further ...

Interconnect Structure and Method of Forming Same

A device includes a first side interconnect structure over a first side of a substrate, wherein active circuits are in the substrate and adjacent to the first side of the substrate, a dielectric layer over a second side of the substrate, a pad embedded in the dielectric layer, the pad comprising an upper portion and a bottom portion formed of two different materials and a passivation layer over the dielectric layer. 1. A device comprising:a dielectric layer on a first side of a semiconductor substrate;a first redistribution line in a first recess in the dielectric layer, the first redistribution line comprising a first layer, the first layer completely filling the first recess;a contact pad in a second recess in the dielectric layer, wherein a width of the contact pad is greater than a width of a first redistribution line, wherein the contact pad comprises a second layer and a third layer over the second layer, wherein the second layer and the first layer are a same material, wherein the second layer and the third layer completely fills the second recess, the second layer and the third layer comprising different materials; anda passivation layer over the dielectric layer.2. The device of further comprising a transistor on a second side of the semiconductor substrate.3. The device of further comprising:a front-side interconnect structure on the second side of the semiconductor substrate; anda through via extending from a conductive feature in the front-side interconnect structure through the semiconductor substrate to the first side of the semiconductor substrate, wherein the contact pad is electrically coupled to the through via.4. The device of claim 3 , wherein the contact pad directly contacts the through via.5. The device of claim 1 , wherein the dielectric layer is interposed between the contact pad and the first side of the semiconductor substrate.6. The device of further comprising a passivation layer over the dielectric layer.7. The device of claim 6 , ...

Semiconductor device

A semiconductor device includes an N-type semiconductor substrate comprising silicon, an N-type low-concentration impurity layer that is in contact with the upper surface of the N-type semiconductor substrate, a metal layer that is in contact with the entire lower surface of the N-type semiconductor substrate and has a thickness of at least 20 μm, and first and second vertical MOS transistors formed in the low-concentration impurity layer. The ratio of the thickness of the metal layer to the thickness of a semiconductor layer containing the N-type semiconductor substrate and the low-concentration impurity layer is greater than 0.27. The semiconductor device further includes a support comprising a ceramic material and bonded to the entire lower surface of the metal layer only via a bonding layer.

SEMICONDUCTOR PACKAGE WITH EMBEDDED DIE AND ITS METHODS OF FABRICATION

Embodiments of the present invention describe a semiconductor package having an embedded die. The semiconductor package comprises a coreless substrate that contains the embedded die. The semiconductor package provides die stacking or package stacking capabilities. Furthermore, embodiments of the present invention describe a method of fabricating the semiconductor package that minimizes assembly costs. 1. A method of forming a semiconductor package comprising:providing a carrier having a conductive surface;forming a first dielectric layer on the conductive surface of the carrier, the first dielectric layer having a die cavity exposing a die region on the conductive surface;forming a layer of adhesive on the die region of the conductive surface;attaching a die onto the layer of adhesive, the die having a back side secured to the layer of adhesive, and a front side having a plurality of die pads;depositing a second dielectric layer onto the first dielectric layer and the die;forming a plurality of die interconnects on the plurality of die pads at the front side of the die; andremoving the carrier to expose the layer of adhesive.2. The method of claim 1 , wherein forming the first dielectric layer further comprises:forming a plurality of pad openings in the first dielectric layer, the plurality of pad openings exposing a plurality of pad regions on the conductive surface;forming a plurality of package pads on the plurality of pad regions of the conductive surface; andforming a plurality of package interconnects on the plurality of package pads.3. The method of claim 2 , wherein the first dielectric layer is a photo-definable dielectric material.4. The method of claim 3 , wherein the first dielectric layer is formed by:laminating the photo-definable dielectric material onto the conductive surface; andexposing the first dielectric layer to a radiation source and developing the first dielectric layer to define the die cavity and the plurality of pad openings in the first ...

FABRICATION METHOD OF PACKAGING SUBSTRATE

A packaging substrate and a semiconductor package using the packaging substrate are provided. The packaging substrate includes: a substrate body having a die attach area, a circuit layer formed around the die attach area and having a plurality of conductive traces each having a wire bonding pad, and a surface treatment layer formed on the wire bonding pads. Therein, only one of the conductive traces is connected to an electroplating line so as to prevent cross-talk that otherwise occurs between conductive traces due to too many electroplating lines in the prior art. 114-. (canceled)15. A fabrication method of a packaging substrate , comprising the steps of:providing a substrate body having a die attach area and a circuit layer formed around the die attach area, wherein the circuit layer has a plurality of conductive traces each having a first end positioned adjacent to the die attach area and an apposing second end positioned away from the die attach area, each of the first ends has a wire bonding pad, the second end of at least one of the conductive traces at at least one side of the die attach area is connected to an electroplating line, and the electroplating lines and the wire bonding pads at the same side of the die attach area are different in number;forming a conductive layer at an edge of the die attach area between the die attach area and the circuit layer, and electrically connecting the conductive layer to the conductive traces;performing an electroplating process through the conductive layer and the electroplating line so as to form a surface treatment layer on the wire bonding pads; andremoving the conductive layer.16. The package of claim 15 , wherein each of the wire bonding pads is connected to an extending line so as to be connected to the conductive layer.17. The method of claim 15 , wherein the conductive layer is removed by laser claim 15 , a chemical solution or a scraper.18. The method of claim 15 , further comprising forming an adhesive layer ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A flip-chip mounting technique with high reliability is provided in flip-chip mounting using a Cu pillar. In a semiconductor device to be coupled to a mounting board via a Cu pillar, the Cu pillar is caused to have a laminated structure including a pillar layer, a barrier layer, and a bump in this order from below, and the bump is formed to be smaller than the barrier layer. 1. A manufacturing method of a semiconductor device , comprising the steps of:(a) applying a resist film over a terminal pad formed over a main surface of a semiconductor substrate;(b) forming an opening in the resist film for exposing the terminal pad in the bottom thereof;(c) forming a Cu film, an Ni film, and an SnAg film in the opening in this order from below;(d) removing the resist film; and(e) etching an outer peripheries of the SnAg film.2. The manufacturing method of a semiconductor device according to claim 1 ,wherein, in the step (e), the etching is performed by using dilute hydrofluoric acid.3. The manufacturing method of a semiconductor device according to claim 1 ,wherein, in the step (b), the forming the opening is performed by using photolithography.4. The manufacturing method of a semiconductor device according to claim 1 ,wherein, in the step (c), the Cu film, the Ni film, and the SnAg film are formed by electrolytic plating.5. The manufacturing method of a semiconductor device according to claim 1 ,wherein, in the step (d), the resist film is removed by ashing.6. The manufacturing method of a semiconductor device according to claim 1 ,wherein, in the step (e), the outer peripheries of the SnAg film is wet etched.7. A manufacturing method of a semiconductor device claim 1 , comprising the steps of:(a) applying a first resist film over a terminal pad formed over a main surface of a semiconductor substrate;(b) forming a first opening in the first resist film for exposing the terminal pad in the bottom thereof;(c) forming a Cu film and an Ni film in this order from below;(d) ...

INTEGRATED CIRCUIT INCLUDING WIRE STRUCTURE AND RELATED METHOD

An integrated circuit (IC), design structure, and a method of making the same. In one embodiment, the IC includes: a substrate; a dielectric layer disposed on the substrate; a set of wire components disposed on the dielectric layer, the set of wire components including a first wire component disposed proximate a second wire component; a bond pad disposed on the first wire component, the bond pad including an exposed portion; a passivation layer disposed on the dielectric layer about a portion of the bond pad and the set of wire components, the passivation layer defining a wire structure via connected to the second wire component; and a wire structure disposed on the passivation layer proximate the bond pad and connected to the second wire component through the wire structure via. 1. A method , comprising:forming a dielectric layer on a substrate;forming a metal layer on the dielectric layer;forming a set of wire components from the metal layer, the set of wire components including a first wire component proximate a second wire component;depositing a bond pad on the first wire component;forming a passivation layer on the dielectric layer and about portions of the set of wire components, the passivation layer including a wire component via connected to the second wire component; andforming a wire structure above the second wire component and physically isolated from the bond pad.2. The method of claim 1 , wherein the forming the wire structure includes patterned plating of copper on at least one of the dielectric layer and the set of wire components.3. The method of claim 1 , further comprising forming a diffusion barrier on at least one of the set of wire components following the forming of the passivation layer.4. The method of claim 3 , wherein the diffusion barrier is self-aligning.5. The method of claim 1 , further comprising:depositing a pattern resist on the bond pad following the depositing of the bond pad, the pattern resist configured to prevent formation of ...

FIRST WAFER, FABRICATING METHOD THEREOF AND WAFER STACK

A first wafer, a method of fabricating thereof and a wafer stack are disclosed. The first wafer includes a first substrate, a first dielectric layer on the first substrate, first metal layers embedded in the first dielectric layer, first switching holes extending partially through the first dielectric layer and exposing the first metal layers, a first interconnection layer filling up the first switching holes and electrically connected to the first metal layers, a first insulating layer residing on surfaces of both the first dielectric layer and the first interconnection layer, first contact holes extending through the first insulating layer and exposing the first interconnection layer, and a second interconnection layer filling up the first contact holes and electrically connected to the first interconnection layer. Filling the first contact holes and the first switching holes with different interconnection layers reduces the difficulty in fabricating interconnection structures for the first metal layers. 1. A first wafer , comprising:a first substrate, a first dielectric layer on the first substrate, first metal layers embedded in the first dielectric layer, first switching holes extending partially through the first dielectric layer and exposing the first metal layers, a first interconnection layer filling up the first switching holes and electrically connected to the first metal layers, a first insulating layer on surfaces of both the first dielectric layer and the first interconnection layer, first contact holes extending through the first insulating layer and exposing the first interconnection layer, and a second interconnection layer filling up the first contact holes and electrically connected to the first interconnection layer.2. The first wafer of claim 1 , wherein the first interconnection layer is made of a material comprising tungsten claim 1 , and wherein the second interconnection layer is made of a material comprising copper.3. The first wafer of ...

Semiconductor Device and Method for Forming Openings and Trenches in Insulating Layer by First LDA and Second LDA for RDL Formation

A semiconductor device has a semiconductor die with an encapsulant deposited over the semiconductor die. A first insulating layer having high tensile strength and elongation is formed over the semiconductor die and encapsulant. A first portion of the first insulating layer is removed by a first laser direct ablation to form a plurality of openings in the first insulating layer. The openings extend partially through the first insulating layer or into the encapsulant. A second portion of the first insulating layer is removed by a second laser direct ablation to form a plurality of trenches in the first insulating layer. A conductive layer is formed in the openings and trenches of the first insulating layer. A second insulating layer is formed over the conductive layer. A portion of the second insulating layer is removed by a third laser direct ablation. Bumps are formed over the conductive layer.

SIDE WETTABLE PACKAGE AND METHOD FOR MANUFACTURING THE SAME

A side wettable package includes a molding compound, a chip and multiple conductive pads exposed from a bottom surface of the molding compound. The conductive pads include peripheral conductive pads arranged near a side wall of the molding compound. Each of the peripheral conductive pads is over etched to form an undercut. When the side wettable package is connected to a circuit board via solder, the solder ascends to the undercut of the peripheral conductive pads for improving connection yield and facilitating inspection of soldering quality. 1. A side wettable package comprising:a molding compound having a bottom surface and a side wall;a chip encapsulated in the molding compound; anda plurality of conductive pads electrically connected to the chip with each conductive pad being partially embedded in the molding compound and exposed from the bottom surface of the molding compound; wherein the plurality of conductive pads comprises multiple peripheral conductive pads distributed near the side wall of the molding compound, and each of the peripheral conductive pads has a side surface and forms an undercut on the side surface; wherein each undercut has a concave surface curved inward relative to the side wall of the molding compound and having a height equal to a thickness of the peripheral conductive pads.2. The side wettable package as claimed in claim 1 , wherein a protection cover is formed to cover each of the conductive pads exposed from the bottom surface of the molding compound and the concave surface of each undercut.3. The side wettable package as claimed in claim 2 , wherein a top most edge of the concave surface of each undercut abuts the molding compound.4. The side wettable package as claimed in claim 2 , wherein the undercut of each peripheral conductive pad is formed by an over etching process.5. The side wettable package as claimed in claim 2 , wherein the chip is a diode chip.6. A method for manufacturing a side wettable package claim 2 , the method ...

SEMICONDUCTOR COPPER METALLIZATION STRUCTURE AND RELATED METHODS

Implementations of semiconductor packages may include: a silicon die including a pad, the pad including aluminum and copper; a passivation layer over at least a portion of the silicon die and a layer of one of a polyimide (PI) a polybenzoxazole (PBO), or a polymer resin coupled to the passivation layer. The package may include a first copper layer coupled over the pad, the first copper layer being about 1 microns to about 20 microns thick; a second copper layer coupled over the first copper layer, the second copper layer may be about 5 microns to about 40 microns thick; where a width of the first copper layer above the pad may be wider than a width of the second copper layer above the pad. The first and second copper layers may be configured to bond with a heavy copper wire or solder with a copper clip. 1. A semiconductor package comprising:a silicon die comprising a pad, the pad comprising one of aluminum copper (AlCu); aluminum copper silicon (AlCuSi); aluminum copper tungsten (AlCuW); aluminum silicon (AlSi); and any combination thereof;a passivation layer over at least a portion of the silicon die;a layer of one of a polyimide (PI), a polybenzoxazole (PBO), a polymer resin, and any combination thereof coupled to the passivation layer;a first copper layer coupled directly over and to the pad and at least a portion of the layer of one of a polyimide (PI), a polybenzoxazole (PBO), a polymer resin, and any combination thereof, the first copper layer being 1 microns to 20 microns thick; anda second copper layer coupled over the first copper layer, the second copper layer being 5 microns to 40 microns thick;wherein a width of the first copper layer above the pad is wider than a width of the second copper layer above the pad; andwherein the first and second copper layers are configured to one of bond with a heavy copper wire and solder with a copper clip.2. A semiconductor package of claim 1 , wherein the heavy copper wire is more than 5 mil in diameter.3. The ...

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a first carrier including a first pad, a second carrier including a second pad disposed opposite to the first pad, a joint coupled with and standing on the first pad, a joint encapsulating the post and bonding the first pad with the second pad, a first entire contact interface between the first pad and the joint, a second entire contact interface between the first pad and the post, and a third entire contact interface between the joint and the second pad. The first entire contact interface, the second entire contact interface and the third entire contact interface are flat surfaces. A distance between the first entire contact interface and the third entire contact interface is equal to a distance between the second entire contact interface and the third entire contact interface. The second entire contact interface is a continuous surface. 1. A semiconductor device , comprising:a silicon substrate;a carrier;a first pad on the silicon substrate;a second pad on the carrier;a post on a surface of the first pad, wherein the post consists of a metal or a metal alloy;a joint disposed between the silicon substrate and the carrier, contacted with the first pad and the second pad, and encapsulating the post;a first entire contact interface between the first pad and the joint;a second entire contact interface between the first pad and the post; anda third entire contact interface between the joint and the second pad,wherein an outer surface of the joint is concaved and curved towards the post, and a height of the post is greater than or equal to ⅓ of a height of the joint between the first pad and the second pad, the first entire contact interface, the second entire contact interface and the third entire contact interface are flat surfaces, wherein a distance between the first entire contact interface and the third entire contact interface is equal to a distance between the second entire contact interface and the third entire contact interface, ...

CHEMICAL MECHANICAL POLISHING FOR HYBRID BONDING

Representative implementations of techniques and methods include chemical mechanical polishing for hybrid bonding. The disclosed methods include depositing and patterning a dielectric layer on a substrate to form openings in the dielectric layer, depositing a barrier layer over the dielectric layer and within a first portion of the openings, and depositing a conductive structure over the barrier layer and within a second portion of the openings not occupied by the barrier layer, at least a portion of the conductive structure in the second portion of the openings coupled or contacting electrical circuitry within the substrate. Additionally, the conductive structure is polished to reveal portions of the barrier layer deposited over the dielectric layer and not in the second portion of the openings. Further, the barrier layer is polished with a selective polish to reveal a bonding surface on or at the dielectric layer. 1. (canceled)2. A method comprising:forming one or more openings in a dielectric layer of a substrate, the one or more openings extending at least partially through the dielectric layer from a surface of the dielectric layer, a width of at least one of the one or more openings being at least 5 microns;forming a barrier layer over the surface of the dielectric layer and surfaces of the openings;forming a conductive structure disposed over the barrier layer and in the openings;polishing at least a portion of the conductive structure to reveal a surface of the barrier layer; andpolishing the barrier layer to reveal a planar dielectric bonding surface with a surface roughness of less than 1 nm root mean square (RMS), the conductive structure is recessed less than 25 nm from the dielectric bonding surface.3. A method according to claim 2 , wherein the substrate is a first substrate claim 2 , the method further comprising directly bonding the planar dielectric bonding surface of the first substrate to a prepared planar bonding surface of a second substrate.4. ...

Preform structure for soldering a semiconductor chip arrangement, a method for forming a preform structure for a semiconductor chip arrangement, and a method for soldering a semiconductor chip arrangement

A preform structure for soldering a semiconductor chip arrangement includes a carbon fiber composite sheet and a solder layer formed over the carbon fiber composite sheet.

Die-on-Interposer Assembly with Dam Structure and Method of Manufacturing the Same

A semiconductor package includes an interposer chip having a frontside, a backside, and a corner area on the backside defined by a first corner edge and a second corner edge of the interposer chip. A die is bonded to the frontside of the interposer chip. At least one dam structure is formed on the corner area of the backside of the interposer chip. The dam structure includes an edge aligned to at least one the first corner edge and the second corner edge of the interposer chip. 1. A package comprising:a substrate having a frontside and a backside, the substrate comprising four corner areas;a die bonded to the frontside of the substrate by a first set of conductive connectors;a molding layer on the frontside of the substrate and surrounding sidewalls of the die;a dam structure in each of the four corner areas on the backside of the substrate, each of the dam structures being at least a part of a circle in a plane parallel to the backside of the substrate; anda second set of conductive connectors on the backside of the substrate.2. The package of further comprising:a through via extending through the substrate, at least one of the second set of conductive connectors being electrically coupled to the through via; andan interconnect structure formed on the frontside of the substrate and electrically coupled to the through via, the die being electrically coupled to the interconnect structure.3. The package of claim 1 , wherein each of the dam structures comprise an edge aligned with an outer edge of the substrate.4. The package of claim 1 , wherein the dam structures comprise a polymer material.5. The package of claim 1 , wherein the molding layer comprises a polymer.6. The package of claim 1 , wherein the dam structures are not electrically coupled to the through via.7. The package of claim 1 , wherein a first corner area of the four corner areas is defined by a first corner edge and a second corner edge of the substrate claim 1 , an intersection of the first corner ...

INTEGRATED CIRCUIT DIE AND MANUFACTURE METHOD THEREOF

The present invention provide an IC die, including an underlay; an active component; an interconnection layer, covering the active component, where the interconnection layer includes multiple metal layers and multiple dielectric layers, the multiple metal layers and the multiple dielectric layers are alternately arranged, a metal layer whose distance to the active component is the farthest in the multiple metal layers includes metal cabling and a metal welding pad; and a heat dissipation layer, where the heat dissipation layer covers a region above the interconnection layer except a position corresponding to the metal welding pad, the heat dissipation layer is located under a package layer, the package layer includes a plastic packaging material, and the heat dissipation layer includes an electrical-insulating material whose heat conductivity is greater than a preset value. 1. An integrated circuit die , comprising:an underlay;an active component;an interconnection layer, covering the active component, wherein the interconnection layer comprises multiple metal layers and multiple dielectric layers, the multiple metal layers and the multiple dielectric layers are alternately arranged, a metal layer whose distance to the active component is the farthest in the multiple metal layers comprises metal cabling and a metal welding pad; anda heat dissipation layer, wherein the heat dissipation layer covers a region above the interconnection layer except a position corresponding to the metal welding pad, the heat dissipation layer is located under a package layer, the package layer comprises a plastic packaging material, and the heat dissipation layer comprises an electrical-insulating material whose heat conductivity is greater than a preset value.2. The integrated circuit die according to claim 1 , wherein the heat dissipation layer covers the metal layer whose distance to the active component is the farthest.3. The integrated circuit die according to claim 1 , wherein the ...

Semiconductor Device and Method of Forming a POP Device with Embedded Vertical Interconnect Units

A semiconductor device has a substrate. A plurality of conductive vias is formed through the substrate. A conductive layer is formed over the substrate. An insulating layer is formed over conductive layer. A portion of the substrate is removed to expose the conductive vias. A plurality of vertical interconnect structures is formed over the substrate. A first semiconductor die is disposed over the substrate. A height of the vertical interconnect structures is less than a height of the first semiconductor die. An encapsulant is deposited over the first semiconductor die and the vertical interconnect structures. A first portion of the encapsulant is removed from over the first semiconductor die while leaving a second portion of the encapsulant over the vertical interconnect structures. The second portion of the encapsulant is removed to expose the vertical interconnect structures. A second semiconductor die is disposed over the first semiconductor die. 1. A semiconductor device , comprising:a substrate including a conductive via formed through the substrate;a modular interconnect unit including a vertical interconnect structure disposed over the substrate;a first semiconductor die disposed over the substrate adjacent to the modular interconnect unit; andan encapsulant deposited around the first semiconductor die and over modular interconnect unit with an opening in the encapsulant extending to the modular interconnect unit.2. The semiconductor device of claim 1 , further including a second semiconductor die disposed over the first semiconductor die with a bump of the second semiconductor die within the opening of the encapsulant to contact the vertical interconnect structure.3. The semiconductor device of claim 1 , further including a first interconnect structure disposed between the substrate and modular interconnect unit.4. The semiconductor device of claim 3 , further including a second interconnect structure disposed between the first interconnect structure and ...

SEMICONDUCTOR DEVICE STRUCTURE AND MANUFACTURING METHOD

A semiconductor device structure and a manufacturing method are provided. The semiconductor device structure includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The semiconductor device structure also includes a conductive trace over the dielectric layer. The semiconductor device structure further includes a conductive feature over the conductive trace, and a width of the conductive feature is substantially equal to or larger than a maximum width of the conductive trace. In addition, the semiconductor device structure includes a conductive bump over the conductive feature. 1. A structure , comprising:a substrate;a conductive trace disposed over the substrate, the conductive trace including a first segment and a second segment that each extend in a first direction, wherein the first segment and the second segment have substantially equal dimensions measured in a second direction;a conductive layer disposed over the first segment, but not over the second segment, of the conductive trace, wherein a dimension of the conductive layer measured in the second direction is greater than the dimension of the first segment of the conductive trace; anda conductive bump disposed over the conductive layer.2. The structure of claim 1 , wherein the conductive bump is in direct contact with the conductive layer.3. The structure of claim 2 , wherein the conductive bump is separated from a sidewall of the conductive trace by the conductive layer.4. The structure of claim 1 , wherein the conductive bump and the conductive layer have similar top view profiles.5. The structure of claim 4 , wherein the conductive bump and the conductive layer each have rounded top view profiles.6. The structure of claim 1 , wherein the conductive trace is free of having a passivation layer formed thereon.7. The structure of claim 1 , wherein an entirety of the conductive trace has a uniform dimension measured in the second direction.8. The structure of claim 1 , ...

Multi-Stack Package-on-Package Structures

Multi-stack package-on-package structures are disclosed. In a method, a first stacked semiconductor device is formed on a first carrier wafer. The first stacked semiconductor device is singulated. The first stacked semiconductor device is adhered to a second carrier wafer. A second semiconductor device is attached on the first stacked semiconductor device. The second semiconductor device and the first stacked semiconductor device are encapsulated. Electrical connections are formed on and electrically coupled to the first stacked semiconductor device and the second semiconductor device.

Apparatus and method of manufacturing solder bump

An apparatus for forming a solder bump on a substrate including a supporter configured to support the substrate to be provided thereon, a housing surrounding the supporter, a cover defining a manufacturing space in combination with the housing and including an edge heating zone along a perimeter thereof, the manufacturing space surrounding the supporter, and an oxide remover supply nozzle configured to supply an oxide remover to the manufacturing space may be provided.

Package with ubm and methods of forming

Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes an integrated circuit die, an encapsulant at least laterally encapsulating the integrated circuit die, a redistribution structure on the integrated circuit die and the encapsulant, a connector support metallization coupled to the redistribution structure, a dummy pattern, a second dielectric layer, and an external connector on the connector support metallization. The redistribution structure comprises a first dielectric layer having a first surface disposed distally from the encapsulant and the integrated circuit die. The dummy pattern is on the first surface of the first dielectric layer and around the connector support metallization. The second dielectric layer is on the first surface of the first dielectric layer and on at least a portion of the dummy pattern. The second dielectric layer does not contact the connector support metallization.

INTERCONNECTION STRUCTURE OF A SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE INCLUDING THE INTERCONNECTION STRUCTURE

An interconnection structure of a semiconductor chip may include an interconnection via, a lower pad, a conductive bump, and an upper pad. The interconnection via may be arranged in the semiconductor chip. The lower pad may be arranged on a lower end of the interconnection via exposed through a lower surface of the semiconductor chip. The conductive bump may be arranged on the lower pad. The upper pad may be arranged on an upper end of the interconnection via exposed through an upper surface of the semiconductor chip. The upper pad may have a width wider than a width of the interconnection via and narrower than a width of the lower pad. Thus, an electrical short between the conductive bumps may not be generated in the interconnection structure having a thin thickness. 1. An interconnection structure of a semiconductor chip , the interconnection structure comprising:an interconnection via arranged in the semiconductor chip;a lower pad arranged on a lower end of the interconnection via exposed through a lower surface of the semiconductor chip;a conductive bump arranged on the lower pad; andan upper pad including a body pad arranged on an upper end of the interconnection via exposed through an upper surface of the semiconductor chip, and an interconnection pad arranged on an upper surface of the body pad,wherein the body pad has a width substantially the same as a width of the lower pad, and the interconnection pad has a width wider than a width of the interconnection via and narrower than the width of the lower pad.2. The interconnection structure of claim 1 , wherein the interconnection pad is positioned on a central portion of the upper surface of the body pad.3. The interconnection structure of claim 1 , wherein the interconnection pad is arranged on an upper surface and a side surface of the body pad.4. The interconnection structure of claim 1 , wherein the width of the lower pad is about 15 μm to about 20 μm claim 1 , the width of the interconnection via is about ...

Semiconductor device

Provided here are: an electrically-conductive semiconductor substrate with which a semiconductor circuit is formed; an insulating film deposited on a major surface of the electrically-conductive semi-conductor substrate; and a bonding pad having fixing parts fixed onto the insulating film, side wall parts rising up from the fixing parts, and an electrode part connected to the side wall parts and disposed in parallel to the major surface; wherein the electrode part forms, together with the insulating film, a gap region therebetween, and portions of the electrode part where it is connected to the side wall parts are configured to have at least one of: a positional relationship in which they sandwich therebetween a central portion of the electrode part in its bonding region to be bonded to a bonding wire; and a positional relationship in which they surround the central portion.

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure includes a substrate comprising a die pad disposed over the substrate, and a passivation disposed over the substrate and surrounding the die pad, a redistribution layer (RDL) comprising a dielectric layer disposed over the passivation and an interconnect structure disposed within the dielectric layer and electrically connecting with the die pad, a conductive bump disposed over and electrically connected with the interconnect structure; and an isolation layer surrounding the substrate and the RDL. 1. A semiconductor structure , comprising:a substrate comprising a die pad disposed over the substrate and a passivation disposed over the substrate and surrounding the die pad;a redistribution layer (RDL) comprising a dielectric layer disposed on the passivation and an interconnect structure disposed within the dielectric layer and electrically connecting with the die pad;an isolation layer directly contacted with the substrate, the passivation and the dielectric layer; anda plurality of recesses formed over at least a sidewall of the substrate, wherein the isolation layer is directly contacted with the sidewall of the substrate at the plurality of recesses.2. The semiconductor structure of claim 1 , wherein the isolation layer is vertically extended along the substrate claim 1 , the passivation and the dielectric layer.3. The semiconductor structure of claim 1 , wherein the isolation layer surrounds the interconnect structure.4. The semiconductor structure of claim 1 , wherein the isolation layer is extended from the substrate over the passivation to the dielectric layer.5. The semiconductor structure of claim 1 , wherein the isolation layer is interfaced with a sidewall of the semiconductor structure extending in a direction from the substrate over the passivation to the dielectric layer.6. The semiconductor structure of claim 5 , wherein the sidewall of the semiconductor structure comprises the sidewall of the substrate claim 5 , a sidewall of ...

SEMICONDUCTOR DEVICE

A semiconductor device includes a substrate, a plurality of pads disposed over the substrate, and a solder mask disposed over the substrate. The substrate includes a pair of first edges parallel to each other, a pair of second edges orthogonal to the pair of first edges, and a center point. The solder mask includes four recess portions exposing an entire top surface and sidewalls of four of the pads in four corners of the regular array, and a plurality of second recess portions exposing a portion of a top surface of other pads in the regular array. A pad size of the four pads in the four corners of the regular array exposed through the first recess portions and a pad size of the other pads exposed through the second recess portions are the same. 2. The semiconductor device of claim 1 , wherein the plurality of pads comprise four non-solder mask defined (NSMD) pads in the four corners of the regular array and a plurality of solder mask defined (SMD) pads disposed away from the four corners of the regular array.3. The semiconductor of claim 2 , wherein each of the four NSMD pads is adjacent to one of the SMD pads in a same horizontal row and another one of the SMD pads in a same vertical column.4. The semiconductor device of claim 1 , wherein the first vertical distances are similar to the second vertical distances.5. The semiconductor device of claim 1 , wherein the first vertical distances are different from the second vertical distances.6. The semiconductor device of claim 1 , wherein a first distance is defined as a distance between the center point and each of the four first recess portions claim 1 , and the first distance is greater than at least one of the first vertical distance and the second vertical distance.7. The semiconductor device of claim 6 , wherein a second distance is defined as a distance between the center point and each of the second recess portions claim 6 , and the second distance is less than the first vertical distance and the second ...

Stacked Semiconductor Structure and Method

A device comprises a first chip comprising a first connection pad embedded in a first dielectric layer and a first bonding pad embedded in the first dielectric layer, wherein the first bonding pad comprises a first portion and a second portion, the second portion being in contact with the first connection pad and a second chip comprising a second bonding pad embedded in a second dielectric layer of the second chip, wherein the first chip and the second chip are face-to-face bonded together through the first bonding pad the second bonding pad. 1. A device comprising: a first connection pad embedded in a first dielectric layer;', 'a first connector embedded in the first dielectric layer, the first connector directly contacting the first connection pad; and', 'a first bonding pad embedded in the first dielectric layer, the first connector being interposed between first bonding pad and the first connection pad; and, 'a first chip comprising a semiconductor substrate', 'an interconnect structure interposed between the semiconductor substrate and the first chip;', 'an external connection pad directly on the interconnect structure, the interconnect structure being interposed between the external connection pad and the first chip;', 'a second dielectric layer interposed between the interconnect structure the first chip, the second dielectric layer being directly bonded to the first dielectric layer; and', 'a second bonding pad embedded in the second dielectric layer of the second chip, wherein the first chip and the second chip are face-to-face bonded together through the first bonding pad the second bonding pad., 'a second chip bonded to the first chip, the second chip comprising2. The device of claim 1 , wherein a width of the first connector is less than a width of the first bonding pad and a width of the first connection pad.3. The device of claim 2 , wherein a width of the first bonding pad is less than a width of the second bonding pad.4. The device of claim 1 , ...

Fingerprint Sensor Device and Method

A fingerprint sensor package and method are provided. The fingerprint sensor package comprises a fingerprint sensor along with a fingerprint sensor surface material and electrical connections from a first side of the fingerprint sensor to a second side of the fingerprint sensor. A high voltage chip is connected to the fingerprint sensor and then the fingerprint sensor package with the high voltage chip are connected to a substrate, wherein the substrate has an opening to accommodate the presence of the high voltage chip. 1. A device comprising:a substrate;a connector on the substrate; a through via (TV), the fingerprint sensor being electrically connected to the connector through the TV; and', 'a plurality of electrodes electrically connected to the TV; and, 'a fingerprint sensor bonded to the connector, the fingerprint sensor comprisinga fingerprint sensor cover attached to the fingerprint sensor, the plurality of electrodes being interposed between the fingerprint sensor cover and the substrate.2. The device of claim 1 , further comprising a glue layer interposed between the fingerprint sensor cover and the plurality of electrodes.3. The device of claim 1 , wherein the fingerprint sensor cover comprises sapphire or glass.4. The device of claim 1 , wherein the connector comprises a metal ball.5. The device of claim 1 , wherein the connector comprises copper.6. The device of claim 1 , wherein the plurality of electrodes are configured to measure a difference in capacitance between different areas of an overlying finger.7. The device of claim 1 , wherein the fingerprint sensor cover has a thickness between about 50 μm and about 1000 μm.8. A device comprising: a plurality of electrodes on the first side, the plurality of electrodes being electrically coupled to a circuitry within the fingerprint sensor; and', 'a through via (TV) extending from the first side to the second side, the TV being electrically coupled to the plurality of electrodes;, 'a fingerprint sensor ...

Semiconductor structure and manufacturing method thereof

A semiconductor structure includes a substrate; a pad disposed over the substrate; a first passivation disposed over the substrate, partially covering the pad, and including a protrusion protruded from the first passivation and away from the substrate; a conductive layer disposed over the first passivation and a portion of the pad exposed from the first passivation; and a second passivation disposed over the conductive layer, wherein the conductive layer disposed over the protrusion is exposed from the second passivation.

SEMICONDUCTOR DEVICE

A semiconductor device includes a substrate including a surface, a plurality of pads disposing on the surface of the substrate, the plurality of pads includes a non-solder mask defined (NSMD) pad and a solder mask defined (SMD) pad, and the NSMD pad is arranged at a predetermined location. Further, a method of manufacturing a semiconductor device includes providing a substrate, disposing a plurality of pads on a surface of the substrate, disposing a solder mask over the surface of the substrate and the plurality of pads, forming a first recess in the solder mask to surround one of the plurality of pads, and forming a second recess in the solder mask and above one of the plurality of pads. 2. The semiconductor device of claim 1 , wherein the plurality of pads are arranged in a regular array including a plurality of horizontal rows and a plurality of vertical columns.3. The semiconductor device of claim 1 , wherein the plurality of pads comprise a plurality of non-solder mask defined (NSMD) pads and a plurality of solder mask defined (SMD) pads.4. The semiconductor of claim 3 , wherein the first recess portion entirely exposes one of the NSMD pads claim 3 , and the second recess portion partially exposes one of the SMD pads.5. The semiconductor device of claim 1 , wherein first recess portion is disposed on a corner of the semiconductor device and the second recess portion is disposed away from the corner of the semiconductor device.6. The semiconductor device of claim 1 , wherein the first distance between the central point and the first edge is greater than a fourth distance between the central point and the second recess portion claim 1 , and the second distance between the central point and the second edge is greater than the fourth distance between the central point and the second recess portion.7. A semiconductor device claim 1 , comprising:a substrate comprising a pair of first edges parallel to each other, a pair of second edges orthogonal to the first edge, ...

Semiconductor Device and Method of Forming Patterned Repassivation Openings Between RDL and UBM to Reduce Adverse Effects of Electro-Migration

A semiconductor device has a semiconductor wafer with a first conductive layer formed over a surface of the semiconductor wafer. A first insulating layer is formed over the surface of the semiconductor wafer and first conductive layer. A second conductive layer is formed over the first insulating layer and first conductive layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A plurality of openings is formed in the second insulating layer in a bump formation area of the semiconductor wafer to expose the second conductive layer and reduce adverse effects of electro-migration. The openings are separated by portions of the second insulating layer. A UBM layer is formed over the openings in the second insulating layer in the bump formation area electrically connected to the second conductive layer. A bump is formed over the UBM layer.

WAFER-LEVEL PACKAGE INCLUDING UNDER BUMP METAL LAYER

A semiconductor package includes a semiconductor chip comprising a first surface and a second surface, a redistribution layer on the first surface of the semiconductor chip, an under bump metal (UBM) layer on the redistribution layer, and a solder bump on the UBM layer, and the solder bump covers both outer side surfaces of the UBM layer. 1. A wafer-level semiconductor package comprising:a semiconductor chip including a first surface and a second surface, and including a connection pad on the first surface;a first passivation layer covering the first surface of the semiconductor chip, the first passivation layer including a first trench exposing the connection pad;a redistribution layer in the first trench and on the first passivation layer;a second passivation layer on the redistribution layer, and the second passivation layer includes a second trench exposing the redistribution layer;a UBM layer in the second trench and on the second passivation and in contact with the redistribution layer, and the thickness of the UBM layer is approximately 25 to 35 μm; anda solder bump on the UBM layer and covering an outer surface of the UBM layer, and a thickness of the solder bump is approximately 210 to 220 μm.2. The wafer-level semiconductor package of claim 1 , wherein the solder bump includes Au.3. The wafer-level semiconductor package of claim 1 , wherein the solder bump further comprises a contact surface in contact with the second passivation layer.4. The wafer-level semiconductor package of claim 1 , wherein an width of a portion of the solder bump covering the outer surface of the UBM layer gradually increases from the second passivation layer to the bottom surface of the UBM layer.5. The wafer-level semiconductor package of claim 1 , wherein the UBM layer comprises a first UBM layer in contact with the redistribution layer and a second UBM layer disposed on the first UBM layer.6. The wafer-level semiconductor package of claim 1 , wherein the wafer-level ...

Semiconductor device and manufacturing method thereof

A method of manufacturing a semiconductor structure includes receiving a substrate including a die pad disposed thereon; disposing a passivation over the substrate and around the die pad; disposing a polymer over the passivation; forming a post passivation interconnect (PPI) including an elongated portion and a via portion contacting with the die pad; depositing a metallic paste on the elongated portion of the PPI by a stencil; disposing a conductive bump over the metallic paste; and disposing a molding over the PPI and around the metallic paste and the conductive bump.

Semiconductor Device Load Terminal

A semiconductor device is presented. The semiconductor device comprises a semiconductor body coupled to a first load terminal and to a second load terminal and configured to carry a load current between the first load terminal and the second load terminal. The first load terminal comprises a contiguous metal layer coupled to the semiconductor body; and at least one metal island arranged on top of and in contact with the contiguous metal layer and configured to be contacted by an end of a bond wire and to receive at least a part of the load current by means of the bond wire, wherein the contiguous metal layer and the metal island are composed of the same metal. 1. A semiconductor device comprising a semiconductor body coupled to a first load terminal and to a second load terminal and configured to carry a load current between the first load terminal and the second load terminal , wherein the first load terminal comprises:a contiguous metal layer coupled to the semiconductor body; andat least one metal island arranged on top of and in contact with the contiguous metal layer and configured to be contacted by an end of a bond wire and to receive at least a part of the load current by means of the bond wire, wherein the contiguous metal layer and the metal island are composed of the same metal.2. The semiconductor device of claim 1 , wherein the contiguous metal layer and the at least one metal island form a monolithic metal region.3. The semiconductor device of claim 1 , wherein the contiguous metal layer is electrically connected to at least a section of the semiconductor body.4. The semiconductor device of claim 1 , wherein the contiguous metal layer is in contact with the semiconductor body.5. The semiconductor device of claim 1 , wherein the contiguous metal layer exhibits a thickness of at least 10 μm along a vertical direction.6. The semiconductor device of claim 1 , wherein the at least one metal island exhibits a thickness of at least 5 μm along a vertical ...

INTEGRATED CIRCUIT PACKAGE

Embodiments of the present disclosure are directed towards a method of assembling an integrated circuit package. In embodiments the method may include providing a wafer having an unpatterned passivation layer to prevent corrosion of metal conductors embedded in the wafer. The method may further include laminating a dielectric material on the passivation layer to form a dielectric layer and selectively removing dielectric material to form voids in the dielectric layer. These voids may reveal portions of the passivation layer disposed over the metal conductors. The method may then involve removing the portions of the passivation layer to reveal the metal conductors. Other embodiments may be described and/or claimed. 1. A method of assembling an integrated circuit package comprising:providing a wafer having an unpatterned passivation layer to prevent corrosion of metal conductors embedded in the wafer;laminating a dielectric material on the passivation layer to form a dielectric layer;selectively removing dielectric material to form voids in the dielectric layer revealing portions of the passivation layer disposed over the metal conductors; andremoving the portions of the passivation layer to reveal the metal conductors.2. The method of claim 1 , wherein the metal conductor comprises copper and further comprising applying a wet etch process to the metal conductor to remove copper oxide formed thereon.3. The method of claim 2 , wherein the wet etch process involves applying phosphoric acid and hydrogen peroxide.4. The method of claim 1 , wherein laminating a dielectric material further comprises: spin-coating of the dielectric material on the passivation layer; andcuring the dielectric material to harden the dielectric material.5. The method of claim 1 , wherein selectively removing dielectric material comprises either a photolithography process or a laser drilling process.6. The method of claim 1 , wherein removing the portions of the passivation layer further ...

SEMICONDUCTOR CONTACT STRUCTURE HAVING STRESS BUFFER LAYER FORMED BETWEEN UNDER BUMP METAL LAYER AND COPPER PILLAR

Semiconductor apparatus and method for manufacturing semiconductor apparatus are provided. Semiconductor apparatus includes a semiconductor substrate having metal pads, a first passivation layer, a second passivation layer, an under bump metal layer, a stress buffer layer, a copper pillar and a solder structure. First passivation layer is formed on the semiconductor substrate and covers a portion of each metal pad, the first passivation layer has first passivation layer openings to expose a first portion of each metal pad. Second passivation layer is formed on the first passivation layer, the second passivation layer has second passivation layer openings to expose a second portion of each metal pad. Under bump metal layer is formed on the second portion of each metal pad exposed by the second passivation layer opening. Stress buffer layer is formed on the under bump metal layer, and the copper pillar is disposed on the stress buffer layer. 1. A semiconductor apparatus , comprising:a semiconductor substrate having at least one metal pad;a first passivation layer formed on the semiconductor substrate and covering a portion of the at least one metal pad, the first passivation layer having at least one first passivation layer opening to expose a first portion of the at least one metal pad;a second passivation layer formed on the first passivation layer, the second passivation layer having at least one second passivation layer opening to expose a second portion of the at least one metal pad;an under bump metal layer at least formed on the second portion of the at least one metal pad exposed by the second passivation layer opening;a stress buffer layer formed on the under bump metal layer, wherein the material of the stress buffer layer comprises tin, tin-silver, tin alloy, indium or indium alloy; anda copper pillar disposed on the stress buffer layer.2. The semiconductor apparatus according to claim 1 , wherein the material of the under bump metal layer comprises ...

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

A semiconductor structure includes a substrate including a first surface; a dielectric layer disposed over the first surface of the substrate; a first conductive line surrounded by the dielectric layer and extended over the first surface of the substrate; a conductive via disposed over the first conductive line and extended through the dielectric layer; and a cross section of the conductive via parallel to the first surface of the substrate, wherein the first conductive line includes a second surface at least partially interfaced with the conductive via, the second surface of the first conductive line includes a first end, a second end opposite to the first end and a first central axis passing through the first end and the second end, the cross section of the conductive via includes a second central axis parallel to the first central axis and a third central axis orthogonal to the second central axis. 1. A semiconductor structure , comprising:a substrate including a first surface;a dielectric layer disposed over the first surface of the substrate;a first conductive line surrounded by the dielectric layer and extended over the first surface of the substrate;a conductive via disposed over the first conductive line and extended through the dielectric layer;a second conductive line extended over the dielectric layer and coupled with the conductive via; and 'wherein the first conductive line includes a second surface at least partially interfaced with the conductive via, the second surface of the first conductive line includes a first end, a second end opposite to the first end and a first central axis passing through the first end and the second end, the cross section of the conductive via includes a second central axis substantially parallel to the first central axis and a third central axis substantially orthogonal to the second central axis, the cross section of the conductive via includes a longest length along the second central axis and a shortest length along the ...

SEMICONDUCTOR CHIPS HAVING THROUGH SILICON VIAS AND RELATED FABRICATION METHODS AND SEMICONDUCTOR PACKAGES

A semiconductor chip including through silicon vias (TSVs), wherein the TSVs may be prevented from bending and the method of fabricating the semiconductor chip may be simplified, and a method of fabricating the semiconductor chip. The semiconductor chip includes a silicon substrate having a first surface and a second surface; a plurality of TSVs which penetrate the silicon substrate and protrude above the second surface of the silicon substrate; a polymer pattern layer which is formed on the second surface of the silicon substrate, surrounds side surfaces of the protruding portion of each of the TSVs, and comprises a flat first portion and a second portion protruding above the first portion; and a plated pad which is formed on the polymer pattern layer and covers a portion of each of the TSVs exposed from the polymer pattern layer. 1. A method of fabricating a semiconductor chip , the method comprising:forming a plurality of through silicon vias (TSV) in a substrate that has a first surface and an opposed second surface;recessing the second surface of the substrate so that each TSV includes a protruding portion that protrudes above the second surface of the substrate;forming a polymer buffer layer that covers the protruding portions of the TSVs;performing an exposure process using a phase shift mask (PSM) on the polymer buffer layer to form a polymer pattern layer that includes a completely-exposed region and a half-exposed region; andforming a plated pad on the TSVs via an electroplating process.2. The method of claim 1 , further comprising curing the polymer pattern layer after the polymer pattern layer is formed.3. The method of claim 1 , wherein an insulation layer is formed on the top surface and the side surfaces of the TSVs claim 1 , anda portion of the insulation layer on the protruding portion of each of the TSVs is removed before the electroplating process is performed.4. The method of claim 1 , wherein the TSVs protrude above the half-exposed region of ...

Package With UBM and Methods of Forming

Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes an integrated circuit die, an encapsulant at least laterally encapsulating the integrated circuit die, a redistribution structure on the integrated circuit die and the encapsulant, a connector support metallization coupled to the redistribution structure, a dummy pattern, a second dielectric layer, and an external connector on the connector support metallization. The redistribution structure comprises a first dielectric layer having a first surface disposed distally from the encapsulant and the integrated circuit die. The dummy pattern is on the first surface of the first dielectric layer and around the connector support metallization. The second dielectric layer is on the first surface of the first dielectric layer and on at least a portion of the dummy pattern. The second dielectric layer does not contact the connector support metallization. 1. A method comprising:encapsulating an integrated circuit die with an encapsulant;forming a redistribution structure on the integrated circuit die and the encapsulant, the redistribution structure comprising a first dielectric layer having a first surface distal from the integrated circuit die and the encapsulant;forming an under ball metallization (UBM) and a dummy pattern on the redistribution structure, the dummy pattern surrounding the UBM on the first surface of the first dielectric layer, the dummy pattern being electrically isolated; andforming a second dielectric layer on the first surface of the first dielectric layer and at least a portion of the dummy pattern, wherein after the forming the second dielectric layer, the second dielectric layer is physically spaced apart from the UBM, wherein the second dielectric layer covers an exterior portion of the dummy pattern laterally distal from the UBM and exposes an interior portion of the dummy pattern proximate the UBM.2. The ...

Semiconductor Device and Method of Forming Interposer Frame Over Semiconductor Die to Provide Vertical Interconnect

A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.

Conductive Line System and Process

A system and method for providing a conductive line is provided. In an embodiment the conductive line is formed by forming two passivation layers, wherein each passivation layer is independently patterned. Once formed, a seed layer is deposited into the two passivation layers, and a conductive material is deposited to fill and overfill the patterns within the two passivation layers. A planarization process such as a chemical mechanical polish may then be utilized in order to remove excess conductive material and form the conductive lines within the two passivation layers. 1. A method of manufacturing a semiconductor device , the method comprising:applying a positive tone photosensitive material over a negative tone photosensitive material over a substrate;forming a first conductive material to extend through the positive tone photosensitive material and the negative tone photosensitive material to make electrical connection with a contact pad; andforming a second conductive material to extend through the positive tone photosensitive material, wherein after the forming the second conductive material a first surface of the second conductive material faces a second surface of the negative tone photosensitive material, the second surface of the negative tone photosensitive material facing away from the substrate.8. A method of manufacturing a semiconductor device , the method comprising:coating a dielectric layer with a negative tone photosensitive material, the dielectric layer exposing a first portion of a first contact pad;patterning and developing the negative tone photosensitive material;coating the negative tone photosensitive material with a positive tone photosensitive material;patterning and developing the positive tone photosensitive material to expose a first portion of the negative tone photosensitive material and also to expose the first portion of the first contact pad, wherein the first portion of the negative tone photosensitive material is separated ...

FULLY MOLDED MINIATURIZED SEMICONDUCTOR MODULE

A semiconductor module can comprise a fully molded base portion comprising a planar surface that further comprises a semiconductor die comprising contact pads, conductive pillars coupled to the contact pads and extending to the planar surface, and an encapsulant material disposed over the active surface, four side surfaces, and around the conductive pillars, wherein ends of the conductive pillars are exposed from the encapsulant material at the planar surface of the fully molded base portion. A build-up interconnect structure comprising a routing layer can be disposed over the fully molded base portion. A photo-imageable solder mask material can be disposed over the routing layer and comprise openings to form surface mount device (SMD) land pads electrically coupled to the semiconductor die and the conductive pillars. A SMD component can be electrically coupled to the SMD land pads with surface mount technology (SMT). 1. A semiconductor module , comprising: a semiconductor die comprising contact pads,', 'conductive pillars coupled to the contact pads and extending to the planar surface, and', 'an encapsulant material disposed over the active surface, four side surfaces, and around the conductive pillars, wherein ends of the conductive pillars are exposed from the encapsulant material at the planar surface of the fully molded base portion;, 'a fully molded base portion comprising a planar surface that further comprisesa build-up interconnect structure comprising a routing layer disposed over the fully molded base portion;a photo-imageable solder mask material disposed over the routing layer and comprising openings to form surface mount device (SMD) land pads electrically coupled to the semiconductor die and the conductive pillars; anda SMD component electrically coupled to the SMD land pads with surface mount technology (SMT).2. The semiconductor module of claim 1 , wherein the photo-imageable solder mask comprises at least one of epoxy solder resist claim 1 , ...

SEMICONDUCTOR COPPER METALLIZATION STRUCTURE AND RELATED METHODS

Implementations of semiconductor packages may include: a silicon die including a pad, the pad including aluminum and copper; a passivation layer over at least a portion of the silicon die and a layer of one of a polyimide (PI) a polybenzoxazole (PBO), or a polymer resin coupled to the passivation layer. The package may include a first copper layer coupled over the pad, the first copper layer being about 1 microns to about 20 microns thick; a second copper layer coupled over the first copper layer, the second copper layer may be about 5 microns to about 40 microns thick; where a width of the first copper layer above the pad may be wider than a width of the second copper layer above the pad. The first and second copper layers may be configured to bond with a heavy copper wire or solder with a copper clip. 1. A semiconductor package comprising:a die comprising a pad on a first side of the die, the pad comprising one of aluminum and copper (AlCu); aluminum, copper and silicon (AlCuSi); aluminum, copper, and tungsten (AlCuW); aluminum silicon (AlSi); or any combination thereof;a first copper layer coupled directly over and to the pad;a second copper layer coupled over the first copper layer; anda metal layer comprised on a second side of the die opposite the first side of the die, wherein an implanted doped layer is formed in the second side of the die.2. A semiconductor package of claim 1 , wherein a width of the first copper layer above the pad is wider than a width of the second copper layer above the pad.3. The semiconductor package of claim 1 , further comprising a metal coating forming one of a metal cap on a top of the second copper layer or a full metal coverage of the first and the second copper layers claim 1 , the metal coating applied through one of electroless plating or electrolytic plating.4. The semiconductor package of claim 3 , wherein the metal coating comprises one of nickel and gold (Ni/Au); nickel claim 3 , palladium claim 3 , and gold (Ni/Pd/Au); ...

REDISTRIBUTION METAL AND UNDER BUMP METAL INTERCONNECT STRUCTURES AND METHOD

An integrated circuit die includes a metal layer, a first passivation layer disposed above the metal layer, an aluminum containing redistribution layer disposed above the first passivation layer, an under bump metallization layer, and a redistribution layer plug. The redistribution layer plug is coupled to the metal layer and disposed in a via in the first passivation layer. The under bump metallization layer is coupled to the aluminum containing redistribution layer above the first passivation layer at a distance from the redistribution layer plug. 1. An integrated circuit die , comprising:a metal layer;a redistribution layer;a dielectric layer disposed between the metal layer and the redistribution layer, the dielectric layer directly contacting a first portion of a first surface of the redistribution layer;a redistribution layer plug disposed in a via through the dielectric layer, wherein a first surface of the redistribution layer plug is substantially in-plane with the first surface of the redistribution layer, and a second surface of the redistribution layer plug is substantially in-plane with a surface of the metal layer; andan under bump metallization layer coupled to a portion of a second surface of the redistribution layer, the portion of the second surface of the redistribution layer facing a second portion of the first surface of the redistribution layer.2. The integrated circuit die of claim 1 , wherein material of the redistribution layer is not within the via.3. The integrated circuit die of claim 1 , wherein the redistribution layer plug comprises tungsten claim 1 , titanium claim 1 , titanium nitride claim 1 , titanium-tungsten claim 1 , or nickel silicide.4. The integrated circuit die of claim 1 , wherein the redistribution layer plug comprises copper.5. The integrated circuit die of claim 4 , wherein the first surface of the redistribution layer plug comprises tungsten claim 4 , titanium claim 4 , or tantalum.6. The integrated circuit die of claim ...

HIGH ELECTRON MOBILITY TRANSISTOR (HEMT)

HEMT having a drain field plate is provided. The drain field plate is formed in the area between the gate and drain of a HEMT. The drain field plate includes a metal pad that has a larger projection area than the drain pad. The drain field plate and semiconductor layer disposed beneath the drain field plate form a metal-semiconductor (M-S) Schottky structure. The capacitance of the M-S Schottky structure generates capacitance in the semiconductor area, which increases the breakdown voltage of the transistor components of the HEMT. A portion of the substrate under the active area may be removed to thereby increase the heat conductivity and reduce the junction temperature of the transistor components of the HEMT. 1. A method for processing a semiconductor transistor , the semiconductor transistor including a substrate , an epitaxial layer , and a plurality of transistor components that are formed on the epitaxial layer , the method comprising:removing a portion of the substrate that is disposed below a portion of the plurality of transistor components, to thereby expose a portion of a bottom surface of the epitaxial layer;forming an insulating layer on the expose portion of the bottom surface of the epitaxial layer, the insulating layer being made of an electrically insulating material;forming at least one via that extends from a bottom surface of the insulating layer to a bottom surface of at least one of the plurality of the transistor components; anddepositing at least one metal layer on the bottom surface of the insulating layer, on a side wall of the via and on the bottom surface of the at least one of the plurality of transistor components.2. The method of claim 1 , further comprising:applying a solder paste on a bottom surface of the at least one metal layer.3. The method of claim 1 , wherein the step of depositing at least one metal layer includes:depositing a first metal layer on the bottom surface of the insulating layer, on the side wall of the via and on ...

Die-to-Die Gap Control for Semiconductor Structure and Method

An embodiment is a structure comprising a substrate, a first die, and a second die. The substrate has a first surface and a second surface opposite the first surface. The substrate has a through substrate via extending from the first surface towards the second surface. The first die is attached to the substrate, and the first die is coupled to the first surface of the substrate. The second die is attached to the substrate, and the second die is coupled to the first surface of the substrate. A first distance is between a first edge of the first die and a first edge of the second die, and the first distance is in a direction parallel to the first surface of the substrate. The first distance is equal to or less than 200 micrometers.

Chip stack with electrically insulating walls

A chip stack is provided and includes two or more chips, a solder joint operably disposed between adjacent ones of the two or more chips, the solder joint occupying about 25-30% or more of an area of the chip stack and insulating walls disposed on at least one of the two or more chips to separate the solder joint from an adjacent solder joint.

Fingerprint Sensor Device and Method

A fingerprint sensor package and method are provided. The fingerprint sensor package comprises a fingerprint sensor along with a fingerprint sensor surface material and electrical connections from a first side of the fingerprint sensor to a second side of the fingerprint sensor. A high voltage chip is connected to the fingerprint sensor and then the fingerprint sensor package with the high voltage chip are connected to a substrate, wherein the substrate has an opening to accommodate the presence of the high voltage chip. 1. A method comprising:attaching a fingerprint sensor to a first side of a first redistribution layer;attaching a high voltage chip to a second side of the first redistribution layer, wherein the second side of the first redistribution layer is opposite to the first side of the first redistribution layer; andattaching a substrate to the second side of the first redistribution layer, wherein the high voltage chip extends into an opening of the substrate.2. The method of claim 1 , further comprising forming a conductive column on the first side of the first redistribution layer adjacent the fingerprint sensor.3. The method of claim 2 , further comprising encapsulating the fingerprint sensor and the conductive column in an encapsulant.4. The method of claim 1 , forming a second redistribution layer in electrical contact with the fingerprint sensor claim 1 , wherein the fingerprint sensor is interposed between the first redistribution layer and the second redistribution layer.5. The method of claim 4 , further comprising forming a sensor surface material layer on the second redistribution layer claim 4 , wherein the second redistribution layer is interposed between the sensor surface material layer and the fingerprint sensor.6. The method of claim 1 , wherein a center of the high voltage chip is spaced apart from a center of the fingerprint sensor in a plan view.7. The method of claim 1 , wherein a width of the high voltage chip is less than a width of ...

Mechanisms for Forming Hybrid Bonding Structures with Elongated Bumps

Embodiments of mechanisms for forming a package structure are provided. The package structure includes a semiconductor die and a substrate. The package structure includes a pillar bump and an elongated solder bump bonded to the semiconductor die and the substrate. A height of the elongated solder bump is substantially equal to a height of the pillar bump. The elongated solder bump has a first width, at a first horizontal plane passing through an upper end of a sidewall surface of the elongated solder bump, and a second width, at a second horizontal plane passing through a midpoint of the sidewall surface. A ratio of the second width to the first width is in a range from about 0.5 to about 1.1. 1. A package structure , comprising:a first substrate;a second substrate;a pillar bump bonded to the first substrate and the second substrate, the pillar bump being electrically coupled to the first substrate and the second substrate, wherein the pillar bump comprises a pillar and a bonding layer, the pillar is a non-solder material having a higher reflow temperature than the bonding layer, the bonding layer is between the pillar and the second substrate, and the pillar includes a linear sidewall profile; andan elongated solder bump bonded to the first substrate and the second substrate, wherein a height of the elongated solder bump is substantially equal to a height of the pillar bump, wherein the elongated solder bump and the bonding layer are formed of a solder.2. The package structure of claim 1 , wherein the first substrate comprises a semiconductor die.3. The package structure of claim 2 , wherein the bonding layer is interposed between the pillar and the second substrate.4. The package structure of claim 1 , wherein the elongated solder bump has convex sidewalls.5. The package structure of claim 1 , wherein the elongated solder bump has a solder portion having a first width at a first horizontal plane passing through an upper end of a sidewall surface of the elongated ...

Stacked Semiconductor Structure and Method

A device comprises a first chip comprising a first connection pad embedded in a first dielectric layer and a first bonding pad embedded in the first dielectric layer, wherein the first bonding pad comprises a first portion and a second portion, the second portion being in contact with the first connection pad and a second chip comprising a second bonding pad embedded in a second dielectric layer of the second chip, wherein the first chip and the second chip are face-to-face bonded together through the first bonding pad the second bonding pad. 1. A device comprising: a first connection pad embedded in a first dielectric layer; and', 'a first bonding pad embedded in the first dielectric layer, wherein the first bonding pad comprises a first portion and a second portion, the second portion being in contact with the first connection pad; and, 'a first chip comprisinga second chip comprising a second bonding pad embedded in a second dielectric layer of the second chip, wherein the first chip and the second chip are face-to-face bonded together through the first bonding pad the second bonding pad.2. The device of claim 1 , wherein:a width of the first connection pad is greater than a width of the second portion of the first bonding pad; anda width of the first portion of the first bonding pad is greater than the width of the second portion of the first bonding pad.3. The device of claim 1 , wherein:a width of the second bonding pad is greater than a width of the first portion of the first bonding pad.4. The device of claim 1 , further comprising:a homogeneous layer between the first bonding pad and the second bonding pad, wherein the homogeneous layer is formed through an inter-diffusion process between the first bonding pad and the second bonding pad.5. The device of claim 1 , wherein:the second portion of the first bonding pad is a connector between the first portion of the first bonding pad and the first connection pad.6. The device of claim 5 , wherein:the connector ...

CHIP PACKAGE AND MANUFACTURING METHOD THEREOF

A chip package includes a chip, a laser stopper, an isolation layer, a redistribution layer, an insulating layer, and a conductive structure. The chip has a conductive pad, a first surface, and a second surface. The conductive pad is located on the first surface. The second surface has a first though hole to expose the conductive pad. The laser stopper is located on the conductive pad in the first though hole. The isolation layer is located on the second surface and in the first though hole. The isolation layer has a third surface opposite to the second surface, and has a second though hole to expose the laser stopper. The redistribution layer is located on the third surface, a sidewall of the second though hole, and the laser stopper in the second though hole. The conductive structure is located on the redistribution. 1. A chip package , comprising:a chip having a conductive pad, a first surface, and a second surface opposite to the first surface, wherein the conductive pad is located on the first surface, and the second surface has a first through hole to expose the conductive pad;a laser stopper located on the conductive pad that is in the first though hole;an isolation layer located on the second surface and in the first though hole, and having a third surface opposite to the second surface, and having a second though hole to expose the laser stopper;a redistribution layer located on the third surface, a sidewall of the second though hole, and the laser stopper that is in the second though hole;an insulating layer located on the third surface and the redistribution layer, and having an opening to expose the redistribution layer; anda conductive structure located on the redistribution layer that is in the opening of the insulating layer, such that the conductive structure is electrically connected to the conductive pad.2. The chip package of claim 1 , wherein a diameter of the second though hole is smaller than that of the first though hole.3. The chip package of ...

Semiconductor packages with an intermetallic layer

A method of forming a semiconductor package. Implementations include forming on a die backside an intermediate metal layer having multiple sublayers, each including a metal selected from the group consisting of titanium, nickel, copper, silver, and combinations thereof. A tin layer is deposited onto the intermediate metal layer and is then reflowed with a silver layer of a substrate to form an intermetallic layer having a melting temperature above 260 degrees Celsius and including an intermetallic consisting of silver and tin and/or an intermetallic consisting of copper and tin. Another method of forming a semiconductor package includes forming a bump on each of a plurality of exposed pads of a top side of a die, each exposed pad surrounded by a passivation layer, each bump including an intermediate metal layer as described above and a tin layer coupled to the intermediate metal layer is reflowed to form an intermetallic layer.

Semiconductor Device Structure and Manufacturing Method

A semiconductor device structure and a manufacturing method are provided. The semiconductor device structure includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The semiconductor device structure also includes a conductive trace over the dielectric layer. The semiconductor device structure further includes a conductive feature over the conductive trace, and a width of the conductive feature is substantially equal to or larger than a maximum width of the conductive trace. In addition, the semiconductor device structure includes a conductive bump over the conductive feature. 1. A structure , comprising:a first substrate;a dielectric layer disposed over the first substrate;a first conductive trace disposed over the dielectric layer;an under-bump metallization (UBM) element disposed over the first conductive trace; anda conductive bump disposed over the UBM element.2. The structure of claim 1 , further comprising a conductive line embedded in the dielectric layer claim 1 , wherein the first conductive trace is electrically coupled to the conductive line.3. The structure of claim 1 , wherein a sidewall of the first conductive trace is aligned with a sidewall of the UBM element.4. The structure of claim 1 , wherein a width of the first conductive trace is substantially equal to a width of the UBM element.5. The structure of claim 1 , wherein the conductive bump is disposed on a sidewall of the UBM element but not on a sidewall of the first conductive trace.6. The structure of claim 1 , wherein a portion of the UBM element is disposed on a sidewall of the first conductive trace.7. The structure of claim 1 , further comprising:a second substrate; anda second conductive trace disposed over the second substrate;wherein the second conductive trace is bonded to the conductive bump.8. The structure of claim 7 , further comprising: a protection material that surrounds the first conductive trace claim 7 , the UBM element claim 7 , the ...

IC DIE, ULTRASOUND PROBE, ULTRASONIC DIAGNOSTIC SYSTEM AND METHOD

An integrated circuit (IC) die () is disclosed having a major surface delimited by at least one edge () of the IC die, said major surface carrying a plurality of electrically conductive contact plates () extending from said major surface beyond the at least one edge such that each contact plate includes an exposed contact surface portion () delimited by the at least one edge for mating with an electrically conductive further contact surface portion () on at least one further edge () of a body (), said at least one further edge delimiting a cavity for receiving the IC die. An ultrasound probe including such an IC die and a method of providing such an IC die with contacts are also disclosed. 1. An ultrasound probe comprising a tip including:an integrated circuit die having a major surface delimited by at least one edge of the IC die, said major surface comprising an ultrasound sensing area and carrying a plurality of electrically conductive contact plates for suspending the IC die in a cavity; anda body having at least one further edge delimiting the cavity comprising the IC die, said at least one further edge comprising a plurality of electrically conductive first further contact surface portion, wherein the contact plates extending from said die major surface beyond the at least one edge such that each contact plate includes an exposed contact surface portion delimited by the at least one edge for mating with the electrically conductive further contact surface portion on the further edge of the body, said at least one further edge delimiting the cavity for receiving the IC die; and wherein each electrically conductive first further contact surface is conductively coupled to the contact surface portion of one of said contact plates.2. (canceled)3. The IC die of claim 1 , wherein the ultrasound sensing area is defined by a plurality of capacitive micromachined ultrasonic transducer elements.4. The IC die of claim 1 , wherein said major surface comprises a plurality of ...

SEMICONDUCTOR DEVICE ASSEMBLY WITH DIE SUPPORT STRUCTURES

A semiconductor device assembly is provided. The assembly includes a first semiconductor die and a second semiconductor die disposed over the first semiconductor die. The assembly further includes a plurality of die support structures between the first and second semiconductor dies and a plurality of interconnects between the first and second semiconductor dies. Each of the plurality of die support structures includes a stand-off pillar and a stand-off pad having a first bond material with a first solder joint thickness between them. Each of the plurality of interconnects includes a conductive pillar and a conductive pad having a second bond material with a second solder joint thickness between them. The first solder joint thickness is less than the second solder joint thickness. 1. A semiconductor package comprising a plurality of dies arranged in a stack ,wherein adjacent ones of the plurality of dies are separated by a plurality of interconnects and a plurality of die support structures,wherein each of the plurality of die support structures includes a stand-off pillar and a stand-off pad with a first distance between the stand-off pillar and the stand-off pad,wherein each of the plurality of interconnects includes a conductive pillar, a conductive pad, and a bond material with a solder joint thickness between the conductive pillar and the conductive pad, andwherein the first distance is less than the solder joint thickness.2. The semiconductor package of claim 1 , wherein the plurality of die support structures includes die support structures disposed about a periphery of the semiconductor package.3. The semiconductor package of claim 1 , wherein the plurality of die support structures includes die support structures disposed in a medial region of the semiconductor device assembly.4. The semiconductor package of claim 1 , wherein the plurality of dies includes more than two dies.5. The semiconductor package of claim 1 , wherein the plurality of dies includes at ...

Semiconductor dies having ultra-thin wafer backmetal systems, microelectronic devices containing the same, and associated fabrication methods

Semiconductor dies including ultra-thin wafer backmetal systems, microelectronic devices containing such semiconductor dies, and associated fabrication methods are disclosed. In one embodiment, a method for processing a device wafer includes obtaining a device wafer having a wafer frontside and a wafer backside opposite the wafer frontside. A wafer-level gold-based ohmic bond layer, which has a first average grain size and which is predominately composed of gold, by weight, is sputter deposited onto the wafer backside. An electroplating process is utilized to deposit a wafer-level silicon ingress-resistant plated layer over the wafer-level Au-based ohmic bond layer, while imparting the plated layer with a second average grain size exceeding the first average grain size. The device wafer is singulated to separate the device wafer into a plurality of semiconductor die each having a die frontside, an Au-based ohmic bond layer, and a silicon ingress-resistant plated layer.

COPPER ELECTROPLATING COMPOSITIONS AND METHODS OF ELECTROPLATING COPPER ON SUBSTRATES

Copper electroplating compositions which include an imidazole compound enables the electroplating of copper having uniform morphology on substrates. The composition and methods of enable copper electroplating of photoresist defined features. Such features include pillars, bond pads and line space features. 2. The composition of claim 1 , wherein the one or more imidazole compounds are in amounts of 0.25 ppm to 1000 ppm.3. The composition of claim 1 , wherein R claim 1 , R claim 1 , R claim 1 , R claim 1 , Rand Rare independently chosen from hydrogen; and (C-C)alkyl.4. The composition of claim 3 , wherein R claim 3 , R claim 3 , Rand Rare independently chosen from hydrogen; and methyl; and Rand Rare hydrogen.6. The method of claim 1 , wherein the substrate comprises photoresist defined features and the photoresist defined features are electroplated with copper during electroplating.7. The method of claim 6 , wherein the photoresist defined features on the substrate are chosen from one or more of pillars claim 6 , bond pads and line space features.8. The method of claim 5 , wherein the one or more imidazole compounds are in amounts of 0.25 ppm to 1000 ppm.9. The method of claim 5 , wherein electroplating is done at a current density of 0.25 ASD to 40 ASD. The present invention is directed to copper electroplating compositions and methods of electroplating copper on substrates, wherein the copper electroplating compositions include an imidazole compound to provide copper deposits having uniform morphology. More specifically, the present invention is directed to copper electroplating compositions and methods of electroplating copper on substrates, wherein the copper electroplating compositions include an imidazole compound to provide copper deposits having uniform morphology and wherein the copper electroplating compositions and copper electroplating methods can be used to electroplate photoresist defined features.Photoresist defined features include copper pillars and ...

COPPER ELECTROPLATING COMPOSITIONS AND METHODS OF ELECTROPLATING COPPER ON SUBSTRATES

Copper electroplating compositions which include a diimidazole compound enables the electroplating of copper having uniform morphology on substrates. The composition and methods of enable copper electroplating of photoresist defined features. Such features include pillars, bond pads and line space features. 2. The composition of claim 1 , wherein the one or more imidazole compounds are in amounts of 0.25 ppm to 1000 ppm.3. The composition of claim 1 , wherein R claim 1 , R claim 1 , Rand Rare independently chosen from hydrogen; and (C-C)alkyl.4. The composition of claim 3 , wherein R claim 3 , R claim 3 , Rand Rare independently chosen from hydrogen; and methyl.6. The method of claim 1 , wherein the substrate comprises photoresist defined features and the photoresist defined features are electroplated with copper during electroplating.7. The method of claim 6 , wherein the photoresist defined features on the substrate are chosen from one or more of pillars claim 6 , bond pads and line space features.8. The method of claim 5 , wherein the one or more imidazole compounds are in amounts of 0.25 ppm to 1000 ppm.9. The method of claim 5 , wherein electroplating is done at a current density of 0.25 ASD to 40 ASD. The present invention is directed to copper electroplating compositions and methods of electroplating copper on substrates, wherein the copper electroplating compositions include a diimidazole compound to provide copper deposits having uniform morphology. More specifically, the present invention is directed to copper electroplating compositions and methods of electroplating copper on substrates, wherein the copper electroplating compositions include an diimidazole compound to provide copper deposits having uniform morphology and wherein the copper electroplating compositions and copper electroplating methods can be used to electroplate photoresist defined features.Photoresist defined features include copper pillars and redistribution layer wiring such as bond ...

Chip Packages and Methods of Manufacture Thereof

A chip package may include a die and a redistribution structure over the die. The redistribution structure may include a die, a redistribution structure over the die, and an under-bump metallurgy (UBM) structure over the redistribution structure. The UBM structure may include a central portion, a peripheral portion physically separated from and surrounding a perimeter of the central portion, and a bridging portion having a first end and a second end opposite the first end. The first end of the bridging portion may be coupled to the central portion of the UBM structure, while the second end of the bridging portion may be coupled to the peripheral portion of the UBM structure. 1. A chip package , comprising:a die;a redistribution structure over the die; andan under-bump metallurgy (UBM) structure over the redistribution structure, the UBM structure comprising a central portion, a peripheral portion physically separated from and surrounding a perimeter of the central portion, and a bridging portion having a first end and a second end opposite the first end, the first end of the bridging portion coupled to the central portion of the UBM structure, the second end of the bridging portion coupled to the peripheral portion of the UBM structure, the second end having a greater width than the first end.2. The chip package of claim 1 , further comprising a polymer layer encapsulating the peripheral portion of the UBM structure claim 1 , wherein a sidewall of the polymer layer is separated from a sidewall of the central portion of the UBM structure.3. The chip package of claim 2 , where the sidewall of the polymer layer and the sidewall of the central portion of the UBM structure are separated by a distance in a range from about 2 micrometers to about 50 micrometers.4. The chip package of claim 2 , wherein an air gap is disposed between the sidewall of the polymer layer and the sidewall of the central portion of the UBM structure.5. The chip package of claim 1 , further ...

CONTACT STRUCTURES FOR DIRECT BONDING

A bonded structure is disclosed. The bonded structure can include a first element that includes a first conductive feature and a first nonconductive region. The first conductive feature can include a fine grain metal that has an average grain size of 500 nm or less. The bonded structure can include a second element that includes a second conductive feature and a second nonconductive region. The first conductive feature is directly bonded to the second conductive feature without an intervening adhesive, and the second nonconductive region is directly bonded to the second nonconductive region without an intervening adhesive. 1. A bonded structure comprising:a first element having a first conductive feature and a first nonconductive region, the first conductive feature comprising a fine grain metal having an average grain size of 500 nm or less; anda second element having a second conductive feature and a second nonconductive region,wherein the first conductive feature is directly bonded to the second conductive feature without an intervening adhesive, and the first nonconductive region is directly bonded to the second nonconductive region without an intervening adhesive.2. The bonded structure of claim 1 , wherein the first conductive feature comprises copper.3. The bonded structure of claim 1 , wherein the grains of the first conductive feature have a maximum grain size less than 500 nm.4. The bonded structure of claim 3 , wherein the grains of the first conductive feature have the maximum grain size less than 350 nm.5. The bonded structure of claim 4 , wherein the grains of the first conductive feature have the maximum grain size less than 50 nm.6. The bonded structure of claim 1 , wherein an average grain size of grains of the second conductive feature is 500 nm or less.7. The bonded structure of claim 1 , wherein the second conductive feature comprises a coarse grain metal.8. The bonded structure of claim 7 , wherein an average grain size of grains of the second ...