Package-Struktur und Verfahren

In einer Ausführungsform umfasst eine Vorrichtung: ein Substrat mit einer ersten Seite und einer zweiten Seite gegenüber der ersten Seite; eine Verbindungsstruktur benachbart zu der ersten Seite des Substrats; und eine IC-Vorrichtung, welche an der Verbindungsstruktur befestigt ist; eine Durchkontaktierung, welche sich von der ersten Seite des Substrats bis zu der zweiten Seite des Substrats erstreckt, wobei die Durchkontaktierung mit der IC-Vorrichtung elektrisch verbunden ist; eine Under-Bump-Metallurgie (UBM) benachbart zu der zweiten Seite des Substrats und die Durchkontaktierung kontaktierend; einen leitfähigen Höcker auf der UBM, wobei es sich bei dem leitfähigen Höcker und der UBM um ein durchgängiges leitfähiges Material handelt, wobei der leitfähige Höcker von der Durchkontaktierung seitlich versetzt ist; und eine Unterfüllung, welche die UBM und den leitfähigen Höcker umgibt.

Chipgehäuse und Verfahren zum Herstellen eines Chipgehäuses

Ein Verfahren zum Herstellen eines Chipgehäuses wird bereitgestellt. Das Verfahren aufweisend: Halten eines Trägers (402), aufweisend eine Mehrzahl von Dies (4041, 4042, 4043, ..., 404n-1, 404n); Bilden einer Separation zwischen der Mehrzahl von Dies (4041, 4042, 4043, ..., 404n-1, 404n) mittels Entfernens eines oder mehr Bereiche (422) des Trägers (402) von dem Träger (402) zwischen der Mehrzahl von Dies (4041, 4042, 4043, ..., 404n-1, 404n); Bilden eines Verkapselungsmaterials (434) in dem einen oder den mehreren entfernten Bereichen (428) zwischen der Mehrzahl von Dies (4041, 4042, 4043, ..., 404n-1, 404n Vereinzeln der Dies (4041, 4042, 4043, ..., 404n-1, 404n) durch das Verkapselungsmaterial (434).

Laminatpackung von Chip auf Träger und in Kavität

Eine Packung (100), umfassend einen Chipträger (102), hergestellt aus einem ersten Material, einen Körper (104), hergestellt aus einem zweiten Material, das sich vom ersten Material unterscheidet, und angeordnet auf dem Chipträger (102) zum Bilden einer Kavität (106), einen Halbleiterchip (108), mindestens teilweise in der Kavität (106) angeordnet, und ein Laminat (110), einkapselnd mindestens eines von mindestens einem Teil des Chipträgers (102), mindestens einem Teils des Körpers (104) und mindestens einem Teil des Halbleiterchips (108).

Halbleitervorrichtung mit einer Bonding-Fläche und einer Abschirmungsstruktur und Verfahren zur Herstellung derselben

Eine Halbleitervorrichtung mit: einem Vorrichtungssubstrat (310) mit einer Vorderseite (312) und einer Rückseite (314), die einer ersten Seite bzw. einer zweiten Seite der Halbleitervorrichtung entsprechen; einer auf der Vorderseite (312) des Vorrichtungssubstrats (310) ausgebildeten Metallstruktur (342); einem auf der zweiten Seite der Halbleitervorrichtung angeordneten Bonding-Pad (374), das in einer elektrischen Verbindung mit der Metallstruktur (342) steht; und einer auf der Rückseite (314) des Vorrichtungssubstrats (310) angeordneten Metallabschirmungsstruktur (376), wobei die Metallabschirmungsstruktur (376) und das Bonding-Pad (374) unterschiedliche Dicken aufweisen.

Leistungshalbleiterchip und Verfahren zur Herstellung eines Leistungshalbleiterchips und Leistungshalbleitereinrichtung

Leistungshalbleiterchip mit einem Halbleiterbauelementkörper (2) und mit einer auf dem Halbleiterbauelementkörper (2) angeordneten mehrschichtigen Metallisierung (10), die eine über dem Halbleiterbauelementkörper (2) angeordnete Nickelschicht (6) aufweist, wobei die Metallisierung (10) eine auf dem Halbleiterbauelementkörper (2) angeordnete, Aluminium aufweisende erste Metallschicht (3) aufweist, wobei die Nickelschicht (6) über der ersten Metallschicht (3) angeordnet ist, wobei die Metallisierung (10) eine zweite Metallschicht (4), die als Chromschicht ausgebildet ist und eine auf der zweiten Metallschicht (4) angeordnete Zwischenschicht (13), die aus Nickel besteht und eine auf der Zwischenschicht (13) angeordnete dritte Metallschicht (5), die als Silberschicht ausgebildet ist, aufweist, wobei die zweite Metallschicht (4) auf der ersten Metallschicht (3) angeordnet ist, wobei die Nickelschicht (6) auf der dritten Metallschicht (5) angeordnet ist, wobei die Nickelschicht (6) eine Dicke ...

Halbleiterbauelement und Verfahren zu dessen Herstellung

Ein Verfahren zur effektiven Herstellung eines Halbleiterbauelements umfasst separates Herstellen eines ersten Substrats mit einer Transistorschicht und eines zweiten Substrats mit einer Metalldrahtschicht und Stapeln des ersten und zweiten Substrats. Ein Transistor auf dem ersten Substrat wird durch eine Anschlusselektrode elektrisch mit einem Metalldraht auf dem zweiten Substrat verbunden.

Superconducting bump bonds

A device (100) includes a first chip (104) having a first circuit element (112), a first interconnect pad (116) in electrical contact (118) with the first circuit element, and a barrier layer (120) on the first interconnect pad, a superconducting bump bond (106) on the barrier layer, and a second chip (102) joined to the first chip by the superconducting bump bond, the second chip having a quantum circuit element (108), in which the superconducting bump bond provides an electrical connection between the first circuit element and the quantum circuit element.

SUPERCONDUCTING BUMP BONDS

A device (100) includes a first chip (104) having a first circuit element (112), a first interconnect pad (116) in electrical contact (118) with the first circuit element, and a barrier layer (120) on the first interconnect pad, a superconducting bump bond (106) on the barrier layer, and a second chip (102) joined to the first chip by the superconducting bump bond, the second chip having a quantum circuit element (108), in which the superconducting bump bond provides an electrical connection between the first circuit element and the quantum circuit element.

SEMICONDUCTOR LASER MOUNTING WITH INTACT DIFFUSION BARRIER LAYER

A first contact (310) surface of a semiconductor laser chip (302) is formed to a surface roughness selected to have a maximum peak to valley height that is substantially smaller than a diffusion barrier layer thickness. A diffusion barrier layer that includes a non-metallic, electrically-conducting compound and that has the barrier layer thickness is applied to the first contact surface, and the semiconductor laser chip is soldered to a carrier mounting (304) along the first contact surface using a solder composition (306) by heating the soldering composition to less than a threshold temperature at which dissolution of the barrier layer into the soldering composition occurs. Thereby the diffusion barrier remains contiguous. The non-metallic, electrically conducting compound may comprise at least one of titanium nitride, titanium oxy-nitride, tungsten nitride, cerium oxide and cerium gadolinium oxy-nitride ...

ELECTRONIC DEVICES UTILIZING CONTACT PADS WITH PROTRUSIONS AND METHODS FOR FABRICATION

An electronic device includes a substrate including a front side, a back side, a thickness between the front side and back side, one or more front- side vias extending from the front side into a part of the thickness, and an interconnect via extending from the back side toward the front side; a contact pad on the front side and including one or more protrusions extending through corresponding front- side vias and into the interconnect via; and an interconnect extending through the interconnect via and into contact with the protrusion(s).

LOW TEMPERATURE METHOD AND COMPOSITIONS FOR PRODUCING ELECTRICAL CONDUCTORS

A composition for matter having a metal powder or powders for specified characteristics in a Reactive Organic Medium (ROM). These compositions can be applied by any convenient printing process to produce patterns of electrical conductors on temperature-sensitive electronic substrates. The patterns can be thermally cured in seconds to form pure metal conductors at a temperature low enough to avoid damaging the substrate.

CHIP PACKAGE, METHOD OF FORMING A CHIP PACKAGE AND METHOD OF FORMING AN ELECTRICAL CONTACT

Conductive particles, anisotropic conductive material and connection structure

DEVICE SEMICONDUCTOR HAS DIODE AND MANUFACTORING PROCESS

Microelectronic device chip including hybrid bump, package thereof, LCD apparatus having the same and method for fabricating the microelectronic device chip

반도체 장치 및 그 형성방법

... 관통 전극을 갖는 반도체 장치가 제공된다. 상기 반도체 장치의 기판을 관통하는 TSV를 둘러싸는 에어 갭에 의하여 상기 TSV가 형성된 반도체 소자에 인가하는 스트레스가 완화되어, 상기 반도체 소자의 전기적 특성 및 신뢰성이 향상될 수 있다.

METHOD FOR FORMING INTERCONNECT STRUCTURE

MULTI-CHIP SEMICONDUCTOR PACKAGE AND A METHOD FOR FORMING THE SAME CAPABLE OF IMPROVING PRODUCTION EFFICIENCY

PURPOSE: A multi-chip semiconductor package and a method for forming the same are provided to reduce a chip crack by using an insulating layer, a protrusion electrode, and an interconnection. CONSTITUTION: A first semiconductor chip(11) having a first protrusion electrode(17) is formed on the upper surface. A second semiconductor chip(21) having a second protrusion electrode(27) is formed on the first semiconductor chip. An insulating layer(8) is formed between the first protrusion electrode and the second protrusion electrode. A groove is formed on the insulating layer. The first protrusion electrode is interconnected with the second protrusion electrode by filling the groove. COPYRIGHT KIPO 2013 ...

Semiconductor structure, 3dic structure and method of fabricating the same

Package carrier and bonding structure

A package carrier including a substrate, at least a under bump metallurgic (UBM) layer and at least a conductive bump is provided. The substrate has a conductive structure and at least a pad connected with the conductive structure, wherein the region of the pad connected with the conductive structure is a signal source region. The UBM layer is disposed on the pad. The UBM layer includes a first conductive pattern and a second conductive pattern. The side wall of the second conductive pattern is directly connected to the side wall of the first conductive pattern, and the second pattern is disposed near the signal source region, wherein the conductivity of the second conductive pattern is smaller than the conductivity of the first conductive pattern. The conductive bump is disposed on the UBM layer.

Copper interconnection with conductive polymer layer and method of forming the same

A conductive polymer between two metallic layers, acts as a glue layer, a barrier layer or an activation seed layer. The conductive polymer layer is employed to encapsulate a copper interconnection structure to prevent copper diffusion into any overlying layers and improve adhesive characteristics between the copper and any overlying layers.

Semiconductor device, manufacturing method for semiconductor device, electronic component, circuit substrate, and electronic apparatus

A semiconductor device includes: a semiconductor substrate including a first face and a second face on a side opposite to the first face; an external connection terminal formed on the first face of the semiconductor substrate; a first electrode formed on the first face of the semiconductor substrate and electrically connected to the external connection terminal; an electronic element formed on or above the second face of the semiconductor substrate; a second electrode electrically connected to the electronic element and having a top face and a rear face; a groove portion formed on the second face of the semiconductor substrate and having a bottom face including at least part of the rear face of the second electrode; and a conductive portion formed in the groove portion and electrically connected to the rear face of the second electrode.

Three dimensional memory device having embedded dynamic random access memory units

Embodiments of a three-dimensional (3D) memory device and a forming method thereof are disclosed. In an example, a 3D memory device comprises a first semiconductor structure, wherein the first semiconductor structure comprises peripheral circuits, an array of embedded dynamic random access memory (DRAM) units and a first bonding layer comprising a plurality of first bonding contacts. The 3D memory device further comprises a second semiconductor structure, wherein the second semiconductor structure comprises an array of 3D NAND memory strings and a second bonding layer comprising a plurality of second bonding contacts. The 3D memory device further comprises a bonding interface located between the first bonding layer and the second bonding layer. The first bonding contacts are in contact with the second bonding contacts in the bonding interface.

Method for forming the package structure

A method for forming the package structure is provided. The method includes forming a die structure over a first surface of a first substrate, and forming a plurality of electrical connectors below a second surface of the first substrate. The method also includes forming a first protruding structure below the second surface of the first substrate, and the electrical connectors are surrounded by the first protruding structure. The method further includes forming a second protruding structure over a second substrate, and bonding the first substrate to the second substrate. The electrical connectors are surrounded by the second protruding structure, and the first protruding structure does not overlap with the second protruding structure.

Non-volatile memory device and manufacturing method thereof

A non-volatile memory device includes a first substrate, a second substrate, a memory array, a circuit structure, a bonding structure, and a shielding structure. A second front side of the second substrate faces a first front side of the first substrate. The memory array is disposed on the first substrate and disposed at the first front side of the first substrate. The circuit structure is disposed on the second substrate and disposed at the second front side of the second substrate. The bonding structure is disposed between the memory array and the circuit structure. The circuit structure is electrically connected with the memory array through the bonding structure. The shielding structure is disposed between the memory array and the circuit structure and surrounds the bonding structure. The shielding structure is electrically connected to a voltage source.

Semiconductor device and method for fabricating the same

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a semiconductor substrate, a plurality of first set conductive elements separately positioned above the semiconductor substrate, a plurality of first set supporting pillars respectively correspondingly positioned between an adjacent pairs of the plurality of first set conductive elements, and a plurality of spaces respectively correspondingly positioned adjacent to the plurality of first set supporting pillars.

SEMICONDUCTOR DEVICE PACKAGE AND MANUFACTURING METHOD THEREOF

Semiconductor device, circuit substrate, electro-optic device and electronic appliance

The invention aims to provide a semiconductor device 121 that enables to securely perform a conductive connection with the opposing substrate. A semiconductor device 121 in the first embodiment includes: an electrode pad 24 and a resin projection 12, formed on an active surface 121a; a conductive film 20 deposited from a surface of the electrode pad 24 to a surface of the resin projection 12; a resin bump 10 formed with the resin projection 12 and with the conductive film 20. The semiconductor device 121 is conductively connected to the opposing substrate through the resin bump electrode 10. The testing electrode 30 is formed with the conductive film 20 that is extended and applied to the opposite side of the electrode pad 24 across the resin projection 12.

Packaged electronic devices having die attach regions with selective thin dielectric layer

A packaged electronic device including a package substrate having a top substrate surface including a die attach region including at least one land pad thereon and a first dielectric layer positioned lateral to the land pad and a non-die attach region. The non-die attach region includes a second dielectric layer, wherein a thickness of the second dielectric layer is>a thickness of the first dielectric layer by at least 5 m. An IC die has a top semiconductor surface including active circuitry and at least one bonding conductor formed on the top semiconductor surface, and a bottom surface, wherein the bonding conductor of the IC die is joined to the land pad of the package substrate. An underfill layer is between the IC die and the die attach region.

SEMICONDUCTOR DEVICES HAVING CRACK-INHIBITING STRUCTURES

Semiconductor devices having metallization structures including crack-inhibiting structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a metallization structure formed over a semiconductor substrate. The metallization structure can include a bond pad electrically coupled to the semiconductor substrate via one or more layers of conductive material, and an insulating material—such as a low-κ dielectric material—at least partially around the conductive material. The metallization structure can further include a crack-inhibiting structure positioned beneath the bond pad between the bond pad and the semiconductor substrate. The crack-inhibiting structure can include (a) a metal lattice extending laterally between the bond pad and the semiconductor substrate and (b) barrier members extending vertically between the metal lattice and the bond pad.

Interconnect structures for preventing solder bridging, and associated systems and methods

Semiconductor dies having interconnect structures formed thereon, and associated systems and methods, are disclosed herein. In one embodiment, an interconnect structure includes a conductive material electrically coupled to an electrically conductive contact of a semiconductor die. The conductive material includes a first portion vertically aligned with the conductive contact, and a second portion that extends laterally away from the conductive contact. A solder material is disposed on the second portion of the interconnect structure such that the solder material is at least partially laterally offset from the conductive contact of the semiconductor die. In some embodiments, an interconnect structure can further include a containment layer that prevents wicking or other undesirable movement of the solder material during a reflow process.

Method of Interconnecting substrates for electrical coupling of microelectronic components

Interconnecting substrates used in the manufacturing of microelectronic devices and printed circuit assemblies, packaged microelectronic devices having interconnecting substrates, and methods of making and using such interconnecting substrates. In one aspect of the invention, an interconnecting substrate comprises a first external layer having a first external surface, a second external layer having a second external surface, and a conductive core between the first and second external layers. The conductive core can have at least a first conductive stratum between the first and second external layers, and a dielectric layer between the first conductive stratum and one of the first or second external layers. The conductive core can also include a second conductive stratum such that the first conductive stratum is on a first surface of the dielectric layer and the second conductive stratum is on a second surface of the dielectric layer. The interconnecting substrate also has at least one ...

Thin metal barrier for electrical interconnections

An interconnect structure and barrier layer for electrical interconnections is described incorporating a layer of TaN in the hexagonal phase between a first material such as Cu and a second material such as Al, W, and PbSn. A multilayer of TaN in the hexagonal phase and Ta in the alpha phase is also described as a barrier layer. The invention overcomes the problem of Cu diffusion into materials desired to be isolated during temperature anneal at 500° C.

Method of forming a temporary test structure for device fabrication

A method of forming a temporary test structure for device fabrication is provided. The method is particularly useful for electrically testing conductive interconnects during controlled collapse chip connections (C4) fabrication and/or through-silicon vias (TSVs) during interposer fabrication. The method includes providing a substrate containing a plurality of electrically conductive interconnects extending vertically to top surface of the substrate. A temporary test structure is formed to connect the plurality of interconnects and for electrical testing. The suitable material for the temporary test structure is TiW for a single layer structure, or Cu or Cu alloy over Ti or TiW for a bilayer structure with thickness in a range of about 20 nm to 1200 nm. Excimer laser ablation can be used to form the temporary test structure. Electrical testing is performed on the substrate by probing at different test locations on the temporary test structure. All or part of the temporary test structure ...

Interconnect structure and method of fabricating same

An interconnect structure and a method of fabrication of the same are introduced. In an embodiment, a post passivation interconnect (PPI) structure is formed over a passivation layer of a substrate. A bump is formed over the PPI structure. A molding layer is formed over the PPI structure. A film is applied over the molding layer and the bump using a roller. The film is removed from over the molding layer and the bump, and the remaining material of the film on the molding layer forms the protective layer. A plasma cleaning is preformed to remove the remaining material of the film on the bump.

Semiconductor device comprising a chip substrate, a mold, and a buffer layer

A semiconductor device and a method of manufacturing the semiconductor device are disclosed. The semiconductor device includes a chip substrate, a mold, and a buffer layer. The mold is disposed over the chip substrate. The buffer layer is externally embedded between the chip substrate and the mold. The buffer layer has an elastic modulus or a coefficient of thermal expansion less than that of the mold. The method includes disposing a buffer layer at least covering scribe lines of a substrate, forming a mold over the substrate and covering the buffer layer, and cutting along the scribe lines and through the mold, the buffer layer and the substrate.

DIE STRUCTURE, DIE STACK STRUCTURE AND METHOD OF FABRICATING THE SAME

Provided is a die structure including a die, a bonding structure, and a protection structure. The die includes a substrate and a metal feature disposed over the substrate. The bonding structure is disposed over the die. The bonding structure includes a bonding dielectric layer and a bonding metal layer disposed in the bonding dielectric layer. The bonding metal layer is electrically connected to the metal feature of the die. The protection structure is disposed between a top portion of the bonding metal layer and a top portion of the bonding dielectric layer. A die stack structure and a method of fabricating the die structure are also provided.

SEMICONDUCTOR MEMORY DEVICE

A semiconductor memory device includes a circuit chip including a first substrate, peripheral circuit elements which are defined on the first substrate and a first dielectric layer which covers the peripheral circuit elements, and having first pads which are coupled to the peripheral circuit elements, on one surface thereof; a memory chip including a second substrate which is disposed on a base dielectric layer, a memory cell array which is defined on the second substrate and a second dielectric layer which covers the memory cell array, and having second pads which are coupled with the first pads, on one surface thereof which is bonded with the one surface of the circuit chip; a contact passing through the base dielectric layer and the second dielectric layer; and one or more dummy contacts passing through the base dielectric layer and the second dielectric layer, and disposed around the contact.

NON-DESTRUCTIVE TESTING OF INTEGRATED CIRCUIT CHIPS

Semiconductor devices and electronics packaging methods include integrated circuit chips having redundant signal bond pads along with signal bond pads connected to the same signal port for non-destructive testing of the integrated circuit chips prior to packaging. Electrical testing is made via the redundant signal bond after which qualified integrated circuit chips can be attached to a pristine and bumped final interposer or printed circuit board to provide increased reliability to the assembled electronic package.

Semiconductor package and manufacturing method thereof

A semiconductor package includes a redistribution structure, a memory wafer, semiconductor dies and conductive vias. The memory wafer, disposed over the redistribution structure, includes at least one memory die. The semiconductor dies are disposed side by side with respect to each other, between the memory wafer and the redistribution structure, and are electrically connected to the redistribution structure. The conductive vias electrically connect the at least one memory die with the redistribution structure. A semiconductor package includes a redistribution structure, a reconstructed wafer, and a heat sink. The reconstructed wafer is disposed on the redistribution structure. The reconstructed wafer includes logic dies and memory dies. The logic dies are electrically connected to the redistribution structure. The memory dies are electrically connected to the redistribution structure and vertically stacked with the logic dies. The heat sink is disposed on the reconstructed wafer. The heat ...

Thin film metal barrier for electrical interconnections

An interconnect structure and barrier layer for electrical interconnections is described incorporating a layer of TaN in the hexagonal phase between a first material such as Cu and a second material such as Al, W, and PbSn. A multilayer of TaN in the hexagonal phase and Ta in the alpha phase is also described as a barrier layer. The invention overcomes the problem of Cu diffusion into materials desired to be isolated during temperature anneal at 500° C.

Seal Ring in an Integrated Circuit Die

The formation of a seal ring in a semiconductor integrated circuit (IC) die is described. Through-silicon vias (TSVs) are typically formed in a semiconductor IC die to facilitate the formation of a three dimensional (3D) stacking die structure. The TSVs may be utilized to provide electrical connections between components in different dies of the 3D stacking die structure. A seal ring is formed in the inter-metal dielectric (IMD) layers of an IC die, enclosing an active circuit region. The real ring is formed prior to the formation of the TSVs, preventing moistures or other undesired chemical agents from diffusing into the active circuit region during the subsequent processes of forming TSVs.

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME

A semiconductor structure is provided. The semiconductor structure includes a first semiconductor device. The first semiconductor device includes a first bonding layer formed below a first substrate, a first bonding via formed through the first oxide layer and the first bonding layer, a first dummy pad formed in the first bonding layer. The semiconductor structure includes a second semiconductor device. The second semiconductor device includes a second bonding layer formed over a second substrate, a second bonding via formed through the second bonding layer, and a second dummy pad formed in the second bonding layer. The semiconductor structure includes a bonding structure between the first substrate and the second substrate, wherein the bonding structure includes the first bonding via bonded to the second bonding via and the first dummy pad bonded to the second dummy pad.

Bundle of long thin carbon structures, manufacturing method thereof, and electronic device

In the bundle of long thin carbon structures of the present invention, end parts of the bundle are interconnected in a carbon network. The interconnected end parts form a flat surface. By this, an electrical connection structure with low resistance and/or a thermal connection structure with high thermal conductivity are obtained. The bundle of long thin carbon structures can be used suitably as a via, heat removal bump or other electronic element.

Interconnect And Method For Mounting An Electronic Device To A Substrate

An interconnect for mounting an electronic device to a substrate includes a base layer between the electronic device and the substrate in electrical communication with integrated circuits on the electronic device, a phase change layer on the base layer made of a material which is liquid at normal operating temperatures of the electronic device. and a retaining layer surrounding the phase change layer, and configured to retain the phase change layer in liquid form on the base layer. A method for mounting an electronic device to a substrate includes the steps of: forming a base layer on the device (or on the substrate); forming a phase change layer on the base layer; placing the phase change layer in contact with a corresponding electrode on the substrate (or on the device); and then forming a retaining layer between the device and the substrate configured to surround the base layer, the phase change layer, and the electrode, and to retain the phase change layer in liquid form between the ...

3D chip-stack with fuse-type through silicon via

Programmable fuse-type through silicon vias (TSVs) in silicon chips are provided with non-programmable TSVs in the same chip. The programmable fuse-type TSVs may employ a region within the TSV structure having sidewall spacers that restrict the cross-sectional conductive path of the TSV adjacent a chip surface contact pad. Application of sufficient current by programming circuitry causes electromigration of metal to create a void in the contact pad and, thus, an open circuit. Programming may be carried out by complementary circuitry on two adjacent chips in a multi-story chip stack.

SEMICONDUCTOR PACKAGE

A semiconductor package includes a first semiconductor chip having a first chip substrate, the first chip substrate having a first upper surface and a first lower surface opposite to each other, a first through-silicon via (TSV), a lower connection pad and a first lower passivation layer on the first lower surface of the first chip substrate, the first lower passivation layer exposing a portion of the lower connection pad, an upper connection pad and a first upper passivation layer on the first upper surface of the first chip substrate, the first upper passivation layer including a first upper inorganic material layer, and a second semiconductor chip connected to the first semiconductor chip, the second semiconductor chip including a second TSV, wherein the first lower passivation layer has a stacked structure of a first lower inorganic material layer and a lower organic material layer.

Semiconductor device having under-filled die in a die stack

A semiconductor device including a semiconductor die in a die stack under-filled with a film. Once the semiconductor die are formed, they may be stacked and interconnected. The interconnection may leave a small space between semiconductor die in the die stack. This space is advantageously completely filled using a vapor deposition process where a coating is deposited as a vapor which flows over all surfaces of the die stack, including into the spaces between the die in the stack. The vapor then deposits on the surfaces between and around the die and forms a film which completely fills the spaces between the die in the die stack. The material used in the vapor deposition under-fill process may for example be a member of the parylene family of polymers, and in embodiments, may be parylene-N.

Semiconductor packaging structure and manufacturing method thereof

A semiconductor structure includes a die, a molding interfacing with the die along a first direction, wherein a coefficient of thermal expansion (CTE) mismatch is between the molding and the die, a via extending within and through the molding, an elongated member extending within the molding and at least partially along the first direction, a conductive trace over the elongated member and the die, and a dielectric between the elongated member and the conductive trace, wherein the elongated member is proximal to the die than the via.

SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURE

A semiconductor package including a first interposer comprising a first substrate, first optical components over the first substrate, a first dielectric layer over the first optical components, and first conductive connectors embedded in the first dielectric layer, a photonic package bonded to a first side of the first interposer, where a first bond between the first interposer and the photonic package includes a dielectric-to-dielectric bond between a second dielectric layer on the photonic package and the first dielectric layer, and a second bond between the first interposer and the photonic package includes a metal-to-metal bond between a second conductive connector on the photonic package and a first one of the first conductive connectors and a first die bonded to the first side of the first interposer.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

PROBLEM TO BE SOLVED: To improve characteristics of a semiconductor device in a high frequency region. SOLUTION: A semiconductor device 20A is formed with an emitter pad electrode 23E, a collector pad electrode 23C, and a base pad electrode 23B connected with an active region 21, on the surface of a semiconductor substrate 25. Further, a back electrode 26 is formed on the backside of the semiconductor substrate 25. Further, the emitter pad electrode 23E connected with a ground potential is connected with the back electrode 26 through a through-electrode 24A that passes through the semiconductor substrate 25 in a thickness direction. COPYRIGHT: (C)2007,JPO&INPIT ...

СВЕТОИЗЛУЧАЮЩЕЕ УСТРОЙСТВО И СПОСОБ ЕГО ИЗГОТОВЛЕНИЯ

Предложено светоизлучающее устройство и способ изготовления устройства, которое может испускать свет с малой неравномерностью цвета и высокой яркостью. Устройство включает светоизлучающий прибор, светопроницаемый элемент, принимающий падающий свет от светоизлучающего прибора, и покрывающий элемент. Светопроницаемый элемент сформирован из неорганического материала и является преобразующим свет элементом, включающим непокрытую снаружи светоизлучающую поверхность и боковую поверхность, примыкающую к светоизлучающей поверхности. Покрывающий элемент содержит отражающий материал и покрывает, по меньшей мере, боковые поверхности светопроницаемого элемента. По существу, только светоизлучающая поверхность выполняет функцию области излучения устройства. Имеется возможность обеспечить испускаемый свет, имеющий превосходную направленность и яркость. Испускаемый свет можно легко оптически регулировать. Если каждое светоизлучающее устройство используется в качестве единичного источника света, светоизлучающее ...

Verfahren zur Herstellung einer Kontaktierungsvorrichtung auf einem keramischen Substrat sowie eine nach dem Verfahren erzeugte Kontaktierungsvorrichtung

Verfahren zur Herstellung einer Kontaktierungsvorrichtung auf einem keramischen Substrat (201) umfassend• einen ersten Schritt (101) in dem ein Substrat (201) aus einem keramischen Material bereitgestellt wird, wobei auf oder im Substrat (201) eine elektrische Schaltung angeordnet ist, und• einen dritten Schritt (103) in dem ein Anschlusselement (206) bereitgestellt wird, und dadurch gekennzeichnet, dass• in einem zweiten Schritt (102) ein Kontaktelement (204) haftend auf einem lokal begrenzten, mit der Schaltung elektrisch verbundenen Kontaktierungsbereich auf einer Oberfläche (202) des Substrats (201), in einer Vertiefung (203) im Substrat (201) mittels eines maskenlosen kontinuierlichen Materialauftrags mit gleichzeitiger Aushärtung aufgebracht wird, wobei das Kontaktelement (204) mit einer Schichtdicke (205) erzeugt wird, deren Höhe größer als wenigstens eine laterale Ausdehnungsbreite des Kontaktelementes (204) ist, und• in einem vierten Schritt (104) das Anschlusselement (206) auf ...

Semiconductor laser mounting with intact diffusion barrier layer

A first contact (310) surface of a semiconductor laser chip (302) is formed to a surface roughness selected to have a maximum peak to valley height that is substantially smaller than a diffusion barrier layer thickness. A diffusion barrier layer that includes a non-metallic, electrically-conducting compound and that has the barrier layer thickness is applied to the first contact surface, and the semiconductor laser chip is soldered to a carrier mounting (304) along the first contact surface using a solder composition (306) by heating the soldering composition to less than a threshold temperature at which dissolution of the barrier layer into the soldering composition occurs. Thereby the diffusion barrier remains contiguous. The non-metallic, electrically conducting compound may comprise at least one of titanium nitride, titanium oxy-nitride, tungsten nitride, cerium oxide and cerium gadolinium oxy-nitride ...

LOW TEMPERATURE METHOD AND COMPOSITIONS FOR PRODUCING ELECTRICAL CONDUCTORS

A composition for matter having a metal powder or powders for specified characteristics in a Reactive Organic Medium (ROM), These compositions can be applied by any convenient printing process to produce patterns of electrical conductors on temperature-sensitive electronic substrates. The patterns can be thermally cured in seconds to form pure metal conductors at a temperature low enough to avoid damaging the substrate.

Conformal dummy die

지문센서 패키지

... 본 발명은 지문센서 패키지에 관한 것으로, 해결하고자 하는 기술적 과제는 도전성 범프와 지문센싱부가 반도체 다이의 일면에 구비되고, 타면에 구비된 보호판이나 보호막에 지문이 인접할 경우, 정전용량 변화를 통해 지문을 센싱할 수 있고, 지문센싱부가 구비된 반도체 다이가 기판에 플립칩 타입으로 안착되므로, 공정을 간소화하는데 있다.

앵커 인터커넥트

... 실시예는, 하부 및 상부 금속 층들 사이의 복수의 금속 층들을 포함하는 백엔드 부분 - 상부 금속 층은 제1 및 제2의 대향하는 측벽 표면들 및 측벽 표면들을 서로 결합하는 상부 표면을 갖는 상부 금속 층 부분을 포함함 -; 상부 표면에 직접적으로 접촉하는 절연체 층; 및 상부 금속 층 부분에 접촉 범프를 결합하는 비아를 포함하며; 백엔드 부분에 결합되는 기판에 직교하는 제1 수직 축이 접촉 범프, 질화물 층, 비아, 및 상부 금속 층 부분을 가로지르는 반도체 구조체를 포함한다. 다른 실시예들이 본 명세서에 설명된다.

Semiconductor device and manufacturing method thereof

A semiconductor device includes a substrate including a surface, a plurality of pads disposing on the surface of the substrate, the plurality of pads includes a non-solder mask defined (NSMD) pad and a solder mask defined (SMD) pad, and the NSMD pad is arranged at a predetermined location. Further, a method of manufacturing a semiconductor device includes providing a substrate, disposing a plurality of pads on a surface of the substrate, disposing a solder mask over the surface of the substrate and the plurality of pads, forming a first recess in the solder mask to surround one of the plurality of pads, and forming a second recess in the solder mask and above one of the plurality of pads.

Semiconductor packaging and manufacturing method thereof

The present disclosure provides a semiconductor package, which includes a substrate, a passivation layer, a post-passivation interconnect (PPI) having a top surface; and a conductive structure. The top surface of the PPI includes a first region receiving the conductive structure, and a second region surrounding the first region. The second region includes metal derivative transformed from materials made of the first region. The present disclosure provide a method of manufacturing a semiconductor package, including forming a first flux layer covering a portion of a top surface of a PPI; transforming a portion of the top surface of the PPI uncovered by the first flux layer into a metal derivative layer; removing the first flux layer; forming a second flux layer on the first region of the PPI; dropping a solder ball on the flux layer; and forming electrical connection between the solder ball and the PPI.

3di solder cup

A substrate or semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a solder cup. The semiconductor device assembly includes a substrate disposed over another substrate. At least one solder cup extends from one substrate towards an under bump metal (UBM) on the other substrate. The barrier on the exterior of the solder cup may be a standoff to control a bond line between the substrates. The barrier may reduce solder bridging during the formation of a semiconductor device assembly. The barrier may help to align the solder cup with a UBM when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of substrates and/or semiconductor devices.

Three-dimensional integrated circuit structures

Three-dimensional integrated circuit structures are disclosed. A three-dimensional integrated circuit structure includes a first die, a second die and a device-free die. The first die includes a first device. The second die includes a second device and is bonded to the first die. The device-free die is located aside the second die and is bonded to the first die. The device-free die includes a conductive feature electrically connected to the first die and the second die.

Semiconductor device and manufacturing method thereof

BIOSENSOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

SEMICONDUCTOR PACKAGE

A semiconductor package including a first semiconductor chip having a first thickness, a second semiconductor chip on the first semiconductor chip and having a second thickness, the second thickness being smaller than the first thickness, a third semiconductor chip on the second semiconductor chip and having a third thickness, the third thickness being smaller than the second thickness, a fourth semiconductor chip on the third semiconductor chip and having a fourth thickness, the fourth thickness being greater than the third thickness, and a fifth semiconductor chip disposed on the fourth semiconductor chip and having a fifth thickness, the fifth thickness being greater than the fourth thickness may be provided.

CHIP PACKAGE, METHOD OF FORMING A CHIP PACKAGE AND METHOD OF FORMING AN ELECTRICAL CONTACT

In various embodiments, a method of forming an electrical contact is provided. The method may include depositing, by atomic layer deposition, a passivation layer over at least a region of a metal surface, wherein the passivation layer may include aluminum oxide, and electrically contacting the region of the metal surface with a metal contact structure, wherein the metal contact structure may include copper.

T-shaped post for semiconductor devices

A T-shaped post for semiconductor devices is provided. The T-shaped post has an under-bump metallization (UBM) section and a pillar section extending from the UBM section. The UBM section and the pillar section may be formed of a same material or different materials. In an embodiment, a substrate, such as a die, wafer, printed circuit board, packaging substrate, or the like, having T-shaped posts is attached to a contact of another substrate, such as a die, wafer, printed circuit board, packaging substrate, or the like. The T-shaped posts may have a solder material pre-formed on the pillar section such that the pillar section is exposed or such that the pillar section is covered by the solder material. In another embodiment, the T-shaped posts may be formed on one substrate and the solder material formed on the other substrate.

BUNDLE OF LONG THIN CARBON STRUCTURES, MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE

In the bundle of long thin carbon structures of the present invention, end parts of the bundle are interconnected in a carbon network. The interconnected end parts form a flat surface. By this, an electrical connection structure with low resistance and/or a thermal connection structure with high thermal conductivity are obtained. The bundle of long thin carbon structures can be used suitably as a via, heat removal bump or other electronic element.

Semiconductor package having memory devices stacked on logic device

A semiconductor package includes a base substrate, a logic device with a serializer/deserializer (SerDes), a plurality of odd memory devices disposed on a lower surface of the logic device and operatively stack-connected with the SerDes, and a plurality of even memory devices disposed on an upper surface of the logic device and operatively stack-connected with the SerDes, such that the plurality of odd memory devices and the plurality of even memory devices are connected in parallel by the SerDes.

NONVOLATILE MEMORY DEVICES

Nonvolatile memory device includes memory cell region including a first metal pad and a second metal pad, peripheral circuit region including a third metal pad and a fourth metal pad, vertically connected to the memory cell region. The nonvolatile memory device includes a page buffer circuit including page buffers to sense data from selected memory cells, each including two sequential sensing operations to determine one data state, and each of the page buffers including a latch to sequentially store results of the two sequential sensing operations. The nonvolatile memory device includes control circuit in the peripheral circuit region, to control the page buffers to store result of the first read operation, reset the latches after completion of the first read operation, and control the page buffers to perform the second read operation based on a valley determined based on the result of the first read operation.

Method for fabricating semiconductor component with adjustment circuitry for electrical characteristics or input/output configuration

A semiconductor component includes adjustment circuitry configured to adjust selected physical and electrical characteristics of the component or elements thereof, and an input/output configuration of the component. The component includes a semiconductor die, a substrate attached to the die, and terminal contacts on the substrate. The adjustment circuitry includes conductors and programmable links, such as fuses or anti-fuses, in electrical communication with the die and the terminal contacts. The adjustment circuit can also include capacitors and inductance conductors. The programmable links can be placed in a selected state (e.g., short or open) using a laser or programming signals. A method for fabricating the component includes the steps of forming the adjustment circuitry, and then placing the programmable links in the selected state to achieve the selected adjustment.

NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME

According to an exemplary embodiment of the inventive concept, there is provided a nonvolatile memory device comprising: a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, a memory cell array, in the memory cell region, comprising a plurality of memory cells, a plurality of word lines and a bit line connected to the memory cells, wherein each memory cell is connected to one of the word lines, a voltage generator, in the peripheral circuit region, supplying a plurality of supply voltages to the memory cell array, a control logic circuit, in the peripheral circuit region, programming a selected one of the memory cells connected to a selected one of the word lines into a first program state by controlling the voltage generator, and a verify circuit, in the peripheral circuit region, controlling a verify operation on the memory cell array ...

Single mask package apparatus and method

Disclosed herein is a single mask package apparatus on a device comprising a first substrate having a land disposed on a first surface, a stud disposed on the land and a protective layer disposed over the first surface of the first substrate and around the stud. The protective layer may optionally have a thickness of at least 3 m. A PPI may be disposed over the protective layer and in electrical contact with the stud, with a first portion of the PPI extending laterally from the stud. An interconnect may be disposed on and in electrical contact with the first portion of the PPI, and a second substrate mounted on the interconnect. A molding compound may be disposed over the PPI and around the interconnect. The stud may be a substantially solid material having a cylindrical cross section and may optionally be wirebonded to the land.

Semiconductor device, manufacturing method for semiconductor device, electronic component, circuit substrate, and electronic apparatus

A semiconductor device includes: a semiconductor substrate including a first face and a second face on a side opposite to the first face; an external connection terminal formed on the first face of the semiconductor substrate; a first electrode formed on the first face of the semiconductor substrate and electrically connected to the external connection terminal; an electronic element formed on or above the second face of the semiconductor substrate; a second electrode electrically connected to the electronic element and having a top face and a rear face; a groove portion formed on the second face of the semiconductor substrate and having a bottom face including at least part of the rear face of the second electrode; and a conductive portion formed in the groove portion and electrically connected to the rear face of the second electrode.

Method for manufacturing semiconductor device and semiconductor device

A semiconductor device includes: a connecting body including a connecting electrode; and at least one semiconductor chip stacked on the connecting body, the semiconductor chip including: a substrate; and a trans-substrate conductive plug that penetrates the substrate, the trans-substrate conductive plug having a first terminal that is provided on an active surface side of the substrate; and a second terminal that is provided on a back surface side that is opposite the active surface side, an outer shape of the first terminal being formed larger than an outer shape of the second terminal, wherein the second terminal of the semiconductor chip is electrically connected to a connecting electrode of the connecting body via a brazing material.

Top layers of metal for high performance IC's

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Increased contact alignment tolerance for direct bonding

A bonded device structure including a first substrate having a first set of conductive contact structures, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the contact structures on the first substrate, a second substrate having a second set of conductive contact structures, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the contact structures on the second substrate, and a contact-bonded interface between the first and second set of contact structures formed by contact bonding of the first non-metallic region to the second non-metallic region. The contact structures include elongated contact features, such as individual lines or lines connected in a grid, that are non-parallel on the two substrates, making contact at intersections. Alignment tolerances are thus improved while minimizing dishing and parasitic capacitance.

RADIOFREQUENCY DEVICE AND MANUFACTURING METHOD THEREOF

A radiofrequency device includes a buried insulation layer, a transistor, a contact structure, a connection bump, an interlayer dielectric layer, and a mold compound layer. The buried insulation layer has a first side and a second side opposite to the first side in a thickness direction of the buried insulation layer. The transistor is disposed on the first side of the buried insulation layer. The contact structure penetrates the buried insulation layer and is electrically connected with the transistor. The connection bump is disposed on the second side of the buried insulation layer and electrically connected with the contact structure. The interlayer dielectric layer is disposed on the first side of the buried insulation layer and covers the transistor. The mold compound layer is disposed on the interlayer dielectric layer. The mold compound layer may be used to improve operation performance and reduce manufacturing cost of the radiofrequency device.

SEMICONDUCTOR MODULE, DISPLAY DEVICE, AND SEMICONDUCTOR MODULE MANUFACTURING METHOD

Resin covers a side surface and a back surface of a blue LED and holds the blue LED level. An electrode is disposed between a top surface of a wiring substrate and a back surface of the blue LED, extends through the resin, and electrically connects the wiring substrate and the blue LED to each other. A light-outgoing surface (top-surface) of the blue LED is exposed without being covered with the resin, and the light-outgoing surface (top-surface) is flush with a top surface of the resin.

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF

A semiconductor package includes a first semiconductor die and a second semiconductor die disposed laterally adjacent one another. The semiconductor package includes a semiconductor bridge overlapping a first corner of the first semiconductor die and a second corner of the second semiconductor die. The semiconductor bridge electrically couples the first semiconductor to the second semiconductor die. The semiconductor package includes a third semiconductor die and a fourth semiconductor die electrically coupled to the first semiconductor die and the second semiconductor die, respectively. The semiconductor bridge is interposed between the third semiconductor die and the fourth semiconductor die.

СВЕТОИЗЛУЧАЮЩЕЕ УСТРОЙСТВО И СПОСОБ ЕГО ИЗГОТОВЛЕНИЯ

... 1. Светоизлучающее устройство, содержащее: ! светоизлучающий прибор, ! светопроницаемый элемент, принимающий падающий свет от светоизлучающего прибора, и ! покрывающий элемент, ! причем светопроницаемый элемент образован преобразующим свет элементом из неорганического материала, который имеет светоизлучающую поверхность, непокрытую снаружи, и боковую поверхность, примыкающую к светоизлучающей поверхности, ! а покрывающий элемент содержит светоотражающий материал и покрывает по меньшей мере боковую поверхность светопроницаемого элемента. ! 2. Светоизлучающее устройство по п.1, в котором покрывающий элемент окружает светоизлучающий прибор. ! 3. Светоизлучающее устройство по п.2, в котором светопроницаемый элемент имеет форму пластины и содержит принимающую свет поверхность, противоположную указанной светоизлучающей поверхности, причем светоизлучающий прибор соединен с принимающей свет поверхностью. ! 4. Светоизлучающее устройство по п.3, в котором светоизлучающий прибор смонтирован на монтажной ...

Verfahren für die Ausbildung einer Verbindungsstruktur

Ein Verfahren für die Ausbildung von Verbindungsstrukturen weist das Ausbilden einer Metallleitung, die aus einem ersten leitfähigen Material besteht, über einem Substrat auf, sowie das Abscheiden einer dielektrischen Schicht über der Metallleitung, das Strukturieren der dielektrischen Schicht, um eine Öffnung auszubilden, das Abscheiden einer ersten Sperrschicht auf einer Unterseite sowie auf Seitenwänden der Öffnung unter Verwendung eines atomaren Schichtabscheidungsverfahrens, das Abscheiden einer zweiten Sperrschicht über der ersten Sperrschicht, wobei die erste Sperrschicht mit Erde verbunden ist, sowie das Ausbilden eines Pads, das aus einem zweiten leitfähigen Material besteht, in der Öffnung.

Halbleiterstruktur und dazugehöriges Herstellungsverfahren

Halbleiterstruktur, umfassend:einen leitenden Bump (101) zum Anordnen über einem Substrat (201); undein längliches ferromagnetisches Glied (102), das in seiner Längsrichtung eine zentrale Achse (102c) aufweist, die sich von einem ersten Ende (102a) zu einem zweiten Ende (102b) des länglichen ferromagnetischen Glieds (102) erstreckt, wobei das längliche ferromagnetische Glied (102) ein Verhältnis von Länge zu Breite von mindestens 1,5:1 hat;wobei das längliche ferromagnetische Glied (102) von dem leitenden Bump (101) umgeben ist und die zentrale Achse (102c) des länglichen ferromagnetischen Glieds (102) im Wesentlichen orthogonal zu dem Substrat (201) angeordnet ist; undeine leitende Spur (204) mit einem Schleifenabschnitt (204a) zum Erzeugen eines elektromagnetischen Felds und zum Ausrichten des leitenden Bumps (101) mit dem darin einschlossenen länglichen ferromagnetischen Glied (102) durch das von dem Schleifenabschnitt (204a) erzeugte elektromagnetische Feld.

Dichtringstruktur mit Metallpad

Ein Verfahren enthält: Bereitstellen eines Substrats mit einem Dichtringbereich und einem Schaltkreisbereich; Ausbilden einer Dichtringstruktur über dem Dichtringbereich; Ausbilden einer ersten vorderseitigen Passivierungsschicht über der Dichtringstruktur; Ätzen einer vorderseitigen Öffnung in der ersten vorderseitigen Passivierungsschicht benachbart zu einem äußeren Bereich der Dichtringstruktur; Ausbilden eines vorderseitigen Metallpads in der vorderseitigen Öffnung, um das vorderseitige Metallpad mit dem äußeren Bereich der Dichtringstruktur zu koppeln; Ausbilden einer ersten rückseitigen Passivierungsschicht unter der Dichtringstruktur; Ätzen einer rückseitigen Öffnung in die erste rückseitige Passivierungsschicht benachbart zum äußeren Bereich der Dichtringstruktur; und Ausbilden eines rückseitigen Metallpads in der rückseitigen Öffnung, um das rückseitige Metallpad mit dem äußeren Bereich der Dichtringstruktur zu koppeln. Außerdem werden Halbleitervorrichtungen angegeben, die durch ...

LOW-TEMPERATURE PROCEDURE AND COMPOSITIONS FOR THE PRODUCTION OF ELEKTI LEADERS

SUPERCONDUCTING BUMP BONDS

A device (100) includes a first chip (104) having a first circuit element (112), a first interconnect pad (116) in electrical contact (118) with the first circuit element, and a barrier layer (120) on the first interconnect pad, a superconducting bump bond (106) on the barrier layer, and a second chip (102) joined to the first chip by the superconducting bump bond, the second chip having a quantum circuit element (108), in which the superconducting bump bond provides an electrical connection between the first circuit element and the quantum circuit element.

INTEGRATED CIRCUITS WITH PASSIVATION AND METALLIZATION FOR HERMETIC PROTECTION

This invention relates to integrated circuits which are protected from the environment. Such circuits are sealed by applying a non-corroding metal layer to the bond pads and a passivation layer to the remainder of the circuit.

Method for mounting a semiconductor chip on a carrier

Semiconductor device and method of manufacturing the same

The invention provides a semiconductor device and a method of manufacturing the same. In this semiconductor device, the through-hole is formed in the substrate, and is located under the conductive pattern. The insulating layer is located at the bottom surface of the through-hole. The conductive pattern is located on one surface side of the substrate. The opening pattern is formed in the insulating layer which is located between the through-hole and the conductive pattern, where the distance r3 from the circumference of the opening pattern to the central axis of the through-hole is smaller than the distance r1 in the through-hole. By providing the opening pattern, the conductive pattern is exposed at the bottom surface of the through-hole. The bump is located on the back surface side of the substrate, and is formed integrally with the through-electrode.

Semiconductor device

The invention relates to a semiconductor device. The top surface of a semiconductor substrate is provided with at least one bonding pad. A passivation layer is located on the top surface of the semiconductor substrate. At least one opening located within the passivation layer exposes the bonding pad. A metal layer is stacked on the bonding pad.

METHOD OF MANUFACTURING INTEGRATED CIRCUIT BY DIRECTLY BONDING SUBSTRATES COMPRISING SURFACE PORTIONS OF COPPER AND OF DIELECTRIC MATERIAL

Procédé de réalisation d'un circuit intégré par collage direct d'un premier (201) et d'un second (301) substrats, comprenant les étapes suivantes consistant à a) former un premier et un second substrats munis chacun d'une surface comportant au moins une portion d'un premier matériau (205, 305) et des portions d'au moins un deuxième matériau (203, 303), une région de barrière (209, 309) en un troisième matériau étant disposée en surface entre chaque portion du premier matériau et le deuxième matériau; et b) mettre en contact la surface du premier substrat avec la surface du second substrat avec un désalignement maximum donné, la largeur de la région de barrière formée à l'étape a) étant choisie de sorte qu'elle soit supérieure au désalignement maximum.

반도체 장치, 반도체 패키지 및 반도체 패키지의 제조 방법

... 반도체 장치가 개시된다. 반도체 장치는, 기판 상에 형성된 도전 성분(conductive component); 상기 기판 상에 형성되며 개구부를 구비하는 패시베이션층으로서, 상기 개구부가 상기 도전 성분의 적어도 일부분을 노출하는, 상기 패시베이션층; 및 상기 패시베이션층 상에서 상기 개구부를 채우며, 상기 도전 성분과 전기적으로 연결되는 패드 구조물을 포함한다. 상기 패드 구조물은 상기 개구부의 내벽 상에 및 상기 개구부 주위의 상기 패시베이션층 상면 상에 콘포말하게 형성되며, 순서대로 적층된 도전 배리어층, 제1 시드층, 식각 정지층 및 제2 시드층을 포함하는 하부 도전층, 상기 하부 도전층 상에 형성되며, 상기 개구부를 적어도 부분적으로 채우는 제1 패드층, 및 상기 제1 패드층 상에 형성되며, 상기 패시베이션층의 상기 상면 상에 배치되는 상기 하부 도전층의 외주 부분과 접촉하는 제2 패드층을 포함한다.

METHOD FOR FABRICATING MODULE OF SEMICONDUCTOR CHIP

SEMICONDUCTOR DEVICE HAVING A BONDING PAD AND SHIELD STRUCTURE AND METHOD OF MANUFACTURING THE SAME

Package structures and methods of forming the same

Semiconductor device and method for bonding semiconductor structures

Chip structure, chip package structure and manufacturing thereof

A chip structure comprising a chip, a passivation layer, a buffer layer and a metal layer is provided, and a bump disposed on the metal layer for electrically connected a bonding pad of the chip. The passivation layer and the buffer layer are covered on an active surface of the chip, and have an opening respectively for exposing top surface of the bonding pad. Wherein, the buffer layer is utilized to make bump heat-pressed onto a contact of a substrate with good electrical performance. The buffer layer is made of polyimide or other macromolecule polymer. Moreover, the chip structure further comprises a plurality of buffer granular structure in the bottom of the bump to enhance the bonding reliability of the bump.

Conductive bump and electroless Pt plating bath

The present invention provides a bump that can prevent diffusion of a metal used as a base conductive layer of the bump into a surface of an Au layer or an Ag layer. A conductive bump of the present invention is s conductive bump formed on a substrate. The conductive bump comprises, at least in order from the substrate: a base conductive layer; a Pd layer; a Pt layer; and an Au layer or an Ag layer having directly contact with the Pd layer, wherein a diameter of the conductive bump is 20 [mu]m or less.

Method for manufacture of integrated circuit package system with protected conductive layers for pads

A method for manufacture of an integrated circuit package system includes: providing an integrated circuit die having a contact pad; forming a protection cover over the contact pad; forming a passivation layer having a first opening over the protection cover with the first opening exposing the protection cover; developing a conductive layer over the passivation layer; forming a pad opening in the protection cover for exposing the contact pad having the conductive layer partially removed; and an interconnect directly on the contact pad and only adjacent to the protection cover and the passivation layer.

Conductive connection structure with stress reduction arrangement for a semiconductor device, and related fabrication method

A semiconductor device disclosed herein includes a conductive connection structure having a stepped profile that serves as a stress relief feature. The conductive connection structure includes a stress buffer arrangement for a contact pad. The stress buffer arrangement has a stepped via that terminates at the contact pad, and the stepped via has a plurality of inwardly sloped and concentric sections in a stacked orientation. The connection structure also includes underbump metallization overlying at least a portion of the contact pad and lining the stepped via, and a conductive connection element coupled to the underbump metallization. The conductive connection element fills the lined recess.

Package carrier

A package carrier including a substrate, at least an under bump metallurgic (UBM) layer and at least a conductive bump is provided. The substrate has a conductive structure and at least a pad connected with the conductive structure. A region of the pad connected with the conductive structure is a signal source region. The UBM layer is disposed on the pad and includes a first conductive pattern and a second conductive pattern. A side wall of the second conductive pattern is directly connected to a side wall of the first conductive pattern, and the second conductive pattern is disposed close to the signal source region. The conductivity of the second conductive pattern is smaller than the conductivity of the first conductive pattern. The conductive bump is disposed on the UBM layer.

Semiconductor laser mounting with intact diffusion barrier layer

A first contact surface of a semiconductor laser chip can be formed to a target surface roughness selected to have a maximum peak to valley height that is substantially smaller than a barrier layer thickness. A barrier layer that includes a non-metallic, electrically-conducting compound and that has the barrier layer thickness can be applied to the first contact surface, and the semiconductor laser chip can be soldered to a carrier mounting along the first contact surface using a solder composition by heating the soldering composition to less than a threshold temperature at which dissolution of the barrier layer into the soldering composition occurs. Related systems, methods, articles of manufacture, and the like are also described.

Multi-chip semiconductor package and method of fabricating the same

A first semiconductor chip having a first projection electrode formed on an upper surface thereof is prepared. A second semiconductor chip having a second projection electrode is mounted on the first semiconductor chip to expose the first projection electrode. An insulating film is formed between the first projection electrode and the second projection electrode. A groove is formed in the insulating film. An interconnection configured to fill an inside of the groove and connected to the first projection electrode and the second projection electrode is formed.

On-Chip Heat Spreader

A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.

Methods of manufacturing stress buffer structures in a mounting structure of a semiconductor device

A mounting structure for a semiconductor device is formed to include a stepwise stress buffer layer under a stepwise UBM structure.

Wafer Level Semiconductor Package

There are disclosed herein various implementations of improved wafer level semiconductor packages. One exemplary implementation comprises forming a post-fabrication redistribution layer (post-Fab RDL) between first and second dielectric layers affixed over a surface of a wafer, and forming a window for receiving an electrical contact body in the second dielectric layer, the window exposing the post-Fab RDL. At least one of the first and second dielectric layers is a pre-formed dielectric layer, which may be affixed over the surface of the wafer using a lamination process. In one implementation, the window is formed using a direct laser ablation process.

Semiconductor device and method for production of semiconductor device

A semiconductor device with a connection pad in a substrate, the connection pad having an exposed surface made of a metallic material that diffuses less readily into a dielectric layer than does a metal of a wiring layer connected thereto.

Bump structure and electronic packaging solder joint structure and fabricating method thereof

A bump structure includes a substrate, a pad, an electrode and a protruding electrode. The pad is disposed on the substrate. The electrode is formed by a first metal material and disposed on the pad. The protruding electrode is formed by a second metal material and disposed on the electrode, wherein a cross-sectional area of the protruding electrode is less than a cross-sectional area of the electrode.

Via plugs

The present disclosure relates to providing via plugs in vias of a semiconductor material. The via plugs may be formed of a polymer, such as a polyimide, that can withstand subsequent soldering and operating temperatures. The via plugs effectively fill the vias to prevent the vias from being filled substantially with solder during a subsequent soldering processes.

Semiconductor device

A semiconductor device includes a protective layer, a redistribution pattern, a pad pattern and an insulating polymer layer. The protective layer may be formed on a substrate. The redistribution pattern may be formed on the protective layer. An upper surface of the redistribution may be substantially flat. The pad pattern may be formed directly on the redistribution pattern. An upper surface of the pad pattern may be substantially flat. The insulating polymer layer may be formed on the redistribution pattern and the pad pattern. An upper surface of the insulating polymer layer may be lower than the upper surface of the pad pattern. The semiconductor device may have a high reliability.

Semiconductor structure and method of forming the same

The present invention relates to a semiconductor structure and method of forming the same. The semiconductor structure includes a first substrate, a first adhesive/bonding stack on the surface of first substrate, wherein the first adhesive/bonding stack includes at least one first adhesive layer and at least one first bonding layer. The material of first bonding layer includes dielectrics such as silicon, nitrogen and carbon, the material of first adhesive layer includes dielectrics such as silicon and nitrogen, and the first adhesive/bonding stack of semiconductor structure is provided with higher bonding force in bonding process.

Heat Spreading Device and Method

In an embodiment, a device includes: an integrated circuit die having a first side and a second side opposite the first side; a die stack on the first side of the integrated circuit die; a dummy semiconductor feature on the first side of the integrated circuit die, the dummy semiconductor feature laterally surrounding the die stack, the dummy semiconductor feature electrically isolated from the die stack and the integrated circuit die; a first adhesive disposed between the die stack and the dummy semiconductor feature; and a plurality of conductive connectors on the second side of the integrated circuit die.

Unified semiconductor devices having processor and heterogeneous memories and methods for forming the same

Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes NAND memory cells and a first bonding layer including first bonding contacts. The semiconductor device also includes a second semiconductor structure including DRAM cells and a second bonding layer including second bonding contacts. The semiconductor device also includes a third semiconductor structure including a processor, SRAM cells, and a third bonding layer including third bonding contacts. The semiconductor device further includes a first bonding interface between the first and third bonding layers, and a second bonding interface between the second and third bonding layers. The first bonding contacts are in contact with a first set of the third bonding contacts at the first bonding interface. The second bonding contacts are in contact with a second set of the third bonding contacts at the second bonding interface. The first and second bonding interfaces are in a same plane.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

An improvement is achieved in the reliability of a semiconductor device. Over a semiconductor substrate, an interlayer insulating film is formed and, over the interlayer insulating film, a pad is formed. Over the interlayer insulating film, an insulating film is formed so as to cover the pad. In the insulating film, an opening is formed to expose a part of the pad. The pad is a pad to which a copper wire is to be electrically coupled and which includes an Al-containing conductive film containing aluminum as a main component. Over the Al-containing conductive film in a region overlapping the opening in plan view, a laminated film including a barrier conductor film, and a metal film over the barrier conductor film is formed. The metal film is in an uppermost layer. The barrier conductor film is a single-layer film or a laminated film including one or more layers of films selected from the group consisting of a Ti film, a TiN film, a Ta film, a TaN film, a W film, a WN film, a TiW film, and a TaW film. The metal film is made of one or more metals selected from the group consisting of Pd, Au, Ru, Rh, Pt, and Ir. 1. A semiconductor device , comprising:a semiconductor substrate;a first insulating film formed over the semiconductor substrate;a pad formed over the first insulating film;a second insulating film formed over the first insulating film so as to cover the pad; andan opening formed in the second insulating film to expose a part of the pad,wherein the pad is a pad to which a copper wire is to be electrically coupled and which includes an Al-containing conductive film containing aluminum as a main component,wherein, over the Al-containing conductive film in a region overlapping the opening in plan view, a first laminated film including a first conductor film, and a second conductor film over the first conductor film is formed,wherein the second conductor film is in an uppermost layer of the first laminated film,wherein the first conductor film is a single-layer film ...

3D Integrated Circuit and Methods of Forming the Same

An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer. 1. A semiconductor device comprising:a first contact extending away from a planar surface of a substrate, the first contact having straight sidewalls;a first dielectric layer surrounding a first portion of the first contact, the first dielectric layer being separated from the planar surface;a second dielectric layer surrounding a second portion of the first contact, wherein the second dielectric layer has a larger porosity than the first dielectric layer and wherein the first dielectric layer is located between the second dielectric layer and the substrate; anda dielectric barrier layer surrounding a third portion of the first contact, the dielectric barrier layer sharing a planar surface with the first contact.2. The semiconductor device of claim 1 , wherein the straight sidewalls are perpendicular to a major surface of the substrate.3. The semiconductor device of claim 1 , wherein the straight sidewalls are tilted with respect to a major surface of the substrate.4. The semiconductor device of claim 1 , wherein the first dielectric layer has a porosity of less than about 5%.5. The semiconductor device of claim 4 , wherein the first dielectric layer comprises un-doped silicate glass (USG).6. The semiconductor device of claim 1 , wherein the second dielectric layer ...

Semiconductor device with recessed pad layer and method for fabricating the same

The present application discloses a semiconductor device with a recessed pad layer and a method for fabricating the semiconductor device. The semiconductor device includes a first die, a second die positioned on the first die, a pad layer positioned in the first die, a filler layer including an upper portion and a recessed portion, and a barrier layer positioned between the second die and the upper portion of the filler layer, between the first die and the upper portion of the filler layer, and between the pad layer and the recessed portion of the filler layer. The upper portion of the filler layer is positioned along the second die and the first die, and the recessed portion of the filler layer is extending from the upper portion and positioned in the pad layer.

SURFACE FINISHES FOR INTERCONNECTION PADS IN MICROELECTRONIC STRUCTURES

A surface finish may be formed in a microelectronic structure, wherein the surface finish may include a multilayer interlayer structure. Thus, needed characteristics, such as compliance and electro-migration resistance, of the interlayer structure may be satisfied by different material layers, rather attempting to achieve these characteristics with a single layer. In one embodiment, the multilayer interlayer structure may comprises a two-layer structure, wherein a first layer is formed proximate a solder interconnect and comprises a material which forms a ductile joint with the solder interconnect, and a second layer comprising a material having strong electro-migration resistance formed between the first layer and an interconnection pad. In a further embodiment, third layer may be formed adjacent the interconnection pad comprising a material which forms a ductile joint with the interconnection pad. 125.-. (canceled)26. A microelectronic structure , comprising:an interconnection pad;a surface finish on the interconnection pad, wherein the surface finish comprises a multilayer interlayer structure including at least one ductile layer and at least one electro-migration resistant layer; anda solder interconnect on the surface finish.27. The microelectronic structure of claim 26 , wherein the at least one ductile layer comprises a nickel material having phosphorus content of between about 2% and 10% by weight.28. The microelectronic structure of claim 26 , wherein the at least one electro-migration resistant layer comprises a nickel material having phosphorus content of between about 11% and 20% by weight.29. The microelectronic structure of claim 26 , wherein the at least one electro-migration resistant layer comprises a high atomic weight metal.30. The microelectronic structure of claim 29 , wherein the high atomic weight metal is selected from the group consisting of nickel claim 29 , cobalt claim 29 , and iron.31. The microelectronic structure of claim 26 , wherein ...

CONDUCTIVE BUMP AND ELECTROLESS Pt PLATING BATH

The present invention provides a bump that can prevent diffusion of a metal used as a base conductive layer of the bump into a surface of an Au layer or an Ag layer. A conductive bump of the present invention is a conductive bump formed on a substrate. The conductive bump comprises, at least in order from the substrate: a base conductive layer; a Pd layer; a Pt layer; and an Au layer or an Ag layer having directly contact with the Pd layer, wherein a diameter of the conductive bump is 20 μm or less.

Semiconductor devices and processing methods

Various embodiments provide a semiconductor device, including a final metal layer having a top side and at least one sidewall; and a passivation layer disposed over at least part of at least one of the top side and the at least one sidewall of the final metal layer; wherein the passivation layer has a substantially uniform thickness.

SEMICONDUCTOR DEVICES, SEMICONDUCTOR PACKAGES, AND METHODS OF MANUFACTURING THE SEMICONDUCTOR DEVICES

A semiconductor device includes a conductive component on a substrate, a passivation layer on the substrate and including an opening that exposes at least a portion of the conductive component, and a pad structure in the opening and located on the passivation layer, the pad structure being electrically connected to the conductive component. The pad structure includes a lower conductive layer conformally extending on an inner sidewall of the opening, the lower conductive layer including a conductive barrier layer, a first seed layer, an etch stop layer, and a second seed layer that are sequentially stacked, a first pad layer on the lower conductive layer and at least partially filling the opening, and a second pad layer on the first pad layer and being in contact with a peripheral portion of the lower conductive layer located on the top surface of the passivation layer. 1. A semiconductor device comprising:a conductive component on a substrate;a passivation layer on the substrate and including an opening therein, wherein the opening exposes at least a portion of the conductive component; and a lower conductive layer conformally extending on an inner sidewall of the opening and on a top surface of the passivation layer around the opening, the lower conductive layer including a conductive barrier layer, a first seed layer, an etch stop layer, and a second seed layer that are sequentially stacked,', 'a first pad layer on the lower conductive layer, the first pad layer at least partially filling the opening, and', 'a second pad layer on the first pad layer, the second pad layer laterally extending beyond the first pad layer to contact a peripheral portion of the lower conductive layer located on the top surface of the passivation layer., 'a pad structure on the passivation layer and in the opening, the pad structure electrically connected to the conductive component, the pad structure comprising2. The semiconductor device of claim 1 , wherein the second pad layer is ...

SEMICONDUCTOR DEVICES

A semiconductor device includes a substrate, a protection layer on the substrate that includes a trench that penetrates therethrough, a lower bump that includes a first part that fills at least a portion of the trench and a second part on the protection layer; and an upper bump on the lower bump. The protection layer includes a first part that surrounds the trench and a second part that surrounds the first part. A first height from an upper surface of the substrate to an upper surface of the first part of the protection layer is greater than a second height from the upper surface of the substrate to an upper surface of the second part of the protection layer. 1. A semiconductor device , comprising:a substrate;a protection layer on the substrate, the protection layer including a trench that penetrates therethrough;a lower bump that includes a first part that fills at least a portion of the trench and a second part on the protection layer, wherein an upper surface of the first art of the lower bump is curved downward toward the substrate; andan upper bump on the lower bump,wherein the protection layer includes a first part that surrounds the trench and a second part that surrounds the first part, anda first height from an upper surface of the substrate to an upper surface of the first part of the protection layer is greater than a second height from the upper surface of the substrate to an upper surface of the second part of the protection layer.2. The semiconductor device according to claim 1 , wherein the lower bump includes a recess claim 1 , andthe upper bump includes a first part in the recess and a second part on the first part.3. The semiconductor device according to claim 1 , wherein an upper surface of the first part of the lower bump includes a second point spaced apart by a first distance from a first point on a sidewall of the trench in a first direction parallel to the upper surface of the substrate and a third point spaced apart by a second distance from ...

BONDED ASSEMBLY CONTAINING OXIDATION BARRIERS AND/OR ADHESION ENHANCERS AND METHODS OF FORMING THE SAME

A method of forming a bonded assembly includes providing a first semiconductor die containing a first substrate, first semiconductor devices, and first bonding pads that are electrically connected to a respective node of the first semiconductor devices, forming a first oxidation barrier layer on physically exposed surfaces of the first bonding pads, providing a second semiconductor die containing a second substrate, second semiconductor devices, and second bonding pads that are electrically connected to a respective node of the second semiconductor devices, and bonding the second bonding pads to the first bonding pads with at least the first oxidation barrier layer located between the respective first and second bonding pads. 1. A method of forming a bonded assembly , comprising:providing a first semiconductor die comprising a first substrate, first semiconductor devices, and first bonding pads that are electrically connected to a respective node of the first semiconductor devices;forming a first oxidation barrier layer on physically exposed surfaces of the first bonding pads;providing a second semiconductor die comprising a second substrate, second semiconductor devices, and second bonding pads that are electrically connected to a respective node of the second semiconductor devices; andbonding the second bonding pads to the first bonding pads with at least the first oxidation barrier layer located between the respective first and second bonding pads.2. The method of claim 1 , wherein:the first bonding pads are located within a first bonding dielectric layer;the second bonding pads are located within a second bonding dielectric layer; andthe oxidation barrier layer is selectively formed on physically exposed surfaces of the first bonding pads without forming the first oxidation barrier layer on physically exposed surfaces of the first bonding dielectric layer.3. The method of claim 2 , wherein:the first bonding dielectric layer and the second bonding dielectric ...

Integrated circuit chip and display device including the same

An exemplary embodiment provides a driving circuit chip including: a substrate; a terminal electrode disposed on the substrate; and an electrode pad disposed on the terminal electrode, wherein the electrode pad includes: a bump structure protruded from the substrate to include a short side and a long side; and a bump electrode disposed on the bump structure and connected with the terminal electrode around a short edge portion of the bump structure, wherein the bump electrode is disposed to not cover at least a part of a long edge portion of the bump structure.

3D Integrated Circuit and Methods of Forming the Same

An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer. 1. A method of manufacturing a semiconductor device , the method comprising:pre-bonding a first dielectric barrier layer and a second dielectric barrier layer at room temperature for a time of less than about one minute, wherein the first dielectric barrier layer is adjacent to a first high porosity dielectric layer and the second dielectric barrier layer is adjacent to a second high porosity dielectric layer, wherein the first high porosity dielectric layer is adjacent to a first low porosity dielectric layer and the second high porosity dielectric layer is adjacent to a second low porosity dielectric layer, and wherein a first contact extends through the first low porosity dielectric layer, the first high porosity dielectric layer, and the first dielectric barrier layer to make contact with a second contact, the second contact extending through the second dielectric barrier layer, the second high porosity dielectric layer, and the second low porosity dielectric layer; andannealing the first dielectric barrier layer and the second dielectric barrier layer at a temperature of between about 300° C. and about 400° C.2. The method of claim 1 , further comprising curing the first dielectric barrier layer and the second dielectric barrier layer.3. The method of claim 1 ...

Integrated circuit device structures and double-sided fabrication techniques

Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

A semiconductor package includes a chip, a redistribution structure, and first under-ball metallurgies patterns. The chip includes conductive posts exposed at an active surface. The redistribution structure is disposed on the active surface. The redistribution structure includes a first dielectric layer, a topmost metallization layer, and a second dielectric layer. The first dielectric layer includes first openings exposing the conductive posts of the chip. The topmost metallization layer is disposed over the first dielectric layer and is electrically connected to the conductive posts. The topmost metallization layer comprises first contact pads and routing traces connected to the first contact pads. The second dielectric layer is disposed on the topmost metallization layer and includes second openings exposing the first contact pads. The first under-ball metallurgies patterns are disposed on the first contact pads, extending on and contacting sidewalls and top surfaces of the first contact pads. 1. A semiconductor package , comprising:a chip comprising conductive posts exposed at an active surface of the chip; a first dielectric layer, including first openings exposing the conductive posts of the chip;', 'a topmost metallization layer, disposed over the first dielectric layer and electrically connected to the conductive posts, wherein the topmost metallization layer comprises first contact pads and routing traces connected to the first contact pads; and', 'a second dielectric layer, disposed on the topmost metallization layer and including second openings exposing the first contact pads; and, 'a redistribution layer disposed on the active surface of the chip, comprisingfirst under-ball metallurgies patterns disposed on the first contact pads, wherein the first under-ball metallurgy patterns extend on and contact sidewalls and top surfaces of the first contact pads.2. The semiconductor package of claim 1 , wherein the topmost metallization layer further comprises ...

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, CIRCUIT SUBSTRATE, AND ELECTRONIC APPARATUS

A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the second face; an external connection terminal that is disposed at the first face side; a conductive portion that is disposed in the through hole, the conductive portion being electrically connected to the external connection terminal; and an electronic element that is disposed at a second face side. 1. A device comprising:a semiconductor substrate including a first face and a second face on a side opposite to the first face;an external connection terminal formed on the first face of the semiconductor substrate;a first electrode formed on the first face of the semiconductor substrate and electrically connected to the external connection terminal;a second electrode formed on the first face of the semiconductor substrate;an integrated circuit formed on the first face, the integrated circuit being electrically connected to the first electrode and the second electrode;a rear face electrode formed on the second face of the semiconductor substrate;a groove portion formed in the semiconductor substrate, the groove portion having an inner wall;an insulating film formed on side walls of the groove portion; anda conductive portion formed inside the groove portion on the insulating portion and electrically connected to the second electrode and the rear face electrode;wherein the integrated circuit and the first electrode are electrically disposed between the second electrode and the external connection terminal.2. The device of claim 1 , wherein the semiconductor substrate is silicon.3. The device of claim 2 , wherein:the second electrode comprises a second electrode rear face facing the first face of the semiconductor substrate;the rear face electrode comprises a rear face ...

Interconnect Structure and Method of Forming Same

A device includes a first side interconnect structure over a first side of a substrate, wherein active circuits are in the substrate and adjacent to the first side of the substrate, a dielectric layer over a second side of the substrate, a pad embedded in the dielectric layer, the pad comprising an upper portion and a bottom portion formed of two different materials and a passivation layer over the dielectric layer. 1. A device comprising:a dielectric layer on a first side of a semiconductor substrate;a first redistribution line in a first recess in the dielectric layer, the first redistribution line comprising a first layer, the first layer completely filling the first recess;a contact pad in a second recess in the dielectric layer, wherein a width of the contact pad is greater than a width of a first redistribution line, wherein the contact pad comprises a second layer and a third layer over the second layer, wherein the second layer and the first layer are a same material, wherein the second layer and the third layer completely fills the second recess, the second layer and the third layer comprising different materials; anda passivation layer over the dielectric layer.2. The device of further comprising a transistor on a second side of the semiconductor substrate.3. The device of further comprising:a front-side interconnect structure on the second side of the semiconductor substrate; anda through via extending from a conductive feature in the front-side interconnect structure through the semiconductor substrate to the first side of the semiconductor substrate, wherein the contact pad is electrically coupled to the through via.4. The device of claim 3 , wherein the contact pad directly contacts the through via.5. The device of claim 1 , wherein the dielectric layer is interposed between the contact pad and the first side of the semiconductor substrate.6. The device of further comprising a passivation layer over the dielectric layer.7. The device of claim 6 , ...

Light-emittng device

A light-emitting device includes a first light-emitting element, a second light-emitting element having a peak emission wavelength different from that of the first light-emitting element, a light-guide member covering a light extracting surface and lateral surfaces of the first light-emitting element and a light extracting surface and lateral surfaces of the second light-emitting element, and a wavelength conversion layer continuously covering the light extracting surface of each of the first and second light-emitting elements and disposed apart from each of the first and second light-emitting elements, and a first reflective member covering outer lateral surfaces of the light-guide member. An angle defined by an active layer of the first light-emitting element and an active layer of the second light-emitting element is less than 180° at a wavelength conversion layer side.

Structures and methods for low temperature bonding

A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

SEMICONDUCTOR DEVICE STRUCTURE WITH CONDUCTIVE POLYMER LINER AND METHOD FOR FORMING THE SAME

The present disclosure relates to a semiconductor device structure with a conductive polymer liner and a method for preparing the semiconductor device structure. The semiconductor device structure includes a first metal layer disposed over a semiconductor substrate, and a second metal layer disposed over the first metal layer. The semiconductor device structure also includes a conductive structure disposed between the first metal layer and the second metal layer. The conductive structure includes a first conductive via and a first conductive polymer liner surrounding the first conductive via.

Barrier materials between bumps and pads

Disclosed are barrier materials between bumps and pads, and related devices and methods. A semiconductor device includes an interconnect, a top material, a pad on the interconnect and at least a portion of the top material, a bump on the pad, and a barrier material between the pad and the bump. The top material defines a via therethrough to the interconnect. The pad includes electrically conductive material. The bump includes electrically conductive material. The bump is configured to electrically connect the interconnect to another device. The barrier material is between the pad and the bump. The barrier material includes a conductive material that is resistant to electromigration, intermetallic compound reaction, or both electromigration and intermetallic compound reaction.

Semiconductor device having through silicon vias

The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a conductive feature, a redistribution layer, at least one through silicon via and at least one bump. The conductive feature is disposed over a front surface of the substrate, and the redistribution layer is disposed over a back surface opposite to the front surface. The through silicon via penetrates through the substrate and contacts the conductive feature embedded in an insulative layer. The bump contacts the redistribution layer and the through silicon via and serves as an electrical connection therebetween.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device includes a first carrier including a first pad, a second carrier including a second pad disposed opposite to the first pad, a joint coupled with and standing on the first pad, a joint encapsulating the post and bonding the first pad with the second pad, a first entire contact interface between the first pad and the joint, a second entire contact interface between the first pad and the post, and a third entire contact interface between the joint and the second pad. The first entire contact interface, the second entire contact interface and the third entire contact interface are flat surfaces. A distance between the first entire contact interface and the third entire contact interface is equal to a distance between the second entire contact interface and the third entire contact interface. The second entire contact interface is a continuous surface. 1. A semiconductor device , comprising:a silicon substrate;a carrier;a first pad on the silicon substrate;a second pad on the carrier;a post on a surface of the first pad, wherein the post consists of a metal or a metal alloy;a joint disposed between the silicon substrate and the carrier, contacted with the first pad and the second pad, and encapsulating the post;a first entire contact interface between the first pad and the joint;a second entire contact interface between the first pad and the post; anda third entire contact interface between the joint and the second pad,wherein an outer surface of the joint is concaved and curved towards the post, and a height of the post is greater than or equal to ⅓ of a height of the joint between the first pad and the second pad, the first entire contact interface, the second entire contact interface and the third entire contact interface are flat surfaces, wherein a distance between the first entire contact interface and the third entire contact interface is equal to a distance between the second entire contact interface and the third entire contact interface, ...

Semiconductor device

A semiconductor device suitable for preventing malfunction is provided. The semiconductor device includes a semiconductor chip 1 , a first electrode pad 21 laminated on the semiconductor chip 1 , an intermediate layer 4 having a rectangular shape defined by first edges 49 a and second edges, and a plurality of bumps 5 arranged to sandwich the intermediate layer 4 by cooperating with the semiconductor chip 1 . The first edges 49 a extend in the direction x, whereas the second edges extend in the direction y. The plurality of bumps 5 include a first bump 51 electrically connected to the first electrode pad 21 and a second bump 52 electrically connected to the first electrode pad 21 . The first bump 51 is arranged at one end in the direction x and one end in the direction y.

SEMICONDUCTOR PACKAGING AND MANUFACTURING METHOD THEREOF

The present disclosure provides a semiconductor package, which includes a substrate, a passivation layer, a post-passivation interconnect (PPI) having a top surface; and a conductive structure. The top surface of the PPI includes a first region receiving the conductive structure, and a second region surrounding the first region. The second region includes metal derivative transformed from materials made of the first region. The present disclosure provide a method of manufacturing a semiconductor package, including forming a first flux layer covering a portion of a top surface of a PPI; transforming a portion of the top surface of the PPI uncovered by the first flux layer into a metal derivative layer; removing the first flux layer; forming a second flux layer on the first region of the PPI; dropping a solder ball on the flux layer; and forming electrical connection between the solder ball and the PPI. 1. A method of manufacturing a semiconductor package , comprising:patterning a metal derivative in a second region of a post-passivation interconnect (PPI);forming a flux layer in a first region of the PPI, wherein the first region is surrounded by the second region;dropping a solder ball on the flux layer; andforming electrical connection between the solder ball and the PPI.2. The method of manufacturing a semiconductor package in claim 1 , wherein the to patterning the metal derivative in the second region of the PPI further comprising forming a mask layer over the PPI.3. The method of manufacturing a semiconductor package in claim 2 , wherein the forming the mask layer over the PPI comprises forming a mask layer on the PPI.4. The method of manufacturing a semiconductor package in claim 2 , wherein the forming the mask layer over the PPI comprises positioning a first stencil plate over the PPI.5. The method of manufacturing a semiconductor package in claim 1 , wherein the patterning the metal derivative in the second region of the PPI comprises an oxygen plasma ...

Semiconductor package

A semiconductor package including a package substrate, a semiconductor chip on a top surface of the package substrate, a connection terminal between the package substrate and the semiconductor chip, the connection terminal connecting the package substrate to the semiconductor chip, a non-conductive film (NCF) between the package substrate and semiconductor chip, the NCF surrounding the connection terminal and bonding the semiconductor chip to the package substrate, and a side encapsulation material covering a side surface of the semiconductor chip, contacting the package substrate, and including a first portion between a bottom surface of the semiconductor chip and the top surface of the package substrate may be provided. At least a portion of the NCF includes a second portion that horizontally protrudes from the semiconductor chip when viewed, and a portion of the side encapsulation material is in contact with the bottom surface of the semiconductor chip.

Semiconductor device with slanted conductive layers and method for fabricating the same

The present application discloses a semiconductor device with slanted conductive layers and a method for fabricating the semiconductor device with the slanted conductive layers. The semiconductor device includes a substrate, a first insulating layer positioned above the substrate, first slanted conductive layers positioned in the first insulating layer, and a top conductive layer positioned covering the first slanted conductive layers.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

A method of manufacturing a semiconductor device includes providing a semiconductor substrate, forming, over a main surface the semiconductor substrate, a first insulating film, forming, over the first insulating film, an Al-containing conductive film containing aluminum as a main component, patterning the Al-containing conductive film to form a pad, forming, over the first insulating film, a second insulating film to cover the pad therewith, forming an opening in the second insulating film, and electrically coupling a copper wire to the pad exposed from the opening. 1. A method of manufacturing a semiconductor device , the method comprising:(a) providing a semiconductor substrate;(b) forming, over a main surface the semiconductor substrate, a first insulating film;(c) forming, over the first insulating film, an Al-containing conductive film containing aluminum as a main component;(d) patterning the Al-containing conductive film to form a pad;(e) forming, over the first insulating film, a second insulating film to cover the pad therewith;(f) forming an opening in the second insulating film;(g) electrically coupling a copper wire to the pad exposed from the opening;(h) after the (c) and before the (g), forming a first conductor film over the Al-containing conductive film; and(i) after the (h) and before the (g), forming a second conductor film over the first conductor film,wherein the first conductor film includes a single-layer film or a laminated film including one or more layers of films selected from a group consisting of a titanium film, a titanium nitride film, a tantalum film, a tantalum nitride film, a tungsten film, a tungsten nitride film, a titanium-tungsten film, and a tantalum-tungsten film,wherein the second conductor film comprises one or more metals selected from a group consisting of palladium, gold, ruthenium, rhodium, platinum, and iridium, andwherein, in the (g), the copper wire is bonded to the second conductor film.2. The method of manufacturing ...

Method of forming a chip assembly and chip assembly

A method of forming a chip assembly may include forming a plurality of cavities in a carrier; The method may further include arranging a die attach liquid in each of the cavities; arranging a plurality of chips on the die attach liquid, each chip comprising a rear side metallization and a rear side interconnect material disposed over the rear side metallization, wherein the rear side interconnect material faces the carrier; evaporating the die attach liquid; and after the evaporating the die attach liquid, fixing the plurality of chips to the carrier.

Semiconductor device, manufacturing method for semiconductor device, electronic component, circuit substrate, and electronic apparatus

A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the second face; an external connection terminal that is disposed at the first face side; a conductive portion that is disposed in the through hole, the conductive portion being electrically connected to the external connection terminal; and an electronic element that is disposed at a second face side.

SEMICONDUCTOR DEVICE

A semiconductor device includes a first substrate and a second substrate that is stacked on a first surface of the first substrate in a stacking direction and includes a second surface facing the first surface. A plurality of first terminals is provided on the first surface of the first substrate. A plurality of second terminals is provided on the second surface of the second substrate. A plurality of metallic portions is respectively provided between the plurality of first terminals and the plurality of second terminals. In a cross-section substantially perpendicular to the stacking direction, at least one of (i) each of the plurality of first terminals or (ii) each of the plurality of second terminals (a) includes a recessed portion in a first direction toward an adjacent first terminal or second terminal or (b) includes a projecting portion in a second direction intersecting with the first direction. 1. A semiconductor device comprising:a first substrate having a first surface;a second substrate stacked on the first surface of the first substrate in a stacking direction, the second substrate having a second surface facing the first surface;a plurality of first terminals provided on the first surface of the first substrate;a plurality of second terminals provided on the second surface of the second substrate; anda plurality of metallic portions respectively provided between the plurality of first terminals and the plurality of second terminals,wherein, in a cross-section substantially perpendicular to the stacking direction, at least one of (i) each of the plurality of first terminals or (ii) each of the plurality of second terminals (a) includes a recessed portion in a first direction toward an adjacent first terminal or second terminal or (b) includes a projecting portion in a second direction intersecting with the first direction.2. The semiconductor device according to claim 1 , wherein each of the metallic portions is made from a material having a lower ...

Package with ubm and methods of forming

Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes an integrated circuit die, an encapsulant at least laterally encapsulating the integrated circuit die, a redistribution structure on the integrated circuit die and the encapsulant, a connector support metallization coupled to the redistribution structure, a dummy pattern, a second dielectric layer, and an external connector on the connector support metallization. The redistribution structure comprises a first dielectric layer having a first surface disposed distally from the encapsulant and the integrated circuit die. The dummy pattern is on the first surface of the first dielectric layer and around the connector support metallization. The second dielectric layer is on the first surface of the first dielectric layer and on at least a portion of the dummy pattern. The second dielectric layer does not contact the connector support metallization.

SEMICONDUCTOR DEVICE

A semiconductor device includes a substrate, a plurality of pads disposed over the substrate, and a solder mask disposed over the substrate. The substrate includes a pair of first edges parallel to each other, a pair of second edges orthogonal to the pair of first edges, and a center point. The solder mask includes four recess portions exposing an entire top surface and sidewalls of four of the pads in four corners of the regular array, and a plurality of second recess portions exposing a portion of a top surface of other pads in the regular array. A pad size of the four pads in the four corners of the regular array exposed through the first recess portions and a pad size of the other pads exposed through the second recess portions are the same. 2. The semiconductor device of claim 1 , wherein the plurality of pads comprise four non-solder mask defined (NSMD) pads in the four corners of the regular array and a plurality of solder mask defined (SMD) pads disposed away from the four corners of the regular array.3. The semiconductor of claim 2 , wherein each of the four NSMD pads is adjacent to one of the SMD pads in a same horizontal row and another one of the SMD pads in a same vertical column.4. The semiconductor device of claim 1 , wherein the first vertical distances are similar to the second vertical distances.5. The semiconductor device of claim 1 , wherein the first vertical distances are different from the second vertical distances.6. The semiconductor device of claim 1 , wherein a first distance is defined as a distance between the center point and each of the four first recess portions claim 1 , and the first distance is greater than at least one of the first vertical distance and the second vertical distance.7. The semiconductor device of claim 6 , wherein a second distance is defined as a distance between the center point and each of the second recess portions claim 6 , and the second distance is less than the first vertical distance and the second ...

Semiconductor structure and manufacturing method thereof

A semiconductor structure includes a substrate; a pad disposed over the substrate; a first passivation disposed over the substrate, partially covering the pad, and including a protrusion protruded from the first passivation and away from the substrate; a conductive layer disposed over the first passivation and a portion of the pad exposed from the first passivation; and a second passivation disposed over the conductive layer, wherein the conductive layer disposed over the protrusion is exposed from the second passivation.

SEMICONDUCTOR DEVICE

A semiconductor device includes a substrate including a surface, a plurality of pads disposing on the surface of the substrate, the plurality of pads includes a non-solder mask defined (NSMD) pad and a solder mask defined (SMD) pad, and the NSMD pad is arranged at a predetermined location. Further, a method of manufacturing a semiconductor device includes providing a substrate, disposing a plurality of pads on a surface of the substrate, disposing a solder mask over the surface of the substrate and the plurality of pads, forming a first recess in the solder mask to surround one of the plurality of pads, and forming a second recess in the solder mask and above one of the plurality of pads. 2. The semiconductor device of claim 1 , wherein the plurality of pads are arranged in a regular array including a plurality of horizontal rows and a plurality of vertical columns.3. The semiconductor device of claim 1 , wherein the plurality of pads comprise a plurality of non-solder mask defined (NSMD) pads and a plurality of solder mask defined (SMD) pads.4. The semiconductor of claim 3 , wherein the first recess portion entirely exposes one of the NSMD pads claim 3 , and the second recess portion partially exposes one of the SMD pads.5. The semiconductor device of claim 1 , wherein first recess portion is disposed on a corner of the semiconductor device and the second recess portion is disposed away from the corner of the semiconductor device.6. The semiconductor device of claim 1 , wherein the first distance between the central point and the first edge is greater than a fourth distance between the central point and the second recess portion claim 1 , and the second distance between the central point and the second edge is greater than the fourth distance between the central point and the second recess portion.7. A semiconductor device claim 1 , comprising:a substrate comprising a pair of first edges parallel to each other, a pair of second edges orthogonal to the first edge, ...

CHIP AND MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE

Embodiments of this application provide a chip and a manufacturing method thereof, and an electronic device, and belong to the field of chip heat dissipation technologies. The chip includes a die and a thermal conductive sheet. An active surface of the die is connected to the thermal conductive sheet by using a first bonding layer. Heat generated at a part with a relatively high temperature on the active surface of the die can be quickly conducted and dispersed by using the thermal conductive sheet, so that temperatures on the active surface are evenly distributed to avoid an excessively high local temperature of the chip, thereby preventing running of the chip from being affected. 1. A chip , comprising:a die; anda thermal conductive sheet, wherein an active surface of the die is connected to the thermal conductive sheet by using a first bonding layer.2. The chip according to claim 1 , further comprising:a plurality of conductive pillars run through the thermal conductive sheet,wherein the first bonding layer comprises an insulated connection layer and a plurality of electrical interconnection structures, wherein the electrical interconnection structures are located in the insulated connection layer; anda plurality of pads of the active surface arc connected to the conductive pillars through bonding by using the electrical interconnection structures, and wherein a region of the active surface other than the pads is connected to the thermal conductive sheet through bonding by using the insulated connection layer.3. The chip according to claim 1 , further comprising:a plurality of conductive pillars run through the thermal conductive sheet; andwherein the first bonding layer comprises an insulated connection layer, wherein the conductive pillars are deposited on pads of the active surface, and wherein a region of the active surface other than the pads is connected to the thermal conductive sheet through bonding by using the insulated connection layer.4. The chip ...

Nonvolatile memory device, system including the same and method of fabricating the same

A nonvolatile memory device including a substrate extending in a first direction, a ground selection line extending in the first direction on the substrate, a plurality of word lines stacked sequentially on the ground selection line and extending in the first direction, a landing pad spaced apart from the ground selection line and the plurality of word lines in the first direction, a rear contact plug connected to a lower face of the landing pad and extending in a second direction intersecting the first direction, a front contact plug connected to an upper face of the landing pad opposite the lower face and extending in the second direction, an input/output pad electrically connected to the rear contact plug, and an upper bonding pad electrically connected to the front contact plug and connected to at least a part of a plurality of circuit elements of the nonvolatile memory device.

METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE

The present disclosure provides a method for manufacturing a semiconductor structure employing a via structure. The method includes forming a first conductive pad on a first semiconductor device; forming a second conductive pad on the first conductive pad; connecting a second semiconductor device to the first semiconductor device; and forming a via structure in the second semiconductor device, The via structure contacts the second conductive pad, and the first conductive pad and the second conductive pad are formed of different metal materials. 1. A method of manufacturing a semiconductor structure , comprising:forming a first conductive pad on a first semiconductor device;forming a second conductive pad on the first conductive pad;connecting a second semiconductor device to the first semiconductor device; andforming a via structure in the second semiconductor device, wherein the via structure contacts the second conductive pad;wherein the first conductive pad and the second conductive pad are formed of different metal materials.2. The method of claim 1 , wherein the forming of the second conductive pad on the first conductive pad comprises: forming a dielectric layer on the first conductive pad; and forming an opening in the dielectric layer to expose the first conductive pad.3. The method of claim 2 , wherein the forming of the second conductive pad on the first conductive pad comprises: forming the second conductive pad in the opening.4. The method of claim 1 , further comprising: forming the first conductive pad and the second conductive pad with chemical reactivity that increase at positions along a direction from the via structure to the first semiconductor device.5. The method of claim 1 , further comprising: forming the second conductive pad with a thickness less than a thickness of the first conductive pad.6. The method of claim 1 , further comprising: forming a step structure of the first conductive pad and the second conductive pad claim 1 , wherein a ...

Method of forming a temporary test structure for device fabrication

A method of forming a temporary test structure for device fabrication is provided. The method allows for electrically testing conductive interconnects during controlled collapse chip connections (C4) fabrication and/or through-silicon vias (TSVs) during interposer fabrication. The method includes providing a substrate containing a plurality of electrically conductive interconnects extending vertically to top surface of the substrate. A temporary test structure is formed to connect the plurality of interconnects for electrical testing. Electrical testing is performed on the substrate by probing at different test locations on the temporary test structure. All or part of the temporary test structure is removed so as not to affect product performance. The temporary test structure can contain electrical test pads which provide a way to make temporary connections to small interconnect landings or features at extreme tight pitch to fan them out to testable pads sizes and pitches.

LIGHT EMITTING APPARATUS AND METHOD FOR PRODUCING THE SAME

A light emitting apparatus includes: a mount substrate; at least one light emitting device mounted on the mount substrate; a light transparent member, wherein a lower surface of the light transparent member is attached to an upper surface of the at least one light emitting device via at least one adhesive material layer, wherein the light transparent member has a plate shape and is positioned to receive incident light emitted from the light emitting devices, and wherein a lateral surface of the light transparent member is located laterally inward of a lateral surface of the at least one light emitting device; and a covering member that contains a light reflective material and covers at least the lateral surface of the light transparent member.

Method and apparatus for die-to-die pad contact

A semiconductor device includes at least a first semiconductor die and a second semiconductor die. The first semiconductor dies comprises a first and second side, and includes at least a first contact pad located on the first side of the first semiconductor die. The second semiconductor die comprises a first and second side, and includes at least a second contact pad located on the first side of the second semiconductor die, wherein the first semiconductor die is stacked on the second semiconductor die and wherein the first side of the first semiconductor die faces the first side of the second semiconductor die. At least one voltage-guided conductive filament is created between the first contact pad and the second contact pad.

Semiconductor device structure with bottle-shaped through silicon via and method for forming the same

A semiconductor device structure includes a silicon layer disposed over a first semiconductor die, and a first mask layer disposed over the silicon layer. The semiconductor device structure also includes a second semiconductor die disposed over the first mask layer, and a through silicon via penetrating through the silicon layer and the first mask layer. A bottom surface of the through silicon via is greater than a top surface of the through silicon via, and the top surface of the through silicon via is greater than a cross-section of the through silicon via between and parallel to the top surface and the bottom surface of the through silicon via.

Semiconductor apparatus

A semiconductor apparatus according to an embodiment of the present invention includes: a plurality of semiconductor chips that are laminated; a plurality of penetration electrodes that penetrate in a lamination direction through the plurality of semiconductor chips and that electrically connect together the plurality of semiconductor chips; and a plurality of input/output elements that are configured to perform a signal input/output operation to the plurality of penetration electrodes, wherein the semiconductor chips are joined together via no bump, one of the plurality of input/output elements is connected to each of the plurality of penetration electrodes such that a functional element connected to each of the plurality of penetration electrodes performs an ON or OFF operation at a predetermined timing, and the input/output element connected to a first of two adjacent penetration electrodes among the plurality of penetration electrodes and the input/output element connected to a second of two adjacent penetration electrodes are configured to perform the signal input/output operation at a different timing from each other.

SEMICONDUCTOR DEVICES INCLUDING A THICK METAL LAYER

A semiconductor device includes a plurality of middle interconnections and a plurality of middle plugs, which are disposed in an interlayer insulating layer and on a substrate. An upper insulating layer is disposed on the interlayer insulating layer. A first upper plug, a first upper interconnection, a second upper plug, and a second upper interconnection are disposed in the upper insulating layer. Each of the plurality of middle interconnections has a first thickness. The first upper interconnection has a second thickness that is greater than the first thickness. The second upper interconnection has a third thickness that is greater than the first thickness. The third thickness is twice to 100 times the first thickness. The second upper interconnection includes a material different from the second upper plug. 1. A semiconductor device comprising:an interlayer insulating layer disposed on a substrate;a plurality of middle interconnections disposed in the interlayer insulating layer;a plurality of middle plugs disposed in the interlayer insulating layer and between the plurality of middle interconnections;an upper insulating layer disposed on the interlayer insulating layer;a first upper plug disposed in the upper insulating layer and connected to one middle interconnection of the plurality of middle interconnections, the one middle interconnection having a first thickness;a first upper interconnection disposed in the upper insulating layer on the first upper plug and having a second thickness, wherein the second thickness is greater than the first thickness;a second upper plug disposed in the upper insulating layer on the first upper interconnection;a second upper interconnection disposed in the upper insulating layer on the second upper plug and having a third thickness, wherein the third thickness is greater than the first thickness; andan opening configured to pass through the upper insulating layer to expose the second upper interconnection,wherein the third ...

Wafer Level Package (WLP) and Method for Forming the Same

A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a conductive pad formed on the substrate. The semiconductor device structure includes a protection layer formed over the conductive pad and a post-passivation interconnect (PPI) structure formed at least in the protection layer. The PPI structure is electrically connected to the conductive pad. The semiconductor device structure also includes a first moisture-resistant layer formed over the protection layer, and the protection layer and the first moisture-resistant layer are made of different materials. The semiconductor device structure further includes an under bump metallurgy (UBM) layer formed over the first moisture-resistant layer and connected to the PPI structure. 1. A semiconductor device comprising:a first conductive pad over a chip structure;a passivation layer over the first conductive pad;a first protection layer over the passivation layer;a post-passivation interconnect (PPI) pad extending through the first protection layer and the passivation layer, the PPI pad being coupled to the first conductive pad;an insulating layer surrounding sidewalls of the chip structure and the first protection layer;a second protection layer over the first protection layer and the insulating layer;a PPI structure extending through the second protection layer, the PPI structure being coupled to the PPI pad;a first moisture-resistant layer over the second protection layer and the PPI structure;a ball-like bump over the first moisture-resistant layer; anda second conductive pad over the ball-like bump.2. The semiconductor device of claim 1 , wherein at least a portion of the passivation layer is disposed between the PPI structure and the first conductive pad in a direction perpendicular to a major surface of the chip structure.3. The semiconductor device of claim 1 , further comprising an under bump metallurgy (UBM) extending through the ...

Package With UBM and Methods of Forming

Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes an integrated circuit die, an encapsulant at least laterally encapsulating the integrated circuit die, a redistribution structure on the integrated circuit die and the encapsulant, a connector support metallization coupled to the redistribution structure, a dummy pattern, a second dielectric layer, and an external connector on the connector support metallization. The redistribution structure comprises a first dielectric layer having a first surface disposed distally from the encapsulant and the integrated circuit die. The dummy pattern is on the first surface of the first dielectric layer and around the connector support metallization. The second dielectric layer is on the first surface of the first dielectric layer and on at least a portion of the dummy pattern. The second dielectric layer does not contact the connector support metallization. 1. A method comprising:encapsulating an integrated circuit die with an encapsulant;forming a redistribution structure on the integrated circuit die and the encapsulant, the redistribution structure comprising a first dielectric layer having a first surface distal from the integrated circuit die and the encapsulant;forming an under ball metallization (UBM) and a dummy pattern on the redistribution structure, the dummy pattern surrounding the UBM on the first surface of the first dielectric layer, the dummy pattern being electrically isolated; andforming a second dielectric layer on the first surface of the first dielectric layer and at least a portion of the dummy pattern, wherein after the forming the second dielectric layer, the second dielectric layer is physically spaced apart from the UBM, wherein the second dielectric layer covers an exterior portion of the dummy pattern laterally distal from the UBM and exposes an interior portion of the dummy pattern proximate the UBM.2. The ...

BUMP BONDED CRYOGENIC CHIP CARRIER

A technique relates to a device. First thin films are characterized by having a first opposing surface and a first connection surface in which the first connection surface is in physical contact with a first superconducting region. Second thin films are characterized by having a second opposing surface and a second connection surface in which the first and second opposing surfaces are opposite one another. The second connection surface is in physical contact with a second superconducting region. A solder material electrically connects the first and second opposing surfaces, and the solder material is characterized by maintaining a low ohmic electrical contact between the first and second opposing surfaces at temperatures below 100 degrees Kelvin. The first and second superconducting regions are formed of materials that have a melting point of at least 700 degrees Celsius. 1. A device comprising:a first plurality of thin films, the first plurality of thin films characterized by having a first opposing surface and a first connection surface, wherein the first connection surface is in physical contact with a first superconducting region;a second plurality of thin films, the second plurality of thin films characterized by having a second opposing surface and a second connection surface, the first and second opposing surfaces being opposite one another, wherein the second connection surface is in physical contact with a second superconducting region; anda solder material electrically connecting the first and second opposing surfaces, the solder material characterized by maintaining a low ohmic electrical contact between the first and second opposing surfaces at temperatures below 100 degrees Kelvin, wherein the first and second superconducting regions are comprised of materials that have a melting point of at least 700 degrees Celsius.2. The device of claim 1 , wherein the first and second plurality of thin films are electrically conductive.3. The device of claim 1 , ...

BONDING ALIGNMENT MARKS AT BONDING INTERFACE

Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a bonded structure includes a first bonding layer including a first bonding contact and a first bonding alignment mark, a second bonding layer including a second bonding contact and a second bonding alignment mark, and a bonding interface between the first bonding layer and the second bonding layer. The first bonding alignment mark is aligned with the second bonding alignment mark at the bonding interface, such that the first bonding contact is aligned with the second bonding contact at the bonding interface. The first bonding alignment mark includes a plurality of first repetitive patterns. The second bonding alignment mark includes a plurality of second repetitive patterns different from the plurality of first repetitive patterns. 1. A bonded structure , comprising:a first bonding layer comprising a first bonding contact and a first bonding alignment mark;a second bonding layer comprising a second bonding contact and a second bonding alignment mark; anda bonding interface between the first bonding layer and the second bonding layer,wherein the first bonding alignment mark is aligned with the second bonding alignment mark at the bonding interface, such that the first bonding contact is aligned with the second bonding contact at the bonding interface;the first bonding alignment mark comprises a plurality of first repetitive patterns; andthe second bonding alignment mark comprises a plurality of second repetitive patterns different from the plurality of first repetitive patterns.2. The bonded structure of claim 1 , wherein the plurality of first repetitive patterns are repetitive strips and the plurality of second repetitive patterns are repetitive squares.3. The semiconductor device of claim 2 , wherein the repetitive strips of the plurality of first repetitive patterns and the repetitive squares of the plurality of second repetitive patterns are at least ...

Final passivation for wafer level warpage and ulk stress reduction

Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having an annular PSPI region formed under a BLM pad. An annular region is formed under a barrier layer metallurgy (BLM) pad. The annular region includes a photosensitive polyimide (PSPI). A conductive pedestal is formed on a surface of the BLM pad and a solder bump is formed on a surface of the conductive pedestal. The annular PSPI region reduces wafer warpage and ULK peeling stress.

Semiconductor device with contact pad and method of making

A semiconductor structure includes a conductive structure over a first passivation layer; and a second passivation layer over the conductive structure and the first passivation layer. The second passivation layer has a first oxide film extending along a top surface of the first passivation layer, sidewalls and a top surface of the conductive structure, wherein a top surface of the first oxide film is planar. The second passivation layer further includes a second oxide film over a top surface of the first oxide film and a top surface of the conductive structure, wherein a top surface of the second oxide film is planar. The second passivation layer further includes a third oxide film extending along a top surface of the second oxide film, the sidewalls and the top surface of the conductive structure, wherein a top surface of the third oxide film is curved.

Zinc Layer For A Semiconductor Die Pillar

A method for fabricating a copper pillar. The method includes forming a layer of titanium tungsten (TiW) over a semiconductor wafer, forming a layer of zinc (Zn) over the layer of TiW, and forming a copper pillar over the via. In addition, the method includes performing an anneal to diffuse the layer of Zn into the copper pillar. A semiconductor device that includes a layer of TiW coupled to a via of a semiconductor wafer and a copper pillar coupled to the layer of TiW. The copper pillar has interdiffused Zn within its bottom portion. Another method for fabricating a copper pillar includes forming a layer of TiW over a semiconductor wafer, forming a first patterned photoresist, forming a layer of Zn, and then removing the first patterned photoresist. The method further includes forming a second patterned photoresist and forming a copper pillar.

Semiconductor Device and Method for Fabricating the Same

Exemplary embodiments for redistribution layers of integrated circuit components are disclosed. The redistribution layers of integrated circuit components of the present disclosure include one or more arrays of conductive contacts that are configured and arranged to allow a bonding wave to displace air between the redistribution layers during bonding. This configuration and arrangement of the one or more arrays minimize discontinuities, such as pockets of air to provide an example, between the redistribution layers during the bonding.

Package Structures and Methods of Forming the Same

An embodiment is a method including bonding a first die to a first side of an interposer using first electrical connectors, bonding a second die to first side of the interposer using second electrical connectors, attaching a first dummy die to the first side of the interposer adjacent the second die, encapsulating the first die, the second die, and the first dummy die with an encapsulant, and singulating the interposer and the first dummy die to form a package structure.

Substrateless Integrated Circuit Packages and Methods of Forming Same

Integrated circuit packages and methods of forming the same are provided. One or more redistribution layers are formed on a carrier. First connectors are formed on a first side of the RDLs. Dies are bonded to the first side of the RDLs using the first connectors. An encapsulant is formed on the first side of the RDLs around the dies. The carrier is de-bonded from the overlaying structure and second connectors are formed on a second side of the RDLs. The resulting structure in diced to form individual packages. 1. A device comprising: a first dielectric layer;', 'a first conductive feature extending from a first side of the first dielectric layer to a second side of the first dielectric layer, the first conductive feature having a first width at the first side of the first dielectric layer and a second width at the second side of the first dielectric layer, the first width being greater than the second width;', 'a plurality of second dielectric layers on the first side of the first dielectric layer; and', 'a plurality of second conductive features in the second dielectric layers;, 'an interconnect comprisinga third dielectric layer on the second side of the first dielectric layer; andan under-bump metallurgy (UBM) extending through the third dielectric layer to couple with the first conductive feature.2. The device of claim 1 , further comprising:first connectors coupled to the second conductive features of the interconnect.3. The device of claim 2 , further comprising:a die attached to the first connectors; andan encapsulant on the second dielectric layers of the interconnect, the encapsulant surrounding the die and the first connectors.4. The device of claim 2 , further comprising:second connectors coupled to the UBM, the second connectors being larger than the first connectors.5. The device of claim 4 , further comprising:a package substrate connected to the second connectors.6. The device of claim 4 , wherein a pitch of the first connectors is smaller than a ...

Die-to-Die Gap Control for Semiconductor Structure and Method

An embodiment is a structure comprising a substrate, a first die, and a second die. The substrate has a first surface and a second surface opposite the first surface. The substrate has a through substrate via extending from the first surface towards the second surface. The first die is attached to the substrate, and the first die is coupled to the first surface of the substrate. The second die is attached to the substrate, and the second die is coupled to the first surface of the substrate. A first distance is between a first edge of the first die and a first edge of the second die, and the first distance is in a direction parallel to the first surface of the substrate. The first distance is equal to or less than 200 micrometers.

Semiconductor device and method of forming a semiconductor device

A semiconductor device and method is disclosed. The semiconductor device may include a semiconductor substrate including an active area, a metal layer structure over the active area, wherein the metal layer structure is configured to form an electrical contact, the metal layer structure including a solder area, a buffer area, and a barrier area between the solder area and the buffer area, wherein, in the barrier area, the metal layer structure is further away from the active area than in the solder area and in the buffer area, and wherein each of the solder area and the buffer area is in direct contact with the active area or with a wiring layer structure arranged between the active area and the metal layer structure.

SEMICONDUCTOR DEVICE AND PROCESS FOR FABRICATING THE SAME

A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode. A second insulating layer is formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, and bump electrodes are formed on both electrodes. 1. A semiconductor device comprising:a semiconductor substrate having a first main surface, at which an active element is provided, and a second main surface opposing the first main surface;an insulating layer that covers the first main surface of the semiconductor substrate and the active element;a wiring portion that contacts the first main surface via the insulating layer;a through-type electrode that penetrates through the semiconductor substrate from the first main surface to the second main surface; anda connecting hole that connects the wiring portion and the through-type electrode, the connecting hole having a diameter that is smaller than a diameter of the through-type electrode.2. The semiconductor device according to claim 1 , wherein the wiring portion is connected with the active element via another connecting hole.3. The semiconductor device according to claim 1 , further comprising a multilayer wiring part that covers the insulating layer and the wiring portion claim 1 , and in which wirings and insulating films are laminated claim 1 , ...

SEMICONDUCTOR DEVICE AND PROCESS FOR FABRICATING THE SAME

A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode. A second insulating layer is formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, and bump electrodes are formed on both electrodes. 14-. (canceled)5. A stacked semiconductor device comprising:a daughter board having an upper surface and a lower surface, the daughter board including a plurality of bump electrodes that are fixed on the lower surface; anda first semiconductor device electrically connected with the bump electrodes and fixed on the upper surface of the daughter board, wires in the daughter board or on the upper surface of the daughter board, and', 'a plurality of terminal electrodes that are electrically connected with respective ones of the wires and are exposed to the upper surface of the daughter board,, 'wherein the daughter board comprises'} a first semiconductor substrate having one surface and another surface, the first semiconductor substrate including a circuit element on the one surface,', 'a multilayer wiring part on the one surface of the first semiconductor substrate,', 'a first insulating layer that covers the multilayer wiring part,', 'a plurality of through-type electrodes that pierce through the first semiconductor substrate from a specified depth of ...

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

A semiconductor device includes a first substrate, a pad array, a conductive bump, a first via and a dielectric. The pad array, formed on a surface of the first substrate, includes a first type pad and a second type pad at a same level. The conductive bump connects one of the first type pad of the second type pad to a second substrate. The first via, connected to a conductive feature at a different level to the first type pad, is located within a projection area of the first type pad and directly contacts the first type pad. The second type pad is laterally connected with a conductive trace on the same level. The conductive trace is connected to a second via at a same level with the first via. The dielectric in the first substrate contacts the second type pad. The second type pad is floated on the dielectric. 1. A semiconductor device , comprising:a first substrate including a surface;a pad array on the surface of the first substrate, wherein the pad array comprises a first type pad and a second type pad at a same level;a conductive bump connecting one of the first type pad of the second type pad to a second substrate;a first via connected to a conductive feature at a different level to the first type pad, the first via being located within a projection area of the first type pad and directly contacting the first type pad, wherein the second type pad is laterally connected with a conductive trace on the same level, and the conductive trace is connected to a second via that is at a same level with the first via; anda dielectric in the first substrate, the dielectric contacting the second type pad, wherein the second type pad is floated on the dielectric.2. The semiconductor device of claim 1 , wherein the second via is connected to the conductive feature.3. The semiconductor device of claim 1 , wherein the second type pad is arranged symmetrically to a geometric center of the pad array.4. The semiconductor device of claim 1 , wherein the first substrate is a printed ...

SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCTION OF SEMICONDUCTOR DEVICE

A semiconductor device with a connection pad in a substrate, the connection pad having an exposed surface made of a metallic material that diffuses less readily into a dielectric layer than does a metal of a wiring layer connected thereto. 110-. (canceled)12. The semiconductor device of claim 11 , wherein the first portion of the diffusion preventing layer forming a portion of the first surface contacts the second insulating film.13. The semiconductor device of claim 12 , wherein a second portion of the diffusion preventing layer forming a second surface opposite to the first surface contacts the first insulating film.14. The semiconductor device of claim 13 , wherein the first pad has a first surface extended in a direction perpendicular to the first surface claim 13 , and wherein the first surface of the first pad contacts the diffusion preventing layer and the first insulating film.15. The semiconductor device of claim 11 , wherein the diffusion preventing layer includes at least one of Si claim 11 , N claim 11 , O claim 11 , or C.16. The semiconductor device of claim 15 , wherein the diffusion preventing layer includes SiN or SiOC.17. The semiconductor device of claim 11 , wherein the second pad is partially covered by a barrier metal.18. The semiconductor device of claim 17 , wherein the barrier metal covers at least a portion of at least two surfaces of the second pad that extends in a direction perpendicular to the first surface.19. The semiconductor device of claim 17 , wherein the barrier metal covers at least a portion of at least a part of a surface extended in a direction parallel to the first surface.20. The semiconductor device of claim 17 , wherein the barrier metal includes at least one of Ti claim 17 , N claim 17 , or Ta.21. The semiconductor device of claim 20 , wherein the barrier metal includes TiN or TaN.22. The semiconductor device of claim 17 , wherein a portion of the barrier metal contacts the first pad.23. The semiconductor device of claim ...

Semiconductor device with tilted insulating layers and method for fabricating the same

The present disclosure relates to a semiconductor device with tilted insulating layers and a method for fabricating the semiconductor device with the tilted insulating layers. The semiconductor device includes a substrate, two conductive pillars positioned above the substrate and extended along a vertical axis, a first set of tilted insulating layers parallel to each other and positioned between the two conductive pillars, and a second set of tilted insulating layers parallel to each other and positioned between the two conductive pillars. The first set of tilted insulating layers are extended along a first direction slanted with respect to the vertical axis, the second set of tilted insulating layers are extended along a second direction slanted with respect to the vertical axis, and the first direction and the second direction are crossed.

Die stack structure and method of fabricating the same

Provided is a die stack structure including a first die, a second die, a first bonding structure, and a second bonding structure. The first bonding structure is disposed on a back side of the first die. The second bonding structure is disposed on a front side of the second die. The first die and the second die are bonded together via the first bonding structure and the second bonding structure and a bondable topography variation of a surface of the first bonding structure bonding with the second bonding structure is less than less than 1 μm per 1 mm range. A method of manufacturing the die stack structure is also provided.

Die stack structure and method of fabricating the same and package

Provided is a die stack structure including a first die and a second die. The first die and the second die are bonded together through a hybrid bonding structure. At least one of a first test pad of the first die or a second test pad of the second die has a protrusion of the at least one of the first test pad or the second test pad, and a bonding insulating layer of the hybrid bonding structure covers and contacts with the protrusion, so that the first test pad and the second test pad are electrically isolated from each other.

BUMP BONDED CRYOGENIC CHIP CARRIER

A device has a first stack of thin films, the first stack of thin films having a first opposing surface and a first connection surface, wherein the first connection surface contacts a first superconducting region; a second stack of thin films, the second stack of thin films having a second opposing surface and a second connection surface, wherein the second connection surface contacts a second superconducting region; and a superconducting bump bond electrically connecting the first and second opposing surfaces, the superconducting bump bond maintaining a low ohmic electrical contact between the first and second opposing surfaces at temperatures below 100 degrees Kelvin, wherein at least one of the first or second superconducting regions comprise material with a melting point of at least 700 degrees Celsius. 1. A device comprising:a first stack of thin films, the first stack of thin films having a first opposing surface and a first connection surface, wherein the first connection surface contacts a first superconducting region;a second stack of thin films, the second stack of thin films having a second opposing surface and a second connection surface, wherein the second connection surface contacts a second superconducting region; anda superconducting bump bond electrically connecting the first and second opposing surfaces, the superconducting bump bond maintaining a low ohmic electrical contact between the first and second opposing surfaces at temperatures below 100 degrees Kelvin, wherein at least one of the first or second superconducting regions comprise material with a melting point of at least 700 degrees Celsius.2. The device of claim 1 , wherein at least one of the first or second stack of thin films are electrically conductive.3. The device of claim 1 , wherein the first stack of thin films has a first opposing film and a first connection film claim 1 , the first opposing film and the first connection film positioned on opposite ends of the stack of thin ...

System and Method for an Improved Fine Pitch Joint

Presented herein are an interconnect and method for forming the same, the method comprising forming an interconnect on a mounting surface of a mounting pad disposed on a first surface of a first substrate, the interconnect comprising a conductive material, optionally solder or metal, the interconnect avoiding the sides of the mounting pad. A molding compound is applied to the first surface of the first substrate and molded around the interconnect to covering at least a lower portion of the interconnect and a second substrate may be mounted on the interconnect. The interconnect may comprise an interconnect material disposed between a first and second substrate and a molding compound disposed on a surface of the first substrate, and exposing a portion of the interconnect. A sidewall of the interconnect material contacts the mounting pad at an angle less than about 30 degrees from a plane perpendicular to the first substrate.

MICRO-CONNECTION STRUCTURE AND MANUFACTURING METHOD THEREOF

A micro-connection structure is provided. The micro-connection structure includes an under bump metallurgy (UBM) pad, a bump and an insulating ring. The UBM pad is electrically connected to at least one metallic contact of a substrate. The bump is disposed on the UBM pad and electrically connected with the UBM pad. The insulating ring surrounds the bump and the UBM pad. The bump is separate from the insulating ring with a distance and the bump is isolated by a gap between the insulating ring and the bump. 1. A micro-connection structure , comprising:an under bump metallurgy (UBM) pad, electrically connected to at least one metallic contact of a substrate;a bump, disposed on the UBM pad and electrically connected with the UBM pad;an insulating ring surrounding the bump and the UBM pad; anda barrier layer, disposed on and covering the insulating ring,wherein the bump is separate and isolated from the barrier layer and the insulating ring by an open trench between the barrier layer on a sidewall of the insulating ring and the bump.2. The structure of claim 1 , wherein the barrier layer is in contact with the UBM pad without being in contact with the bump.3. (Withdrawn and currently amended) The structure of claim 1 , wherein the UBM pad is located directly on the barrier layer and the barrier layer is not in contact with the bump located on the UBM pad.4. The structure of claim 3 , wherein the barrier layer comprises a tantalum layer conformally covering the insulating ring and an aluminum layer located on the tantalum layer.5. The structure of claim 1 , further comprising a metallic pad disposed directly under the UBM pad and sandwiched between the UBM pad and the at least one metallic contact claim 1 , wherein the UBM pad is electrically connected to the at least one metallic contact through the metallic pad.6. The structure of claim 5 , wherein the UBM pad includes a sidewall portion surrounding the bump and covering a sidewall of the bump claim 5 , and a height of ...

Copper pillar bump having annular protrusion

A copper pillar bump for an electrode pad of a semiconductor chip includes a first copper layer, a first metal layer formed directly on the first copper layer, a second copper layer formed directly on the first metal layer, and a second metal layer formed directly on the second copper layer, wherein the first metal layer and the second metal layer are made of a metal having a different etching rate than copper, wherein an outer perimeter ring of the first metal layer protrudes beyond a lateral surface of the first copper layer, and wherein an outer perimeter ring of the second metal layer protrudes beyond a lateral surface of the second copper layer.

Interconnect Structure and Method of Forming Same

A device includes a first side interconnect structure over a first side of a substrate, wherein active circuits are in the substrate and adjacent to the first side of the substrate, a dielectric layer over a second side of the substrate, a pad embedded in the dielectric layer, the pad comprising an upper portion and a bottom portion formed of two different materials and a passivation layer over the dielectric layer. 1. A device comprising:a first side interconnect structure over a first side of a substrate, wherein active circuits are in the substrate and adjacent to the first side of the substrate;a dielectric layer over a second side of the substrate;a pad embedded in the dielectric layer, the pad comprising an upper portion and a bottom portion formed of two different materials; anda passivation layer over the dielectric layer.2. The device of claim 1 , further comprising:a via extending through the substrate and partially through the dielectric layer.3. The device of claim 1 , further comprising:a first metal line embedded in the dielectric layer, wherein a bottom of the first metal line is substantially level with a bottom of the pad.4. The device of claim 3 , wherein:a width of the pad is greater than a width of the first metal line.5. The device of claim 3 , further comprising:an isolation region in the substrate; anda second metal line embedded in the dielectric layer, wherein a distance between the first metal line and the isolation region is substantially equal to a distance between the isolation region and the second metal line.6. The device of claim 1 , wherein:the bottom portion of the pad is formed of a first conductive material; andthe upper portion of the pad is formed of a second conductive material, and wherein the upper portion of the pad is of a trapezoidal shape surrounded by the bottom portion of the pad.7. The device of claim 6 , wherein:the first conductive material is copper; andthe second conductive material is nickel.8. The device of claim ...

Intergrated Circuit Packages and Methods of Forming Same

An integrated circuit package and a method of forming the same are provided. A method includes forming a first redistribution layer over a carrier, the first redistribution layer including a contact pad and a bond pad. A conductive pillar is formed over the contact pad. A backside surface of an integrated circuit die is attached to the bond pad using a solder joint. An encapsulant is formed along a sidewall of the conductive pillar and a sidewall of the integrated circuit die, a front-side surface of the integrated circuit die being substantially level with a topmost surface of the encapsulant and a topmost surface of the conductive pillar. A second redistribution layer is formed over the front-side surface of the integrated circuit die, the topmost surface of the encapsulant and the topmost surface of the conductive pillar. 1. A method comprising:forming a first redistribution layer over a carrier, the first redistribution layer comprising a contact pad and a bond pad;forming a conductive pillar over the contact pad;attaching a backside surface of an integrated circuit die to the bond pad using a solder joint;forming an encapsulant along a sidewall of the conductive pillar and a sidewall of the integrated circuit die, a front-side surface of the integrated circuit die being substantially level with a topmost surface of the encapsulant and a topmost surface of the conductive pillar; andforming a second redistribution layer over the front-side surface of the integrated circuit die, the topmost surface of the encapsulant and the topmost surface of the conductive pillar.2. The method of claim 1 , wherein attaching the backside surface of the integrated circuit die to the bond pad using the solder joint comprises:applying a solder paste on the backside surface of the integrated circuit die;placing the integrated circuit die over the bond pad, the solder paste being in physical contact with the bond pad; andreflowing the solder paste to form the solder joint.3. The ...

Power Semiconductor Chip, Method for Producing a Power Semiconductor Chip, and Power Semiconductor Device

A power semiconductor chip having: a semiconductor component body; a multilayer metallization arranged on the semiconductor component body; and a nickel layer arranged over the semiconductor component body. The invention further relates to a method for producing a power semiconductor chip and to a power semiconductor device. The invention provides a power semiconductor chip which has a metallization to which a copper wire, provided without a thick metallic coating, can be reliably bonded without damage to the power semiconductor chip during bonding.

MULTIPLE PLATED VIA ARRAYS OF DIFFERENT WIRE HEIGHTS ON SAME SUBSTRATE

Apparatus(es) and method(s) relate generally to via arrays on a substrate. In one such apparatus, the substrate has a conductive layer. First plated conductors are in a first region extending from a surface of the conductive layer. Second plated conductors are in a second region extending from the surface of the conductive layer. The first plated conductors and the second plated conductors are external to the first substrate. The first region is disposed at least partially within the second region. The first plated conductors are of a first height. The second plated conductors are of a second height greater than the first height. A second substrate is coupled to first ends of the first plated conductors. The second substrate has at least one electronic component coupled thereto. A die is coupled to second ends of the second plated conductors. The die is located over the at least one electronic component. 1. An apparatus , comprising:a first substrate having a conductive layer;first plated conductors in a first region extending from a surface of the conductive layer;second plated conductors in a second region extending from the surface of the conductive layer;wherein the first plated conductors and the second plated conductors are external to the first substrate;wherein the first region is disposed at least partially within the second region;wherein the first plated conductors are of a first height;wherein the second plated conductors are of a second height greater than the first height;a second substrate coupled to first ends of the first plated conductors;the second substrate having at least one electronic component coupled thereto;a die coupled to second ends of the second plated conductors; andthe die located over the at least one electronic component.2. The apparatus according to claim 1 , wherein the at least one electronic component includes a discrete passive component.3. The apparatus according to claim 2 , wherein the second substrate includes a ...

Semiconductor device and method for manufacturing the same

A semiconductor device including a substrate, an insulating layer on the substrate and including a trench, at least one via structure penetrating the substrate and protruding above a bottom surface of the trench, and a conductive structure surrounding the at least one via structure in the trench may be provided.

Element chip manufacturing method

Provided is a method of manufacturing a semiconductor chip, the method comprising: preparing a plurality of semiconductor chips, each of which has a surface to which a BG tape is stuck, and a rear surface to which a DAF is stuck, and which are held spaced from each other by the BG tape and the DAF, exposing the DAF between semiconductor chips that are adjacent to each other when viewed from the surface side, by stripping the BG tape from the surface of each of the plurality of semiconductor chips, etching the DAF that is exposed between the semiconductor chips that are adjacent to each other, by irradiating the plurality of semiconductor chips held on the DAF, with plasma.

Structure and Method of Forming a Joint Assembly

A method of manufacturing a semiconductor device structure includes forming a bond or joint between a first device and a second device. The first device comprises an integrated passive device (IPD) and a first contact pad disposed over the IPD. The second device comprises a second contact pad. The first contact pad has a first surface with first lateral extents. The second contact pad has a second surface with second lateral extents. The width of the second lateral extents is less than the width of the first lateral extents. The joint structure includes the first contact pad, the second contact pad, and a solder layer interposed therebetween. The solder layer has tapered sidewalls extending in a direction away from the first surface of the first contact pad to the second surface of the second contact pad. At least one of the first surface or the second surface is substantially planar. 1. A device comprising:a first semiconductor device comprising a first contact pad having a first surface contacting a metal feature, the first contact pad having a second surface opposite the first surface, the second surface being planar, wherein a ratio of a first width of the first surface to a second width of the second surface is 2:5;a solder layer bonded to the first contact pad; anda second semiconductor device comprising a second contact pad, the second contact pad having a third surface bonded to the solder layer, the second contact pad having a fourth surface opposite the third surface, the third surface being planar, wherein a ratio of a third width of the third surface to a fourth width of the fourth surface is 5:2, wherein the solder layer has tapered sidewalls continuously diminishing from the second width at a fifth surface adjoining the first contact pad to the third width at a sixth surface adjoining the second contact pad.2. The device of claim 1 , wherein the first semiconductor device further comprises an integrated passive device.3. The device of claim 2 , wherein ...

Structures And Methods For Low Temperature Bonding Using Nanoparticles

A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements. 1a first component including a substrate having a first surface and a plurality of first conductive elements exposed at the first surface, each first conductive element having a top surface generally facing in a first direction, the top surface of each first conductive element exposed in a recess extending below the first surface; anda second component including a substrate having a major surface and a plurality of second conductive elements exposed at the major surface, each second conductive element having a top surface generally facing in a second direction opposite the first direction, the top surface of each second conductive element exposed in a recess extending below the major surface,the first conductive elements being joined with the second conductive elements, such that the top surfaces of the first conductive elements at least partially confront the top surfaces of the second conductive elements,each first conductive element being electrically interconnected with a corresponding one of the second conductive elements by a bond ...

3D Integrated Circuit and Methods of Forming the Same

An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer. 1. A semiconductor structure comprising:a first adsorption layer, a first bonding layer, a second bonding layer, and a second adsorption layer stacked on a first substrate; anda conductive pattern structure penetrating through the first adsorption layer, the first bonding layer, the second bonding layer and the second adsorption layer,wherein the first and second bonding layers are in contact with each other, andwherein each of the first and second adsorption layers includes a low-k dielectric material.2. The semiconductor structure according to claim 1 , further comprising:a first insulating interlayer between the first substrate and the first adsorption layer; anda second insulating interlayer on the second adsorption layer.3. The semiconductor structure according to claim 2 , wherein the conductive pattern structure at least partially penetrates into each of the first and second insulating interlayers.4. The semiconductor structure according to claim 1 , wherein the first adsorption layer is a first porous dielectric layer.5. The semiconductor structure according to claim 4 , wherein the first porous dielectric layer has a porosity between about 5 percent and about 40 percent.6. The semiconductor structure according to claim 5 , wherein the second adsorption ...

SEMICONDUCTOR DEVICE AND PROCESS FOR FABRICATING THE SAME

A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode. A second insulating layer is formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, and bump electrodes are formed on both electrodes. 1. A stacked semiconductor device comprising:a daughter board having an upper surface and a lower surface, the daughter board including a plurality of bump electrodes that are fixed on the lower surface; anda first semiconductor device electrically connected with the bump electrodes and fixed on the upper surface of the daughter board, wires in the daughter board or on the upper surface of the daughter board, and', 'a plurality of terminal electrodes that are electrically connected with respective ones of the wires and are exposed to the upper surface of the daughter board,, 'wherein the daughter board comprises'} a first semiconductor substrate having one surface and another surface, the first semiconductor substrate including a circuit element on the one surface,', 'a multilayer wiring part on the one surface of the first semiconductor substrate,', 'a first insulating layer that covers the multilayer wiring part,', 'a plurality of through-type electrodes that pierce through the first semiconductor substrate from a specified depth of the multilayer ...

3DI Solder Cup

A substrate or semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a solder cup. The semiconductor device assembly includes a substrate disposed over another substrate. At least one solder cup extends from one substrate towards an under bump metal (UBM) on the other substrate. The barrier on the exterior of the solder cup may be a standoff to control a bond line between the substrates. The barrier may reduce solder bridging during the formation of a semiconductor device assembly. The barrier may help to align the solder cup with a UBM when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of substrates and/or semiconductor devices.

Semiconductor device

A semiconductor device includes an insulating structure; a plurality of horizontal layers vertically stacked and spaced apart from each other in the insulating structure; a conductive material pattern contacting the insulating structure; and a vertical structure penetrating through the plurality of horizontal layers and extending into the conductive material pattern in the insulating structure. Each of the plurality of horizontal layers comprises a conductive material, the vertical structure comprises a vertical portion and a protruding portion, the vertical portion of the vertical structure penetrates through the plurality of horizontal layers, the protruding portion of the vertical structure extends from the vertical portion into the conductive material pattern, a width of the vertical portion is greater than a width of the protruding portion, and a side surface of the protruding portion is in contact with the conductive material pattern.

Semiconductor element

A transistor includes a semiconductor region provided on a substrate and three different terminal electrodes. At least one terminal electrode has an isolated electrode structure composed of a plurality of conductor patterns. A bump, which electrically connects the plurality of conductor patterns to each other, is arranged on the terminal electrode having the isolated electrode structure. A stress-relaxing layer, which is composed of a metal material containing a high-melting-point metal, is arranged between the semiconductor region of the transistor and the bump. No current path for connecting the plurality of conductor patterns to each other is arranged between the conductor patterns and the bump.

FLIP CHIP PACKAGE STRUCTURE AND FABRICATION PROCESS THEREOF

Disclosed herein are various chip packaging structures and methods of fabrication. In one embodiment, a flip chip package structure can include: (i) a pad on a chip; (ii) an isolation layer on the chip and the pad, where the isolation layer includes a through hole that exposes a portion of an upper surface of the pad; (iii) a metal layer on the pad, where the metal layer fully covers the exposed upper surface portion of the pad; and (iv) a bump on the metal layer, where side edges of the bump do not make contact with the isolation layer. 1. (canceled)2. (canceled)3. (canceled)4. (canceled)5. (canceled)6. (canceled)7. (canceled)8. A method of fabricating a flip chip package structure , the method comprising:a) forming a pad on a die;b) depositing an isolation layer on said die and said pad;c) forming a through hole in said isolation layer to selectively expose a portion of said pad;d) depositing a metal layer on said pad to fully cover said exposed portion of said pad; ande) forming a bump on said metal layer, wherein said bump is separated from said isolation layer by gaps.9. The method of claim 8 , wherein said isolation layer comprises a passivation layer.10. The method of claim 8 , wherein said metal layer comprises a first type metal layer for protecting said pad from corrosion.11. The method of claim 8 , wherein said depositing said metal layer comprises:a) sputtering a titanium metal layer on said exposed portion of said pad; andb) sputtering a copper metal layer on said titanium metal layer.12. The method of claim 10 , wherein said first type metal layer comprises a tungsten metal layer.13. The method of claim 8 , wherein said depositing said metal layer comprises:a) sputtering a titanium metal layer on said exposed portion of said pad;b) sputtering a tungsten metal layer on said titanium metal layer; andc) sputtering a copper metal layer on said tungsten metal layer.14. The method of claim 8 , wherein said bump comprises at least one of: tin claim 8 , copper ...

SEMICONDUCTOR DEVICE

A semiconductor chip includes a substrate, an electrode pad formed on the substrate, an insulating layer covering the substrate and the electrode pad, and having an opening exposing a portion of a surface of the electrode pad, a first conductive layer formed on the exposed portion of the surface of the electrode pad and extending to a surface of the insulating layer, and a second conductive layer formed on the first conductive layer, covering the first conductive layer in a plan view, and having an outer edge portion which is located further out than an outer edge of the first conductive layer in a plan view. The outer edge portion of the second conductive layer has at least one curved portion. At least one portion of the curved portion is located between the outer edge of the first conductive layer and an outer edge of the second conductive layer in a plan view. 1. A semiconductor chip , comprising:a substrate;an electrode pad formed on the substrate;an insulating layer covering the substrate and the electrode pad, and having an opening exposing a portion of a surface of the electrode pad therethrough;a first conductive layer formed on the exposed portion of the surface of the electrode pad and extending to a surface of the insulating layer; anda second conductive layer formed on the first conductive layer, covering the first conductive layer in a plan view, and having an outer edge portion which is located further out than an outer edge of the first conductive layer in a plan view,wherein the outer edge portion of the second conductive layer has at least one curved portion, andat least one portion of the curved portion is located between the outer edge of the first conductive layer and an outer edge of the second conductive layer in a plan view.2. The semiconductor chip according to claim 1 , further comprising a bump electrode formed on the second conductive layer and covering the curved portion.3. The semiconductor chip according to claim 2 , wherein at least ...

Semiconductor device and method of manufacturing the same

A semiconductor device includes a first semiconductor substrate having a first wiring layer which includes a first conductive pad, a second semiconductor substrate disposed on the first semiconductor substrate and including a second wiring layer which includes a second conductive pad, a first oxide layer disposed on the second semiconductor substrate and containing a second end of an intermediate connection which extends vertically through the second semiconductor substrate and has a first end electrically connected to the second conductive pad, and a third semiconductor substrate disposed on the first oxide layer and including a third wiring layer which includes a third conductive pad. The second end of the intermediate connection layer is electrically connected to the third conductive pad via a metal bond.

Semiconductor package and method of manufacturing the same

A semiconductor package includes a substrate, a plurality of semiconductor devices stacked on the substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the substrate and the plurality of semiconductor devices, and molding resin surrounding the plurality of semiconductor devices. At least one of the underfill fillets is exposed from side surfaces of the molding resin.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A method of manufacturing a semiconductor device includes providing a carrier, disposing a first pad on the carrier, forming a post on the first pad, and disposing a joint adjacent to the post and the first pad to form a first entire contact interface between the first pad and the joint and a second entire contact interface between the first pad and the post. The first entire contact interface and the second entire contact interface are flat surfaces. 1. A method of manufacturing a semiconductor device , comprising:providing a first carrier;disposing a first pad on the first carrier;forming a post on the first pad; anddisposing a joint adjacent to the post and the first pad to form a first entire contact interface between the first pad and the joint and a second entire contact interface between the first pad and the post, wherein the first entire contact interface and the second entire contact\ interface are flat surfaces.2. The method of manufacturing the semiconductor device of claim 1 , wherein the disposing of the joint is performed by pasting a solder over the post and the first pad through a stencil.3. The method of manufacturing the semiconductor device of claim 1 , further comprising providing a second carrier and disposing a second pad on the second carrier.4. The method of manufacturing the semiconductor device of claim 3 , wherein a height of the post is greater than or equal to ⅓ of a distance between the first pad and the second pad.5. The method of manufacturing the semiconductor device of claim 3 , further comprising disposing the joint between the first pad and the second pad to bond the first pad with the second pad and to form a third entire contact interface between the joint and the second pad claim 3 , wherein the third entire contact interface is a flat surface.6. The method of manufacturing the semiconductor device of claim 5 , further comprising disposing a pre-soldering bump on the second pad prior to disposing the joint between the first ...